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10924 Need mitigation of L1TF (CVE-2018-3646)
Reviewed by: Robert Mustacchi <rm@joyent.com>
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Reviewed by: Peter Tribble <peter.tribble@gmail.com>
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--- old/usr/src/uts/i86pc/sys/machcpuvar.h
+++ new/usr/src/uts/i86pc/sys/machcpuvar.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 23 * Use is subject to license terms.
24 24 */
25 25 /*
26 26 * Copyright 2018 Joyent, Inc.
27 27 */
28 28
29 29 #ifndef _SYS_MACHCPUVAR_H
30 30 #define _SYS_MACHCPUVAR_H
31 31
32 32 #ifdef __cplusplus
33 33 extern "C" {
34 34 #endif
35 35
36 36 #include <sys/inttypes.h>
37 37 #include <sys/x_call.h>
38 38 #include <sys/tss.h>
39 39 #include <sys/segments.h>
40 40 #include <sys/rm_platter.h>
41 41 #include <sys/avintr.h>
42 42 #include <sys/pte.h>
43 43 #include <sys/stddef.h>
44 44 #include <sys/debug.h>
45 45 #include <sys/cpuvar.h>
46 46
47 47 #ifndef _ASM
48 48 /*
49 49 * On a virtualized platform a virtual cpu may not be actually
50 50 * on a physical cpu, especially in situations where a configuration has
51 51 * more vcpus than pcpus. This function tells us (if it's able) if the
52 52 * specified vcpu is currently running on a pcpu. Note if it is not
53 53 * known or not able to determine, it will return the unknown state.
54 54 */
55 55 #define VCPU_STATE_UNKNOWN 0
56 56 #define VCPU_ON_PCPU 1
57 57 #define VCPU_NOT_ON_PCPU 2
58 58
59 59 extern int vcpu_on_pcpu(processorid_t);
60 60
61 61 /*
62 62 * Machine specific fields of the cpu struct
63 63 * defined in common/sys/cpuvar.h.
64 64 *
65 65 * Note: This is kinda kludgy but seems to be the best
66 66 * of our alternatives.
67 67 */
68 68
69 69 struct cpuid_info;
70 70 struct cpu_ucode_info;
71 71 struct cmi_hdl;
72 72
73 73 /*
74 74 * A note about the hypervisor affinity bits: a one bit in the affinity mask
75 75 * means the corresponding event channel is allowed to be serviced
76 76 * by this cpu.
77 77 */
78 78 struct xen_evt_data {
79 79 ulong_t pending_sel[PIL_MAX + 1]; /* event array selectors */
80 80 ulong_t pending_evts[PIL_MAX + 1][sizeof (ulong_t) * 8];
81 81 ulong_t evt_affinity[sizeof (ulong_t) * 8]; /* service on cpu */
82 82 };
83 83
84 84 struct kpti_frame {
85 85 uint64_t kf_lower_redzone;
86 86
87 87 /* Stashed value of %cr3 when we entered the trampoline. */
88 88 greg_t kf_tr_cr3;
89 89
90 90 /*
91 91 * We use %r13-r14 as scratch registers in the trampoline code,
92 92 * so stash those here "below" the rest of the stack so they can be
93 93 * pushed/popped if needed.
94 94 */
95 95 greg_t kf_r14;
96 96 greg_t kf_r13;
97 97
98 98 /*
99 99 * Part of this struct is used as the HW stack frame when taking an
100 100 * interrupt on the user page table. The CPU is going to push a bunch
101 101 * of regs onto the stack pointer set in the TSS/IDT (which we set to
102 102 * &kf_rsp here).
103 103 *
104 104 * This is only a temporary holding area for them (we'll move them over
105 105 * to the real interrupt stack once we've set %cr3).
106 106 *
107 107 * Note that these must be cleared during a process switch on this cpu.
108 108 */
109 109 greg_t kf_err; /* Bottom of initial hw stack frame */
110 110 greg_t kf_rip;
111 111 greg_t kf_cs;
112 112 greg_t kf_rflags;
113 113 greg_t kf_rsp;
114 114 greg_t kf_ss;
115 115
116 116 greg_t kf_tr_rsp; /* Top of HW stack frame */
117 117 /* We also write this with the %rsp value on tramp entry */
118 118
119 119 /* Written to 0x1 when this kpti_frame is in use. */
120 120 uint64_t kf_tr_flag;
121 121
122 122 uint64_t kf_middle_redzone;
123 123
124 124 /*
125 125 * The things we need to write to %cr3 to change between page tables.
126 126 * These live "above" the HW stack.
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127 127 */
128 128 greg_t kf_kernel_cr3;
129 129 greg_t kf_user_cr3;
130 130 greg_t kf_tr_ret_rsp;
131 131
132 132 uint64_t kf_unused; /* For 16-byte align */
133 133
134 134 uint64_t kf_upper_redzone;
135 135 };
136 136
137 +typedef struct cpu_ht {
138 + lock_t ch_lock;
139 + char ch_pad[56];
140 + struct cpu *ch_sib;
141 + volatile uint64_t ch_intr_depth;
142 + volatile uint64_t ch_state;
143 + volatile uint64_t ch_sibstate;
144 +} cpu_ht_t;
145 +
137 146 /*
138 147 * This first value, MACHCPU_SIZE is the size of all the members in the cpu_t
139 148 * AND struct machcpu, before we get to the mcpu_pad and the kpti area.
140 149 * The KPTI is used to contain per-CPU data that is visible in both sets of
141 150 * page-tables, and hence must be page-aligned and page-sized. See
142 151 * hat_pcp_setup().
143 152 *
144 - * There is a CTASSERT in os/intr.c that checks these numbers.
153 + * There are CTASSERTs in os/intr.c that verify this all works out.
145 154 */
146 -#define MACHCPU_SIZE (572 + 1584)
155 +#define MACHCPU_SIZE (1568 + 688)
147 156 #define MACHCPU_PAD (MMU_PAGESIZE - MACHCPU_SIZE)
148 157 #define MACHCPU_PAD2 (MMU_PAGESIZE - 16 - 3 * sizeof (struct kpti_frame))
149 158
150 159 struct machcpu {
151 160 /*
152 161 * x_call fields - used for interprocessor cross calls
153 162 */
154 163 struct xc_msg *xc_msgbox;
155 164 struct xc_msg *xc_free;
156 165 xc_data_t xc_data;
157 166 uint32_t xc_wait_cnt;
158 167 volatile uint32_t xc_work_cnt;
159 168
160 169 int mcpu_nodeid; /* node-id */
161 170 int mcpu_pri; /* CPU priority */
162 171
163 172 struct hat *mcpu_current_hat; /* cpu's current hat */
164 173
165 174 struct hat_cpu_info *mcpu_hat_info;
166 175
167 176 volatile ulong_t mcpu_tlb_info;
168 177
169 178 /* i86 hardware table addresses that cannot be shared */
170 179
171 180 user_desc_t *mcpu_gdt; /* GDT */
172 181 gate_desc_t *mcpu_idt; /* current IDT */
173 182
174 183 tss_t *mcpu_tss; /* TSS */
175 184 void *mcpu_ldt;
176 185 size_t mcpu_ldt_len;
177 186
178 187 kmutex_t mcpu_ppaddr_mutex;
179 188 caddr_t mcpu_caddr1; /* per cpu CADDR1 */
180 189 caddr_t mcpu_caddr2; /* per cpu CADDR2 */
181 190 uint64_t mcpu_caddr1pte;
182 191 uint64_t mcpu_caddr2pte;
183 192
184 193 struct softint mcpu_softinfo;
185 194 uint64_t pil_high_start[HIGH_LEVELS];
186 195 uint64_t intrstat[PIL_MAX + 1][2];
187 196
188 197 struct cpuid_info *mcpu_cpi;
189 198
190 199 #if defined(__amd64)
191 200 greg_t mcpu_rtmp_rsp; /* syscall: temporary %rsp stash */
192 201 greg_t mcpu_rtmp_r15; /* syscall: temporary %r15 stash */
193 202 #endif
194 203
195 204 struct vcpu_info *mcpu_vcpu_info;
196 205 uint64_t mcpu_gdtpa; /* hypervisor: GDT physical address */
197 206
198 207 uint16_t mcpu_intr_pending; /* hypervisor: pending intrpt levels */
199 208 uint16_t mcpu_ec_mbox; /* hypervisor: evtchn_dev mailbox */
200 209 struct xen_evt_data *mcpu_evt_pend; /* hypervisor: pending events */
201 210
202 211 volatile uint32_t *mcpu_mwait; /* MONITOR/MWAIT buffer */
203 212 void (*mcpu_idle_cpu)(void); /* idle function */
204 213 uint16_t mcpu_idle_type; /* CPU next idle type */
205 214 uint16_t max_cstates; /* supported max cstates */
206 215
207 216 struct cpu_ucode_info *mcpu_ucode_info;
208 217
209 218 void *mcpu_pm_mach_state;
210 219 struct cmi_hdl *mcpu_cmi_hdl;
211 220 void *mcpu_mach_ctx_ptr;
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212 221
213 222 /*
214 223 * A stamp that is unique per processor and changes
215 224 * whenever an interrupt happens. Userful for detecting
216 225 * if a section of code gets interrupted.
217 226 * The high order 16 bits will hold the cpu->cpu_id.
218 227 * The low order bits will be incremented on every interrupt.
219 228 */
220 229 volatile uint32_t mcpu_istamp;
221 230
231 + cpu_ht_t mcpu_ht;
232 +
222 233 char mcpu_pad[MACHCPU_PAD];
223 234
224 235 /* This is the start of the page */
225 236 char mcpu_pad2[MACHCPU_PAD2];
226 237 struct kpti_frame mcpu_kpti;
227 238 struct kpti_frame mcpu_kpti_flt;
228 239 struct kpti_frame mcpu_kpti_dbg;
229 240 char mcpu_pad3[16];
230 241 };
231 242
232 243 #define NINTR_THREADS (LOCK_LEVEL-1) /* number of interrupt threads */
233 244 #define MWAIT_HALTED (1) /* mcpu_mwait set when halting */
234 245 #define MWAIT_RUNNING (0) /* mcpu_mwait set to wakeup */
235 246 #define MWAIT_WAKEUP_IPI (2) /* need IPI to wakeup */
236 247 #define MWAIT_WAKEUP(cpu) (*((cpu)->cpu_m.mcpu_mwait) = MWAIT_RUNNING)
237 248
238 249 #endif /* _ASM */
239 250
240 251 /* Please DON'T add any more of this namespace-poisoning sewage here */
241 252
242 253 #define cpu_nodeid cpu_m.mcpu_nodeid
243 254 #define cpu_pri cpu_m.mcpu_pri
244 255 #define cpu_current_hat cpu_m.mcpu_current_hat
245 256 #define cpu_hat_info cpu_m.mcpu_hat_info
246 257 #define cpu_ppaddr_mutex cpu_m.mcpu_ppaddr_mutex
247 258 #define cpu_gdt cpu_m.mcpu_gdt
248 259 #define cpu_idt cpu_m.mcpu_idt
249 260 #define cpu_tss cpu_m.mcpu_tss
250 261 #define cpu_caddr1 cpu_m.mcpu_caddr1
251 262 #define cpu_caddr2 cpu_m.mcpu_caddr2
252 263 #define cpu_softinfo cpu_m.mcpu_softinfo
253 264 #define cpu_caddr1pte cpu_m.mcpu_caddr1pte
254 265 #define cpu_caddr2pte cpu_m.mcpu_caddr2pte
255 266
256 267 #ifdef __cplusplus
257 268 }
258 269 #endif
259 270
260 271 #endif /* _SYS_MACHCPUVAR_H */
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