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10924 Need mitigation of L1TF (CVE-2018-3646)
Reviewed by: Robert Mustacchi <rm@joyent.com>
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Reviewed by: Peter Tribble <peter.tribble@gmail.com>
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--- old/usr/src/uts/i86pc/io/pcplusmp/apic.c
+++ new/usr/src/uts/i86pc/io/pcplusmp/apic.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 */
25 25 /*
26 26 * Copyright (c) 2010, Intel Corporation.
27 27 * All rights reserved.
28 28 * Copyright 2018 Joyent, Inc.
29 29 */
30 30
31 31 /*
32 32 * To understand how the pcplusmp module interacts with the interrupt subsystem
33 33 * read the theory statement in uts/i86pc/os/intr.c.
34 34 */
35 35
36 36 /*
37 37 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
38 38 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
39 39 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
40 40 * PSMI 1.5 extensions are supported in Solaris Nevada.
41 41 * PSMI 1.6 extensions are supported in Solaris Nevada.
42 42 * PSMI 1.7 extensions are supported in Solaris Nevada.
43 43 */
44 44 #define PSMI_1_7
45 45
46 46 #include <sys/processor.h>
47 47 #include <sys/time.h>
48 48 #include <sys/psm.h>
49 49 #include <sys/smp_impldefs.h>
50 50 #include <sys/cram.h>
51 51 #include <sys/acpi/acpi.h>
52 52 #include <sys/acpica.h>
53 53 #include <sys/psm_common.h>
54 54 #include <sys/apic.h>
55 55 #include <sys/pit.h>
56 56 #include <sys/ddi.h>
57 57 #include <sys/sunddi.h>
58 58 #include <sys/ddi_impldefs.h>
59 59 #include <sys/pci.h>
60 60 #include <sys/promif.h>
61 61 #include <sys/x86_archext.h>
62 62 #include <sys/cpc_impl.h>
63 63 #include <sys/uadmin.h>
64 64 #include <sys/panic.h>
65 65 #include <sys/debug.h>
66 66 #include <sys/archsystm.h>
67 67 #include <sys/trap.h>
68 68 #include <sys/machsystm.h>
69 69 #include <sys/sysmacros.h>
70 70 #include <sys/cpuvar.h>
71 71 #include <sys/rm_platter.h>
72 72 #include <sys/privregs.h>
73 73 #include <sys/note.h>
74 74 #include <sys/pci_intr_lib.h>
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75 75 #include <sys/spl.h>
76 76 #include <sys/clock.h>
77 77 #include <sys/cyclic.h>
78 78 #include <sys/dditypes.h>
79 79 #include <sys/sunddi.h>
80 80 #include <sys/x_call.h>
81 81 #include <sys/reboot.h>
82 82 #include <sys/hpet.h>
83 83 #include <sys/apic_common.h>
84 84 #include <sys/apic_timer.h>
85 +#include <sys/ht.h>
85 86
86 87 /*
87 88 * Local Function Prototypes
88 89 */
89 90 static void apic_init_intr(void);
90 91
91 92 /*
92 93 * standard MP entries
93 94 */
94 95 static int apic_probe(void);
95 96 static int apic_getclkirq(int ipl);
96 97 static void apic_init(void);
97 98 static void apic_picinit(void);
98 99 static int apic_post_cpu_start(void);
99 100 static int apic_intr_enter(int ipl, int *vect);
100 101 static void apic_setspl(int ipl);
101 102 static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl);
102 103 static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl);
103 104 static int apic_disable_intr(processorid_t cpun);
104 105 static void apic_enable_intr(processorid_t cpun);
105 106 static int apic_get_ipivect(int ipl, int type);
106 107 static void apic_post_cyclic_setup(void *arg);
107 108
108 109 #define UCHAR_MAX UINT8_MAX
109 110
110 111 /*
111 112 * The following vector assignments influence the value of ipltopri and
112 113 * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program
113 114 * idle to 0 and IPL 0 to 0xf to differentiate idle in case
114 115 * we care to do so in future. Note some IPLs which are rarely used
115 116 * will share the vector ranges and heavily used IPLs (5 and 6) have
116 117 * a wide range.
117 118 *
118 119 * This array is used to initialize apic_ipls[] (in apic_init()).
119 120 *
120 121 * IPL Vector range. as passed to intr_enter
121 122 * 0 none.
122 123 * 1,2,3 0x20-0x2f 0x0-0xf
123 124 * 4 0x30-0x3f 0x10-0x1f
124 125 * 5 0x40-0x5f 0x20-0x3f
125 126 * 6 0x60-0x7f 0x40-0x5f
126 127 * 7,8,9 0x80-0x8f 0x60-0x6f
127 128 * 10 0x90-0x9f 0x70-0x7f
128 129 * 11 0xa0-0xaf 0x80-0x8f
129 130 * ... ...
130 131 * 15 0xe0-0xef 0xc0-0xcf
131 132 * 15 0xf0-0xff 0xd0-0xdf
132 133 */
133 134 uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = {
134 135 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15
135 136 };
136 137 /*
137 138 * The ipl of an ISR at vector X is apic_vectortoipl[X>>4]
138 139 * NOTE that this is vector as passed into intr_enter which is
139 140 * programmed vector - 0x20 (APIC_BASE_VECT)
140 141 */
141 142
142 143 uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */
143 144 /* The taskpri to be programmed into apic to mask given ipl */
144 145
145 146 /*
146 147 * Correlation of the hardware vector to the IPL in use, initialized
147 148 * from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate
148 149 * to the IPLs in apic_vectortoipl on some systems that share interrupt lines
149 150 * connected to errata-stricken IOAPICs
150 151 */
151 152 uchar_t apic_ipls[APIC_AVAIL_VECTOR];
152 153
153 154 /*
154 155 * Patchable global variables.
155 156 */
156 157 int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */
157 158 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */
158 159
159 160 /*
160 161 * Local static data
161 162 */
162 163 static struct psm_ops apic_ops = {
163 164 apic_probe,
164 165
165 166 apic_init,
166 167 apic_picinit,
167 168 apic_intr_enter,
168 169 apic_intr_exit,
169 170 apic_setspl,
170 171 apic_addspl,
171 172 apic_delspl,
172 173 apic_disable_intr,
173 174 apic_enable_intr,
174 175 (int (*)(int))NULL, /* psm_softlvl_to_irq */
175 176 (void (*)(int))NULL, /* psm_set_softintr */
176 177
177 178 apic_set_idlecpu,
178 179 apic_unset_idlecpu,
179 180
180 181 apic_clkinit,
181 182 apic_getclkirq,
182 183 (void (*)(void))NULL, /* psm_hrtimeinit */
183 184 apic_gethrtime,
184 185
185 186 apic_get_next_processorid,
186 187 apic_cpu_start,
187 188 apic_post_cpu_start,
188 189 apic_shutdown,
189 190 apic_get_ipivect,
190 191 apic_send_ipi,
191 192
192 193 (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */
193 194 (void (*)(int, char *))NULL, /* psm_notify_error */
194 195 (void (*)(int))NULL, /* psm_notify_func */
195 196 apic_timer_reprogram,
196 197 apic_timer_enable,
197 198 apic_timer_disable,
198 199 apic_post_cyclic_setup,
199 200 apic_preshutdown,
200 201 apic_intr_ops, /* Advanced DDI Interrupt framework */
201 202 apic_state, /* save, restore apic state for S3 */
202 203 apic_cpu_ops, /* CPU control interface. */
203 204
204 205 apic_get_pir_ipivect,
205 206 apic_send_pir_ipi,
206 207 apic_cmci_setup,
207 208 };
208 209
209 210 struct psm_ops *psmops = &apic_ops;
210 211
211 212 static struct psm_info apic_psm_info = {
212 213 PSM_INFO_VER01_7, /* version */
213 214 PSM_OWN_EXCLUSIVE, /* ownership */
214 215 (struct psm_ops *)&apic_ops, /* operation */
215 216 APIC_PCPLUSMP_NAME, /* machine name */
216 217 "pcplusmp v1.4 compatible",
217 218 };
218 219
219 220 static void *apic_hdlp;
220 221
221 222 /* to gather intr data and redistribute */
222 223 static void apic_redistribute_compute(void);
223 224
224 225 /*
225 226 * This is the loadable module wrapper
226 227 */
227 228
228 229 int
229 230 _init(void)
230 231 {
231 232 if (apic_coarse_hrtime)
232 233 apic_ops.psm_gethrtime = &apic_gettime;
233 234 return (psm_mod_init(&apic_hdlp, &apic_psm_info));
234 235 }
235 236
236 237 int
237 238 _fini(void)
238 239 {
239 240 return (psm_mod_fini(&apic_hdlp, &apic_psm_info));
240 241 }
241 242
242 243 int
243 244 _info(struct modinfo *modinfop)
244 245 {
245 246 return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop));
246 247 }
247 248
248 249 static int
249 250 apic_probe(void)
250 251 {
251 252 /* check if apix is initialized */
252 253 if (apix_enable && apix_loaded())
253 254 return (PSM_FAILURE);
254 255
255 256 /*
256 257 * Check whether x2APIC mode was activated by BIOS. We don't support
257 258 * that in pcplusmp as apix normally handles that.
258 259 */
259 260 if (apic_local_mode() == LOCAL_X2APIC)
260 261 return (PSM_FAILURE);
261 262
262 263 /* continue using pcplusmp PSM */
263 264 apix_enable = 0;
264 265
265 266 return (apic_probe_common(apic_psm_info.p_mach_idstring));
266 267 }
267 268
268 269 static uchar_t
269 270 apic_xlate_vector_by_irq(uchar_t irq)
270 271 {
271 272 if (apic_irq_table[irq] == NULL)
272 273 return (0);
273 274
274 275 return (apic_irq_table[irq]->airq_vector);
275 276 }
276 277
277 278 void
278 279 apic_init(void)
279 280 {
280 281 int i;
281 282 int j = 1;
282 283
283 284 psm_get_ioapicid = apic_get_ioapicid;
284 285 psm_get_localapicid = apic_get_localapicid;
285 286 psm_xlate_vector_by_irq = apic_xlate_vector_by_irq;
286 287
287 288 apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */
288 289 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) {
289 290 if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) &&
290 291 (apic_vectortoipl[i + 1] == apic_vectortoipl[i]))
291 292 /* get to highest vector at the same ipl */
292 293 continue;
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293 294 for (; j <= apic_vectortoipl[i]; j++) {
294 295 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) +
295 296 APIC_BASE_VECT;
296 297 }
297 298 }
298 299 for (; j < MAXIPL + 1; j++)
299 300 /* fill up any empty ipltopri slots */
300 301 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT;
301 302 apic_init_common();
302 303
304 + /*
305 + * For pcplusmp, we'll keep things simple and always disable this.
306 + */
307 + ht_intr_alloc_pil(XC_CPUPOKE_PIL);
308 +
303 309 apic_pir_vect = apic_get_ipivect(XC_CPUPOKE_PIL, -1);
304 310
305 311 #if !defined(__amd64)
306 312 if (cpuid_have_cr8access(CPU))
307 313 apic_have_32bit_cr8 = 1;
308 314 #endif
309 315 }
310 316
311 317 static void
312 318 apic_init_intr(void)
313 319 {
314 320 processorid_t cpun = psm_get_cpu_id();
315 321 uint_t nlvt;
316 322 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR;
317 323
318 324 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL);
319 325
320 326 ASSERT(apic_mode == LOCAL_APIC);
321 327
322 328 /*
323 329 * We are running APIC in MMIO mode.
324 330 */
325 331 if (apic_flat_model) {
326 332 apic_reg_ops->apic_write(APIC_FORMAT_REG, APIC_FLAT_MODEL);
327 333 } else {
328 334 apic_reg_ops->apic_write(APIC_FORMAT_REG, APIC_CLUSTER_MODEL);
329 335 }
330 336
331 337 apic_reg_ops->apic_write(APIC_DEST_REG, AV_HIGH_ORDER >> cpun);
332 338
333 339 if (apic_directed_EOI_supported()) {
334 340 /*
335 341 * Setting the 12th bit in the Spurious Interrupt Vector
336 342 * Register suppresses broadcast EOIs generated by the local
337 343 * APIC. The suppression of broadcast EOIs happens only when
338 344 * interrupts are level-triggered.
339 345 */
340 346 svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI;
341 347 }
342 348
343 349 /* need to enable APIC before unmasking NMI */
344 350 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr);
345 351
346 352 /*
347 353 * Presence of an invalid vector with delivery mode AV_FIXED can
348 354 * cause an error interrupt, even if the entry is masked...so
349 355 * write a valid vector to LVT entries along with the mask bit
350 356 */
351 357
352 358 /* All APICs have timer and LINT0/1 */
353 359 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ);
354 360 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ);
355 361 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */
356 362
357 363 /*
358 364 * On integrated APICs, the number of LVT entries is
359 365 * 'Max LVT entry' + 1; on 82489DX's (non-integrated
360 366 * APICs), nlvt is "3" (LINT0, LINT1, and timer)
361 367 */
362 368
363 369 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) {
364 370 nlvt = 3;
365 371 } else {
366 372 nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) &
367 373 0xFF) + 1;
368 374 }
369 375
370 376 if (nlvt >= 5) {
371 377 /* Enable performance counter overflow interrupt */
372 378
373 379 if (!is_x86_feature(x86_featureset, X86FSET_MSR))
374 380 apic_enable_cpcovf_intr = 0;
375 381 if (apic_enable_cpcovf_intr) {
376 382 if (apic_cpcovf_vect == 0) {
377 383 int ipl = APIC_PCINT_IPL;
378 384 int irq = apic_get_ipivect(ipl, -1);
379 385
380 386 ASSERT(irq != -1);
381 387 apic_cpcovf_vect =
382 388 apic_irq_table[irq]->airq_vector;
383 389 ASSERT(apic_cpcovf_vect);
384 390 (void) add_avintr(NULL, ipl,
385 391 (avfunc)kcpc_hw_overflow_intr,
386 392 "apic pcint", irq, NULL, NULL, NULL, NULL);
387 393 kcpc_hw_overflow_intr_installed = 1;
388 394 kcpc_hw_enable_cpc_intr =
389 395 apic_cpcovf_mask_clear;
390 396 }
391 397 apic_reg_ops->apic_write(APIC_PCINT_VECT,
392 398 apic_cpcovf_vect);
393 399 }
394 400 }
395 401
396 402 if (nlvt >= 6) {
397 403 /* Only mask TM intr if the BIOS apparently doesn't use it */
398 404
399 405 uint32_t lvtval;
400 406
401 407 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT);
402 408 if (((lvtval & AV_MASK) == AV_MASK) ||
403 409 ((lvtval & AV_DELIV_MODE) != AV_SMI)) {
404 410 apic_reg_ops->apic_write(APIC_THERM_VECT,
405 411 AV_MASK|APIC_RESV_IRQ);
406 412 }
407 413 }
408 414
409 415 /* Enable error interrupt */
410 416
411 417 if (nlvt >= 4 && apic_enable_error_intr) {
412 418 if (apic_errvect == 0) {
413 419 int ipl = 0xf; /* get highest priority intr */
414 420 int irq = apic_get_ipivect(ipl, -1);
415 421
416 422 ASSERT(irq != -1);
417 423 apic_errvect = apic_irq_table[irq]->airq_vector;
418 424 ASSERT(apic_errvect);
419 425 /*
420 426 * Not PSMI compliant, but we are going to merge
421 427 * with ON anyway
422 428 */
423 429 (void) add_avintr((void *)NULL, ipl,
424 430 (avfunc)apic_error_intr, "apic error intr",
425 431 irq, NULL, NULL, NULL, NULL);
426 432 }
427 433 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect);
428 434 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
429 435 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
430 436 }
431 437
432 438 /*
433 439 * Ensure a CMCI interrupt is allocated, regardless of whether it is
434 440 * enabled or not.
435 441 */
436 442 if (apic_cmci_vect == 0) {
437 443 const int ipl = 0x2;
438 444 int irq = apic_get_ipivect(ipl, -1);
439 445
440 446 ASSERT(irq != -1);
441 447 apic_cmci_vect = apic_irq_table[irq]->airq_vector;
442 448 ASSERT(apic_cmci_vect);
443 449
444 450 (void) add_avintr(NULL, ipl,
445 451 (avfunc)cmi_cmci_trap,
446 452 "apic cmci intr", irq, NULL, NULL, NULL, NULL);
447 453 }
448 454 }
449 455
450 456 static void
451 457 apic_picinit(void)
452 458 {
453 459 int i, j;
454 460 uint_t isr;
455 461
456 462 /*
457 463 * Initialize and enable interrupt remapping before apic
458 464 * hardware initialization
459 465 */
460 466 apic_intrmap_init(apic_mode);
461 467
462 468 /*
463 469 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr
464 470 * bit on without clearing it with EOI. Since softint
465 471 * uses vector 0x20 to interrupt itself, so softint will
466 472 * not work on this machine. In order to fix this problem
467 473 * a check is made to verify all the isr bits are clear.
468 474 * If not, EOIs are issued to clear the bits.
469 475 */
470 476 for (i = 7; i >= 1; i--) {
471 477 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4));
472 478 if (isr != 0)
473 479 for (j = 0; ((j < 32) && (isr != 0)); j++)
474 480 if (isr & (1 << j)) {
475 481 apic_reg_ops->apic_write(
476 482 APIC_EOI_REG, 0);
477 483 isr &= ~(1 << j);
478 484 apic_error |= APIC_ERR_BOOT_EOI;
479 485 }
480 486 }
481 487
482 488 /* set a flag so we know we have run apic_picinit() */
483 489 apic_picinit_called = 1;
484 490 LOCK_INIT_CLEAR(&apic_gethrtime_lock);
485 491 LOCK_INIT_CLEAR(&apic_ioapic_lock);
486 492 LOCK_INIT_CLEAR(&apic_error_lock);
487 493 LOCK_INIT_CLEAR(&apic_mode_switch_lock);
488 494
489 495 picsetup(); /* initialise the 8259 */
490 496
491 497 /* add nmi handler - least priority nmi handler */
492 498 LOCK_INIT_CLEAR(&apic_nmi_lock);
493 499
494 500 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr,
495 501 "pcplusmp NMI handler", (caddr_t)NULL))
496 502 cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler");
497 503
498 504 /*
499 505 * Check for directed-EOI capability in the local APIC.
500 506 */
501 507 if (apic_directed_EOI_supported() == 1) {
502 508 apic_set_directed_EOI_handler();
503 509 }
504 510
505 511 apic_init_intr();
506 512
507 513 /* enable apic mode if imcr present */
508 514 if (apic_imcrp) {
509 515 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT);
510 516 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC);
511 517 }
512 518
513 519 ioapic_init_intr(IOAPIC_MASK);
514 520 }
515 521
516 522 #ifdef DEBUG
517 523 void
518 524 apic_break(void)
519 525 {
520 526 }
521 527 #endif /* DEBUG */
522 528
523 529 /*
524 530 * platform_intr_enter
525 531 *
526 532 * Called at the beginning of the interrupt service routine to
527 533 * mask all level equal to and below the interrupt priority
528 534 * of the interrupting vector. An EOI should be given to
529 535 * the interrupt controller to enable other HW interrupts.
530 536 *
531 537 * Return -1 for spurious interrupts
532 538 *
533 539 */
534 540 /*ARGSUSED*/
535 541 static int
536 542 apic_intr_enter(int ipl, int *vectorp)
537 543 {
538 544 uchar_t vector;
539 545 int nipl;
540 546 int irq;
541 547 ulong_t iflag;
542 548 apic_cpus_info_t *cpu_infop;
543 549
544 550 /*
545 551 * The real vector delivered is (*vectorp + 0x20), but our caller
546 552 * subtracts 0x20 from the vector before passing it to us.
547 553 * (That's why APIC_BASE_VECT is 0x20.)
548 554 */
549 555 vector = (uchar_t)*vectorp;
550 556
551 557 /* if interrupted by the clock, increment apic_nsec_since_boot */
552 558 if (vector == apic_clkvect) {
553 559 if (!apic_oneshot) {
554 560 /* NOTE: this is not MT aware */
555 561 apic_hrtime_stamp++;
556 562 apic_nsec_since_boot += apic_nsec_per_intr;
557 563 apic_hrtime_stamp++;
558 564 last_count_read = apic_hertz_count;
559 565 apic_redistribute_compute();
560 566 }
561 567
562 568 /* We will avoid all the book keeping overhead for clock */
563 569 nipl = apic_ipls[vector];
564 570
565 571 *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT];
566 572
567 573 apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]);
568 574 apic_reg_ops->apic_send_eoi(0);
569 575
570 576 return (nipl);
571 577 }
572 578
573 579 cpu_infop = &apic_cpus[psm_get_cpu_id()];
574 580
575 581 if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) {
576 582 cpu_infop->aci_spur_cnt++;
577 583 return (APIC_INT_SPURIOUS);
578 584 }
579 585
580 586 /* Check if the vector we got is really what we need */
581 587 if (apic_revector_pending) {
582 588 /*
583 589 * Disable interrupts for the duration of
584 590 * the vector translation to prevent a self-race for
585 591 * the apic_revector_lock. This cannot be done
586 592 * in apic_xlate_vector because it is recursive and
587 593 * we want the vector translation to be atomic with
588 594 * respect to other (higher-priority) interrupts.
589 595 */
590 596 iflag = intr_clear();
591 597 vector = apic_xlate_vector(vector + APIC_BASE_VECT) -
592 598 APIC_BASE_VECT;
593 599 intr_restore(iflag);
594 600 }
595 601
596 602 nipl = apic_ipls[vector];
597 603 *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT];
598 604
599 605 apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]);
600 606
601 607 cpu_infop->aci_current[nipl] = (uchar_t)irq;
602 608 cpu_infop->aci_curipl = (uchar_t)nipl;
603 609 cpu_infop->aci_ISR_in_progress |= 1 << nipl;
604 610
605 611 /*
606 612 * apic_level_intr could have been assimilated into the irq struct.
607 613 * but, having it as a character array is more efficient in terms of
608 614 * cache usage. So, we leave it as is.
609 615 */
610 616 if (!apic_level_intr[irq]) {
611 617 apic_reg_ops->apic_send_eoi(0);
612 618 }
613 619
614 620 #ifdef DEBUG
615 621 APIC_DEBUG_BUF_PUT(vector);
616 622 APIC_DEBUG_BUF_PUT(irq);
617 623 APIC_DEBUG_BUF_PUT(nipl);
618 624 APIC_DEBUG_BUF_PUT(psm_get_cpu_id());
619 625 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl)))
620 626 drv_usecwait(apic_stretch_interrupts);
621 627
622 628 if (apic_break_on_cpu == psm_get_cpu_id())
623 629 apic_break();
624 630 #endif /* DEBUG */
625 631 return (nipl);
626 632 }
627 633
628 634 void
629 635 apic_intr_exit(int prev_ipl, int irq)
630 636 {
631 637 apic_cpus_info_t *cpu_infop;
632 638
633 639 apic_reg_ops->apic_write_task_reg(apic_ipltopri[prev_ipl]);
634 640
635 641 cpu_infop = &apic_cpus[psm_get_cpu_id()];
636 642 if (apic_level_intr[irq])
637 643 apic_reg_ops->apic_send_eoi(irq);
638 644 cpu_infop->aci_curipl = (uchar_t)prev_ipl;
639 645 /* ISR above current pri could not be in progress */
640 646 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1;
641 647 }
642 648
643 649 intr_exit_fn_t
644 650 psm_intr_exit_fn(void)
645 651 {
646 652 return (apic_intr_exit);
647 653 }
648 654
649 655 /*
650 656 * Mask all interrupts below or equal to the given IPL.
651 657 */
652 658 static void
653 659 apic_setspl(int ipl)
654 660 {
655 661 apic_reg_ops->apic_write_task_reg(apic_ipltopri[ipl]);
656 662
657 663 /* interrupts at ipl above this cannot be in progress */
658 664 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
659 665 /*
660 666 * this is a patch fix for the ALR QSMP P5 machine, so that interrupts
661 667 * have enough time to come in before the priority is raised again
662 668 * during the idle() loop.
663 669 */
664 670 if (apic_setspl_delay)
665 671 (void) apic_reg_ops->apic_get_pri();
666 672 }
667 673
668 674 /*ARGSUSED*/
669 675 static int
670 676 apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl)
671 677 {
672 678 return (apic_addspl_common(irqno, ipl, min_ipl, max_ipl));
673 679 }
674 680
675 681 static int
676 682 apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl)
677 683 {
678 684 return (apic_delspl_common(irqno, ipl, min_ipl, max_ipl));
679 685 }
680 686
681 687 static int
682 688 apic_post_cpu_start(void)
683 689 {
684 690 int cpun;
685 691 static int cpus_started = 1;
686 692
687 693 /* We know this CPU + BSP started successfully. */
688 694 cpus_started++;
689 695
690 696 splx(ipltospl(LOCK_LEVEL));
691 697 apic_init_intr();
692 698
693 699 /*
694 700 * since some systems don't enable the internal cache on the non-boot
695 701 * cpus, so we have to enable them here
696 702 */
697 703 setcr0(getcr0() & ~(CR0_CD | CR0_NW));
698 704
699 705 APIC_AV_PENDING_SET();
700 706
701 707 /*
702 708 * We may be booting, or resuming from suspend; aci_status will
703 709 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the
704 710 * APIC_CPU_ONLINE flag here rather than setting aci_status completely.
705 711 */
706 712 cpun = psm_get_cpu_id();
707 713 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE;
708 714
709 715 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init);
710 716 return (PSM_SUCCESS);
711 717 }
712 718
713 719 /*
714 720 * type == -1 indicates it is an internal request. Do not change
715 721 * resv_vector for these requests
716 722 */
717 723 static int
718 724 apic_get_ipivect(int ipl, int type)
719 725 {
720 726 uchar_t vector;
721 727 int irq;
722 728
723 729 if ((irq = apic_allocate_irq(APIC_VECTOR(ipl))) != -1) {
724 730 if ((vector = apic_allocate_vector(ipl, irq, 1))) {
725 731 apic_irq_table[irq]->airq_mps_intr_index =
726 732 RESERVE_INDEX;
727 733 apic_irq_table[irq]->airq_vector = vector;
728 734 if (type != -1) {
729 735 apic_resv_vector[ipl] = vector;
730 736 }
731 737 return (irq);
732 738 }
733 739 }
734 740 apic_error |= APIC_ERR_GET_IPIVECT_FAIL;
735 741 return (-1); /* shouldn't happen */
736 742 }
737 743
738 744 static int
739 745 apic_getclkirq(int ipl)
740 746 {
741 747 int irq;
742 748
743 749 if ((irq = apic_get_ipivect(ipl, -1)) == -1)
744 750 return (-1);
745 751 /*
746 752 * Note the vector in apic_clkvect for per clock handling.
747 753 */
748 754 apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT;
749 755 APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n",
750 756 apic_clkvect));
751 757 return (irq);
752 758 }
753 759
754 760 /*
755 761 * Try and disable all interrupts. We just assign interrupts to other
756 762 * processors based on policy. If any were bound by user request, we
757 763 * let them continue and return failure. We do not bother to check
758 764 * for cache affinity while rebinding.
759 765 */
760 766
761 767 static int
762 768 apic_disable_intr(processorid_t cpun)
763 769 {
764 770 int bind_cpu = 0, i, hardbound = 0;
765 771 apic_irq_t *irq_ptr;
766 772 ulong_t iflag;
767 773
768 774 iflag = intr_clear();
769 775 lock_set(&apic_ioapic_lock);
770 776
771 777 for (i = 0; i <= APIC_MAX_VECTOR; i++) {
772 778 if (apic_reprogram_info[i].done == B_FALSE) {
773 779 if (apic_reprogram_info[i].bindcpu == cpun) {
774 780 /*
775 781 * CPU is busy -- it's the target of
776 782 * a pending reprogramming attempt
777 783 */
778 784 lock_clear(&apic_ioapic_lock);
779 785 intr_restore(iflag);
780 786 return (PSM_FAILURE);
781 787 }
782 788 }
783 789 }
784 790
785 791 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE;
786 792
787 793 apic_cpus[cpun].aci_curipl = 0;
788 794
789 795 i = apic_min_device_irq;
790 796 for (; i <= apic_max_device_irq; i++) {
791 797 /*
792 798 * If there are bound interrupts on this cpu, then
793 799 * rebind them to other processors.
794 800 */
795 801 if ((irq_ptr = apic_irq_table[i]) != NULL) {
796 802 ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) ||
797 803 (irq_ptr->airq_temp_cpu == IRQ_UNINIT) ||
798 804 (apic_cpu_in_range(irq_ptr->airq_temp_cpu)));
799 805
800 806 if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) {
801 807 hardbound = 1;
802 808 continue;
803 809 }
804 810
805 811 if (irq_ptr->airq_temp_cpu == cpun) {
806 812 do {
807 813 bind_cpu =
808 814 apic_find_cpu(APIC_CPU_INTR_ENABLE);
809 815 } while (apic_rebind_all(irq_ptr, bind_cpu));
810 816 }
811 817 }
812 818 }
813 819
814 820 lock_clear(&apic_ioapic_lock);
815 821 intr_restore(iflag);
816 822
817 823 if (hardbound) {
818 824 cmn_err(CE_WARN, "Could not disable interrupts on %d"
819 825 "due to user bound interrupts", cpun);
820 826 return (PSM_FAILURE);
821 827 }
822 828 else
823 829 return (PSM_SUCCESS);
824 830 }
825 831
826 832 /*
827 833 * Bind interrupts to the CPU's local APIC.
828 834 * Interrupts should not be bound to a CPU's local APIC until the CPU
829 835 * is ready to receive interrupts.
830 836 */
831 837 static void
832 838 apic_enable_intr(processorid_t cpun)
833 839 {
834 840 int i;
835 841 apic_irq_t *irq_ptr;
836 842 ulong_t iflag;
837 843
838 844 iflag = intr_clear();
839 845 lock_set(&apic_ioapic_lock);
840 846
841 847 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE;
842 848
843 849 i = apic_min_device_irq;
844 850 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
845 851 if ((irq_ptr = apic_irq_table[i]) != NULL) {
846 852 if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) {
847 853 (void) apic_rebind_all(irq_ptr,
848 854 irq_ptr->airq_cpu);
849 855 }
850 856 }
851 857 }
852 858
853 859 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND)
854 860 apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND;
855 861
856 862 lock_clear(&apic_ioapic_lock);
857 863 intr_restore(iflag);
858 864 }
859 865
860 866 /*
861 867 * If this module needs a periodic handler for the interrupt distribution, it
862 868 * can be added here. The argument to the periodic handler is not currently
863 869 * used, but is reserved for future.
864 870 */
865 871 static void
866 872 apic_post_cyclic_setup(void *arg)
867 873 {
868 874 _NOTE(ARGUNUSED(arg))
869 875
870 876 cyc_handler_t cyh;
871 877 cyc_time_t cyt;
872 878
873 879 /* cpu_lock is held */
874 880 /* set up a periodic handler for intr redistribution */
875 881
876 882 /*
877 883 * In peridoc mode intr redistribution processing is done in
878 884 * apic_intr_enter during clk intr processing
879 885 */
880 886 if (!apic_oneshot)
881 887 return;
882 888
883 889 /*
884 890 * Register a periodical handler for the redistribution processing.
885 891 * Though we would generally prefer to use the DDI interface for
886 892 * periodic handler invocation, ddi_periodic_add(9F), we are
887 893 * unfortunately already holding cpu_lock, which ddi_periodic_add will
888 894 * attempt to take for us. Thus, we add our own cyclic directly:
889 895 */
890 896 cyh.cyh_func = (void (*)(void *))apic_redistribute_compute;
891 897 cyh.cyh_arg = NULL;
892 898 cyh.cyh_level = CY_LOW_LEVEL;
893 899
894 900 cyt.cyt_when = 0;
895 901 cyt.cyt_interval = apic_redistribute_sample_interval;
896 902
897 903 apic_cyclic_id = cyclic_add(&cyh, &cyt);
898 904 }
899 905
900 906 static void
901 907 apic_redistribute_compute(void)
902 908 {
903 909 int i, j, max_busy;
904 910
905 911 if (apic_enable_dynamic_migration) {
906 912 if (++apic_nticks == apic_sample_factor_redistribution) {
907 913 /*
908 914 * Time to call apic_intr_redistribute().
909 915 * reset apic_nticks. This will cause max_busy
910 916 * to be calculated below and if it is more than
911 917 * apic_int_busy, we will do the whole thing
912 918 */
913 919 apic_nticks = 0;
914 920 }
915 921 max_busy = 0;
916 922 for (i = 0; i < apic_nproc; i++) {
917 923 if (!apic_cpu_in_range(i))
918 924 continue;
919 925
920 926 /*
921 927 * Check if curipl is non zero & if ISR is in
922 928 * progress
923 929 */
924 930 if (((j = apic_cpus[i].aci_curipl) != 0) &&
925 931 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) {
926 932
927 933 int irq;
928 934 apic_cpus[i].aci_busy++;
929 935 irq = apic_cpus[i].aci_current[j];
930 936 apic_irq_table[irq]->airq_busy++;
931 937 }
932 938
933 939 if (!apic_nticks &&
934 940 (apic_cpus[i].aci_busy > max_busy))
935 941 max_busy = apic_cpus[i].aci_busy;
936 942 }
937 943 if (!apic_nticks) {
938 944 if (max_busy > apic_int_busy_mark) {
939 945 /*
940 946 * We could make the following check be
941 947 * skipped > 1 in which case, we get a
942 948 * redistribution at half the busy mark (due to
943 949 * double interval). Need to be able to collect
944 950 * more empirical data to decide if that is a
945 951 * good strategy. Punt for now.
946 952 */
947 953 if (apic_skipped_redistribute) {
948 954 apic_cleanup_busy();
949 955 apic_skipped_redistribute = 0;
950 956 } else {
951 957 apic_intr_redistribute();
952 958 }
953 959 } else
954 960 apic_skipped_redistribute++;
955 961 }
956 962 }
957 963 }
958 964
959 965
960 966 /*
961 967 * The following functions are in the platform specific file so that they
962 968 * can be different functions depending on whether we are running on
963 969 * bare metal or a hypervisor.
964 970 */
965 971
966 972 /*
967 973 * Check to make sure there are enough irq slots
968 974 */
969 975 int
970 976 apic_check_free_irqs(int count)
971 977 {
972 978 int i, avail;
973 979
974 980 avail = 0;
975 981 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
976 982 if ((apic_irq_table[i] == NULL) ||
977 983 apic_irq_table[i]->airq_mps_intr_index == FREE_INDEX) {
978 984 if (++avail >= count)
979 985 return (PSM_SUCCESS);
980 986 }
981 987 }
982 988 return (PSM_FAILURE);
983 989 }
984 990
985 991 /*
986 992 * This function allocates "count" MSI vector(s) for the given "dip/pri/type"
987 993 */
988 994 int
989 995 apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, int pri,
990 996 int behavior)
991 997 {
992 998 int rcount, i;
993 999 uchar_t start, irqno;
994 1000 uint32_t cpu = 0;
995 1001 major_t major;
996 1002 apic_irq_t *irqptr;
997 1003
998 1004 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: dip=0x%p "
999 1005 "inum=0x%x pri=0x%x count=0x%x behavior=%d\n",
1000 1006 (void *)dip, inum, pri, count, behavior));
1001 1007
1002 1008 if (count > 1) {
1003 1009 if (behavior == DDI_INTR_ALLOC_STRICT &&
1004 1010 apic_multi_msi_enable == 0)
1005 1011 return (0);
1006 1012 if (apic_multi_msi_enable == 0)
1007 1013 count = 1;
1008 1014 }
1009 1015
1010 1016 if ((rcount = apic_navail_vector(dip, pri)) > count)
1011 1017 rcount = count;
1012 1018 else if (rcount == 0 || (rcount < count &&
1013 1019 behavior == DDI_INTR_ALLOC_STRICT))
1014 1020 return (0);
1015 1021
1016 1022 /* if not ISP2, then round it down */
1017 1023 if (!ISP2(rcount))
1018 1024 rcount = 1 << (highbit(rcount) - 1);
1019 1025
1020 1026 mutex_enter(&airq_mutex);
1021 1027
1022 1028 for (start = 0; rcount > 0; rcount >>= 1) {
1023 1029 if ((start = apic_find_multi_vectors(pri, rcount)) != 0 ||
1024 1030 behavior == DDI_INTR_ALLOC_STRICT)
1025 1031 break;
1026 1032 }
1027 1033
1028 1034 if (start == 0) {
1029 1035 /* no vector available */
1030 1036 mutex_exit(&airq_mutex);
1031 1037 return (0);
1032 1038 }
1033 1039
1034 1040 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1035 1041 /* not enough free irq slots available */
1036 1042 mutex_exit(&airq_mutex);
1037 1043 return (0);
1038 1044 }
1039 1045
1040 1046 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1041 1047 for (i = 0; i < rcount; i++) {
1042 1048 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1043 1049 (uchar_t)-1) {
1044 1050 /*
1045 1051 * shouldn't happen because of the
1046 1052 * apic_check_free_irqs() check earlier
1047 1053 */
1048 1054 mutex_exit(&airq_mutex);
1049 1055 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1050 1056 "apic_allocate_irq failed\n"));
1051 1057 return (i);
1052 1058 }
1053 1059 apic_max_device_irq = max(irqno, apic_max_device_irq);
1054 1060 apic_min_device_irq = min(irqno, apic_min_device_irq);
1055 1061 irqptr = apic_irq_table[irqno];
1056 1062 #ifdef DEBUG
1057 1063 if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ)
1058 1064 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1059 1065 "apic_vector_to_irq is not APIC_RESV_IRQ\n"));
1060 1066 #endif
1061 1067 apic_vector_to_irq[start + i] = (uchar_t)irqno;
1062 1068
1063 1069 irqptr->airq_vector = (uchar_t)(start + i);
1064 1070 irqptr->airq_ioapicindex = (uchar_t)inum; /* start */
1065 1071 irqptr->airq_intin_no = (uchar_t)rcount;
1066 1072 ASSERT(pri >= 0 && pri <= UCHAR_MAX);
1067 1073 irqptr->airq_ipl = (uchar_t)pri;
1068 1074 irqptr->airq_vector = start + i;
1069 1075 irqptr->airq_origirq = (uchar_t)(inum + i);
1070 1076 irqptr->airq_share_id = 0;
1071 1077 irqptr->airq_mps_intr_index = MSI_INDEX;
1072 1078 irqptr->airq_dip = dip;
1073 1079 irqptr->airq_major = major;
1074 1080 if (i == 0) /* they all bound to the same cpu */
1075 1081 cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno,
1076 1082 0xff, 0xff);
1077 1083 else
1078 1084 irqptr->airq_cpu = cpu;
1079 1085 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: irq=0x%x "
1080 1086 "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno,
1081 1087 (void *)irqptr->airq_dip, irqptr->airq_vector,
1082 1088 irqptr->airq_origirq, pri));
1083 1089 }
1084 1090 mutex_exit(&airq_mutex);
1085 1091 return (rcount);
1086 1092 }
1087 1093
1088 1094 /*
1089 1095 * This function allocates "count" MSI-X vector(s) for the given "dip/pri/type"
1090 1096 */
1091 1097 int
1092 1098 apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, int pri,
1093 1099 int behavior)
1094 1100 {
1095 1101 int rcount, i;
1096 1102 major_t major;
1097 1103
1098 1104 mutex_enter(&airq_mutex);
1099 1105
1100 1106 if ((rcount = apic_navail_vector(dip, pri)) > count)
1101 1107 rcount = count;
1102 1108 else if (rcount == 0 || (rcount < count &&
1103 1109 behavior == DDI_INTR_ALLOC_STRICT)) {
1104 1110 rcount = 0;
1105 1111 goto out;
1106 1112 }
1107 1113
1108 1114 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1109 1115 /* not enough free irq slots available */
1110 1116 rcount = 0;
1111 1117 goto out;
1112 1118 }
1113 1119
1114 1120 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1115 1121 for (i = 0; i < rcount; i++) {
1116 1122 uchar_t vector, irqno;
1117 1123 apic_irq_t *irqptr;
1118 1124
1119 1125 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1120 1126 (uchar_t)-1) {
1121 1127 /*
1122 1128 * shouldn't happen because of the
1123 1129 * apic_check_free_irqs() check earlier
1124 1130 */
1125 1131 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1126 1132 "apic_allocate_irq failed\n"));
1127 1133 rcount = i;
1128 1134 goto out;
1129 1135 }
1130 1136 if ((vector = apic_allocate_vector(pri, irqno, 1)) == 0) {
1131 1137 /*
1132 1138 * shouldn't happen because of the
1133 1139 * apic_navail_vector() call earlier
1134 1140 */
1135 1141 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1136 1142 "apic_allocate_vector failed\n"));
1137 1143 rcount = i;
1138 1144 goto out;
1139 1145 }
1140 1146 apic_max_device_irq = max(irqno, apic_max_device_irq);
1141 1147 apic_min_device_irq = min(irqno, apic_min_device_irq);
1142 1148 irqptr = apic_irq_table[irqno];
1143 1149 irqptr->airq_vector = (uchar_t)vector;
1144 1150 ASSERT(pri >= 0 && pri <= UCHAR_MAX);
1145 1151 irqptr->airq_ipl = (uchar_t)pri;
1146 1152 irqptr->airq_origirq = (uchar_t)(inum + i);
1147 1153 irqptr->airq_share_id = 0;
1148 1154 irqptr->airq_mps_intr_index = MSIX_INDEX;
1149 1155 irqptr->airq_dip = dip;
1150 1156 irqptr->airq_major = major;
1151 1157 irqptr->airq_cpu = apic_bind_intr(dip, irqno, 0xff, 0xff);
1152 1158 }
1153 1159 out:
1154 1160 mutex_exit(&airq_mutex);
1155 1161 return (rcount);
1156 1162 }
1157 1163
1158 1164 /*
1159 1165 * Allocate a free vector for irq at ipl. Takes care of merging of multiple
1160 1166 * IPLs into a single APIC level as well as stretching some IPLs onto multiple
1161 1167 * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority
1162 1168 * requests and allocated only when pri is set.
1163 1169 */
1164 1170 uchar_t
1165 1171 apic_allocate_vector(int ipl, int irq, int pri)
1166 1172 {
1167 1173 int lowest, highest, i;
1168 1174
1169 1175 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK;
1170 1176 lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL;
1171 1177
1172 1178 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */
1173 1179 lowest -= APIC_VECTOR_PER_IPL;
1174 1180
1175 1181 #ifdef DEBUG
1176 1182 if (apic_restrict_vector) /* for testing shared interrupt logic */
1177 1183 highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS;
1178 1184 #endif /* DEBUG */
1179 1185 if (pri == 0)
1180 1186 highest -= APIC_HI_PRI_VECTS;
1181 1187
1182 1188 for (i = lowest; i <= highest; i++) {
1183 1189 if (APIC_CHECK_RESERVE_VECTORS(i))
1184 1190 continue;
1185 1191 if (apic_vector_to_irq[i] == APIC_RESV_IRQ) {
1186 1192 apic_vector_to_irq[i] = (uchar_t)irq;
1187 1193 ASSERT(i >= 0 && i <= UCHAR_MAX);
1188 1194 return ((uchar_t)i);
1189 1195 }
1190 1196 }
1191 1197
1192 1198 return (0);
1193 1199 }
1194 1200
1195 1201 /* Mark vector as not being used by any irq */
1196 1202 void
1197 1203 apic_free_vector(uchar_t vector)
1198 1204 {
1199 1205 apic_vector_to_irq[vector] = APIC_RESV_IRQ;
1200 1206 }
1201 1207
1202 1208 /*
1203 1209 * Call rebind to do the actual programming.
1204 1210 * Must be called with interrupts disabled and apic_ioapic_lock held
1205 1211 * 'p' is polymorphic -- if this function is called to process a deferred
1206 1212 * reprogramming, p is of type 'struct ioapic_reprogram_data *', from which
1207 1213 * the irq pointer is retrieved. If not doing deferred reprogramming,
1208 1214 * p is of the type 'apic_irq_t *'.
1209 1215 *
1210 1216 * apic_ioapic_lock must be held across this call, as it protects apic_rebind
1211 1217 * and it protects apic_get_next_bind_cpu() from a race in which a CPU can be
1212 1218 * taken offline after a cpu is selected, but before apic_rebind is called to
1213 1219 * bind interrupts to it.
1214 1220 */
1215 1221 int
1216 1222 apic_setup_io_intr(void *p, int irq, boolean_t deferred)
1217 1223 {
1218 1224 apic_irq_t *irqptr;
1219 1225 struct ioapic_reprogram_data *drep = NULL;
1220 1226 int rv;
1221 1227
1222 1228 if (deferred) {
1223 1229 drep = (struct ioapic_reprogram_data *)p;
1224 1230 ASSERT(drep != NULL);
1225 1231 irqptr = drep->irqp;
1226 1232 } else
1227 1233 irqptr = (apic_irq_t *)p;
1228 1234
1229 1235 ASSERT(irqptr != NULL);
1230 1236
1231 1237 rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, drep);
1232 1238 if (rv) {
1233 1239 /*
1234 1240 * CPU is not up or interrupts are disabled. Fall back to
1235 1241 * the first available CPU
1236 1242 */
1237 1243 rv = apic_rebind(irqptr, apic_find_cpu(APIC_CPU_INTR_ENABLE),
1238 1244 drep);
1239 1245 }
1240 1246
1241 1247 return (rv);
1242 1248 }
1243 1249
1244 1250
1245 1251 uchar_t
1246 1252 apic_modify_vector(uchar_t vector, int irq)
1247 1253 {
1248 1254 apic_vector_to_irq[vector] = (uchar_t)irq;
1249 1255 return (vector);
1250 1256 }
1251 1257
1252 1258 char *
1253 1259 apic_get_apic_type(void)
1254 1260 {
1255 1261 return (apic_psm_info.p_mach_idstring);
1256 1262 }
1257 1263
1258 1264 void
1259 1265 apic_switch_ipi_callback(boolean_t enter)
1260 1266 {
1261 1267 ASSERT(enter == B_TRUE);
1262 1268 }
1263 1269
1264 1270 int
1265 1271 apic_detect_x2apic(void)
1266 1272 {
1267 1273 return (0);
1268 1274 }
1269 1275
1270 1276 void
1271 1277 apic_enable_x2apic(void)
1272 1278 {
1273 1279 cmn_err(CE_PANIC, "apic_enable_x2apic() called in pcplusmp");
1274 1280 }
1275 1281
1276 1282 void
1277 1283 x2apic_update_psm(void)
1278 1284 {
1279 1285 cmn_err(CE_PANIC, "x2apic_update_psm() called in pcplusmp");
1280 1286 }
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