1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25 /*
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
28 * Copyright 2018 Joyent, Inc.
29 */
30
31 /*
32 * To understand how the pcplusmp module interacts with the interrupt subsystem
33 * read the theory statement in uts/i86pc/os/intr.c.
34 */
35
36 /*
37 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
38 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
39 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
40 * PSMI 1.5 extensions are supported in Solaris Nevada.
41 * PSMI 1.6 extensions are supported in Solaris Nevada.
42 * PSMI 1.7 extensions are supported in Solaris Nevada.
43 */
44 #define PSMI_1_7
45
46 #include <sys/processor.h>
47 #include <sys/time.h>
48 #include <sys/psm.h>
49 #include <sys/smp_impldefs.h>
50 #include <sys/cram.h>
51 #include <sys/acpi/acpi.h>
52 #include <sys/acpica.h>
53 #include <sys/psm_common.h>
54 #include <sys/apic.h>
55 #include <sys/pit.h>
56 #include <sys/ddi.h>
57 #include <sys/sunddi.h>
58 #include <sys/ddi_impldefs.h>
59 #include <sys/pci.h>
60 #include <sys/promif.h>
61 #include <sys/x86_archext.h>
62 #include <sys/cpc_impl.h>
63 #include <sys/uadmin.h>
64 #include <sys/panic.h>
65 #include <sys/debug.h>
66 #include <sys/archsystm.h>
67 #include <sys/trap.h>
68 #include <sys/machsystm.h>
69 #include <sys/sysmacros.h>
70 #include <sys/cpuvar.h>
71 #include <sys/rm_platter.h>
72 #include <sys/privregs.h>
73 #include <sys/note.h>
74 #include <sys/pci_intr_lib.h>
75 #include <sys/spl.h>
76 #include <sys/clock.h>
77 #include <sys/cyclic.h>
78 #include <sys/dditypes.h>
79 #include <sys/sunddi.h>
80 #include <sys/x_call.h>
81 #include <sys/reboot.h>
82 #include <sys/hpet.h>
83 #include <sys/apic_common.h>
84 #include <sys/apic_timer.h>
85
86 /*
87 * Local Function Prototypes
88 */
89 static void apic_init_intr(void);
90
91 /*
92 * standard MP entries
93 */
94 static int apic_probe(void);
95 static int apic_getclkirq(int ipl);
96 static void apic_init(void);
97 static void apic_picinit(void);
98 static int apic_post_cpu_start(void);
99 static int apic_intr_enter(int ipl, int *vect);
100 static void apic_setspl(int ipl);
101 static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl);
102 static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl);
103 static int apic_disable_intr(processorid_t cpun);
104 static void apic_enable_intr(processorid_t cpun);
105 static int apic_get_ipivect(int ipl, int type);
106 static void apic_post_cyclic_setup(void *arg);
107
108 #define UCHAR_MAX UINT8_MAX
109
110 /*
111 * The following vector assignments influence the value of ipltopri and
112 * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program
113 * idle to 0 and IPL 0 to 0xf to differentiate idle in case
114 * we care to do so in future. Note some IPLs which are rarely used
115 * will share the vector ranges and heavily used IPLs (5 and 6) have
116 * a wide range.
117 *
118 * This array is used to initialize apic_ipls[] (in apic_init()).
119 *
120 * IPL Vector range. as passed to intr_enter
121 * 0 none.
122 * 1,2,3 0x20-0x2f 0x0-0xf
123 * 4 0x30-0x3f 0x10-0x1f
124 * 5 0x40-0x5f 0x20-0x3f
125 * 6 0x60-0x7f 0x40-0x5f
126 * 7,8,9 0x80-0x8f 0x60-0x6f
127 * 10 0x90-0x9f 0x70-0x7f
128 * 11 0xa0-0xaf 0x80-0x8f
129 * ... ...
130 * 15 0xe0-0xef 0xc0-0xcf
131 * 15 0xf0-0xff 0xd0-0xdf
132 */
133 uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = {
134 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15
135 };
136 /*
137 * The ipl of an ISR at vector X is apic_vectortoipl[X>>4]
138 * NOTE that this is vector as passed into intr_enter which is
139 * programmed vector - 0x20 (APIC_BASE_VECT)
140 */
141
142 uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */
143 /* The taskpri to be programmed into apic to mask given ipl */
144
145 /*
146 * Correlation of the hardware vector to the IPL in use, initialized
147 * from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate
148 * to the IPLs in apic_vectortoipl on some systems that share interrupt lines
149 * connected to errata-stricken IOAPICs
150 */
151 uchar_t apic_ipls[APIC_AVAIL_VECTOR];
152
153 /*
154 * Patchable global variables.
155 */
156 int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */
157 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */
158
159 /*
160 * Local static data
161 */
162 static struct psm_ops apic_ops = {
163 apic_probe,
164
165 apic_init,
166 apic_picinit,
167 apic_intr_enter,
168 apic_intr_exit,
169 apic_setspl,
170 apic_addspl,
171 apic_delspl,
172 apic_disable_intr,
173 apic_enable_intr,
174 (int (*)(int))NULL, /* psm_softlvl_to_irq */
175 (void (*)(int))NULL, /* psm_set_softintr */
176
177 apic_set_idlecpu,
178 apic_unset_idlecpu,
179
180 apic_clkinit,
181 apic_getclkirq,
182 (void (*)(void))NULL, /* psm_hrtimeinit */
183 apic_gethrtime,
184
185 apic_get_next_processorid,
186 apic_cpu_start,
187 apic_post_cpu_start,
188 apic_shutdown,
189 apic_get_ipivect,
190 apic_send_ipi,
191
192 (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */
193 (void (*)(int, char *))NULL, /* psm_notify_error */
194 (void (*)(int))NULL, /* psm_notify_func */
195 apic_timer_reprogram,
196 apic_timer_enable,
197 apic_timer_disable,
198 apic_post_cyclic_setup,
199 apic_preshutdown,
200 apic_intr_ops, /* Advanced DDI Interrupt framework */
201 apic_state, /* save, restore apic state for S3 */
202 apic_cpu_ops, /* CPU control interface. */
203
204 apic_get_pir_ipivect,
205 apic_send_pir_ipi,
206 apic_cmci_setup,
207 };
208
209 struct psm_ops *psmops = &apic_ops;
210
211 static struct psm_info apic_psm_info = {
212 PSM_INFO_VER01_7, /* version */
213 PSM_OWN_EXCLUSIVE, /* ownership */
214 (struct psm_ops *)&apic_ops, /* operation */
215 APIC_PCPLUSMP_NAME, /* machine name */
216 "pcplusmp v1.4 compatible",
217 };
218
219 static void *apic_hdlp;
220
221 /* to gather intr data and redistribute */
222 static void apic_redistribute_compute(void);
223
224 /*
225 * This is the loadable module wrapper
226 */
227
228 int
229 _init(void)
230 {
231 if (apic_coarse_hrtime)
232 apic_ops.psm_gethrtime = &apic_gettime;
233 return (psm_mod_init(&apic_hdlp, &apic_psm_info));
234 }
235
236 int
237 _fini(void)
238 {
239 return (psm_mod_fini(&apic_hdlp, &apic_psm_info));
240 }
241
242 int
243 _info(struct modinfo *modinfop)
244 {
245 return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop));
246 }
247
248 static int
249 apic_probe(void)
250 {
251 /* check if apix is initialized */
252 if (apix_enable && apix_loaded())
253 return (PSM_FAILURE);
254
255 /*
256 * Check whether x2APIC mode was activated by BIOS. We don't support
257 * that in pcplusmp as apix normally handles that.
258 */
259 if (apic_local_mode() == LOCAL_X2APIC)
260 return (PSM_FAILURE);
261
262 /* continue using pcplusmp PSM */
263 apix_enable = 0;
264
265 return (apic_probe_common(apic_psm_info.p_mach_idstring));
266 }
267
268 static uchar_t
269 apic_xlate_vector_by_irq(uchar_t irq)
270 {
271 if (apic_irq_table[irq] == NULL)
272 return (0);
273
274 return (apic_irq_table[irq]->airq_vector);
275 }
276
277 void
278 apic_init(void)
279 {
280 int i;
281 int j = 1;
282
283 psm_get_ioapicid = apic_get_ioapicid;
284 psm_get_localapicid = apic_get_localapicid;
285 psm_xlate_vector_by_irq = apic_xlate_vector_by_irq;
286
287 apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */
288 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) {
289 if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) &&
290 (apic_vectortoipl[i + 1] == apic_vectortoipl[i]))
291 /* get to highest vector at the same ipl */
292 continue;
293 for (; j <= apic_vectortoipl[i]; j++) {
294 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) +
295 APIC_BASE_VECT;
296 }
297 }
298 for (; j < MAXIPL + 1; j++)
299 /* fill up any empty ipltopri slots */
300 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT;
301 apic_init_common();
302
303 apic_pir_vect = apic_get_ipivect(XC_CPUPOKE_PIL, -1);
304
305 #if !defined(__amd64)
306 if (cpuid_have_cr8access(CPU))
307 apic_have_32bit_cr8 = 1;
308 #endif
309 }
310
311 static void
312 apic_init_intr(void)
313 {
314 processorid_t cpun = psm_get_cpu_id();
315 uint_t nlvt;
316 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR;
317
318 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL);
319
320 ASSERT(apic_mode == LOCAL_APIC);
321
322 /*
323 * We are running APIC in MMIO mode.
324 */
325 if (apic_flat_model) {
326 apic_reg_ops->apic_write(APIC_FORMAT_REG, APIC_FLAT_MODEL);
327 } else {
328 apic_reg_ops->apic_write(APIC_FORMAT_REG, APIC_CLUSTER_MODEL);
329 }
330
331 apic_reg_ops->apic_write(APIC_DEST_REG, AV_HIGH_ORDER >> cpun);
332
333 if (apic_directed_EOI_supported()) {
334 /*
335 * Setting the 12th bit in the Spurious Interrupt Vector
336 * Register suppresses broadcast EOIs generated by the local
337 * APIC. The suppression of broadcast EOIs happens only when
338 * interrupts are level-triggered.
339 */
340 svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI;
341 }
342
343 /* need to enable APIC before unmasking NMI */
344 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr);
345
346 /*
347 * Presence of an invalid vector with delivery mode AV_FIXED can
348 * cause an error interrupt, even if the entry is masked...so
349 * write a valid vector to LVT entries along with the mask bit
350 */
351
352 /* All APICs have timer and LINT0/1 */
353 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ);
354 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ);
355 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */
356
357 /*
358 * On integrated APICs, the number of LVT entries is
359 * 'Max LVT entry' + 1; on 82489DX's (non-integrated
360 * APICs), nlvt is "3" (LINT0, LINT1, and timer)
361 */
362
363 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) {
364 nlvt = 3;
365 } else {
366 nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) &
367 0xFF) + 1;
368 }
369
370 if (nlvt >= 5) {
371 /* Enable performance counter overflow interrupt */
372
373 if (!is_x86_feature(x86_featureset, X86FSET_MSR))
374 apic_enable_cpcovf_intr = 0;
375 if (apic_enable_cpcovf_intr) {
376 if (apic_cpcovf_vect == 0) {
377 int ipl = APIC_PCINT_IPL;
378 int irq = apic_get_ipivect(ipl, -1);
379
380 ASSERT(irq != -1);
381 apic_cpcovf_vect =
382 apic_irq_table[irq]->airq_vector;
383 ASSERT(apic_cpcovf_vect);
384 (void) add_avintr(NULL, ipl,
385 (avfunc)kcpc_hw_overflow_intr,
386 "apic pcint", irq, NULL, NULL, NULL, NULL);
387 kcpc_hw_overflow_intr_installed = 1;
388 kcpc_hw_enable_cpc_intr =
389 apic_cpcovf_mask_clear;
390 }
391 apic_reg_ops->apic_write(APIC_PCINT_VECT,
392 apic_cpcovf_vect);
393 }
394 }
395
396 if (nlvt >= 6) {
397 /* Only mask TM intr if the BIOS apparently doesn't use it */
398
399 uint32_t lvtval;
400
401 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT);
402 if (((lvtval & AV_MASK) == AV_MASK) ||
403 ((lvtval & AV_DELIV_MODE) != AV_SMI)) {
404 apic_reg_ops->apic_write(APIC_THERM_VECT,
405 AV_MASK|APIC_RESV_IRQ);
406 }
407 }
408
409 /* Enable error interrupt */
410
411 if (nlvt >= 4 && apic_enable_error_intr) {
412 if (apic_errvect == 0) {
413 int ipl = 0xf; /* get highest priority intr */
414 int irq = apic_get_ipivect(ipl, -1);
415
416 ASSERT(irq != -1);
417 apic_errvect = apic_irq_table[irq]->airq_vector;
418 ASSERT(apic_errvect);
419 /*
420 * Not PSMI compliant, but we are going to merge
421 * with ON anyway
422 */
423 (void) add_avintr((void *)NULL, ipl,
424 (avfunc)apic_error_intr, "apic error intr",
425 irq, NULL, NULL, NULL, NULL);
426 }
427 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect);
428 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
429 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
430 }
431
432 /*
433 * Ensure a CMCI interrupt is allocated, regardless of whether it is
434 * enabled or not.
435 */
436 if (apic_cmci_vect == 0) {
437 const int ipl = 0x2;
438 int irq = apic_get_ipivect(ipl, -1);
439
440 ASSERT(irq != -1);
441 apic_cmci_vect = apic_irq_table[irq]->airq_vector;
442 ASSERT(apic_cmci_vect);
443
444 (void) add_avintr(NULL, ipl,
445 (avfunc)cmi_cmci_trap,
446 "apic cmci intr", irq, NULL, NULL, NULL, NULL);
447 }
448 }
449
450 static void
451 apic_picinit(void)
452 {
453 int i, j;
454 uint_t isr;
455
456 /*
457 * Initialize and enable interrupt remapping before apic
458 * hardware initialization
459 */
460 apic_intrmap_init(apic_mode);
461
462 /*
463 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr
464 * bit on without clearing it with EOI. Since softint
465 * uses vector 0x20 to interrupt itself, so softint will
466 * not work on this machine. In order to fix this problem
467 * a check is made to verify all the isr bits are clear.
468 * If not, EOIs are issued to clear the bits.
469 */
470 for (i = 7; i >= 1; i--) {
471 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4));
472 if (isr != 0)
473 for (j = 0; ((j < 32) && (isr != 0)); j++)
474 if (isr & (1 << j)) {
475 apic_reg_ops->apic_write(
476 APIC_EOI_REG, 0);
477 isr &= ~(1 << j);
478 apic_error |= APIC_ERR_BOOT_EOI;
479 }
480 }
481
482 /* set a flag so we know we have run apic_picinit() */
483 apic_picinit_called = 1;
484 LOCK_INIT_CLEAR(&apic_gethrtime_lock);
485 LOCK_INIT_CLEAR(&apic_ioapic_lock);
486 LOCK_INIT_CLEAR(&apic_error_lock);
487 LOCK_INIT_CLEAR(&apic_mode_switch_lock);
488
489 picsetup(); /* initialise the 8259 */
490
491 /* add nmi handler - least priority nmi handler */
492 LOCK_INIT_CLEAR(&apic_nmi_lock);
493
494 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr,
495 "pcplusmp NMI handler", (caddr_t)NULL))
496 cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler");
497
498 /*
499 * Check for directed-EOI capability in the local APIC.
500 */
501 if (apic_directed_EOI_supported() == 1) {
502 apic_set_directed_EOI_handler();
503 }
504
505 apic_init_intr();
506
507 /* enable apic mode if imcr present */
508 if (apic_imcrp) {
509 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT);
510 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC);
511 }
512
513 ioapic_init_intr(IOAPIC_MASK);
514 }
515
516 #ifdef DEBUG
517 void
518 apic_break(void)
519 {
520 }
521 #endif /* DEBUG */
522
523 /*
524 * platform_intr_enter
525 *
526 * Called at the beginning of the interrupt service routine to
527 * mask all level equal to and below the interrupt priority
528 * of the interrupting vector. An EOI should be given to
529 * the interrupt controller to enable other HW interrupts.
530 *
531 * Return -1 for spurious interrupts
532 *
533 */
534 /*ARGSUSED*/
535 static int
536 apic_intr_enter(int ipl, int *vectorp)
537 {
538 uchar_t vector;
539 int nipl;
540 int irq;
541 ulong_t iflag;
542 apic_cpus_info_t *cpu_infop;
543
544 /*
545 * The real vector delivered is (*vectorp + 0x20), but our caller
546 * subtracts 0x20 from the vector before passing it to us.
547 * (That's why APIC_BASE_VECT is 0x20.)
548 */
549 vector = (uchar_t)*vectorp;
550
551 /* if interrupted by the clock, increment apic_nsec_since_boot */
552 if (vector == apic_clkvect) {
553 if (!apic_oneshot) {
554 /* NOTE: this is not MT aware */
555 apic_hrtime_stamp++;
556 apic_nsec_since_boot += apic_nsec_per_intr;
557 apic_hrtime_stamp++;
558 last_count_read = apic_hertz_count;
559 apic_redistribute_compute();
560 }
561
562 /* We will avoid all the book keeping overhead for clock */
563 nipl = apic_ipls[vector];
564
565 *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT];
566
567 apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]);
568 apic_reg_ops->apic_send_eoi(0);
569
570 return (nipl);
571 }
572
573 cpu_infop = &apic_cpus[psm_get_cpu_id()];
574
575 if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) {
576 cpu_infop->aci_spur_cnt++;
577 return (APIC_INT_SPURIOUS);
578 }
579
580 /* Check if the vector we got is really what we need */
581 if (apic_revector_pending) {
582 /*
583 * Disable interrupts for the duration of
584 * the vector translation to prevent a self-race for
585 * the apic_revector_lock. This cannot be done
586 * in apic_xlate_vector because it is recursive and
587 * we want the vector translation to be atomic with
588 * respect to other (higher-priority) interrupts.
589 */
590 iflag = intr_clear();
591 vector = apic_xlate_vector(vector + APIC_BASE_VECT) -
592 APIC_BASE_VECT;
593 intr_restore(iflag);
594 }
595
596 nipl = apic_ipls[vector];
597 *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT];
598
599 apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]);
600
601 cpu_infop->aci_current[nipl] = (uchar_t)irq;
602 cpu_infop->aci_curipl = (uchar_t)nipl;
603 cpu_infop->aci_ISR_in_progress |= 1 << nipl;
604
605 /*
606 * apic_level_intr could have been assimilated into the irq struct.
607 * but, having it as a character array is more efficient in terms of
608 * cache usage. So, we leave it as is.
609 */
610 if (!apic_level_intr[irq]) {
611 apic_reg_ops->apic_send_eoi(0);
612 }
613
614 #ifdef DEBUG
615 APIC_DEBUG_BUF_PUT(vector);
616 APIC_DEBUG_BUF_PUT(irq);
617 APIC_DEBUG_BUF_PUT(nipl);
618 APIC_DEBUG_BUF_PUT(psm_get_cpu_id());
619 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl)))
620 drv_usecwait(apic_stretch_interrupts);
621
622 if (apic_break_on_cpu == psm_get_cpu_id())
623 apic_break();
624 #endif /* DEBUG */
625 return (nipl);
626 }
627
628 void
629 apic_intr_exit(int prev_ipl, int irq)
630 {
631 apic_cpus_info_t *cpu_infop;
632
633 apic_reg_ops->apic_write_task_reg(apic_ipltopri[prev_ipl]);
634
635 cpu_infop = &apic_cpus[psm_get_cpu_id()];
636 if (apic_level_intr[irq])
637 apic_reg_ops->apic_send_eoi(irq);
638 cpu_infop->aci_curipl = (uchar_t)prev_ipl;
639 /* ISR above current pri could not be in progress */
640 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1;
641 }
642
643 intr_exit_fn_t
644 psm_intr_exit_fn(void)
645 {
646 return (apic_intr_exit);
647 }
648
649 /*
650 * Mask all interrupts below or equal to the given IPL.
651 */
652 static void
653 apic_setspl(int ipl)
654 {
655 apic_reg_ops->apic_write_task_reg(apic_ipltopri[ipl]);
656
657 /* interrupts at ipl above this cannot be in progress */
658 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
659 /*
660 * this is a patch fix for the ALR QSMP P5 machine, so that interrupts
661 * have enough time to come in before the priority is raised again
662 * during the idle() loop.
663 */
664 if (apic_setspl_delay)
665 (void) apic_reg_ops->apic_get_pri();
666 }
667
668 /*ARGSUSED*/
669 static int
670 apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl)
671 {
672 return (apic_addspl_common(irqno, ipl, min_ipl, max_ipl));
673 }
674
675 static int
676 apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl)
677 {
678 return (apic_delspl_common(irqno, ipl, min_ipl, max_ipl));
679 }
680
681 static int
682 apic_post_cpu_start(void)
683 {
684 int cpun;
685 static int cpus_started = 1;
686
687 /* We know this CPU + BSP started successfully. */
688 cpus_started++;
689
690 splx(ipltospl(LOCK_LEVEL));
691 apic_init_intr();
692
693 /*
694 * since some systems don't enable the internal cache on the non-boot
695 * cpus, so we have to enable them here
696 */
697 setcr0(getcr0() & ~(CR0_CD | CR0_NW));
698
699 APIC_AV_PENDING_SET();
700
701 /*
702 * We may be booting, or resuming from suspend; aci_status will
703 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the
704 * APIC_CPU_ONLINE flag here rather than setting aci_status completely.
705 */
706 cpun = psm_get_cpu_id();
707 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE;
708
709 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init);
710 return (PSM_SUCCESS);
711 }
712
713 /*
714 * type == -1 indicates it is an internal request. Do not change
715 * resv_vector for these requests
716 */
717 static int
718 apic_get_ipivect(int ipl, int type)
719 {
720 uchar_t vector;
721 int irq;
722
723 if ((irq = apic_allocate_irq(APIC_VECTOR(ipl))) != -1) {
724 if ((vector = apic_allocate_vector(ipl, irq, 1))) {
725 apic_irq_table[irq]->airq_mps_intr_index =
726 RESERVE_INDEX;
727 apic_irq_table[irq]->airq_vector = vector;
728 if (type != -1) {
729 apic_resv_vector[ipl] = vector;
730 }
731 return (irq);
732 }
733 }
734 apic_error |= APIC_ERR_GET_IPIVECT_FAIL;
735 return (-1); /* shouldn't happen */
736 }
737
738 static int
739 apic_getclkirq(int ipl)
740 {
741 int irq;
742
743 if ((irq = apic_get_ipivect(ipl, -1)) == -1)
744 return (-1);
745 /*
746 * Note the vector in apic_clkvect for per clock handling.
747 */
748 apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT;
749 APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n",
750 apic_clkvect));
751 return (irq);
752 }
753
754 /*
755 * Try and disable all interrupts. We just assign interrupts to other
756 * processors based on policy. If any were bound by user request, we
757 * let them continue and return failure. We do not bother to check
758 * for cache affinity while rebinding.
759 */
760
761 static int
762 apic_disable_intr(processorid_t cpun)
763 {
764 int bind_cpu = 0, i, hardbound = 0;
765 apic_irq_t *irq_ptr;
766 ulong_t iflag;
767
768 iflag = intr_clear();
769 lock_set(&apic_ioapic_lock);
770
771 for (i = 0; i <= APIC_MAX_VECTOR; i++) {
772 if (apic_reprogram_info[i].done == B_FALSE) {
773 if (apic_reprogram_info[i].bindcpu == cpun) {
774 /*
775 * CPU is busy -- it's the target of
776 * a pending reprogramming attempt
777 */
778 lock_clear(&apic_ioapic_lock);
779 intr_restore(iflag);
780 return (PSM_FAILURE);
781 }
782 }
783 }
784
785 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE;
786
787 apic_cpus[cpun].aci_curipl = 0;
788
789 i = apic_min_device_irq;
790 for (; i <= apic_max_device_irq; i++) {
791 /*
792 * If there are bound interrupts on this cpu, then
793 * rebind them to other processors.
794 */
795 if ((irq_ptr = apic_irq_table[i]) != NULL) {
796 ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) ||
797 (irq_ptr->airq_temp_cpu == IRQ_UNINIT) ||
798 (apic_cpu_in_range(irq_ptr->airq_temp_cpu)));
799
800 if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) {
801 hardbound = 1;
802 continue;
803 }
804
805 if (irq_ptr->airq_temp_cpu == cpun) {
806 do {
807 bind_cpu =
808 apic_find_cpu(APIC_CPU_INTR_ENABLE);
809 } while (apic_rebind_all(irq_ptr, bind_cpu));
810 }
811 }
812 }
813
814 lock_clear(&apic_ioapic_lock);
815 intr_restore(iflag);
816
817 if (hardbound) {
818 cmn_err(CE_WARN, "Could not disable interrupts on %d"
819 "due to user bound interrupts", cpun);
820 return (PSM_FAILURE);
821 }
822 else
823 return (PSM_SUCCESS);
824 }
825
826 /*
827 * Bind interrupts to the CPU's local APIC.
828 * Interrupts should not be bound to a CPU's local APIC until the CPU
829 * is ready to receive interrupts.
830 */
831 static void
832 apic_enable_intr(processorid_t cpun)
833 {
834 int i;
835 apic_irq_t *irq_ptr;
836 ulong_t iflag;
837
838 iflag = intr_clear();
839 lock_set(&apic_ioapic_lock);
840
841 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE;
842
843 i = apic_min_device_irq;
844 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
845 if ((irq_ptr = apic_irq_table[i]) != NULL) {
846 if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) {
847 (void) apic_rebind_all(irq_ptr,
848 irq_ptr->airq_cpu);
849 }
850 }
851 }
852
853 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND)
854 apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND;
855
856 lock_clear(&apic_ioapic_lock);
857 intr_restore(iflag);
858 }
859
860 /*
861 * If this module needs a periodic handler for the interrupt distribution, it
862 * can be added here. The argument to the periodic handler is not currently
863 * used, but is reserved for future.
864 */
865 static void
866 apic_post_cyclic_setup(void *arg)
867 {
868 _NOTE(ARGUNUSED(arg))
869
870 cyc_handler_t cyh;
871 cyc_time_t cyt;
872
873 /* cpu_lock is held */
874 /* set up a periodic handler for intr redistribution */
875
876 /*
877 * In peridoc mode intr redistribution processing is done in
878 * apic_intr_enter during clk intr processing
879 */
880 if (!apic_oneshot)
881 return;
882
883 /*
884 * Register a periodical handler for the redistribution processing.
885 * Though we would generally prefer to use the DDI interface for
886 * periodic handler invocation, ddi_periodic_add(9F), we are
887 * unfortunately already holding cpu_lock, which ddi_periodic_add will
888 * attempt to take for us. Thus, we add our own cyclic directly:
889 */
890 cyh.cyh_func = (void (*)(void *))apic_redistribute_compute;
891 cyh.cyh_arg = NULL;
892 cyh.cyh_level = CY_LOW_LEVEL;
893
894 cyt.cyt_when = 0;
895 cyt.cyt_interval = apic_redistribute_sample_interval;
896
897 apic_cyclic_id = cyclic_add(&cyh, &cyt);
898 }
899
900 static void
901 apic_redistribute_compute(void)
902 {
903 int i, j, max_busy;
904
905 if (apic_enable_dynamic_migration) {
906 if (++apic_nticks == apic_sample_factor_redistribution) {
907 /*
908 * Time to call apic_intr_redistribute().
909 * reset apic_nticks. This will cause max_busy
910 * to be calculated below and if it is more than
911 * apic_int_busy, we will do the whole thing
912 */
913 apic_nticks = 0;
914 }
915 max_busy = 0;
916 for (i = 0; i < apic_nproc; i++) {
917 if (!apic_cpu_in_range(i))
918 continue;
919
920 /*
921 * Check if curipl is non zero & if ISR is in
922 * progress
923 */
924 if (((j = apic_cpus[i].aci_curipl) != 0) &&
925 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) {
926
927 int irq;
928 apic_cpus[i].aci_busy++;
929 irq = apic_cpus[i].aci_current[j];
930 apic_irq_table[irq]->airq_busy++;
931 }
932
933 if (!apic_nticks &&
934 (apic_cpus[i].aci_busy > max_busy))
935 max_busy = apic_cpus[i].aci_busy;
936 }
937 if (!apic_nticks) {
938 if (max_busy > apic_int_busy_mark) {
939 /*
940 * We could make the following check be
941 * skipped > 1 in which case, we get a
942 * redistribution at half the busy mark (due to
943 * double interval). Need to be able to collect
944 * more empirical data to decide if that is a
945 * good strategy. Punt for now.
946 */
947 if (apic_skipped_redistribute) {
948 apic_cleanup_busy();
949 apic_skipped_redistribute = 0;
950 } else {
951 apic_intr_redistribute();
952 }
953 } else
954 apic_skipped_redistribute++;
955 }
956 }
957 }
958
959
960 /*
961 * The following functions are in the platform specific file so that they
962 * can be different functions depending on whether we are running on
963 * bare metal or a hypervisor.
964 */
965
966 /*
967 * Check to make sure there are enough irq slots
968 */
969 int
970 apic_check_free_irqs(int count)
971 {
972 int i, avail;
973
974 avail = 0;
975 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
976 if ((apic_irq_table[i] == NULL) ||
977 apic_irq_table[i]->airq_mps_intr_index == FREE_INDEX) {
978 if (++avail >= count)
979 return (PSM_SUCCESS);
980 }
981 }
982 return (PSM_FAILURE);
983 }
984
985 /*
986 * This function allocates "count" MSI vector(s) for the given "dip/pri/type"
987 */
988 int
989 apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, int pri,
990 int behavior)
991 {
992 int rcount, i;
993 uchar_t start, irqno;
994 uint32_t cpu = 0;
995 major_t major;
996 apic_irq_t *irqptr;
997
998 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: dip=0x%p "
999 "inum=0x%x pri=0x%x count=0x%x behavior=%d\n",
1000 (void *)dip, inum, pri, count, behavior));
1001
1002 if (count > 1) {
1003 if (behavior == DDI_INTR_ALLOC_STRICT &&
1004 apic_multi_msi_enable == 0)
1005 return (0);
1006 if (apic_multi_msi_enable == 0)
1007 count = 1;
1008 }
1009
1010 if ((rcount = apic_navail_vector(dip, pri)) > count)
1011 rcount = count;
1012 else if (rcount == 0 || (rcount < count &&
1013 behavior == DDI_INTR_ALLOC_STRICT))
1014 return (0);
1015
1016 /* if not ISP2, then round it down */
1017 if (!ISP2(rcount))
1018 rcount = 1 << (highbit(rcount) - 1);
1019
1020 mutex_enter(&airq_mutex);
1021
1022 for (start = 0; rcount > 0; rcount >>= 1) {
1023 if ((start = apic_find_multi_vectors(pri, rcount)) != 0 ||
1024 behavior == DDI_INTR_ALLOC_STRICT)
1025 break;
1026 }
1027
1028 if (start == 0) {
1029 /* no vector available */
1030 mutex_exit(&airq_mutex);
1031 return (0);
1032 }
1033
1034 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1035 /* not enough free irq slots available */
1036 mutex_exit(&airq_mutex);
1037 return (0);
1038 }
1039
1040 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1041 for (i = 0; i < rcount; i++) {
1042 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1043 (uchar_t)-1) {
1044 /*
1045 * shouldn't happen because of the
1046 * apic_check_free_irqs() check earlier
1047 */
1048 mutex_exit(&airq_mutex);
1049 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1050 "apic_allocate_irq failed\n"));
1051 return (i);
1052 }
1053 apic_max_device_irq = max(irqno, apic_max_device_irq);
1054 apic_min_device_irq = min(irqno, apic_min_device_irq);
1055 irqptr = apic_irq_table[irqno];
1056 #ifdef DEBUG
1057 if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ)
1058 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1059 "apic_vector_to_irq is not APIC_RESV_IRQ\n"));
1060 #endif
1061 apic_vector_to_irq[start + i] = (uchar_t)irqno;
1062
1063 irqptr->airq_vector = (uchar_t)(start + i);
1064 irqptr->airq_ioapicindex = (uchar_t)inum; /* start */
1065 irqptr->airq_intin_no = (uchar_t)rcount;
1066 ASSERT(pri >= 0 && pri <= UCHAR_MAX);
1067 irqptr->airq_ipl = (uchar_t)pri;
1068 irqptr->airq_vector = start + i;
1069 irqptr->airq_origirq = (uchar_t)(inum + i);
1070 irqptr->airq_share_id = 0;
1071 irqptr->airq_mps_intr_index = MSI_INDEX;
1072 irqptr->airq_dip = dip;
1073 irqptr->airq_major = major;
1074 if (i == 0) /* they all bound to the same cpu */
1075 cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno,
1076 0xff, 0xff);
1077 else
1078 irqptr->airq_cpu = cpu;
1079 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: irq=0x%x "
1080 "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno,
1081 (void *)irqptr->airq_dip, irqptr->airq_vector,
1082 irqptr->airq_origirq, pri));
1083 }
1084 mutex_exit(&airq_mutex);
1085 return (rcount);
1086 }
1087
1088 /*
1089 * This function allocates "count" MSI-X vector(s) for the given "dip/pri/type"
1090 */
1091 int
1092 apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, int pri,
1093 int behavior)
1094 {
1095 int rcount, i;
1096 major_t major;
1097
1098 mutex_enter(&airq_mutex);
1099
1100 if ((rcount = apic_navail_vector(dip, pri)) > count)
1101 rcount = count;
1102 else if (rcount == 0 || (rcount < count &&
1103 behavior == DDI_INTR_ALLOC_STRICT)) {
1104 rcount = 0;
1105 goto out;
1106 }
1107
1108 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1109 /* not enough free irq slots available */
1110 rcount = 0;
1111 goto out;
1112 }
1113
1114 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1115 for (i = 0; i < rcount; i++) {
1116 uchar_t vector, irqno;
1117 apic_irq_t *irqptr;
1118
1119 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1120 (uchar_t)-1) {
1121 /*
1122 * shouldn't happen because of the
1123 * apic_check_free_irqs() check earlier
1124 */
1125 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1126 "apic_allocate_irq failed\n"));
1127 rcount = i;
1128 goto out;
1129 }
1130 if ((vector = apic_allocate_vector(pri, irqno, 1)) == 0) {
1131 /*
1132 * shouldn't happen because of the
1133 * apic_navail_vector() call earlier
1134 */
1135 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1136 "apic_allocate_vector failed\n"));
1137 rcount = i;
1138 goto out;
1139 }
1140 apic_max_device_irq = max(irqno, apic_max_device_irq);
1141 apic_min_device_irq = min(irqno, apic_min_device_irq);
1142 irqptr = apic_irq_table[irqno];
1143 irqptr->airq_vector = (uchar_t)vector;
1144 ASSERT(pri >= 0 && pri <= UCHAR_MAX);
1145 irqptr->airq_ipl = (uchar_t)pri;
1146 irqptr->airq_origirq = (uchar_t)(inum + i);
1147 irqptr->airq_share_id = 0;
1148 irqptr->airq_mps_intr_index = MSIX_INDEX;
1149 irqptr->airq_dip = dip;
1150 irqptr->airq_major = major;
1151 irqptr->airq_cpu = apic_bind_intr(dip, irqno, 0xff, 0xff);
1152 }
1153 out:
1154 mutex_exit(&airq_mutex);
1155 return (rcount);
1156 }
1157
1158 /*
1159 * Allocate a free vector for irq at ipl. Takes care of merging of multiple
1160 * IPLs into a single APIC level as well as stretching some IPLs onto multiple
1161 * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority
1162 * requests and allocated only when pri is set.
1163 */
1164 uchar_t
1165 apic_allocate_vector(int ipl, int irq, int pri)
1166 {
1167 int lowest, highest, i;
1168
1169 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK;
1170 lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL;
1171
1172 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */
1173 lowest -= APIC_VECTOR_PER_IPL;
1174
1175 #ifdef DEBUG
1176 if (apic_restrict_vector) /* for testing shared interrupt logic */
1177 highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS;
1178 #endif /* DEBUG */
1179 if (pri == 0)
1180 highest -= APIC_HI_PRI_VECTS;
1181
1182 for (i = lowest; i <= highest; i++) {
1183 if (APIC_CHECK_RESERVE_VECTORS(i))
1184 continue;
1185 if (apic_vector_to_irq[i] == APIC_RESV_IRQ) {
1186 apic_vector_to_irq[i] = (uchar_t)irq;
1187 ASSERT(i >= 0 && i <= UCHAR_MAX);
1188 return ((uchar_t)i);
1189 }
1190 }
1191
1192 return (0);
1193 }
1194
1195 /* Mark vector as not being used by any irq */
1196 void
1197 apic_free_vector(uchar_t vector)
1198 {
1199 apic_vector_to_irq[vector] = APIC_RESV_IRQ;
1200 }
1201
1202 /*
1203 * Call rebind to do the actual programming.
1204 * Must be called with interrupts disabled and apic_ioapic_lock held
1205 * 'p' is polymorphic -- if this function is called to process a deferred
1206 * reprogramming, p is of type 'struct ioapic_reprogram_data *', from which
1207 * the irq pointer is retrieved. If not doing deferred reprogramming,
1208 * p is of the type 'apic_irq_t *'.
1209 *
1210 * apic_ioapic_lock must be held across this call, as it protects apic_rebind
1211 * and it protects apic_get_next_bind_cpu() from a race in which a CPU can be
1212 * taken offline after a cpu is selected, but before apic_rebind is called to
1213 * bind interrupts to it.
1214 */
1215 int
1216 apic_setup_io_intr(void *p, int irq, boolean_t deferred)
1217 {
1218 apic_irq_t *irqptr;
1219 struct ioapic_reprogram_data *drep = NULL;
1220 int rv;
1221
1222 if (deferred) {
1223 drep = (struct ioapic_reprogram_data *)p;
1224 ASSERT(drep != NULL);
1225 irqptr = drep->irqp;
1226 } else
1227 irqptr = (apic_irq_t *)p;
1228
1229 ASSERT(irqptr != NULL);
1230
1231 rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, drep);
1232 if (rv) {
1233 /*
1234 * CPU is not up or interrupts are disabled. Fall back to
1235 * the first available CPU
1236 */
1237 rv = apic_rebind(irqptr, apic_find_cpu(APIC_CPU_INTR_ENABLE),
1238 drep);
1239 }
1240
1241 return (rv);
1242 }
1243
1244
1245 uchar_t
1246 apic_modify_vector(uchar_t vector, int irq)
1247 {
1248 apic_vector_to_irq[vector] = (uchar_t)irq;
1249 return (vector);
1250 }
1251
1252 char *
1253 apic_get_apic_type(void)
1254 {
1255 return (apic_psm_info.p_mach_idstring);
1256 }
1257
1258 void
1259 apic_switch_ipi_callback(boolean_t enter)
1260 {
1261 ASSERT(enter == B_TRUE);
1262 }
1263
1264 int
1265 apic_detect_x2apic(void)
1266 {
1267 return (0);
1268 }
1269
1270 void
1271 apic_enable_x2apic(void)
1272 {
1273 cmn_err(CE_PANIC, "apic_enable_x2apic() called in pcplusmp");
1274 }
1275
1276 void
1277 x2apic_update_psm(void)
1278 {
1279 cmn_err(CE_PANIC, "x2apic_update_psm() called in pcplusmp");
1280 }