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10886 smatch debug macro cleanup in usr/src/uts
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--- old/usr/src/uts/common/io/rwn/rt2860.c
+++ new/usr/src/uts/common/io/rwn/rt2860.c
1 1 /*
2 2 * Copyright 2017 Gary Mills
3 3 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
4 4 * Use is subject to license terms.
5 - * Copyright (c) 2018, Joyent, Inc.
5 + * Copyright 2019 Joyent, Inc.
6 6 */
7 7
8 8 /*
9 9 * Copyright (c) 2007, 2008
10 10 * Damien Bergamini <damien.bergamini@free.fr>
11 11 *
12 12 * Permission to use, copy, modify, and distribute this software for any
13 13 * purpose with or without fee is hereby granted, provided that the above
14 14 * copyright notice and this permission notice appear in all copies.
15 15 *
16 16 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
17 17 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
18 18 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
19 19 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
20 20 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
21 21 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
22 22 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 23 */
24 24
25 25 /*
26 26 * Ralink Technology RT2860 chipset driver
27 27 * http://www.ralinktech.com/
28 28 */
29 29
30 30 #include <sys/types.h>
31 31 #include <sys/byteorder.h>
32 32 #include <sys/conf.h>
33 33 #include <sys/cmn_err.h>
34 34 #include <sys/stat.h>
35 35 #include <sys/ddi.h>
36 36 #include <sys/sunddi.h>
37 37 #include <sys/strsubr.h>
38 38 #include <inet/common.h>
39 39 #include <sys/note.h>
40 40 #include <sys/stream.h>
41 41 #include <sys/strsun.h>
42 42 #include <sys/modctl.h>
43 43 #include <sys/devops.h>
44 44 #include <sys/mac_provider.h>
45 45 #include <sys/mac_wifi.h>
46 46 #include <sys/net80211.h>
47 47 #include <sys/net80211_proto.h>
48 48 #include <sys/varargs.h>
49 49 #include <sys/pci.h>
50 50 #include <sys/crypto/common.h>
51 51 #include <sys/crypto/api.h>
52 52 #include <inet/wifi_ioctl.h>
53 53
54 54 #include "rt2860_reg.h"
55 55 #include "rt2860_var.h"
56 56
57 57 #define RT2860_DBG_80211 (1 << 0)
58 58 #define RT2860_DBG_DMA (1 << 1)
59 59 #define RT2860_DBG_EEPROM (1 << 2)
60 60 #define RT2860_DBG_FW (1 << 3)
61 61 #define RT2860_DBG_HW (1 << 4)
62 62 #define RT2860_DBG_INTR (1 << 5)
63 63 #define RT2860_DBG_RX (1 << 6)
64 64 #define RT2860_DBG_SCAN (1 << 7)
65 65 #define RT2860_DBG_TX (1 << 8)
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66 66 #define RT2860_DBG_RADIO (1 << 9)
67 67 #define RT2860_DBG_RESUME (1 << 10)
68 68 #define RT2860_DBG_MSG (1 << 11)
69 69
70 70 uint32_t rt2860_dbg_flags = 0x0;
71 71
72 72 #ifdef DEBUG
73 73 #define RWN_DEBUG \
74 74 rt2860_debug
75 75 #else
76 -#define RWN_DEBUG
76 +#define RWN_DEBUG(...) (void)(0)
77 77 #endif
78 78
79 79 static void *rt2860_soft_state_p = NULL;
80 80 static uint8_t rt2860_fw_bin [] = {
81 81 #include "fw-rt2860/rt2860.ucode"
82 82 };
83 83
84 84 static const struct ieee80211_rateset rt2860_rateset_11b =
85 85 { 4, { 2, 4, 11, 22 } };
86 86
87 87 static const struct ieee80211_rateset rt2860_rateset_11g =
88 88 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
89 89
90 90 static const struct {
91 91 uint32_t reg;
92 92 uint32_t val;
93 93 } rt2860_def_mac[] = {
94 94 RT2860_DEF_MAC
95 95 };
96 96
97 97 static const struct {
98 98 uint8_t reg;
99 99 uint8_t val;
100 100 } rt2860_def_bbp[] = {
101 101 RT2860_DEF_BBP
102 102 };
103 103
104 104 static const struct rfprog {
105 105 uint8_t chan;
106 106 uint32_t r1, r2, r3, r4;
107 107 } rt2860_rf2850[] = {
108 108 RT2860_RF2850
109 109 };
110 110
111 111 /*
112 112 * PIO access attributes for registers
113 113 */
114 114 static ddi_device_acc_attr_t rwn_csr_accattr = {
115 115 DDI_DEVICE_ATTR_V0,
116 116 DDI_STRUCTURE_LE_ACC,
117 117 DDI_STRICTORDER_ACC
118 118 };
119 119
120 120 /*
121 121 * DMA access attributes for descriptors: NOT to be byte swapped.
122 122 */
123 123 static ddi_device_acc_attr_t rt2860_desc_accattr = {
124 124 DDI_DEVICE_ATTR_V0,
125 125 DDI_STRUCTURE_LE_ACC,
126 126 DDI_STRICTORDER_ACC
127 127 };
128 128
129 129 static ddi_device_acc_attr_t rt2860_buf_accattr = {
130 130 DDI_DEVICE_ATTR_V0,
131 131 DDI_NEVERSWAP_ACC,
132 132 DDI_STRICTORDER_ACC,
133 133 DDI_DEFAULT_ACC
134 134 };
135 135
136 136 /*
137 137 * Describes the chip's DMA engine
138 138 */
139 139 static ddi_dma_attr_t rt2860_dma_attr = {
140 140 DMA_ATTR_V0, /* dma_attr version */
141 141 0x0, /* dma_attr_addr_lo */
142 142 0xffffffffU, /* dma_attr_addr_hi */
143 143 0xffffffffU, /* dma_attr_count_max */
144 144 16, /* dma_attr_align */
145 145 0x00000fff, /* dma_attr_burstsizes */
146 146 1, /* dma_attr_minxfer */
147 147 0xffffffffU, /* dma_attr_maxxfer */
148 148 0xffffffffU, /* dma_attr_seg */
149 149 1, /* dma_attr_sgllen */
150 150 1, /* dma_attr_granular */
151 151 0 /* dma_attr_flags */
152 152 };
153 153
154 154 static uint16_t rt2860_eeprom_read(struct rt2860_softc *, uint8_t);
155 155 static int rt2860_read_eeprom(struct rt2860_softc *);
156 156 const char *rt2860_get_rf(uint8_t);
157 157 static int rt2860_alloc_dma_mem(dev_info_t *, ddi_dma_attr_t *, size_t,
158 158 ddi_device_acc_attr_t *, uint_t, uint_t, struct dma_area *);
159 159 static void rt2860_free_dma_mem(struct dma_area *);
160 160 static int rt2860_alloc_tx_ring(struct rt2860_softc *,
161 161 struct rt2860_tx_ring *);
162 162 static void rt2860_free_tx_ring(struct rt2860_softc *,
163 163 struct rt2860_tx_ring *);
164 164 static int rt2860_alloc_rx_ring(struct rt2860_softc *,
165 165 struct rt2860_rx_ring *);
166 166 static void rt2860_free_rx_ring(struct rt2860_softc *,
167 167 struct rt2860_rx_ring *);
168 168 static int rt2860_alloc_tx_pool(struct rt2860_softc *);
169 169 static void rt2860_free_tx_pool(struct rt2860_softc *);
170 170 static uint16_t rt2860_txtime(int, int, uint32_t);
171 171 static int rt2860_ack_rate(struct ieee80211com *, int);
172 172 static int rt2860_send(ieee80211com_t *, mblk_t *, uint8_t);
173 173 static uint8_t rt2860_maxrssi_chain(struct rt2860_softc *,
174 174 const struct rt2860_rxwi *);
175 175 static void rt2860_drain_stats_fifo(struct rt2860_softc *);
176 176 static void rt2860_tx_intr(struct rt2860_softc *, int);
177 177 static void rt2860_rx_intr(struct rt2860_softc *);
178 178 static uint_t rt2860_softintr(caddr_t);
179 179 static uint_t rt2860_intr(caddr_t);
180 180 static void rt2860_set_region_4(struct rt2860_softc *,
181 181 uint32_t, uint32_t, int);
182 182 static int rt2860_load_microcode(struct rt2860_softc *);
183 183 static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *);
184 184 static int rt2860_bbp_init(struct rt2860_softc *);
185 185 static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t);
186 186 static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t);
187 187 static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t);
188 188 static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t);
189 189 static void rt2860_select_chan_group(struct rt2860_softc *, int);
190 190 static void rt2860_set_chan(struct rt2860_softc *,
191 191 struct ieee80211_channel *);
192 192 static void rt2860_updateprot(struct ieee80211com *);
193 193 static void rt2860_set_leds(struct rt2860_softc *, uint16_t);
194 194 static void rt2860_next_scan(void *);
195 195 static void rt2860_iter_func(void *, struct ieee80211_node *);
196 196 static void rt2860_updateslot(struct rt2860_softc *);
197 197 static uint8_t rt2860_rate2mcs(uint8_t);
198 198 static void rt2860_enable_mrr(struct rt2860_softc *);
199 199 static void rt2860_set_txpreamble(struct rt2860_softc *);
200 200 static void rt2860_set_basicrates(struct rt2860_softc *);
201 201 static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *);
202 202 static void rt2860_amrr_node_init(const struct rt2860_amrr *,
203 203 struct rt2860_amrr_node *);
204 204 static void rt2860_amrr_choose(struct rt2860_amrr *,
205 205 struct ieee80211_node *, struct rt2860_amrr_node *);
206 206 static void rt2860_newassoc(struct ieee80211com *, struct ieee80211_node *,
207 207 int);
208 208 static void rt2860_enable_tsf_sync(struct rt2860_softc *);
209 209 static int rt2860_newstate(struct ieee80211com *,
210 210 enum ieee80211_state, int);
211 211 static int rt2860_init(struct rt2860_softc *);
212 212 static void rt2860_stop(struct rt2860_softc *);
213 213 static int rt2860_quiesce(dev_info_t *t);
214 214
215 215 /*
216 216 * device operations
217 217 */
218 218 static int rt2860_attach(dev_info_t *, ddi_attach_cmd_t);
219 219 static int rt2860_detach(dev_info_t *, ddi_detach_cmd_t);
220 220
221 221 /*
222 222 * Module Loading Data & Entry Points
223 223 */
224 224 DDI_DEFINE_STREAM_OPS(rwn_dev_ops, nulldev, nulldev, rt2860_attach,
225 225 rt2860_detach, nodev, NULL, D_MP, NULL, rt2860_quiesce);
226 226
227 227 static struct modldrv rwn_modldrv = {
228 228 &mod_driverops, /* Type of module. This one is a driver */
229 229 "Ralink RT2700/2800 driver v1.2", /* short description */
230 230 &rwn_dev_ops /* driver specific ops */
231 231 };
232 232
233 233 static struct modlinkage modlinkage = {
234 234 MODREV_1,
235 235 (void *)&rwn_modldrv,
236 236 NULL
237 237 };
238 238
239 239 static int rt2860_m_stat(void *, uint_t, uint64_t *);
240 240 static int rt2860_m_start(void *);
241 241 static void rt2860_m_stop(void *);
242 242 static int rt2860_m_promisc(void *, boolean_t);
243 243 static int rt2860_m_multicst(void *, boolean_t, const uint8_t *);
244 244 static int rt2860_m_unicst(void *, const uint8_t *);
245 245 static mblk_t *rt2860_m_tx(void *, mblk_t *);
246 246 static void rt2860_m_ioctl(void *, queue_t *, mblk_t *);
247 247 static int rt2860_m_setprop(void *arg, const char *pr_name,
248 248 mac_prop_id_t wldp_pr_num,
249 249 uint_t wldp_length, const void *wldp_buf);
250 250 static void rt2860_m_propinfo(void *arg, const char *pr_name,
251 251 mac_prop_id_t wldp_pr_num, mac_prop_info_handle_t prh);
252 252 static int rt2860_m_getprop(void *arg, const char *pr_name,
253 253 mac_prop_id_t wldp_pr_num, uint_t wldp_length,
254 254 void *wldp_buf);
255 255
256 256 static mac_callbacks_t rt2860_m_callbacks = {
257 257 MC_IOCTL | MC_SETPROP | MC_GETPROP | MC_PROPINFO,
258 258 rt2860_m_stat,
259 259 rt2860_m_start,
260 260 rt2860_m_stop,
261 261 rt2860_m_promisc,
262 262 rt2860_m_multicst,
263 263 rt2860_m_unicst,
264 264 rt2860_m_tx,
265 265 NULL,
266 266 rt2860_m_ioctl,
267 267 NULL,
268 268 NULL,
269 269 NULL,
270 270 rt2860_m_setprop,
271 271 rt2860_m_getprop,
272 272 rt2860_m_propinfo
273 273 };
274 274
275 275 #ifdef DEBUG
276 276 void
277 277 rt2860_debug(uint32_t dbg_flags, const int8_t *fmt, ...)
278 278 {
279 279 va_list args;
280 280
281 281 if (dbg_flags & rt2860_dbg_flags) {
282 282 va_start(args, fmt);
283 283 vcmn_err(CE_CONT, fmt, args);
284 284 va_end(args);
285 285 }
286 286 }
287 287 #endif
288 288
289 289 const char *
290 290 rt2860_get_rf(uint8_t rev)
291 291 {
292 292 switch (rev) {
293 293 case RT2860_RF_2820: return "RT2820";
294 294 case RT2860_RF_2850: return "RT2850";
295 295 case RT2860_RF_2720: return "RT2720";
296 296 case RT2860_RF_2750: return "RT2750";
297 297 default: return "unknown";
298 298 }
299 299 }
300 300
301 301 /*
302 302 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46,
303 303 * 93C66 or 93C86).
304 304 */
305 305 static uint16_t
306 306 rt2860_eeprom_read(struct rt2860_softc *sc, uint8_t addr)
307 307 {
308 308 int n;
309 309 uint16_t val;
310 310 uint32_t tmp;
311 311
312 312 /* clock C once before the first command */
313 313 RT2860_EEPROM_CTL(sc, 0);
314 314
315 315 RT2860_EEPROM_CTL(sc, RT2860_S);
316 316 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
317 317 RT2860_EEPROM_CTL(sc, RT2860_S);
318 318
319 319 /* write start bit (1) */
320 320 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D);
321 321 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C);
322 322
323 323 /* write READ opcode (10) */
324 324 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D);
325 325 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C);
326 326 RT2860_EEPROM_CTL(sc, RT2860_S);
327 327 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
328 328
329 329 /* write address (A5-A0 or A7-A0) */
330 330 n = ((RT2860_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7;
331 331 for (; n >= 0; n--) {
332 332 RT2860_EEPROM_CTL(sc, RT2860_S |
333 333 (((addr >> n) & 1) << RT2860_SHIFT_D));
334 334 RT2860_EEPROM_CTL(sc, RT2860_S |
335 335 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C);
336 336 }
337 337
338 338 RT2860_EEPROM_CTL(sc, RT2860_S);
339 339
340 340 /* read data Q15-Q0 */
341 341 val = 0;
342 342 for (n = 15; n >= 0; n--) {
343 343 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
344 344 tmp = RT2860_READ(sc, RT2860_PCI_EECTRL);
345 345 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n;
346 346 RT2860_EEPROM_CTL(sc, RT2860_S);
347 347 }
348 348
349 349 RT2860_EEPROM_CTL(sc, 0);
350 350
351 351 /* clear Chip Select and clock C */
352 352 RT2860_EEPROM_CTL(sc, RT2860_S);
353 353 RT2860_EEPROM_CTL(sc, 0);
354 354 RT2860_EEPROM_CTL(sc, RT2860_C);
355 355
356 356 return (val);
357 357 }
358 358
359 359 /*
360 360 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word.
361 361 * Used to adjust per-rate Tx power registers.
362 362 */
363 363 static inline uint32_t
364 364 b4inc(uint32_t b32, int8_t delta)
365 365 {
366 366 int8_t i, b4;
367 367
368 368 for (i = 0; i < 8; i++) {
369 369 b4 = b32 & 0xf;
370 370 b4 += delta;
371 371 if (b4 < 0)
372 372 b4 = 0;
373 373 else if (b4 > 0xf)
374 374 b4 = 0xf;
375 375 b32 = b32 >> 4 | b4 << 28;
376 376 }
377 377 return (b32);
378 378 }
379 379
380 380 static int
381 381 rt2860_read_eeprom(struct rt2860_softc *sc)
382 382 {
383 383 struct ieee80211com *ic = &sc->sc_ic;
384 384 int ridx, ant, i;
385 385 int8_t delta_2ghz, delta_5ghz;
386 386 uint16_t val;
387 387
388 388 /* read EEPROM version */
389 389 val = rt2860_eeprom_read(sc, RT2860_EEPROM_VERSION);
390 390 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
391 391 "EEPROM rev=%d, FAE=%d\n",
392 392 val & 0xff, val >> 8);
393 393
394 394 /* read MAC address */
395 395 val = rt2860_eeprom_read(sc, RT2860_EEPROM_MAC01);
396 396 ic->ic_macaddr[0] = val & 0xff;
397 397 ic->ic_macaddr[1] = val >> 8;
398 398 val = rt2860_eeprom_read(sc, RT2860_EEPROM_MAC23);
399 399 ic->ic_macaddr[2] = val & 0xff;
400 400 ic->ic_macaddr[3] = val >> 8;
401 401 val = rt2860_eeprom_read(sc, RT2860_EEPROM_MAC45);
402 402 ic->ic_macaddr[4] = val & 0xff;
403 403 ic->ic_macaddr[5] = val >> 8;
404 404 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
405 405 "MAC address is: %x:%x:%x:%x:%x:%x\n",
406 406 ic->ic_macaddr[0], ic->ic_macaddr[1],
407 407 ic->ic_macaddr[2], ic->ic_macaddr[3],
408 408 ic->ic_macaddr[4], ic->ic_macaddr[5]);
409 409
410 410 /* read country code */
411 411 val = rt2860_eeprom_read(sc, RT2860_EEPROM_COUNTRY);
412 412 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
413 413 "EEPROM region code=0x%04x\n", val);
414 414
415 415 /* read default BBP settings */
416 416 for (i = 0; i < 8; i++) {
417 417 val = rt2860_eeprom_read(sc, RT2860_EEPROM_BBP_BASE + i);
418 418 sc->bbp[i].val = val & 0xff;
419 419 sc->bbp[i].reg = val >> 8;
420 420 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
421 421 "BBP%d=0x%02x\n",
422 422 sc->bbp[i].reg, sc->bbp[i].val);
423 423 }
424 424
425 425 /* read RF frequency offset from EEPROM */
426 426 val = rt2860_eeprom_read(sc, RT2860_EEPROM_FREQ_LEDS);
427 427 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0;
428 428 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
429 429 "EEPROM freq offset %d\n", sc->freq & 0xff);
430 430
431 431 if ((sc->leds = val >> 8) != 0xff) {
432 432 /* read LEDs operating mode */
433 433 sc->led[0] = rt2860_eeprom_read(sc, RT2860_EEPROM_LED1);
434 434 sc->led[1] = rt2860_eeprom_read(sc, RT2860_EEPROM_LED2);
435 435 sc->led[2] = rt2860_eeprom_read(sc, RT2860_EEPROM_LED3);
436 436 } else {
437 437 /* broken EEPROM, use default settings */
438 438 sc->leds = 0x01;
439 439 sc->led[0] = 0x5555;
440 440 sc->led[1] = 0x2221;
441 441 sc->led[2] = 0xa9f8;
442 442 }
443 443 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
444 444 "EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n",
445 445 sc->leds, sc->led[0], sc->led[1], sc->led[2]);
446 446
447 447 /* read RF information */
448 448 val = rt2860_eeprom_read(sc, RT2860_EEPROM_ANTENNA);
449 449 if (val == 0xffff) {
450 450 /* broken EEPROM, default to RF2820 1T2R */
451 451 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
452 452 "invalid EEPROM antenna info, using default\n");
453 453 sc->rf_rev = RT2860_RF_2820;
454 454 sc->ntxchains = 1;
455 455 sc->nrxchains = 2;
456 456 } else {
457 457 sc->rf_rev = (val >> 8) & 0xf;
458 458 sc->ntxchains = (val >> 4) & 0xf;
459 459 sc->nrxchains = val & 0xf;
460 460 }
461 461 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
462 462 "EEPROM RF rev=0x%02x chains=%dT%dR\n",
463 463 sc->rf_rev, sc->ntxchains, sc->nrxchains);
464 464
465 465 /* check if RF supports automatic Tx access gain control */
466 466 val = rt2860_eeprom_read(sc, RT2860_EEPROM_CONFIG);
467 467 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
468 468 "EEPROM CFG 0x%04x\n", val);
469 469 if ((val & 0xff) != 0xff)
470 470 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */;
471 471
472 472 if (sc->sc_flags & RT2860_ADVANCED_PS) {
473 473 /* read PCIe power save level */
474 474 val = rt2860_eeprom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL);
475 475 if ((val & 0xff) != 0xff) {
476 476 sc->pslevel = val & 0x3;
477 477 val = rt2860_eeprom_read(sc, RT2860_EEPROM_REV);
478 478 if (val >> 8 != 0x92 || !(val & 0x80))
479 479 sc->pslevel = MIN(sc->pslevel, 1);
480 480 RWN_DEBUG(RT2860_DBG_EEPROM,
481 481 "rwn: rt2860_read_eeprom(): "
482 482 "EEPROM PCIe PS Level=%d\n",
483 483 sc->pslevel);
484 484 }
485 485 }
486 486 /* read power settings for 2GHz channels */
487 487 for (i = 0; i < 14; i += 2) {
488 488 val = rt2860_eeprom_read(sc,
489 489 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2);
490 490 sc->txpow1[i + 0] = (int8_t)(val & 0xff);
491 491 sc->txpow1[i + 1] = (int8_t)(val >> 8);
492 492
493 493 val = rt2860_eeprom_read(sc,
494 494 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2);
495 495 sc->txpow2[i + 0] = (int8_t)(val & 0xff);
496 496 sc->txpow2[i + 1] = (int8_t)(val >> 8);
497 497 }
498 498 /* fix broken Tx power entries */
499 499 for (i = 0; i < 14; i++) {
500 500 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31)
501 501 sc->txpow1[i] = 5;
502 502 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31)
503 503 sc->txpow2[i] = 5;
504 504 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
505 505 "chan %d: power1=%d, power2=%d\n",
506 506 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i]);
507 507 }
508 508 /* read power settings for 5GHz channels */
509 509 for (i = 0; i < 36; i += 2) {
510 510 val = rt2860_eeprom_read(sc,
511 511 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2);
512 512 sc->txpow1[i + 14] = (int8_t)(val & 0xff);
513 513 sc->txpow1[i + 15] = (int8_t)(val >> 8);
514 514
515 515 val = rt2860_eeprom_read(sc,
516 516 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2);
517 517 sc->txpow2[i + 14] = (int8_t)(val & 0xff);
518 518 sc->txpow2[i + 15] = (int8_t)(val >> 8);
519 519 }
520 520 /* fix broken Tx power entries */
521 521 for (i = 0; i < 35; i++) {
522 522 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15)
523 523 sc->txpow1[14 + i] = 5;
524 524 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15)
525 525 sc->txpow2[14 + i] = 5;
526 526 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
527 527 "chan %d: power1=%d, power2=%d\n",
528 528 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i],
529 529 sc->txpow2[14 + i]);
530 530 }
531 531
532 532 /* read Tx power compensation for each Tx rate */
533 533 val = rt2860_eeprom_read(sc, RT2860_EEPROM_DELTAPWR);
534 534 delta_2ghz = delta_5ghz = 0;
535 535 if ((val & 0xff) != 0xff && (val & 0x80)) {
536 536 delta_2ghz = val & 0xf;
537 537 if (!(val & 0x40)) /* negative number */
538 538 delta_2ghz = -delta_2ghz;
539 539 }
540 540 val >>= 8;
541 541 if ((val & 0xff) != 0xff && (val & 0x80)) {
542 542 delta_5ghz = val & 0xf;
543 543 if (!(val & 0x40)) /* negative number */
544 544 delta_5ghz = -delta_5ghz;
545 545 }
546 546 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
547 547 "power compensation=%d (2GHz), %d (5GHz) \n",
548 548 delta_2ghz, delta_5ghz);
549 549
550 550 for (ridx = 0; ridx < 5; ridx++) {
551 551 uint32_t reg;
552 552
553 553 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RPWR + ridx);
554 554 reg = (uint32_t)val << 16;
555 555 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RPWR + ridx + 1);
556 556 reg |= val;
557 557
558 558 sc->txpow20mhz[ridx] = reg;
559 559 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);
560 560 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);
561 561
562 562 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
563 563 "ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, "
564 564 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx],
565 565 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx]);
566 566 }
567 567
568 568 /* read factory-calibrated samples for temperature compensation */
569 569 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI1_2GHZ);
570 570 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */
571 571 sc->tssi_2ghz[1] = val >> 8; /* [-3] */
572 572 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI2_2GHZ);
573 573 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */
574 574 sc->tssi_2ghz[3] = val >> 8; /* [-1] */
575 575 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI3_2GHZ);
576 576 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */
577 577 sc->tssi_2ghz[5] = val >> 8; /* [+1] */
578 578 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI4_2GHZ);
579 579 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */
580 580 sc->tssi_2ghz[7] = val >> 8; /* [+3] */
581 581 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI5_2GHZ);
582 582 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */
583 583 sc->step_2ghz = val >> 8;
584 584 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
585 585 "TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x "
586 586 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1],
587 587 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4],
588 588 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7],
589 589 sc->tssi_2ghz[8], sc->step_2ghz);
590 590 /* check that ref value is correct, otherwise disable calibration */
591 591 if (sc->tssi_2ghz[4] == 0xff)
592 592 sc->calib_2ghz = 0;
593 593
594 594 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI1_5GHZ);
595 595 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */
596 596 sc->tssi_5ghz[1] = val >> 8; /* [-3] */
597 597 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI2_5GHZ);
598 598 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */
599 599 sc->tssi_5ghz[3] = val >> 8; /* [-1] */
600 600 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI3_5GHZ);
601 601 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */
602 602 sc->tssi_5ghz[5] = val >> 8; /* [+1] */
603 603 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI4_5GHZ);
604 604 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */
605 605 sc->tssi_5ghz[7] = val >> 8; /* [+3] */
606 606 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI5_5GHZ);
607 607 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */
608 608 sc->step_5ghz = val >> 8;
609 609 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
610 610 "TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x "
611 611 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1],
612 612 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4],
613 613 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7],
614 614 sc->tssi_5ghz[8], sc->step_5ghz);
615 615 /* check that ref value is correct, otherwise disable calibration */
616 616 if (sc->tssi_5ghz[4] == 0xff)
617 617 sc->calib_5ghz = 0;
618 618
619 619 /* read RSSI offsets and LNA gains from EEPROM */
620 620 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RSSI1_2GHZ);
621 621 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */
622 622 sc->rssi_2ghz[1] = val >> 8; /* Ant B */
623 623 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RSSI2_2GHZ);
624 624 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */
625 625 sc->lna[2] = val >> 8; /* channel group 2 */
626 626
627 627 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RSSI1_5GHZ);
628 628 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */
629 629 sc->rssi_5ghz[1] = val >> 8; /* Ant B */
630 630 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RSSI2_5GHZ);
631 631 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */
632 632 sc->lna[3] = val >> 8; /* channel group 3 */
633 633
634 634 val = rt2860_eeprom_read(sc, RT2860_EEPROM_LNA);
635 635 sc->lna[0] = val & 0xff; /* channel group 0 */
636 636 sc->lna[1] = val >> 8; /* channel group 1 */
637 637
638 638 /* fix broken 5GHz LNA entries */
639 639 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) {
640 640 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
641 641 "invalid LNA for channel group %d\n", 2);
642 642 sc->lna[2] = sc->lna[1];
643 643 }
644 644 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) {
645 645 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
646 646 "invalid LNA for channel group %d\n", 3);
647 647 sc->lna[3] = sc->lna[1];
648 648 }
649 649
650 650 /* fix broken RSSI offset entries */
651 651 for (ant = 0; ant < 3; ant++) {
652 652 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) {
653 653 RWN_DEBUG(RT2860_DBG_EEPROM,
654 654 "rwn: rt2860_read_eeprom(): "
655 655 "invalid RSSI%d offset: %d (2GHz)\n",
656 656 ant + 1, sc->rssi_2ghz[ant]);
657 657 sc->rssi_2ghz[ant] = 0;
658 658 }
659 659 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) {
660 660 RWN_DEBUG(RT2860_DBG_EEPROM,
661 661 "rwn: rt2860_read_eeprom(): "
662 662 "invalid RSSI%d offset: %d (2GHz)\n",
663 663 ant + 1, sc->rssi_5ghz[ant]);
664 664 sc->rssi_5ghz[ant] = 0;
665 665 }
666 666 }
667 667
668 668 return (RT2860_SUCCESS);
669 669 }
670 670
671 671 /*
672 672 * Allocate an DMA memory and a DMA handle for accessing it
673 673 */
674 674 static int
675 675 rt2860_alloc_dma_mem(dev_info_t *devinfo, ddi_dma_attr_t *dma_attr,
676 676 size_t memsize, ddi_device_acc_attr_t *attr_p, uint_t alloc_flags,
677 677 uint_t bind_flags, struct dma_area *dma_p)
678 678 {
679 679 int err;
680 680
681 681 /*
682 682 * Allocate handle
683 683 */
684 684 err = ddi_dma_alloc_handle(devinfo, dma_attr,
685 685 DDI_DMA_SLEEP, NULL, &dma_p->dma_hdl);
686 686 if (err != DDI_SUCCESS) {
687 687 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rwn_allo_dma_mem(): "
688 688 "failed to alloc handle\n");
689 689 goto fail1;
690 690 }
691 691
692 692 /*
693 693 * Allocate memory
694 694 */
695 695 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p,
696 696 alloc_flags, DDI_DMA_SLEEP, NULL, &dma_p->mem_va,
697 697 &dma_p->alength, &dma_p->acc_hdl);
698 698 if (err != DDI_SUCCESS) {
699 699 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rwn_alloc_dma_mem(): "
700 700 "failed to alloc mem\n");
701 701 goto fail2;
702 702 }
703 703
704 704 /*
705 705 * Bind the two together
706 706 */
707 707 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL,
708 708 dma_p->mem_va, dma_p->alength, bind_flags,
709 709 DDI_DMA_SLEEP, NULL, &dma_p->cookie, &dma_p->ncookies);
710 710 if (err != DDI_DMA_MAPPED) {
711 711 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rwn_alloc_dma_mem(): "
712 712 "failed to bind handle\n");
713 713 goto fail3;
714 714 }
715 715
716 716 if (dma_p->ncookies != 1) {
717 717 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rwn_alloc_dma_mem(): "
718 718 "failed to alloc cookies\n");
719 719 goto fail4;
720 720 }
721 721
722 722 dma_p->nslots = ~0U;
723 723 dma_p->size = ~0U;
724 724 dma_p->token = ~0U;
725 725 dma_p->offset = 0;
726 726 return (DDI_SUCCESS);
727 727
728 728 fail4:
729 729 (void) ddi_dma_unbind_handle(dma_p->dma_hdl);
730 730 fail3:
731 731 ddi_dma_mem_free(&dma_p->acc_hdl);
732 732 fail2:
733 733 ddi_dma_free_handle(&dma_p->dma_hdl);
734 734 fail1:
735 735 return (err);
736 736 }
737 737
738 738 static void
739 739 rt2860_free_dma_mem(struct dma_area *dma_p)
740 740 {
741 741 if (dma_p->dma_hdl != NULL) {
742 742 (void) ddi_dma_unbind_handle(dma_p->dma_hdl);
743 743 if (dma_p->acc_hdl != NULL) {
744 744 ddi_dma_mem_free(&dma_p->acc_hdl);
745 745 dma_p->acc_hdl = NULL;
746 746 }
747 747 ddi_dma_free_handle(&dma_p->dma_hdl);
748 748 dma_p->ncookies = 0;
749 749 dma_p->dma_hdl = NULL;
750 750 }
751 751 }
752 752
753 753 /*ARGSUSED*/
754 754 static int
755 755 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
756 756 {
757 757 int size, err;
758 758
759 759 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd);
760 760
761 761 err = rt2860_alloc_dma_mem(sc->sc_dev, &rt2860_dma_attr, size,
762 762 &rt2860_desc_accattr, DDI_DMA_CONSISTENT,
763 763 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
764 764 &ring->txdesc_dma);
765 765 if (err != DDI_SUCCESS) {
766 766 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rt2860_alloc_tx_ring(): "
767 767 "failed to alloc dma mem\n");
768 768 goto fail1;
769 769 }
770 770
771 771 ring->txd = (struct rt2860_txd *)ring->txdesc_dma.mem_va;
772 772 ring->paddr = ring->txdesc_dma.cookie.dmac_address;
773 773
774 774 ring->cur = 0;
775 775 ring->next = 0;
776 776 ring->queued = 0;
777 777
778 778 (void) bzero(ring->txd, size);
779 779 RT2860_DMA_SYNC(ring->txdesc_dma, DDI_DMA_SYNC_FORDEV);
780 780 return (DDI_SUCCESS);
781 781 fail1:
782 782 return (err);
783 783 }
784 784
785 785 void
786 786 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
787 787 {
788 788 struct rt2860_tx_data *data;
789 789 int i;
790 790
791 791 for (i = 0; i < RT2860_TX_RING_COUNT; i++) {
792 792 ring->txd[i].sdl0 &= ~LE_16(RT2860_TX_DDONE);
793 793
794 794 if ((data = ring->data[i]) == NULL)
795 795 continue; /* nothing mapped in this slot */
796 796
797 797 /* by pass if it's quiesced */
798 798 if (!(sc->sc_flags & RT2860_F_QUIESCE))
799 799 RT2860_DMA_SYNC(data->txbuf_dma, DDI_DMA_SYNC_FORDEV);
800 800
801 801 if (data->ni != NULL) {
802 802 ieee80211_free_node(data->ni);
803 803 data->ni = NULL; /* node already freed */
804 804 }
805 805
806 806 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
807 807 ring->data[i] = NULL;
808 808 }
809 809
810 810 /* by pass if it's quiesced */
811 811 if (!(sc->sc_flags & RT2860_F_QUIESCE))
812 812 RT2860_DMA_SYNC(ring->txdesc_dma, DDI_DMA_SYNC_FORDEV);
813 813
814 814 ring->queued = 0;
815 815 ring->cur = ring->next = 0;
816 816 }
817 817
818 818 /*ARGSUSED*/
819 819 static void
820 820 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
821 821 {
822 822 if (ring->txd != NULL) {
823 823 rt2860_free_dma_mem(&ring->txdesc_dma);
824 824 }
825 825 }
826 826
827 827 static int
828 828 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
829 829 {
830 830 struct rt2860_rx_data *data;
831 831 struct rt2860_rxd *rxd;
832 832 int i, err, size, datalen;
833 833
834 834 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd);
835 835
836 836 err = rt2860_alloc_dma_mem(sc->sc_dev, &rt2860_dma_attr, size,
837 837 &rt2860_desc_accattr, DDI_DMA_CONSISTENT,
838 838 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
839 839 &ring->rxdesc_dma);
840 840 if (err != DDI_SUCCESS) {
841 841 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rt2860_alloc_rx_ring(): "
842 842 "failed to alloc dma mem\n");
843 843 goto fail1;
844 844 }
845 845
846 846 ring->rxd = (struct rt2860_rxd *)ring->rxdesc_dma.mem_va;
847 847 ring->paddr = ring->rxdesc_dma.cookie.dmac_address;
848 848 bzero(ring->rxd, size);
849 849
850 850 /*
851 851 * Pre-allocate Rx buffers and populate Rx ring.
852 852 */
853 853 datalen = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rx_data);
854 854 bzero(ring->data, datalen);
855 855 for (i = 0; i < RT2860_RX_RING_COUNT; i++) {
856 856 rxd = &ring->rxd[i];
857 857 data = &ring->data[i];
858 858 /* alloc DMA memory */
859 859 (void) rt2860_alloc_dma_mem(sc->sc_dev, &rt2860_dma_attr,
860 860 sc->sc_dmabuf_size,
861 861 &rt2860_buf_accattr,
862 862 DDI_DMA_STREAMING,
863 863 DDI_DMA_READ | DDI_DMA_STREAMING,
864 864 &data->rxbuf_dma);
865 865 rxd->sdp0 = LE_32(data->rxbuf_dma.cookie.dmac_address);
866 866 rxd->sdl0 = LE_16(sc->sc_dmabuf_size);
867 867 }
868 868
869 869 ring->cur = 0;
870 870
871 871 RT2860_DMA_SYNC(ring->rxdesc_dma, DDI_DMA_SYNC_FORDEV);
872 872 return (DDI_SUCCESS);
873 873 fail2:
874 874 rt2860_free_dma_mem(&ring->rxdesc_dma);
875 875 fail1:
876 876 return (err);
877 877 }
878 878
879 879 /*ARGSUSED*/
880 880 void
881 881 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
882 882 {
883 883 int i;
884 884
885 885 for (i = 0; i < RT2860_RX_RING_COUNT; i++)
886 886 ring->rxd[i].sdl0 &= ~LE_16(RT2860_RX_DDONE);
887 887
888 888 RT2860_DMA_SYNC(ring->rxdesc_dma, DDI_DMA_SYNC_FORDEV);
889 889
890 890 ring->cur = 0;
891 891 }
892 892
893 893 /*ARGSUSED*/
894 894 static void
895 895 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
896 896 {
897 897 struct rt2860_rx_data *data;
898 898 int i, count;
899 899
900 900 if (ring->rxd != NULL)
901 901 rt2860_free_dma_mem(&ring->rxdesc_dma);
902 902
903 903 count = RT2860_RX_RING_COUNT;
904 904
905 905 for (i = 0; i < count; i++) {
906 906 data = &ring->data[i];
907 907 rt2860_free_dma_mem(&data->rxbuf_dma);
908 908 }
909 909 }
910 910
911 911 static int
912 912 rt2860_alloc_tx_pool(struct rt2860_softc *sc)
913 913 {
914 914 struct rt2860_tx_data *data;
915 915 int i, err, size;
916 916
917 917 size = RT2860_TX_POOL_COUNT * sizeof (struct rt2860_txwi);
918 918
919 919 /* init data_pool early in case of failure.. */
920 920 SLIST_INIT(&sc->data_pool);
921 921
922 922 err = rt2860_alloc_dma_mem(sc->sc_dev, &rt2860_dma_attr, size,
923 923 &rt2860_desc_accattr, DDI_DMA_CONSISTENT,
924 924 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
925 925 &sc->txpool_dma);
926 926 if (err != DDI_SUCCESS) {
927 927 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rt2860_alloc_tx_pool(): "
928 928 "failed to alloc dma mem\n");
929 929 goto fail1;
930 930 }
931 931
932 932 sc->txwi = (struct rt2860_txwi *)sc->txpool_dma.mem_va;
933 933 (void) bzero(sc->txwi, size);
934 934 RT2860_DMA_SYNC(sc->txpool_dma, DDI_DMA_SYNC_FORDEV);
935 935
936 936 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) {
937 937 data = &sc->data[i];
938 938
939 939 err = rt2860_alloc_dma_mem(sc->sc_dev, &rt2860_dma_attr,
940 940 sc->sc_dmabuf_size,
941 941 &rt2860_buf_accattr, DDI_DMA_CONSISTENT,
942 942 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
943 943 &data->txbuf_dma);
944 944 if (err != DDI_SUCCESS) {
945 945 RWN_DEBUG(RT2860_DBG_DMA,
946 946 "rwn: rt2860_alloc_tx_pool(): "
947 947 "failed to alloc dma mem\n");
948 948 goto fail2;
949 949 }
950 950 data->txwi = &sc->txwi[i];
951 951 data->paddr = sc->txpool_dma.cookie.dmac_address +
952 952 i * sizeof (struct rt2860_txwi);
953 953
954 954 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
955 955 }
956 956 return (DDI_SUCCESS);
957 957 fail2:
958 958 rt2860_free_dma_mem(&sc->txpool_dma);
959 959 fail1:
960 960 return (err);
961 961 }
962 962
963 963 static void
964 964 rt2860_free_tx_pool(struct rt2860_softc *sc)
965 965 {
966 966 struct rt2860_tx_data *data;
967 967 int i;
968 968
969 969 if (sc->txwi != NULL) {
970 970 rt2860_free_dma_mem(&sc->txpool_dma);
971 971 }
972 972
973 973 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) {
974 974 data = &sc->data[i];
975 975 rt2860_free_dma_mem(&data->txbuf_dma);
976 976 }
977 977 }
978 978
979 979 /* quickly determine if a given rate is CCK or OFDM */
980 980 #define RT2860_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22)
981 981
982 982 #define RT2860_ACK_SIZE 14 /* 10 + 4(FCS) */
983 983 #define RT2860_SIFS_TIME 10
984 984
985 985 static uint8_t
986 986 rt2860_rate2mcs(uint8_t rate)
987 987 {
988 988 switch (rate) {
989 989 /* CCK rates */
990 990 case 2:
991 991 return (0);
992 992 case 4:
993 993 return (1);
994 994 case 11:
995 995 return (2);
996 996 case 22:
997 997 return (3);
998 998 /* OFDM rates */
999 999 case 12:
1000 1000 return (0);
1001 1001 case 18:
1002 1002 return (1);
1003 1003 case 24:
1004 1004 return (2);
1005 1005 case 36:
1006 1006 return (3);
1007 1007 case 48:
1008 1008 return (4);
1009 1009 case 72:
1010 1010 return (5);
1011 1011 case 96:
1012 1012 return (6);
1013 1013 case 108:
1014 1014 return (7);
1015 1015 }
1016 1016
1017 1017 return (0); /* shouldn't get there */
1018 1018 }
1019 1019
1020 1020 /*
1021 1021 * Return the expected ack rate for a frame transmitted at rate `rate'.
1022 1022 */
1023 1023 static int
1024 1024 rt2860_ack_rate(struct ieee80211com *ic, int rate)
1025 1025 {
1026 1026 switch (rate) {
1027 1027 /* CCK rates */
1028 1028 case 2:
1029 1029 return (2);
1030 1030 case 4:
1031 1031 case 11:
1032 1032 case 22:
1033 1033 return ((ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate);
1034 1034
1035 1035 /* OFDM rates */
1036 1036 case 12:
1037 1037 case 18:
1038 1038 return (12);
1039 1039 case 24:
1040 1040 case 36:
1041 1041 return (24);
1042 1042 case 48:
1043 1043 case 72:
1044 1044 case 96:
1045 1045 case 108:
1046 1046 return (48);
1047 1047 }
1048 1048
1049 1049 /* default to 1Mbps */
1050 1050 return (2);
1051 1051 }
1052 1052
1053 1053
1054 1054 /*
1055 1055 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'.
1056 1056 * The function automatically determines the operating mode depending on the
1057 1057 * given rate. `flags' indicates whether short preamble is in use or not.
1058 1058 */
1059 1059 static uint16_t
1060 1060 rt2860_txtime(int len, int rate, uint32_t flags)
1061 1061 {
1062 1062 uint16_t txtime;
1063 1063
1064 1064 if (RT2860_RATE_IS_OFDM(rate)) {
1065 1065 /* IEEE Std 802.11g-2003, pp. 44 */
1066 1066 txtime = (8 + 4 * len + 3 + rate - 1) / rate;
1067 1067 txtime = 16 + 4 + 4 * txtime + 6;
1068 1068 } else {
1069 1069 /* IEEE Std 802.11b-1999, pp. 28 */
1070 1070 txtime = (16 * len + rate - 1) / rate;
1071 1071 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE))
1072 1072 txtime += 72 + 24;
1073 1073 else
1074 1074 txtime += 144 + 48;
1075 1075 }
1076 1076 return (txtime);
1077 1077 }
1078 1078
1079 1079 static int
1080 1080 rt2860_send(ieee80211com_t *ic, mblk_t *mp, uint8_t type)
1081 1081 {
1082 1082 struct rt2860_softc *sc = (struct rt2860_softc *)ic;
1083 1083 struct rt2860_tx_ring *ring;
1084 1084 struct rt2860_tx_data *data;
1085 1085 struct rt2860_txd *txd;
1086 1086 struct rt2860_txwi *txwi;
1087 1087 struct ieee80211_frame *wh;
1088 1088 struct ieee80211_node *ni;
1089 1089 int qid, off, rate, err;
1090 1090 int mblen, pktlen;
1091 1091 uint_t hdrlen;
1092 1092 uint8_t mcs, pid, qsel;
1093 1093 uint16_t dur;
1094 1094 mblk_t *m, *m0;
1095 1095
1096 1096 err = DDI_SUCCESS;
1097 1097
1098 1098 mutex_enter(&sc->sc_txlock);
1099 1099 if (RT2860_IS_SUSPEND(sc)) {
1100 1100 err = ENXIO;
1101 1101 goto fail1;
1102 1102 }
1103 1103
1104 1104 if ((type & IEEE80211_FC0_TYPE_MASK) !=
1105 1105 IEEE80211_FC0_TYPE_DATA)
1106 1106 qid = sc->mgtqid;
1107 1107 else
1108 1108 qid = EDCA_AC_BE;
1109 1109 ring = &sc->txq[qid];
1110 1110
1111 1111 if (SLIST_EMPTY(&sc->data_pool) || (ring->queued > 15)) {
1112 1112 sc->sc_need_sched = 1;
1113 1113 sc->sc_tx_nobuf++;
1114 1114 err = ENOMEM;
1115 1115 goto fail1;
1116 1116 }
1117 1117
1118 1118 /* the data pool contains at least one element, pick the first */
1119 1119 data = SLIST_FIRST(&sc->data_pool);
1120 1120
1121 1121 m = allocb(msgdsize(mp) + 32, BPRI_MED);
1122 1122 if (m == NULL) {
1123 1123 RWN_DEBUG(RT2860_DBG_TX, "rwn: rt2860_send():"
1124 1124 "rt2860_mgmt_send: can't alloc mblk.\n");
1125 1125 err = DDI_FAILURE;
1126 1126 goto fail1;
1127 1127 }
1128 1128
1129 1129 for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) {
1130 1130 mblen = MBLKL(m0);
1131 1131 (void) bcopy(m0->b_rptr, m->b_rptr + off, mblen);
1132 1132 off += mblen;
1133 1133 }
1134 1134 m->b_wptr += off;
1135 1135
1136 1136 wh = (struct ieee80211_frame *)m->b_rptr;
1137 1137 ni = ieee80211_find_txnode(ic, wh->i_addr1);
1138 1138 if (ni == NULL) {
1139 1139 err = DDI_FAILURE;
1140 1140 sc->sc_tx_err++;
1141 1141 goto fail2;
1142 1142 }
1143 1143
1144 1144 if ((type & IEEE80211_FC0_TYPE_MASK) ==
1145 1145 IEEE80211_FC0_TYPE_DATA)
1146 1146 (void) ieee80211_encap(ic, m, ni);
1147 1147
1148 1148 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1149 1149 struct ieee80211_key *k;
1150 1150 k = ieee80211_crypto_encap(ic, m);
1151 1151 if (k == NULL) {
1152 1152 sc->sc_tx_err++;
1153 1153 err = DDI_FAILURE;
1154 1154 goto fail3;
1155 1155 }
1156 1156 /* packet header may have moved, reset our local pointer */
1157 1157 wh = (struct ieee80211_frame *)m->b_rptr;
1158 1158 }
1159 1159 pktlen = msgdsize(m);
1160 1160 hdrlen = sizeof (*wh);
1161 1161
1162 1162 /* pickup a rate */
1163 1163 if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
1164 1164 ((type & IEEE80211_FC0_TYPE_MASK) !=
1165 1165 IEEE80211_FC0_TYPE_DATA))
1166 1166 rate = ni->in_rates.ir_rates[0];
1167 1167 else {
1168 1168 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE)
1169 1169 rate = ic->ic_fixed_rate;
1170 1170 else
1171 1171 rate = ni->in_rates.ir_rates[ni->in_txrate];
1172 1172 }
1173 1173 rate &= IEEE80211_RATE_VAL;
1174 1174
1175 1175 /* get MCS code from rate */
1176 1176 mcs = rt2860_rate2mcs(rate);
1177 1177
1178 1178 /* setup TX Wireless Information */
1179 1179 txwi = data->txwi;
1180 1180 (void) bzero(txwi, sizeof (struct rt2860_txwi));
1181 1181 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ?
1182 1182 RT2860_AID2WCID(ni->in_associd) : 0xff;
1183 1183 txwi->len = LE_16(pktlen);
1184 1184 if (!RT2860_RATE_IS_OFDM(rate)) {
1185 1185 txwi->phy = LE_16(RT2860_PHY_CCK);
1186 1186 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1187 1187 mcs |= RT2860_PHY_SHPRE;
1188 1188 } else
1189 1189 txwi->phy = LE_16(RT2860_PHY_OFDM);
1190 1190 txwi->phy |= LE_16(mcs);
1191 1191
1192 1192 /*
1193 1193 * We store the MCS code into the driver-private PacketID field.
1194 1194 * The PacketID is latched into TX_STAT_FIFO when Tx completes so
1195 1195 * that we know at which initial rate the frame was transmitted.
1196 1196 * We add 1 to the MCS code because setting the PacketID field to
1197 1197 * 0 means that we don't want feedback in TX_STAT_FIFO.
1198 1198 */
1199 1199 pid = (mcs + 1) & 0xf;
1200 1200 txwi->len |= LE_16(pid << RT2860_TX_PID_SHIFT);
1201 1201
1202 1202 /* check if RTS/CTS or CTS-to-self protection is required */
1203 1203 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1204 1204 (pktlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold ||
1205 1205 ((ic->ic_flags &
1206 1206 IEEE80211_F_USEPROT) && RT2860_RATE_IS_OFDM(rate))))
1207 1207 txwi->txop = RT2860_TX_TXOP_HT;
1208 1208 else
1209 1209 txwi->txop = RT2860_TX_TXOP_BACKOFF;
1210 1210
1211 1211 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1212 1212 txwi->xflags |= RT2860_TX_ACK;
1213 1213
1214 1214 dur = rt2860_txtime(RT2860_ACK_SIZE, rt2860_ack_rate(ic, rate),
1215 1215 ic->ic_flags) + sc->sifs;
1216 1216 *(uint16_t *)wh->i_dur = LE_16(dur);
1217 1217 }
1218 1218
1219 1219 /* copy and trim 802.11 header */
1220 1220 bcopy(wh, &txwi->wh, hdrlen);
1221 1221 m->b_rptr += hdrlen;
1222 1222 bcopy(m->b_rptr, data->txbuf_dma.mem_va, pktlen - hdrlen);
1223 1223
1224 1224 qsel = (qid < EDCA_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT;
1225 1225
1226 1226 /* first segment is TXWI + 802.11 header */
1227 1227 txd = &ring->txd[ring->cur];
1228 1228 txd->sdp0 = LE_32(data->paddr);
1229 1229 txd->sdl0 = LE_16(16 + hdrlen);
1230 1230 txd->flags = qsel;
1231 1231
1232 1232 /* finalize last segment */
1233 1233 txd->sdp1 = LE_32(data->txbuf_dma.cookie.dmac_address);
1234 1234 txd->sdl1 = LE_16(pktlen - hdrlen | RT2860_TX_LS1);
1235 1235
1236 1236 /* remove from the free pool and link it into the SW Tx slot */
1237 1237 SLIST_REMOVE_HEAD(&sc->data_pool, next);
1238 1238 data->ni = ieee80211_ref_node(ni);
1239 1239 ring->data[ring->cur] = data;
1240 1240
1241 1241 (void) ddi_dma_sync(sc->txpool_dma.dma_hdl,
1242 1242 _PTRDIFF(txwi, sc->txwi),
1243 1243 (hdrlen + 16 + 2),
1244 1244 DDI_DMA_SYNC_FORDEV);
1245 1245 RT2860_DMA_SYNC(data->txbuf_dma, DDI_DMA_SYNC_FORDEV);
1246 1246 RT2860_DMA_SYNC(ring->txdesc_dma, DDI_DMA_SYNC_FORDEV);
1247 1247
1248 1248 RWN_DEBUG(RT2860_DBG_TX, "rwn: rt2860_send():"
1249 1249 "sending frame qid=%d wcid=%d rate=%d cur = %x\n",
1250 1250 qid, txwi->wcid, rate, ring->cur);
1251 1251
1252 1252 ring->queued++;
1253 1253 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1254 1254
1255 1255 /* kick Tx */
1256 1256 RT2860_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur);
1257 1257
1258 1258 sc->sc_tx_timer = 5;
1259 1259
1260 1260 ic->ic_stats.is_tx_frags++;
1261 1261 ic->ic_stats.is_tx_bytes += pktlen;
1262 1262
1263 1263 fail3:
1264 1264 ieee80211_free_node(ni);
1265 1265 fail2:
1266 1266 freemsg(m);
1267 1267 fail1:
1268 1268 if ((type & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_DATA ||
1269 1269 err == DDI_SUCCESS)
1270 1270 freemsg(mp);
1271 1271 mutex_exit(&sc->sc_txlock);
1272 1272 return (err);
1273 1273 }
1274 1274
1275 1275 /*
1276 1276 * This function is called periodically (every 200ms) during scanning to
1277 1277 * switch from one channel to another.
1278 1278 */
1279 1279 static void
1280 1280 rt2860_next_scan(void *arg)
1281 1281 {
1282 1282 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
1283 1283 struct ieee80211com *ic = &sc->sc_ic;
1284 1284
1285 1285 if (ic->ic_state == IEEE80211_S_SCAN)
1286 1286 (void) ieee80211_next_scan(ic);
1287 1287 }
1288 1288
1289 1289 static void
1290 1290 rt2860_updateslot(struct rt2860_softc *sc)
1291 1291 {
1292 1292 struct ieee80211com *ic = &sc->sc_ic;
1293 1293 uint32_t tmp;
1294 1294
1295 1295 tmp = RT2860_READ(sc, RT2860_BKOFF_SLOT_CFG);
1296 1296 tmp &= ~0xff;
1297 1297 tmp |= (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20;
1298 1298 RT2860_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp);
1299 1299 }
1300 1300
1301 1301 static void
1302 1302 rt2860_iter_func(void *arg, struct ieee80211_node *ni)
1303 1303 {
1304 1304 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
1305 1305 uint8_t wcid;
1306 1306
1307 1307 wcid = RT2860_AID2WCID(ni->in_associd);
1308 1308 rt2860_amrr_choose(&sc->amrr, ni, &sc->amn[wcid]);
1309 1309 }
1310 1310
1311 1311 static void
1312 1312 rt2860_updatestats(void *arg)
1313 1313 {
1314 1314 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
1315 1315 struct ieee80211com *ic = &sc->sc_ic;
1316 1316
1317 1317 if (ic->ic_opmode == IEEE80211_M_STA)
1318 1318 rt2860_iter_func(sc, ic->ic_bss);
1319 1319 else
1320 1320 ieee80211_iterate_nodes(&ic->ic_sta, rt2860_iter_func, arg);
1321 1321
1322 1322 sc->sc_rssadapt_id = timeout(rt2860_updatestats, (void *)sc,
1323 1323 drv_usectohz(500 * 1000));
1324 1324 }
1325 1325
1326 1326 static void
1327 1327 rt2860_enable_mrr(struct rt2860_softc *sc)
1328 1328 {
1329 1329 #define CCK(mcs) (mcs)
1330 1330 #define OFDM(mcs) ((uint32_t)1 << 3 | (mcs))
1331 1331 RT2860_WRITE(sc, RT2860_LG_FBK_CFG0,
1332 1332 OFDM(6) << 28 | /* 54->48 */
1333 1333 OFDM(5) << 24 | /* 48->36 */
1334 1334 OFDM(4) << 20 | /* 36->24 */
1335 1335 OFDM(3) << 16 | /* 24->18 */
1336 1336 OFDM(2) << 12 | /* 18->12 */
1337 1337 OFDM(1) << 8 | /* 12-> 9 */
1338 1338 OFDM(0) << 4 | /* 9-> 6 */
1339 1339 OFDM(0)); /* 6-> 6 */
1340 1340
1341 1341 RT2860_WRITE(sc, RT2860_LG_FBK_CFG1,
1342 1342 CCK(2) << 12 | /* 11->5.5 */
1343 1343 CCK(1) << 8 | /* 5.5-> 2 */
1344 1344 CCK(0) << 4 | /* 2-> 1 */
1345 1345 CCK(0)); /* 1-> 1 */
1346 1346 #undef OFDM
1347 1347 #undef CCK
1348 1348 }
1349 1349
1350 1350 static void
1351 1351 rt2860_set_txpreamble(struct rt2860_softc *sc)
1352 1352 {
1353 1353 uint32_t tmp;
1354 1354
1355 1355 tmp = RT2860_READ(sc, RT2860_AUTO_RSP_CFG);
1356 1356 tmp &= ~RT2860_CCK_SHORT_EN;
1357 1357 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE)
1358 1358 tmp |= RT2860_CCK_SHORT_EN;
1359 1359 RT2860_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp);
1360 1360 }
1361 1361
1362 1362 static void
1363 1363 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid)
1364 1364 {
1365 1365 RT2860_WRITE(sc, RT2860_MAC_BSSID_DW0,
1366 1366 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24);
1367 1367 RT2860_WRITE(sc, RT2860_MAC_BSSID_DW1,
1368 1368 bssid[4] | bssid[5] << 8);
1369 1369 }
1370 1370
1371 1371 static void
1372 1372 rt2860_set_basicrates(struct rt2860_softc *sc)
1373 1373 {
1374 1374 struct ieee80211com *ic = &sc->sc_ic;
1375 1375
1376 1376 /* set basic rates mask */
1377 1377 if (ic->ic_curmode == IEEE80211_MODE_11B)
1378 1378 RT2860_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x003);
1379 1379 else if (ic->ic_curmode == IEEE80211_MODE_11A)
1380 1380 RT2860_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x150);
1381 1381 else /* 11g */
1382 1382 RT2860_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x15f);
1383 1383 }
1384 1384
1385 1385 static void
1386 1386 rt2860_amrr_node_init(const struct rt2860_amrr *amrr,
1387 1387 struct rt2860_amrr_node *amn)
1388 1388 {
1389 1389 amn->amn_success = 0;
1390 1390 amn->amn_recovery = 0;
1391 1391 amn->amn_txcnt = amn->amn_retrycnt = 0;
1392 1392 amn->amn_success_threshold = amrr->amrr_min_success_threshold;
1393 1393 }
1394 1394
1395 1395 static void
1396 1396 rt2860_amrr_choose(struct rt2860_amrr *amrr, struct ieee80211_node *ni,
1397 1397 struct rt2860_amrr_node *amn)
1398 1398 {
1399 1399 #define RV(rate) ((rate) & IEEE80211_RATE_VAL)
1400 1400 #define is_success(amn) \
1401 1401 ((amn)->amn_retrycnt < (amn)->amn_txcnt / 10)
1402 1402 #define is_failure(amn) \
1403 1403 ((amn)->amn_retrycnt > (amn)->amn_txcnt / 3)
1404 1404 #define is_enough(amn) \
1405 1405 ((amn)->amn_txcnt > 10)
1406 1406 #define is_min_rate(ni) \
1407 1407 ((ni)->in_txrate == 0)
1408 1408 #define is_max_rate(ni) \
1409 1409 ((ni)->in_txrate == (ni)->in_rates.ir_nrates - 1)
1410 1410 #define increase_rate(ni) \
1411 1411 ((ni)->in_txrate++)
1412 1412 #define decrease_rate(ni) \
1413 1413 ((ni)->in_txrate--)
1414 1414 #define reset_cnt(amn) \
1415 1415 { (amn)->amn_txcnt = (amn)->amn_retrycnt = 0; }
1416 1416
1417 1417 int need_change = 0;
1418 1418
1419 1419 if (is_success(amn) && is_enough(amn)) {
1420 1420 amn->amn_success++;
1421 1421 if (amn->amn_success >= amn->amn_success_threshold &&
1422 1422 !is_max_rate(ni)) {
1423 1423 amn->amn_recovery = 1;
1424 1424 amn->amn_success = 0;
1425 1425 increase_rate(ni);
1426 1426 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_amrr_choose(): "
1427 1427 "increase rate = %d, #tx = %d, #retries = %d\n",
1428 1428 RV(ni->in_rates.ir_rates[ni->in_txrate]),
1429 1429 amn->amn_txcnt, amn->amn_retrycnt);
1430 1430 need_change = 1;
1431 1431 } else {
1432 1432 amn->amn_recovery = 0;
1433 1433 }
1434 1434 } else if (is_failure(amn)) {
1435 1435 amn->amn_success = 0;
1436 1436 if (!is_min_rate(ni)) {
1437 1437 if (amn->amn_recovery) {
1438 1438 amn->amn_success_threshold *= 2;
1439 1439 if (amn->amn_success_threshold >
1440 1440 amrr->amrr_max_success_threshold)
1441 1441 amn->amn_success_threshold =
1442 1442 amrr->amrr_max_success_threshold;
1443 1443 } else {
1444 1444 amn->amn_success_threshold =
1445 1445 amrr->amrr_min_success_threshold;
1446 1446 }
1447 1447 decrease_rate(ni);
1448 1448 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_amrr_choose(): "
1449 1449 "decrease rate = %d, #tx = %d, #retries = %d\n",
1450 1450 RV(ni->in_rates.ir_rates[ni->in_txrate]),
1451 1451 amn->amn_txcnt, amn->amn_retrycnt);
1452 1452 need_change = 1;
1453 1453 }
1454 1454 amn->amn_recovery = 0;
1455 1455 }
1456 1456
1457 1457 if (is_enough(amn) || need_change)
1458 1458 reset_cnt(amn);
1459 1459 #undef RV
1460 1460 }
1461 1461
1462 1462 static void
1463 1463 rt2860_newassoc(struct ieee80211com *ic, struct ieee80211_node *in, int isnew)
1464 1464 {
1465 1465 struct rt2860_softc *sc = (struct rt2860_softc *)ic;
1466 1466 uint32_t off;
1467 1467 uint8_t *fptr, wcid = 0;
1468 1468 int i;
1469 1469
1470 1470 if (isnew && in->in_associd != 0) {
1471 1471 /* only interested in true associations */
1472 1472 wcid = RT2860_AID2WCID(in->in_associd);
1473 1473
1474 1474 /* init WCID table entry */
1475 1475 off = RT2860_WCID_ENTRY(wcid);
1476 1476 fptr = in->in_macaddr;
1477 1477 for (i = 0; i < IEEE80211_ADDR_LEN; i++)
1478 1478 rt2860_mem_write1(sc, off++, *fptr++);
1479 1479 }
1480 1480 rt2860_amrr_node_init(&sc->amrr, &sc->amn[wcid]);
1481 1481
1482 1482 /* set rate to some reasonable initial value */
1483 1483 i = in->in_rates.ir_nrates - 1;
1484 1484 for (; i > 0 && (in->in_rates.ir_rates[i] & IEEE80211_RATE_VAL) > 72; )
1485 1485 i--;
1486 1486 in->in_txrate = i;
1487 1487
1488 1488 RWN_DEBUG(RT2860_DBG_80211, "rwn: rt2860_newassoc(): "
1489 1489 "new assoc isnew=%d WCID=%d, initial rate=%d\n",
1490 1490 isnew, wcid,
1491 1491 in->in_rates.ir_rates[i] & IEEE80211_RATE_VAL);
1492 1492 RWN_DEBUG(RT2860_DBG_80211, "rwn: rt2860_newassoc(): "
1493 1493 "addr=%x:%x:%x:%x:%x:%x\n",
1494 1494 in->in_macaddr[0], in->in_macaddr[1], in->in_macaddr[2],
1495 1495 in->in_macaddr[3], in->in_macaddr[4], in->in_macaddr[5]);
1496 1496 }
1497 1497
1498 1498 void
1499 1499 rt2860_enable_tsf_sync(struct rt2860_softc *sc)
1500 1500 {
1501 1501 struct ieee80211com *ic = &sc->sc_ic;
1502 1502 uint32_t tmp;
1503 1503
1504 1504 tmp = RT2860_READ(sc, RT2860_BCN_TIME_CFG);
1505 1505
1506 1506 tmp &= ~0x1fffff;
1507 1507 tmp |= ic->ic_bss->in_intval * 16;
1508 1508 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN;
1509 1509 if (ic->ic_opmode == IEEE80211_M_STA) {
1510 1510 /*
1511 1511 * Local TSF is always updated with remote TSF on beacon
1512 1512 * reception.
1513 1513 */
1514 1514 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT;
1515 1515 }
1516 1516
1517 1517 RT2860_WRITE(sc, RT2860_BCN_TIME_CFG, tmp);
1518 1518 }
1519 1519
1520 1520 static int
1521 1521 rt2860_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
1522 1522 {
1523 1523 struct rt2860_softc *sc = (struct rt2860_softc *)ic;
1524 1524 enum ieee80211_state ostate;
1525 1525 int err;
1526 1526 uint32_t tmp;
1527 1527
1528 1528 ostate = ic->ic_state;
1529 1529 RWN_DEBUG(RT2860_DBG_80211, "rwn: rt2860_newstate(): "
1530 1530 "%x -> %x!\n", ostate, nstate);
1531 1531
1532 1532 RT2860_GLOCK(sc);
1533 1533 if (sc->sc_scan_id != 0) {
1534 1534 (void) untimeout(sc->sc_scan_id);
1535 1535 sc->sc_scan_id = 0;
1536 1536 }
1537 1537 if (sc->sc_rssadapt_id != 0) {
1538 1538 (void) untimeout(sc->sc_rssadapt_id);
1539 1539 sc->sc_rssadapt_id = 0;
1540 1540 }
1541 1541 if (ostate == IEEE80211_S_RUN) {
1542 1542 /* turn link LED off */
1543 1543 rt2860_set_leds(sc, RT2860_LED_RADIO);
1544 1544 }
1545 1545
1546 1546 switch (nstate) {
1547 1547 case IEEE80211_S_INIT:
1548 1548 if (ostate == IEEE80211_S_RUN) {
1549 1549 /* abort TSF synchronization */
1550 1550 tmp = RT2860_READ(sc, RT2860_BCN_TIME_CFG);
1551 1551 RT2860_WRITE(sc, RT2860_BCN_TIME_CFG,
1552 1552 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN |
1553 1553 RT2860_TBTT_TIMER_EN));
1554 1554 }
1555 1555 break;
1556 1556
1557 1557 case IEEE80211_S_SCAN:
1558 1558 rt2860_set_chan(sc, ic->ic_curchan);
1559 1559 sc->sc_scan_id = timeout(rt2860_next_scan, (void *)sc,
1560 1560 drv_usectohz(200000));
1561 1561 break;
1562 1562
1563 1563 case IEEE80211_S_AUTH:
1564 1564 case IEEE80211_S_ASSOC:
1565 1565 rt2860_set_chan(sc, ic->ic_curchan);
1566 1566 break;
1567 1567
1568 1568 case IEEE80211_S_RUN:
1569 1569 rt2860_set_chan(sc, ic->ic_curchan);
1570 1570
1571 1571 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1572 1572 rt2860_updateslot(sc);
1573 1573 rt2860_enable_mrr(sc);
1574 1574 rt2860_set_txpreamble(sc);
1575 1575 rt2860_set_basicrates(sc);
1576 1576 rt2860_set_bssid(sc, ic->ic_bss->in_bssid);
1577 1577 }
1578 1578 if (ic->ic_opmode == IEEE80211_M_STA) {
1579 1579 /* fake a join to init the tx rate */
1580 1580 rt2860_newassoc(ic, ic->ic_bss, 1);
1581 1581 }
1582 1582
1583 1583 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1584 1584 rt2860_enable_tsf_sync(sc);
1585 1585 sc->sc_rssadapt_id = timeout(rt2860_updatestats,
1586 1586 (void *)sc, drv_usectohz(500 * 1000));
1587 1587 }
1588 1588
1589 1589 /* turn link LED on */
1590 1590 rt2860_set_leds(sc, RT2860_LED_RADIO |
1591 1591 (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) ?
1592 1592 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ));
1593 1593 break;
1594 1594 }
1595 1595
1596 1596 RT2860_GUNLOCK(sc);
1597 1597
1598 1598 err = sc->sc_newstate(ic, nstate, arg);
1599 1599
1600 1600 return (err);
1601 1601 }
1602 1602
1603 1603 /*
1604 1604 * Return the Rx chain with the highest RSSI for a given frame.
1605 1605 */
1606 1606 static uint8_t
1607 1607 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi)
1608 1608 {
1609 1609 uint8_t rxchain = 0;
1610 1610
1611 1611 if (sc->nrxchains > 1)
1612 1612 if (rxwi->rssi[1] > rxwi->rssi[rxchain])
1613 1613 rxchain = 1;
1614 1614 if (sc->nrxchains > 2)
1615 1615 if (rxwi->rssi[2] > rxwi->rssi[rxchain])
1616 1616 rxchain = 2;
1617 1617
1618 1618 return (rxchain);
1619 1619 }
1620 1620
1621 1621 static void
1622 1622 rt2860_drain_stats_fifo(struct rt2860_softc *sc)
1623 1623 {
1624 1624 struct rt2860_amrr_node *amn;
1625 1625 uint32_t stat;
1626 1626 uint8_t wcid, mcs, pid;
1627 1627
1628 1628 /* drain Tx status FIFO (maxsize = 16) */
1629 1629 while ((stat = RT2860_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) {
1630 1630 RWN_DEBUG(RT2860_DBG_TX, "rwn: rt2860_drain_stats_fifo(): "
1631 1631 "tx stat 0x%08\n", stat);
1632 1632
1633 1633 wcid = (stat >> 8) & 0xff;
1634 1634
1635 1635 /* if no ACK was requested, no feedback is available */
1636 1636 if (!(stat & RT2860_TXQ_ACKREQ) || wcid == 0xff)
1637 1637 continue;
1638 1638 /* update per-STA AMRR stats */
1639 1639 amn = &sc->amn[wcid];
1640 1640 amn->amn_txcnt++;
1641 1641 if (stat & RT2860_TXQ_OK) {
1642 1642 /*
1643 1643 * Check if there were retries, ie if the Tx success
1644 1644 * rate is different from the requested rate. Note
1645 1645 * that it works only because we do not allow rate
1646 1646 * fallback from OFDM to CCK.
1647 1647 */
1648 1648 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f;
1649 1649 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf;
1650 1650 if (mcs + 1 != pid)
1651 1651 amn->amn_retrycnt++;
1652 1652 } else
1653 1653 amn->amn_retrycnt++;
1654 1654 }
1655 1655 }
1656 1656
1657 1657 /*ARGSUSED*/
1658 1658 static void
1659 1659 rt2860_tx_intr(struct rt2860_softc *sc, int qid)
1660 1660 {
1661 1661 struct rt2860_tx_ring *ring = &sc->txq[qid];
1662 1662 struct ieee80211com *ic = &sc->sc_ic;
1663 1663 uint32_t hw;
1664 1664
1665 1665 rt2860_drain_stats_fifo(sc);
1666 1666
1667 1667 mutex_enter(&sc->sc_txlock);
1668 1668 hw = RT2860_READ(sc, RT2860_TX_DTX_IDX(qid));
1669 1669 RWN_DEBUG(RT2860_DBG_TX, "rwn: rwn_tx_intr():"
1670 1670 "hw = %x, ring->next = %x, queued = %d\n",
1671 1671 hw, ring->next, ring->queued);
1672 1672 while (ring->next != hw) {
1673 1673 struct rt2860_txd *txd = &ring->txd[ring->next];
1674 1674 struct rt2860_tx_data *data = ring->data[ring->next];
1675 1675
1676 1676 if (data != NULL) {
1677 1677 RT2860_DMA_SYNC(data->txbuf_dma, DDI_DMA_SYNC_FORDEV);
1678 1678 if (data->ni != NULL) {
1679 1679 ieee80211_free_node(data->ni);
1680 1680 data->ni = NULL;
1681 1681 }
1682 1682 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
1683 1683 ring->data[ring->next] = NULL;
1684 1684 }
1685 1685
1686 1686 txd->sdl0 &= ~LE_16(RT2860_TX_DDONE);
1687 1687
1688 1688 (void) ddi_dma_sync(ring->txdesc_dma.dma_hdl,
1689 1689 ring->next * sizeof (struct rt2860_txd),
1690 1690 sizeof (struct rt2860_txd),
1691 1691 DDI_DMA_SYNC_FORDEV);
1692 1692
1693 1693 ring->queued--;
1694 1694 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT;
1695 1695
1696 1696 if (sc->sc_need_sched &&
1697 1697 (ring->queued < RT2860_TX_RING_COUNT)) {
1698 1698 sc->sc_need_sched = 0;
1699 1699 mac_tx_update(ic->ic_mach);
1700 1700 }
1701 1701 }
1702 1702 sc->sc_tx_timer = 0;
1703 1703 mutex_exit(&sc->sc_txlock);
1704 1704 }
1705 1705
1706 1706 static void
1707 1707 rt2860_rx_intr(struct rt2860_softc *sc)
1708 1708 {
1709 1709 struct ieee80211com *ic = &sc->sc_ic;
1710 1710 struct ieee80211_node *ni;
1711 1711 struct ieee80211_frame *wh;
1712 1712 int pktlen;
1713 1713 uint8_t ant, rssi, *rxbuf;
1714 1714 mblk_t *mp0;
1715 1715
1716 1716 mutex_enter(&sc->sc_rxlock);
1717 1717 for (;;) {
1718 1718 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur];
1719 1719 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur];
1720 1720 struct rt2860_rxwi *rxwi;
1721 1721
1722 1722 (void) ddi_dma_sync(sc->rxq.rxdesc_dma.dma_hdl,
1723 1723 sc->rxq.cur * sizeof (struct rt2860_rxd),
1724 1724 sizeof (struct rt2860_rxd),
1725 1725 DDI_DMA_SYNC_FORKERNEL);
1726 1726
1727 1727 if (!(rxd->sdl0 & LE_16(RT2860_RX_DDONE))) {
1728 1728 RWN_DEBUG(RT2860_DBG_RX, "rwn: rt2860_rx_intr(): "
1729 1729 "rx done!\n");
1730 1730 break;
1731 1731 }
1732 1732
1733 1733 if (rxd->flags &
1734 1734 LE_32(RT2860_RX_CRCERR | RT2860_RX_ICVERR)) {
1735 1735 RWN_DEBUG(RT2860_DBG_RX, "rwn: rt2860_rx_intr(): "
1736 1736 "rx crc error & rx icv error!\n");
1737 1737 sc->sc_rx_err++;
1738 1738 goto skip;
1739 1739 }
1740 1740
1741 1741 if (rxd->flags & LE_32(RT2860_RX_MICERR)) {
1742 1742 RWN_DEBUG(RT2860_DBG_RX, "rwn: rt2860_rx_intr(): "
1743 1743 "rx mic error!\n");
1744 1744 sc->sc_rx_err++;
1745 1745 goto skip;
1746 1746 }
1747 1747
1748 1748 (void) ddi_dma_sync(data->rxbuf_dma.dma_hdl,
1749 1749 data->rxbuf_dma.offset,
1750 1750 data->rxbuf_dma.alength,
1751 1751 DDI_DMA_SYNC_FORCPU);
1752 1752
1753 1753 rxbuf = (uint8_t *)data->rxbuf_dma.mem_va;
1754 1754 rxd->sdp0 = LE_32(data->rxbuf_dma.cookie.dmac_address);
1755 1755 rxwi = (struct rt2860_rxwi *)rxbuf;
1756 1756 rxbuf = (uint8_t *)(rxwi + 1);
1757 1757 pktlen = LE_16(rxwi->len) & 0xfff;
1758 1758
1759 1759 mp0 = allocb(sc->sc_dmabuf_size, BPRI_MED);
1760 1760 if (mp0 == NULL) {
1761 1761 RWN_DEBUG(RT2860_DBG_RX, "rwn: rt2860_rx_intr():"
1762 1762 "alloc mblk error\n");
1763 1763 sc->sc_rx_nobuf++;
1764 1764 goto skip;
1765 1765 }
1766 1766 bcopy(rxbuf, mp0->b_rptr, pktlen);
1767 1767 mp0->b_wptr += pktlen;
1768 1768
1769 1769 wh = (struct ieee80211_frame *)mp0->b_rptr;
1770 1770
1771 1771 /* HW may insert 2 padding bytes after 802.11 header */
1772 1772 if (rxd->flags & LE_32(RT2860_RX_L2PAD)) {
1773 1773 RWN_DEBUG(RT2860_DBG_RX, "rwn: rt2860_rx_intr():"
1774 1774 "2 padding bytes after 80211 header!\n");
1775 1775 }
1776 1776
1777 1777 ant = rt2860_maxrssi_chain(sc, rxwi);
1778 1778 rssi = RT2860_RSSI_OFFSET - rxwi->rssi[ant];
1779 1779 /* grab a reference to the source node */
1780 1780 ni = ieee80211_find_rxnode(ic, wh);
1781 1781
1782 1782 (void) ieee80211_input(ic, mp0, ni, rssi, 0);
1783 1783
1784 1784 /* node is no longer needed */
1785 1785 ieee80211_free_node(ni);
1786 1786 skip:
1787 1787 rxd->sdl0 &= ~LE_16(RT2860_RX_DDONE);
1788 1788
1789 1789 (void) ddi_dma_sync(sc->rxq.rxdesc_dma.dma_hdl,
1790 1790 sc->rxq.cur * sizeof (struct rt2860_rxd),
1791 1791 sizeof (struct rt2860_rxd),
1792 1792 DDI_DMA_SYNC_FORDEV);
1793 1793
1794 1794 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT;
1795 1795 }
1796 1796 mutex_exit(&sc->sc_rxlock);
1797 1797
1798 1798 /* tell HW what we have processed */
1799 1799 RT2860_WRITE(sc, RT2860_RX_CALC_IDX,
1800 1800 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT);
1801 1801 }
1802 1802
1803 1803 static uint_t
1804 1804 rt2860_softintr(caddr_t data)
1805 1805 {
1806 1806 struct rt2860_softc *sc = (struct rt2860_softc *)data;
1807 1807
1808 1808 /*
1809 1809 * Check if the soft interrupt is triggered by another
1810 1810 * driver at the same level.
1811 1811 */
1812 1812 RT2860_GLOCK(sc);
1813 1813 if (sc->sc_rx_pend) {
1814 1814 sc->sc_rx_pend = 0;
1815 1815 RT2860_GUNLOCK(sc);
1816 1816 rt2860_rx_intr(sc);
1817 1817 return (DDI_INTR_CLAIMED);
1818 1818 }
1819 1819 RT2860_GUNLOCK(sc);
1820 1820
1821 1821 return (DDI_INTR_UNCLAIMED);
1822 1822 }
1823 1823
1824 1824 static uint_t
1825 1825 rt2860_intr(caddr_t arg)
1826 1826 {
1827 1827 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
1828 1828 uint32_t r;
1829 1829
1830 1830 RT2860_GLOCK(sc);
1831 1831
1832 1832 if ((!RT2860_IS_RUNNING(sc)) || RT2860_IS_SUSPEND(sc)) {
1833 1833 /*
1834 1834 * The hardware is not ready/present, don't touch anything.
1835 1835 * Note this can happen early on if the IRQ is shared.
1836 1836 */
1837 1837 RT2860_GUNLOCK(sc);
1838 1838 return (DDI_INTR_UNCLAIMED);
1839 1839 }
1840 1840
1841 1841 r = RT2860_READ(sc, RT2860_INT_STATUS);
1842 1842 if (r == 0xffffffff) {
1843 1843 RT2860_GUNLOCK(sc);
1844 1844 return (DDI_INTR_UNCLAIMED);
1845 1845 }
1846 1846 if (r == 0) {
1847 1847 RT2860_GUNLOCK(sc);
1848 1848 return (DDI_INTR_UNCLAIMED);
1849 1849 }
1850 1850
1851 1851 /* acknowledge interrupts */
1852 1852 RT2860_WRITE(sc, RT2860_INT_STATUS, r);
1853 1853
1854 1854 if (r & RT2860_TX_COHERENT)
1855 1855 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr()"
1856 1856 "RT2860_TX_COHERENT\n");
1857 1857
1858 1858 if (r & RT2860_RX_COHERENT)
1859 1859 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr()"
1860 1860 "RT2860_RX_COHERENT\n");
1861 1861
1862 1862 if (r & RT2860_MAC_INT_2) {
1863 1863 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1864 1864 "RT2860_MAC_INT_2\n");
1865 1865 rt2860_drain_stats_fifo(sc);
1866 1866 }
1867 1867
1868 1868 if (r & RT2860_TX_DONE_INT5) {
1869 1869 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1870 1870 "RT2860_TX_DONE_INT5\n");
1871 1871 rt2860_tx_intr(sc, 5);
1872 1872 }
1873 1873
1874 1874 if (r & RT2860_RX_DONE_INT) {
1875 1875 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr()"
1876 1876 "RT2860_RX_INT\n");
1877 1877 sc->sc_rx_pend = 1;
1878 1878 ddi_trigger_softintr(sc->sc_softintr_hdl);
1879 1879 }
1880 1880
1881 1881 if (r & RT2860_TX_DONE_INT4) {
1882 1882 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1883 1883 "RT2860_TX_DONE_INT4\n");
1884 1884 rt2860_tx_intr(sc, 4);
1885 1885 }
1886 1886
1887 1887 if (r & RT2860_TX_DONE_INT3) {
1888 1888 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1889 1889 "RT2860_TX_DONE_INT3\n");
1890 1890 rt2860_tx_intr(sc, 3);
1891 1891 }
1892 1892
1893 1893 if (r & RT2860_TX_DONE_INT2) {
1894 1894 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1895 1895 "RT2860_TX_DONE_INT2\n");
1896 1896 rt2860_tx_intr(sc, 2);
1897 1897 }
1898 1898
1899 1899 if (r & RT2860_TX_DONE_INT1) {
1900 1900 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1901 1901 "RT2860_TX_DONE_INT1\n");
1902 1902 rt2860_tx_intr(sc, 1);
1903 1903 }
1904 1904
1905 1905 if (r & RT2860_TX_DONE_INT0) {
1906 1906 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1907 1907 "RT2860_TX_DONE_INT0\n");
1908 1908 rt2860_tx_intr(sc, 0);
1909 1909 }
1910 1910
1911 1911 if (r & RT2860_MAC_INT_0) {
1912 1912 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1913 1913 "RT2860_MAC_INT_0\n");
1914 1914 struct ieee80211com *ic = &sc->sc_ic;
1915 1915 /* check if protection mode has changed */
1916 1916 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) {
1917 1917 rt2860_updateprot(ic);
1918 1918 sc->sc_ic_flags = ic->ic_flags;
1919 1919 }
1920 1920 }
1921 1921
1922 1922 if (r & RT2860_MAC_INT_3)
1923 1923 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1924 1924 "RT2860_MAC_INT_3\n");
1925 1925
1926 1926 RT2860_GUNLOCK(sc);
1927 1927
1928 1928 return (DDI_INTR_CLAIMED);
1929 1929 }
1930 1930
1931 1931 static void
1932 1932 rt2860_set_region_4(struct rt2860_softc *sc,
1933 1933 uint32_t addr, uint32_t data, int size)
1934 1934 {
1935 1935 for (; size > 0; size--, data++, addr += 4)
1936 1936 ddi_put32((sc)->sc_io_handle,
1937 1937 (uint32_t *)((uintptr_t)(sc)->sc_io_base + addr), data);
1938 1938 }
1939 1939
1940 1940 static int
1941 1941 rt2860_load_microcode(struct rt2860_softc *sc)
1942 1942 {
1943 1943 int ntries;
1944 1944 size_t size;
1945 1945 uint8_t *ucode, *fptr;
1946 1946 uint32_t off, i;
1947 1947
1948 1948 ucode = rt2860_fw_bin;
1949 1949 size = sizeof (rt2860_fw_bin);
1950 1950 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_load_microcode(): "
1951 1951 "The size of ucode is: %x\n", size);
1952 1952
1953 1953 /* set "host program ram write selection" bit */
1954 1954 RT2860_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL);
1955 1955 /* write microcode image */
1956 1956 fptr = ucode;
1957 1957 off = RT2860_FW_BASE;
1958 1958 for (i = 0; i < size; i++) {
1959 1959 rt2860_mem_write1(sc, off++, *fptr++);
1960 1960 }
1961 1961 /* kick microcontroller unit */
1962 1962 RT2860_WRITE(sc, RT2860_SYS_CTRL, 0);
1963 1963 RT2860_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET);
1964 1964
1965 1965 RT2860_WRITE(sc, RT2860_H2M_BBPAGENT, 0);
1966 1966 RT2860_WRITE(sc, RT2860_H2M_MAILBOX, 0);
1967 1967
1968 1968 /* wait until microcontroller is ready */
1969 1969 for (ntries = 0; ntries < 1000; ntries++) {
1970 1970 if (RT2860_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY)
1971 1971 break;
1972 1972 DELAY(1000);
1973 1973 }
1974 1974 if (ntries == 1000) {
1975 1975 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_load_microcode(): "
1976 1976 "timeout waiting for MCU to initialie\n");
1977 1977 return (ETIMEDOUT);
1978 1978 }
1979 1979
1980 1980 return (0);
1981 1981 }
1982 1982
1983 1983 static void
1984 1984 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr)
1985 1985 {
1986 1986 RT2860_WRITE(sc, RT2860_MAC_ADDR_DW0,
1987 1987 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
1988 1988 RT2860_WRITE(sc, RT2860_MAC_ADDR_DW1,
1989 1989 addr[4] | addr[5] << 8);
1990 1990 }
1991 1991
1992 1992 /*
1993 1993 * Send a command to the 8051 microcontroller unit.
1994 1994 */
1995 1995 static int
1996 1996 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg)
1997 1997 {
1998 1998 int ntries;
1999 1999
2000 2000 for (ntries = 0; ntries < 100; ntries++) {
2001 2001 if (!(RT2860_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY))
2002 2002 break;
2003 2003 DELAY(2);
2004 2004 }
2005 2005 if (ntries == 100)
2006 2006 return (EIO);
2007 2007
2008 2008 RT2860_WRITE(sc, RT2860_H2M_MAILBOX,
2009 2009 RT2860_H2M_BUSY | RT2860_TOKEN_NO_INTR << 16 | arg);
2010 2010 RT2860_WRITE(sc, RT2860_HOST_CMD, cmd);
2011 2011
2012 2012 return (RT2860_SUCCESS);
2013 2013 }
2014 2014
2015 2015 /*
2016 2016 * Reading and writing from/to the BBP is different from RT2560 and RT2661.
2017 2017 * We access the BBP through the 8051 microcontroller unit which means that
2018 2018 * the microcode must be loaded first.
2019 2019 */
2020 2020 static uint8_t
2021 2021 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg)
2022 2022 {
2023 2023 uint32_t val;
2024 2024 int ntries;
2025 2025
2026 2026 for (ntries = 0; ntries < 100; ntries++) {
2027 2027 if (!(RT2860_READ(sc,
2028 2028 RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK))
2029 2029 break;
2030 2030 DELAY(1);
2031 2031 }
2032 2032 if (ntries == 100) {
2033 2033 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_mcu_bbp_read():"
2034 2034 "could not read from BBP through MCU\n");
2035 2035 return (0);
2036 2036 }
2037 2037
2038 2038 RT2860_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL |
2039 2039 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8);
2040 2040
2041 2041 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0);
2042 2042 DELAY(1000);
2043 2043
2044 2044 for (ntries = 0; ntries < 100; ntries++) {
2045 2045 val = RT2860_READ(sc, RT2860_H2M_BBPAGENT);
2046 2046 if (!(val & RT2860_BBP_CSR_KICK))
2047 2047 return (val & 0xff);
2048 2048 DELAY(1);
2049 2049 }
2050 2050 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_mcu_bbp_read():"
2051 2051 "could not read from BBP through MCU\n");
2052 2052
2053 2053 return (0);
2054 2054 }
2055 2055
2056 2056 static void
2057 2057 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)
2058 2058 {
2059 2059 int ntries;
2060 2060
2061 2061 for (ntries = 0; ntries < 100; ntries++) {
2062 2062 if (!(RT2860_READ(sc,
2063 2063 RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK))
2064 2064 break;
2065 2065 DELAY(1);
2066 2066 }
2067 2067 if (ntries == 100) {
2068 2068 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_mcu_bbp_write():"
2069 2069 "could not write to BBP through MCU\n");
2070 2070 return;
2071 2071 }
2072 2072
2073 2073 RT2860_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL |
2074 2074 RT2860_BBP_CSR_KICK | reg << 8 | val);
2075 2075
2076 2076 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0);
2077 2077 DELAY(1000);
2078 2078 }
2079 2079
2080 2080 static int
2081 2081 rt2860_bbp_init(struct rt2860_softc *sc)
2082 2082 {
2083 2083 int i, ntries;
2084 2084
2085 2085 /* wait for BBP to wake up */
2086 2086 for (ntries = 0; ntries < 20; ntries++) {
2087 2087 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0);
2088 2088 if (bbp0 != 0 && bbp0 != 0xff)
2089 2089 break;
2090 2090 }
2091 2091 if (ntries == 20) {
2092 2092 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_bbp_init():"
2093 2093 "timeout waiting for BBP to wake up\n");
2094 2094 return (ETIMEDOUT);
2095 2095 }
2096 2096
2097 2097 /* initialize BBP registers to default values */
2098 2098 for (i = 0; i < 12; i++) {
2099 2099 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg,
2100 2100 rt2860_def_bbp[i].val);
2101 2101 }
2102 2102
2103 2103 /* fix BBP69 and BBP73 for RT2860C */
2104 2104 if (sc->mac_rev == 0x28600100) {
2105 2105 rt2860_mcu_bbp_write(sc, 69, 0x16);
2106 2106 rt2860_mcu_bbp_write(sc, 73, 0x12);
2107 2107 }
2108 2108
2109 2109 return (0);
2110 2110 }
2111 2111
2112 2112 static void
2113 2113 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val)
2114 2114 {
2115 2115 uint32_t tmp;
2116 2116 int ntries;
2117 2117
2118 2118 for (ntries = 0; ntries < 100; ntries++) {
2119 2119 if (!(RT2860_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL))
2120 2120 break;
2121 2121 DELAY(1);
2122 2122 }
2123 2123 if (ntries == 100) {
2124 2124 RWN_DEBUG(RT2860_DBG_FW, "rwn: rwn_init()"
2125 2125 "could not write to RF\n");
2126 2126 return;
2127 2127 }
2128 2128
2129 2129 /* RF registers are 24-bit on the RT2860 */
2130 2130 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT |
2131 2131 (val & 0x3fffff) << 2 | (reg & 3);
2132 2132 RT2860_WRITE(sc, RT2860_RF_CSR_CFG0, tmp);
2133 2133 }
2134 2134
2135 2135 static void
2136 2136 rt2860_select_chan_group(struct rt2860_softc *sc, int group)
2137 2137 {
2138 2138 uint32_t tmp;
2139 2139
2140 2140 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]);
2141 2141 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]);
2142 2142 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]);
2143 2143 rt2860_mcu_bbp_write(sc, 82, (group == 0) ? 0x62 : 0xf2);
2144 2144
2145 2145 tmp = RT2860_READ(sc, RT2860_TX_BAND_CFG);
2146 2146 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P);
2147 2147 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P;
2148 2148 RT2860_WRITE(sc, RT2860_TX_BAND_CFG, tmp);
2149 2149
2150 2150 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */
2151 2151 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN;
2152 2152 if (group == 0) { /* 2GHz */
2153 2153 tmp |= RT2860_PA_PE_G0_EN | RT2860_LNA_PE_G0_EN;
2154 2154 if (sc->ntxchains > 1)
2155 2155 tmp |= RT2860_PA_PE_G1_EN;
2156 2156 if (sc->nrxchains > 1)
2157 2157 tmp |= RT2860_LNA_PE_G1_EN;
2158 2158 } else { /* 5GHz */
2159 2159 tmp |= RT2860_PA_PE_A0_EN | RT2860_LNA_PE_A0_EN;
2160 2160 if (sc->ntxchains > 1)
2161 2161 tmp |= RT2860_PA_PE_A1_EN;
2162 2162 if (sc->nrxchains > 1)
2163 2163 tmp |= RT2860_LNA_PE_A1_EN;
2164 2164 }
2165 2165 RT2860_WRITE(sc, RT2860_TX_PIN_CFG, tmp);
2166 2166
2167 2167 rt2860_mcu_bbp_write(sc, 66, 0x2e + sc->lna[group]);
2168 2168 }
2169 2169 static void
2170 2170 rt2860_set_chan(struct rt2860_softc *sc, struct ieee80211_channel *c)
2171 2171 {
2172 2172 struct ieee80211com *ic = &sc->sc_ic;
2173 2173 const struct rfprog *rfprog = rt2860_rf2850;
2174 2174 uint_t i, chan, group;
2175 2175 uint8_t txpow1, txpow2;
2176 2176 uint32_t r2, r3, r4;
2177 2177
2178 2178 chan = ieee80211_chan2ieee(ic, c);
2179 2179 if (chan == 0 || chan == IEEE80211_CHAN_ANY) {
2180 2180 RWN_DEBUG(RT2860_DBG_FW, "Unkonwn channel!\n");
2181 2181 return;
2182 2182 }
2183 2183
2184 2184 /* find the settings for this channel (we know it exists) */
2185 2185 for (i = 0; rfprog[i].chan != chan; )
2186 2186 i++;
2187 2187
2188 2188 r2 = rfprog[i].r2;
2189 2189 if (sc->ntxchains == 1)
2190 2190 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */
2191 2191 if (sc->nrxchains == 1)
2192 2192 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */
2193 2193 else if (sc->nrxchains == 2)
2194 2194 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */
2195 2195
2196 2196 /* use Tx power values from EEPROM */
2197 2197 txpow1 = sc->txpow1[i];
2198 2198 txpow2 = sc->txpow2[i];
2199 2199 if (IEEE80211_IS_CHAN_5GHZ(c)) {
2200 2200 txpow1 = txpow1 << 1 | 1;
2201 2201 txpow2 = txpow2 << 1 | 1;
2202 2202 }
2203 2203 r3 = rfprog[i].r3 | txpow1 << 7;
2204 2204 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4;
2205 2205
2206 2206 rt2860_rf_write(sc, RAL_RF1, rfprog[i].r1);
2207 2207 rt2860_rf_write(sc, RAL_RF2, r2);
2208 2208 rt2860_rf_write(sc, RAL_RF3, r3);
2209 2209 rt2860_rf_write(sc, RAL_RF4, r4);
2210 2210
2211 2211 DELAY(200);
2212 2212
2213 2213 rt2860_rf_write(sc, RAL_RF1, rfprog[i].r1);
2214 2214 rt2860_rf_write(sc, RAL_RF2, r2);
2215 2215 rt2860_rf_write(sc, RAL_RF3, r3 | 1);
2216 2216 rt2860_rf_write(sc, RAL_RF4, r4);
2217 2217
2218 2218 DELAY(200);
2219 2219
2220 2220 rt2860_rf_write(sc, RAL_RF1, rfprog[i].r1);
2221 2221 rt2860_rf_write(sc, RAL_RF2, r2);
2222 2222 rt2860_rf_write(sc, RAL_RF3, r3);
2223 2223 rt2860_rf_write(sc, RAL_RF4, r4);
2224 2224
2225 2225 /* 802.11a uses a 16 microseconds short interframe space */
2226 2226 sc->sifs = IEEE80211_IS_CHAN_5GHZ(c) ? 16 : 10;
2227 2227
2228 2228 /* determine channel group */
2229 2229 if (chan <= 14)
2230 2230 group = 0;
2231 2231 else if (chan <= 64)
2232 2232 group = 1;
2233 2233 else if (chan <= 128)
2234 2234 group = 2;
2235 2235 else
2236 2236 group = 3;
2237 2237
2238 2238 /* XXX necessary only when group has changed! */
2239 2239 rt2860_select_chan_group(sc, group);
2240 2240
2241 2241 DELAY(1000);
2242 2242 }
2243 2243
2244 2244 static void
2245 2245 rt2860_updateprot(struct ieee80211com *ic)
2246 2246 {
2247 2247 struct rt2860_softc *sc = (struct rt2860_softc *)ic;
2248 2248 uint32_t tmp;
2249 2249
2250 2250 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL;
2251 2251 /* setup protection frame rate (MCS code) */
2252 2252 tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ? 0 : 3;
2253 2253
2254 2254 /* CCK frames don't require protection */
2255 2255 RT2860_WRITE(sc, RT2860_CCK_PROT_CFG, tmp);
2256 2256
2257 2257 if (ic->ic_flags & IEEE80211_F_USEPROT) {
2258 2258 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
2259 2259 tmp |= RT2860_PROT_CTRL_RTS_CTS;
2260 2260 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
2261 2261 tmp |= RT2860_PROT_CTRL_CTS;
2262 2262 }
2263 2263 RT2860_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp);
2264 2264 }
2265 2265
2266 2266 static void
2267 2267 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which)
2268 2268 {
2269 2269 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS,
2270 2270 which | (sc->leds & 0x7f));
2271 2271 }
2272 2272
2273 2273 static int
2274 2274 rt2860_init(struct rt2860_softc *sc)
2275 2275 {
2276 2276 #define N(a) (sizeof (a) / sizeof ((a)[0]))
2277 2277 struct ieee80211com *ic;
2278 2278 int i, err, qid, ridx, ntries;
2279 2279 uint8_t bbp1, bbp3;
2280 2280 uint32_t tmp;
2281 2281
2282 2282 ic = &sc->sc_ic;
2283 2283
2284 2284 rt2860_stop(sc);
2285 2285 tmp = RT2860_READ(sc, RT2860_WPDMA_GLO_CFG);
2286 2286 tmp &= 0xff0;
2287 2287 RT2860_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp | RT2860_TX_WB_DDONE);
2288 2288
2289 2289 RT2860_WRITE(sc, RT2860_WPDMA_RST_IDX, 0xffffffff);
2290 2290
2291 2291 /* PBF hardware reset */
2292 2292 RT2860_WRITE(sc, RT2860_SYS_CTRL, 0xe1f);
2293 2293 RT2860_WRITE(sc, RT2860_SYS_CTRL, 0xe00);
2294 2294
2295 2295 if (!(sc->sc_flags & RT2860_FWLOADED)) {
2296 2296 if ((err = rt2860_load_microcode(sc)) != 0) {
2297 2297 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_init(): "
2298 2298 "could not load 8051 microcode\n");
2299 2299 rt2860_stop(sc);
2300 2300 return (err);
2301 2301 }
2302 2302 RT2860_GLOCK(sc);
2303 2303 sc->sc_flags |= RT2860_FWLOADED;
2304 2304 RT2860_GUNLOCK(sc);
2305 2305 }
2306 2306
2307 2307 rt2860_set_macaddr(sc, ic->ic_macaddr);
2308 2308
2309 2309 /* init Tx power for all Tx rates (from EEPROM) */
2310 2310 for (ridx = 0; ridx < 5; ridx++) {
2311 2311 if (sc->txpow20mhz[ridx] == 0xffffffff)
2312 2312 continue;
2313 2313 RT2860_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]);
2314 2314 }
2315 2315
2316 2316 for (ntries = 0; ntries < 100; ntries++) {
2317 2317 tmp = RT2860_READ(sc, RT2860_WPDMA_GLO_CFG);
2318 2318 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
2319 2319 break;
2320 2320 DELAY(1000);
2321 2321 }
2322 2322 if (ntries == 100) {
2323 2323 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rt2860_init():"
2324 2324 "timeout waiting for DMA engine\n");
2325 2325 rt2860_stop(sc);
2326 2326 return (ETIMEDOUT);
2327 2327 }
2328 2328 tmp &= 0xff0;
2329 2329 RT2860_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp | RT2860_TX_WB_DDONE);
2330 2330
2331 2331 /* reset Rx ring and all 6 Tx rings */
2332 2332 RT2860_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f);
2333 2333
2334 2334 /* PBF hardware reset */
2335 2335 RT2860_WRITE(sc, RT2860_SYS_CTRL, 0xe1f);
2336 2336 RT2860_WRITE(sc, RT2860_SYS_CTRL, 0xe00);
2337 2337
2338 2338 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL,
2339 2339 RT2860_BBP_HRST | RT2860_MAC_SRST);
2340 2340 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL, 0);
2341 2341
2342 2342 for (i = 0; i < N(rt2860_def_mac); i++)
2343 2343 RT2860_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val);
2344 2344
2345 2345 /* wait while MAC is busy */
2346 2346 for (ntries = 0; ntries < 100; ntries++) {
2347 2347 if (!(RT2860_READ(sc, RT2860_MAC_STATUS_REG) &
2348 2348 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY)))
2349 2349 break;
2350 2350 DELAY(1000);
2351 2351 }
2352 2352 if (ntries == 100) {
2353 2353 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_init():"
2354 2354 "timeout waiting for MAC\n");
2355 2355 rt2860_stop(sc);
2356 2356 return (ETIMEDOUT);
2357 2357 }
2358 2358
2359 2359 /* clear Host to MCU mailbox */
2360 2360 RT2860_WRITE(sc, RT2860_H2M_BBPAGENT, 0);
2361 2361 RT2860_WRITE(sc, RT2860_H2M_MAILBOX, 0);
2362 2362
2363 2363 if ((err = rt2860_bbp_init(sc)) != 0) {
2364 2364 rt2860_stop(sc);
2365 2365 return (err);
2366 2366 }
2367 2367
2368 2368 /* init Tx rings (4 EDCAs + HCCA + Mgt) */
2369 2369 for (qid = 0; qid < 6; qid++) {
2370 2370 RT2860_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr);
2371 2371 RT2860_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT);
2372 2372 RT2860_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0);
2373 2373 }
2374 2374
2375 2375 /* init Rx ring */
2376 2376 RT2860_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr);
2377 2377 RT2860_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT);
2378 2378 RT2860_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1);
2379 2379
2380 2380 /* setup maximum buffer sizes */
2381 2381 RT2860_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 |
2382 2382 (sc->sc_dmabuf_size - sizeof (struct rt2860_rxwi) - 2));
2383 2383
2384 2384 for (ntries = 0; ntries < 100; ntries++) {
2385 2385 tmp = RT2860_READ(sc, RT2860_WPDMA_GLO_CFG);
2386 2386 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
2387 2387 break;
2388 2388 DELAY(1000);
2389 2389 }
2390 2390 if (ntries == 100) {
2391 2391 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rt2860_init():"
2392 2392 "timeout waiting for DMA engine\n");
2393 2393 rt2860_stop(sc);
2394 2394 return (ETIMEDOUT);
2395 2395 }
2396 2396 tmp &= 0xff0;
2397 2397 RT2860_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp | RT2860_TX_WB_DDONE);
2398 2398
2399 2399 /* disable interrupts mitigation */
2400 2400 RT2860_WRITE(sc, RT2860_DELAY_INT_CFG, 0);
2401 2401
2402 2402 /* write vendor-specific BBP values (from EEPROM) */
2403 2403 for (i = 0; i < 8; i++) {
2404 2404 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff)
2405 2405 continue;
2406 2406 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);
2407 2407 }
2408 2408
2409 2409 /* send LEDs operating mode to microcontroller */
2410 2410 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0]);
2411 2411 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1]);
2412 2412 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2]);
2413 2413
2414 2414 /* disable non-existing Rx chains */
2415 2415 bbp3 = rt2860_mcu_bbp_read(sc, 3);
2416 2416 bbp3 &= ~(1 << 3 | 1 << 4);
2417 2417 if (sc->nrxchains == 2)
2418 2418 bbp3 |= 1 << 3;
2419 2419 else if (sc->nrxchains == 3)
2420 2420 bbp3 |= 1 << 4;
2421 2421 rt2860_mcu_bbp_write(sc, 3, bbp3);
2422 2422
2423 2423 /* disable non-existing Tx chains */
2424 2424 bbp1 = rt2860_mcu_bbp_read(sc, 1);
2425 2425 if (sc->ntxchains == 1)
2426 2426 bbp1 &= ~(1 << 3 | 1 << 4);
2427 2427 rt2860_mcu_bbp_write(sc, 1, bbp1);
2428 2428
2429 2429 /* select default channel */
2430 2430 rt2860_set_chan(sc, ic->ic_curchan);
2431 2431
2432 2432 /* XXX not clear what the following 8051 command does.. */
2433 2433 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BOOT, 0);
2434 2434
2435 2435 /* set RTS threshold */
2436 2436 tmp = RT2860_READ(sc, RT2860_TX_RTS_CFG);
2437 2437 tmp &= ~0xffff00;
2438 2438 tmp |= ic->ic_rtsthreshold << 8;
2439 2439
2440 2440 /* setup initial protection mode */
2441 2441 sc->sc_ic_flags = ic->ic_flags;
2442 2442 rt2860_updateprot(ic);
2443 2443
2444 2444 /* enable Tx/Rx DMA engine */
2445 2445 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN);
2446 2446 for (ntries = 0; ntries < 200; ntries++) {
2447 2447 tmp = RT2860_READ(sc, RT2860_WPDMA_GLO_CFG);
2448 2448 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
2449 2449 break;
2450 2450 DELAY(1000);
2451 2451 }
2452 2452 if (ntries == 200) {
2453 2453 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rt2860_int():"
2454 2454 "timeout waiting for DMA engine\n");
2455 2455 rt2860_stop(sc);
2456 2456 return (ETIMEDOUT);
2457 2457 }
2458 2458
2459 2459 DELAY(50);
2460 2460
2461 2461 tmp |= RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN |
2462 2462 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT;
2463 2463 RT2860_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
2464 2464
2465 2465 /* turn radio LED on */
2466 2466 rt2860_set_leds(sc, RT2860_LED_RADIO);
2467 2467
2468 2468 /* set Rx filter */
2469 2469 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR;
2470 2470 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2471 2471 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL |
2472 2472 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK |
2473 2473 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV |
2474 2474 RT2860_DROP_CFACK | RT2860_DROP_CFEND;
2475 2475 if (ic->ic_opmode == IEEE80211_M_STA)
2476 2476 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL;
2477 2477 }
2478 2478 RT2860_WRITE(sc, RT2860_RX_FILTR_CFG, tmp);
2479 2479
2480 2480 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL,
2481 2481 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
2482 2482
2483 2483 /* clear pending interrupts */
2484 2484 RT2860_WRITE(sc, RT2860_INT_STATUS, 0xffffffff);
2485 2485 /* enable interrupts */
2486 2486 RT2860_WRITE(sc, RT2860_INT_MASK, 0x3fffc);
2487 2487
2488 2488 if (sc->sc_flags & RT2860_ADVANCED_PS)
2489 2489 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel);
2490 2490
2491 2491 return (DDI_SUCCESS);
2492 2492 }
2493 2493
2494 2494 static int
2495 2495 rt2860_quiesce(dev_info_t *dip)
2496 2496 {
2497 2497 struct rt2860_softc *sc;
2498 2498
2499 2499 sc = ddi_get_soft_state(rt2860_soft_state_p, ddi_get_instance(dip));
2500 2500 if (sc == NULL)
2501 2501 return (DDI_FAILURE);
2502 2502
2503 2503 #ifdef DEBUG
2504 2504 rt2860_dbg_flags = 0;
2505 2505 #endif
2506 2506
2507 2507 /*
2508 2508 * No more blocking is allowed while we are in quiesce(9E) entry point
2509 2509 */
2510 2510 sc->sc_flags |= RT2860_F_QUIESCE;
2511 2511
2512 2512 /*
2513 2513 * Disable and mask all interrupts
2514 2514 */
2515 2515 rt2860_stop(sc);
2516 2516 return (DDI_SUCCESS);
2517 2517 }
2518 2518
2519 2519 static void
2520 2520 rt2860_stop(struct rt2860_softc *sc)
2521 2521 {
2522 2522 int qid;
2523 2523 uint32_t tmp;
2524 2524
2525 2525 /* by pass if it's quiesced */
2526 2526 if (!(sc->sc_flags & RT2860_F_QUIESCE))
2527 2527 RT2860_GLOCK(sc);
2528 2528 if (sc->sc_flags == RT2860_F_RUNNING)
2529 2529 rt2860_set_leds(sc, 0); /* turn all LEDs off */
2530 2530 sc->sc_tx_timer = 0;
2531 2531 /* by pass if it's quiesced */
2532 2532 if (!(sc->sc_flags & RT2860_F_QUIESCE))
2533 2533 RT2860_GUNLOCK(sc);
2534 2534
2535 2535 /* clear RX WCID search table */
2536 2536 rt2860_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512);
2537 2537 /* clear pairwise key table */
2538 2538 rt2860_set_region_4(sc, RT2860_PKEY(0), 0, 2048);
2539 2539 /* clear IV/EIV table */
2540 2540 rt2860_set_region_4(sc, RT2860_IVEIV(0), 0, 512);
2541 2541 /* clear WCID attribute table */
2542 2542 rt2860_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 256);
2543 2543 /* clear shared key table */
2544 2544 rt2860_set_region_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32);
2545 2545 /* clear shared key mode */
2546 2546 rt2860_set_region_4(sc, RT2860_SKEY_MODE_0_7, 0, 4);
2547 2547
2548 2548 /* disable interrupts */
2549 2549 RT2860_WRITE(sc, RT2860_INT_MASK, 0);
2550 2550
2551 2551 /* disable Rx */
2552 2552 tmp = RT2860_READ(sc, RT2860_MAC_SYS_CTRL);
2553 2553 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
2554 2554 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp);
2555 2555
2556 2556 /* reset adapter */
2557 2557 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL,
2558 2558 RT2860_BBP_HRST | RT2860_MAC_SRST);
2559 2559 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL, 0);
2560 2560
2561 2561 /* reset Tx and Rx rings (and reclaim TXWIs) */
2562 2562 for (qid = 0; qid < 6; qid++)
2563 2563 rt2860_reset_tx_ring(sc, &sc->txq[qid]);
2564 2564 rt2860_reset_rx_ring(sc, &sc->rxq);
2565 2565
2566 2566 /* by pass if it's quiesced */
2567 2567 if (!(sc->sc_flags & RT2860_F_QUIESCE))
2568 2568 RT2860_GLOCK(sc);
2569 2569 sc->sc_flags &= ~RT2860_UPD_BEACON;
2570 2570 /* by pass if it's quiesced */
2571 2571 if (!(sc->sc_flags & RT2860_F_QUIESCE))
2572 2572 RT2860_GUNLOCK(sc);
2573 2573 }
2574 2574
2575 2575 static int
2576 2576 rt2860_m_start(void *arg)
2577 2577 {
2578 2578 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2579 2579 struct ieee80211com *ic = &sc->sc_ic;
2580 2580 int err;
2581 2581
2582 2582 err = rt2860_init(sc);
2583 2583 if (err != DDI_SUCCESS) {
2584 2584 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_m_start():"
2585 2585 "Hardware initialization failed\n");
2586 2586 goto fail1;
2587 2587 }
2588 2588
2589 2589 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
2590 2590
2591 2591 RT2860_GLOCK(sc);
2592 2592 sc->sc_flags |= RT2860_F_RUNNING;
2593 2593 RT2860_GUNLOCK(sc);
2594 2594
2595 2595 return (err);
2596 2596 fail1:
2597 2597 rt2860_stop(sc);
2598 2598 return (err);
2599 2599 }
2600 2600
2601 2601 static void
2602 2602 rt2860_m_stop(void *arg)
2603 2603 {
2604 2604 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2605 2605
2606 2606 (void) rt2860_stop(sc);
2607 2607
2608 2608 ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1);
2609 2609
2610 2610 RT2860_GLOCK(sc);
2611 2611 sc->sc_flags &= ~RT2860_F_RUNNING;
2612 2612 RT2860_GUNLOCK(sc);
2613 2613 }
2614 2614
2615 2615 static void
2616 2616 rt2860_m_ioctl(void* arg, queue_t *wq, mblk_t *mp)
2617 2617 {
2618 2618 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2619 2619 struct ieee80211com *ic = &sc->sc_ic;
2620 2620 int err;
2621 2621
2622 2622 err = ieee80211_ioctl(ic, wq, mp);
2623 2623 RT2860_GLOCK(sc);
2624 2624 if (err == ENETRESET) {
2625 2625 if (ic->ic_des_esslen) {
2626 2626 if (RT2860_IS_RUNNING(sc)) {
2627 2627 RT2860_GUNLOCK(sc);
2628 2628 (void) rt2860_init(sc);
2629 2629 (void) ieee80211_new_state(ic,
2630 2630 IEEE80211_S_SCAN, -1);
2631 2631 RT2860_GLOCK(sc);
2632 2632 }
2633 2633 }
2634 2634 }
2635 2635 RT2860_GUNLOCK(sc);
2636 2636 }
2637 2637
2638 2638 /*
2639 2639 * Call back function for get/set proporty
2640 2640 */
2641 2641 static int
2642 2642 rt2860_m_getprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
2643 2643 uint_t wldp_length, void *wldp_buf)
2644 2644 {
2645 2645 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2646 2646 int err = 0;
2647 2647
2648 2648 err = ieee80211_getprop(&sc->sc_ic, pr_name, wldp_pr_num,
2649 2649 wldp_length, wldp_buf);
2650 2650
2651 2651 return (err);
2652 2652 }
2653 2653
2654 2654 static void
2655 2655 rt2860_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
2656 2656 mac_prop_info_handle_t prh)
2657 2657 {
2658 2658 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2659 2659
2660 2660 ieee80211_propinfo(&sc->sc_ic, pr_name, wldp_pr_num, prh);
2661 2661 }
2662 2662
2663 2663 static int
2664 2664 rt2860_m_setprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
2665 2665 uint_t wldp_length, const void *wldp_buf)
2666 2666 {
2667 2667 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2668 2668 ieee80211com_t *ic = &sc->sc_ic;
2669 2669 int err;
2670 2670
2671 2671 err = ieee80211_setprop(ic, pr_name, wldp_pr_num, wldp_length,
2672 2672 wldp_buf);
2673 2673 RT2860_GLOCK(sc);
2674 2674 if (err == ENETRESET) {
2675 2675 if (ic->ic_des_esslen) {
2676 2676 if (RT2860_IS_RUNNING(sc)) {
2677 2677 RT2860_GUNLOCK(sc);
2678 2678 (void) rt2860_init(sc);
2679 2679 (void) ieee80211_new_state(ic,
2680 2680 IEEE80211_S_SCAN, -1);
2681 2681 RT2860_GLOCK(sc);
2682 2682 }
2683 2683 }
2684 2684 err = 0;
2685 2685 }
2686 2686 RT2860_GUNLOCK(sc);
2687 2687 return (err);
2688 2688 }
2689 2689
2690 2690 static mblk_t *
2691 2691 rt2860_m_tx(void *arg, mblk_t *mp)
2692 2692 {
2693 2693 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2694 2694 struct ieee80211com *ic = &sc->sc_ic;
2695 2695 mblk_t *next;
2696 2696
2697 2697 if (RT2860_IS_SUSPEND(sc)) {
2698 2698 freemsgchain(mp);
2699 2699 return (NULL);
2700 2700 }
2701 2701
2702 2702 /*
2703 2703 * No data frames go out unless we're associated; this
2704 2704 * should not happen as the 802.11 layer does not enable
2705 2705 * the xmit queue until we enter the RUN state.
2706 2706 */
2707 2707 if (ic->ic_state != IEEE80211_S_RUN) {
2708 2708 RWN_DEBUG(RT2860_DBG_TX, "rwn: rt2860_tx_data(): "
2709 2709 "discard, state %u\n", ic->ic_state);
2710 2710 freemsgchain(mp);
2711 2711 return (NULL);
2712 2712 }
2713 2713
2714 2714 while (mp != NULL) {
2715 2715 next = mp->b_next;
2716 2716 mp->b_next = NULL;
2717 2717 if (rt2860_send(ic, mp, IEEE80211_FC0_TYPE_DATA) !=
2718 2718 DDI_SUCCESS) {
2719 2719 mp->b_next = next;
2720 2720 break;
2721 2721 }
2722 2722 mp = next;
2723 2723 }
2724 2724 return (mp);
2725 2725 }
2726 2726
2727 2727 /*ARGSUSED*/
2728 2728 static int
2729 2729 rt2860_m_unicst(void *arg, const uint8_t *macaddr)
2730 2730 {
2731 2731 return (ENOTSUP);
2732 2732 }
2733 2733
2734 2734 /*ARGSUSED*/
2735 2735 static int
2736 2736 rt2860_m_multicst(void *arg, boolean_t add, const uint8_t *mca)
2737 2737 {
2738 2738 return (ENOTSUP);
2739 2739 }
2740 2740
2741 2741 /*ARGSUSED*/
2742 2742 static int
2743 2743 rt2860_m_promisc(void *arg, boolean_t on)
2744 2744 {
2745 2745 return (0);
2746 2746 }
2747 2747
2748 2748 static int
2749 2749 rt2860_m_stat(void *arg, uint_t stat, uint64_t *val)
2750 2750 {
2751 2751 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2752 2752 ieee80211com_t *ic = &sc->sc_ic;
2753 2753 ieee80211_node_t *ni = ic->ic_bss;
2754 2754 struct ieee80211_rateset *rs = &ni->in_rates;
2755 2755
2756 2756 RT2860_GLOCK(sc);
2757 2757 switch (stat) {
2758 2758 case MAC_STAT_IFSPEED:
2759 2759 *val = ((ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) ?
2760 2760 (rs->ir_rates[ni->in_txrate] & IEEE80211_RATE_VAL)
2761 2761 : ic->ic_fixed_rate) / 2 * 1000000;
2762 2762 break;
2763 2763 case MAC_STAT_NOXMTBUF:
2764 2764 *val = sc->sc_tx_nobuf;
2765 2765 break;
2766 2766 case MAC_STAT_NORCVBUF:
2767 2767 *val = sc->sc_rx_nobuf;
2768 2768 break;
2769 2769 case MAC_STAT_IERRORS:
2770 2770 *val = sc->sc_rx_err;
2771 2771 break;
2772 2772 case MAC_STAT_RBYTES:
2773 2773 *val = ic->ic_stats.is_rx_bytes;
2774 2774 break;
2775 2775 case MAC_STAT_IPACKETS:
2776 2776 *val = ic->ic_stats.is_rx_frags;
2777 2777 break;
2778 2778 case MAC_STAT_OBYTES:
2779 2779 *val = ic->ic_stats.is_tx_bytes;
2780 2780 break;
2781 2781 case MAC_STAT_OPACKETS:
2782 2782 *val = ic->ic_stats.is_tx_frags;
2783 2783 break;
2784 2784 case MAC_STAT_OERRORS:
2785 2785 case WIFI_STAT_TX_FAILED:
2786 2786 *val = sc->sc_tx_err;
2787 2787 break;
2788 2788 case WIFI_STAT_TX_RETRANS:
2789 2789 *val = sc->sc_tx_retries;
2790 2790 break;
2791 2791 case WIFI_STAT_FCS_ERRORS:
2792 2792 case WIFI_STAT_WEP_ERRORS:
2793 2793 case WIFI_STAT_TX_FRAGS:
2794 2794 case WIFI_STAT_MCAST_TX:
2795 2795 case WIFI_STAT_RTS_SUCCESS:
2796 2796 case WIFI_STAT_RTS_FAILURE:
2797 2797 case WIFI_STAT_ACK_FAILURE:
2798 2798 case WIFI_STAT_RX_FRAGS:
2799 2799 case WIFI_STAT_MCAST_RX:
2800 2800 case WIFI_STAT_RX_DUPS:
2801 2801 RT2860_GUNLOCK(sc);
2802 2802 return (ieee80211_stat(ic, stat, val));
2803 2803 default:
2804 2804 RT2860_GUNLOCK(sc);
2805 2805 return (ENOTSUP);
2806 2806 }
2807 2807 RT2860_GUNLOCK(sc);
2808 2808
2809 2809 return (0);
2810 2810 }
2811 2811
2812 2812 static int
2813 2813 rt2860_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
2814 2814 {
2815 2815 struct rt2860_softc *sc;
2816 2816 struct ieee80211com *ic;
2817 2817 int i, err, qid, ntries, instance;
2818 2818 uint8_t cachelsz;
2819 2819 uint16_t command, vendor_id, device_id;
2820 2820 char strbuf[32];
2821 2821 wifi_data_t wd = { 0 };
2822 2822 mac_register_t *macp;
2823 2823
2824 2824 switch (cmd) {
2825 2825 case DDI_ATTACH:
2826 2826 break;
2827 2827 case DDI_RESUME:
2828 2828 sc = ddi_get_soft_state(rt2860_soft_state_p,
2829 2829 ddi_get_instance(devinfo));
2830 2830 ASSERT(sc != NULL);
2831 2831 RT2860_GLOCK(sc);
2832 2832 sc->sc_flags &= ~RT2860_F_SUSPEND;
2833 2833 RT2860_GUNLOCK(sc);
2834 2834 if (RT2860_IS_RUNNING(sc))
2835 2835 (void) rt2860_init(sc);
2836 2836 RWN_DEBUG(RT2860_DBG_RESUME, "rwn: rt2860_attach(): "
2837 2837 "resume now\n");
2838 2838 return (DDI_SUCCESS);
2839 2839 default:
2840 2840 return (DDI_FAILURE);
2841 2841 }
2842 2842
2843 2843 instance = ddi_get_instance(devinfo);
2844 2844
2845 2845 err = ddi_soft_state_zalloc(rt2860_soft_state_p, instance);
2846 2846 if (err != DDI_SUCCESS) {
2847 2847 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2848 2848 "unable to alloc soft_state_p\n");
2849 2849 return (err);
2850 2850 }
2851 2851
2852 2852 sc = ddi_get_soft_state(rt2860_soft_state_p, instance);
2853 2853 ic = (ieee80211com_t *)&sc->sc_ic;
2854 2854 sc->sc_dev = devinfo;
2855 2855
2856 2856 /* pci configuration */
2857 2857 err = ddi_regs_map_setup(devinfo, 0, &sc->sc_cfg_base, 0, 0,
2858 2858 &rwn_csr_accattr, &sc->sc_cfg_handle);
2859 2859 if (err != DDI_SUCCESS) {
2860 2860 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2861 2861 "ddi_regs_map_setup() failed");
2862 2862 goto fail1;
2863 2863 }
2864 2864
2865 2865 cachelsz = ddi_get8(sc->sc_cfg_handle,
2866 2866 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_CACHE_LINESZ));
2867 2867 if (cachelsz == 0)
2868 2868 cachelsz = 0x10;
2869 2869 sc->sc_cachelsz = cachelsz << 2;
2870 2870 sc->sc_dmabuf_size = roundup(IEEE80211_MAX_LEN, sc->sc_cachelsz);
2871 2871
2872 2872 vendor_id = ddi_get16(sc->sc_cfg_handle,
2873 2873 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_VENID));
2874 2874 device_id = ddi_get16(sc->sc_cfg_handle,
2875 2875 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_DEVID));
2876 2876 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2877 2877 "vendor 0x%x, device id 0x%x, cache size %d\n",
2878 2878 vendor_id, device_id, cachelsz);
2879 2879
2880 2880 /*
2881 2881 * Enable response to memory space accesses,
2882 2882 * and enabe bus master.
2883 2883 */
2884 2884 command = PCI_COMM_MAE | PCI_COMM_ME;
2885 2885 ddi_put16(sc->sc_cfg_handle,
2886 2886 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_COMM),
2887 2887 command);
2888 2888 ddi_put8(sc->sc_cfg_handle,
2889 2889 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_LATENCY_TIMER), 0xa8);
2890 2890 ddi_put8(sc->sc_cfg_handle,
2891 2891 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_ILINE), 0x10);
2892 2892
2893 2893 /* pci i/o space */
2894 2894 err = ddi_regs_map_setup(devinfo, 1,
2895 2895 &sc->sc_io_base, 0, 0, &rwn_csr_accattr, &sc->sc_io_handle);
2896 2896 if (err != DDI_SUCCESS) {
2897 2897 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2898 2898 "ddi_regs_map_setup() failed");
2899 2899 goto fail2;
2900 2900 }
2901 2901 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2902 2902 "PCI configuration is done successfully\n");
2903 2903
2904 2904 sc->amrr.amrr_min_success_threshold = 1;
2905 2905 sc->amrr.amrr_max_success_threshold = 15;
2906 2906
2907 2907 /* wait for NIC to initialize */
2908 2908 for (ntries = 0; ntries < 100; ntries++) {
2909 2909 sc->mac_rev = RT2860_READ(sc, RT2860_ASIC_VER_ID);
2910 2910 if (sc->mac_rev != 0 && sc->mac_rev != 0xffffffff)
2911 2911 break;
2912 2912 DELAY(10);
2913 2913 }
2914 2914 if (ntries == 100) {
2915 2915 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2916 2916 "timeout waiting for NIC initialize\n");
2917 2917 return (DDI_FAILURE);
2918 2918 }
2919 2919
2920 2920 if ((sc->mac_rev >> 16) != 0x2860 &&
2921 2921 (device_id == PRODUCT_RALINK_RT2890 ||
2922 2922 device_id == PRODUCT_RALINK_RT2790 ||
2923 2923 device_id == PRODUCT_AWT_RT2890))
2924 2924 sc->sc_flags |= RT2860_ADVANCED_PS;
2925 2925
2926 2926 /* retrieve RF rev. no and various other things from EEPROM */
2927 2927 (void) rt2860_read_eeprom(sc);
2928 2928 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2929 2929 "MAC/BBP RT%X (rev 0x%04X), RF %s (%dT%dR)\n",
2930 2930 sc->mac_rev >> 16, sc->mac_rev & 0xffff,
2931 2931 rt2860_get_rf(sc->rf_rev), sc->ntxchains, sc->nrxchains);
2932 2932
2933 2933 /*
2934 2934 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings.
2935 2935 */
2936 2936 for (qid = 0; qid < 6; qid++) {
2937 2937 if ((err = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) {
2938 2938 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2939 2939 "could not allocate Tx ring %d\n", qid);
2940 2940 goto fail3;
2941 2941 }
2942 2942 }
2943 2943
2944 2944 if ((err = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) {
2945 2945 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2946 2946 "could not allocte Rx ring\n");
2947 2947 goto fail4;
2948 2948 }
2949 2949
2950 2950 if ((err = rt2860_alloc_tx_pool(sc)) != 0) {
2951 2951 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2952 2952 "could not allocte Tx pool\n");
2953 2953 goto fail5;
2954 2954 }
2955 2955
2956 2956 mutex_init(&sc->sc_genlock, NULL, MUTEX_DRIVER, NULL);
2957 2957 mutex_init(&sc->sc_txlock, NULL, MUTEX_DRIVER, NULL);
2958 2958 mutex_init(&sc->sc_rxlock, NULL, MUTEX_DRIVER, NULL);
2959 2959
2960 2960 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */
2961 2961 sc->mgtqid = (sc->mac_rev == 0x28600100) ? EDCA_AC_VO : 5;
2962 2962 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach():"
2963 2963 "mgtqid = %x\n", sc->mgtqid);
2964 2964
2965 2965 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
2966 2966 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
2967 2967 ic->ic_state = IEEE80211_S_INIT;
2968 2968
2969 2969 /* set device capabilities */
2970 2970 ic->ic_caps =
2971 2971 IEEE80211_C_TXPMGT | /* tx power management */
2972 2972 IEEE80211_C_SHPREAMBLE | /* short preamble supported */
2973 2973 IEEE80211_C_SHSLOT; /* short slot time supported */
2974 2974
2975 2975 /* WPA/WPA2 support */
2976 2976 ic->ic_caps |= IEEE80211_C_WPA; /* Support WPA/WPA2 */
2977 2977
2978 2978 /* set supported .11b and .11g rates */
2979 2979 ic->ic_sup_rates[IEEE80211_MODE_11B] = rt2860_rateset_11b;
2980 2980 ic->ic_sup_rates[IEEE80211_MODE_11G] = rt2860_rateset_11g;
2981 2981
2982 2982 /* set supported .11b and .11g channels (1 through 14) */
2983 2983 for (i = 1; i <= 14; i++) {
2984 2984 ic->ic_sup_channels[i].ich_freq =
2985 2985 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
2986 2986 ic->ic_sup_channels[i].ich_flags =
2987 2987 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM |
2988 2988 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ;
2989 2989 }
2990 2990
2991 2991 ic->ic_maxrssi = 63;
2992 2992 ic->ic_xmit = rt2860_send;
2993 2993
2994 2994 ieee80211_attach(ic);
2995 2995
2996 2996 /* register WPA door */
2997 2997 ieee80211_register_door(ic, ddi_driver_name(devinfo),
2998 2998 ddi_get_instance(devinfo));
2999 2999
3000 3000 /* override state transition machine */
3001 3001 sc->sc_newstate = ic->ic_newstate;
3002 3002 ic->ic_newstate = rt2860_newstate;
3003 3003 ieee80211_media_init(ic);
3004 3004 ic->ic_def_txkey = 0;
3005 3005
3006 3006 err = ddi_add_softintr(devinfo, DDI_SOFTINT_LOW,
3007 3007 &sc->sc_softintr_hdl, NULL, 0, rt2860_softintr, (caddr_t)sc);
3008 3008 if (err != DDI_SUCCESS) {
3009 3009 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
3010 3010 "ddi_add_softintr() failed");
3011 3011 goto fail8;
3012 3012 }
3013 3013
3014 3014 err = ddi_get_iblock_cookie(devinfo, 0, &sc->sc_iblock);
3015 3015 if (err != DDI_SUCCESS) {
3016 3016 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
3017 3017 "Can not get iblock cookie for INT\n");
3018 3018 goto fail7;
3019 3019 }
3020 3020
3021 3021 err = ddi_add_intr(devinfo, 0, NULL, NULL, rt2860_intr, (caddr_t)sc);
3022 3022 if (err != DDI_SUCCESS) {
3023 3023 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
3024 3024 "unable to add device interrupt handler\n");
3025 3025 goto fail7;
3026 3026 }
3027 3027
3028 3028 /*
3029 3029 * Provide initial settings for the WiFi plugin; whenever this
3030 3030 * information changes, we need to call mac_plugindata_update()
3031 3031 */
3032 3032 wd.wd_opmode = ic->ic_opmode;
3033 3033 wd.wd_secalloc = WIFI_SEC_NONE;
3034 3034 IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_bss->in_bssid);
3035 3035
3036 3036 if ((macp = mac_alloc(MAC_VERSION)) == NULL) {
3037 3037 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
3038 3038 "MAC version mismatch\n");
3039 3039 goto fail9;
3040 3040 }
3041 3041
3042 3042 macp->m_type_ident = MAC_PLUGIN_IDENT_WIFI;
3043 3043 macp->m_driver = sc;
3044 3044 macp->m_dip = devinfo;
3045 3045 macp->m_src_addr = ic->ic_macaddr;
3046 3046 macp->m_callbacks = &rt2860_m_callbacks;
3047 3047 macp->m_min_sdu = 0;
3048 3048 macp->m_max_sdu = IEEE80211_MTU;
3049 3049 macp->m_pdata = &wd;
3050 3050 macp->m_pdata_size = sizeof (wd);
3051 3051
3052 3052 err = mac_register(macp, &ic->ic_mach);
3053 3053 mac_free(macp);
3054 3054 if (err != 0) {
3055 3055 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
3056 3056 "mac_register err %x\n", err);
3057 3057 goto fail9;
3058 3058 }
3059 3059
3060 3060 /*
3061 3061 * Create minor node of type DDI_NT_NET_WIFI
3062 3062 */
3063 3063 (void) snprintf(strbuf, sizeof (strbuf), "%s%d",
3064 3064 "rwn", instance);
3065 3065 err = ddi_create_minor_node(devinfo, strbuf, S_IFCHR,
3066 3066 instance + 1, DDI_NT_NET_WIFI, 0);
3067 3067
3068 3068 /*
3069 3069 * Notify link is down now
3070 3070 */
3071 3071 mac_link_update(ic->ic_mach, LINK_STATE_DOWN);
3072 3072
3073 3073 sc->sc_flags &= ~RT2860_F_RUNNING;
3074 3074
3075 3075 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach() successfully.\n");
3076 3076 return (DDI_SUCCESS);
3077 3077 fail9:
3078 3078 ddi_remove_softintr(sc->sc_softintr_hdl);
3079 3079 fail8:
3080 3080 ddi_remove_intr(devinfo, 0, sc->sc_iblock);
3081 3081 fail7:
3082 3082 mutex_destroy(&sc->sc_genlock);
3083 3083 mutex_destroy(&sc->sc_txlock);
3084 3084 mutex_destroy(&sc->sc_rxlock);
3085 3085 fail6:
3086 3086 rt2860_free_tx_pool(sc);
3087 3087 fail5:
3088 3088 rt2860_free_rx_ring(sc, &sc->rxq);
3089 3089 fail4:
3090 3090 while (--qid >= 0)
3091 3091 rt2860_free_tx_ring(sc, &sc->txq[qid]);
3092 3092 fail3:
3093 3093 ddi_regs_map_free(&sc->sc_io_handle);
3094 3094 fail2:
3095 3095 ddi_regs_map_free(&sc->sc_cfg_handle);
3096 3096 fail1:
3097 3097 return (err);
3098 3098 }
3099 3099
3100 3100 static int
3101 3101 rt2860_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
3102 3102 {
3103 3103 struct rt2860_softc *sc;
3104 3104 int qid;
3105 3105
3106 3106 sc = ddi_get_soft_state(rt2860_soft_state_p, ddi_get_instance(devinfo));
3107 3107
3108 3108 switch (cmd) {
3109 3109 case DDI_DETACH:
3110 3110 break;
3111 3111 case DDI_SUSPEND:
3112 3112 if (RT2860_IS_RUNNING(sc))
3113 3113 rt2860_stop(sc);
3114 3114 RT2860_GLOCK(sc);
3115 3115 sc->sc_flags &= ~RT2860_FWLOADED;
3116 3116 sc->sc_flags |= RT2860_F_SUSPEND;
3117 3117 RT2860_GUNLOCK(sc);
3118 3118 RWN_DEBUG(RT2860_DBG_RESUME, "rwn: rt2860_detach(): "
3119 3119 "suspend now\n");
3120 3120 return (DDI_SUCCESS);
3121 3121 default:
3122 3122 return (DDI_FAILURE);
3123 3123 }
3124 3124
3125 3125 if (mac_disable(sc->sc_ic.ic_mach) != 0)
3126 3126 return (DDI_FAILURE);
3127 3127
3128 3128 rt2860_stop(sc);
3129 3129
3130 3130 /*
3131 3131 * Unregister from the MAC layer subsystem
3132 3132 */
3133 3133 (void) mac_unregister(sc->sc_ic.ic_mach);
3134 3134
3135 3135 ddi_remove_intr(devinfo, 0, sc->sc_iblock);
3136 3136 ddi_remove_softintr(sc->sc_softintr_hdl);
3137 3137
3138 3138 /*
3139 3139 * detach ieee80211 layer
3140 3140 */
3141 3141 ieee80211_detach(&sc->sc_ic);
3142 3142
3143 3143 rt2860_free_tx_pool(sc);
3144 3144 rt2860_free_rx_ring(sc, &sc->rxq);
3145 3145 for (qid = 0; qid < 6; qid++)
3146 3146 rt2860_free_tx_ring(sc, &sc->txq[qid]);
3147 3147
3148 3148 ddi_regs_map_free(&sc->sc_io_handle);
3149 3149
3150 3150 mutex_destroy(&sc->sc_genlock);
3151 3151 mutex_destroy(&sc->sc_txlock);
3152 3152 mutex_destroy(&sc->sc_rxlock);
3153 3153
3154 3154 ddi_remove_minor_node(devinfo, NULL);
3155 3155 ddi_soft_state_free(rt2860_soft_state_p, ddi_get_instance(devinfo));
3156 3156
3157 3157 return (DDI_SUCCESS);
3158 3158 }
3159 3159
3160 3160 int
3161 3161 _info(struct modinfo *modinfop)
3162 3162 {
3163 3163 return (mod_info(&modlinkage, modinfop));
3164 3164 }
3165 3165
3166 3166 int
3167 3167 _init(void)
3168 3168 {
3169 3169 int status;
3170 3170
3171 3171 status = ddi_soft_state_init(&rt2860_soft_state_p,
3172 3172 sizeof (struct rt2860_softc), 1);
3173 3173 if (status != 0)
3174 3174 return (status);
3175 3175
3176 3176 mac_init_ops(&rwn_dev_ops, "rwn");
3177 3177 status = mod_install(&modlinkage);
3178 3178 if (status != 0) {
3179 3179 mac_fini_ops(&rwn_dev_ops);
3180 3180 ddi_soft_state_fini(&rt2860_soft_state_p);
3181 3181 }
3182 3182 return (status);
3183 3183 }
3184 3184
3185 3185 int
3186 3186 _fini(void)
3187 3187 {
3188 3188 int status;
3189 3189
3190 3190 status = mod_remove(&modlinkage);
3191 3191 if (status == 0) {
3192 3192 mac_fini_ops(&rwn_dev_ops);
3193 3193 ddi_soft_state_fini(&rt2860_soft_state_p);
3194 3194 }
3195 3195 return (status);
3196 3196 }
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