478 #define PCIE_BUS_ALL (PCIE_BUS_INITIAL | PCIE_BUS_FINAL)
479
480 #ifdef DEBUG
481 #define PCIE_DBG pcie_dbg
482 /* Common Debugging shortcuts */
483 #define PCIE_DBG_CFG(dip, bus_p, name, sz, off, org) \
484 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \
485 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \
486 PCIE_GET(sz, bus_p, off))
487 #define PCIE_DBG_CAP(dip, bus_p, name, sz, off, org) \
488 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \
489 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \
490 PCIE_CAP_GET(sz, bus_p, off))
491 #define PCIE_DBG_AER(dip, bus_p, name, sz, off, org) \
492 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \
493 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \
494 PCIE_AER_GET(sz, bus_p, off))
495
496 #else /* DEBUG */
497
498 #define PCIE_DBG_CFG(...)
499 #define PCIE_DBG(...)
500 #define PCIE_ARI_DBG(...)
501 #define PCIE_DBG_CAP(...)
502 #define PCIE_DBG_AER(...)
503
504 #endif /* DEBUG */
505
506 /* PCIe Friendly Functions */
507 extern int pcie_init(dev_info_t *dip, caddr_t arg);
508 extern int pcie_uninit(dev_info_t *dip);
509 extern int pcie_hpintr_enable(dev_info_t *dip);
510 extern int pcie_hpintr_disable(dev_info_t *dip);
511 extern int pcie_intr(dev_info_t *dip);
512 extern int pcie_open(dev_info_t *dip, dev_t *devp, int flags, int otyp,
513 cred_t *credp);
514 extern int pcie_close(dev_info_t *dip, dev_t dev, int flags, int otyp,
515 cred_t *credp);
516 extern int pcie_ioctl(dev_info_t *dip, dev_t dev, int cmd, intptr_t arg,
517 int mode, cred_t *credp, int *rvalp);
518 extern int pcie_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op,
519 int flags, char *name, caddr_t valuep, int *lengthp);
520
521 extern void pcie_init_root_port_mps(dev_info_t *dip);
522 extern int pcie_initchild(dev_info_t *dip);
|
478 #define PCIE_BUS_ALL (PCIE_BUS_INITIAL | PCIE_BUS_FINAL)
479
480 #ifdef DEBUG
481 #define PCIE_DBG pcie_dbg
482 /* Common Debugging shortcuts */
483 #define PCIE_DBG_CFG(dip, bus_p, name, sz, off, org) \
484 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \
485 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \
486 PCIE_GET(sz, bus_p, off))
487 #define PCIE_DBG_CAP(dip, bus_p, name, sz, off, org) \
488 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \
489 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \
490 PCIE_CAP_GET(sz, bus_p, off))
491 #define PCIE_DBG_AER(dip, bus_p, name, sz, off, org) \
492 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \
493 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \
494 PCIE_AER_GET(sz, bus_p, off))
495
496 #else /* DEBUG */
497
498 #define PCIE_DBG_CFG(...) (void)(0)
499 #define PCIE_DBG(...) (void)(0)
500 #define PCIE_ARI_DBG(...) (void)(0)
501 #define PCIE_DBG_CAP(...) (void)(0)
502 #define PCIE_DBG_AER(...) (void)(0)
503
504 #endif /* DEBUG */
505
506 /* PCIe Friendly Functions */
507 extern int pcie_init(dev_info_t *dip, caddr_t arg);
508 extern int pcie_uninit(dev_info_t *dip);
509 extern int pcie_hpintr_enable(dev_info_t *dip);
510 extern int pcie_hpintr_disable(dev_info_t *dip);
511 extern int pcie_intr(dev_info_t *dip);
512 extern int pcie_open(dev_info_t *dip, dev_t *devp, int flags, int otyp,
513 cred_t *credp);
514 extern int pcie_close(dev_info_t *dip, dev_t dev, int flags, int otyp,
515 cred_t *credp);
516 extern int pcie_ioctl(dev_info_t *dip, dev_t dev, int cmd, intptr_t arg,
517 int mode, cred_t *credp, int *rvalp);
518 extern int pcie_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op,
519 int flags, char *name, caddr_t valuep, int *lengthp);
520
521 extern void pcie_init_root_port_mps(dev_info_t *dip);
522 extern int pcie_initchild(dev_info_t *dip);
|