20  */
  21 /*
  22  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
  23  */
  24 
  25 /*
  26  * Copyright 2019, Joyent, Inc.
  27  */
  28 
  29 #ifndef _SYS_PCIEB_H
  30 #define _SYS_PCIEB_H
  31 
  32 #ifdef  __cplusplus
  33 extern "C" {
  34 #endif
  35 
  36 #if defined(DEBUG)
  37 #define PCIEB_DEBUG pcieb_dbg
  38 extern void pcieb_dbg(uint_t bit, dev_info_t *dip, char *fmt, ...);
  39 #else /* DEBUG */
  40 #define PCIEB_DEBUG(...)
  41 #endif /* DEBUG */
  42 
  43 typedef enum {  /* same sequence as pcieb_debug_sym[] */
  44         /*  0 */ DBG_ATTACH,
  45         /*  1 */ DBG_PWR,
  46         /*  2 */ DBG_INTR
  47 } pcieb_debug_bit_t;
  48 
  49 /*
  50  * Intel specific register offsets with bit definitions.
  51  */
  52 #define PCIEB_PX_CAPABILITY_ID  0x44
  53 #define PCIEB_BRIDGE_CONF               0x40
  54 
  55 /*
  56  * PCI/PCI-E Configuration register specific values.
  57  */
  58 #define PX_PMODE        0x4000          /* PCI/PCIX Mode */
  59 #define PX_PFREQ_66     0x200           /* PCI clock frequency */
  60 #define PX_PFREQ_100    0x400

  20  */
  21 /*
  22  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
  23  */
  24 
  25 /*
  26  * Copyright 2019, Joyent, Inc.
  27  */
  28 
  29 #ifndef _SYS_PCIEB_H
  30 #define _SYS_PCIEB_H
  31 
  32 #ifdef  __cplusplus
  33 extern "C" {
  34 #endif
  35 
  36 #if defined(DEBUG)
  37 #define PCIEB_DEBUG pcieb_dbg
  38 extern void pcieb_dbg(uint_t bit, dev_info_t *dip, char *fmt, ...);
  39 #else /* DEBUG */
  40 #define PCIEB_DEBUG(...) (void)(0)
  41 #endif /* DEBUG */
  42 
  43 typedef enum {  /* same sequence as pcieb_debug_sym[] */
  44         /*  0 */ DBG_ATTACH,
  45         /*  1 */ DBG_PWR,
  46         /*  2 */ DBG_INTR
  47 } pcieb_debug_bit_t;
  48 
  49 /*
  50  * Intel specific register offsets with bit definitions.
  51  */
  52 #define PCIEB_PX_CAPABILITY_ID  0x44
  53 #define PCIEB_BRIDGE_CONF               0x40
  54 
  55 /*
  56  * PCI/PCI-E Configuration register specific values.
  57  */
  58 #define PX_PMODE        0x4000          /* PCI/PCIX Mode */
  59 #define PX_PFREQ_66     0x200           /* PCI clock frequency */
  60 #define PX_PFREQ_100    0x400