5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
23 */
24
25 #ifndef _SYS_PCIE_IMPL_H
26 #define _SYS_PCIE_IMPL_H
27
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31
32 #include <sys/pcie.h>
33 #include <sys/pciev.h>
34
35 #define PCI_GET_BDF(dip) \
36 PCIE_DIP2BUS(dip)->bus_bdf
37 #define PCI_GET_SEC_BUS(dip) \
38 PCIE_DIP2BUS(dip)->bus_bdg_secbus
39 #define PCI_GET_PCIE2PCI_SECBUS(dip) \
40 PCIE_DIP2BUS(dip)->bus_pcie2pci_secbus
41
42 #define DEVI_PORT_TYPE_PCI \
43 ((PCI_CLASS_BRIDGE << 16) | (PCI_BRIDGE_PCI << 8) | \
44 PCI_BRIDGE_PCI_IF_PCI2PCI)
474 #define PCIE_BUS_ALL (PCIE_BUS_INITIAL | PCIE_BUS_FINAL)
475
476 #ifdef DEBUG
477 #define PCIE_DBG pcie_dbg
478 /* Common Debugging shortcuts */
479 #define PCIE_DBG_CFG(dip, bus_p, name, sz, off, org) \
480 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \
481 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \
482 PCIE_GET(sz, bus_p, off))
483 #define PCIE_DBG_CAP(dip, bus_p, name, sz, off, org) \
484 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \
485 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \
486 PCIE_CAP_GET(sz, bus_p, off))
487 #define PCIE_DBG_AER(dip, bus_p, name, sz, off, org) \
488 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \
489 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \
490 PCIE_AER_GET(sz, bus_p, off))
491
492 #else /* DEBUG */
493
494 #define PCIE_DBG_CFG 0 &&
495 #define PCIE_DBG 0 &&
496 #define PCIE_ARI_DBG 0 &&
497 #define PCIE_DBG_CAP 0 &&
498 #define PCIE_DBG_AER 0 &&
499
500 #endif /* DEBUG */
501
502 /* PCIe Friendly Functions */
503 extern int pcie_init(dev_info_t *dip, caddr_t arg);
504 extern int pcie_uninit(dev_info_t *dip);
505 extern int pcie_hpintr_enable(dev_info_t *dip);
506 extern int pcie_hpintr_disable(dev_info_t *dip);
507 extern int pcie_intr(dev_info_t *dip);
508 extern int pcie_open(dev_info_t *dip, dev_t *devp, int flags, int otyp,
509 cred_t *credp);
510 extern int pcie_close(dev_info_t *dip, dev_t dev, int flags, int otyp,
511 cred_t *credp);
512 extern int pcie_ioctl(dev_info_t *dip, dev_t dev, int cmd, intptr_t arg,
513 int mode, cred_t *credp, int *rvalp);
514 extern int pcie_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op,
515 int flags, char *name, caddr_t valuep, int *lengthp);
516
517 extern void pcie_init_root_port_mps(dev_info_t *dip);
518 extern int pcie_initchild(dev_info_t *dip);
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5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
23 */
24
25 /*
26 * Copyright 2019, Joyent, Inc.
27 */
28
29 #ifndef _SYS_PCIE_IMPL_H
30 #define _SYS_PCIE_IMPL_H
31
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35
36 #include <sys/pcie.h>
37 #include <sys/pciev.h>
38
39 #define PCI_GET_BDF(dip) \
40 PCIE_DIP2BUS(dip)->bus_bdf
41 #define PCI_GET_SEC_BUS(dip) \
42 PCIE_DIP2BUS(dip)->bus_bdg_secbus
43 #define PCI_GET_PCIE2PCI_SECBUS(dip) \
44 PCIE_DIP2BUS(dip)->bus_pcie2pci_secbus
45
46 #define DEVI_PORT_TYPE_PCI \
47 ((PCI_CLASS_BRIDGE << 16) | (PCI_BRIDGE_PCI << 8) | \
48 PCI_BRIDGE_PCI_IF_PCI2PCI)
478 #define PCIE_BUS_ALL (PCIE_BUS_INITIAL | PCIE_BUS_FINAL)
479
480 #ifdef DEBUG
481 #define PCIE_DBG pcie_dbg
482 /* Common Debugging shortcuts */
483 #define PCIE_DBG_CFG(dip, bus_p, name, sz, off, org) \
484 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \
485 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \
486 PCIE_GET(sz, bus_p, off))
487 #define PCIE_DBG_CAP(dip, bus_p, name, sz, off, org) \
488 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \
489 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \
490 PCIE_CAP_GET(sz, bus_p, off))
491 #define PCIE_DBG_AER(dip, bus_p, name, sz, off, org) \
492 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \
493 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \
494 PCIE_AER_GET(sz, bus_p, off))
495
496 #else /* DEBUG */
497
498 #define PCIE_DBG_CFG(...)
499 #define PCIE_DBG(...)
500 #define PCIE_ARI_DBG(...)
501 #define PCIE_DBG_CAP(...)
502 #define PCIE_DBG_AER(...)
503
504 #endif /* DEBUG */
505
506 /* PCIe Friendly Functions */
507 extern int pcie_init(dev_info_t *dip, caddr_t arg);
508 extern int pcie_uninit(dev_info_t *dip);
509 extern int pcie_hpintr_enable(dev_info_t *dip);
510 extern int pcie_hpintr_disable(dev_info_t *dip);
511 extern int pcie_intr(dev_info_t *dip);
512 extern int pcie_open(dev_info_t *dip, dev_t *devp, int flags, int otyp,
513 cred_t *credp);
514 extern int pcie_close(dev_info_t *dip, dev_t dev, int flags, int otyp,
515 cred_t *credp);
516 extern int pcie_ioctl(dev_info_t *dip, dev_t dev, int cmd, intptr_t arg,
517 int mode, cred_t *credp, int *rvalp);
518 extern int pcie_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op,
519 int flags, char *name, caddr_t valuep, int *lengthp);
520
521 extern void pcie_init_root_port_mps(dev_info_t *dip);
522 extern int pcie_initchild(dev_info_t *dip);
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