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10320 qede_gld.c uses assignment, means equality
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--- old/usr/src/uts/common/io/qede/qede_gld.c
+++ new/usr/src/uts/common/io/qede/qede_gld.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License, v.1, (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://opensource.org/licenses/CDDL-1.0.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright 2014-2017 Cavium, Inc.
24 24 * The contents of this file are subject to the terms of the Common Development
25 25 * and Distribution License, v.1, (the "License").
26 26
27 27 * You may not use this file except in compliance with the License.
28 28
29 29 * You can obtain a copy of the License at available
30 30 * at http://opensource.org/licenses/CDDL-1.0
31 31
32 32 * See the License for the specific language governing permissions and
33 33 * limitations under the License.
34 34 */
35 35
36 36 /*
37 37 * Copyright 2018 Joyent, Inc.
38 38 */
39 39
40 40 #include "qede.h"
41 41
42 42 #define FP_LOCK(ptr) \
43 43 mutex_enter(&ptr->fp_lock);
44 44 #define FP_UNLOCK(ptr) \
45 45 mutex_exit(&ptr->fp_lock);
46 46
47 47 int
48 48 qede_ucst_find(qede_t *qede, const uint8_t *mac_addr)
49 49 {
50 50 int slot;
51 51
52 52 for(slot = 0; slot < qede->ucst_total; slot++) {
53 53 if (bcmp(qede->ucst_mac[slot].mac_addr.ether_addr_octet,
54 54 mac_addr, ETHERADDRL) == 0) {
55 55 return (slot);
56 56 }
57 57 }
58 58 return (-1);
59 59
60 60 }
61 61
62 62 static int
63 63 qede_set_mac_addr(qede_t *qede, uint8_t *mac_addr, uint8_t fl)
64 64 {
65 65 struct ecore_filter_ucast params;
66 66
67 67 memset(¶ms, 0, sizeof (params));
68 68
69 69 params.opcode = fl;
70 70 params.type = ECORE_FILTER_MAC;
71 71 params.is_rx_filter = true;
72 72 params.is_tx_filter = true;
73 73 COPY_ETH_ADDRESS(mac_addr, params.mac);
74 74
75 75 return (ecore_filter_ucast_cmd(&qede->edev,
76 76 ¶ms, ECORE_SPQ_MODE_EBLOCK, NULL));
77 77
78 78
79 79 }
80 80 static int
81 81 qede_add_macaddr(qede_t *qede, uint8_t *mac_addr)
82 82 {
83 83 int i, ret = 0;
84 84
85 85 i = qede_ucst_find(qede, mac_addr);
86 86 if (i != -1) {
87 87 /* LINTED E_ARGUMENT_MISMATCH */
88 88 qede_info(qede, "mac addr already added %d\n",
89 89 qede->ucst_avail);
90 90 return (0);
91 91 }
92 92 if (qede->ucst_avail == 0) {
93 93 qede_info(qede, "add macaddr ignored \n");
94 94 return (ENOSPC);
95 95 }
96 96 for (i = 0; i < qede->ucst_total; i++) {
97 97 if (qede->ucst_mac[i].set == 0) {
98 98 break;
99 99 }
100 100 }
101 101 if (i >= qede->ucst_total) {
102 102 qede_info(qede, "add macaddr ignored no space");
103 103 return (ENOSPC);
104 104 }
105 105 ret = qede_set_mac_addr(qede, (uint8_t *)mac_addr, ECORE_FILTER_ADD);
106 106 if (ret == 0) {
107 107 bcopy(mac_addr,
108 108 qede->ucst_mac[i].mac_addr.ether_addr_octet,
109 109 ETHERADDRL);
110 110 qede->ucst_mac[i].set = 1;
111 111 qede->ucst_avail--;
112 112 /* LINTED E_ARGUMENT_MISMATCH */
113 113 qede_info(qede, " add macaddr passed for addr "
114 114 "%02x:%02x:%02x:%02x:%02x:%02x",
115 115 mac_addr[0], mac_addr[1],
116 116 mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
117 117 } else {
118 118 /* LINTED E_ARGUMENT_MISMATCH */
119 119 qede_info(qede, "add macaddr failed for addr "
120 120 "%02x:%02x:%02x:%02x:%02x:%02x",
121 121 mac_addr[0], mac_addr[1],
122 122 mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
123 123
124 124 }
125 125 if (qede->ucst_avail == (qede->ucst_total -1)) {
126 126 u8 bcast_addr[] =
127 127 {
128 128 0xff, 0xff, 0xff, 0xff, 0xff,
129 129 0xff
130 130 };
131 131 for (i = 0; i < qede->ucst_total; i++) {
132 132 if (qede->ucst_mac[i].set == 0)
133 133 break;
134 134 }
135 135 ret = qede_set_mac_addr(qede,
136 136 (uint8_t *)bcast_addr, ECORE_FILTER_ADD);
137 137 if (ret == 0) {
138 138 bcopy(bcast_addr,
139 139 qede->ucst_mac[i].mac_addr.ether_addr_octet,
140 140 ETHERADDRL);
141 141 qede->ucst_mac[i].set = 1;
142 142 qede->ucst_avail--;
143 143 } else {
144 144
145 145 /* LINTED E_ARGUMENT_MISMATCH */
146 146 qede_info(qede, "add macaddr failed for addr "
147 147 "%02x:%02x:%02x:%02x:%02x:%02x",
148 148 mac_addr[0], mac_addr[1],
149 149 mac_addr[2], mac_addr[3], mac_addr[4],
150 150 mac_addr[5]);
151 151 }
152 152
153 153 }
154 154
155 155 return (ret);
156 156
157 157 }
158 158
159 159 #ifndef ILLUMOS
160 160 static int
161 161 qede_add_mac_addr(void *arg, const uint8_t *mac_addr, const uint64_t flags)
162 162 #else
163 163 static int
164 164 qede_add_mac_addr(void *arg, const uint8_t *mac_addr)
165 165 #endif
166 166 {
167 167 qede_mac_group_t *rx_group = (qede_mac_group_t *)arg;
168 168 qede_t *qede = rx_group->qede;
169 169 int ret = DDI_SUCCESS;
170 170
171 171 /* LINTED E_ARGUMENT_MISMATCH */
172 172 qede_info(qede, " mac addr :" MAC_STRING, MACTOSTR(mac_addr));
173 173
174 174 mutex_enter(&qede->gld_lock);
175 175 if (qede->qede_state == QEDE_STATE_SUSPENDED) {
176 176 mutex_exit(&qede->gld_lock);
177 177 return (ECANCELED);
178 178 }
179 179 ret = qede_add_macaddr(qede, (uint8_t *)mac_addr);
180 180
181 181 mutex_exit(&qede->gld_lock);
182 182
183 183
184 184 return (ret);
185 185 }
186 186
187 187 static int
188 188 qede_rem_macaddr(qede_t *qede, uint8_t *mac_addr)
189 189 {
190 190 int ret = 0;
191 191 int i;
192 192
193 193 i = qede_ucst_find(qede, mac_addr);
194 194 if (i == -1) {
195 195 /* LINTED E_ARGUMENT_MISMATCH */
196 196 qede_info(qede,
197 197 "mac addr not there to remove",
198 198 MAC_STRING, MACTOSTR(mac_addr));
199 199 return (0);
200 200 }
201 201 if (qede->ucst_mac[i].set == 0) {
202 202 return (EINVAL);
203 203 }
204 204 ret = qede_set_mac_addr(qede, (uint8_t *)mac_addr, ECORE_FILTER_REMOVE);
205 205 if (ret == 0) {
206 206 bzero(qede->ucst_mac[i].mac_addr.ether_addr_octet,ETHERADDRL);
207 207 qede->ucst_mac[i].set = 0;
208 208 qede->ucst_avail++;
209 209 } else {
210 210 /* LINTED E_ARGUMENT_MISMATCH */
211 211 qede_info(qede, "mac addr remove failed",
212 212 MAC_STRING, MACTOSTR(mac_addr));
213 213 }
214 214 return (ret);
215 215
216 216 }
217 217
218 218
219 219 static int
220 220 qede_rem_mac_addr(void *arg, const uint8_t *mac_addr)
221 221 {
222 222 qede_mac_group_t *rx_group = (qede_mac_group_t *)arg;
223 223 qede_t *qede = rx_group->qede;
224 224 int ret = DDI_SUCCESS;
225 225
226 226 /* LINTED E_ARGUMENT_MISMATCH */
227 227 qede_info(qede, "mac addr remove:" MAC_STRING, MACTOSTR(mac_addr));
228 228 mutex_enter(&qede->gld_lock);
229 229 if (qede->qede_state == QEDE_STATE_SUSPENDED) {
230 230 mutex_exit(&qede->gld_lock);
231 231 return (ECANCELED);
232 232 }
233 233 ret = qede_rem_macaddr(qede, (uint8_t *)mac_addr);
234 234 mutex_exit(&qede->gld_lock);
235 235 return (ret);
236 236 }
237 237
238 238
239 239 static int
240 240 qede_tx_ring_stat(mac_ring_driver_t rh, uint_t stat, uint64_t *val)
241 241 {
242 242 int ret = 0;
243 243
244 244 qede_fastpath_t *fp = (qede_fastpath_t *)rh;
245 245 qede_tx_ring_t *tx_ring = fp->tx_ring[0];
246 246 qede_t *qede = fp->qede;
247 247
248 248
249 249 if (qede->qede_state == QEDE_STATE_SUSPENDED)
250 250 return (ECANCELED);
251 251
252 252 switch (stat) {
253 253 case MAC_STAT_OBYTES:
254 254 *val = tx_ring->tx_byte_count;
255 255 break;
256 256
257 257 case MAC_STAT_OPACKETS:
258 258 *val = tx_ring->tx_pkt_count;
259 259 break;
260 260
261 261 default:
262 262 *val = 0;
263 263 ret = ENOTSUP;
264 264 }
265 265
266 266 return (ret);
267 267 }
268 268
269 269 #ifndef ILLUMOS
270 270 static mblk_t *
271 271 qede_rx_ring_poll(void *arg, int poll_bytes, int poll_pkts)
272 272 {
273 273 #else
274 274 static mblk_t *
275 275 qede_rx_ring_poll(void *arg, int poll_bytes)
276 276 {
277 277 /* XXX pick a value at the moment */
278 278 int poll_pkts = 100;
279 279 #endif
280 280 qede_fastpath_t *fp = (qede_fastpath_t *)arg;
281 281 mblk_t *mp = NULL;
282 282 int work_done = 0;
283 283 qede_t *qede = fp->qede;
284 284
285 285 if (poll_bytes == 0) {
286 286 return (NULL);
287 287 }
288 288
289 289 mutex_enter(&fp->fp_lock);
290 290 qede->intrSbPollCnt[fp->vect_info->vect_index]++;
291 291
292 292 mp = qede_process_fastpath(fp, poll_bytes, poll_pkts, &work_done);
293 293 if (mp != NULL) {
294 294 fp->rx_ring->rx_poll_cnt++;
295 295 } else if ((mp == NULL) && (work_done == 0)) {
296 296 qede->intrSbPollNoChangeCnt[fp->vect_info->vect_index]++;
297 297 }
298 298
299 299 mutex_exit(&fp->fp_lock);
300 300 return (mp);
301 301 }
302 302
303 303 #ifndef ILLUMOS
304 304 static int
305 305 qede_rx_ring_intr_enable(mac_ring_driver_t rh)
306 306 #else
307 307 static int
308 308 qede_rx_ring_intr_enable(mac_intr_handle_t rh)
309 309 #endif
310 310 {
311 311 qede_fastpath_t *fp = (qede_fastpath_t *)rh;
312 312
313 313 mutex_enter(&fp->qede->drv_lock);
314 314 if (!fp->sb_phys && (fp->sb_dma_handle == NULL)) {
315 315 mutex_exit(&fp->qede->drv_lock);
316 316 return (DDI_FAILURE);
317 317 }
318 318
319 319 fp->rx_ring->intrEnableCnt++;
320 320 qede_enable_hw_intr(fp);
321 321 fp->disabled_by_poll = 0;
322 322 mutex_exit(&fp->qede->drv_lock);
323 323
324 324 return (DDI_SUCCESS);
325 325 }
326 326
327 327 #ifndef ILLUMOS
328 328 static int
329 329 qede_rx_ring_intr_disable(mac_ring_driver_t rh)
330 330 #else
331 331 static int
332 332 qede_rx_ring_intr_disable(mac_intr_handle_t rh)
333 333 #endif
334 334 {
335 335 qede_fastpath_t *fp = (qede_fastpath_t *)rh;
336 336
337 337 mutex_enter(&fp->qede->drv_lock);
338 338 if (!fp->sb_phys && (fp->sb_dma_handle == NULL)) {
339 339 mutex_exit(&fp->qede->drv_lock);
340 340 return (DDI_FAILURE);
341 341 }
342 342 fp->rx_ring->intrDisableCnt++;
343 343 qede_disable_hw_intr(fp);
344 344 fp->disabled_by_poll = 1;
345 345 mutex_exit(&fp->qede->drv_lock);
346 346 return (DDI_SUCCESS);
347 347 }
348 348
349 349 static int
350 350 qede_rx_ring_stat(mac_ring_driver_t rh, uint_t stat, uint64_t *val)
351 351 {
352 352
353 353 int ret = 0;
354 354
355 355 qede_fastpath_t *fp = (qede_fastpath_t *)rh;
356 356 qede_t *qede = fp->qede;
357 357 qede_rx_ring_t *rx_ring = fp->rx_ring;
358 358
359 359 if (qede->qede_state == QEDE_STATE_SUSPENDED) {
360 360 return (ECANCELED);
361 361 }
362 362
363 363 switch (stat) {
364 364 case MAC_STAT_RBYTES:
365 365 *val = rx_ring->rx_byte_cnt;
366 366 break;
367 367 case MAC_STAT_IPACKETS:
368 368 *val = rx_ring->rx_pkt_cnt;
369 369 break;
370 370 default:
371 371 *val = 0;
372 372 ret = ENOTSUP;
373 373 break;
374 374 }
375 375
376 376 return (ret);
377 377 }
378 378
379 379 static int
380 380 qede_get_global_ring_index(qede_t *qede, int gindex, int rindex)
381 381 {
382 382 qede_fastpath_t *fp;
383 383 qede_rx_ring_t *rx_ring;
384 384 int i = 0;
385 385
386 386 for (i = 0; i < qede->num_fp; i++) {
387 387 fp = &qede->fp_array[i];
388 388 rx_ring = fp->rx_ring;
389 389
390 390 if (rx_ring->group_index == gindex) {
391 391 rindex--;
392 392 }
393 393 if (rindex < 0) {
394 394 return (i);
395 395 }
396 396 }
397 397
398 398 return (-1);
399 399 }
400 400
401 401 static void
402 402 qede_rx_ring_stop(mac_ring_driver_t rh)
403 403 {
404 404 qede_fastpath_t *fp = (qede_fastpath_t *)rh;
405 405 qede_rx_ring_t *rx_ring = fp->rx_ring;
406 406
407 407 qede_print("!%s(%d): called", __func__,fp->qede->instance);
408 408 mutex_enter(&fp->fp_lock);
409 409 rx_ring->mac_ring_started = B_FALSE;
410 410 mutex_exit(&fp->fp_lock);
411 411 }
412 412
413 413 static int
414 414 qede_rx_ring_start(mac_ring_driver_t rh, u64 mr_gen_num)
415 415 {
416 416 qede_fastpath_t *fp = (qede_fastpath_t *)rh;
417 417 qede_rx_ring_t *rx_ring = fp->rx_ring;
418 418
419 419 qede_print("!%s(%d): called", __func__,fp->qede->instance);
420 420 mutex_enter(&fp->fp_lock);
421 421 rx_ring->mr_gen_num = mr_gen_num;
422 422 rx_ring->mac_ring_started = B_TRUE;
423 423 rx_ring->intrDisableCnt = 0;
424 424 rx_ring->intrEnableCnt = 0;
425 425 fp->disabled_by_poll = 0;
426 426
427 427 mutex_exit(&fp->fp_lock);
428 428
429 429 return (DDI_SUCCESS);
430 430 }
431 431
432 432 /* Callback function from mac layer to register rings */
433 433 void
434 434 qede_fill_ring(void *arg, mac_ring_type_t rtype, const int group_index,
435 435 const int ring_index, mac_ring_info_t *infop, mac_ring_handle_t rh)
436 436 {
437 437 qede_t *qede = (qede_t *)arg;
438 438 mac_intr_t *mintr = &infop->mri_intr;
439 439
440 440 switch (rtype) {
441 441 case MAC_RING_TYPE_RX: {
442 442 /*
443 443 * Index passed as a param is the ring index within the
444 444 * given group index. If multiple groups are supported
445 445 * then need to search into all groups to find out the
446 446 * global ring index for the passed group relative
447 447 * ring index
448 448 */
449 449 int global_ring_index = qede_get_global_ring_index(qede,
450 450 group_index, ring_index);
451 451 qede_fastpath_t *fp;
452 452 qede_rx_ring_t *rx_ring;
453 453 int i;
454 454
455 455 /*
456 456 * global_ring_index < 0 means group index passed
457 457 * was registered by our driver
458 458 */
459 459 ASSERT(global_ring_index >= 0);
460 460
461 461 if (rh == NULL) {
462 462 cmn_err(CE_WARN, "!rx ring(%d) ring handle NULL",
463 463 global_ring_index);
464 464 }
465 465
466 466 fp = &qede->fp_array[global_ring_index];
467 467 rx_ring = fp->rx_ring;
468 468 fp->qede = qede;
469 469
470 470 rx_ring->mac_ring_handle = rh;
471 471
472 472 qede_info(qede, "rx_ring %d mac_ring_handle %p",
473 473 rx_ring->rss_id, rh);
474 474
475 475 /* mri_driver passed as arg to mac_ring* callbacks */
476 476 infop->mri_driver = (mac_ring_driver_t)fp;
477 477 /*
478 478 * mri_start callback will supply a mac rings generation
479 479 * number which is needed while indicating packets
480 480 * upstream via mac_ring_rx() call
481 481 */
482 482 infop->mri_start = qede_rx_ring_start;
483 483 infop->mri_stop = qede_rx_ring_stop;
484 484 infop->mri_poll = qede_rx_ring_poll;
485 485 infop->mri_stat = qede_rx_ring_stat;
486 486
487 487 mintr->mi_handle = (mac_intr_handle_t)fp;
488 488 mintr->mi_enable = qede_rx_ring_intr_enable;
489 489 mintr->mi_disable = qede_rx_ring_intr_disable;
490 490 if (qede->intr_ctx.intr_type_in_use &
491 491 (DDI_INTR_TYPE_MSIX | DDI_INTR_TYPE_MSI)) {
492 492 mintr->mi_ddi_handle =
493 493 qede->intr_ctx.
494 494 intr_hdl_array[global_ring_index + qede->num_hwfns];
495 495 }
496 496 break;
497 497 }
498 498 case MAC_RING_TYPE_TX: {
499 499 qede_fastpath_t *fp;
500 500 qede_tx_ring_t *tx_ring;
501 501 int i, tc;
502 502
503 503 ASSERT(ring_index < qede->num_fp);
504 504
505 505 fp = &qede->fp_array[ring_index];
506 506 fp->qede = qede;
507 507 tx_ring = fp->tx_ring[0];
508 508 tx_ring->mac_ring_handle = rh;
509 509 qede_info(qede, "tx_ring %d mac_ring_handle %p",
510 510 tx_ring->tx_queue_index, rh);
511 511 infop->mri_driver = (mac_ring_driver_t)fp;
512 512 infop->mri_start = NULL;
513 513 infop->mri_stop = NULL;
514 514 infop->mri_tx = qede_ring_tx;
515 515 infop->mri_stat = qede_tx_ring_stat;
516 516 if (qede->intr_ctx.intr_type_in_use &
517 517 (DDI_INTR_TYPE_MSIX | DDI_INTR_TYPE_MSI)) {
518 518 mintr->mi_ddi_handle =
519 519 qede->intr_ctx.
520 520 intr_hdl_array[ring_index + qede->num_hwfns];
521 521 }
522 522 break;
523 523 }
524 524 default:
525 525 break;
526 526 }
527 527 }
528 528
529 529 /*
530 530 * Callback function from mac layer to register group
531 531 */
532 532 void
533 533 qede_fill_group(void *arg, mac_ring_type_t rtype, const int index,
534 534 mac_group_info_t *infop, mac_group_handle_t gh)
535 535 {
536 536 qede_t *qede = (qede_t *)arg;
537 537
538 538 switch (rtype) {
539 539 case MAC_RING_TYPE_RX: {
540 540 qede_mac_group_t *rx_group;
541 541
542 542 rx_group = &qede->rx_groups[index];
543 543 rx_group->group_handle = gh;
544 544 rx_group->group_index = index;
545 545 rx_group->qede = qede;
546 546 infop->mgi_driver = (mac_group_driver_t)rx_group;
547 547 infop->mgi_start = NULL;
548 548 infop->mgi_stop = NULL;
549 549 #ifndef ILLUMOS
550 550 infop->mgi_addvlan = NULL;
551 551 infop->mgi_remvlan = NULL;
552 552 infop->mgi_getsriov_info = NULL;
553 553 infop->mgi_setmtu = NULL;
554 554 #endif
555 555 infop->mgi_addmac = qede_add_mac_addr;
556 556 infop->mgi_remmac = qede_rem_mac_addr;
557 557 infop->mgi_count = qede->num_fp;
558 558 #ifndef ILLUMOS
559 559 if (index == 0) {
560 560 infop->mgi_flags = MAC_GROUP_DEFAULT;
561 561 }
562 562 #endif
563 563
564 564 break;
565 565 }
566 566 case MAC_RING_TYPE_TX: {
567 567 qede_mac_group_t *tx_group;
568 568
569 569 tx_group = &qede->tx_groups[index];
570 570 tx_group->group_handle = gh;
571 571 tx_group->group_index = index;
572 572 tx_group->qede = qede;
573 573
574 574 infop->mgi_driver = (mac_group_driver_t)tx_group;
575 575 infop->mgi_start = NULL;
576 576 infop->mgi_stop = NULL;
577 577 infop->mgi_addmac = NULL;
578 578 infop->mgi_remmac = NULL;
579 579 #ifndef ILLUMOS
580 580 infop->mgi_addvlan = NULL;
581 581 infop->mgi_remvlan = NULL;
582 582 infop->mgi_setmtu = NULL;
583 583 infop->mgi_getsriov_info = NULL;
584 584 #endif
585 585
586 586 infop->mgi_count = qede->num_fp;
587 587
588 588 #ifndef ILLUMOS
589 589 if (index == 0) {
590 590 infop->mgi_flags = MAC_GROUP_DEFAULT;
591 591 }
592 592 #endif
593 593 break;
594 594 }
595 595 default:
596 596 break;
597 597 }
598 598 }
599 599
600 600 #ifdef ILLUMOS
601 601 static int
602 602 qede_transceiver_info(void *arg, uint_t id, mac_transceiver_info_t *infop)
603 603 {
604 604 qede_t *qede = arg;
605 605 struct ecore_dev *edev = &qede->edev;
606 606 struct ecore_hwfn *hwfn;
607 607 struct ecore_ptt *ptt;
608 608 uint32_t transceiver_state;
609 609
610 610 if (id >= edev->num_hwfns || arg == NULL || infop == NULL)
611 611 return (EINVAL);
612 612
613 613 hwfn = &edev->hwfns[id];
614 614 ptt = ecore_ptt_acquire(hwfn);
615 615 if (ptt == NULL) {
616 616 return (EIO);
617 617 }
618 618 /*
619 619 * Use the underlying raw API to get this information. While the
620 620 * ecore_phy routines have some ways of getting to this information, it
621 621 * ends up writing the raw data as ASCII characters which doesn't help
622 622 * us one bit.
623 623 */
624 624 transceiver_state = ecore_rd(hwfn, ptt, hwfn->mcp_info->port_addr +
625 625 offsetof(struct public_port, transceiver_data));
626 626 transceiver_state = GET_FIELD(transceiver_state, ETH_TRANSCEIVER_STATE);
627 627 ecore_ptt_release(hwfn, ptt);
628 628
629 629 if ((transceiver_state & ETH_TRANSCEIVER_STATE_PRESENT) != 0) {
630 630 mac_transceiver_info_set_present(infop, B_TRUE);
631 631 /*
632 632 * Based on our testing, the ETH_TRANSCEIVER_STATE_VALID flag is
633 633 * not set, so we cannot rely on it. Instead, we have found that
634 634 * the ETH_TRANSCEIVER_STATE_UPDATING will be set when we cannot
635 635 * use the transceiver.
636 636 */
637 637 if ((transceiver_state & ETH_TRANSCEIVER_STATE_UPDATING) != 0) {
638 638 mac_transceiver_info_set_usable(infop, B_FALSE);
639 639 } else {
640 640 mac_transceiver_info_set_usable(infop, B_TRUE);
641 641 }
642 642 } else {
643 643 mac_transceiver_info_set_present(infop, B_FALSE);
644 644 mac_transceiver_info_set_usable(infop, B_FALSE);
645 645 }
646 646
647 647 return (0);
648 648 }
649 649
650 650 static int
651 651 qede_transceiver_read(void *arg, uint_t id, uint_t page, void *buf,
652 652 size_t nbytes, off_t offset, size_t *nread)
653 653 {
654 654 qede_t *qede = arg;
655 655 struct ecore_dev *edev = &qede->edev;
656 656 struct ecore_hwfn *hwfn;
657 657 uint32_t port, lane;
658 658 struct ecore_ptt *ptt;
659 659 enum _ecore_status_t ret;
660 660
661 661 if (id >= edev->num_hwfns || buf == NULL || nbytes == 0 || nread == NULL ||
662 662 (page != 0xa0 && page != 0xa2) || offset < 0)
663 663 return (EINVAL);
664 664
665 665 /*
666 666 * Both supported pages have a length of 256 bytes, ensure nothing asks
667 667 * us to go beyond that.
668 668 */
669 669 if (nbytes > 256 || offset >= 256 || (offset + nbytes > 256)) {
670 670 return (EINVAL);
671 671 }
672 672
673 673 hwfn = &edev->hwfns[id];
674 674 ptt = ecore_ptt_acquire(hwfn);
675 675 if (ptt == NULL) {
676 676 return (EIO);
677 677 }
678 678
679 679 ret = ecore_mcp_phy_sfp_read(hwfn, ptt, hwfn->port_id, page, offset,
680 680 nbytes, buf);
681 681 ecore_ptt_release(hwfn, ptt);
682 682 if (ret != ECORE_SUCCESS) {
683 683 return (EIO);
684 684 }
685 685 *nread = nbytes;
686 686 return (0);
687 687 }
688 688 #endif /* ILLUMOS */
689 689
690 690
691 691 static int
692 692 qede_mac_stats(void * arg,
693 693 uint_t stat,
694 694 uint64_t * value)
695 695 {
696 696 qede_t * qede = (qede_t *)arg;
697 697 struct ecore_eth_stats vstats;
698 698 struct ecore_dev *edev = &qede->edev;
699 699 struct qede_link_cfg lnkcfg;
700 700 int rc = 0;
701 701 qede_fastpath_t *fp = &qede->fp_array[0];
702 702 qede_rx_ring_t *rx_ring;
703 703 qede_tx_ring_t *tx_ring;
704 704
705 705 if ((qede == NULL) || (value == NULL)) {
706 706 return EINVAL;
707 707 }
708 708
709 709
710 710 mutex_enter(&qede->gld_lock);
711 711
712 712 if(qede->qede_state != QEDE_STATE_STARTED) {
713 713 mutex_exit(&qede->gld_lock);
714 714 return EAGAIN;
715 715 }
716 716
717 717 *value = 0;
718 718
719 719 memset(&vstats, 0, sizeof(struct ecore_eth_stats));
720 720 ecore_get_vport_stats(edev, &vstats);
721 721
722 722
723 723 memset(&qede->curcfg, 0, sizeof(struct qede_link_cfg));
724 724 qede_get_link_info(&edev->hwfns[0], &qede->curcfg);
725 725
726 726
727 727
728 728 switch (stat)
729 729 {
730 730 case MAC_STAT_IFSPEED:
731 731 *value = (qede->props.link_speed * 1000000ULL);
732 732 break;
733 733 case MAC_STAT_MULTIRCV:
734 734 *value = vstats.common.rx_mcast_pkts;
735 735 break;
736 736 case MAC_STAT_BRDCSTRCV:
737 737 *value = vstats.common.rx_bcast_pkts;
738 738 break;
739 739 case MAC_STAT_MULTIXMT:
740 740 *value = vstats.common.tx_mcast_pkts;
741 741 break;
742 742 case MAC_STAT_BRDCSTXMT:
743 743 *value = vstats.common.tx_bcast_pkts;
744 744 break;
745 745 case MAC_STAT_NORCVBUF:
746 746 *value = vstats.common.no_buff_discards;
747 747 break;
748 748 case MAC_STAT_NOXMTBUF:
749 749 *value = 0;
750 750 break;
751 751 case MAC_STAT_IERRORS:
752 752 case ETHER_STAT_MACRCV_ERRORS:
753 753 *value = vstats.common.mac_filter_discards +
754 754 vstats.common.packet_too_big_discard +
755 755 vstats.common.rx_crc_errors;
756 756 break;
757 757
758 758 case MAC_STAT_OERRORS:
759 759 break;
760 760
761 761 case MAC_STAT_COLLISIONS:
762 762 *value = vstats.bb.tx_total_collisions;
763 763 break;
764 764
765 765 case MAC_STAT_RBYTES:
766 766 *value = vstats.common.rx_ucast_bytes +
767 767 vstats.common.rx_mcast_bytes +
768 768 vstats.common.rx_bcast_bytes;
769 769 break;
770 770
771 771 case MAC_STAT_IPACKETS:
772 772 *value = vstats.common.rx_ucast_pkts +
773 773 vstats.common.rx_mcast_pkts +
774 774 vstats.common.rx_bcast_pkts;
775 775 break;
776 776
777 777 case MAC_STAT_OBYTES:
778 778 *value = vstats.common.tx_ucast_bytes +
779 779 vstats.common.tx_mcast_bytes +
780 780 vstats.common.tx_bcast_bytes;
781 781 break;
782 782
783 783 case MAC_STAT_OPACKETS:
784 784 *value = vstats.common.tx_ucast_pkts +
785 785 vstats.common.tx_mcast_pkts +
786 786 vstats.common.tx_bcast_pkts;
787 787 break;
788 788
789 789 case ETHER_STAT_ALIGN_ERRORS:
790 790 *value = vstats.common.rx_align_errors;
791 791 break;
792 792
793 793 case ETHER_STAT_FCS_ERRORS:
794 794 *value = vstats.common.rx_crc_errors;
795 795 break;
796 796
797 797 case ETHER_STAT_FIRST_COLLISIONS:
798 798 break;
799 799
800 800 case ETHER_STAT_MULTI_COLLISIONS:
801 801 break;
802 802
803 803 case ETHER_STAT_DEFER_XMTS:
804 804 break;
805 805
806 806 case ETHER_STAT_TX_LATE_COLLISIONS:
807 807 break;
808 808
809 809 case ETHER_STAT_EX_COLLISIONS:
810 810 break;
811 811
812 812 case ETHER_STAT_MACXMT_ERRORS:
813 813 *value = 0;
814 814 break;
815 815
816 816 case ETHER_STAT_CARRIER_ERRORS:
817 817 break;
818 818
819 819 case ETHER_STAT_TOOLONG_ERRORS:
820 820 *value = vstats.common.rx_oversize_packets;
821 821 break;
822 822
823 823 #if (MAC_VERSION > 1)
824 824 case ETHER_STAT_TOOSHORT_ERRORS:
825 825 *value = vstats.common.rx_undersize_packets;
826 826 break;
827 827 #endif
828 828
829 829 case ETHER_STAT_XCVR_ADDR:
830 830 *value = 0;
831 831 break;
832 832
833 833 case ETHER_STAT_XCVR_ID:
834 834 *value = 0;
835 835 break;
836 836
837 837 case ETHER_STAT_XCVR_INUSE:
838 838 switch (qede->props.link_speed) {
839 839 default:
840 840 *value = XCVR_UNDEFINED;
841 841 }
842 842 break;
843 843 #if (MAC_VERSION > 1)
844 844 case ETHER_STAT_CAP_10GFDX:
845 845 *value = 0;
846 846 break;
847 847 #endif
848 848 case ETHER_STAT_CAP_100FDX:
849 849 *value = 0;
850 850 break;
851 851 case ETHER_STAT_CAP_100HDX:
852 852 *value = 0;
853 853 break;
854 854 case ETHER_STAT_CAP_ASMPAUSE:
855 855 *value = 1;
856 856 break;
857 857 case ETHER_STAT_CAP_PAUSE:
858 858 *value = 1;
859 859 break;
860 860 case ETHER_STAT_CAP_AUTONEG:
861 861 *value = 1;
862 862 break;
863 863
864 864 #if (MAC_VERSION > 1)
865 865 case ETHER_STAT_CAP_REMFAULT:
866 866 *value = 0;
867 867 break;
868 868 #endif
869 869
870 870 #if (MAC_VERSION > 1)
871 871 case ETHER_STAT_ADV_CAP_10GFDX:
872 872 *value = 0;
873 873 break;
874 874 #endif
875 875 case ETHER_STAT_ADV_CAP_ASMPAUSE:
876 876 *value = 1;
877 877 break;
878 878
879 879 case ETHER_STAT_ADV_CAP_PAUSE:
880 880 *value = 1;
881 881 break;
882 882
883 883 case ETHER_STAT_ADV_CAP_AUTONEG:
884 884 *value = qede->curcfg.adv_capab.autoneg;
885 885 break;
886 886
887 887 #if (MAC_VERSION > 1)
888 888 case ETHER_STAT_ADV_REMFAULT:
889 889 *value = 0;
890 890 break;
891 891 #endif
892 892
893 893 case ETHER_STAT_LINK_AUTONEG:
894 894 *value = qede->curcfg.autoneg;
895 895 break;
896 896
897 897 case ETHER_STAT_LINK_DUPLEX:
898 898 *value = (qede->props.link_duplex == DUPLEX_FULL) ?
899 899 LINK_DUPLEX_FULL : LINK_DUPLEX_HALF;
900 900 break;
901 901 /*
902 902 * Supported speeds. These indicate what hardware is capable of.
903 903 */
904 904 case ETHER_STAT_CAP_1000HDX:
905 905 *value = qede->curcfg.supp_capab.param_1000hdx;
906 906 break;
907 907
908 908 case ETHER_STAT_CAP_1000FDX:
909 909 *value = qede->curcfg.supp_capab.param_1000fdx;
910 910 break;
911 911
912 912 case ETHER_STAT_CAP_10GFDX:
913 913 *value = qede->curcfg.supp_capab.param_10000fdx;
914 914 break;
915 915
916 916 case ETHER_STAT_CAP_25GFDX:
917 917 *value = qede->curcfg.supp_capab.param_25000fdx;
918 918 break;
919 919
920 920 case ETHER_STAT_CAP_40GFDX:
921 921 *value = qede->curcfg.supp_capab.param_40000fdx;
922 922 break;
923 923
924 924 case ETHER_STAT_CAP_50GFDX:
925 925 *value = qede->curcfg.supp_capab.param_50000fdx;
926 926 break;
927 927
928 928 case ETHER_STAT_CAP_100GFDX:
929 929 *value = qede->curcfg.supp_capab.param_100000fdx;
930 930 break;
931 931
932 932 /*
933 933 * Advertised speeds. These indicate what hardware is currently sending.
934 934 */
935 935 case ETHER_STAT_ADV_CAP_1000HDX:
936 936 *value = qede->curcfg.adv_capab.param_1000hdx;
937 937 break;
938 938
939 939 case ETHER_STAT_ADV_CAP_1000FDX:
940 940 *value = qede->curcfg.adv_capab.param_1000fdx;
941 941 break;
942 942
943 943 case ETHER_STAT_ADV_CAP_10GFDX:
944 944 *value = qede->curcfg.adv_capab.param_10000fdx;
945 945 break;
946 946
947 947 case ETHER_STAT_ADV_CAP_25GFDX:
948 948 *value = qede->curcfg.adv_capab.param_25000fdx;
949 949 break;
950 950
951 951 case ETHER_STAT_ADV_CAP_40GFDX:
952 952 *value = qede->curcfg.adv_capab.param_40000fdx;
953 953 break;
954 954
955 955 case ETHER_STAT_ADV_CAP_50GFDX:
956 956 *value = qede->curcfg.adv_capab.param_50000fdx;
957 957 break;
958 958
959 959 case ETHER_STAT_ADV_CAP_100GFDX:
960 960 *value = qede->curcfg.adv_capab.param_100000fdx;
961 961 break;
962 962
963 963 default:
964 964 rc = ENOTSUP;
965 965 }
966 966
967 967 mutex_exit(&qede->gld_lock);
968 968 return (rc);
969 969 }
970 970
971 971 /* (flag) TRUE = on, FALSE = off */
972 972 static int
973 973 qede_mac_promiscuous(void *arg,
974 974 boolean_t on)
975 975 {
976 976 qede_t *qede = (qede_t *)arg;
977 977 qede_print("!%s(%d): called", __func__,qede->instance);
978 978 int ret = DDI_SUCCESS;
979 979 enum qede_filter_rx_mode_type mode;
980 980
981 981 mutex_enter(&qede->drv_lock);
982 982
983 983 if (qede->qede_state == QEDE_STATE_SUSPENDED) {
984 984 ret = ECANCELED;
985 985 goto exit;
986 986 }
987 987
988 988 if (on) {
989 989 qede_info(qede, "Entering promiscuous mode");
990 990 mode = QEDE_FILTER_RX_MODE_PROMISC;
991 991 qede->params.promisc_fl = B_TRUE;
992 992 } else {
993 993 qede_info(qede, "Leaving promiscuous mode");
994 994 if(qede->params.multi_promisc_fl == B_TRUE) {
995 995 mode = QEDE_FILTER_RX_MODE_MULTI_PROMISC;
996 996 } else {
997 997 mode = QEDE_FILTER_RX_MODE_REGULAR;
998 998 }
999 999 qede->params.promisc_fl = B_FALSE;
1000 1000 }
1001 1001
1002 1002 ret = qede_set_filter_rx_mode(qede, mode);
1003 1003
1004 1004 exit:
1005 1005 mutex_exit(&qede->drv_lock);
1006 1006 return (ret);
1007 1007 }
1008 1008
1009 1009 int qede_set_rx_mac_mcast(qede_t *qede, enum ecore_filter_opcode opcode,
1010 1010 uint8_t *mac, int mc_cnt)
1011 1011 {
1012 1012 struct ecore_filter_mcast cmd;
1013 1013 int i;
1014 1014 memset(&cmd, 0, sizeof(cmd));
1015 1015 cmd.opcode = opcode;
1016 1016 cmd.num_mc_addrs = mc_cnt;
1017 1017
1018 1018 for (i = 0; i < mc_cnt; i++, mac += ETH_ALLEN) {
1019 1019 COPY_ETH_ADDRESS(mac, cmd.mac[i]);
1020 1020 }
1021 1021
1022 1022
1023 1023 return (ecore_filter_mcast_cmd(&qede->edev, &cmd,
1024 1024 ECORE_SPQ_MODE_CB, NULL));
1025 1025
1026 1026 }
1027 1027
1028 1028 int
1029 1029 qede_set_filter_rx_mode(qede_t * qede, enum qede_filter_rx_mode_type type)
1030 1030 {
1031 1031 struct ecore_filter_accept_flags flg;
1032 1032
1033 1033 memset(&flg, 0, sizeof(flg));
1034 1034
1035 1035 flg.update_rx_mode_config = 1;
1036 1036 flg.update_tx_mode_config = 1;
1037 1037 flg.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
1038 1038 ECORE_ACCEPT_MCAST_MATCHED | ECORE_ACCEPT_BCAST;
1039 1039 flg.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
1040 1040 ECORE_ACCEPT_MCAST_MATCHED | ECORE_ACCEPT_BCAST;
1041 1041
1042 1042 if (type == QEDE_FILTER_RX_MODE_PROMISC)
1043 1043 flg.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
1044 1044 ECORE_ACCEPT_MCAST_UNMATCHED;
1045 1045 else if (type == QEDE_FILTER_RX_MODE_MULTI_PROMISC)
1046 1046 flg.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
1047 1047 qede_info(qede, "rx_mode rx_filter=0x%x tx_filter=0x%x type=0x%x\n",
1048 1048 flg.rx_accept_filter, flg.tx_accept_filter, type);
1049 1049 return (ecore_filter_accept_cmd(&qede->edev, 0, flg,
1050 1050 0, /* update_accept_any_vlan */
1051 1051 0, /* accept_any_vlan */
1052 1052 ECORE_SPQ_MODE_CB, NULL));
1053 1053 }
1054 1054
1055 1055 int
1056 1056 qede_multicast(qede_t *qede, boolean_t flag, const uint8_t *ptr_mcaddr)
1057 1057 {
1058 1058 int i, ret = DDI_SUCCESS;
1059 1059 qede_mcast_list_entry_t *ptr_mlist;
1060 1060 qede_mcast_list_entry_t *ptr_entry;
1061 1061 int mc_cnt;
1062 1062 unsigned char *mc_macs, *tmpmc;
1063 1063 size_t size;
1064 1064 boolean_t mcmac_exists = B_FALSE;
1065 1065 enum qede_filter_rx_mode_type mode;
1066 1066
1067 1067 if (!ptr_mcaddr) {
1068 1068 cmn_err(CE_NOTE, "Removing all multicast");
1069 1069 } else {
1070 1070 cmn_err(CE_NOTE,
1071 1071 "qede=%p %s multicast: %02x:%02x:%02x:%02x:%02x:%02x",
1072 1072 qede, (flag) ? "Adding" : "Removing", ptr_mcaddr[0],
1073 1073 ptr_mcaddr[1],ptr_mcaddr[2],ptr_mcaddr[3],ptr_mcaddr[4],
1074 1074 ptr_mcaddr[5]);
1075 1075 }
1076 1076
1077 1077
1078 1078 if (flag && (ptr_mcaddr == NULL)) {
1079 1079 cmn_err(CE_WARN, "ERROR: Multicast address not specified");
1080 1080 return EINVAL;
1081 1081 }
1082 1082
1083 1083
1084 1084 /* exceeds addition of mcaddr above limit */
1085 1085 if (flag && (qede->mc_cnt >= MAX_MC_SOFT_LIMIT)) {
1086 1086 qede_info(qede, "Cannot add more than MAX_MC_SOFT_LIMIT");
1087 1087 return ENOENT;
1088 1088 }
1089 1089
1090 1090 size = MAX_MC_SOFT_LIMIT * ETH_ALLEN;
1091 1091
1092 1092 mc_macs = kmem_zalloc(size, KM_NOSLEEP);
1093 1093 if (!mc_macs) {
1094 1094 cmn_err(CE_WARN, "ERROR: Failed to allocate for mc_macs");
1095 1095 return EINVAL;
1096 1096 }
1097 1097
1098 1098 tmpmc = mc_macs;
1099 1099
1100 1100 /* remove all multicast - as flag not set and mcaddr not specified*/
1101 1101 if (!flag && (ptr_mcaddr == NULL)) {
1102 1102 QEDE_LIST_FOR_EACH_ENTRY(ptr_entry,
1103 1103 &qede->mclist.head, qede_mcast_list_entry_t, mclist_entry)
1104 1104 {
1105 1105 if (ptr_entry != NULL) {
1106 1106 QEDE_LIST_REMOVE(&ptr_entry->mclist_entry,
1107 1107 &qede->mclist.head);
1108 1108 kmem_free(ptr_entry,
1109 1109 sizeof (qede_mcast_list_entry_t) + ETH_ALLEN);
1110 1110 }
1111 1111 }
1112 1112
1113 1113 ret = qede_set_rx_mac_mcast(qede,
1114 1114 ECORE_FILTER_REMOVE, mc_macs, 1);
1115 1115 qede->mc_cnt = 0;
1116 1116 goto exit;
1117 1117 }
1118 1118
1119 1119 QEDE_LIST_FOR_EACH_ENTRY(ptr_entry,
1120 1120 &qede->mclist.head, qede_mcast_list_entry_t, mclist_entry)
1121 1121 {
1122 1122 if ((ptr_entry != NULL) &&
1123 1123 IS_ETH_ADDRESS_EQUAL(ptr_mcaddr, ptr_entry->mac)) {
1124 1124 mcmac_exists = B_TRUE;
1125 1125 break;
1126 1126 }
1127 1127 }
1128 1128 if (flag && mcmac_exists) {
1129 1129 ret = DDI_SUCCESS;
1130 1130 goto exit;
1131 1131 } else if (!flag && !mcmac_exists) {
1132 1132 ret = DDI_SUCCESS;
1133 1133 goto exit;
1134 1134 }
1135 1135
1136 1136 if (flag) {
1137 1137 ptr_entry = kmem_zalloc((sizeof (qede_mcast_list_entry_t) +
1138 1138 ETH_ALLEN), KM_NOSLEEP);
1139 1139 ptr_entry->mac = (uint8_t *)ptr_entry +
1140 1140 sizeof (qede_mcast_list_entry_t);
1141 1141 COPY_ETH_ADDRESS(ptr_mcaddr, ptr_entry->mac);
1142 1142 QEDE_LIST_ADD(&ptr_entry->mclist_entry, &qede->mclist.head);
1143 1143 } else {
1144 1144 QEDE_LIST_REMOVE(&ptr_entry->mclist_entry, &qede->mclist.head);
1145 1145 kmem_free(ptr_entry, sizeof(qede_mcast_list_entry_t) +
1146 1146 ETH_ALLEN);
1147 1147 }
1148 1148
1149 1149 mc_cnt = 0;
1150 1150 QEDE_LIST_FOR_EACH_ENTRY(ptr_entry, &qede->mclist.head,
1151 1151 qede_mcast_list_entry_t, mclist_entry) {
1152 1152 COPY_ETH_ADDRESS(ptr_entry->mac, tmpmc);
1153 1153 tmpmc += ETH_ALLEN;
1154 1154 mc_cnt++;
1155 1155 }
1156 1156 qede->mc_cnt = mc_cnt;
1157 1157 if (mc_cnt <=64) {
|
↓ open down ↓ |
1157 lines elided |
↑ open up ↑ |
1158 1158 ret = qede_set_rx_mac_mcast(qede, ECORE_FILTER_ADD,
1159 1159 (unsigned char *)mc_macs, mc_cnt);
1160 1160 if ((qede->params.multi_promisc_fl == B_TRUE) &&
1161 1161 (qede->params.promisc_fl == B_FALSE)) {
1162 1162 mode = QEDE_FILTER_RX_MODE_REGULAR;
1163 1163 ret = qede_set_filter_rx_mode(qede, mode);
1164 1164 }
1165 1165 qede->params.multi_promisc_fl = B_FALSE;
1166 1166 } else {
1167 1167 if ((qede->params.multi_promisc_fl == B_FALSE) &&
1168 - (qede->params.promisc_fl = B_FALSE)) {
1168 + (qede->params.promisc_fl == B_FALSE)) {
1169 1169 ret = qede_set_filter_rx_mode(qede,
1170 1170 QEDE_FILTER_RX_MODE_MULTI_PROMISC);
1171 1171 }
1172 1172 qede->params.multi_promisc_fl = B_TRUE;
1173 1173 qede_info(qede, "mode is MULTI_PROMISC");
1174 1174 }
1175 1175 exit:
1176 1176 kmem_free(mc_macs, size);
1177 1177 qede_info(qede, "multicast ret %d mc_cnt %d\n", ret, qede->mc_cnt);
1178 1178 return (ret);
1179 1179 }
1180 1180
1181 1181 /*
1182 1182 * This function is used to enable or disable multicast packet reception for
1183 1183 * particular multicast addresses.
1184 1184 * (flag) TRUE = add, FALSE = remove
1185 1185 */
1186 1186 static int
1187 1187 qede_mac_multicast(void *arg,
1188 1188 boolean_t flag,
1189 1189 const uint8_t * mcast_addr)
1190 1190 {
1191 1191 qede_t *qede = (qede_t *)arg;
1192 1192 int ret = DDI_SUCCESS;
1193 1193
1194 1194
1195 1195 mutex_enter(&qede->gld_lock);
1196 1196 if(qede->qede_state != QEDE_STATE_STARTED) {
1197 1197 mutex_exit(&qede->gld_lock);
1198 1198 return (EAGAIN);
1199 1199 }
1200 1200 ret = qede_multicast(qede, flag, mcast_addr);
1201 1201
1202 1202 mutex_exit(&qede->gld_lock);
1203 1203
1204 1204 return (ret);
1205 1205 }
1206 1206 int
1207 1207 qede_clear_filters(qede_t *qede)
1208 1208 {
1209 1209 int ret = 0;
1210 1210 int i;
1211 1211 if ((qede->params.promisc_fl == B_TRUE) ||
1212 1212 (qede->params.multi_promisc_fl == B_TRUE)) {
1213 1213 ret = qede_set_filter_rx_mode(qede,
1214 1214 QEDE_FILTER_RX_MODE_REGULAR);
1215 1215 if (ret) {
1216 1216 qede_info(qede,
1217 1217 "qede_clear_filters failed to set rx_mode");
1218 1218 }
1219 1219 }
1220 1220 for (i=0; i < qede->ucst_total; i++)
1221 1221 {
1222 1222 if (qede->ucst_mac[i].set) {
1223 1223 qede_rem_macaddr(qede,
1224 1224 qede->ucst_mac[i].mac_addr.ether_addr_octet);
1225 1225 }
1226 1226 }
1227 1227 qede_multicast(qede, B_FALSE, NULL);
1228 1228 return (ret);
1229 1229 }
1230 1230
1231 1231
1232 1232 #ifdef NO_CROSSBOW
1233 1233 static int
1234 1234 qede_mac_unicast(void *arg,
1235 1235 const uint8_t * mac_addr)
1236 1236 {
1237 1237 qede_t *qede = (qede_t *)arg;
1238 1238 return 0;
1239 1239 }
1240 1240
1241 1241
1242 1242 static mblk_t *
1243 1243 qede_mac_tx(void *arg,
1244 1244 mblk_t * mblk)
1245 1245 {
1246 1246 qede_t *qede = (qede_t *)arg;
1247 1247 qede_fastpath_t *fp = &qede->fp_array[0];
1248 1248
1249 1249 mblk = qede_ring_tx((void *)fp, mblk);
1250 1250
1251 1251 return (mblk);
1252 1252 }
1253 1253 #endif /* NO_CROSSBOW */
1254 1254
1255 1255
1256 1256 static lb_property_t loopmodes[] = {
1257 1257 { normal, "normal", QEDE_LOOP_NONE },
1258 1258 { internal, "internal", QEDE_LOOP_INTERNAL },
1259 1259 { external, "external", QEDE_LOOP_EXTERNAL },
1260 1260 };
1261 1261
1262 1262 /*
1263 1263 * Set Loopback mode
1264 1264 */
1265 1265
1266 1266 static enum ioc_reply
1267 1267 qede_set_loopback_mode(qede_t *qede, uint32_t mode)
1268 1268 {
1269 1269 int i = 0;
1270 1270 struct ecore_dev *edev = &qede->edev;
1271 1271 struct ecore_hwfn *hwfn;
1272 1272 struct ecore_ptt *ptt = NULL;
1273 1273 struct ecore_mcp_link_params *link_params;
1274 1274
1275 1275 hwfn = &edev->hwfns[0];
1276 1276 link_params = ecore_mcp_get_link_params(hwfn);
1277 1277 ptt = ecore_ptt_acquire(hwfn);
1278 1278
1279 1279 switch(mode) {
1280 1280 default:
1281 1281 qede_info(qede, "unknown loopback mode !!");
1282 1282 ecore_ptt_release(hwfn, ptt);
1283 1283 return IOC_INVAL;
1284 1284
1285 1285 case QEDE_LOOP_NONE:
1286 1286 ecore_mcp_set_link(hwfn, ptt, 0);
1287 1287
1288 1288 while (qede->params.link_state && i < 5000) {
1289 1289 OSAL_MSLEEP(1);
1290 1290 i++;
1291 1291 }
1292 1292 i = 0;
1293 1293
1294 1294 link_params->loopback_mode = ETH_LOOPBACK_NONE;
1295 1295 qede->loop_back_mode = QEDE_LOOP_NONE;
1296 1296 (void) ecore_mcp_set_link(hwfn, ptt, 1);
1297 1297 ecore_ptt_release(hwfn, ptt);
1298 1298
1299 1299 while (!qede->params.link_state && i < 5000) {
1300 1300 OSAL_MSLEEP(1);
1301 1301 i++;
1302 1302 }
1303 1303 return IOC_REPLY;
1304 1304
1305 1305 case QEDE_LOOP_INTERNAL:
1306 1306 qede_print("!%s(%d) : loopback mode (INTERNAL) is set!",
1307 1307 __func__, qede->instance);
1308 1308 ecore_mcp_set_link(hwfn, ptt, 0);
1309 1309
1310 1310 while(qede->params.link_state && i < 5000) {
1311 1311 OSAL_MSLEEP(1);
1312 1312 i++;
1313 1313 }
1314 1314 i = 0;
1315 1315 link_params->loopback_mode = ETH_LOOPBACK_INT_PHY;
1316 1316 qede->loop_back_mode = QEDE_LOOP_INTERNAL;
1317 1317 (void) ecore_mcp_set_link(hwfn, ptt, 1);
1318 1318 ecore_ptt_release(hwfn, ptt);
1319 1319
1320 1320 while(!qede->params.link_state && i < 5000) {
1321 1321 OSAL_MSLEEP(1);
1322 1322 i++;
1323 1323 }
1324 1324 return IOC_REPLY;
1325 1325
1326 1326 case QEDE_LOOP_EXTERNAL:
1327 1327 qede_print("!%s(%d) : External loopback mode is not supported",
1328 1328 __func__, qede->instance);
1329 1329 ecore_ptt_release(hwfn, ptt);
1330 1330 return IOC_INVAL;
1331 1331 }
1332 1332 }
1333 1333
1334 1334 static int
1335 1335 qede_ioctl_pcicfg_rd(qede_t *qede, u32 addr, void *data,
1336 1336 int len)
1337 1337 {
1338 1338 u32 crb, actual_crb;
1339 1339 uint32_t ret = 0;
1340 1340 int cap_offset = 0, cap_id = 0, next_cap = 0;
1341 1341 ddi_acc_handle_t pci_cfg_handle = qede->pci_cfg_handle;
1342 1342 qede_ioctl_data_t * data1 = (qede_ioctl_data_t *) data;
1343 1343
1344 1344 cap_offset = pci_config_get8(pci_cfg_handle, PCI_CONF_CAP_PTR);
1345 1345 while (cap_offset != 0) {
1346 1346 /* Check for an invalid PCI read. */
1347 1347 if (cap_offset == PCI_EINVAL8) {
1348 1348 return DDI_FAILURE;
1349 1349 }
1350 1350 cap_id = pci_config_get8(pci_cfg_handle, cap_offset);
1351 1351 if (cap_id == PCI_CAP_ID_PCI_E) {
1352 1352 /* PCIe expr capab struct found */
1353 1353 break;
1354 1354 } else {
1355 1355 next_cap = pci_config_get8(pci_cfg_handle,
1356 1356 cap_offset + 1);
1357 1357 cap_offset = next_cap;
1358 1358 }
1359 1359 }
1360 1360
1361 1361 switch (len) {
1362 1362 case 1:
1363 1363 ret = pci_config_get8(qede->pci_cfg_handle, addr);
1364 1364 (void) memcpy(data, &ret, sizeof(uint8_t));
1365 1365 break;
1366 1366 case 2:
1367 1367 ret = pci_config_get16(qede->pci_cfg_handle, addr);
1368 1368 (void) memcpy(data, &ret, sizeof(uint16_t));
1369 1369 break;
1370 1370 case 4:
1371 1371 ret = pci_config_get32(qede->pci_cfg_handle, addr);
1372 1372 (void) memcpy(data, &ret, sizeof(uint32_t));
1373 1373 break;
1374 1374 default:
1375 1375 cmn_err(CE_WARN, "bad length for pci config read\n");
1376 1376 return (1);
1377 1377 }
1378 1378 return (0);
1379 1379 }
1380 1380
1381 1381 static int
1382 1382 qede_ioctl_pcicfg_wr(qede_t *qede, u32 addr, void *data,
1383 1383 int len)
1384 1384 {
1385 1385 uint16_t ret = 0;
1386 1386 int cap_offset = 0, cap_id = 0, next_cap = 0;
1387 1387 qede_ioctl_data_t * data1 = (qede_ioctl_data_t *) data;
1388 1388 ddi_acc_handle_t pci_cfg_handle = qede->pci_cfg_handle;
1389 1389 #if 1
1390 1390 cap_offset = pci_config_get8(pci_cfg_handle, PCI_CONF_CAP_PTR);
1391 1391 while (cap_offset != 0) {
1392 1392 cap_id = pci_config_get8(pci_cfg_handle, cap_offset);
1393 1393 if (cap_id == PCI_CAP_ID_PCI_E) {
1394 1394 /* PCIe expr capab struct found */
1395 1395 break;
1396 1396 } else {
1397 1397 next_cap = pci_config_get8(pci_cfg_handle,
1398 1398 cap_offset + 1);
1399 1399 cap_offset = next_cap;
1400 1400 }
1401 1401 }
1402 1402 #endif
1403 1403
1404 1404 switch(len) {
1405 1405 case 1:
1406 1406 pci_config_put8(qede->pci_cfg_handle, addr,
1407 1407 *(char *)&(data));
1408 1408 break;
1409 1409 case 2:
1410 1410 ret = pci_config_get16(qede->pci_cfg_handle, addr);
1411 1411 ret = ret | *(uint16_t *)data1->uabc;
1412 1412
1413 1413 pci_config_put16(qede->pci_cfg_handle, addr,
1414 1414 ret);
1415 1415 break;
1416 1416 case 4:
1417 1417 pci_config_put32(qede->pci_cfg_handle, addr, *(uint32_t *)data1->uabc);
1418 1418 break;
1419 1419
1420 1420 default:
1421 1421 return (1);
1422 1422 }
1423 1423 return (0);
1424 1424 }
1425 1425
1426 1426 static int
1427 1427 qede_ioctl_rd_wr_reg(qede_t *qede, void *data)
1428 1428 {
1429 1429 struct ecore_hwfn *p_hwfn;
1430 1430 struct ecore_dev *edev = &qede->edev;
1431 1431 struct ecore_ptt *ptt;
1432 1432 qede_ioctl_data_t *data1 = (qede_ioctl_data_t *)data;
1433 1433 uint32_t ret = 0;
1434 1434 uint8_t cmd = (uint8_t) data1->unused1;
1435 1435 uint32_t addr = data1->off;
1436 1436 uint32_t val = *(uint32_t *)&data1->uabc[1];
1437 1437 uint32_t hwfn_index = *(uint32_t *)&data1->uabc[5];
1438 1438 uint32_t *reg_addr;
1439 1439
1440 1440 if (hwfn_index > qede->num_hwfns) {
1441 1441 cmn_err(CE_WARN, "invalid hwfn index from application\n");
1442 1442 return (EINVAL);
1443 1443 }
1444 1444 p_hwfn = &edev->hwfns[hwfn_index];
1445 1445
1446 1446 switch(cmd) {
1447 1447 case QEDE_REG_READ:
1448 1448 ret = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, addr);
1449 1449 (void) memcpy(data1->uabc, &ret, sizeof(uint32_t));
1450 1450 break;
1451 1451
1452 1452 case QEDE_REG_WRITE:
1453 1453 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, addr, val);
1454 1454 break;
1455 1455
1456 1456 default:
1457 1457 cmn_err(CE_WARN,
1458 1458 "wrong command in register read/write from application\n");
1459 1459 break;
1460 1460 }
1461 1461 return (ret);
1462 1462 }
1463 1463
1464 1464 static int
1465 1465 qede_ioctl_rd_wr_nvram(qede_t *qede, mblk_t *mp)
1466 1466 {
1467 1467 qede_nvram_data_t *data1 = (qede_nvram_data_t *)(mp->b_cont->b_rptr);
1468 1468 qede_nvram_data_t *data2, *next_data;
1469 1469 struct ecore_dev *edev = &qede->edev;
1470 1470 uint32_t hdr_size = 24, bytes_to_copy, copy_len = 0;
1471 1471 uint32_t copy_len1 = 0;
1472 1472 uint32_t addr = data1->off;
1473 1473 uint32_t size = data1->size, i, buf_size;
1474 1474 uint8_t cmd, cmd2;
1475 1475 uint8_t *buf, *tmp_buf;
1476 1476 mblk_t *mp1;
1477 1477
1478 1478 cmd = (uint8_t)data1->unused1;
1479 1479
1480 1480 switch(cmd) {
1481 1481 case QEDE_NVRAM_CMD_READ:
1482 1482 buf = kmem_zalloc(size, GFP_KERNEL);
1483 1483 if(buf == NULL) {
1484 1484 cmn_err(CE_WARN, "memory allocation failed"
1485 1485 " in nvram read ioctl\n");
1486 1486 return (DDI_FAILURE);
1487 1487 }
1488 1488 (void) ecore_mcp_nvm_read(edev, addr, buf, data1->size);
1489 1489
1490 1490 copy_len = (MBLKL(mp->b_cont)) - hdr_size;
1491 1491 if(copy_len > size) {
1492 1492 (void) memcpy(data1->uabc, buf, size);
1493 1493 kmem_free(buf, size);
1494 1494 //OSAL_FREE(edev, buf);
1495 1495 break;
1496 1496 }
1497 1497 (void) memcpy(data1->uabc, buf, copy_len);
1498 1498 bytes_to_copy = size - copy_len;
1499 1499 tmp_buf = ((uint8_t *)buf) + copy_len;
1500 1500 copy_len1 = copy_len;
1501 1501 mp1 = mp->b_cont;
1502 1502 mp1 = mp1->b_cont;
1503 1503
1504 1504 while (mp1) {
1505 1505 copy_len = MBLKL(mp1);
1506 1506 if(mp1->b_cont == NULL) {
1507 1507 copy_len = MBLKL(mp1) - 4;
1508 1508 }
1509 1509 data2 = (qede_nvram_data_t *)mp1->b_rptr;
1510 1510 if (copy_len > bytes_to_copy) {
1511 1511 (void) memcpy(data2->uabc, tmp_buf,
1512 1512 bytes_to_copy);
1513 1513 kmem_free(buf, size);
1514 1514 //OSAL_FREE(edev, buf);
1515 1515 break;
1516 1516 }
1517 1517 (void) memcpy(data2->uabc, tmp_buf, copy_len);
1518 1518 tmp_buf = tmp_buf + copy_len;
1519 1519 copy_len += copy_len;
1520 1520 mp1 = mp1->b_cont;
1521 1521 bytes_to_copy = bytes_to_copy - copy_len;
1522 1522 }
1523 1523
1524 1524 kmem_free(buf, size);
1525 1525 //OSAL_FREE(edev, buf);
1526 1526 break;
1527 1527
1528 1528 case QEDE_NVRAM_CMD_WRITE:
1529 1529 cmd2 = (uint8_t )data1->cmd2;
1530 1530 size = data1->size;
1531 1531 addr = data1->off;
1532 1532 buf_size = size; //data1->buf_size;
1533 1533 //buf_size = data1->buf_size;
1534 1534
1535 1535 switch(cmd2){
1536 1536 case START_NVM_WRITE:
1537 1537 buf = kmem_zalloc(size, GFP_KERNEL);
1538 1538 //buf = qede->reserved_buf;
1539 1539 qede->nvm_buf_size = data1->size;
1540 1540 if(buf == NULL) {
1541 1541 cmn_err(CE_WARN,
1542 1542 "memory allocation failed in START_NVM_WRITE\n");
1543 1543 return DDI_FAILURE;
1544 1544 }
1545 1545 qede->nvm_buf_start = buf;
1546 1546 cmn_err(CE_NOTE,
1547 1547 "buf = %p, size = %x\n", qede->nvm_buf_start, size);
1548 1548 qede->nvm_buf = buf;
1549 1549 qede->copy_len = 0;
1550 1550 //tmp_buf = buf + addr;
1551 1551 break;
1552 1552
1553 1553 case ACCUMULATE_NVM_BUF:
1554 1554 tmp_buf = qede->nvm_buf;
1555 1555 copy_len = MBLKL(mp->b_cont) - hdr_size;
1556 1556 if(copy_len > buf_size) {
1557 1557 if (buf_size < qede->nvm_buf_size) {
1558 1558 (void) memcpy(tmp_buf, data1->uabc, buf_size);
1559 1559 qede->copy_len = qede->copy_len +
1560 1560 buf_size;
1561 1561 } else {
1562 1562 (void) memcpy(tmp_buf,
1563 1563 data1->uabc, qede->nvm_buf_size);
1564 1564 qede->copy_len =
1565 1565 qede->copy_len + qede->nvm_buf_size;
1566 1566 }
1567 1567 tmp_buf = tmp_buf + buf_size;
1568 1568 qede->nvm_buf = tmp_buf;
1569 1569 //qede->copy_len = qede->copy_len + buf_size;
1570 1570 cmn_err(CE_NOTE,
1571 1571 "buf_size from app = %x\n", copy_len);
1572 1572 break;
1573 1573 }
1574 1574 (void) memcpy(tmp_buf, data1->uabc, copy_len);
1575 1575 tmp_buf = tmp_buf + copy_len;
1576 1576 bytes_to_copy = buf_size - copy_len;
1577 1577 mp1 = mp->b_cont;
1578 1578 mp1 = mp1->b_cont;
1579 1579 copy_len1 = copy_len;
1580 1580
1581 1581 while (mp1) {
1582 1582 copy_len = MBLKL(mp1);
1583 1583 if (mp1->b_cont == NULL) {
1584 1584 copy_len = MBLKL(mp1) - 4;
1585 1585 }
1586 1586 next_data = (qede_nvram_data_t *) mp1->b_rptr;
1587 1587 if (copy_len > bytes_to_copy){
1588 1588 (void) memcpy(tmp_buf, next_data->uabc,
1589 1589 bytes_to_copy);
1590 1590 qede->copy_len = qede->copy_len +
1591 1591 bytes_to_copy;
1592 1592 break;
1593 1593 }
1594 1594 (void) memcpy(tmp_buf, next_data->uabc,
1595 1595 copy_len);
1596 1596 qede->copy_len = qede->copy_len + copy_len;
1597 1597 tmp_buf = tmp_buf + copy_len;
1598 1598 copy_len = copy_len1 + copy_len;
1599 1599 bytes_to_copy = bytes_to_copy - copy_len;
1600 1600 mp1 = mp1->b_cont;
1601 1601 }
1602 1602 qede->nvm_buf = tmp_buf;
1603 1603 break;
1604 1604
1605 1605 case STOP_NVM_WRITE:
1606 1606 //qede->nvm_buf = tmp_buf;
1607 1607 break;
1608 1608 case READ_BUF:
1609 1609 tmp_buf = (uint8_t *)qede->nvm_buf_start;
1610 1610 for(i = 0; i < size ; i++){
1611 1611 cmn_err(CE_NOTE,
1612 1612 "buff (%d) : %d\n", i, *tmp_buf);
1613 1613 tmp_buf ++;
1614 1614 }
1615 1615 break;
1616 1616 }
1617 1617 break;
1618 1618 case QEDE_NVRAM_CMD_PUT_FILE_DATA:
1619 1619 tmp_buf = qede->nvm_buf_start;
1620 1620 (void) ecore_mcp_nvm_write(edev, ECORE_PUT_FILE_DATA,
1621 1621 addr, tmp_buf, size);
1622 1622 kmem_free(qede->nvm_buf_start, size);
1623 1623 //OSAL_FREE(edev, tmp_buf);
1624 1624 cmn_err(CE_NOTE, "total size = %x, copied size = %x\n",
1625 1625 qede->nvm_buf_size, qede->copy_len);
1626 1626 tmp_buf = NULL;
1627 1627 qede->nvm_buf = NULL;
1628 1628 qede->nvm_buf_start = NULL;
1629 1629 break;
1630 1630
1631 1631 case QEDE_NVRAM_CMD_SET_SECURE_MODE:
1632 1632 (void) ecore_mcp_nvm_set_secure_mode(edev, addr);
1633 1633 break;
1634 1634
1635 1635 case QEDE_NVRAM_CMD_DEL_FILE:
1636 1636 (void) ecore_mcp_nvm_del_file(edev, addr);
1637 1637 break;
1638 1638
1639 1639 case QEDE_NVRAM_CMD_PUT_FILE_BEGIN:
1640 1640 (void) ecore_mcp_nvm_put_file_begin(edev, addr);
1641 1641 break;
1642 1642
1643 1643 case QEDE_NVRAM_CMD_GET_NVRAM_RESP:
1644 1644 buf = kmem_zalloc(size, KM_SLEEP);
1645 1645 (void) ecore_mcp_nvm_resp(edev, buf);
1646 1646 (void)memcpy(data1->uabc, buf, size);
1647 1647 kmem_free(buf, size);
1648 1648 break;
1649 1649
1650 1650 default:
1651 1651 cmn_err(CE_WARN,
1652 1652 "wrong command in NVRAM read/write from application\n");
1653 1653 break;
1654 1654 }
1655 1655 return (DDI_SUCCESS);
1656 1656 }
1657 1657
1658 1658 static int
1659 1659 qede_get_func_info(qede_t *qede, void *data)
1660 1660 {
1661 1661 qede_link_output_t link_op;
1662 1662 qede_func_info_t func_info;
1663 1663 qede_ioctl_data_t *data1 = (qede_ioctl_data_t *)data;
1664 1664 struct ecore_dev *edev = &qede->edev;
1665 1665 struct ecore_hwfn *hwfn;
1666 1666 struct ecore_mcp_link_params params;
1667 1667 struct ecore_mcp_link_state link;
1668 1668
1669 1669 hwfn = &edev->hwfns[0];
1670 1670
1671 1671 if(hwfn == NULL){
1672 1672 cmn_err(CE_WARN, "(%s) : cannot acquire hwfn\n",
1673 1673 __func__);
1674 1674 return (DDI_FAILURE);
1675 1675 }
1676 1676 memcpy(¶ms, &hwfn->mcp_info->link_input, sizeof(params));
1677 1677 memcpy(&link, &hwfn->mcp_info->link_output, sizeof(link));
1678 1678
1679 1679 if(link.link_up) {
1680 1680 link_op.link_up = true;
1681 1681 }
1682 1682
1683 1683 link_op.supported_caps = SUPPORTED_FIBRE;
1684 1684 if(params.speed.autoneg) {
1685 1685 link_op.supported_caps |= SUPPORTED_Autoneg;
1686 1686 }
1687 1687
1688 1688 if(params.pause.autoneg ||
1689 1689 (params.pause.forced_rx && params.pause.forced_tx)) {
1690 1690 link_op.supported_caps |= SUPPORTED_Asym_Pause;
1691 1691 }
1692 1692
1693 1693 if (params.pause.autoneg || params.pause.forced_rx ||
1694 1694 params.pause.forced_tx) {
1695 1695 link_op.supported_caps |= SUPPORTED_Pause;
1696 1696 }
1697 1697
1698 1698 if (params.speed.advertised_speeds &
1699 1699 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) {
1700 1700 link_op.supported_caps |= SUPPORTED_1000baseT_Half |
1701 1701 SUPPORTED_1000baseT_Full;
1702 1702 }
1703 1703
1704 1704 if (params.speed.advertised_speeds &
1705 1705 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) {
1706 1706 link_op.supported_caps |= SUPPORTED_10000baseKR_Full;
1707 1707 }
1708 1708
1709 1709 if (params.speed.advertised_speeds &
1710 1710 NVM_CFG1_PORT_DRV_LINK_SPEED_40G) {
1711 1711 link_op.supported_caps |= SUPPORTED_40000baseLR4_Full;
1712 1712 }
1713 1713
1714 1714 link_op.advertised_caps = link_op.supported_caps;
1715 1715
1716 1716 if(link.link_up) {
1717 1717 link_op.speed = link.speed;
1718 1718 } else {
1719 1719 link_op.speed = 0;
1720 1720 }
1721 1721
1722 1722 link_op.duplex = DUPLEX_FULL;
1723 1723 link_op.port = PORT_FIBRE;
1724 1724
1725 1725 link_op.autoneg = params.speed.autoneg;
1726 1726
1727 1727 /* Link partner capabilities */
1728 1728 if (link.partner_adv_speed &
1729 1729 ECORE_LINK_PARTNER_SPEED_1G_HD) {
1730 1730 link_op.lp_caps |= SUPPORTED_1000baseT_Half;
1731 1731 }
1732 1732
1733 1733 if (link.partner_adv_speed &
1734 1734 ECORE_LINK_PARTNER_SPEED_1G_FD) {
1735 1735 link_op.lp_caps |= SUPPORTED_1000baseT_Full;
1736 1736 }
1737 1737
1738 1738 if (link.partner_adv_speed &
1739 1739 ECORE_LINK_PARTNER_SPEED_10G) {
1740 1740 link_op.lp_caps |= SUPPORTED_10000baseKR_Full;
1741 1741 }
1742 1742
1743 1743 if (link.partner_adv_speed &
1744 1744 ECORE_LINK_PARTNER_SPEED_20G) {
1745 1745 link_op.lp_caps |= SUPPORTED_20000baseKR2_Full;
1746 1746 }
1747 1747
1748 1748 if (link.partner_adv_speed &
1749 1749 ECORE_LINK_PARTNER_SPEED_40G) {
1750 1750 link_op.lp_caps |= SUPPORTED_40000baseLR4_Full;
1751 1751 }
1752 1752
1753 1753 if (link.an_complete) {
1754 1754 link_op.lp_caps |= SUPPORTED_Autoneg;
1755 1755 }
1756 1756
1757 1757 if (link.partner_adv_pause) {
1758 1758 link_op.lp_caps |= SUPPORTED_Pause;
1759 1759 }
1760 1760
1761 1761 if (link.partner_adv_pause == ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE ||
1762 1762 link.partner_adv_pause == ECORE_LINK_PARTNER_BOTH_PAUSE) {
1763 1763 link_op.lp_caps |= SUPPORTED_Asym_Pause;
1764 1764 }
1765 1765
1766 1766 func_info.supported = link_op.supported_caps;
1767 1767 func_info.advertising = link_op.advertised_caps;
1768 1768 func_info.speed = link_op.speed;
1769 1769 func_info.duplex = link_op.duplex;
1770 1770 func_info.port = qede->pci_func & 0x1;
1771 1771 func_info.autoneg = link_op.autoneg;
1772 1772
1773 1773 (void) memcpy(data1->uabc, &func_info, sizeof(qede_func_info_t));
1774 1774
1775 1775 return (0);
1776 1776 }
1777 1777
1778 1778 static int
1779 1779 qede_do_ioctl(qede_t *qede, queue_t *q, mblk_t *mp)
1780 1780 {
1781 1781 qede_ioctl_data_t *up_data;
1782 1782 qede_driver_info_t driver_info;
1783 1783 struct ecore_dev *edev = &qede->edev;
1784 1784 struct ecore_hwfn *hwfn;
1785 1785 struct ecore_ptt *ptt = NULL;
1786 1786 struct mcp_file_att attrib;
1787 1787 uint32_t flash_size;
1788 1788 uint32_t mcp_resp, mcp_param, txn_size;
1789 1789 uint32_t cmd, size, ret = 0;
1790 1790 uint64_t off;
1791 1791 int * up_data1;
1792 1792 void * ptr;
1793 1793 mblk_t *mp1 = mp;
1794 1794 char mac_addr[32];
1795 1795
1796 1796 up_data = (qede_ioctl_data_t *)(mp->b_cont->b_rptr);
1797 1797
1798 1798 cmd = up_data->cmd;
1799 1799 off = up_data->off;
1800 1800 size = up_data->size;
1801 1801
1802 1802 switch (cmd) {
1803 1803 case QEDE_DRV_INFO:
1804 1804 hwfn = &edev->hwfns[0];
1805 1805 ptt = ecore_ptt_acquire(hwfn);
1806 1806
1807 1807 snprintf(driver_info.drv_name, MAX_QEDE_NAME_LEN, "%s", "qede");
1808 1808 snprintf(driver_info.drv_version, QEDE_STR_SIZE,
1809 1809 "v:%s", qede->version);
1810 1810 snprintf(driver_info.mfw_version, QEDE_STR_SIZE,
1811 1811 "%s", qede->versionMFW);
1812 1812 snprintf(driver_info.stormfw_version, QEDE_STR_SIZE,
1813 1813 "%s", qede->versionFW);
1814 1814 snprintf(driver_info.bus_info, QEDE_STR_SIZE,
1815 1815 "%s", qede->bus_dev_func);
1816 1816
1817 1817
1818 1818 /*
1819 1819 * calling ecore_mcp_nvm_rd_cmd to find the flash length, i
1820 1820 * 0x08 is equivalent of NVM_TYPE_MFW_TRACE1
1821 1821 */
1822 1822 ecore_mcp_get_flash_size(hwfn, ptt, &flash_size);
1823 1823 driver_info.eeprom_dump_len = flash_size;
1824 1824 (void) memcpy(up_data->uabc, &driver_info,
1825 1825 sizeof (qede_driver_info_t));
1826 1826 up_data->size = sizeof (qede_driver_info_t);
1827 1827
1828 1828 ecore_ptt_release(hwfn, ptt);
1829 1829 break;
1830 1830
1831 1831 case QEDE_RD_PCICFG:
1832 1832 ret = qede_ioctl_pcicfg_rd(qede, off, up_data->uabc, size);
1833 1833 break;
1834 1834
1835 1835 case QEDE_WR_PCICFG:
1836 1836 ret = qede_ioctl_pcicfg_wr(qede, off, up_data, size);
1837 1837 break;
1838 1838
1839 1839 case QEDE_RW_REG:
1840 1840 ret = qede_ioctl_rd_wr_reg(qede, (void *)up_data);
1841 1841 break;
1842 1842
1843 1843 case QEDE_RW_NVRAM:
1844 1844 ret = qede_ioctl_rd_wr_nvram(qede, mp1);
1845 1845 break;
1846 1846
1847 1847 case QEDE_FUNC_INFO:
1848 1848 ret = qede_get_func_info(qede, (void *)up_data);
1849 1849 break;
1850 1850
1851 1851 case QEDE_MAC_ADDR:
1852 1852 snprintf(mac_addr, sizeof(mac_addr),
1853 1853 "%02x:%02x:%02x:%02x:%02x:%02x",
1854 1854 qede->ether_addr[0], qede->ether_addr[1],
1855 1855 qede->ether_addr[2], qede->ether_addr[3],
1856 1856 qede->ether_addr[4], qede->ether_addr[5]);
1857 1857 (void) memcpy(up_data->uabc, &mac_addr, sizeof(mac_addr));
1858 1858 break;
1859 1859
1860 1860 }
1861 1861 //if (cmd == QEDE_RW_NVRAM) {
1862 1862 // miocack (q, mp, (sizeof(qede_ioctl_data_t)), 0);
1863 1863 // return IOC_REPLY;
1864 1864 //}
1865 1865 miocack (q, mp, (sizeof(qede_ioctl_data_t)), ret);
1866 1866 //miocack (q, mp, 0, ret);
1867 1867 return (IOC_REPLY);
1868 1868 }
1869 1869
1870 1870 static void
1871 1871 qede_ioctl(qede_t *qede, int cmd, queue_t *q, mblk_t *mp)
1872 1872 {
1873 1873 void *ptr;
1874 1874
1875 1875 switch(cmd) {
1876 1876 case QEDE_CMD:
1877 1877 (void) qede_do_ioctl(qede, q, mp);
1878 1878 break;
1879 1879 default :
1880 1880 cmn_err(CE_WARN, "qede ioctl command %x not supported\n", cmd);
1881 1881 break;
1882 1882 }
1883 1883 return;
1884 1884 }
1885 1885 enum ioc_reply
1886 1886 qede_loopback_ioctl(qede_t *qede, queue_t *wq, mblk_t *mp,
1887 1887 struct iocblk *iocp)
1888 1888 {
1889 1889 lb_info_sz_t *lb_info_size;
1890 1890 lb_property_t *lb_prop;
1891 1891 uint32_t *lb_mode;
1892 1892 int cmd;
1893 1893
1894 1894 /*
1895 1895 * Validate format of ioctl
1896 1896 */
1897 1897 if(mp->b_cont == NULL) {
1898 1898 return IOC_INVAL;
1899 1899 }
1900 1900
1901 1901 cmd = iocp->ioc_cmd;
1902 1902
1903 1903 switch(cmd) {
1904 1904 default:
1905 1905 qede_print("!%s(%d): unknown ioctl command %x\n",
1906 1906 __func__, qede->instance, cmd);
1907 1907 return IOC_INVAL;
1908 1908 case LB_GET_INFO_SIZE:
1909 1909 if (iocp->ioc_count != sizeof(lb_info_sz_t)) {
1910 1910 qede_info(qede, "error: ioc_count %d, sizeof %d",
1911 1911 iocp->ioc_count, sizeof(lb_info_sz_t));
1912 1912 return IOC_INVAL;
1913 1913 }
1914 1914 lb_info_size = (void *)mp->b_cont->b_rptr;
1915 1915 *lb_info_size = sizeof(loopmodes);
1916 1916 return IOC_REPLY;
1917 1917 case LB_GET_INFO:
1918 1918 if (iocp->ioc_count != sizeof (loopmodes)) {
1919 1919 qede_info(qede, "error: iocp->ioc_count %d, sizepof %d",
1920 1920 iocp->ioc_count, sizeof (loopmodes));
1921 1921 return (IOC_INVAL);
1922 1922 }
1923 1923 lb_prop = (void *)mp->b_cont->b_rptr;
1924 1924 bcopy(loopmodes, lb_prop, sizeof (loopmodes));
1925 1925 return IOC_REPLY;
1926 1926 case LB_GET_MODE:
1927 1927 if (iocp->ioc_count != sizeof (uint32_t)) {
1928 1928 qede_info(qede, "iocp->ioc_count %d, sizeof : %d\n",
1929 1929 iocp->ioc_count, sizeof (uint32_t));
1930 1930 return (IOC_INVAL);
1931 1931 }
1932 1932 lb_mode = (void *)mp->b_cont->b_rptr;
1933 1933 *lb_mode = qede->loop_back_mode;
1934 1934 return IOC_REPLY;
1935 1935 case LB_SET_MODE:
1936 1936 if (iocp->ioc_count != sizeof (uint32_t)) {
1937 1937 qede_info(qede, "iocp->ioc_count %d, sizeof : %d\n",
1938 1938 iocp->ioc_count, sizeof (uint32_t));
1939 1939 return (IOC_INVAL);
1940 1940 }
1941 1941 lb_mode = (void *)mp->b_cont->b_rptr;
1942 1942 return (qede_set_loopback_mode(qede,*lb_mode));
1943 1943 }
1944 1944 }
1945 1945
1946 1946 static void
1947 1947 qede_mac_ioctl(void * arg,
1948 1948 queue_t * wq,
1949 1949 mblk_t * mp)
1950 1950 {
1951 1951 int err, cmd;
1952 1952 qede_t * qede = (qede_t *)arg;
1953 1953 struct iocblk *iocp = (struct iocblk *) (uintptr_t)mp->b_rptr;
1954 1954 enum ioc_reply status = IOC_DONE;
1955 1955 boolean_t need_privilege = B_TRUE;
1956 1956
1957 1957 iocp->ioc_error = 0;
1958 1958 cmd = iocp->ioc_cmd;
1959 1959
1960 1960 mutex_enter(&qede->drv_lock);
1961 1961 if ((qede->qede_state == QEDE_STATE_SUSPENDING) ||
1962 1962 (qede->qede_state == QEDE_STATE_SUSPENDED)) {
1963 1963 mutex_exit(&qede->drv_lock);
1964 1964 miocnak(wq, mp, 0, EINVAL);
1965 1965 return;
1966 1966 }
1967 1967
1968 1968 switch(cmd) {
1969 1969 case QEDE_CMD:
1970 1970 break;
1971 1971 case LB_GET_INFO_SIZE:
1972 1972 case LB_GET_INFO:
1973 1973 case LB_GET_MODE:
1974 1974 need_privilege = B_FALSE;
1975 1975 case LB_SET_MODE:
1976 1976 break;
1977 1977 default:
1978 1978 qede_print("!%s(%d) unknown ioctl command %x\n",
1979 1979 __func__, qede->instance, cmd);
1980 1980 miocnak(wq, mp, 0, EINVAL);
1981 1981 mutex_exit(&qede->drv_lock);
1982 1982 return;
1983 1983 }
1984 1984
1985 1985 if(need_privilege) {
1986 1986 err = secpolicy_net_config(iocp->ioc_cr, B_FALSE);
1987 1987 if(err){
1988 1988 qede_info(qede, "secpolicy() failed");
1989 1989 miocnak(wq, mp, 0, err);
1990 1990 mutex_exit(&qede->drv_lock);
1991 1991 return;
1992 1992 }
1993 1993 }
1994 1994
1995 1995 switch (cmd) {
1996 1996 default:
1997 1997 qede_print("!%s(%d) : unknown ioctl command %x\n",
1998 1998 __func__, qede->instance, cmd);
1999 1999 status = IOC_INVAL;
2000 2000 mutex_exit(&qede->drv_lock);
2001 2001 return;
2002 2002 case LB_GET_INFO_SIZE:
2003 2003 case LB_GET_INFO:
2004 2004 case LB_GET_MODE:
2005 2005 case LB_SET_MODE:
2006 2006 status = qede_loopback_ioctl(qede, wq, mp, iocp);
2007 2007 break;
2008 2008 case QEDE_CMD:
2009 2009 qede_ioctl(qede, cmd, wq, mp);
2010 2010 status = IOC_DONE;
2011 2011 break;
2012 2012 }
2013 2013
2014 2014 switch(status){
2015 2015 default:
2016 2016 qede_print("!%s(%d) : invalid status from ioctl",
2017 2017 __func__,qede->instance);
2018 2018 break;
2019 2019 case IOC_DONE:
2020 2020 /*
2021 2021 * OK, Reply already sent
2022 2022 */
2023 2023
2024 2024 break;
2025 2025 case IOC_REPLY:
2026 2026 mp->b_datap->db_type = iocp->ioc_error == 0 ?
2027 2027 M_IOCACK : M_IOCNAK;
2028 2028 qreply(wq, mp);
2029 2029 break;
2030 2030 case IOC_INVAL:
2031 2031 mutex_exit(&qede->drv_lock);
2032 2032 //miocack(wq, mp, 0, 0);
2033 2033 miocnak(wq, mp, 0, iocp->ioc_error == 0 ?
2034 2034 EINVAL : iocp->ioc_error);
2035 2035 return;
2036 2036 }
2037 2037 mutex_exit(&qede->drv_lock);
2038 2038 }
2039 2039
2040 2040 extern ddi_dma_attr_t qede_buf2k_dma_attr_txbuf;
2041 2041 extern ddi_dma_attr_t qede_dma_attr_rxbuf;
2042 2042 extern ddi_dma_attr_t qede_dma_attr_desc;
2043 2043
2044 2044 static boolean_t
2045 2045 qede_mac_get_capability(void *arg,
2046 2046 mac_capab_t capability,
2047 2047 void * cap_data)
2048 2048 {
2049 2049 qede_t * qede = (qede_t *)arg;
2050 2050 uint32_t *txflags = cap_data;
2051 2051 boolean_t ret = B_FALSE;
2052 2052
2053 2053 switch (capability) {
2054 2054 case MAC_CAPAB_HCKSUM: {
2055 2055 u32 *tx_flags = cap_data;
2056 2056 /*
2057 2057 * Check if checksum is enabled on
2058 2058 * tx and advertise the cksum capab
2059 2059 * to mac layer accordingly. On Rx
2060 2060 * side checksummed packets are
2061 2061 * reveiced anyway
2062 2062 */
2063 2063 qede_info(qede, "%s tx checksum offload",
2064 2064 (qede->checksum == DEFAULT_CKSUM_OFFLOAD) ?
2065 2065 "Enabling":
2066 2066 "Disabling");
2067 2067
2068 2068 if (qede->checksum != DEFAULT_CKSUM_OFFLOAD) {
2069 2069 ret = B_FALSE;
2070 2070 break;
2071 2071 }
2072 2072 /*
2073 2073 * Hardware does not support ICMPv6 checksumming. Right now the
2074 2074 * GLDv3 doesn't provide us a way to specify that we don't
2075 2075 * support that. As such, we cannot indicate
2076 2076 * HCKSUM_INET_FULL_V6.
2077 2077 */
2078 2078
2079 2079 *tx_flags = HCKSUM_INET_FULL_V4 |
2080 2080 HCKSUM_IPHDRCKSUM;
2081 2081 ret = B_TRUE;
2082 2082 break;
2083 2083 }
2084 2084 case MAC_CAPAB_LSO: {
2085 2085 mac_capab_lso_t *cap_lso = (mac_capab_lso_t *)cap_data;
2086 2086
2087 2087 qede_info(qede, "%s large segmentation offload",
2088 2088 qede->lso_enable ? "Enabling": "Disabling");
2089 2089 if (qede->lso_enable) {
2090 2090 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4;
2091 2091 cap_lso->lso_basic_tcp_ipv4.lso_max = QEDE_LSO_MAXLEN;
2092 2092 ret = B_TRUE;
2093 2093 }
2094 2094 break;
2095 2095 }
2096 2096 case MAC_CAPAB_RINGS: {
2097 2097 #ifndef NO_CROSSBOW
2098 2098 mac_capab_rings_t *cap_rings = cap_data;
2099 2099 #ifndef ILLUMOS
2100 2100 cap_rings->mr_version = MAC_RINGS_VERSION_1;
2101 2101 #endif
2102 2102
2103 2103 switch (cap_rings->mr_type) {
2104 2104 case MAC_RING_TYPE_RX:
2105 2105 #ifndef ILLUMOS
2106 2106 cap_rings->mr_flags = MAC_RINGS_VLAN_TRANSPARENT;
2107 2107 #endif
2108 2108 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC;
2109 2109 //cap_rings->mr_rnum = 1; /* qede variable */
2110 2110 cap_rings->mr_rnum = qede->num_fp; /* qede variable */
2111 2111 cap_rings->mr_gnum = 1;
2112 2112 cap_rings->mr_rget = qede_fill_ring;
2113 2113 cap_rings->mr_gget = qede_fill_group;
2114 2114 cap_rings->mr_gaddring = NULL;
2115 2115 cap_rings->mr_gremring = NULL;
2116 2116 #ifndef ILLUMOS
2117 2117 cap_rings->mr_ggetringtc = NULL;
2118 2118 #endif
2119 2119 ret = B_TRUE;
2120 2120 break;
2121 2121 case MAC_RING_TYPE_TX:
2122 2122 #ifndef ILLUMOS
2123 2123 cap_rings->mr_flags = MAC_RINGS_VLAN_TRANSPARENT;
2124 2124 #endif
2125 2125 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC;
2126 2126 //cap_rings->mr_rnum = 1;
2127 2127 cap_rings->mr_rnum = qede->num_fp;
2128 2128 cap_rings->mr_gnum = 0;
2129 2129 cap_rings->mr_rget = qede_fill_ring;
2130 2130 cap_rings->mr_gget = qede_fill_group;
2131 2131 cap_rings->mr_gaddring = NULL;
2132 2132 cap_rings->mr_gremring = NULL;
2133 2133 #ifndef ILLUMOS
2134 2134 cap_rings->mr_ggetringtc = NULL;
2135 2135 #endif
2136 2136 ret = B_TRUE;
2137 2137 break;
2138 2138 default:
2139 2139 ret = B_FALSE;
2140 2140 break;
2141 2141 }
2142 2142 #endif
2143 2143 break; /* CASE MAC_CAPAB_RINGS */
2144 2144 }
2145 2145 #ifdef ILLUMOS
2146 2146 case MAC_CAPAB_TRANSCEIVER: {
2147 2147 mac_capab_transceiver_t *mct = cap_data;
2148 2148
2149 2149 mct->mct_flags = 0;
2150 2150 mct->mct_ntransceivers = qede->edev.num_hwfns;
2151 2151 mct->mct_info = qede_transceiver_info;
2152 2152 mct->mct_read = qede_transceiver_read;
2153 2153
2154 2154 ret = B_TRUE;
2155 2155 break;
2156 2156 }
2157 2157 #endif
2158 2158 default:
2159 2159 break;
2160 2160 }
2161 2161
2162 2162 return (ret);
2163 2163 }
2164 2164
2165 2165 int
2166 2166 qede_configure_link(qede_t *qede, bool op);
2167 2167
2168 2168 static int
2169 2169 qede_mac_set_property(void * arg,
2170 2170 const char * pr_name,
2171 2171 mac_prop_id_t pr_num,
2172 2172 uint_t pr_valsize,
2173 2173 const void * pr_val)
2174 2174 {
2175 2175 qede_t * qede = (qede_t *)arg;
2176 2176 struct ecore_mcp_link_params *link_params;
2177 2177 struct ecore_dev *edev = &qede->edev;
2178 2178 struct ecore_hwfn *hwfn;
2179 2179 int ret_val = 0, i;
2180 2180 uint32_t option;
2181 2181
2182 2182 mutex_enter(&qede->gld_lock);
2183 2183 switch (pr_num)
2184 2184 {
2185 2185 case MAC_PROP_MTU:
2186 2186 bcopy(pr_val, &option, sizeof (option));
2187 2187
2188 2188 if(option == qede->mtu) {
2189 2189 ret_val = 0;
2190 2190 break;
2191 2191 }
2192 2192 if ((option != DEFAULT_JUMBO_MTU) &&
2193 2193 (option != DEFAULT_MTU)) {
2194 2194 ret_val = EINVAL;
2195 2195 break;
2196 2196 }
2197 2197 if(qede->qede_state == QEDE_STATE_STARTED) {
2198 2198 ret_val = EBUSY;
2199 2199 break;
2200 2200 }
2201 2201
2202 2202 ret_val = mac_maxsdu_update(qede->mac_handle, qede->mtu);
2203 2203 if (ret_val == 0) {
2204 2204
2205 2205 qede->mtu = option;
2206 2206 if (option == DEFAULT_JUMBO_MTU) {
2207 2207 qede->jumbo_enable = B_TRUE;
2208 2208 } else {
2209 2209 qede->jumbo_enable = B_FALSE;
2210 2210 }
2211 2211
2212 2212 hwfn = ECORE_LEADING_HWFN(edev);
2213 2213 hwfn->hw_info.mtu = qede->mtu;
2214 2214 ret_val = ecore_mcp_ov_update_mtu(hwfn,
2215 2215 hwfn->p_main_ptt,
2216 2216 hwfn->hw_info.mtu);
2217 2217 if (ret_val != ECORE_SUCCESS) {
2218 2218 qede_print("!%s(%d): MTU change %d option %d"
2219 2219 "FAILED",
2220 2220 __func__,qede->instance, qede->mtu, option);
2221 2221 break;
2222 2222 }
2223 2223 qede_print("!%s(%d): MTU changed %d MTU option"
2224 2224 " %d hwfn %d",
2225 2225 __func__,qede->instance, qede->mtu,
2226 2226 option, hwfn->hw_info.mtu);
2227 2227 }
2228 2228 break;
2229 2229
2230 2230 case MAC_PROP_EN_10GFDX_CAP:
2231 2231 hwfn = &edev->hwfns[0];
2232 2232 link_params = ecore_mcp_get_link_params(hwfn);
2233 2233 if (*(uint8_t *) pr_val) {
2234 2234 link_params->speed.autoneg = 0;
2235 2235 link_params->speed.forced_speed = 10000;
2236 2236 link_params->speed.advertised_speeds =
2237 2237 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
2238 2238 qede->forced_speed_10G = *(uint8_t *)pr_val;
2239 2239 }
2240 2240 else {
2241 2241 memcpy(link_params,
2242 2242 &qede->link_input_params.default_link_params,
2243 2243 sizeof (struct ecore_mcp_link_params));
2244 2244 qede->forced_speed_10G = *(uint8_t *)pr_val;
2245 2245 }
2246 2246 if (qede->qede_state == QEDE_STATE_STARTED) {
2247 2247 qede_configure_link(qede,1);
2248 2248 } else {
2249 2249 mutex_exit(&qede->gld_lock);
2250 2250 return (0);
2251 2251 }
2252 2252 break;
2253 2253 default:
2254 2254 ret_val = ENOTSUP;
2255 2255 break;
2256 2256 }
2257 2257 mutex_exit(&qede->gld_lock);
2258 2258 return (ret_val);
2259 2259 }
2260 2260
2261 2261 static void
2262 2262 qede_mac_stop(void *arg)
2263 2263 {
2264 2264 qede_t *qede = (qede_t *)arg;
2265 2265 int status;
2266 2266
2267 2267 qede_print("!%s(%d): called",
2268 2268 __func__,qede->instance);
2269 2269 mutex_enter(&qede->drv_lock);
2270 2270 status = qede_stop(qede);
2271 2271 if (status != DDI_SUCCESS) {
2272 2272 qede_print("!%s(%d): qede_stop "
2273 2273 "FAILED",
2274 2274 __func__,qede->instance);
2275 2275 }
2276 2276
2277 2277 mac_link_update(qede->mac_handle, LINK_STATE_UNKNOWN);
2278 2278 mutex_exit(&qede->drv_lock);
2279 2279 }
2280 2280
2281 2281 static int
2282 2282 qede_mac_start(void *arg)
2283 2283 {
2284 2284 qede_t *qede = (qede_t *)arg;
2285 2285 int status;
2286 2286
2287 2287 qede_print("!%s(%d): called", __func__,qede->instance);
2288 2288 if (!mutex_tryenter(&qede->drv_lock)) {
2289 2289 return (EAGAIN);
2290 2290 }
2291 2291
2292 2292 if (qede->qede_state == QEDE_STATE_SUSPENDED) {
2293 2293 mutex_exit(&qede->drv_lock);
2294 2294 return (ECANCELED);
2295 2295 }
2296 2296
2297 2297 status = qede_start(qede);
2298 2298 if (status != DDI_SUCCESS) {
2299 2299 mutex_exit(&qede->drv_lock);
2300 2300 return (EIO);
2301 2301 }
2302 2302
2303 2303 mutex_exit(&qede->drv_lock);
2304 2304
2305 2305 #ifdef DBLK_DMA_PREMAP
2306 2306 qede->pm_handle = mac_pmh_tx_get(qede->mac_handle);
2307 2307 #endif
2308 2308 return (0);
2309 2309 }
2310 2310
2311 2311 static int
2312 2312 qede_mac_get_property(void *arg,
2313 2313 const char *pr_name,
2314 2314 mac_prop_id_t pr_num,
2315 2315 uint_t pr_valsize,
2316 2316 void *pr_val)
2317 2317 {
2318 2318 qede_t *qede = (qede_t *)arg;
2319 2319 struct ecore_dev *edev = &qede->edev;
2320 2320 link_state_t link_state;
2321 2321 link_duplex_t link_duplex;
2322 2322 uint64_t link_speed;
2323 2323 link_flowctrl_t link_flowctrl;
2324 2324 struct qede_link_cfg link_cfg;
2325 2325 qede_link_cfg_t *hw_cfg = &qede->hwinit;
2326 2326 int ret_val = 0;
2327 2327
2328 2328 memset(&link_cfg, 0, sizeof (struct qede_link_cfg));
2329 2329 qede_get_link_info(&edev->hwfns[0], &link_cfg);
2330 2330
2331 2331
2332 2332
2333 2333 switch (pr_num)
2334 2334 {
2335 2335 case MAC_PROP_MTU:
2336 2336
2337 2337 ASSERT(pr_valsize >= sizeof(uint32_t));
2338 2338 bcopy(&qede->mtu, pr_val, sizeof(uint32_t));
2339 2339 break;
2340 2340
2341 2341 case MAC_PROP_DUPLEX:
2342 2342
2343 2343 ASSERT(pr_valsize >= sizeof(link_duplex_t));
2344 2344 link_duplex = (qede->props.link_duplex) ?
2345 2345 LINK_DUPLEX_FULL : LINK_DUPLEX_HALF;
2346 2346 bcopy(&link_duplex, pr_val, sizeof(link_duplex_t));
2347 2347 break;
2348 2348
2349 2349 case MAC_PROP_SPEED:
2350 2350
2351 2351 ASSERT(pr_valsize >= sizeof(link_speed));
2352 2352
2353 2353 link_speed = (qede->props.link_speed * 1000000ULL);
2354 2354 bcopy(&link_speed, pr_val, sizeof(link_speed));
2355 2355 break;
2356 2356
2357 2357 case MAC_PROP_STATUS:
2358 2358
2359 2359 ASSERT(pr_valsize >= sizeof(link_state_t));
2360 2360
2361 2361 link_state = (qede->params.link_state) ?
2362 2362 LINK_STATE_UP : LINK_STATE_DOWN;
2363 2363 bcopy(&link_state, pr_val, sizeof(link_state_t));
2364 2364 qede_info(qede, "mac_prop_status %d\n", link_state);
2365 2365 break;
2366 2366
2367 2367 case MAC_PROP_AUTONEG:
2368 2368
2369 2369 *(uint8_t *)pr_val = link_cfg.autoneg;
2370 2370 break;
2371 2371
2372 2372 case MAC_PROP_FLOWCTRL:
2373 2373
2374 2374 ASSERT(pr_valsize >= sizeof(link_flowctrl_t));
2375 2375
2376 2376 /*
2377 2377 * illumos does not have the notion of LINK_FLOWCTRL_AUTO at this time.
2378 2378 */
2379 2379 #ifndef ILLUMOS
2380 2380 if (link_cfg.pause_cfg & QEDE_LINK_PAUSE_AUTONEG_ENABLE) {
2381 2381 link_flowctrl = LINK_FLOWCTRL_AUTO;
2382 2382 }
2383 2383 #endif
2384 2384
2385 2385 if (!(link_cfg.pause_cfg & QEDE_LINK_PAUSE_RX_ENABLE) &&
2386 2386 !(link_cfg.pause_cfg & QEDE_LINK_PAUSE_TX_ENABLE)) {
2387 2387 link_flowctrl = LINK_FLOWCTRL_NONE;
2388 2388 }
2389 2389 if ((link_cfg.pause_cfg & QEDE_LINK_PAUSE_RX_ENABLE) &&
2390 2390 !(link_cfg.pause_cfg & QEDE_LINK_PAUSE_TX_ENABLE)) {
2391 2391 link_flowctrl = LINK_FLOWCTRL_RX;
2392 2392 }
2393 2393 if (!(link_cfg.pause_cfg & QEDE_LINK_PAUSE_RX_ENABLE) &&
2394 2394 (link_cfg.pause_cfg & QEDE_LINK_PAUSE_TX_ENABLE)) {
2395 2395 link_flowctrl = LINK_FLOWCTRL_TX;
2396 2396 }
2397 2397 if ((link_cfg.pause_cfg & QEDE_LINK_PAUSE_RX_ENABLE) &&
2398 2398 (link_cfg.pause_cfg & QEDE_LINK_PAUSE_TX_ENABLE)) {
2399 2399 link_flowctrl = LINK_FLOWCTRL_BI;
2400 2400 }
2401 2401
2402 2402 bcopy(&link_flowctrl, pr_val, sizeof (link_flowctrl_t));
2403 2403 break;
2404 2404
2405 2405 case MAC_PROP_ADV_10GFDX_CAP:
2406 2406 *(uint8_t *)pr_val = link_cfg.adv_capab.param_10000fdx;
2407 2407 break;
2408 2408
2409 2409 case MAC_PROP_EN_10GFDX_CAP:
2410 2410 *(uint8_t *)pr_val = qede->forced_speed_10G;
2411 2411 break;
2412 2412
2413 2413 case MAC_PROP_PRIVATE:
2414 2414 default:
2415 2415 return (ENOTSUP);
2416 2416
2417 2417 }
2418 2418
2419 2419 return (0);
2420 2420 }
2421 2421
2422 2422 static void
2423 2423 qede_mac_property_info(void *arg,
2424 2424 const char *pr_name,
2425 2425 mac_prop_id_t pr_num,
2426 2426 mac_prop_info_handle_t prh)
2427 2427 {
2428 2428 qede_t *qede = (qede_t *)arg;
2429 2429 qede_link_props_t *def_cfg = &qede_def_link_props;
2430 2430 link_flowctrl_t link_flowctrl;
2431 2431
2432 2432
2433 2433 switch (pr_num)
2434 2434 {
2435 2435
2436 2436 case MAC_PROP_STATUS:
2437 2437 case MAC_PROP_SPEED:
2438 2438 case MAC_PROP_DUPLEX:
2439 2439 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
2440 2440 break;
2441 2441
2442 2442 case MAC_PROP_MTU:
2443 2443
2444 2444 mac_prop_info_set_range_uint32(prh,
2445 2445 MIN_MTU,
2446 2446 MAX_MTU);
2447 2447 break;
2448 2448
2449 2449 case MAC_PROP_AUTONEG:
2450 2450
2451 2451 mac_prop_info_set_default_uint8(prh, def_cfg->autoneg);
2452 2452 break;
2453 2453
2454 2454 case MAC_PROP_FLOWCTRL:
2455 2455
2456 2456 if (!def_cfg->pause) {
2457 2457 link_flowctrl = LINK_FLOWCTRL_NONE;
2458 2458 } else {
2459 2459 link_flowctrl = LINK_FLOWCTRL_BI;
2460 2460 }
2461 2461
2462 2462 mac_prop_info_set_default_link_flowctrl(prh, link_flowctrl);
2463 2463 break;
2464 2464
2465 2465 case MAC_PROP_EN_10GFDX_CAP:
2466 2466 mac_prop_info_set_perm(prh, MAC_PROP_PERM_RW);
2467 2467 break;
2468 2468
2469 2469 case MAC_PROP_ADV_10GFDX_CAP:
2470 2470 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
2471 2471 break;
2472 2472
2473 2473 default:
2474 2474 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
2475 2475 break;
2476 2476
2477 2477 }
2478 2478 }
2479 2479
2480 2480 static mac_callbacks_t qede_callbacks =
2481 2481 {
2482 2482 (
2483 2483 MC_IOCTL
2484 2484 /* | MC_RESOURCES */
2485 2485 | MC_SETPROP
2486 2486 | MC_GETPROP
2487 2487 | MC_PROPINFO
2488 2488 | MC_GETCAPAB
2489 2489 ),
2490 2490 qede_mac_stats,
2491 2491 qede_mac_start,
2492 2492 qede_mac_stop,
2493 2493 qede_mac_promiscuous,
2494 2494 qede_mac_multicast,
2495 2495 NULL,
2496 2496 #ifndef NO_CROSSBOW
2497 2497 NULL,
2498 2498 #else
2499 2499 qede_mac_tx,
2500 2500 #endif
2501 2501 NULL, /* qede_mac_resources, */
2502 2502 qede_mac_ioctl,
2503 2503 qede_mac_get_capability,
2504 2504 NULL,
2505 2505 NULL,
2506 2506 qede_mac_set_property,
2507 2507 qede_mac_get_property,
2508 2508 #ifdef MC_PROPINFO
2509 2509 qede_mac_property_info
2510 2510 #endif
2511 2511 };
2512 2512
2513 2513 boolean_t
2514 2514 qede_gld_init(qede_t *qede)
2515 2515 {
2516 2516 int status, ret;
2517 2517 mac_register_t *macp;
2518 2518
2519 2519 macp = mac_alloc(MAC_VERSION);
2520 2520 if (macp == NULL) {
2521 2521 cmn_err(CE_NOTE, "%s: mac_alloc() failed\n", __func__);
2522 2522 return (B_FALSE);
2523 2523 }
2524 2524
2525 2525 macp->m_driver = qede;
2526 2526 macp->m_dip = qede->dip;
2527 2527 macp->m_instance = qede->instance;
2528 2528 macp->m_priv_props = NULL;
2529 2529 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER;
2530 2530 macp->m_src_addr = qede->ether_addr;
2531 2531 macp->m_callbacks = &qede_callbacks;
2532 2532 macp->m_min_sdu = 0;
2533 2533 macp->m_max_sdu = qede->mtu;
2534 2534 macp->m_margin = VLAN_TAGSZ;
2535 2535 #ifdef ILLUMOS
2536 2536 macp->m_v12n = MAC_VIRT_LEVEL1;
2537 2537 #endif
2538 2538
2539 2539 status = mac_register(macp, &qede->mac_handle);
2540 2540 if (status != 0) {
2541 2541 cmn_err(CE_NOTE, "%s: mac_register() failed\n", __func__);
2542 2542 }
2543 2543
2544 2544 mac_free(macp);
2545 2545 if (status == 0) {
2546 2546 return (B_TRUE);
2547 2547 }
2548 2548 return (B_FALSE);
2549 2549 }
2550 2550
2551 2551 boolean_t qede_gld_fini(qede_t * qede)
2552 2552 {
2553 2553 return (B_TRUE);
2554 2554 }
2555 2555
2556 2556
2557 2557 void qede_link_update(qede_t * qede,
2558 2558 link_state_t state)
2559 2559 {
2560 2560 mac_link_update(qede->mac_handle, state);
2561 2561 }
2562 2562
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