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--- old/usr/src/uts/i86pc/io/mp_platform_common.c
+++ new/usr/src/uts/i86pc/io/mp_platform_common.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
|
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14 lines elided |
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15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 * Copyright 2016 Nexenta Systems, Inc.
24 24 * Copyright (c) 2017 by Delphix. All rights reserved.
25 - * Copyright (c) 2018, Joyent, Inc.
25 + * Copyright (c) 2019, Joyent, Inc.
26 26 */
27 27 /*
28 28 * Copyright (c) 2010, Intel Corporation.
29 29 * All rights reserved.
30 30 */
31 31
32 32 /*
33 33 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
34 34 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
35 35 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
36 36 * PSMI 1.5 extensions are supported in Solaris Nevada.
37 37 * PSMI 1.6 extensions are supported in Solaris Nevada.
38 38 * PSMI 1.7 extensions are supported in Solaris Nevada.
39 39 */
40 40 #define PSMI_1_7
41 41
42 42 #include <sys/processor.h>
43 43 #include <sys/time.h>
44 44 #include <sys/psm.h>
45 45 #include <sys/smp_impldefs.h>
46 46 #include <sys/cram.h>
47 47 #include <sys/acpi/acpi.h>
48 48 #include <sys/acpica.h>
49 49 #include <sys/psm_common.h>
50 50 #include <sys/apic.h>
51 51 #include <sys/apic_timer.h>
52 52 #include <sys/pit.h>
53 53 #include <sys/ddi.h>
54 54 #include <sys/sunddi.h>
55 55 #include <sys/ddi_impldefs.h>
56 56 #include <sys/pci.h>
57 57 #include <sys/promif.h>
58 58 #include <sys/x86_archext.h>
59 59 #include <sys/cpc_impl.h>
60 60 #include <sys/uadmin.h>
61 61 #include <sys/panic.h>
62 62 #include <sys/debug.h>
63 63 #include <sys/archsystm.h>
64 64 #include <sys/trap.h>
65 65 #include <sys/machsystm.h>
66 66 #include <sys/cpuvar.h>
67 67 #include <sys/rm_platter.h>
68 68 #include <sys/privregs.h>
69 69 #include <sys/cyclic.h>
70 70 #include <sys/note.h>
71 71 #include <sys/pci_intr_lib.h>
72 72 #include <sys/sunndi.h>
73 73 #if !defined(__xpv)
74 74 #include <sys/hpet.h>
75 75 #include <sys/clock.h>
76 76 #endif
77 77
78 78 /*
79 79 * Local Function Prototypes
80 80 */
81 81 static int apic_handle_defconf();
82 82 static int apic_parse_mpct(caddr_t mpct, int bypass);
83 83 static struct apic_mpfps_hdr *apic_find_fps_sig(caddr_t fptr, int size);
84 84 static int apic_checksum(caddr_t bptr, int len);
85 85 static int apic_find_bus_type(char *bus);
86 86 static int apic_find_bus(int busid);
87 87 static struct apic_io_intr *apic_find_io_intr(int irqno);
88 88 static int apic_find_free_irq(int start, int end);
89 89 struct apic_io_intr *apic_find_io_intr_w_busid(int irqno, int busid);
90 90 static void apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp);
91 91 static void apic_free_apic_cpus(void);
92 92 static boolean_t apic_is_ioapic_AMD_813x(uint32_t physaddr);
93 93 static int apic_acpi_enter_apicmode(void);
94 94
95 95 int apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno,
96 96 int child_ipin, struct apic_io_intr **intrp);
97 97 int apic_find_bus_id(int bustype);
98 98 int apic_find_intin(uchar_t ioapic, uchar_t intin);
99 99 void apic_record_rdt_entry(apic_irq_t *irqptr, int irq);
100 100
101 101 int apic_debug_mps_id = 0; /* 1 - print MPS ID strings */
102 102
103 103 /* ACPI SCI interrupt configuration; -1 if SCI not used */
104 104 int apic_sci_vect = -1;
105 105 iflag_t apic_sci_flags;
106 106
107 107 #if !defined(__xpv)
108 108 /* ACPI HPET interrupt configuration; -1 if HPET not used */
109 109 int apic_hpet_vect = -1;
110 110 iflag_t apic_hpet_flags;
111 111 #endif
112 112
113 113 /*
114 114 * psm name pointer
115 115 */
116 116 char *psm_name;
117 117
118 118 /* ACPI support routines */
119 119 static int acpi_probe(char *);
120 120 static int apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip,
121 121 int *pci_irqp, iflag_t *intr_flagp);
122 122
123 123 int apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid,
124 124 int ipin, int *pci_irqp, iflag_t *intr_flagp);
125 125 uchar_t acpi_find_ioapic(int irq);
126 126 static int acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2);
127 127
128 128 /* Max wait time (in repetitions) for flags to clear in an RDT entry. */
129 129 int apic_max_reps_clear_pending = 1000;
130 130
131 131 int apic_intr_policy = INTR_ROUND_ROBIN;
132 132
133 133 int apic_next_bind_cpu = 1; /* For round robin assignment */
134 134 /* start with cpu 1 */
135 135
136 136 /*
137 137 * If enabled, the distribution works as follows:
138 138 * On every interrupt entry, the current ipl for the CPU is set in cpu_info
139 139 * and the irq corresponding to the ipl is also set in the aci_current array.
140 140 * interrupt exit and setspl (due to soft interrupts) will cause the current
141 141 * ipl to be be changed. This is cache friendly as these frequently used
142 142 * paths write into a per cpu structure.
143 143 *
144 144 * Sampling is done by checking the structures for all CPUs and incrementing
145 145 * the busy field of the irq (if any) executing on each CPU and the busy field
146 146 * of the corresponding CPU.
147 147 * In periodic mode this is done on every clock interrupt.
148 148 * In one-shot mode, this is done thru a cyclic with an interval of
149 149 * apic_redistribute_sample_interval (default 10 milli sec).
150 150 *
151 151 * Every apic_sample_factor_redistribution times we sample, we do computations
152 152 * to decide which interrupt needs to be migrated (see comments
153 153 * before apic_intr_redistribute().
154 154 */
155 155
156 156 /*
157 157 * Following 3 variables start as % and can be patched or set using an
158 158 * API to be defined in future. They will be scaled to
159 159 * sample_factor_redistribution which is in turn set to hertz+1 (in periodic
160 160 * mode), or 101 in one-shot mode to stagger it away from one sec processing
161 161 */
162 162
163 163 int apic_int_busy_mark = 60;
164 164 int apic_int_free_mark = 20;
165 165 int apic_diff_for_redistribution = 10;
166 166
167 167 /* sampling interval for interrupt redistribution for dynamic migration */
168 168 int apic_redistribute_sample_interval = NANOSEC / 100; /* 10 millisec */
169 169
170 170 /*
171 171 * number of times we sample before deciding to redistribute interrupts
172 172 * for dynamic migration
173 173 */
174 174 int apic_sample_factor_redistribution = 101;
175 175
176 176 int apic_redist_cpu_skip = 0;
177 177 int apic_num_imbalance = 0;
178 178 int apic_num_rebind = 0;
179 179
180 180 /*
181 181 * Maximum number of APIC CPUs in the system, -1 indicates that dynamic
182 182 * allocation of CPU ids is disabled.
183 183 */
184 184 int apic_max_nproc = -1;
185 185 int apic_nproc = 0;
186 186 size_t apic_cpus_size = 0;
187 187 int apic_defconf = 0;
188 188 int apic_irq_translate = 0;
189 189 int apic_spec_rev = 0;
190 190 int apic_imcrp = 0;
191 191
192 192 int apic_use_acpi = 1; /* 1 = use ACPI, 0 = don't use ACPI */
193 193 int apic_use_acpi_madt_only = 0; /* 1=ONLY use MADT from ACPI */
194 194
195 195 /*
196 196 * For interrupt link devices, if apic_unconditional_srs is set, an irq resource
197 197 * will be assigned (via _SRS). If it is not set, use the current
198 198 * irq setting (via _CRS), but only if that irq is in the set of possible
199 199 * irqs (returned by _PRS) for the device.
200 200 */
201 201 int apic_unconditional_srs = 1;
202 202
203 203 /*
204 204 * For interrupt link devices, if apic_prefer_crs is set when we are
205 205 * assigning an IRQ resource to a device, prefer the current IRQ setting
206 206 * over other possible irq settings under same conditions.
207 207 */
208 208
209 209 int apic_prefer_crs = 1;
210 210
211 211 uchar_t apic_io_id[MAX_IO_APIC];
212 212 volatile uint32_t *apicioadr[MAX_IO_APIC];
213 213 uchar_t apic_io_ver[MAX_IO_APIC];
214 214 uchar_t apic_io_vectbase[MAX_IO_APIC];
215 215 uchar_t apic_io_vectend[MAX_IO_APIC];
216 216 uchar_t apic_reserved_irqlist[MAX_ISA_IRQ + 1];
217 217 uint32_t apic_physaddr[MAX_IO_APIC];
218 218
219 219 boolean_t ioapic_mask_workaround[MAX_IO_APIC];
220 220
221 221 /*
222 222 * First available slot to be used as IRQ index into the apic_irq_table
223 223 * for those interrupts (like MSI/X) that don't have a physical IRQ.
224 224 */
225 225 int apic_first_avail_irq = APIC_FIRST_FREE_IRQ;
226 226
227 227 /*
228 228 * apic_ioapic_lock protects the ioapics (reg select), the status, temp_bound
229 229 * and bound elements of cpus_info and the temp_cpu element of irq_struct
230 230 */
231 231 lock_t apic_ioapic_lock;
232 232
233 233 int apic_io_max = 0; /* no. of i/o apics enabled */
234 234
235 235 struct apic_io_intr *apic_io_intrp = NULL;
236 236 static struct apic_bus *apic_busp;
237 237
238 238 uchar_t apic_resv_vector[MAXIPL+1];
239 239
240 240 char apic_level_intr[APIC_MAX_VECTOR+1];
241 241
242 242 uint32_t eisa_level_intr_mask = 0;
243 243 /* At least MSB will be set if EISA bus */
244 244
245 245 int apic_pci_bus_total = 0;
246 246 uchar_t apic_single_pci_busid = 0;
247 247
248 248 /*
249 249 * airq_mutex protects additions to the apic_irq_table - the first
250 250 * pointer and any airq_nexts off of that one. It also protects
251 251 * apic_max_device_irq & apic_min_device_irq. It also guarantees
252 252 * that share_id is unique as new ids are generated only when new
253 253 * irq_t structs are linked in. Once linked in the structs are never
254 254 * deleted. temp_cpu & mps_intr_index field indicate if it is programmed
255 255 * or allocated. Note that there is a slight gap between allocating in
256 256 * apic_introp_xlate and programming in addspl.
257 257 */
258 258 kmutex_t airq_mutex;
259 259 apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1];
260 260 int apic_max_device_irq = 0;
261 261 int apic_min_device_irq = APIC_MAX_VECTOR;
262 262
263 263 typedef struct prs_irq_list_ent {
264 264 int list_prio;
265 265 int32_t irq;
266 266 iflag_t intrflags;
267 267 acpi_prs_private_t prsprv;
268 268 struct prs_irq_list_ent *next;
269 269 } prs_irq_list_t;
270 270
271 271
272 272 /*
273 273 * ACPI variables
274 274 */
275 275 /* 1 = acpi is enabled & working, 0 = acpi is not enabled or not there */
276 276 int apic_enable_acpi = 0;
277 277
278 278 /* ACPI Multiple APIC Description Table ptr */
279 279 static ACPI_TABLE_MADT *acpi_mapic_dtp = NULL;
280 280
281 281 /* ACPI Interrupt Source Override Structure ptr */
282 282 ACPI_MADT_INTERRUPT_OVERRIDE *acpi_isop = NULL;
283 283 int acpi_iso_cnt = 0;
284 284
285 285 /* ACPI Non-maskable Interrupt Sources ptr */
286 286 static ACPI_MADT_NMI_SOURCE *acpi_nmi_sp = NULL;
287 287 static int acpi_nmi_scnt = 0;
288 288 static ACPI_MADT_LOCAL_APIC_NMI *acpi_nmi_cp = NULL;
289 289 static int acpi_nmi_ccnt = 0;
290 290
291 291 static boolean_t acpi_found_smp_config = B_FALSE;
292 292
293 293 /*
294 294 * The following added to identify a software poweroff method if available.
295 295 */
296 296
297 297 static struct {
298 298 int poweroff_method;
299 299 char oem_id[APIC_MPS_OEM_ID_LEN + 1]; /* MAX + 1 for NULL */
300 300 char prod_id[APIC_MPS_PROD_ID_LEN + 1]; /* MAX + 1 for NULL */
301 301 } apic_mps_ids[] = {
302 302 { APIC_POWEROFF_VIA_RTC, "INTEL", "ALDER" }, /* 4300 */
303 303 { APIC_POWEROFF_VIA_RTC, "NCR", "AMC" }, /* 4300 */
304 304 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "A450NX" }, /* 4400? */
305 305 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AD450NX" }, /* 4400 */
306 306 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AC450NX" }, /* 4400R */
307 307 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "S450NX" }, /* S50 */
308 308 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "SC450NX" } /* S50? */
309 309 };
310 310
311 311 int apic_poweroff_method = APIC_POWEROFF_NONE;
312 312
313 313 /*
314 314 * Auto-configuration routines
315 315 */
316 316
317 317 /*
318 318 * Look at MPSpec 1.4 (Intel Order # 242016-005) for details of what we do here
319 319 * May work with 1.1 - but not guaranteed.
320 320 * According to the MP Spec, the MP floating pointer structure
321 321 * will be searched in the order described below:
322 322 * 1. In the first kilobyte of Extended BIOS Data Area (EBDA)
323 323 * 2. Within the last kilobyte of system base memory
324 324 * 3. In the BIOS ROM address space between 0F0000h and 0FFFFh
325 325 * Once we find the right signature with proper checksum, we call
326 326 * either handle_defconf or parse_mpct to get all info necessary for
327 327 * subsequent operations.
328 328 */
329 329 int
330 330 apic_probe_common(char *modname)
331 331 {
332 332 uint32_t mpct_addr, ebda_start = 0, base_mem_end;
333 333 caddr_t biosdatap;
334 334 caddr_t mpct = NULL;
335 335 caddr_t fptr;
336 336 int i, mpct_size = 0, mapsize, retval = PSM_FAILURE;
337 337 ushort_t ebda_seg, base_mem_size;
338 338 struct apic_mpfps_hdr *fpsp;
339 339 struct apic_mp_cnf_hdr *hdrp;
340 340 int bypass_cpu_and_ioapics_in_mptables;
341 341 int acpi_user_options;
342 342
343 343 if (apic_forceload < 0)
344 344 return (retval);
345 345
346 346 /*
347 347 * Remember who we are
348 348 */
349 349 psm_name = modname;
350 350
351 351 /* Allow override for MADT-only mode */
352 352 acpi_user_options = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_root_node(), 0,
353 353 "acpi-user-options", 0);
354 354 apic_use_acpi_madt_only = ((acpi_user_options & ACPI_OUSER_MADT) != 0);
355 355
356 356 /* Allow apic_use_acpi to override MADT-only mode */
357 357 if (!apic_use_acpi)
358 358 apic_use_acpi_madt_only = 0;
359 359
360 360 retval = acpi_probe(modname);
361 361
362 362 /* in UEFI system, there is no BIOS data */
363 363 if (ddi_prop_exists(DDI_DEV_T_ANY, ddi_root_node(), 0, "efi-systab"))
364 364 goto apic_ret;
365 365
366 366 /*
367 367 * mapin the bios data area 40:0
368 368 * 40:13h - two-byte location reports the base memory size
369 369 * 40:0Eh - two-byte location for the exact starting address of
370 370 * the EBDA segment for EISA
371 371 */
372 372 biosdatap = psm_map_phys(0x400, 0x20, PROT_READ);
373 373 if (!biosdatap)
374 374 goto apic_ret;
375 375 fpsp = (struct apic_mpfps_hdr *)NULL;
376 376 mapsize = MPFPS_RAM_WIN_LEN;
377 377 /*LINTED: pointer cast may result in improper alignment */
378 378 ebda_seg = *((ushort_t *)(biosdatap+0xe));
379 379 /* check the 1k of EBDA */
380 380 if (ebda_seg) {
381 381 ebda_start = ((uint32_t)ebda_seg) << 4;
382 382 fptr = psm_map_phys(ebda_start, MPFPS_RAM_WIN_LEN, PROT_READ);
383 383 if (fptr) {
384 384 if (!(fpsp =
385 385 apic_find_fps_sig(fptr, MPFPS_RAM_WIN_LEN)))
386 386 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN);
387 387 }
388 388 }
389 389 /* If not in EBDA, check the last k of system base memory */
390 390 if (!fpsp) {
391 391 /*LINTED: pointer cast may result in improper alignment */
392 392 base_mem_size = *((ushort_t *)(biosdatap + 0x13));
393 393
394 394 if (base_mem_size > 512)
395 395 base_mem_end = 639 * 1024;
396 396 else
397 397 base_mem_end = 511 * 1024;
398 398 /* if ebda == last k of base mem, skip to check BIOS ROM */
399 399 if (base_mem_end != ebda_start) {
400 400
401 401 fptr = psm_map_phys(base_mem_end, MPFPS_RAM_WIN_LEN,
402 402 PROT_READ);
403 403
404 404 if (fptr) {
405 405 if (!(fpsp = apic_find_fps_sig(fptr,
406 406 MPFPS_RAM_WIN_LEN)))
407 407 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN);
408 408 }
409 409 }
410 410 }
411 411 psm_unmap_phys(biosdatap, 0x20);
412 412
413 413 /* If still cannot find it, check the BIOS ROM space */
414 414 if (!fpsp) {
415 415 mapsize = MPFPS_ROM_WIN_LEN;
416 416 fptr = psm_map_phys(MPFPS_ROM_WIN_START,
417 417 MPFPS_ROM_WIN_LEN, PROT_READ);
418 418 if (fptr) {
419 419 if (!(fpsp =
420 420 apic_find_fps_sig(fptr, MPFPS_ROM_WIN_LEN))) {
421 421 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
422 422 goto apic_ret;
423 423 }
424 424 }
425 425 }
426 426
427 427 if (apic_checksum((caddr_t)fpsp, fpsp->mpfps_length * 16) != 0) {
428 428 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
429 429 goto apic_ret;
430 430 }
431 431
432 432 apic_spec_rev = fpsp->mpfps_spec_rev;
433 433 if ((apic_spec_rev != 04) && (apic_spec_rev != 01)) {
434 434 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
435 435 goto apic_ret;
436 436 }
437 437
438 438 /* check IMCR is present or not */
439 439 apic_imcrp = fpsp->mpfps_featinfo2 & MPFPS_FEATINFO2_IMCRP;
440 440
441 441 /* check default configuration (dual CPUs) */
442 442 if ((apic_defconf = fpsp->mpfps_featinfo1) != 0) {
443 443 psm_unmap_phys(fptr, mapsize);
444 444 if ((retval = apic_handle_defconf()) != PSM_SUCCESS)
445 445 return (retval);
446 446
447 447 goto apic_ret;
448 448 }
449 449
450 450 /* MP Configuration Table */
451 451 mpct_addr = (uint32_t)(fpsp->mpfps_mpct_paddr);
452 452
453 453 psm_unmap_phys(fptr, mapsize); /* unmap floating ptr struct */
454 454
455 455 /*
456 456 * Map in enough memory for the MP Configuration Table Header.
457 457 * Use this table to read the total length of the BIOS data and
458 458 * map in all the info
459 459 */
460 460 /*LINTED: pointer cast may result in improper alignment */
461 461 hdrp = (struct apic_mp_cnf_hdr *)psm_map_phys(mpct_addr,
462 462 sizeof (struct apic_mp_cnf_hdr), PROT_READ);
463 463 if (!hdrp)
464 464 goto apic_ret;
465 465
466 466 /* check mp configuration table signature PCMP */
467 467 if (hdrp->mpcnf_sig != 0x504d4350) {
468 468 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr));
469 469 goto apic_ret;
470 470 }
471 471 mpct_size = (int)hdrp->mpcnf_tbl_length;
472 472
473 473 apic_set_pwroff_method_from_mpcnfhdr(hdrp);
474 474
475 475 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr));
476 476
477 477 if ((retval == PSM_SUCCESS) && !apic_use_acpi_madt_only) {
478 478 /* This is an ACPI machine No need for further checks */
479 479 goto apic_ret;
480 480 }
481 481
482 482 /*
483 483 * Map in the entries for this machine, ie. Processor
484 484 * Entry Tables, Bus Entry Tables, etc.
485 485 * They are in fixed order following one another
486 486 */
487 487 mpct = psm_map_phys(mpct_addr, mpct_size, PROT_READ);
488 488 if (!mpct)
489 489 goto apic_ret;
490 490
491 491 if (apic_checksum(mpct, mpct_size) != 0)
492 492 goto apic_fail1;
493 493
494 494 /*LINTED: pointer cast may result in improper alignment */
495 495 hdrp = (struct apic_mp_cnf_hdr *)mpct;
496 496 apicadr = (uint32_t *)mapin_apic((uint32_t)hdrp->mpcnf_local_apic,
497 497 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE);
498 498 if (!apicadr)
499 499 goto apic_fail1;
500 500
501 501 /* Parse all information in the tables */
502 502 bypass_cpu_and_ioapics_in_mptables = (retval == PSM_SUCCESS);
503 503 if (apic_parse_mpct(mpct, bypass_cpu_and_ioapics_in_mptables) ==
504 504 PSM_SUCCESS) {
505 505 retval = PSM_SUCCESS;
506 506 goto apic_ret;
507 507 }
508 508
509 509 apic_fail1:
510 510 psm_unmap_phys(mpct, mpct_size);
511 511 mpct = NULL;
512 512
513 513 apic_ret:
514 514 if (retval == PSM_SUCCESS) {
515 515 extern int apic_ioapic_method_probe();
516 516
517 517 if ((retval = apic_ioapic_method_probe()) == PSM_SUCCESS)
518 518 return (PSM_SUCCESS);
519 519 }
520 520
521 521 for (i = 0; i < apic_io_max; i++)
522 522 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN);
523 523 if (apic_cpus) {
524 524 kmem_free(apic_cpus, apic_cpus_size);
525 525 apic_cpus = NULL;
526 526 }
527 527 if (apicadr) {
528 528 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
529 529 apicadr = NULL;
530 530 }
531 531 if (mpct)
532 532 psm_unmap_phys(mpct, mpct_size);
533 533
534 534 return (retval);
535 535 }
536 536
537 537 static void
538 538 apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp)
539 539 {
540 540 int i;
541 541
542 542 for (i = 0; i < (sizeof (apic_mps_ids) / sizeof (apic_mps_ids[0]));
543 543 i++) {
544 544 if ((strncmp(hdrp->mpcnf_oem_str, apic_mps_ids[i].oem_id,
545 545 strlen(apic_mps_ids[i].oem_id)) == 0) &&
546 546 (strncmp(hdrp->mpcnf_prod_str, apic_mps_ids[i].prod_id,
547 547 strlen(apic_mps_ids[i].prod_id)) == 0)) {
548 548
549 549 apic_poweroff_method = apic_mps_ids[i].poweroff_method;
550 550 break;
551 551 }
552 552 }
553 553
554 554 if (apic_debug_mps_id != 0) {
555 555 cmn_err(CE_CONT, "%s: MPS OEM ID = '%c%c%c%c%c%c%c%c'"
556 556 "Product ID = '%c%c%c%c%c%c%c%c%c%c%c%c'\n",
557 557 psm_name,
558 558 hdrp->mpcnf_oem_str[0],
559 559 hdrp->mpcnf_oem_str[1],
560 560 hdrp->mpcnf_oem_str[2],
561 561 hdrp->mpcnf_oem_str[3],
562 562 hdrp->mpcnf_oem_str[4],
563 563 hdrp->mpcnf_oem_str[5],
564 564 hdrp->mpcnf_oem_str[6],
565 565 hdrp->mpcnf_oem_str[7],
566 566 hdrp->mpcnf_prod_str[0],
567 567 hdrp->mpcnf_prod_str[1],
568 568 hdrp->mpcnf_prod_str[2],
569 569 hdrp->mpcnf_prod_str[3],
570 570 hdrp->mpcnf_prod_str[4],
571 571 hdrp->mpcnf_prod_str[5],
572 572 hdrp->mpcnf_prod_str[6],
573 573 hdrp->mpcnf_prod_str[7],
574 574 hdrp->mpcnf_prod_str[8],
575 575 hdrp->mpcnf_prod_str[9],
576 576 hdrp->mpcnf_prod_str[10],
577 577 hdrp->mpcnf_prod_str[11]);
578 578 }
579 579 }
580 580
581 581 static void
582 582 apic_free_apic_cpus(void)
583 583 {
584 584 if (apic_cpus != NULL) {
585 585 kmem_free(apic_cpus, apic_cpus_size);
586 586 apic_cpus = NULL;
587 587 apic_cpus_size = 0;
588 588 }
589 589 }
590 590
591 591 static int
592 592 acpi_probe(char *modname)
593 593 {
594 594 int i, intmax, index;
595 595 uint32_t id, ver;
596 596 int acpi_verboseflags = 0;
597 597 int madt_seen, madt_size;
598 598 ACPI_SUBTABLE_HEADER *ap;
599 599 ACPI_MADT_LOCAL_APIC *mpa;
600 600 ACPI_MADT_LOCAL_X2APIC *mpx2a;
601 601 ACPI_MADT_IO_APIC *mia;
602 602 ACPI_MADT_IO_SAPIC *misa;
603 603 ACPI_MADT_INTERRUPT_OVERRIDE *mio;
604 604 ACPI_MADT_NMI_SOURCE *mns;
605 605 ACPI_MADT_INTERRUPT_SOURCE *mis;
606 606 ACPI_MADT_LOCAL_APIC_NMI *mlan;
607 607 ACPI_MADT_LOCAL_X2APIC_NMI *mx2alan;
608 608 ACPI_MADT_LOCAL_APIC_OVERRIDE *mao;
609 609 int sci;
610 610 iflag_t sci_flags;
611 611 volatile uint32_t *ioapic;
612 612 int ioapic_ix;
613 613 uint32_t *local_ids;
614 614 uint32_t *proc_ids;
615 615 uchar_t hid;
616 616 int warned = 0;
617 617
618 618 if (!apic_use_acpi)
619 619 return (PSM_FAILURE);
620 620
621 621 if (AcpiGetTable(ACPI_SIG_MADT, 1,
622 622 (ACPI_TABLE_HEADER **) &acpi_mapic_dtp) != AE_OK) {
623 623 cmn_err(CE_WARN, "!acpi_probe: No MADT found!");
624 624 return (PSM_FAILURE);
625 625 }
626 626
627 627 apicadr = mapin_apic((uint32_t)acpi_mapic_dtp->Address,
628 628 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE);
629 629 if (!apicadr)
630 630 return (PSM_FAILURE);
631 631
632 632 if ((local_ids = (uint32_t *)kmem_zalloc(NCPU * sizeof (uint32_t),
633 633 KM_NOSLEEP)) == NULL)
634 634 return (PSM_FAILURE);
635 635
636 636 if ((proc_ids = (uint32_t *)kmem_zalloc(NCPU * sizeof (uint32_t),
637 637 KM_NOSLEEP)) == NULL) {
638 638 kmem_free(local_ids, NCPU * sizeof (uint32_t));
639 639 return (PSM_FAILURE);
640 640 }
641 641
642 642 id = apic_reg_ops->apic_read(APIC_LID_REG);
643 643 local_ids[0] = (uchar_t)(id >> 24);
644 644 apic_nproc = index = 1;
645 645 apic_io_max = 0;
646 646
647 647 ap = (ACPI_SUBTABLE_HEADER *) (acpi_mapic_dtp + 1);
648 648 madt_size = acpi_mapic_dtp->Header.Length;
649 649 madt_seen = sizeof (*acpi_mapic_dtp);
650 650
651 651 while (madt_seen < madt_size) {
652 652 switch (ap->Type) {
653 653 case ACPI_MADT_TYPE_LOCAL_APIC:
654 654 mpa = (ACPI_MADT_LOCAL_APIC *) ap;
655 655 if (mpa->LapicFlags & ACPI_MADT_ENABLED) {
656 656 if (mpa->Id == 255) {
657 657 cmn_err(CE_WARN, "!%s: encountered "
658 658 "invalid entry in MADT: CPU %d "
659 659 "has Local APIC Id equal to 255 ",
660 660 psm_name, mpa->ProcessorId);
661 661 }
662 662 if (mpa->Id == local_ids[0]) {
663 663 ASSERT(index == 1);
664 664 proc_ids[0] = mpa->ProcessorId;
665 665 } else if (apic_nproc < NCPU && use_mp &&
666 666 apic_nproc < boot_ncpus) {
667 667 local_ids[index] = mpa->Id;
668 668 proc_ids[index] = mpa->ProcessorId;
669 669 index++;
670 670 apic_nproc++;
671 671 } else if (apic_nproc == NCPU && !warned) {
672 672 cmn_err(CE_WARN, "%s: CPU limit "
673 673 "exceeded"
674 674 #if !defined(__amd64)
675 675 " for 32-bit mode"
676 676 #endif
677 677 "; Solaris will use %d CPUs.",
678 678 psm_name, NCPU);
679 679 warned = 1;
680 680 }
681 681 }
682 682 break;
683 683
684 684 case ACPI_MADT_TYPE_IO_APIC:
685 685 mia = (ACPI_MADT_IO_APIC *) ap;
686 686 if (apic_io_max < MAX_IO_APIC) {
687 687 ioapic_ix = apic_io_max;
688 688 apic_io_id[apic_io_max] = mia->Id;
689 689 apic_io_vectbase[apic_io_max] =
690 690 mia->GlobalIrqBase;
691 691 apic_physaddr[apic_io_max] =
692 692 (uint32_t)mia->Address;
693 693 ioapic = apicioadr[apic_io_max] =
694 694 mapin_ioapic((uint32_t)mia->Address,
695 695 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
696 696 if (!ioapic)
697 697 goto cleanup;
698 698 ioapic_mask_workaround[apic_io_max] =
699 699 apic_is_ioapic_AMD_813x(mia->Address);
700 700 apic_io_max++;
701 701 }
702 702 break;
703 703
704 704 case ACPI_MADT_TYPE_INTERRUPT_OVERRIDE:
705 705 mio = (ACPI_MADT_INTERRUPT_OVERRIDE *) ap;
706 706 if (acpi_isop == NULL)
707 707 acpi_isop = mio;
708 708 acpi_iso_cnt++;
709 709 break;
710 710
711 711 case ACPI_MADT_TYPE_NMI_SOURCE:
712 712 /* UNIMPLEMENTED */
713 713 mns = (ACPI_MADT_NMI_SOURCE *) ap;
714 714 if (acpi_nmi_sp == NULL)
715 715 acpi_nmi_sp = mns;
716 716 acpi_nmi_scnt++;
717 717
718 718 cmn_err(CE_NOTE, "!apic: nmi source: %d 0x%x\n",
719 719 mns->GlobalIrq, mns->IntiFlags);
720 720 break;
721 721
722 722 case ACPI_MADT_TYPE_LOCAL_APIC_NMI:
723 723 /* UNIMPLEMENTED */
724 724 mlan = (ACPI_MADT_LOCAL_APIC_NMI *) ap;
725 725 if (acpi_nmi_cp == NULL)
726 726 acpi_nmi_cp = mlan;
727 727 acpi_nmi_ccnt++;
728 728
729 729 cmn_err(CE_NOTE, "!apic: local nmi: %d 0x%x %d\n",
730 730 mlan->ProcessorId, mlan->IntiFlags,
731 731 mlan->Lint);
732 732 break;
733 733
734 734 case ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE:
735 735 /* UNIMPLEMENTED */
736 736 mao = (ACPI_MADT_LOCAL_APIC_OVERRIDE *) ap;
737 737 cmn_err(CE_NOTE, "!apic: address override: %lx\n",
738 738 (long)mao->Address);
739 739 break;
740 740
741 741 case ACPI_MADT_TYPE_IO_SAPIC:
742 742 /* UNIMPLEMENTED */
743 743 misa = (ACPI_MADT_IO_SAPIC *) ap;
744 744
745 745 cmn_err(CE_NOTE, "!apic: io sapic: %d %d %lx\n",
746 746 misa->Id, misa->GlobalIrqBase,
747 747 (long)misa->Address);
748 748 break;
749 749
750 750 case ACPI_MADT_TYPE_INTERRUPT_SOURCE:
751 751 /* UNIMPLEMENTED */
752 752 mis = (ACPI_MADT_INTERRUPT_SOURCE *) ap;
753 753
754 754 cmn_err(CE_NOTE,
755 755 "!apic: irq source: %d %d %d 0x%x %d %d\n",
756 756 mis->Id, mis->Eid, mis->GlobalIrq,
757 757 mis->IntiFlags, mis->Type,
758 758 mis->IoSapicVector);
759 759 break;
760 760
761 761 case ACPI_MADT_TYPE_LOCAL_X2APIC:
762 762 mpx2a = (ACPI_MADT_LOCAL_X2APIC *) ap;
763 763
764 764 if (mpx2a->LapicFlags & ACPI_MADT_ENABLED) {
765 765 if (mpx2a->LocalApicId == local_ids[0]) {
766 766 ASSERT(index == 1);
767 767 proc_ids[0] = mpx2a->Uid;
768 768 } else if (apic_nproc < NCPU && use_mp &&
769 769 apic_nproc < boot_ncpus) {
770 770 local_ids[index] = mpx2a->LocalApicId;
771 771 proc_ids[index] = mpx2a->Uid;
772 772 index++;
773 773 apic_nproc++;
774 774 } else if (apic_nproc == NCPU && !warned) {
775 775 cmn_err(CE_WARN, "%s: CPU limit "
776 776 "exceeded"
777 777 #if !defined(__amd64)
778 778 " for 32-bit mode"
779 779 #endif
780 780 "; Solaris will use %d CPUs.",
781 781 psm_name, NCPU);
782 782 warned = 1;
783 783 }
784 784 }
785 785
786 786 break;
787 787
788 788 case ACPI_MADT_TYPE_LOCAL_X2APIC_NMI:
789 789 /* UNIMPLEMENTED */
790 790 mx2alan = (ACPI_MADT_LOCAL_X2APIC_NMI *) ap;
791 791 if (mx2alan->Uid >> 8)
792 792 acpi_nmi_ccnt++;
793 793
794 794 #ifdef DEBUG
795 795 cmn_err(CE_NOTE,
796 796 "!apic: local x2apic nmi: %d 0x%x %d\n",
797 797 mx2alan->Uid, mx2alan->IntiFlags, mx2alan->Lint);
798 798 #endif
799 799
800 800 break;
801 801
802 802 case ACPI_MADT_TYPE_RESERVED:
803 803 default:
804 804 break;
805 805 }
806 806
807 807 /* advance to next entry */
808 808 madt_seen += ap->Length;
809 809 ap = (ACPI_SUBTABLE_HEADER *)(((char *)ap) + ap->Length);
810 810 }
811 811
812 812 /* We found multiple enabled cpus via MADT */
813 813 if ((apic_nproc > 1) && (apic_io_max > 0)) {
814 814 acpi_found_smp_config = B_TRUE;
815 815 cmn_err(CE_NOTE,
816 816 "!apic: Using ACPI (MADT) for SMP configuration");
817 817 }
818 818
819 819 /*
820 820 * allocate enough space for possible hot-adding of CPUs.
821 821 * max_ncpus may be less than apic_nproc if it's set by user.
822 822 */
823 823 if (plat_dr_support_cpu()) {
824 824 apic_max_nproc = max_ncpus;
825 825 }
826 826 apic_cpus_size = max(apic_nproc, max_ncpus) * sizeof (*apic_cpus);
827 827 if ((apic_cpus = kmem_zalloc(apic_cpus_size, KM_NOSLEEP)) == NULL)
828 828 goto cleanup;
829 829
830 830 /*
831 831 * ACPI doesn't provide the local apic ver, get it directly from the
832 832 * local apic
833 833 */
834 834 ver = apic_reg_ops->apic_read(APIC_VERS_REG);
835 835 for (i = 0; i < apic_nproc; i++) {
836 836 apic_cpus[i].aci_local_id = local_ids[i];
837 837 apic_cpus[i].aci_local_ver = (uchar_t)(ver & 0xFF);
838 838 apic_cpus[i].aci_processor_id = proc_ids[i];
839 839 /* Only build mapping info for CPUs present at boot. */
840 840 if (i < boot_ncpus)
841 841 (void) acpica_map_cpu(i, proc_ids[i]);
842 842 }
843 843
844 844 /*
845 845 * To support CPU dynamic reconfiguration, the apic CPU info structure
846 846 * for each possible CPU will be pre-allocated at boot time.
847 847 * The state for each apic CPU info structure will be assigned according
848 848 * to the following rules:
849 849 * Rule 1:
850 850 * Slot index range: [0, min(apic_nproc, boot_ncpus))
851 851 * State flags: 0
852 852 * Note: cpu exists and will be configured/enabled at boot time
853 853 * Rule 2:
854 854 * Slot index range: [boot_ncpus, apic_nproc)
855 855 * State flags: APIC_CPU_FREE | APIC_CPU_DIRTY
856 856 * Note: cpu exists but won't be configured/enabled at boot time
857 857 * Rule 3:
858 858 * Slot index range: [apic_nproc, boot_ncpus)
859 859 * State flags: APIC_CPU_FREE
860 860 * Note: cpu doesn't exist at boot time
861 861 * Rule 4:
862 862 * Slot index range: [max(apic_nproc, boot_ncpus), max_ncpus)
863 863 * State flags: APIC_CPU_FREE
864 864 * Note: cpu doesn't exist at boot time
865 865 */
866 866 CPUSET_ZERO(apic_cpumask);
867 867 for (i = 0; i < min(boot_ncpus, apic_nproc); i++) {
868 868 CPUSET_ADD(apic_cpumask, i);
869 869 apic_cpus[i].aci_status = 0;
870 870 }
871 871 for (i = boot_ncpus; i < apic_nproc; i++) {
872 872 apic_cpus[i].aci_status = APIC_CPU_FREE | APIC_CPU_DIRTY;
873 873 }
874 874 for (i = apic_nproc; i < boot_ncpus; i++) {
875 875 apic_cpus[i].aci_status = APIC_CPU_FREE;
876 876 }
877 877 for (i = max(boot_ncpus, apic_nproc); i < max_ncpus; i++) {
878 878 apic_cpus[i].aci_status = APIC_CPU_FREE;
879 879 }
880 880
881 881 for (i = 0; i < apic_io_max; i++) {
882 882 ioapic_ix = i;
883 883
884 884 /*
885 885 * need to check Sitka on the following acpi problem
886 886 * On the Sitka, the ioapic's apic_id field isn't reporting
887 887 * the actual io apic id. We have reported this problem
888 888 * to Intel. Until they fix the problem, we will get the
889 889 * actual id directly from the ioapic.
890 890 */
891 891 id = ioapic_read(ioapic_ix, APIC_ID_CMD);
892 892 hid = (uchar_t)(id >> 24);
893 893
894 894 if (hid != apic_io_id[i]) {
895 895 if (apic_io_id[i] == 0)
896 896 apic_io_id[i] = hid;
897 897 else { /* set ioapic id to whatever reported by ACPI */
898 898 id = ((uint32_t)apic_io_id[i]) << 24;
899 899 ioapic_write(ioapic_ix, APIC_ID_CMD, id);
900 900 }
901 901 }
902 902 ver = ioapic_read(ioapic_ix, APIC_VERS_CMD);
903 903 apic_io_ver[i] = (uchar_t)(ver & 0xff);
904 904 intmax = (ver >> 16) & 0xff;
905 905 apic_io_vectend[i] = apic_io_vectbase[i] + intmax;
906 906 if (apic_first_avail_irq <= apic_io_vectend[i])
907 907 apic_first_avail_irq = apic_io_vectend[i] + 1;
908 908 }
909 909
910 910
911 911 /*
912 912 * Process SCI configuration here
913 913 * An error may be returned here if
914 914 * acpi-user-options specifies legacy mode
915 915 * (no SCI, no ACPI mode)
916 916 */
917 917 if (acpica_get_sci(&sci, &sci_flags) != AE_OK)
918 918 sci = -1;
919 919
920 920 /*
921 921 * Now call acpi_init() to generate namespaces
922 922 * If this fails, we don't attempt to use ACPI
923 923 * even if we were able to get a MADT above
924 924 */
925 925 if (acpica_init() != AE_OK) {
926 926 cmn_err(CE_WARN, "!apic: Failed to initialize acpica!");
927 927 goto cleanup;
928 928 }
929 929
930 930 /*
931 931 * Call acpica_build_processor_map() now that we have
932 932 * ACPI namesspace access
933 933 */
934 934 (void) acpica_build_processor_map();
935 935
936 936 /*
937 937 * Squirrel away the SCI and flags for later on
938 938 * in apic_picinit() when we're ready
939 939 */
940 940 apic_sci_vect = sci;
941 941 apic_sci_flags = sci_flags;
942 942
943 943 if (apic_verbose & APIC_VERBOSE_IRQ_FLAG)
944 944 acpi_verboseflags |= PSM_VERBOSE_IRQ_FLAG;
945 945
946 946 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG)
947 947 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_FLAG;
948 948
949 949 if (apic_verbose & APIC_VERBOSE_POWEROFF_PAUSE_FLAG)
950 950 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_PAUSE_FLAG;
951 951
952 952 if (acpi_psm_init(modname, acpi_verboseflags) == ACPI_PSM_FAILURE)
953 953 goto cleanup;
954 954
955 955 /* Enable ACPI APIC interrupt routing */
956 956 if (apic_acpi_enter_apicmode() != PSM_FAILURE) {
957 957 cmn_err(CE_NOTE, "!apic: Using APIC interrupt routing mode");
958 958 build_reserved_irqlist((uchar_t *)apic_reserved_irqlist);
959 959 apic_enable_acpi = 1;
960 960 if (apic_sci_vect > 0) {
961 961 acpica_set_core_feature(ACPI_FEATURE_SCI_EVENT);
962 962 }
963 963 if (apic_use_acpi_madt_only) {
964 964 cmn_err(CE_CONT,
965 965 "?Using ACPI for CPU/IOAPIC information ONLY\n");
966 966 }
967 967
968 968 #if !defined(__xpv)
969 969 /*
970 970 * probe ACPI for hpet information here which is used later
971 971 * in apic_picinit().
972 972 */
973 973 if (hpet_acpi_init(&apic_hpet_vect, &apic_hpet_flags) < 0) {
974 974 cmn_err(CE_NOTE, "!ACPI HPET table query failed\n");
975 975 }
976 976 #endif
977 977
978 978 kmem_free(local_ids, NCPU * sizeof (uint32_t));
979 979 kmem_free(proc_ids, NCPU * sizeof (uint32_t));
980 980 return (PSM_SUCCESS);
981 981 }
982 982 /* if setting APIC mode failed above, we fall through to cleanup */
983 983
984 984 cleanup:
985 985 cmn_err(CE_WARN, "!apic: Failed acpi_probe, SMP config was %s",
986 986 acpi_found_smp_config ? "found" : "not found");
987 987 apic_free_apic_cpus();
988 988 if (apicadr != NULL) {
989 989 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
990 990 apicadr = NULL;
991 991 }
992 992 apic_max_nproc = -1;
993 993 apic_nproc = 0;
994 994 for (i = 0; i < apic_io_max; i++) {
995 995 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN);
996 996 apicioadr[i] = NULL;
997 997 }
998 998 apic_io_max = 0;
999 999 acpi_isop = NULL;
1000 1000 acpi_iso_cnt = 0;
1001 1001 acpi_nmi_sp = NULL;
1002 1002 acpi_nmi_scnt = 0;
1003 1003 acpi_nmi_cp = NULL;
1004 1004 acpi_nmi_ccnt = 0;
1005 1005 acpi_found_smp_config = B_FALSE;
1006 1006 kmem_free(local_ids, NCPU * sizeof (uint32_t));
1007 1007 kmem_free(proc_ids, NCPU * sizeof (uint32_t));
1008 1008 return (PSM_FAILURE);
1009 1009 }
1010 1010
1011 1011 /*
1012 1012 * Handle default configuration. Fill in reqd global variables & tables
1013 1013 * Fill all details as MP table does not give any more info
1014 1014 */
1015 1015 static int
1016 1016 apic_handle_defconf()
1017 1017 {
1018 1018 uint_t lid;
1019 1019
1020 1020 /* Failed to probe ACPI MADT tables, disable CPU DR. */
1021 1021 apic_max_nproc = -1;
1022 1022 apic_free_apic_cpus();
1023 1023 plat_dr_disable_cpu();
1024 1024
1025 1025 apicioadr[0] = (void *)mapin_ioapic(APIC_IO_ADDR,
1026 1026 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
1027 1027 apicadr = (void *)psm_map_phys(APIC_LOCAL_ADDR,
1028 1028 APIC_LOCAL_MEMLEN, PROT_READ);
1029 1029 apic_cpus_size = 2 * sizeof (*apic_cpus);
1030 1030 apic_cpus = (apic_cpus_info_t *)
1031 1031 kmem_zalloc(apic_cpus_size, KM_NOSLEEP);
1032 1032 if ((!apicadr) || (!apicioadr[0]) || (!apic_cpus))
1033 1033 goto apic_handle_defconf_fail;
1034 1034 CPUSET_ONLY(apic_cpumask, 0);
1035 1035 CPUSET_ADD(apic_cpumask, 1);
1036 1036 apic_nproc = 2;
1037 1037 lid = apic_reg_ops->apic_read(APIC_LID_REG);
1038 1038 apic_cpus[0].aci_local_id = (uchar_t)(lid >> APIC_ID_BIT_OFFSET);
1039 1039 /*
1040 1040 * According to the PC+MP spec 1.1, the local ids
1041 1041 * for the default configuration has to be 0 or 1
1042 1042 */
1043 1043 if (apic_cpus[0].aci_local_id == 1)
1044 1044 apic_cpus[1].aci_local_id = 0;
1045 1045 else if (apic_cpus[0].aci_local_id == 0)
1046 1046 apic_cpus[1].aci_local_id = 1;
1047 1047 else
1048 1048 goto apic_handle_defconf_fail;
1049 1049
1050 1050 apic_io_id[0] = 2;
1051 1051 apic_io_max = 1;
1052 1052 if (apic_defconf >= 5) {
1053 1053 apic_cpus[0].aci_local_ver = APIC_INTEGRATED_VERS;
1054 1054 apic_cpus[1].aci_local_ver = APIC_INTEGRATED_VERS;
1055 1055 apic_io_ver[0] = APIC_INTEGRATED_VERS;
1056 1056 } else {
1057 1057 apic_cpus[0].aci_local_ver = 0; /* 82489 DX */
1058 1058 apic_cpus[1].aci_local_ver = 0;
1059 1059 apic_io_ver[0] = 0;
1060 1060 }
1061 1061 if (apic_defconf == 2 || apic_defconf == 3 || apic_defconf == 6)
1062 1062 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) |
1063 1063 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1);
1064 1064 return (PSM_SUCCESS);
1065 1065
1066 1066 apic_handle_defconf_fail:
1067 1067 if (apicadr)
1068 1068 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
1069 1069 if (apicioadr[0])
1070 1070 mapout_ioapic((caddr_t)apicioadr[0], APIC_IO_MEMLEN);
1071 1071 return (PSM_FAILURE);
1072 1072 }
1073 1073
1074 1074 /* Parse the entries in MP configuration table and collect info that we need */
1075 1075 static int
1076 1076 apic_parse_mpct(caddr_t mpct, int bypass_cpus_and_ioapics)
1077 1077 {
1078 1078 struct apic_procent *procp;
1079 1079 struct apic_bus *busp;
1080 1080 struct apic_io_entry *ioapicp;
1081 1081 struct apic_io_intr *intrp;
1082 1082 int ioapic_ix;
1083 1083 uint_t lid;
1084 1084 uint32_t id;
1085 1085 uchar_t hid;
1086 1086 int warned = 0;
1087 1087
1088 1088 /*LINTED: pointer cast may result in improper alignment */
1089 1089 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr));
1090 1090
1091 1091 /* No need to count cpu entries if we won't use them */
1092 1092 if (!bypass_cpus_and_ioapics) {
1093 1093
1094 1094 /* Find max # of CPUS and allocate structure accordingly */
1095 1095 apic_nproc = 0;
1096 1096 CPUSET_ZERO(apic_cpumask);
1097 1097 while (procp->proc_entry == APIC_CPU_ENTRY) {
1098 1098 if (procp->proc_cpuflags & CPUFLAGS_EN) {
1099 1099 if (apic_nproc < NCPU && use_mp &&
1100 1100 apic_nproc < boot_ncpus) {
1101 1101 CPUSET_ADD(apic_cpumask, apic_nproc);
1102 1102 apic_nproc++;
1103 1103 } else if (apic_nproc == NCPU && !warned) {
1104 1104 cmn_err(CE_WARN, "%s: CPU limit "
1105 1105 "exceeded"
1106 1106 #if !defined(__amd64)
1107 1107 " for 32-bit mode"
1108 1108 #endif
1109 1109 "; Solaris will use %d CPUs.",
1110 1110 psm_name, NCPU);
1111 1111 warned = 1;
1112 1112 }
1113 1113
1114 1114 }
1115 1115 procp++;
1116 1116 }
1117 1117 apic_cpus_size = apic_nproc * sizeof (*apic_cpus);
1118 1118 if (!apic_nproc || !(apic_cpus = (apic_cpus_info_t *)
1119 1119 kmem_zalloc(apic_cpus_size, KM_NOSLEEP)))
1120 1120 return (PSM_FAILURE);
1121 1121 }
1122 1122
1123 1123 /*LINTED: pointer cast may result in improper alignment */
1124 1124 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr));
1125 1125
1126 1126 /*
1127 1127 * start with index 1 as 0 needs to be filled in with Boot CPU, but
1128 1128 * if we're bypassing this information, it has already been filled
1129 1129 * in by acpi_probe(), so don't overwrite it.
1130 1130 */
1131 1131 if (!bypass_cpus_and_ioapics)
1132 1132 apic_nproc = 1;
1133 1133
1134 1134 while (procp->proc_entry == APIC_CPU_ENTRY) {
1135 1135 /* check whether the cpu exists or not */
1136 1136 if (!bypass_cpus_and_ioapics &&
1137 1137 procp->proc_cpuflags & CPUFLAGS_EN) {
1138 1138 if (procp->proc_cpuflags & CPUFLAGS_BP) { /* Boot CPU */
1139 1139 lid = apic_reg_ops->apic_read(APIC_LID_REG);
1140 1140 apic_cpus[0].aci_local_id = procp->proc_apicid;
1141 1141 if (apic_cpus[0].aci_local_id !=
1142 1142 (uchar_t)(lid >> APIC_ID_BIT_OFFSET)) {
1143 1143 return (PSM_FAILURE);
1144 1144 }
1145 1145 apic_cpus[0].aci_local_ver =
1146 1146 procp->proc_version;
1147 1147 } else if (apic_nproc < NCPU && use_mp &&
1148 1148 apic_nproc < boot_ncpus) {
1149 1149 apic_cpus[apic_nproc].aci_local_id =
1150 1150 procp->proc_apicid;
1151 1151
1152 1152 apic_cpus[apic_nproc].aci_local_ver =
1153 1153 procp->proc_version;
1154 1154 apic_nproc++;
1155 1155
1156 1156 }
1157 1157 }
1158 1158 procp++;
1159 1159 }
1160 1160
1161 1161 /*
1162 1162 * Save start of bus entries for later use.
1163 1163 * Get EISA level cntrl if EISA bus is present.
1164 1164 * Also get the CPI bus id for single CPI bus case
1165 1165 */
1166 1166 apic_busp = busp = (struct apic_bus *)procp;
1167 1167 while (busp->bus_entry == APIC_BUS_ENTRY) {
1168 1168 lid = apic_find_bus_type((char *)&busp->bus_str1);
1169 1169 if (lid == BUS_EISA) {
1170 1170 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) |
1171 1171 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1);
1172 1172 } else if (lid == BUS_PCI) {
1173 1173 /*
1174 1174 * apic_single_pci_busid will be used only if
1175 1175 * apic_pic_bus_total is equal to 1
1176 1176 */
1177 1177 apic_pci_bus_total++;
1178 1178 apic_single_pci_busid = busp->bus_id;
1179 1179 }
1180 1180 busp++;
1181 1181 }
1182 1182
1183 1183 ioapicp = (struct apic_io_entry *)busp;
1184 1184
1185 1185 if (!bypass_cpus_and_ioapics)
1186 1186 apic_io_max = 0;
1187 1187 do {
1188 1188 if (!bypass_cpus_and_ioapics && apic_io_max < MAX_IO_APIC) {
1189 1189 if (ioapicp->io_flags & IOAPIC_FLAGS_EN) {
1190 1190 apic_io_id[apic_io_max] = ioapicp->io_apicid;
1191 1191 apic_io_ver[apic_io_max] = ioapicp->io_version;
1192 1192 apicioadr[apic_io_max] =
1193 1193 (void *)mapin_ioapic(
1194 1194 (uint32_t)ioapicp->io_apic_addr,
1195 1195 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
1196 1196
1197 1197 if (!apicioadr[apic_io_max])
1198 1198 return (PSM_FAILURE);
1199 1199
1200 1200 ioapic_mask_workaround[apic_io_max] =
1201 1201 apic_is_ioapic_AMD_813x(
1202 1202 ioapicp->io_apic_addr);
1203 1203
1204 1204 ioapic_ix = apic_io_max;
1205 1205 id = ioapic_read(ioapic_ix, APIC_ID_CMD);
1206 1206 hid = (uchar_t)(id >> 24);
1207 1207
1208 1208 if (hid != apic_io_id[apic_io_max]) {
1209 1209 if (apic_io_id[apic_io_max] == 0)
1210 1210 apic_io_id[apic_io_max] = hid;
1211 1211 else {
1212 1212 /*
1213 1213 * set ioapic id to whatever
1214 1214 * reported by MPS
1215 1215 *
1216 1216 * may not need to set index
1217 1217 * again ???
1218 1218 * take it out and try
1219 1219 */
1220 1220
1221 1221 id = ((uint32_t)
1222 1222 apic_io_id[apic_io_max]) <<
1223 1223 24;
1224 1224
1225 1225 ioapic_write(ioapic_ix,
1226 1226 APIC_ID_CMD, id);
1227 1227 }
1228 1228 }
1229 1229 apic_io_max++;
1230 1230 }
1231 1231 }
1232 1232 ioapicp++;
1233 1233 } while (ioapicp->io_entry == APIC_IO_ENTRY);
1234 1234
1235 1235 apic_io_intrp = (struct apic_io_intr *)ioapicp;
1236 1236
1237 1237 intrp = apic_io_intrp;
1238 1238 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1239 1239 if ((intrp->intr_irq > APIC_MAX_ISA_IRQ) ||
1240 1240 (apic_find_bus(intrp->intr_busid) == BUS_PCI)) {
1241 1241 apic_irq_translate = 1;
1242 1242 break;
1243 1243 }
1244 1244 intrp++;
1245 1245 }
1246 1246
1247 1247 return (PSM_SUCCESS);
1248 1248 }
1249 1249
1250 1250 boolean_t
1251 1251 apic_cpu_in_range(int cpu)
1252 1252 {
1253 1253 cpu &= ~IRQ_USER_BOUND;
1254 1254 /* Check whether cpu id is in valid range. */
1255 1255 if (cpu < 0 || cpu >= apic_nproc) {
1256 1256 return (B_FALSE);
1257 1257 } else if (apic_max_nproc != -1 && cpu >= apic_max_nproc) {
1258 1258 /*
1259 1259 * Check whether cpuid is in valid range if CPU DR is enabled.
1260 1260 */
1261 1261 return (B_FALSE);
1262 1262 } else if (!CPU_IN_SET(apic_cpumask, cpu)) {
1263 1263 return (B_FALSE);
1264 1264 }
1265 1265
1266 1266 return (B_TRUE);
1267 1267 }
1268 1268
1269 1269 processorid_t
1270 1270 apic_get_next_bind_cpu(void)
1271 1271 {
1272 1272 int i, count;
1273 1273 processorid_t cpuid = 0;
1274 1274
1275 1275 for (count = 0; count < apic_nproc; count++) {
1276 1276 if (apic_next_bind_cpu >= apic_nproc) {
1277 1277 apic_next_bind_cpu = 0;
1278 1278 }
1279 1279 i = apic_next_bind_cpu++;
1280 1280 if (apic_cpu_in_range(i)) {
1281 1281 cpuid = i;
1282 1282 break;
1283 1283 }
1284 1284 }
1285 1285
1286 1286 return (cpuid);
1287 1287 }
1288 1288
1289 1289 uint16_t
1290 1290 apic_get_apic_version()
1291 1291 {
1292 1292 int i;
1293 1293 uchar_t min_io_apic_ver = 0;
1294 1294 static uint16_t version; /* Cache as value is constant */
1295 1295 static boolean_t found = B_FALSE; /* Accomodate zero version */
1296 1296
1297 1297 if (found == B_FALSE) {
1298 1298 found = B_TRUE;
1299 1299
1300 1300 /*
1301 1301 * Don't assume all IO APICs in the system are the same.
1302 1302 *
1303 1303 * Set to the minimum version.
1304 1304 */
1305 1305 for (i = 0; i < apic_io_max; i++) {
1306 1306 if ((apic_io_ver[i] != 0) &&
1307 1307 ((min_io_apic_ver == 0) ||
1308 1308 (min_io_apic_ver >= apic_io_ver[i])))
1309 1309 min_io_apic_ver = apic_io_ver[i];
1310 1310 }
1311 1311
1312 1312 /* Assume all local APICs are of the same version. */
1313 1313 version = (min_io_apic_ver << 8) | apic_cpus[0].aci_local_ver;
1314 1314 }
1315 1315 return (version);
1316 1316 }
1317 1317
1318 1318 static struct apic_mpfps_hdr *
1319 1319 apic_find_fps_sig(caddr_t cptr, int len)
1320 1320 {
1321 1321 int i;
1322 1322
1323 1323 /* Look for the pattern "_MP_" */
1324 1324 for (i = 0; i < len; i += 16) {
1325 1325 if ((*(cptr+i) == '_') &&
1326 1326 (*(cptr+i+1) == 'M') &&
1327 1327 (*(cptr+i+2) == 'P') &&
1328 1328 (*(cptr+i+3) == '_'))
1329 1329 /*LINTED: pointer cast may result in improper alignment */
1330 1330 return ((struct apic_mpfps_hdr *)(cptr + i));
1331 1331 }
1332 1332 return (NULL);
1333 1333 }
1334 1334
1335 1335 static int
1336 1336 apic_checksum(caddr_t bptr, int len)
1337 1337 {
1338 1338 int i;
1339 1339 uchar_t cksum;
1340 1340
1341 1341 cksum = 0;
1342 1342 for (i = 0; i < len; i++)
1343 1343 cksum += *bptr++;
1344 1344 return ((int)cksum);
1345 1345 }
1346 1346
1347 1347 /*
1348 1348 * On machines with PCI-PCI bridges, a device behind a PCI-PCI bridge
1349 1349 * needs special handling. We may need to chase up the device tree,
1350 1350 * using the PCI-PCI Bridge specification's "rotating IPIN assumptions",
1351 1351 * to find the IPIN at the root bus that relates to the IPIN on the
1352 1352 * subsidiary bus (for ACPI or MP). We may, however, have an entry
1353 1353 * in the MP table or the ACPI namespace for this device itself.
1354 1354 * We handle both cases in the search below.
1355 1355 */
1356 1356 /* this is the non-acpi version */
1357 1357 int
1358 1358 apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, int child_ipin,
1359 1359 struct apic_io_intr **intrp)
1360 1360 {
1361 1361 dev_info_t *dipp, *dip;
1362 1362 int pci_irq;
1363 1363 ddi_acc_handle_t cfg_handle;
1364 1364 int bridge_devno, bridge_bus;
1365 1365 int ipin;
1366 1366
1367 1367 dip = idip;
1368 1368
1369 1369 /*CONSTCOND*/
1370 1370 while (1) {
1371 1371 if (((dipp = ddi_get_parent(dip)) == (dev_info_t *)NULL) ||
1372 1372 (pci_config_setup(dipp, &cfg_handle) != DDI_SUCCESS))
1373 1373 return (-1);
1374 1374 if ((pci_config_get8(cfg_handle, PCI_CONF_BASCLASS) ==
1375 1375 PCI_CLASS_BRIDGE) && (pci_config_get8(cfg_handle,
1376 1376 PCI_CONF_SUBCLASS) == PCI_BRIDGE_PCI)) {
1377 1377 pci_config_teardown(&cfg_handle);
1378 1378 if (acpica_get_bdf(dipp, &bridge_bus, &bridge_devno,
1379 1379 NULL) != 0)
1380 1380 return (-1);
1381 1381 /*
1382 1382 * This is the rotating scheme documented in the
1383 1383 * PCI-to-PCI spec. If the PCI-to-PCI bridge is
1384 1384 * behind another PCI-to-PCI bridge, then it needs
1385 1385 * to keep ascending until an interrupt entry is
1386 1386 * found or the root is reached.
1387 1387 */
1388 1388 ipin = (child_devno + child_ipin) % PCI_INTD;
1389 1389 if (bridge_bus == 0 && apic_pci_bus_total == 1)
1390 1390 bridge_bus = (int)apic_single_pci_busid;
1391 1391 pci_irq = ((bridge_devno & 0x1f) << 2) |
1392 1392 (ipin & 0x3);
1393 1393 if ((*intrp = apic_find_io_intr_w_busid(pci_irq,
1394 1394 bridge_bus)) != NULL) {
1395 1395 return (pci_irq);
1396 1396 }
1397 1397 dip = dipp;
1398 1398 child_devno = bridge_devno;
1399 1399 child_ipin = ipin;
1400 1400 } else {
1401 1401 pci_config_teardown(&cfg_handle);
1402 1402 return (-1);
1403 1403 }
1404 1404 }
1405 1405 /*LINTED: function will not fall off the bottom */
1406 1406 }
1407 1407
1408 1408 uchar_t
1409 1409 acpi_find_ioapic(int irq)
1410 1410 {
1411 1411 int i;
1412 1412
1413 1413 for (i = 0; i < apic_io_max; i++) {
1414 1414 if (irq >= apic_io_vectbase[i] && irq <= apic_io_vectend[i])
1415 1415 return ((uchar_t)i);
1416 1416 }
1417 1417 return (0xFF); /* shouldn't happen */
1418 1418 }
1419 1419
1420 1420 /*
1421 1421 * See if two irqs are compatible for sharing a vector.
1422 1422 * Currently we only support sharing of PCI devices.
1423 1423 */
1424 1424 static int
1425 1425 acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2)
1426 1426 {
1427 1427 uint_t level1, po1;
1428 1428 uint_t level2, po2;
1429 1429
1430 1430 /* Assume active high by default */
1431 1431 po1 = 0;
1432 1432 po2 = 0;
1433 1433
1434 1434 if (iflag1.bustype != iflag2.bustype || iflag1.bustype != BUS_PCI)
1435 1435 return (0);
1436 1436
1437 1437 if (iflag1.intr_el == INTR_EL_CONFORM)
1438 1438 level1 = AV_LEVEL;
1439 1439 else
1440 1440 level1 = (iflag1.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0;
1441 1441
1442 1442 if (level1 && ((iflag1.intr_po == INTR_PO_ACTIVE_LOW) ||
1443 1443 (iflag1.intr_po == INTR_PO_CONFORM)))
1444 1444 po1 = AV_ACTIVE_LOW;
1445 1445
1446 1446 if (iflag2.intr_el == INTR_EL_CONFORM)
1447 1447 level2 = AV_LEVEL;
1448 1448 else
1449 1449 level2 = (iflag2.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0;
1450 1450
1451 1451 if (level2 && ((iflag2.intr_po == INTR_PO_ACTIVE_LOW) ||
1452 1452 (iflag2.intr_po == INTR_PO_CONFORM)))
1453 1453 po2 = AV_ACTIVE_LOW;
1454 1454
1455 1455 if ((level1 == level2) && (po1 == po2))
1456 1456 return (1);
1457 1457
1458 1458 return (0);
1459 1459 }
1460 1460
1461 1461 struct apic_io_intr *
1462 1462 apic_find_io_intr_w_busid(int irqno, int busid)
1463 1463 {
1464 1464 struct apic_io_intr *intrp;
1465 1465
1466 1466 /*
1467 1467 * It can have more than 1 entry with same source bus IRQ,
1468 1468 * but unique with the source bus id
1469 1469 */
1470 1470 intrp = apic_io_intrp;
1471 1471 if (intrp != NULL) {
1472 1472 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1473 1473 if (intrp->intr_irq == irqno &&
1474 1474 intrp->intr_busid == busid &&
1475 1475 intrp->intr_type == IO_INTR_INT)
1476 1476 return (intrp);
1477 1477 intrp++;
1478 1478 }
1479 1479 }
1480 1480 APIC_VERBOSE_IOAPIC((CE_NOTE, "Did not find io intr for irqno:"
1481 1481 "busid %x:%x\n", irqno, busid));
1482 1482 return ((struct apic_io_intr *)NULL);
1483 1483 }
1484 1484
1485 1485
1486 1486 struct mps_bus_info {
1487 1487 char *bus_name;
1488 1488 int bus_id;
1489 1489 } bus_info_array[] = {
1490 1490 "ISA ", BUS_ISA,
1491 1491 "PCI ", BUS_PCI,
1492 1492 "EISA ", BUS_EISA,
1493 1493 "XPRESS", BUS_XPRESS,
1494 1494 "PCMCIA", BUS_PCMCIA,
1495 1495 "VL ", BUS_VL,
1496 1496 "CBUS ", BUS_CBUS,
1497 1497 "CBUSII", BUS_CBUSII,
1498 1498 "FUTURE", BUS_FUTURE,
1499 1499 "INTERN", BUS_INTERN,
1500 1500 "MBI ", BUS_MBI,
1501 1501 "MBII ", BUS_MBII,
1502 1502 "MPI ", BUS_MPI,
1503 1503 "MPSA ", BUS_MPSA,
1504 1504 "NUBUS ", BUS_NUBUS,
1505 1505 "TC ", BUS_TC,
1506 1506 "VME ", BUS_VME,
1507 1507 "PCI-E ", BUS_PCIE
1508 1508 };
1509 1509
1510 1510 static int
1511 1511 apic_find_bus_type(char *bus)
1512 1512 {
1513 1513 int i = 0;
1514 1514
1515 1515 for (; i < sizeof (bus_info_array)/sizeof (struct mps_bus_info); i++)
1516 1516 if (strncmp(bus, bus_info_array[i].bus_name,
1517 1517 strlen(bus_info_array[i].bus_name)) == 0)
1518 1518 return (bus_info_array[i].bus_id);
1519 1519 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus type for bus %s", bus));
1520 1520 return (0);
1521 1521 }
1522 1522
1523 1523 static int
1524 1524 apic_find_bus(int busid)
1525 1525 {
1526 1526 struct apic_bus *busp;
1527 1527
1528 1528 busp = apic_busp;
1529 1529 while (busp->bus_entry == APIC_BUS_ENTRY) {
1530 1530 if (busp->bus_id == busid)
1531 1531 return (apic_find_bus_type((char *)&busp->bus_str1));
1532 1532 busp++;
1533 1533 }
1534 1534 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus for bus id %x", busid));
1535 1535 return (0);
1536 1536 }
1537 1537
1538 1538 int
1539 1539 apic_find_bus_id(int bustype)
1540 1540 {
1541 1541 struct apic_bus *busp;
1542 1542
1543 1543 busp = apic_busp;
1544 1544 while (busp->bus_entry == APIC_BUS_ENTRY) {
1545 1545 if (apic_find_bus_type((char *)&busp->bus_str1) == bustype)
1546 1546 return (busp->bus_id);
1547 1547 busp++;
1548 1548 }
1549 1549 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus id for bustype %x",
1550 1550 bustype));
1551 1551 return (-1);
1552 1552 }
1553 1553
1554 1554 /*
1555 1555 * Check if a particular irq need to be reserved for any io_intr
1556 1556 */
1557 1557 static struct apic_io_intr *
1558 1558 apic_find_io_intr(int irqno)
1559 1559 {
1560 1560 struct apic_io_intr *intrp;
1561 1561
1562 1562 intrp = apic_io_intrp;
1563 1563 if (intrp != NULL) {
1564 1564 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1565 1565 if (intrp->intr_irq == irqno &&
1566 1566 intrp->intr_type == IO_INTR_INT)
1567 1567 return (intrp);
1568 1568 intrp++;
1569 1569 }
1570 1570 }
1571 1571 return ((struct apic_io_intr *)NULL);
1572 1572 }
1573 1573
1574 1574 /*
1575 1575 * Check if the given ioapicindex intin combination has already been assigned
1576 1576 * an irq. If so return irqno. Else -1
1577 1577 */
1578 1578 int
1579 1579 apic_find_intin(uchar_t ioapic, uchar_t intin)
1580 1580 {
1581 1581 apic_irq_t *irqptr;
1582 1582 int i;
1583 1583
1584 1584 /* find ioapic and intin in the apic_irq_table[] and return the index */
1585 1585 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
1586 1586 irqptr = apic_irq_table[i];
1587 1587 while (irqptr) {
1588 1588 if ((irqptr->airq_mps_intr_index >= 0) &&
1589 1589 (irqptr->airq_intin_no == intin) &&
1590 1590 (irqptr->airq_ioapicindex == ioapic)) {
1591 1591 APIC_VERBOSE_IOAPIC((CE_NOTE, "!Found irq "
1592 1592 "entry for ioapic:intin %x:%x "
1593 1593 "shared interrupts ?", ioapic, intin));
1594 1594 return (i);
1595 1595 }
1596 1596 irqptr = irqptr->airq_next;
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1597 1597 }
1598 1598 }
1599 1599 return (-1);
1600 1600 }
1601 1601
1602 1602 int
1603 1603 apic_allocate_irq(int irq)
1604 1604 {
1605 1605 int freeirq, i;
1606 1606
1607 - if ((freeirq = apic_find_free_irq(irq, (APIC_RESV_IRQ - 1))) == -1)
1607 + if ((freeirq = apic_find_free_irq(irq, (APIC_RESV_IRQ - 1))) == -1) {
1608 1608 if ((freeirq = apic_find_free_irq(APIC_FIRST_FREE_IRQ,
1609 1609 (irq - 1))) == -1) {
1610 1610 /*
1611 1611 * if BIOS really defines every single irq in the mps
1612 1612 * table, then don't worry about conflicting with
1613 1613 * them, just use any free slot in apic_irq_table
1614 1614 */
1615 1615 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
1616 1616 if ((apic_irq_table[i] == NULL) ||
1617 1617 apic_irq_table[i]->airq_mps_intr_index ==
1618 1618 FREE_INDEX) {
1619 - freeirq = i;
1620 - break;
1619 + freeirq = i;
1620 + break;
1621 + }
1621 1622 }
1623 +
1624 + if (freeirq == -1) {
1625 + /* This shouldn't happen, but just in case */
1626 + cmn_err(CE_WARN, "%s: NO available IRQ", psm_name);
1627 + return (-1);
1628 + }
1622 1629 }
1623 - if (freeirq == -1) {
1624 - /* This shouldn't happen, but just in case */
1625 - cmn_err(CE_WARN, "%s: NO available IRQ", psm_name);
1626 - return (-1);
1627 - }
1628 1630 }
1631 +
1629 1632 if (apic_irq_table[freeirq] == NULL) {
1630 1633 apic_irq_table[freeirq] =
1631 1634 kmem_zalloc(sizeof (apic_irq_t), KM_NOSLEEP);
1632 1635 if (apic_irq_table[freeirq] == NULL) {
1633 1636 cmn_err(CE_WARN, "%s: NO memory to allocate IRQ",
1634 1637 psm_name);
1635 1638 return (-1);
1636 1639 }
1637 1640 apic_irq_table[freeirq]->airq_temp_cpu = IRQ_UNINIT;
1638 1641 apic_irq_table[freeirq]->airq_mps_intr_index = FREE_INDEX;
1639 1642 }
1640 1643 return (freeirq);
1641 1644 }
1642 1645
1643 1646 static int
1644 1647 apic_find_free_irq(int start, int end)
1645 1648 {
1646 1649 int i;
1647 1650
1648 1651 for (i = start; i <= end; i++)
1649 1652 /* Check if any I/O entry needs this IRQ */
1650 1653 if (apic_find_io_intr(i) == NULL) {
1651 1654 /* Then see if it is free */
1652 1655 if ((apic_irq_table[i] == NULL) ||
1653 1656 (apic_irq_table[i]->airq_mps_intr_index ==
1654 1657 FREE_INDEX)) {
1655 1658 return (i);
1656 1659 }
1657 1660 }
1658 1661 return (-1);
1659 1662 }
1660 1663
1661 1664 /*
1662 1665 * compute the polarity, trigger mode and vector for programming into
1663 1666 * the I/O apic and record in airq_rdt_entry.
1664 1667 */
1665 1668 void
1666 1669 apic_record_rdt_entry(apic_irq_t *irqptr, int irq)
1667 1670 {
1668 1671 int ioapicindex, bus_type, vector;
1669 1672 short intr_index;
1670 1673 uint_t level, po, io_po;
1671 1674 struct apic_io_intr *iointrp;
1672 1675
1673 1676 intr_index = irqptr->airq_mps_intr_index;
1674 1677 DDI_INTR_IMPLDBG((CE_CONT, "apic_record_rdt_entry: intr_index=%d "
1675 1678 "irq = 0x%x dip = 0x%p vector = 0x%x\n", intr_index, irq,
1676 1679 (void *)irqptr->airq_dip, irqptr->airq_vector));
1677 1680
1678 1681 if (intr_index == RESERVE_INDEX) {
1679 1682 apic_error |= APIC_ERR_INVALID_INDEX;
1680 1683 return;
1681 1684 } else if (APIC_IS_MSI_OR_MSIX_INDEX(intr_index)) {
1682 1685 return;
1683 1686 }
1684 1687
1685 1688 vector = irqptr->airq_vector;
1686 1689 ioapicindex = irqptr->airq_ioapicindex;
1687 1690 /* Assume edge triggered by default */
1688 1691 level = 0;
1689 1692 /* Assume active high by default */
1690 1693 po = 0;
1691 1694
1692 1695 if (intr_index == DEFAULT_INDEX || intr_index == FREE_INDEX) {
1693 1696 ASSERT(irq < 16);
1694 1697 if (eisa_level_intr_mask & (1 << irq))
1695 1698 level = AV_LEVEL;
1696 1699 if (intr_index == FREE_INDEX && apic_defconf == 0)
1697 1700 apic_error |= APIC_ERR_INVALID_INDEX;
1698 1701 } else if (intr_index == ACPI_INDEX) {
1699 1702 bus_type = irqptr->airq_iflag.bustype;
1700 1703 if (irqptr->airq_iflag.intr_el == INTR_EL_CONFORM) {
1701 1704 if (bus_type == BUS_PCI)
1702 1705 level = AV_LEVEL;
1703 1706 } else
1704 1707 level = (irqptr->airq_iflag.intr_el == INTR_EL_LEVEL) ?
1705 1708 AV_LEVEL : 0;
1706 1709 if (level &&
1707 1710 ((irqptr->airq_iflag.intr_po == INTR_PO_ACTIVE_LOW) ||
1708 1711 (irqptr->airq_iflag.intr_po == INTR_PO_CONFORM &&
1709 1712 bus_type == BUS_PCI)))
1710 1713 po = AV_ACTIVE_LOW;
1711 1714 } else {
1712 1715 iointrp = apic_io_intrp + intr_index;
1713 1716 bus_type = apic_find_bus(iointrp->intr_busid);
1714 1717 if (iointrp->intr_el == INTR_EL_CONFORM) {
1715 1718 if ((irq < 16) && (eisa_level_intr_mask & (1 << irq)))
1716 1719 level = AV_LEVEL;
1717 1720 else if (bus_type == BUS_PCI)
1718 1721 level = AV_LEVEL;
1719 1722 } else
1720 1723 level = (iointrp->intr_el == INTR_EL_LEVEL) ?
1721 1724 AV_LEVEL : 0;
1722 1725 if (level && ((iointrp->intr_po == INTR_PO_ACTIVE_LOW) ||
1723 1726 (iointrp->intr_po == INTR_PO_CONFORM &&
1724 1727 bus_type == BUS_PCI)))
1725 1728 po = AV_ACTIVE_LOW;
1726 1729 }
1727 1730 if (level)
1728 1731 apic_level_intr[irq] = 1;
1729 1732 /*
1730 1733 * The 82489DX External APIC cannot do active low polarity interrupts.
1731 1734 */
1732 1735 if (po && (apic_io_ver[ioapicindex] != IOAPIC_VER_82489DX))
1733 1736 io_po = po;
1734 1737 else
1735 1738 io_po = 0;
1736 1739
1737 1740 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG)
1738 1741 prom_printf("setio: ioapic=0x%x intin=0x%x level=0x%x po=0x%x "
1739 1742 "vector=0x%x cpu=0x%x\n\n", ioapicindex,
1740 1743 irqptr->airq_intin_no, level, io_po, vector,
1741 1744 irqptr->airq_cpu);
1742 1745
1743 1746 irqptr->airq_rdt_entry = level|io_po|vector;
1744 1747 }
1745 1748
1746 1749 int
1747 1750 apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid,
1748 1751 int ipin, int *pci_irqp, iflag_t *intr_flagp)
1749 1752 {
1750 1753
1751 1754 int status;
1752 1755 acpi_psm_lnk_t acpipsmlnk;
1753 1756
1754 1757 if ((status = acpi_get_irq_cache_ent(busid, devid, ipin, pci_irqp,
1755 1758 intr_flagp)) == ACPI_PSM_SUCCESS) {
1756 1759 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Found irqno %d "
1757 1760 "from cache for device %s, instance #%d\n", psm_name,
1758 1761 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip)));
1759 1762 return (status);
1760 1763 }
1761 1764
1762 1765 bzero(&acpipsmlnk, sizeof (acpi_psm_lnk_t));
1763 1766
1764 1767 if ((status = acpi_translate_pci_irq(dip, ipin, pci_irqp, intr_flagp,
1765 1768 &acpipsmlnk)) == ACPI_PSM_FAILURE) {
1766 1769 APIC_VERBOSE_IRQ((CE_WARN, "%s: "
1767 1770 " acpi_translate_pci_irq failed for device %s, instance"
1768 1771 " #%d", psm_name, ddi_get_name(dip),
1769 1772 ddi_get_instance(dip)));
1770 1773 return (status);
1771 1774 }
1772 1775
1773 1776 if (status == ACPI_PSM_PARTIAL && acpipsmlnk.lnkobj != NULL) {
1774 1777 status = apic_acpi_irq_configure(&acpipsmlnk, dip, pci_irqp,
1775 1778 intr_flagp);
1776 1779 if (status != ACPI_PSM_SUCCESS) {
1777 1780 status = acpi_get_current_irq_resource(&acpipsmlnk,
1778 1781 pci_irqp, intr_flagp);
1779 1782 }
1780 1783 }
1781 1784
1782 1785 if (status == ACPI_PSM_SUCCESS) {
1783 1786 acpi_new_irq_cache_ent(busid, devid, ipin, *pci_irqp,
1784 1787 intr_flagp, &acpipsmlnk);
1785 1788
1786 1789 APIC_VERBOSE_IRQ((CE_CONT, "%s: [ACPI] "
1787 1790 "new irq %d for device %s, instance #%d\n", psm_name,
1788 1791 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip)));
1789 1792 }
1790 1793
1791 1794 return (status);
1792 1795 }
1793 1796
1794 1797 /*
1795 1798 * Adds an entry to the irq list passed in, and returns the new list.
1796 1799 * Entries are added in priority order (lower numerical priorities are
1797 1800 * placed closer to the head of the list)
1798 1801 */
1799 1802 static prs_irq_list_t *
1800 1803 acpi_insert_prs_irq_ent(prs_irq_list_t *listp, int priority, int irq,
1801 1804 iflag_t *iflagp, acpi_prs_private_t *prsprvp)
1802 1805 {
1803 1806 struct prs_irq_list_ent *newent, *prevp = NULL, *origlistp;
1804 1807
1805 1808 newent = kmem_zalloc(sizeof (struct prs_irq_list_ent), KM_SLEEP);
1806 1809
1807 1810 newent->list_prio = priority;
1808 1811 newent->irq = irq;
1809 1812 newent->intrflags = *iflagp;
1810 1813 newent->prsprv = *prsprvp;
1811 1814 /* ->next is NULL from kmem_zalloc */
1812 1815
1813 1816 /*
1814 1817 * New list -- return the new entry as the list.
1815 1818 */
1816 1819 if (listp == NULL)
1817 1820 return (newent);
1818 1821
1819 1822 /*
1820 1823 * Save original list pointer for return (since we're not modifying
1821 1824 * the head)
1822 1825 */
1823 1826 origlistp = listp;
1824 1827
1825 1828 /*
1826 1829 * Insertion sort, with entries with identical keys stored AFTER
1827 1830 * existing entries (the less-than-or-equal test of priority does
1828 1831 * this for us).
1829 1832 */
1830 1833 while (listp != NULL && listp->list_prio <= priority) {
1831 1834 prevp = listp;
1832 1835 listp = listp->next;
1833 1836 }
1834 1837
1835 1838 newent->next = listp;
1836 1839
1837 1840 if (prevp == NULL) { /* Add at head of list (newent is the new head) */
1838 1841 return (newent);
1839 1842 } else {
1840 1843 prevp->next = newent;
1841 1844 return (origlistp);
1842 1845 }
1843 1846 }
1844 1847
1845 1848 /*
1846 1849 * Frees the list passed in, deallocating all memory and leaving *listpp
1847 1850 * set to NULL.
1848 1851 */
1849 1852 static void
1850 1853 acpi_destroy_prs_irq_list(prs_irq_list_t **listpp)
1851 1854 {
1852 1855 struct prs_irq_list_ent *nextp;
1853 1856
1854 1857 ASSERT(listpp != NULL);
1855 1858
1856 1859 while (*listpp != NULL) {
1857 1860 nextp = (*listpp)->next;
1858 1861 kmem_free(*listpp, sizeof (struct prs_irq_list_ent));
1859 1862 *listpp = nextp;
1860 1863 }
1861 1864 }
1862 1865
1863 1866 /*
1864 1867 * apic_choose_irqs_from_prs returns a list of irqs selected from the list of
1865 1868 * irqs returned by the link device's _PRS method. The irqs are chosen
1866 1869 * to minimize contention in situations where the interrupt link device
1867 1870 * can be programmed to steer interrupts to different interrupt controller
1868 1871 * inputs (some of which may already be in use). The list is sorted in order
1869 1872 * of irqs to use, with the highest priority given to interrupt controller
1870 1873 * inputs that are not shared. When an interrupt controller input
1871 1874 * must be shared, apic_choose_irqs_from_prs adds the possible irqs to the
1872 1875 * returned list in the order that minimizes sharing (thereby ensuring lowest
1873 1876 * possible latency from interrupt trigger time to ISR execution time).
1874 1877 */
1875 1878 static prs_irq_list_t *
1876 1879 apic_choose_irqs_from_prs(acpi_irqlist_t *irqlistent, dev_info_t *dip,
1877 1880 int crs_irq)
1878 1881 {
1879 1882 int32_t irq;
1880 1883 int i;
1881 1884 prs_irq_list_t *prsirqlistp = NULL;
1882 1885 iflag_t iflags;
1883 1886
1884 1887 while (irqlistent != NULL) {
1885 1888 irqlistent->intr_flags.bustype = BUS_PCI;
1886 1889
1887 1890 for (i = 0; i < irqlistent->num_irqs; i++) {
1888 1891
1889 1892 irq = irqlistent->irqs[i];
1890 1893
1891 1894 if (irq <= 0) {
1892 1895 /* invalid irq number */
1893 1896 continue;
1894 1897 }
1895 1898
1896 1899 if ((irq < 16) && (apic_reserved_irqlist[irq]))
1897 1900 continue;
1898 1901
1899 1902 if ((apic_irq_table[irq] == NULL) ||
1900 1903 (apic_irq_table[irq]->airq_dip == dip)) {
1901 1904
1902 1905 prsirqlistp = acpi_insert_prs_irq_ent(
1903 1906 prsirqlistp, 0 /* Highest priority */, irq,
1904 1907 &irqlistent->intr_flags,
1905 1908 &irqlistent->acpi_prs_prv);
1906 1909
1907 1910 /*
1908 1911 * If we do not prefer the current irq from _CRS
1909 1912 * or if we do and this irq is the same as the
1910 1913 * current irq from _CRS, this is the one
1911 1914 * to pick.
1912 1915 */
1913 1916 if (!(apic_prefer_crs) || (irq == crs_irq)) {
1914 1917 return (prsirqlistp);
1915 1918 }
1916 1919 continue;
1917 1920 }
1918 1921
1919 1922 /*
1920 1923 * Edge-triggered interrupts cannot be shared
1921 1924 */
1922 1925 if (irqlistent->intr_flags.intr_el == INTR_EL_EDGE)
1923 1926 continue;
1924 1927
1925 1928 /*
1926 1929 * To work around BIOSes that contain incorrect
1927 1930 * interrupt polarity information in interrupt
1928 1931 * descriptors returned by _PRS, we assume that
1929 1932 * the polarity of the other device sharing this
1930 1933 * interrupt controller input is compatible.
1931 1934 * If it's not, the caller will catch it when
1932 1935 * the caller invokes the link device's _CRS method
1933 1936 * (after invoking its _SRS method).
1934 1937 */
1935 1938 iflags = irqlistent->intr_flags;
1936 1939 iflags.intr_po =
1937 1940 apic_irq_table[irq]->airq_iflag.intr_po;
1938 1941
1939 1942 if (!acpi_intr_compatible(iflags,
1940 1943 apic_irq_table[irq]->airq_iflag)) {
1941 1944 APIC_VERBOSE_IRQ((CE_CONT, "!%s: irq %d "
1942 1945 "not compatible [%x:%x:%x !~ %x:%x:%x]",
1943 1946 psm_name, irq,
1944 1947 iflags.intr_po,
1945 1948 iflags.intr_el,
1946 1949 iflags.bustype,
1947 1950 apic_irq_table[irq]->airq_iflag.intr_po,
1948 1951 apic_irq_table[irq]->airq_iflag.intr_el,
1949 1952 apic_irq_table[irq]->airq_iflag.bustype));
1950 1953 continue;
1951 1954 }
1952 1955
1953 1956 /*
1954 1957 * If we prefer the irq from _CRS, no need
1955 1958 * to search any further (and make sure
1956 1959 * to add this irq with the highest priority
1957 1960 * so it's tried first).
1958 1961 */
1959 1962 if (crs_irq == irq && apic_prefer_crs) {
1960 1963
1961 1964 return (acpi_insert_prs_irq_ent(
1962 1965 prsirqlistp,
1963 1966 0 /* Highest priority */,
1964 1967 irq, &iflags,
1965 1968 &irqlistent->acpi_prs_prv));
1966 1969 }
1967 1970
1968 1971 /*
1969 1972 * Priority is equal to the share count (lower
1970 1973 * share count is higher priority). Note that
1971 1974 * the intr flags passed in here are the ones we
1972 1975 * changed above -- if incorrect, it will be
1973 1976 * caught by the caller's _CRS flags comparison.
1974 1977 */
1975 1978 prsirqlistp = acpi_insert_prs_irq_ent(
1976 1979 prsirqlistp,
1977 1980 apic_irq_table[irq]->airq_share, irq,
1978 1981 &iflags, &irqlistent->acpi_prs_prv);
1979 1982 }
1980 1983
1981 1984 /* Go to the next irqlist entry */
1982 1985 irqlistent = irqlistent->next;
1983 1986 }
1984 1987
1985 1988 return (prsirqlistp);
1986 1989 }
1987 1990
1988 1991 /*
1989 1992 * Configures the irq for the interrupt link device identified by
1990 1993 * acpipsmlnkp.
1991 1994 *
1992 1995 * Gets the current and the list of possible irq settings for the
1993 1996 * device. If apic_unconditional_srs is not set, and the current
1994 1997 * resource setting is in the list of possible irq settings,
1995 1998 * current irq resource setting is passed to the caller.
1996 1999 *
1997 2000 * Otherwise, picks an irq number from the list of possible irq
1998 2001 * settings, and sets the irq of the device to this value.
1999 2002 * If prefer_crs is set, among a set of irq numbers in the list that have
2000 2003 * the least number of devices sharing the interrupt, we pick current irq
2001 2004 * resource setting if it is a member of this set.
2002 2005 *
2003 2006 * Passes the irq number in the value pointed to by pci_irqp, and
2004 2007 * polarity and sensitivity in the structure pointed to by dipintrflagp
2005 2008 * to the caller.
2006 2009 *
2007 2010 * Note that if setting the irq resource failed, but successfuly obtained
2008 2011 * the current irq resource settings, passes the current irq resources
2009 2012 * and considers it a success.
2010 2013 *
2011 2014 * Returns:
2012 2015 * ACPI_PSM_SUCCESS on success.
2013 2016 *
2014 2017 * ACPI_PSM_FAILURE if an error occured during the configuration or
2015 2018 * if a suitable irq was not found for this device, or if setting the
2016 2019 * irq resource and obtaining the current resource fails.
2017 2020 *
2018 2021 */
2019 2022 static int
2020 2023 apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip,
2021 2024 int *pci_irqp, iflag_t *dipintr_flagp)
2022 2025 {
2023 2026 int32_t irq;
2024 2027 int cur_irq = -1;
2025 2028 acpi_irqlist_t *irqlistp;
2026 2029 prs_irq_list_t *prs_irq_listp, *prs_irq_entp;
2027 2030 boolean_t found_irq = B_FALSE;
2028 2031
2029 2032 dipintr_flagp->bustype = BUS_PCI;
2030 2033
2031 2034 if ((acpi_get_possible_irq_resources(acpipsmlnkp, &irqlistp))
2032 2035 == ACPI_PSM_FAILURE) {
2033 2036 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Unable to determine "
2034 2037 "or assign IRQ for device %s, instance #%d: The system was "
2035 2038 "unable to get the list of potential IRQs from ACPI.",
2036 2039 psm_name, ddi_get_name(dip), ddi_get_instance(dip)));
2037 2040
2038 2041 return (ACPI_PSM_FAILURE);
2039 2042 }
2040 2043
2041 2044 if ((acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq,
2042 2045 dipintr_flagp) == ACPI_PSM_SUCCESS) && (!apic_unconditional_srs) &&
2043 2046 (cur_irq > 0)) {
2044 2047 /*
2045 2048 * If an IRQ is set in CRS and that IRQ exists in the set
2046 2049 * returned from _PRS, return that IRQ, otherwise print
2047 2050 * a warning
2048 2051 */
2049 2052
2050 2053 if (acpi_irqlist_find_irq(irqlistp, cur_irq, NULL)
2051 2054 == ACPI_PSM_SUCCESS) {
2052 2055
2053 2056 ASSERT(pci_irqp != NULL);
2054 2057 *pci_irqp = cur_irq;
2055 2058 acpi_free_irqlist(irqlistp);
2056 2059 return (ACPI_PSM_SUCCESS);
2057 2060 }
2058 2061
2059 2062 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find the "
2060 2063 "current irq %d for device %s, instance #%d in ACPI's "
2061 2064 "list of possible irqs for this device. Picking one from "
2062 2065 " the latter list.", psm_name, cur_irq, ddi_get_name(dip),
2063 2066 ddi_get_instance(dip)));
2064 2067 }
2065 2068
2066 2069 if ((prs_irq_listp = apic_choose_irqs_from_prs(irqlistp, dip,
2067 2070 cur_irq)) == NULL) {
2068 2071
2069 2072 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find a "
2070 2073 "suitable irq from the list of possible irqs for device "
2071 2074 "%s, instance #%d in ACPI's list of possible irqs",
2072 2075 psm_name, ddi_get_name(dip), ddi_get_instance(dip)));
2073 2076
2074 2077 acpi_free_irqlist(irqlistp);
2075 2078 return (ACPI_PSM_FAILURE);
2076 2079 }
2077 2080
2078 2081 acpi_free_irqlist(irqlistp);
2079 2082
2080 2083 for (prs_irq_entp = prs_irq_listp;
2081 2084 prs_irq_entp != NULL && found_irq == B_FALSE;
2082 2085 prs_irq_entp = prs_irq_entp->next) {
2083 2086
2084 2087 acpipsmlnkp->acpi_prs_prv = prs_irq_entp->prsprv;
2085 2088 irq = prs_irq_entp->irq;
2086 2089
2087 2090 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Setting irq %d for "
2088 2091 "device %s instance #%d\n", psm_name, irq,
2089 2092 ddi_get_name(dip), ddi_get_instance(dip)));
2090 2093
2091 2094 if ((acpi_set_irq_resource(acpipsmlnkp, irq))
2092 2095 == ACPI_PSM_SUCCESS) {
2093 2096 /*
2094 2097 * setting irq was successful, check to make sure CRS
2095 2098 * reflects that. If CRS does not agree with what we
2096 2099 * set, return the irq that was set.
2097 2100 */
2098 2101
2099 2102 if (acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq,
2100 2103 dipintr_flagp) == ACPI_PSM_SUCCESS) {
2101 2104
2102 2105 if (cur_irq != irq)
2103 2106 APIC_VERBOSE_IRQ((CE_WARN,
2104 2107 "!%s: IRQ resource set "
2105 2108 "(irqno %d) for device %s "
2106 2109 "instance #%d, differs from "
2107 2110 "current setting irqno %d",
2108 2111 psm_name, irq, ddi_get_name(dip),
2109 2112 ddi_get_instance(dip), cur_irq));
2110 2113 } else {
2111 2114 /*
2112 2115 * On at least one system, there was a bug in
2113 2116 * a DSDT method called by _STA, causing _STA to
2114 2117 * indicate that the link device was disabled
2115 2118 * (when, in fact, it was enabled). Since _SRS
2116 2119 * succeeded, assume that _CRS is lying and use
2117 2120 * the iflags from this _PRS interrupt choice.
2118 2121 * If we're wrong about the flags, the polarity
2119 2122 * will be incorrect and we may get an interrupt
2120 2123 * storm, but there's not much else we can do
2121 2124 * at this point.
2122 2125 */
2123 2126 *dipintr_flagp = prs_irq_entp->intrflags;
2124 2127 }
2125 2128
2126 2129 /*
2127 2130 * Return the irq that was set, and not what _CRS
2128 2131 * reports, since _CRS has been seen to return
2129 2132 * different IRQs than what was passed to _SRS on some
2130 2133 * systems (and just not return successfully on others).
2131 2134 */
2132 2135 cur_irq = irq;
2133 2136 found_irq = B_TRUE;
2134 2137 } else {
2135 2138 APIC_VERBOSE_IRQ((CE_WARN, "!%s: set resource "
2136 2139 "irq %d failed for device %s instance #%d",
2137 2140 psm_name, irq, ddi_get_name(dip),
2138 2141 ddi_get_instance(dip)));
2139 2142
2140 2143 if (cur_irq == -1) {
2141 2144 acpi_destroy_prs_irq_list(&prs_irq_listp);
2142 2145 return (ACPI_PSM_FAILURE);
2143 2146 }
2144 2147 }
2145 2148 }
2146 2149
2147 2150 acpi_destroy_prs_irq_list(&prs_irq_listp);
2148 2151
2149 2152 if (!found_irq)
2150 2153 return (ACPI_PSM_FAILURE);
2151 2154
2152 2155 ASSERT(pci_irqp != NULL);
2153 2156 *pci_irqp = cur_irq;
2154 2157 return (ACPI_PSM_SUCCESS);
2155 2158 }
2156 2159
2157 2160 void
2158 2161 ioapic_disable_redirection()
2159 2162 {
2160 2163 int ioapic_ix;
2161 2164 int intin_max;
2162 2165 int intin_ix;
2163 2166
2164 2167 /* Disable the I/O APIC redirection entries */
2165 2168 for (ioapic_ix = 0; ioapic_ix < apic_io_max; ioapic_ix++) {
2166 2169
2167 2170 /* Bits 23-16 define the maximum redirection entries */
2168 2171 intin_max = (ioapic_read(ioapic_ix, APIC_VERS_CMD) >> 16)
2169 2172 & 0xff;
2170 2173
2171 2174 for (intin_ix = 0; intin_ix <= intin_max; intin_ix++) {
2172 2175 /*
2173 2176 * The assumption here is that this is safe, even for
2174 2177 * systems with IOAPICs that suffer from the hardware
2175 2178 * erratum because all devices have been quiesced before
2176 2179 * this function is called from apic_shutdown()
2177 2180 * (or equivalent). If that assumption turns out to be
2178 2181 * false, this mask operation can induce the same
2179 2182 * erratum result we're trying to avoid.
2180 2183 */
2181 2184 ioapic_write(ioapic_ix, APIC_RDT_CMD + 2 * intin_ix,
2182 2185 AV_MASK);
2183 2186 }
2184 2187 }
2185 2188 }
2186 2189
2187 2190 /*
2188 2191 * Looks for an IOAPIC with the specified physical address in the /ioapics
2189 2192 * node in the device tree (created by the PCI enumerator).
2190 2193 */
2191 2194 static boolean_t
2192 2195 apic_is_ioapic_AMD_813x(uint32_t physaddr)
2193 2196 {
2194 2197 /*
2195 2198 * Look in /ioapics, for the ioapic with
2196 2199 * the physical address given
2197 2200 */
2198 2201 dev_info_t *ioapicsnode = ddi_find_devinfo(IOAPICS_NODE_NAME, -1, 0);
2199 2202 dev_info_t *ioapic_child;
2200 2203 boolean_t rv = B_FALSE;
2201 2204 int vid, did;
2202 2205 uint64_t ioapic_paddr;
2203 2206 boolean_t done = B_FALSE;
2204 2207
2205 2208 if (ioapicsnode == NULL)
2206 2209 return (B_FALSE);
2207 2210
2208 2211 /* Load first child: */
2209 2212 ioapic_child = ddi_get_child(ioapicsnode);
2210 2213 while (!done && ioapic_child != 0) { /* Iterate over children */
2211 2214
2212 2215 if ((ioapic_paddr = (uint64_t)ddi_prop_get_int64(DDI_DEV_T_ANY,
2213 2216 ioapic_child, DDI_PROP_DONTPASS, "reg", 0))
2214 2217 != 0 && physaddr == ioapic_paddr) {
2215 2218
2216 2219 vid = ddi_prop_get_int(DDI_DEV_T_ANY, ioapic_child,
2217 2220 DDI_PROP_DONTPASS, IOAPICS_PROP_VENID, 0);
2218 2221
2219 2222 if (vid == VENID_AMD) {
2220 2223
2221 2224 did = ddi_prop_get_int(DDI_DEV_T_ANY,
2222 2225 ioapic_child, DDI_PROP_DONTPASS,
2223 2226 IOAPICS_PROP_DEVID, 0);
2224 2227
2225 2228 if (did == DEVID_8131_IOAPIC ||
2226 2229 did == DEVID_8132_IOAPIC) {
2227 2230 rv = B_TRUE;
2228 2231 done = B_TRUE;
2229 2232 }
2230 2233 }
2231 2234 }
2232 2235
2233 2236 if (!done)
2234 2237 ioapic_child = ddi_get_next_sibling(ioapic_child);
2235 2238 }
2236 2239
2237 2240 /* The ioapics node was held by ddi_find_devinfo, so release it */
2238 2241 ndi_rele_devi(ioapicsnode);
2239 2242 return (rv);
2240 2243 }
2241 2244
2242 2245 struct apic_state {
2243 2246 int32_t as_task_reg;
2244 2247 int32_t as_dest_reg;
2245 2248 int32_t as_format_reg;
2246 2249 int32_t as_local_timer;
2247 2250 int32_t as_pcint_vect;
2248 2251 int32_t as_int_vect0;
2249 2252 int32_t as_int_vect1;
2250 2253 int32_t as_err_vect;
2251 2254 int32_t as_init_count;
2252 2255 int32_t as_divide_reg;
2253 2256 int32_t as_spur_int_reg;
2254 2257 uint32_t as_ioapic_ids[MAX_IO_APIC];
2255 2258 };
2256 2259
2257 2260
2258 2261 static int
2259 2262 apic_acpi_enter_apicmode(void)
2260 2263 {
2261 2264 ACPI_OBJECT_LIST arglist;
2262 2265 ACPI_OBJECT arg;
2263 2266 ACPI_STATUS status;
2264 2267
2265 2268 /* Setup parameter object */
2266 2269 arglist.Count = 1;
2267 2270 arglist.Pointer = &arg;
2268 2271 arg.Type = ACPI_TYPE_INTEGER;
2269 2272 arg.Integer.Value = ACPI_APIC_MODE;
2270 2273
2271 2274 status = AcpiEvaluateObject(NULL, "\\_PIC", &arglist, NULL);
2272 2275 /*
2273 2276 * Per ACPI spec - section 5.8.1 _PIC Method
2274 2277 * calling the \_PIC control method is optional for the OS
2275 2278 * and might not be found. It's ok to not fail in such cases.
2276 2279 * This is the case on linux KVM and qemu (status AE_NOT_FOUND)
2277 2280 */
2278 2281 if (ACPI_FAILURE(status) && (status != AE_NOT_FOUND)) {
2279 2282 cmn_err(CE_NOTE,
2280 2283 "!apic: Reporting APIC mode failed (via _PIC), err: 0x%x",
2281 2284 ACPI_FAILURE(status));
2282 2285 return (PSM_FAILURE);
2283 2286 } else {
2284 2287 return (PSM_SUCCESS);
2285 2288 }
2286 2289 }
2287 2290
2288 2291
2289 2292 static void
2290 2293 apic_save_state(struct apic_state *sp)
2291 2294 {
2292 2295 int i, cpuid;
2293 2296 ulong_t iflag;
2294 2297
2295 2298 PMD(PMD_SX, ("apic_save_state %p\n", (void *)sp))
2296 2299 /*
2297 2300 * First the local APIC.
2298 2301 */
2299 2302 sp->as_task_reg = apic_reg_ops->apic_get_pri();
2300 2303 sp->as_dest_reg = apic_reg_ops->apic_read(APIC_DEST_REG);
2301 2304 if (apic_mode == LOCAL_APIC)
2302 2305 sp->as_format_reg = apic_reg_ops->apic_read(APIC_FORMAT_REG);
2303 2306 sp->as_local_timer = apic_reg_ops->apic_read(APIC_LOCAL_TIMER);
2304 2307 sp->as_pcint_vect = apic_reg_ops->apic_read(APIC_PCINT_VECT);
2305 2308 sp->as_int_vect0 = apic_reg_ops->apic_read(APIC_INT_VECT0);
2306 2309 sp->as_int_vect1 = apic_reg_ops->apic_read(APIC_INT_VECT1);
2307 2310 sp->as_err_vect = apic_reg_ops->apic_read(APIC_ERR_VECT);
2308 2311 sp->as_init_count = apic_reg_ops->apic_read(APIC_INIT_COUNT);
2309 2312 sp->as_divide_reg = apic_reg_ops->apic_read(APIC_DIVIDE_REG);
2310 2313 sp->as_spur_int_reg = apic_reg_ops->apic_read(APIC_SPUR_INT_REG);
2311 2314
2312 2315 /*
2313 2316 * If on the boot processor then save the IOAPICs' IDs
2314 2317 */
2315 2318 if ((cpuid = psm_get_cpu_id()) == 0) {
2316 2319
2317 2320 iflag = intr_clear();
2318 2321 lock_set(&apic_ioapic_lock);
2319 2322
2320 2323 for (i = 0; i < apic_io_max; i++)
2321 2324 sp->as_ioapic_ids[i] = ioapic_read(i, APIC_ID_CMD);
2322 2325
2323 2326 lock_clear(&apic_ioapic_lock);
2324 2327 intr_restore(iflag);
2325 2328 }
2326 2329
2327 2330 /* apic_state() is currently invoked only in Suspend/Resume */
2328 2331 apic_cpus[cpuid].aci_status |= APIC_CPU_SUSPEND;
2329 2332 }
2330 2333
2331 2334 static void
2332 2335 apic_restore_state(struct apic_state *sp)
2333 2336 {
2334 2337 int i;
2335 2338 ulong_t iflag;
2336 2339
2337 2340 /*
2338 2341 * First the local APIC.
2339 2342 */
2340 2343 apic_reg_ops->apic_write_task_reg(sp->as_task_reg);
2341 2344 if (apic_mode == LOCAL_APIC) {
2342 2345 apic_reg_ops->apic_write(APIC_DEST_REG, sp->as_dest_reg);
2343 2346 apic_reg_ops->apic_write(APIC_FORMAT_REG, sp->as_format_reg);
2344 2347 }
2345 2348 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, sp->as_local_timer);
2346 2349 apic_reg_ops->apic_write(APIC_PCINT_VECT, sp->as_pcint_vect);
2347 2350 apic_reg_ops->apic_write(APIC_INT_VECT0, sp->as_int_vect0);
2348 2351 apic_reg_ops->apic_write(APIC_INT_VECT1, sp->as_int_vect1);
2349 2352 apic_reg_ops->apic_write(APIC_ERR_VECT, sp->as_err_vect);
2350 2353 apic_reg_ops->apic_write(APIC_INIT_COUNT, sp->as_init_count);
2351 2354 apic_reg_ops->apic_write(APIC_DIVIDE_REG, sp->as_divide_reg);
2352 2355 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, sp->as_spur_int_reg);
2353 2356
2354 2357 /*
2355 2358 * the following only needs to be done once, so we do it on the
2356 2359 * boot processor, since we know that we only have one of those
2357 2360 */
2358 2361 if (psm_get_cpu_id() == 0) {
2359 2362
2360 2363 iflag = intr_clear();
2361 2364 lock_set(&apic_ioapic_lock);
2362 2365
2363 2366 /* Restore IOAPICs' APIC IDs */
2364 2367 for (i = 0; i < apic_io_max; i++) {
2365 2368 ioapic_write(i, APIC_ID_CMD, sp->as_ioapic_ids[i]);
2366 2369 }
2367 2370
2368 2371 lock_clear(&apic_ioapic_lock);
2369 2372 intr_restore(iflag);
2370 2373
2371 2374 /*
2372 2375 * Reenter APIC mode before restoring LNK devices
2373 2376 */
2374 2377 (void) apic_acpi_enter_apicmode();
2375 2378
2376 2379 /*
2377 2380 * restore acpi link device mappings
2378 2381 */
2379 2382 acpi_restore_link_devices();
2380 2383 }
2381 2384 }
2382 2385
2383 2386 /*
2384 2387 * Returns 0 on success
2385 2388 */
2386 2389 int
2387 2390 apic_state(psm_state_request_t *rp)
2388 2391 {
2389 2392 PMD(PMD_SX, ("apic_state "))
2390 2393 switch (rp->psr_cmd) {
2391 2394 case PSM_STATE_ALLOC:
2392 2395 rp->req.psm_state_req.psr_state =
2393 2396 kmem_zalloc(sizeof (struct apic_state), KM_NOSLEEP);
2394 2397 if (rp->req.psm_state_req.psr_state == NULL)
2395 2398 return (ENOMEM);
2396 2399 rp->req.psm_state_req.psr_state_size =
2397 2400 sizeof (struct apic_state);
2398 2401 PMD(PMD_SX, (":STATE_ALLOC: state %p, size %lx\n",
2399 2402 rp->req.psm_state_req.psr_state,
2400 2403 rp->req.psm_state_req.psr_state_size))
2401 2404 return (0);
2402 2405
2403 2406 case PSM_STATE_FREE:
2404 2407 kmem_free(rp->req.psm_state_req.psr_state,
2405 2408 rp->req.psm_state_req.psr_state_size);
2406 2409 PMD(PMD_SX, (" STATE_FREE: state %p, size %lx\n",
2407 2410 rp->req.psm_state_req.psr_state,
2408 2411 rp->req.psm_state_req.psr_state_size))
2409 2412 return (0);
2410 2413
2411 2414 case PSM_STATE_SAVE:
2412 2415 PMD(PMD_SX, (" STATE_SAVE: state %p, size %lx\n",
2413 2416 rp->req.psm_state_req.psr_state,
2414 2417 rp->req.psm_state_req.psr_state_size))
2415 2418 apic_save_state(rp->req.psm_state_req.psr_state);
2416 2419 return (0);
2417 2420
2418 2421 case PSM_STATE_RESTORE:
2419 2422 apic_restore_state(rp->req.psm_state_req.psr_state);
2420 2423 PMD(PMD_SX, (" STATE_RESTORE: state %p, size %lx\n",
2421 2424 rp->req.psm_state_req.psr_state,
2422 2425 rp->req.psm_state_req.psr_state_size))
2423 2426 return (0);
2424 2427
2425 2428 default:
2426 2429 return (EINVAL);
2427 2430 }
2428 2431 }
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