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10208 Add x86 features for L1TF
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--- old/usr/src/uts/intel/sys/x86_archext.h
+++ new/usr/src/uts/intel/sys/x86_archext.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
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20 20 */
21 21 /*
22 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 24 */
25 25 /*
26 26 * Copyright (c) 2010, Intel Corporation.
27 27 * All rights reserved.
28 28 */
29 29 /*
30 - * Copyright 2018 Joyent, Inc.
30 + * Copyright (c) 2019, Joyent, Inc.
31 31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
32 32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
33 33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
34 34 * Copyright 2018 Nexenta Systems, Inc.
35 35 */
36 36
37 37 #ifndef _SYS_X86_ARCHEXT_H
38 38 #define _SYS_X86_ARCHEXT_H
39 39
40 40 #if !defined(_ASM)
41 41 #include <sys/regset.h>
42 42 #include <sys/processor.h>
43 43 #include <vm/seg_enum.h>
44 44 #include <vm/page.h>
45 45 #endif /* _ASM */
46 46
47 47 #ifdef __cplusplus
48 48 extern "C" {
49 49 #endif
50 50
51 51 /*
52 52 * cpuid instruction feature flags in %edx (standard function 1)
53 53 */
54 54
55 55 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */
56 56 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */
57 57 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */
58 58 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */
59 59 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */
60 60 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
61 61 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */
62 62 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */
63 63 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
64 64 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */
65 65 /* 0x400 - reserved */
66 66 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */
67 67 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */
68 68 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */
69 69 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */
70 70 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */
71 71 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */
72 72 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
73 73 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */
74 74 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */
75 75 /* 0x100000 - reserved */
76 76 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */
77 77 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */
78 78 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */
79 79 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
80 80 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */
81 81 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */
82 82 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */
83 83 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */
84 84 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */
85 85 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */
86 86 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */
87 87
88 88 /*
89 89 * cpuid instruction feature flags in %ecx (standard function 1)
90 90 */
91 91
92 92 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */
93 93 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */
94 94 #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */
95 95 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */
96 96 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
97 97 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */
98 98 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */
99 99 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */
100 100 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */
101 101 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */
102 102 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */
103 103 /* 0x00000800 - reserved */
104 104 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */
105 105 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */
106 106 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */
107 107 #define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */
108 108 /* 0x00010000 - reserved */
109 109 #define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */
110 110 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */
111 111 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */
112 112 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */
113 113 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */
114 114 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */
115 115 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */
116 116 #define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */
117 117 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */
118 118 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */
119 119 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */
120 120 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
121 121 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */
122 122 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */
123 123 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */
124 124
125 125 /*
126 126 * cpuid instruction feature flags in %edx (extended function 0x80000001)
127 127 */
128 128
129 129 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */
130 130 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */
131 131 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */
132 132 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */
133 133 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */
134 134 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
135 135 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */
136 136 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */
137 137 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
138 138 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */
139 139 /* 0x00000400 - sysc on K6m6 */
140 140 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */
141 141 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */
142 142 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */
143 143 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */
144 144 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */
145 145 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */
146 146 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */
147 147 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
148 148 /* 0x00040000 - reserved */
149 149 /* 0x00080000 - reserved */
150 150 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */
151 151 /* 0x00200000 - reserved */
152 152 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */
153 153 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */
154 154 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
155 155 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */
156 156 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */
157 157 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */
158 158 /* 0x10000000 - reserved */
159 159 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */
160 160 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */
161 161 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */
162 162
163 163 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
164 164 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
165 165 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
166 166 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
167 167 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
168 168 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
169 169 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
170 170 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
171 171 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
172 172 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
173 173 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
174 174 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: Extended AVX */
175 175 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
176 176 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
177 177 /* 0x00004000 - reserved */
178 178 #define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */
179 179 #define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */
180 180 /* 0x00020000 - reserved */
181 181 /* 0x00040000 - reserved */
182 182 #define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */
183 183 /* 0x00100000 - reserved */
184 184 #define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */
185 185 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
186 186
187 187 /*
188 188 * AMD uses %ebx for some of their features (extended function 0x80000008).
189 189 */
190 190 #define CPUID_AMD_EBX_ERR_PTR_ZERO 0x000000004 /* AMD: FP Err. Ptr. Zero */
191 191 #define CPUID_AMD_EBX_IBPB 0x000001000 /* AMD: IBPB */
192 192 #define CPUID_AMD_EBX_IBRS 0x000004000 /* AMD: IBRS */
193 193 #define CPUID_AMD_EBX_STIBP 0x000008000 /* AMD: STIBP */
194 194 #define CPUID_AMD_EBX_IBRS_ALL 0x000010000 /* AMD: Enhanced IBRS */
195 195 #define CPUID_AMD_EBX_STIBP_ALL 0x000020000 /* AMD: STIBP ALL */
196 196 #define CPUID_AMD_EBX_PREFER_IBRS 0x000040000 /* AMD: Don't retpoline */
197 197 #define CPUID_AMD_EBX_SSBD 0x001000000 /* AMD: SSBD */
198 198 #define CPUID_AMD_EBX_VIRT_SSBD 0x002000000 /* AMD: VIRT SSBD */
199 199 #define CPUID_AMD_EBX_SSB_NO 0x004000000 /* AMD: SSB Fixed */
200 200
201 201 /*
202 202 * Intel now seems to have claimed part of the "extended" function
203 203 * space that we previously for non-Intel implementors to use.
204 204 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
205 205 * is available in long mode i.e. what AMD indicate using bit 0.
206 206 * On the other hand, everything else is labelled as reserved.
207 207 */
208 208 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
209 209
210 210 /*
211 211 * Intel also uses cpuid leaf 7 to have additional instructions and features.
212 212 * Like some other leaves, but unlike the current ones we care about, it
213 213 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
214 214 * with the potential use of additional sub-leaves in the future, we now
215 215 * specifically label the EBX features with their leaf and sub-leaf.
216 216 */
217 217 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */
218 218 #define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */
219 219 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */
220 220 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */
221 221 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */
222 222 #define CPUID_INTC_EBX_7_0_INVPCID 0x00000400 /* invpcid instr */
223 223 #define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */
224 224 #define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */
225 225 #define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */
226 226 #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */
227 227 #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */
228 228 #define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */
229 229 #define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */
230 230 #define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */
231 231 #define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */
232 232 #define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */
233 233 #define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */
234 234 #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */
235 235 #define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */
236 236 #define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */
237 237
238 238 #define CPUID_INTC_EBX_7_0_ALL_AVX512 \
239 239 (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \
240 240 CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \
241 241 CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \
242 242 CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL)
243 243
244 244 #define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */
245 245 #define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */
246 246 #define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */
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247 247 #define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */
248 248 #define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */
249 249
250 250 #define CPUID_INTC_ECX_7_0_ALL_AVX512 \
251 251 (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ)
252 252
253 253 #define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */
254 254 #define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */
255 255 #define CPUID_INTC_EDX_7_0_SPEC_CTRL 0x04000000 /* Spec, IBPB, IBRS */
256 256 #define CPUID_INTC_EDX_7_0_STIBP 0x08000000 /* STIBP */
257 +#define CPUID_INTC_EDX_7_0_FLUSH_CMD 0x10000000 /* IA32_FLUSH_CMD */
257 258 #define CPUID_INTC_EDX_7_0_ARCH_CAPS 0x20000000 /* IA32_ARCH_CAPS */
258 259 #define CPUID_INTC_EDX_7_0_SSBD 0x80000000 /* SSBD */
259 260
260 261 #define CPUID_INTC_EDX_7_0_ALL_AVX512 \
261 262 (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS)
262 263
263 264 /*
264 265 * Intel also uses cpuid leaf 0xd to report additional instructions and features
265 266 * when the sub-leaf in %ecx == 1. We label these using the same convention as
266 267 * with leaf 7.
267 268 */
268 269 #define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */
269 270 #define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */
270 271 #define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */
271 272
272 273 #define REG_PAT 0x277
273 274 #define REG_TSC 0x10 /* timestamp counter */
274 275 #define REG_APIC_BASE_MSR 0x1b
275 276 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */
276 277
277 278 #if !defined(__xpv)
278 279 /*
279 280 * AMD C1E
280 281 */
281 282 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055
282 283 #define AMD_ACTONCMPHALT_SHIFT 27
283 284 #define AMD_ACTONCMPHALT_MASK 3
284 285 #endif
285 286
286 287 #define MSR_DEBUGCTL 0x1d9
287 288
288 289 #define DEBUGCTL_LBR 0x01
289 290 #define DEBUGCTL_BTF 0x02
290 291
291 292 /* Intel P6, AMD */
292 293 #define MSR_LBR_FROM 0x1db
293 294 #define MSR_LBR_TO 0x1dc
294 295 #define MSR_LEX_FROM 0x1dd
295 296 #define MSR_LEX_TO 0x1de
296 297
297 298 /* Intel P4 (pre-Prescott, non P4 M) */
298 299 #define MSR_P4_LBSTK_TOS 0x1da
299 300 #define MSR_P4_LBSTK_0 0x1db
300 301 #define MSR_P4_LBSTK_1 0x1dc
301 302 #define MSR_P4_LBSTK_2 0x1dd
302 303 #define MSR_P4_LBSTK_3 0x1de
303 304
304 305 /* Intel Pentium M */
305 306 #define MSR_P6M_LBSTK_TOS 0x1c9
306 307 #define MSR_P6M_LBSTK_0 0x040
307 308 #define MSR_P6M_LBSTK_1 0x041
308 309 #define MSR_P6M_LBSTK_2 0x042
309 310 #define MSR_P6M_LBSTK_3 0x043
310 311 #define MSR_P6M_LBSTK_4 0x044
311 312 #define MSR_P6M_LBSTK_5 0x045
312 313 #define MSR_P6M_LBSTK_6 0x046
313 314 #define MSR_P6M_LBSTK_7 0x047
314 315
315 316 /* Intel P4 (Prescott) */
316 317 #define MSR_PRP4_LBSTK_TOS 0x1da
317 318 #define MSR_PRP4_LBSTK_FROM_0 0x680
318 319 #define MSR_PRP4_LBSTK_FROM_1 0x681
319 320 #define MSR_PRP4_LBSTK_FROM_2 0x682
320 321 #define MSR_PRP4_LBSTK_FROM_3 0x683
321 322 #define MSR_PRP4_LBSTK_FROM_4 0x684
322 323 #define MSR_PRP4_LBSTK_FROM_5 0x685
323 324 #define MSR_PRP4_LBSTK_FROM_6 0x686
324 325 #define MSR_PRP4_LBSTK_FROM_7 0x687
325 326 #define MSR_PRP4_LBSTK_FROM_8 0x688
326 327 #define MSR_PRP4_LBSTK_FROM_9 0x689
327 328 #define MSR_PRP4_LBSTK_FROM_10 0x68a
328 329 #define MSR_PRP4_LBSTK_FROM_11 0x68b
329 330 #define MSR_PRP4_LBSTK_FROM_12 0x68c
330 331 #define MSR_PRP4_LBSTK_FROM_13 0x68d
331 332 #define MSR_PRP4_LBSTK_FROM_14 0x68e
332 333 #define MSR_PRP4_LBSTK_FROM_15 0x68f
333 334 #define MSR_PRP4_LBSTK_TO_0 0x6c0
334 335 #define MSR_PRP4_LBSTK_TO_1 0x6c1
335 336 #define MSR_PRP4_LBSTK_TO_2 0x6c2
336 337 #define MSR_PRP4_LBSTK_TO_3 0x6c3
337 338 #define MSR_PRP4_LBSTK_TO_4 0x6c4
338 339 #define MSR_PRP4_LBSTK_TO_5 0x6c5
339 340 #define MSR_PRP4_LBSTK_TO_6 0x6c6
340 341 #define MSR_PRP4_LBSTK_TO_7 0x6c7
341 342 #define MSR_PRP4_LBSTK_TO_8 0x6c8
342 343 #define MSR_PRP4_LBSTK_TO_9 0x6c9
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343 344 #define MSR_PRP4_LBSTK_TO_10 0x6ca
344 345 #define MSR_PRP4_LBSTK_TO_11 0x6cb
345 346 #define MSR_PRP4_LBSTK_TO_12 0x6cc
346 347 #define MSR_PRP4_LBSTK_TO_13 0x6cd
347 348 #define MSR_PRP4_LBSTK_TO_14 0x6ce
348 349 #define MSR_PRP4_LBSTK_TO_15 0x6cf
349 350
350 351 /*
351 352 * Intel IA32_ARCH_CAPABILITIES MSR.
352 353 */
353 -#define MSR_IA32_ARCH_CAPABILITIES 0x10a
354 -#define IA32_ARCH_CAP_RDCL_NO 0x0001
355 -#define IA32_ARCH_CAP_IBRS_ALL 0x0002
356 -#define IA32_ARCH_CAP_RSBA 0x0004
357 -#define IA32_ARCH_CAP_SSB_NO 0x0010
354 +#define MSR_IA32_ARCH_CAPABILITIES 0x10a
355 +#define IA32_ARCH_CAP_RDCL_NO 0x0001
356 +#define IA32_ARCH_CAP_IBRS_ALL 0x0002
357 +#define IA32_ARCH_CAP_RSBA 0x0004
358 +#define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x0008
359 +#define IA32_ARCH_CAP_SSB_NO 0x0010
358 360
359 361 /*
360 362 * Intel Speculation related MSRs
361 363 */
362 364 #define MSR_IA32_SPEC_CTRL 0x48
363 365 #define IA32_SPEC_CTRL_IBRS 0x01
364 366 #define IA32_SPEC_CTRL_STIBP 0x02
365 367 #define IA32_SPEC_CTRL_SSBD 0x04
366 368
367 369 #define MSR_IA32_PRED_CMD 0x49
368 370 #define IA32_PRED_CMD_IBPB 0x01
369 371
372 +#define MSR_IA32_FLUSH_CMD 0x10b
373 +#define IA32_FLUSH_CMD_L1D 0x01
374 +
370 375 #define MCI_CTL_VALUE 0xffffffff
371 376
372 377 #define MTRR_TYPE_UC 0
373 378 #define MTRR_TYPE_WC 1
374 379 #define MTRR_TYPE_WT 4
375 380 #define MTRR_TYPE_WP 5
376 381 #define MTRR_TYPE_WB 6
377 382 #define MTRR_TYPE_UC_ 7
378 383
379 384 /*
380 385 * For Solaris we set up the page attritubute table in the following way:
381 386 * PAT0 Write-Back
382 387 * PAT1 Write-Through
383 388 * PAT2 Unchacheable-
384 389 * PAT3 Uncacheable
385 390 * PAT4 Write-Back
386 391 * PAT5 Write-Through
387 392 * PAT6 Write-Combine
388 393 * PAT7 Uncacheable
389 394 * The only difference from h/w default is entry 6.
390 395 */
391 396 #define PAT_DEFAULT_ATTRIBUTE \
392 397 ((uint64_t)MTRR_TYPE_WB | \
393 398 ((uint64_t)MTRR_TYPE_WT << 8) | \
394 399 ((uint64_t)MTRR_TYPE_UC_ << 16) | \
395 400 ((uint64_t)MTRR_TYPE_UC << 24) | \
396 401 ((uint64_t)MTRR_TYPE_WB << 32) | \
397 402 ((uint64_t)MTRR_TYPE_WT << 40) | \
398 403 ((uint64_t)MTRR_TYPE_WC << 48) | \
399 404 ((uint64_t)MTRR_TYPE_UC << 56))
400 405
401 406 #define X86FSET_LARGEPAGE 0
402 407 #define X86FSET_TSC 1
403 408 #define X86FSET_MSR 2
404 409 #define X86FSET_MTRR 3
405 410 #define X86FSET_PGE 4
406 411 #define X86FSET_DE 5
407 412 #define X86FSET_CMOV 6
408 413 #define X86FSET_MMX 7
409 414 #define X86FSET_MCA 8
410 415 #define X86FSET_PAE 9
411 416 #define X86FSET_CX8 10
412 417 #define X86FSET_PAT 11
413 418 #define X86FSET_SEP 12
414 419 #define X86FSET_SSE 13
415 420 #define X86FSET_SSE2 14
416 421 #define X86FSET_HTT 15
417 422 #define X86FSET_ASYSC 16
418 423 #define X86FSET_NX 17
419 424 #define X86FSET_SSE3 18
420 425 #define X86FSET_CX16 19
421 426 #define X86FSET_CMP 20
422 427 #define X86FSET_TSCP 21
423 428 #define X86FSET_MWAIT 22
424 429 #define X86FSET_SSE4A 23
425 430 #define X86FSET_CPUID 24
426 431 #define X86FSET_SSSE3 25
427 432 #define X86FSET_SSE4_1 26
428 433 #define X86FSET_SSE4_2 27
429 434 #define X86FSET_1GPG 28
430 435 #define X86FSET_CLFSH 29
431 436 #define X86FSET_64 30
432 437 #define X86FSET_AES 31
433 438 #define X86FSET_PCLMULQDQ 32
434 439 #define X86FSET_XSAVE 33
435 440 #define X86FSET_AVX 34
436 441 #define X86FSET_VMX 35
437 442 #define X86FSET_SVM 36
438 443 #define X86FSET_TOPOEXT 37
439 444 #define X86FSET_F16C 38
440 445 #define X86FSET_RDRAND 39
441 446 #define X86FSET_X2APIC 40
442 447 #define X86FSET_AVX2 41
443 448 #define X86FSET_BMI1 42
444 449 #define X86FSET_BMI2 43
445 450 #define X86FSET_FMA 44
446 451 #define X86FSET_SMEP 45
447 452 #define X86FSET_SMAP 46
448 453 #define X86FSET_ADX 47
449 454 #define X86FSET_RDSEED 48
450 455 #define X86FSET_MPX 49
451 456 #define X86FSET_AVX512F 50
452 457 #define X86FSET_AVX512DQ 51
453 458 #define X86FSET_AVX512PF 52
454 459 #define X86FSET_AVX512ER 53
455 460 #define X86FSET_AVX512CD 54
456 461 #define X86FSET_AVX512BW 55
457 462 #define X86FSET_AVX512VL 56
458 463 #define X86FSET_AVX512FMA 57
459 464 #define X86FSET_AVX512VBMI 58
460 465 #define X86FSET_AVX512VPOPCDQ 59
461 466 #define X86FSET_AVX512NNIW 60
462 467 #define X86FSET_AVX512FMAPS 61
463 468 #define X86FSET_XSAVEOPT 62
464 469 #define X86FSET_XSAVEC 63
465 470 #define X86FSET_XSAVES 64
466 471 #define X86FSET_SHA 65
467 472 #define X86FSET_UMIP 66
468 473 #define X86FSET_PKU 67
469 474 #define X86FSET_OSPKE 68
470 475 #define X86FSET_PCID 69
471 476 #define X86FSET_INVPCID 70
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472 477 #define X86FSET_IBRS 71
473 478 #define X86FSET_IBPB 72
474 479 #define X86FSET_STIBP 73
475 480 #define X86FSET_SSBD 74
476 481 #define X86FSET_SSBD_VIRT 75
477 482 #define X86FSET_RDCL_NO 76
478 483 #define X86FSET_IBRS_ALL 77
479 484 #define X86FSET_RSBA 78
480 485 #define X86FSET_SSB_NO 79
481 486 #define X86FSET_STIBP_ALL 80
487 +#define X86FSET_FLUSH_CMD 81
488 +#define X86FSET_L1D_VM_NO 82
482 489
483 490 /*
484 491 * Intel Deep C-State invariant TSC in leaf 0x80000007.
485 492 */
486 493 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
487 494
488 495 /*
489 496 * Intel Deep C-state always-running local APIC timer
490 497 */
491 498 #define CPUID_CSTATE_ARAT (0x4)
492 499
493 500 /*
494 501 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3].
495 502 */
496 503 #define CPUID_EPB_SUPPORT (1 << 3)
497 504
498 505 /*
499 506 * Intel TSC deadline timer
500 507 */
501 508 #define CPUID_DEADLINE_TSC (1 << 24)
502 509
503 510 /*
504 511 * x86_type is a legacy concept; this is supplanted
505 512 * for most purposes by x86_featureset; modern CPUs
506 513 * should be X86_TYPE_OTHER
507 514 */
508 515 #define X86_TYPE_OTHER 0
509 516 #define X86_TYPE_486 1
510 517 #define X86_TYPE_P5 2
511 518 #define X86_TYPE_P6 3
512 519 #define X86_TYPE_CYRIX_486 4
513 520 #define X86_TYPE_CYRIX_6x86L 5
514 521 #define X86_TYPE_CYRIX_6x86 6
515 522 #define X86_TYPE_CYRIX_GXm 7
516 523 #define X86_TYPE_CYRIX_6x86MX 8
517 524 #define X86_TYPE_CYRIX_MediaGX 9
518 525 #define X86_TYPE_CYRIX_MII 10
519 526 #define X86_TYPE_VIA_CYRIX_III 11
520 527 #define X86_TYPE_P4 12
521 528
522 529 /*
523 530 * x86_vendor allows us to select between
524 531 * implementation features and helps guide
525 532 * the interpretation of the cpuid instruction.
526 533 */
527 534 #define X86_VENDOR_Intel 0
528 535 #define X86_VENDORSTR_Intel "GenuineIntel"
529 536
530 537 #define X86_VENDOR_IntelClone 1
531 538
532 539 #define X86_VENDOR_AMD 2
533 540 #define X86_VENDORSTR_AMD "AuthenticAMD"
534 541
535 542 #define X86_VENDOR_Cyrix 3
536 543 #define X86_VENDORSTR_CYRIX "CyrixInstead"
537 544
538 545 #define X86_VENDOR_UMC 4
539 546 #define X86_VENDORSTR_UMC "UMC UMC UMC "
540 547
541 548 #define X86_VENDOR_NexGen 5
542 549 #define X86_VENDORSTR_NexGen "NexGenDriven"
543 550
544 551 #define X86_VENDOR_Centaur 6
545 552 #define X86_VENDORSTR_Centaur "CentaurHauls"
546 553
547 554 #define X86_VENDOR_Rise 7
548 555 #define X86_VENDORSTR_Rise "RiseRiseRise"
549 556
550 557 #define X86_VENDOR_SiS 8
551 558 #define X86_VENDORSTR_SiS "SiS SiS SiS "
552 559
553 560 #define X86_VENDOR_TM 9
554 561 #define X86_VENDORSTR_TM "GenuineTMx86"
555 562
556 563 #define X86_VENDOR_NSC 10
557 564 #define X86_VENDORSTR_NSC "Geode by NSC"
558 565
559 566 /*
560 567 * Vendor string max len + \0
561 568 */
562 569 #define X86_VENDOR_STRLEN 13
563 570
564 571 /*
565 572 * Some vendor/family/model/stepping ranges are commonly grouped under
566 573 * a single identifying banner by the vendor. The following encode
567 574 * that "revision" in a uint32_t with the 8 most significant bits
568 575 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the
569 576 * family, and the remaining 16 typically forming a bitmask of revisions
570 577 * within that family with more significant bits indicating "later" revisions.
571 578 */
572 579
573 580 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u
574 581 #define _X86_CHIPREV_VENDOR_SHIFT 24
575 582 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u
576 583 #define _X86_CHIPREV_FAMILY_SHIFT 16
577 584 #define _X86_CHIPREV_REV_MASK 0x0000ffffu
578 585
579 586 #define _X86_CHIPREV_VENDOR(x) \
580 587 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT)
581 588 #define _X86_CHIPREV_FAMILY(x) \
582 589 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT)
583 590 #define _X86_CHIPREV_REV(x) \
584 591 ((x) & _X86_CHIPREV_REV_MASK)
585 592
586 593 /* True if x matches in vendor and family and if x matches the given rev mask */
587 594 #define X86_CHIPREV_MATCH(x, mask) \
588 595 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \
589 596 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \
590 597 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0))
591 598
592 599 /* True if x matches in vendor and family, and rev is at least minx */
593 600 #define X86_CHIPREV_ATLEAST(x, minx) \
594 601 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
595 602 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \
596 603 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx))
597 604
598 605 #define _X86_CHIPREV_MKREV(vendor, family, rev) \
599 606 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \
600 607 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev))
601 608
602 609 /* True if x matches in vendor, and family is at least minx */
603 610 #define X86_CHIPFAM_ATLEAST(x, minx) \
604 611 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
605 612 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx))
606 613
607 614 /* Revision default */
608 615 #define X86_CHIPREV_UNKNOWN 0x0
609 616
610 617 /*
611 618 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are
612 619 * sufficiently different that we will distinguish them; in all other
613 620 * case we will identify the major revision.
614 621 */
615 622 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001)
616 623 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002)
617 624 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004)
618 625 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008)
619 626 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010)
620 627 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020)
621 628 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040)
622 629
623 630 /*
624 631 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only.
625 632 */
626 633 #define X86_CHIPREV_AMD_10_REV_A \
627 634 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001)
628 635 #define X86_CHIPREV_AMD_10_REV_B \
629 636 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002)
630 637 #define X86_CHIPREV_AMD_10_REV_C2 \
631 638 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004)
632 639 #define X86_CHIPREV_AMD_10_REV_C3 \
633 640 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008)
634 641 #define X86_CHIPREV_AMD_10_REV_D0 \
635 642 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010)
636 643 #define X86_CHIPREV_AMD_10_REV_D1 \
637 644 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020)
638 645 #define X86_CHIPREV_AMD_10_REV_E \
639 646 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040)
640 647
641 648 /*
642 649 * Definitions for AMD Family 0x11.
643 650 */
644 651 #define X86_CHIPREV_AMD_11_REV_B \
645 652 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002)
646 653
647 654 /*
648 655 * Definitions for AMD Family 0x12.
649 656 */
650 657 #define X86_CHIPREV_AMD_12_REV_B \
651 658 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002)
652 659
653 660 /*
654 661 * Definitions for AMD Family 0x14.
655 662 */
656 663 #define X86_CHIPREV_AMD_14_REV_B \
657 664 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002)
658 665 #define X86_CHIPREV_AMD_14_REV_C \
659 666 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004)
660 667
661 668 /*
662 669 * Definitions for AMD Family 0x15
663 670 */
664 671 #define X86_CHIPREV_AMD_15OR_REV_B2 \
665 672 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001)
666 673
667 674 #define X86_CHIPREV_AMD_15TN_REV_A1 \
668 675 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002)
669 676
670 677 /*
671 678 * Various socket/package types, extended as the need to distinguish
672 679 * a new type arises. The top 8 byte identfies the vendor and the
673 680 * remaining 24 bits describe 24 socket types.
674 681 */
675 682
676 683 #define _X86_SOCKET_VENDOR_SHIFT 24
677 684 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT)
678 685 #define _X86_SOCKET_TYPE_MASK 0x00ffffff
679 686 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK)
680 687
681 688 #define _X86_SOCKET_MKVAL(vendor, bitval) \
682 689 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval))
683 690
684 691 #define X86_SOCKET_MATCH(s, mask) \
685 692 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \
686 693 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0)
687 694
688 695 #define X86_SOCKET_UNKNOWN 0x0
689 696 /*
690 697 * AMD socket types
691 698 */
692 699 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001)
693 700 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002)
694 701 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004)
695 702 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008)
696 703 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010)
697 704 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020)
698 705 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040)
699 706 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080)
700 707 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100)
701 708 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200)
702 709 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400)
703 710 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800)
704 711 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000)
705 712 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000)
706 713 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000)
707 714 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000)
708 715 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000)
709 716 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000)
710 717 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000)
711 718 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000)
712 719 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000)
713 720 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000)
714 721
715 722 /*
716 723 * xgetbv/xsetbv support
717 724 * See section 13.3 in vol. 1 of the Intel devlopers manual.
718 725 */
719 726
720 727 #define XFEATURE_ENABLED_MASK 0x0
721 728 /*
722 729 * XFEATURE_ENABLED_MASK values (eax)
723 730 * See setup_xfem().
724 731 */
725 732 #define XFEATURE_LEGACY_FP 0x1
726 733 #define XFEATURE_SSE 0x2
727 734 #define XFEATURE_AVX 0x4
728 735 #define XFEATURE_MPX 0x18 /* 2 bits, both 0 or 1 */
729 736 #define XFEATURE_AVX512 0xe0 /* 3 bits, all 0 or 1 */
730 737 /* bit 8 unused */
731 738 #define XFEATURE_PKRU 0x200
732 739 #define XFEATURE_FP_ALL \
733 740 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \
734 741 XFEATURE_AVX512 | XFEATURE_PKRU)
735 742
736 743 /*
737 744 * Define the set of xfeature flags that should be considered valid in the xsave
738 745 * state vector when we initialize an lwp. This is distinct from the full set so
739 746 * that all of the processor's normal logic and tracking of the xsave state is
740 747 * usable. This should correspond to the state that's been initialized by the
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741 748 * ABI to hold meaningful values. Adding additional bits here can have serious
742 749 * performance implications and cause performance degradations when using the
743 750 * FPU vector (xmm) registers.
744 751 */
745 752 #define XFEATURE_FP_INITIAL (XFEATURE_LEGACY_FP | XFEATURE_SSE)
746 753
747 754 #if !defined(_ASM)
748 755
749 756 #if defined(_KERNEL) || defined(_KMEMUSER)
750 757
751 -#define NUM_X86_FEATURES 81
758 +#define NUM_X86_FEATURES 83
752 759 extern uchar_t x86_featureset[];
753 760
754 761 extern void free_x86_featureset(void *featureset);
755 762 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
756 763 extern void add_x86_feature(void *featureset, uint_t feature);
757 764 extern void remove_x86_feature(void *featureset, uint_t feature);
758 765 extern boolean_t compare_x86_featureset(void *setA, void *setB);
759 766 extern void print_x86_featureset(void *featureset);
760 767
761 768
762 769 extern uint_t x86_type;
763 770 extern uint_t x86_vendor;
764 771 extern uint_t x86_clflush_size;
765 772
766 773 extern uint_t pentiumpro_bug4046376;
767 774
768 775 extern const char CyrixInstead[];
769 776
770 777 #endif
771 778
772 779 #if defined(_KERNEL)
773 780
774 781 /*
775 782 * This structure is used to pass arguments and get return values back
776 783 * from the CPUID instruction in __cpuid_insn() routine.
777 784 */
778 785 struct cpuid_regs {
779 786 uint32_t cp_eax;
780 787 uint32_t cp_ebx;
781 788 uint32_t cp_ecx;
782 789 uint32_t cp_edx;
783 790 };
784 791
785 792 extern int x86_use_pcid;
786 793 extern int x86_use_invpcid;
787 794
788 795 /*
789 796 * Utility functions to get/set extended control registers (XCR)
790 797 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
791 798 */
792 799 extern uint64_t get_xcr(uint_t);
793 800 extern void set_xcr(uint_t, uint64_t);
794 801
795 802 extern uint64_t rdmsr(uint_t);
796 803 extern void wrmsr(uint_t, const uint64_t);
797 804 extern uint64_t xrdmsr(uint_t);
798 805 extern void xwrmsr(uint_t, const uint64_t);
799 806 extern int checked_rdmsr(uint_t, uint64_t *);
800 807 extern int checked_wrmsr(uint_t, uint64_t);
801 808
802 809 extern void invalidate_cache(void);
803 810 extern ulong_t getcr4(void);
804 811 extern void setcr4(ulong_t);
805 812
806 813 extern void mtrr_sync(void);
807 814
808 815 extern void cpu_fast_syscall_enable(void);
809 816 extern void cpu_fast_syscall_disable(void);
810 817
811 818 struct cpu;
812 819
813 820 extern int cpuid_checkpass(struct cpu *, int);
814 821 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *);
815 822 extern uint32_t __cpuid_insn(struct cpuid_regs *);
816 823 extern int cpuid_getbrandstr(struct cpu *, char *, size_t);
817 824 extern int cpuid_getidstr(struct cpu *, char *, size_t);
818 825 extern const char *cpuid_getvendorstr(struct cpu *);
819 826 extern uint_t cpuid_getvendor(struct cpu *);
820 827 extern uint_t cpuid_getfamily(struct cpu *);
821 828 extern uint_t cpuid_getmodel(struct cpu *);
822 829 extern uint_t cpuid_getstep(struct cpu *);
823 830 extern uint_t cpuid_getsig(struct cpu *);
824 831 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *);
825 832 extern uint_t cpuid_get_ncore_per_chip(struct cpu *);
826 833 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *);
827 834 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *);
828 835 extern int cpuid_get_chipid(struct cpu *);
829 836 extern id_t cpuid_get_coreid(struct cpu *);
830 837 extern int cpuid_get_pkgcoreid(struct cpu *);
831 838 extern int cpuid_get_clogid(struct cpu *);
832 839 extern int cpuid_get_cacheid(struct cpu *);
833 840 extern uint32_t cpuid_get_apicid(struct cpu *);
834 841 extern uint_t cpuid_get_procnodeid(struct cpu *cpu);
835 842 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu);
836 843 extern uint_t cpuid_get_compunitid(struct cpu *cpu);
837 844 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu);
838 845 extern size_t cpuid_get_xsave_size();
839 846 extern boolean_t cpuid_need_fp_excp_handling();
840 847 extern int cpuid_is_cmt(struct cpu *);
841 848 extern int cpuid_syscall32_insn(struct cpu *);
842 849 extern int getl2cacheinfo(struct cpu *, int *, int *, int *);
843 850
844 851 extern uint32_t cpuid_getchiprev(struct cpu *);
845 852 extern const char *cpuid_getchiprevstr(struct cpu *);
846 853 extern uint32_t cpuid_getsockettype(struct cpu *);
847 854 extern const char *cpuid_getsocketstr(struct cpu *);
848 855
849 856 extern int cpuid_have_cr8access(struct cpu *);
850 857
851 858 extern int cpuid_opteron_erratum(struct cpu *, uint_t);
852 859
853 860 struct cpuid_info;
854 861
855 862 extern void setx86isalist(void);
856 863 extern void cpuid_alloc_space(struct cpu *);
857 864 extern void cpuid_free_space(struct cpu *);
858 865 extern void cpuid_pass1(struct cpu *, uchar_t *);
859 866 extern void cpuid_pass2(struct cpu *);
860 867 extern void cpuid_pass3(struct cpu *);
861 868 extern void cpuid_pass4(struct cpu *, uint_t *);
862 869 extern void cpuid_set_cpu_properties(void *, processorid_t,
863 870 struct cpuid_info *);
864 871 extern void cpuid_pass_ucode(struct cpu *, uchar_t *);
865 872 extern void cpuid_post_ucodeadm(void);
866 873
867 874 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *);
868 875 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t);
869 876
870 877 #if !defined(__xpv)
871 878 extern uint32_t *cpuid_mwait_alloc(struct cpu *);
872 879 extern void cpuid_mwait_free(struct cpu *);
873 880 extern int cpuid_deep_cstates_supported(void);
874 881 extern int cpuid_arat_supported(void);
875 882 extern int cpuid_iepb_supported(struct cpu *);
876 883 extern int cpuid_deadline_tsc_supported(void);
877 884 extern void vmware_port(int, uint32_t *);
878 885 #endif
879 886
880 887 struct cpu_ucode_info;
881 888
882 889 extern void ucode_alloc_space(struct cpu *);
883 890 extern void ucode_free_space(struct cpu *);
884 891 extern void ucode_check(struct cpu *);
885 892 extern void ucode_cleanup();
886 893
887 894 #if !defined(__xpv)
888 895 extern char _tsc_mfence_start;
889 896 extern char _tsc_mfence_end;
890 897 extern char _tscp_start;
891 898 extern char _tscp_end;
892 899 extern char _no_rdtsc_start;
893 900 extern char _no_rdtsc_end;
894 901 extern char _tsc_lfence_start;
895 902 extern char _tsc_lfence_end;
896 903 #endif
897 904
898 905 #if !defined(__xpv)
899 906 extern char bcopy_patch_start;
900 907 extern char bcopy_patch_end;
901 908 extern char bcopy_ck_size;
902 909 #endif
903 910
904 911 extern void post_startup_cpu_fixups(void);
905 912
906 913 extern uint_t workaround_errata(struct cpu *);
907 914
908 915 #if defined(OPTERON_ERRATUM_93)
909 916 extern int opteron_erratum_93;
910 917 #endif
911 918
912 919 #if defined(OPTERON_ERRATUM_91)
913 920 extern int opteron_erratum_91;
914 921 #endif
915 922
916 923 #if defined(OPTERON_ERRATUM_100)
917 924 extern int opteron_erratum_100;
918 925 #endif
919 926
920 927 #if defined(OPTERON_ERRATUM_121)
921 928 extern int opteron_erratum_121;
922 929 #endif
923 930
924 931 #if defined(OPTERON_WORKAROUND_6323525)
925 932 extern int opteron_workaround_6323525;
926 933 extern void patch_workaround_6323525(void);
927 934 #endif
928 935
929 936 #if !defined(__xpv)
930 937 extern void determine_platform(void);
931 938 #endif
932 939 extern int get_hwenv(void);
933 940 extern int is_controldom(void);
934 941
935 942 extern void enable_pcid(void);
936 943
937 944 extern void xsave_setup_msr(struct cpu *);
938 945
939 946 #if !defined(__xpv)
940 947 extern void reset_gdtr_limit(void);
941 948 #endif
942 949
943 950 /*
944 951 * Hypervisor signatures
945 952 */
946 953 #define HVSIG_XEN_HVM "XenVMMXenVMM"
947 954 #define HVSIG_VMWARE "VMwareVMware"
948 955 #define HVSIG_KVM "KVMKVMKVM"
949 956 #define HVSIG_MICROSOFT "Microsoft Hv"
950 957 #define HVSIG_BHYVE "bhyve bhyve "
951 958
952 959 /*
953 960 * Defined hardware environments
954 961 */
955 962 #define HW_NATIVE (1 << 0) /* Running on bare metal */
956 963 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */
957 964
958 965 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */
959 966 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */
960 967 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */
961 968 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */
962 969 #define HW_BHYVE (1 << 6) /* Running on bhyve hypervisor */
963 970
964 971 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT | \
965 972 HW_BHYVE)
966 973
967 974 #endif /* _KERNEL */
968 975
969 976 #endif /* !_ASM */
970 977
971 978 /*
972 979 * VMware hypervisor related defines
973 980 */
974 981 #define VMWARE_HVMAGIC 0x564d5868
975 982 #define VMWARE_HVPORT 0x5658
976 983 #define VMWARE_HVCMD_GETVERSION 0x0a
977 984 #define VMWARE_HVCMD_GETTSCFREQ 0x2d
978 985
979 986 #ifdef __cplusplus
980 987 }
981 988 #endif
982 989
983 990 #endif /* _SYS_X86_ARCHEXT_H */
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