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10208 Add x86 features for L1TF
*** 25,35 ****
/*
* Copyright (c) 2010, Intel Corporation.
* All rights reserved.
*/
/*
! * Copyright 2018 Joyent, Inc.
* Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
* Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
* Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
* Copyright 2018 Nexenta Systems, Inc.
*/
--- 25,35 ----
/*
* Copyright (c) 2010, Intel Corporation.
* All rights reserved.
*/
/*
! * Copyright (c) 2019, Joyent, Inc.
* Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
* Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
* Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
* Copyright 2018 Nexenta Systems, Inc.
*/
*** 252,261 ****
--- 252,262 ----
#define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */
#define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */
#define CPUID_INTC_EDX_7_0_SPEC_CTRL 0x04000000 /* Spec, IBPB, IBRS */
#define CPUID_INTC_EDX_7_0_STIBP 0x08000000 /* STIBP */
+ #define CPUID_INTC_EDX_7_0_FLUSH_CMD 0x10000000 /* IA32_FLUSH_CMD */
#define CPUID_INTC_EDX_7_0_ARCH_CAPS 0x20000000 /* IA32_ARCH_CAPS */
#define CPUID_INTC_EDX_7_0_SSBD 0x80000000 /* SSBD */
#define CPUID_INTC_EDX_7_0_ALL_AVX512 \
(CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS)
*** 352,361 ****
--- 353,363 ----
*/
#define MSR_IA32_ARCH_CAPABILITIES 0x10a
#define IA32_ARCH_CAP_RDCL_NO 0x0001
#define IA32_ARCH_CAP_IBRS_ALL 0x0002
#define IA32_ARCH_CAP_RSBA 0x0004
+ #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x0008
#define IA32_ARCH_CAP_SSB_NO 0x0010
/*
* Intel Speculation related MSRs
*/
*** 365,374 ****
--- 367,379 ----
#define IA32_SPEC_CTRL_SSBD 0x04
#define MSR_IA32_PRED_CMD 0x49
#define IA32_PRED_CMD_IBPB 0x01
+ #define MSR_IA32_FLUSH_CMD 0x10b
+ #define IA32_FLUSH_CMD_L1D 0x01
+
#define MCI_CTL_VALUE 0xffffffff
#define MTRR_TYPE_UC 0
#define MTRR_TYPE_WC 1
#define MTRR_TYPE_WT 4
*** 477,486 ****
--- 482,493 ----
#define X86FSET_RDCL_NO 76
#define X86FSET_IBRS_ALL 77
#define X86FSET_RSBA 78
#define X86FSET_SSB_NO 79
#define X86FSET_STIBP_ALL 80
+ #define X86FSET_FLUSH_CMD 81
+ #define X86FSET_L1D_VM_NO 82
/*
* Intel Deep C-State invariant TSC in leaf 0x80000007.
*/
#define CPUID_TSC_CSTATE_INVARIANCE (0x100)
*** 746,756 ****
#if !defined(_ASM)
#if defined(_KERNEL) || defined(_KMEMUSER)
! #define NUM_X86_FEATURES 81
extern uchar_t x86_featureset[];
extern void free_x86_featureset(void *featureset);
extern boolean_t is_x86_feature(void *featureset, uint_t feature);
extern void add_x86_feature(void *featureset, uint_t feature);
--- 753,763 ----
#if !defined(_ASM)
#if defined(_KERNEL) || defined(_KMEMUSER)
! #define NUM_X86_FEATURES 83
extern uchar_t x86_featureset[];
extern void free_x86_featureset(void *featureset);
extern boolean_t is_x86_feature(void *featureset, uint_t feature);
extern void add_x86_feature(void *featureset, uint_t feature);