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10208 Add x86 features for L1TF
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--- old/usr/src/uts/i86pc/os/cpuid.c
+++ new/usr/src/uts/i86pc/os/cpuid.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 * Copyright (c) 2011, 2016 by Delphix. All rights reserved.
24 24 * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
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25 25 * Copyright 2014 Josef "Jeff" Sipek <jeffpc@josefsipek.net>
26 26 */
27 27 /*
28 28 * Copyright (c) 2010, Intel Corporation.
29 29 * All rights reserved.
30 30 */
31 31 /*
32 32 * Portions Copyright 2009 Advanced Micro Devices, Inc.
33 33 */
34 34 /*
35 - * Copyright 2018 Joyent, Inc.
35 + * Copyright (c) 2019, Joyent, Inc.
36 36 */
37 37 /*
38 38 * Various routines to handle identification
39 39 * and classification of x86 processors.
40 40 */
41 41
42 42 #include <sys/types.h>
43 43 #include <sys/archsystm.h>
44 44 #include <sys/x86_archext.h>
45 45 #include <sys/kmem.h>
46 46 #include <sys/systm.h>
47 47 #include <sys/cmn_err.h>
48 48 #include <sys/sunddi.h>
49 49 #include <sys/sunndi.h>
50 50 #include <sys/cpuvar.h>
51 51 #include <sys/processor.h>
52 52 #include <sys/sysmacros.h>
53 53 #include <sys/pg.h>
54 54 #include <sys/fp.h>
55 55 #include <sys/controlregs.h>
56 56 #include <sys/bitmap.h>
57 57 #include <sys/auxv_386.h>
58 58 #include <sys/memnode.h>
59 59 #include <sys/pci_cfgspace.h>
60 60 #include <sys/comm_page.h>
61 61 #include <sys/mach_mmu.h>
62 62 #include <sys/ucode.h>
63 63 #include <sys/tsc.h>
64 64
65 65 #ifdef __xpv
66 66 #include <sys/hypervisor.h>
67 67 #else
68 68 #include <sys/ontrap.h>
69 69 #endif
70 70
71 71 /*
72 72 * Pass 0 of cpuid feature analysis happens in locore. It contains special code
73 73 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with
74 74 * them accordingly. For most modern processors, feature detection occurs here
75 75 * in pass 1.
76 76 *
77 77 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup()
78 78 * for the boot CPU and does the basic analysis that the early kernel needs.
79 79 * x86_featureset is set based on the return value of cpuid_pass1() of the boot
80 80 * CPU.
81 81 *
82 82 * Pass 1 includes:
83 83 *
84 84 * o Determining vendor/model/family/stepping and setting x86_type and
85 85 * x86_vendor accordingly.
86 86 * o Processing the feature flags returned by the cpuid instruction while
87 87 * applying any workarounds or tricks for the specific processor.
88 88 * o Mapping the feature flags into illumos feature bits (X86_*).
89 89 * o Processing extended feature flags if supported by the processor,
90 90 * again while applying specific processor knowledge.
91 91 * o Determining the CMT characteristics of the system.
92 92 *
93 93 * Pass 1 is done on non-boot CPUs during their initialization and the results
94 94 * are used only as a meager attempt at ensuring that all processors within the
95 95 * system support the same features.
96 96 *
97 97 * Pass 2 of cpuid feature analysis happens just at the beginning
98 98 * of startup(). It just copies in and corrects the remainder
99 99 * of the cpuid data we depend on: standard cpuid functions that we didn't
100 100 * need for pass1 feature analysis, and extended cpuid functions beyond the
101 101 * simple feature processing done in pass1.
102 102 *
103 103 * Pass 3 of cpuid analysis is invoked after basic kernel services; in
104 104 * particular kernel memory allocation has been made available. It creates a
105 105 * readable brand string based on the data collected in the first two passes.
106 106 *
107 107 * Pass 4 of cpuid analysis is invoked after post_startup() when all
108 108 * the support infrastructure for various hardware features has been
109 109 * initialized. It determines which processor features will be reported
110 110 * to userland via the aux vector.
111 111 *
112 112 * All passes are executed on all CPUs, but only the boot CPU determines what
113 113 * features the kernel will use.
114 114 *
115 115 * Much of the worst junk in this file is for the support of processors
116 116 * that didn't really implement the cpuid instruction properly.
117 117 *
118 118 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon,
119 119 * the pass numbers. Accordingly, changes to the pass code may require changes
120 120 * to the accessor code.
121 121 */
122 122
123 123 uint_t x86_vendor = X86_VENDOR_IntelClone;
124 124 uint_t x86_type = X86_TYPE_OTHER;
125 125 uint_t x86_clflush_size = 0;
126 126
127 127 #if defined(__xpv)
128 128 int x86_use_pcid = 0;
129 129 int x86_use_invpcid = 0;
130 130 #else
131 131 int x86_use_pcid = -1;
132 132 int x86_use_invpcid = -1;
133 133 #endif
134 134
135 135 uint_t pentiumpro_bug4046376;
136 136
137 137 uchar_t x86_featureset[BT_SIZEOFMAP(NUM_X86_FEATURES)];
138 138
139 139 static char *x86_feature_names[NUM_X86_FEATURES] = {
140 140 "lgpg",
141 141 "tsc",
142 142 "msr",
143 143 "mtrr",
144 144 "pge",
145 145 "de",
146 146 "cmov",
147 147 "mmx",
148 148 "mca",
149 149 "pae",
150 150 "cv8",
151 151 "pat",
152 152 "sep",
153 153 "sse",
154 154 "sse2",
155 155 "htt",
156 156 "asysc",
157 157 "nx",
158 158 "sse3",
159 159 "cx16",
160 160 "cmp",
161 161 "tscp",
162 162 "mwait",
163 163 "sse4a",
164 164 "cpuid",
165 165 "ssse3",
166 166 "sse4_1",
167 167 "sse4_2",
168 168 "1gpg",
169 169 "clfsh",
170 170 "64",
171 171 "aes",
172 172 "pclmulqdq",
173 173 "xsave",
174 174 "avx",
175 175 "vmx",
176 176 "svm",
177 177 "topoext",
178 178 "f16c",
179 179 "rdrand",
180 180 "x2apic",
181 181 "avx2",
182 182 "bmi1",
183 183 "bmi2",
184 184 "fma",
185 185 "smep",
186 186 "smap",
187 187 "adx",
188 188 "rdseed",
189 189 "mpx",
190 190 "avx512f",
191 191 "avx512dq",
192 192 "avx512pf",
193 193 "avx512er",
194 194 "avx512cd",
195 195 "avx512bw",
196 196 "avx512vl",
197 197 "avx512fma",
198 198 "avx512vbmi",
199 199 "avx512_vpopcntdq",
200 200 "avx512_4vnniw",
201 201 "avx512_4fmaps",
202 202 "xsaveopt",
203 203 "xsavec",
204 204 "xsaves",
205 205 "sha",
206 206 "umip",
207 207 "pku",
208 208 "ospke",
209 209 "pcid",
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210 210 "invpcid",
211 211 "ibrs",
212 212 "ibpb",
213 213 "stibp",
214 214 "ssbd",
215 215 "ssbd_virt",
216 216 "rdcl_no",
217 217 "ibrs_all",
218 218 "rsba",
219 219 "ssb_no",
220 - "stibp_all"
220 + "stibp_all",
221 + "flush_cmd",
222 + "l1d_vmentry_no"
221 223 };
222 224
223 225 boolean_t
224 226 is_x86_feature(void *featureset, uint_t feature)
225 227 {
226 228 ASSERT(feature < NUM_X86_FEATURES);
227 229 return (BT_TEST((ulong_t *)featureset, feature));
228 230 }
229 231
230 232 void
231 233 add_x86_feature(void *featureset, uint_t feature)
232 234 {
233 235 ASSERT(feature < NUM_X86_FEATURES);
234 236 BT_SET((ulong_t *)featureset, feature);
235 237 }
236 238
237 239 void
238 240 remove_x86_feature(void *featureset, uint_t feature)
239 241 {
240 242 ASSERT(feature < NUM_X86_FEATURES);
241 243 BT_CLEAR((ulong_t *)featureset, feature);
242 244 }
243 245
244 246 boolean_t
245 247 compare_x86_featureset(void *setA, void *setB)
246 248 {
247 249 /*
248 250 * We assume that the unused bits of the bitmap are always zero.
249 251 */
250 252 if (memcmp(setA, setB, BT_SIZEOFMAP(NUM_X86_FEATURES)) == 0) {
251 253 return (B_TRUE);
252 254 } else {
253 255 return (B_FALSE);
254 256 }
255 257 }
256 258
257 259 void
258 260 print_x86_featureset(void *featureset)
259 261 {
260 262 uint_t i;
261 263
262 264 for (i = 0; i < NUM_X86_FEATURES; i++) {
263 265 if (is_x86_feature(featureset, i)) {
264 266 cmn_err(CE_CONT, "?x86_feature: %s\n",
265 267 x86_feature_names[i]);
266 268 }
267 269 }
268 270 }
269 271
270 272 /* Note: This is the maximum size for the CPU, not the size of the structure. */
271 273 static size_t xsave_state_size = 0;
272 274 uint64_t xsave_bv_all = (XFEATURE_LEGACY_FP | XFEATURE_SSE);
273 275 boolean_t xsave_force_disable = B_FALSE;
274 276 extern int disable_smap;
275 277
276 278 /*
277 279 * This is set to platform type we are running on.
278 280 */
279 281 static int platform_type = -1;
280 282
281 283 #if !defined(__xpv)
282 284 /*
283 285 * Variable to patch if hypervisor platform detection needs to be
284 286 * disabled (e.g. platform_type will always be HW_NATIVE if this is 0).
285 287 */
286 288 int enable_platform_detection = 1;
287 289 #endif
288 290
289 291 /*
290 292 * monitor/mwait info.
291 293 *
292 294 * size_actual and buf_actual are the real address and size allocated to get
293 295 * proper mwait_buf alignement. buf_actual and size_actual should be passed
294 296 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use
295 297 * processor cache-line alignment, but this is not guarantied in the furture.
296 298 */
297 299 struct mwait_info {
298 300 size_t mon_min; /* min size to avoid missed wakeups */
299 301 size_t mon_max; /* size to avoid false wakeups */
300 302 size_t size_actual; /* size actually allocated */
301 303 void *buf_actual; /* memory actually allocated */
302 304 uint32_t support; /* processor support of monitor/mwait */
303 305 };
304 306
305 307 /*
306 308 * xsave/xrestor info.
307 309 *
308 310 * This structure contains HW feature bits and the size of the xsave save area.
309 311 * Note: the kernel declares a fixed size (AVX_XSAVE_SIZE) structure
310 312 * (xsave_state) to describe the xsave layout. However, at runtime the
311 313 * per-lwp xsave area is dynamically allocated based on xsav_max_size. The
312 314 * xsave_state structure simply represents the legacy layout of the beginning
313 315 * of the xsave area.
314 316 */
315 317 struct xsave_info {
316 318 uint32_t xsav_hw_features_low; /* Supported HW features */
317 319 uint32_t xsav_hw_features_high; /* Supported HW features */
318 320 size_t xsav_max_size; /* max size save area for HW features */
319 321 size_t ymm_size; /* AVX: size of ymm save area */
320 322 size_t ymm_offset; /* AVX: offset for ymm save area */
321 323 size_t bndregs_size; /* MPX: size of bndregs save area */
322 324 size_t bndregs_offset; /* MPX: offset for bndregs save area */
323 325 size_t bndcsr_size; /* MPX: size of bndcsr save area */
324 326 size_t bndcsr_offset; /* MPX: offset for bndcsr save area */
325 327 size_t opmask_size; /* AVX512: size of opmask save */
326 328 size_t opmask_offset; /* AVX512: offset for opmask save */
327 329 size_t zmmlo_size; /* AVX512: size of zmm 256 save */
328 330 size_t zmmlo_offset; /* AVX512: offset for zmm 256 save */
329 331 size_t zmmhi_size; /* AVX512: size of zmm hi reg save */
330 332 size_t zmmhi_offset; /* AVX512: offset for zmm hi reg save */
331 333 };
332 334
333 335
334 336 /*
335 337 * These constants determine how many of the elements of the
336 338 * cpuid we cache in the cpuid_info data structure; the
337 339 * remaining elements are accessible via the cpuid instruction.
338 340 */
339 341
340 342 #define NMAX_CPI_STD 8 /* eax = 0 .. 7 */
341 343 #define NMAX_CPI_EXTD 0x1f /* eax = 0x80000000 .. 0x8000001e */
342 344
343 345 /*
344 346 * Some terminology needs to be explained:
345 347 * - Socket: Something that can be plugged into a motherboard.
346 348 * - Package: Same as socket
347 349 * - Chip: Same as socket. Note that AMD's documentation uses term "chip"
348 350 * differently: there, chip is the same as processor node (below)
349 351 * - Processor node: Some AMD processors have more than one
350 352 * "subprocessor" embedded in a package. These subprocessors (nodes)
351 353 * are fully-functional processors themselves with cores, caches,
352 354 * memory controllers, PCI configuration spaces. They are connected
353 355 * inside the package with Hypertransport links. On single-node
354 356 * processors, processor node is equivalent to chip/socket/package.
355 357 * - Compute Unit: Some AMD processors pair cores in "compute units" that
356 358 * share the FPU and the I$ and L2 caches.
357 359 */
358 360
359 361 struct cpuid_info {
360 362 uint_t cpi_pass; /* last pass completed */
361 363 /*
362 364 * standard function information
363 365 */
364 366 uint_t cpi_maxeax; /* fn 0: %eax */
365 367 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */
366 368 uint_t cpi_vendor; /* enum of cpi_vendorstr */
367 369
368 370 uint_t cpi_family; /* fn 1: extended family */
369 371 uint_t cpi_model; /* fn 1: extended model */
370 372 uint_t cpi_step; /* fn 1: stepping */
371 373 chipid_t cpi_chipid; /* fn 1: %ebx: Intel: chip # */
372 374 /* AMD: package/socket # */
373 375 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */
374 376 int cpi_clogid; /* fn 1: %ebx: thread # */
375 377 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */
376 378 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */
377 379 uint_t cpi_ncache; /* fn 2: number of elements */
378 380 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */
379 381 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */
380 382 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */
381 383 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */
382 384 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 7 */
383 385 /*
384 386 * extended function information
385 387 */
386 388 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */
387 389 char cpi_brandstr[49]; /* fn 0x8000000[234] */
388 390 uint8_t cpi_pabits; /* fn 0x80000006: %eax */
389 391 uint8_t cpi_vabits; /* fn 0x80000006: %eax */
390 392 uint8_t cpi_fp_amd_save; /* AMD: FP error pointer save rqd. */
391 393 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x800000XX */
392 394
393 395 id_t cpi_coreid; /* same coreid => strands share core */
394 396 int cpi_pkgcoreid; /* core number within single package */
395 397 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */
396 398 /* Intel: fn 4: %eax[31-26] */
397 399 /*
398 400 * supported feature information
399 401 */
400 402 uint32_t cpi_support[6];
401 403 #define STD_EDX_FEATURES 0
402 404 #define AMD_EDX_FEATURES 1
403 405 #define TM_EDX_FEATURES 2
404 406 #define STD_ECX_FEATURES 3
405 407 #define AMD_ECX_FEATURES 4
406 408 #define STD_EBX_FEATURES 5
407 409 /*
408 410 * Synthesized information, where known.
409 411 */
410 412 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */
411 413 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */
412 414 uint32_t cpi_socket; /* Chip package/socket type */
413 415
414 416 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */
415 417 uint32_t cpi_apicid;
416 418 uint_t cpi_procnodeid; /* AMD: nodeID on HT, Intel: chipid */
417 419 uint_t cpi_procnodes_per_pkg; /* AMD: # of nodes in the package */
418 420 /* Intel: 1 */
419 421 uint_t cpi_compunitid; /* AMD: ComputeUnit ID, Intel: coreid */
420 422 uint_t cpi_cores_per_compunit; /* AMD: # of cores in the ComputeUnit */
421 423
422 424 struct xsave_info cpi_xsave; /* fn D: xsave/xrestor info */
423 425 };
424 426
425 427
426 428 static struct cpuid_info cpuid_info0;
427 429
428 430 /*
429 431 * These bit fields are defined by the Intel Application Note AP-485
430 432 * "Intel Processor Identification and the CPUID Instruction"
431 433 */
432 434 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20)
433 435 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16)
434 436 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12)
435 437 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8)
436 438 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0)
437 439 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4)
438 440
439 441 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx)
440 442 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx)
441 443 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx)
442 444 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx)
443 445 #define CPI_FEATURES_7_0_EBX(cpi) ((cpi)->cpi_std[7].cp_ebx)
444 446 #define CPI_FEATURES_7_0_ECX(cpi) ((cpi)->cpi_std[7].cp_ecx)
445 447 #define CPI_FEATURES_7_0_EDX(cpi) ((cpi)->cpi_std[7].cp_edx)
446 448
447 449 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0)
448 450 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7)
449 451 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16)
450 452 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24)
451 453
452 454 #define CPI_MAXEAX_MAX 0x100 /* sanity control */
453 455 #define CPI_XMAXEAX_MAX 0x80000100
454 456 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */
455 457 #define CPI_FNB_ECX_MAX 0x20 /* sanity: max fn B levels */
456 458
457 459 /*
458 460 * Function 4 (Deterministic Cache Parameters) macros
459 461 * Defined by Intel Application Note AP-485
460 462 */
461 463 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26)
462 464 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14)
463 465 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9)
464 466 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8)
465 467 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5)
466 468 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0)
467 469 #define CPI_CPU_LEVEL_TYPE(regs) BITX((regs)->cp_ecx, 15, 8)
468 470
469 471 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22)
470 472 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12)
471 473 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0)
472 474
473 475 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0)
474 476
475 477 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0)
476 478
477 479
478 480 /*
479 481 * A couple of shorthand macros to identify "later" P6-family chips
480 482 * like the Pentium M and Core. First, the "older" P6-based stuff
481 483 * (loosely defined as "pre-Pentium-4"):
482 484 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon
483 485 */
484 486 #define IS_LEGACY_P6(cpi) ( \
485 487 cpi->cpi_family == 6 && \
486 488 (cpi->cpi_model == 1 || \
487 489 cpi->cpi_model == 3 || \
488 490 cpi->cpi_model == 5 || \
489 491 cpi->cpi_model == 6 || \
490 492 cpi->cpi_model == 7 || \
491 493 cpi->cpi_model == 8 || \
492 494 cpi->cpi_model == 0xA || \
493 495 cpi->cpi_model == 0xB) \
494 496 )
495 497
496 498 /* A "new F6" is everything with family 6 that's not the above */
497 499 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi))
498 500
499 501 /* Extended family/model support */
500 502 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 || \
501 503 cpi->cpi_family >= 0xf)
502 504
503 505 /*
504 506 * Info for monitor/mwait idle loop.
505 507 *
506 508 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's
507 509 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November
508 510 * 2006.
509 511 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual
510 512 * Documentation Updates" #33633, Rev 2.05, December 2006.
511 513 */
512 514 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */
513 515 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */
514 516 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */
515 517 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON)
516 518 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2)
517 519 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1)
518 520 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0)
519 521 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0)
520 522 /*
521 523 * Number of sub-cstates for a given c-state.
522 524 */
523 525 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \
524 526 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state)
525 527
526 528 /*
527 529 * XSAVE leaf 0xD enumeration
528 530 */
529 531 #define CPUID_LEAFD_2_YMM_OFFSET 576
530 532 #define CPUID_LEAFD_2_YMM_SIZE 256
531 533
532 534 /*
533 535 * Functions we consune from cpuid_subr.c; don't publish these in a header
534 536 * file to try and keep people using the expected cpuid_* interfaces.
535 537 */
536 538 extern uint32_t _cpuid_skt(uint_t, uint_t, uint_t, uint_t);
537 539 extern const char *_cpuid_sktstr(uint_t, uint_t, uint_t, uint_t);
538 540 extern uint32_t _cpuid_chiprev(uint_t, uint_t, uint_t, uint_t);
539 541 extern const char *_cpuid_chiprevstr(uint_t, uint_t, uint_t, uint_t);
540 542 extern uint_t _cpuid_vendorstr_to_vendorcode(char *);
541 543
542 544 /*
543 545 * Apply up various platform-dependent restrictions where the
544 546 * underlying platform restrictions mean the CPU can be marked
545 547 * as less capable than its cpuid instruction would imply.
546 548 */
547 549 #if defined(__xpv)
548 550 static void
549 551 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp)
550 552 {
551 553 switch (eax) {
552 554 case 1: {
553 555 uint32_t mcamask = DOMAIN_IS_INITDOMAIN(xen_info) ?
554 556 0 : CPUID_INTC_EDX_MCA;
555 557 cp->cp_edx &=
556 558 ~(mcamask |
557 559 CPUID_INTC_EDX_PSE |
558 560 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE |
559 561 CPUID_INTC_EDX_SEP | CPUID_INTC_EDX_MTRR |
560 562 CPUID_INTC_EDX_PGE | CPUID_INTC_EDX_PAT |
561 563 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP |
562 564 CPUID_INTC_EDX_PSE36 | CPUID_INTC_EDX_HTT);
563 565 break;
564 566 }
565 567
566 568 case 0x80000001:
567 569 cp->cp_edx &=
568 570 ~(CPUID_AMD_EDX_PSE |
569 571 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE |
570 572 CPUID_AMD_EDX_MTRR | CPUID_AMD_EDX_PGE |
571 573 CPUID_AMD_EDX_PAT | CPUID_AMD_EDX_PSE36 |
572 574 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP |
573 575 CPUID_AMD_EDX_TSCP);
574 576 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY;
575 577 break;
576 578 default:
577 579 break;
578 580 }
579 581
580 582 switch (vendor) {
581 583 case X86_VENDOR_Intel:
582 584 switch (eax) {
583 585 case 4:
584 586 /*
585 587 * Zero out the (ncores-per-chip - 1) field
586 588 */
587 589 cp->cp_eax &= 0x03fffffff;
588 590 break;
589 591 default:
590 592 break;
591 593 }
592 594 break;
593 595 case X86_VENDOR_AMD:
594 596 switch (eax) {
595 597
596 598 case 0x80000001:
597 599 cp->cp_ecx &= ~CPUID_AMD_ECX_CR8D;
598 600 break;
599 601
600 602 case 0x80000008:
601 603 /*
602 604 * Zero out the (ncores-per-chip - 1) field
603 605 */
604 606 cp->cp_ecx &= 0xffffff00;
605 607 break;
606 608 default:
607 609 break;
608 610 }
609 611 break;
610 612 default:
611 613 break;
612 614 }
613 615 }
614 616 #else
615 617 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */
616 618 #endif
617 619
618 620 /*
619 621 * Some undocumented ways of patching the results of the cpuid
620 622 * instruction to permit running Solaris 10 on future cpus that
621 623 * we don't currently support. Could be set to non-zero values
622 624 * via settings in eeprom.
623 625 */
624 626
625 627 uint32_t cpuid_feature_ecx_include;
626 628 uint32_t cpuid_feature_ecx_exclude;
627 629 uint32_t cpuid_feature_edx_include;
628 630 uint32_t cpuid_feature_edx_exclude;
629 631
630 632 /*
631 633 * Allocate space for mcpu_cpi in the machcpu structure for all non-boot CPUs.
632 634 */
633 635 void
634 636 cpuid_alloc_space(cpu_t *cpu)
635 637 {
636 638 /*
637 639 * By convention, cpu0 is the boot cpu, which is set up
638 640 * before memory allocation is available. All other cpus get
639 641 * their cpuid_info struct allocated here.
640 642 */
641 643 ASSERT(cpu->cpu_id != 0);
642 644 ASSERT(cpu->cpu_m.mcpu_cpi == NULL);
643 645 cpu->cpu_m.mcpu_cpi =
644 646 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP);
645 647 }
646 648
647 649 void
648 650 cpuid_free_space(cpu_t *cpu)
649 651 {
650 652 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
651 653 int i;
652 654
653 655 ASSERT(cpi != NULL);
654 656 ASSERT(cpi != &cpuid_info0);
655 657
656 658 /*
657 659 * Free up any function 4 related dynamic storage
658 660 */
659 661 for (i = 1; i < cpi->cpi_std_4_size; i++)
660 662 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs));
661 663 if (cpi->cpi_std_4_size > 0)
662 664 kmem_free(cpi->cpi_std_4,
663 665 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *));
664 666
665 667 kmem_free(cpi, sizeof (*cpi));
666 668 cpu->cpu_m.mcpu_cpi = NULL;
667 669 }
668 670
669 671 #if !defined(__xpv)
670 672 /*
671 673 * Determine the type of the underlying platform. This is used to customize
672 674 * initialization of various subsystems (e.g. TSC). determine_platform() must
673 675 * only ever be called once to prevent two processors from seeing different
674 676 * values of platform_type. Must be called before cpuid_pass1(), the earliest
675 677 * consumer to execute (uses _cpuid_chiprev --> synth_amd_info --> get_hwenv).
676 678 */
677 679 void
678 680 determine_platform(void)
679 681 {
680 682 struct cpuid_regs cp;
681 683 uint32_t base;
682 684 uint32_t regs[4];
683 685 char *hvstr = (char *)regs;
684 686
685 687 ASSERT(platform_type == -1);
686 688
687 689 platform_type = HW_NATIVE;
688 690
689 691 if (!enable_platform_detection)
690 692 return;
691 693
692 694 /*
693 695 * If Hypervisor CPUID bit is set, try to determine hypervisor
694 696 * vendor signature, and set platform type accordingly.
695 697 *
696 698 * References:
697 699 * http://lkml.org/lkml/2008/10/1/246
698 700 * http://kb.vmware.com/kb/1009458
699 701 */
700 702 cp.cp_eax = 0x1;
701 703 (void) __cpuid_insn(&cp);
702 704 if ((cp.cp_ecx & CPUID_INTC_ECX_HV) != 0) {
703 705 cp.cp_eax = 0x40000000;
704 706 (void) __cpuid_insn(&cp);
705 707 regs[0] = cp.cp_ebx;
706 708 regs[1] = cp.cp_ecx;
707 709 regs[2] = cp.cp_edx;
708 710 regs[3] = 0;
709 711 if (strcmp(hvstr, HVSIG_XEN_HVM) == 0) {
710 712 platform_type = HW_XEN_HVM;
711 713 return;
712 714 }
713 715 if (strcmp(hvstr, HVSIG_VMWARE) == 0) {
714 716 platform_type = HW_VMWARE;
715 717 return;
716 718 }
717 719 if (strcmp(hvstr, HVSIG_KVM) == 0) {
718 720 platform_type = HW_KVM;
719 721 return;
720 722 }
721 723 if (strcmp(hvstr, HVSIG_BHYVE) == 0) {
722 724 platform_type = HW_BHYVE;
723 725 return;
724 726 }
725 727 if (strcmp(hvstr, HVSIG_MICROSOFT) == 0)
726 728 platform_type = HW_MICROSOFT;
727 729 } else {
728 730 /*
729 731 * Check older VMware hardware versions. VMware hypervisor is
730 732 * detected by performing an IN operation to VMware hypervisor
731 733 * port and checking that value returned in %ebx is VMware
732 734 * hypervisor magic value.
733 735 *
734 736 * References: http://kb.vmware.com/kb/1009458
735 737 */
736 738 vmware_port(VMWARE_HVCMD_GETVERSION, regs);
737 739 if (regs[1] == VMWARE_HVMAGIC) {
738 740 platform_type = HW_VMWARE;
739 741 return;
740 742 }
741 743 }
742 744
743 745 /*
744 746 * Check Xen hypervisor. In a fully virtualized domain,
745 747 * Xen's pseudo-cpuid function returns a string representing the
746 748 * Xen signature in %ebx, %ecx, and %edx. %eax contains the maximum
747 749 * supported cpuid function. We need at least a (base + 2) leaf value
748 750 * to do what we want to do. Try different base values, since the
749 751 * hypervisor might use a different one depending on whether Hyper-V
750 752 * emulation is switched on by default or not.
751 753 */
752 754 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
753 755 cp.cp_eax = base;
754 756 (void) __cpuid_insn(&cp);
755 757 regs[0] = cp.cp_ebx;
756 758 regs[1] = cp.cp_ecx;
757 759 regs[2] = cp.cp_edx;
758 760 regs[3] = 0;
759 761 if (strcmp(hvstr, HVSIG_XEN_HVM) == 0 &&
760 762 cp.cp_eax >= (base + 2)) {
761 763 platform_type &= ~HW_NATIVE;
762 764 platform_type |= HW_XEN_HVM;
763 765 return;
764 766 }
765 767 }
766 768 }
767 769
768 770 int
769 771 get_hwenv(void)
770 772 {
771 773 ASSERT(platform_type != -1);
772 774 return (platform_type);
773 775 }
774 776
775 777 int
776 778 is_controldom(void)
777 779 {
778 780 return (0);
779 781 }
780 782
781 783 #else
782 784
783 785 int
784 786 get_hwenv(void)
785 787 {
786 788 return (HW_XEN_PV);
787 789 }
788 790
789 791 int
790 792 is_controldom(void)
791 793 {
792 794 return (DOMAIN_IS_INITDOMAIN(xen_info));
793 795 }
794 796
795 797 #endif /* __xpv */
796 798
797 799 static void
798 800 cpuid_intel_getids(cpu_t *cpu, void *feature)
799 801 {
800 802 uint_t i;
801 803 uint_t chipid_shift = 0;
802 804 uint_t coreid_shift = 0;
803 805 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
804 806
805 807 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1)
806 808 chipid_shift++;
807 809
808 810 cpi->cpi_chipid = cpi->cpi_apicid >> chipid_shift;
809 811 cpi->cpi_clogid = cpi->cpi_apicid & ((1 << chipid_shift) - 1);
810 812
811 813 if (is_x86_feature(feature, X86FSET_CMP)) {
812 814 /*
813 815 * Multi-core (and possibly multi-threaded)
814 816 * processors.
815 817 */
816 818 uint_t ncpu_per_core;
817 819 if (cpi->cpi_ncore_per_chip == 1)
818 820 ncpu_per_core = cpi->cpi_ncpu_per_chip;
819 821 else if (cpi->cpi_ncore_per_chip > 1)
820 822 ncpu_per_core = cpi->cpi_ncpu_per_chip /
821 823 cpi->cpi_ncore_per_chip;
822 824 /*
823 825 * 8bit APIC IDs on dual core Pentiums
824 826 * look like this:
825 827 *
826 828 * +-----------------------+------+------+
827 829 * | Physical Package ID | MC | HT |
828 830 * +-----------------------+------+------+
829 831 * <------- chipid -------->
830 832 * <------- coreid --------------->
831 833 * <--- clogid -->
832 834 * <------>
833 835 * pkgcoreid
834 836 *
835 837 * Where the number of bits necessary to
836 838 * represent MC and HT fields together equals
837 839 * to the minimum number of bits necessary to
838 840 * store the value of cpi->cpi_ncpu_per_chip.
839 841 * Of those bits, the MC part uses the number
840 842 * of bits necessary to store the value of
841 843 * cpi->cpi_ncore_per_chip.
842 844 */
843 845 for (i = 1; i < ncpu_per_core; i <<= 1)
844 846 coreid_shift++;
845 847 cpi->cpi_coreid = cpi->cpi_apicid >> coreid_shift;
846 848 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift;
847 849 } else if (is_x86_feature(feature, X86FSET_HTT)) {
848 850 /*
849 851 * Single-core multi-threaded processors.
850 852 */
851 853 cpi->cpi_coreid = cpi->cpi_chipid;
852 854 cpi->cpi_pkgcoreid = 0;
853 855 }
854 856 cpi->cpi_procnodeid = cpi->cpi_chipid;
855 857 cpi->cpi_compunitid = cpi->cpi_coreid;
856 858 }
857 859
858 860 static void
859 861 cpuid_amd_getids(cpu_t *cpu)
860 862 {
861 863 int i, first_half, coreidsz;
862 864 uint32_t nb_caps_reg;
863 865 uint_t node2_1;
864 866 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
865 867 struct cpuid_regs *cp;
866 868
867 869 /*
868 870 * AMD CMP chips currently have a single thread per core.
869 871 *
870 872 * Since no two cpus share a core we must assign a distinct coreid
871 873 * per cpu, and we do this by using the cpu_id. This scheme does not,
872 874 * however, guarantee that sibling cores of a chip will have sequential
873 875 * coreids starting at a multiple of the number of cores per chip -
874 876 * that is usually the case, but if the ACPI MADT table is presented
875 877 * in a different order then we need to perform a few more gymnastics
876 878 * for the pkgcoreid.
877 879 *
878 880 * All processors in the system have the same number of enabled
879 881 * cores. Cores within a processor are always numbered sequentially
880 882 * from 0 regardless of how many or which are disabled, and there
881 883 * is no way for operating system to discover the real core id when some
882 884 * are disabled.
883 885 *
884 886 * In family 0x15, the cores come in pairs called compute units. They
885 887 * share I$ and L2 caches and the FPU. Enumeration of this feature is
886 888 * simplified by the new topology extensions CPUID leaf, indicated by
887 889 * the X86 feature X86FSET_TOPOEXT.
888 890 */
889 891
890 892 cpi->cpi_coreid = cpu->cpu_id;
891 893 cpi->cpi_compunitid = cpu->cpu_id;
892 894
893 895 if (cpi->cpi_xmaxeax >= 0x80000008) {
894 896
895 897 coreidsz = BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12);
896 898
897 899 /*
898 900 * In AMD parlance chip is really a node while Solaris
899 901 * sees chip as equivalent to socket/package.
900 902 */
901 903 cpi->cpi_ncore_per_chip =
902 904 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1;
903 905 if (coreidsz == 0) {
904 906 /* Use legacy method */
905 907 for (i = 1; i < cpi->cpi_ncore_per_chip; i <<= 1)
906 908 coreidsz++;
907 909 if (coreidsz == 0)
908 910 coreidsz = 1;
909 911 }
910 912 } else {
911 913 /* Assume single-core part */
912 914 cpi->cpi_ncore_per_chip = 1;
913 915 coreidsz = 1;
914 916 }
915 917
916 918 cpi->cpi_clogid = cpi->cpi_pkgcoreid =
917 919 cpi->cpi_apicid & ((1<<coreidsz) - 1);
918 920 cpi->cpi_ncpu_per_chip = cpi->cpi_ncore_per_chip;
919 921
920 922 /* Get node ID, compute unit ID */
921 923 if (is_x86_feature(x86_featureset, X86FSET_TOPOEXT) &&
922 924 cpi->cpi_xmaxeax >= 0x8000001e) {
923 925 cp = &cpi->cpi_extd[0x1e];
924 926 cp->cp_eax = 0x8000001e;
925 927 (void) __cpuid_insn(cp);
926 928
927 929 cpi->cpi_procnodes_per_pkg = BITX(cp->cp_ecx, 10, 8) + 1;
928 930 cpi->cpi_procnodeid = BITX(cp->cp_ecx, 7, 0);
929 931 cpi->cpi_cores_per_compunit = BITX(cp->cp_ebx, 15, 8) + 1;
930 932 cpi->cpi_compunitid = BITX(cp->cp_ebx, 7, 0)
931 933 + (cpi->cpi_ncore_per_chip / cpi->cpi_cores_per_compunit)
932 934 * (cpi->cpi_procnodeid / cpi->cpi_procnodes_per_pkg);
933 935 } else if (cpi->cpi_family == 0xf || cpi->cpi_family >= 0x11) {
934 936 cpi->cpi_procnodeid = (cpi->cpi_apicid >> coreidsz) & 7;
935 937 } else if (cpi->cpi_family == 0x10) {
936 938 /*
937 939 * See if we are a multi-node processor.
938 940 * All processors in the system have the same number of nodes
939 941 */
940 942 nb_caps_reg = pci_getl_func(0, 24, 3, 0xe8);
941 943 if ((cpi->cpi_model < 8) || BITX(nb_caps_reg, 29, 29) == 0) {
942 944 /* Single-node */
943 945 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 5,
944 946 coreidsz);
945 947 } else {
946 948
947 949 /*
948 950 * Multi-node revision D (2 nodes per package
949 951 * are supported)
950 952 */
951 953 cpi->cpi_procnodes_per_pkg = 2;
952 954
953 955 first_half = (cpi->cpi_pkgcoreid <=
954 956 (cpi->cpi_ncore_per_chip/2 - 1));
955 957
956 958 if (cpi->cpi_apicid == cpi->cpi_pkgcoreid) {
957 959 /* We are BSP */
958 960 cpi->cpi_procnodeid = (first_half ? 0 : 1);
959 961 } else {
960 962
961 963 /* We are AP */
962 964 /* NodeId[2:1] bits to use for reading F3xe8 */
963 965 node2_1 = BITX(cpi->cpi_apicid, 5, 4) << 1;
964 966
965 967 nb_caps_reg =
966 968 pci_getl_func(0, 24 + node2_1, 3, 0xe8);
967 969
968 970 /*
969 971 * Check IntNodeNum bit (31:30, but bit 31 is
970 972 * always 0 on dual-node processors)
971 973 */
972 974 if (BITX(nb_caps_reg, 30, 30) == 0)
973 975 cpi->cpi_procnodeid = node2_1 +
974 976 !first_half;
975 977 else
976 978 cpi->cpi_procnodeid = node2_1 +
977 979 first_half;
978 980 }
979 981 }
980 982 } else {
981 983 cpi->cpi_procnodeid = 0;
982 984 }
983 985
984 986 cpi->cpi_chipid =
985 987 cpi->cpi_procnodeid / cpi->cpi_procnodes_per_pkg;
986 988 }
987 989
988 990 static void
989 991 cpuid_scan_security(cpu_t *cpu, uchar_t *featureset)
990 992 {
991 993 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
992 994
993 995 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
994 996 cpi->cpi_xmaxeax >= 0x80000008) {
995 997 if (cpi->cpi_extd[8].cp_ebx & CPUID_AMD_EBX_IBPB)
996 998 add_x86_feature(featureset, X86FSET_IBPB);
997 999 if (cpi->cpi_extd[8].cp_ebx & CPUID_AMD_EBX_IBRS)
998 1000 add_x86_feature(featureset, X86FSET_IBRS);
999 1001 if (cpi->cpi_extd[8].cp_ebx & CPUID_AMD_EBX_STIBP)
1000 1002 add_x86_feature(featureset, X86FSET_STIBP);
1001 1003 if (cpi->cpi_extd[8].cp_ebx & CPUID_AMD_EBX_IBRS_ALL)
1002 1004 add_x86_feature(featureset, X86FSET_IBRS_ALL);
1003 1005 if (cpi->cpi_extd[8].cp_ebx & CPUID_AMD_EBX_STIBP_ALL)
1004 1006 add_x86_feature(featureset, X86FSET_STIBP_ALL);
1005 1007 if (cpi->cpi_extd[8].cp_ebx & CPUID_AMD_EBX_PREFER_IBRS)
1006 1008 add_x86_feature(featureset, X86FSET_RSBA);
1007 1009 if (cpi->cpi_extd[8].cp_ebx & CPUID_AMD_EBX_SSBD)
1008 1010 add_x86_feature(featureset, X86FSET_SSBD);
1009 1011 if (cpi->cpi_extd[8].cp_ebx & CPUID_AMD_EBX_VIRT_SSBD)
1010 1012 add_x86_feature(featureset, X86FSET_SSBD_VIRT);
1011 1013 if (cpi->cpi_extd[8].cp_ebx & CPUID_AMD_EBX_SSB_NO)
1012 1014 add_x86_feature(featureset, X86FSET_SSB_NO);
1013 1015 } else if (cpi->cpi_vendor == X86_VENDOR_Intel &&
1014 1016 cpi->cpi_maxeax >= 7) {
1015 1017 struct cpuid_regs *ecp;
1016 1018 ecp = &cpi->cpi_std[7];
1017 1019
1018 1020 if (ecp->cp_edx & CPUID_INTC_EDX_7_0_SPEC_CTRL) {
1019 1021 add_x86_feature(featureset, X86FSET_IBRS);
1020 1022 add_x86_feature(featureset, X86FSET_IBPB);
1021 1023 }
1022 1024
1023 1025 if (ecp->cp_edx & CPUID_INTC_EDX_7_0_STIBP) {
1024 1026 add_x86_feature(featureset, X86FSET_STIBP);
1025 1027 }
1026 1028
1027 1029 /*
1028 1030 * Don't read the arch caps MSR on xpv where we lack the
1029 1031 * on_trap().
1030 1032 */
1031 1033 #ifndef __xpv
1032 1034 if (ecp->cp_edx & CPUID_INTC_EDX_7_0_ARCH_CAPS) {
1033 1035 on_trap_data_t otd;
1034 1036
1035 1037 /*
1036 1038 * Be paranoid and assume we'll get a #GP.
1037 1039 */
1038 1040 if (!on_trap(&otd, OT_DATA_ACCESS)) {
1039 1041 uint64_t reg;
1040 1042
1041 1043 reg = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
1042 1044 if (reg & IA32_ARCH_CAP_RDCL_NO) {
1043 1045 add_x86_feature(featureset,
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1044 1046 X86FSET_RDCL_NO);
1045 1047 }
1046 1048 if (reg & IA32_ARCH_CAP_IBRS_ALL) {
1047 1049 add_x86_feature(featureset,
1048 1050 X86FSET_IBRS_ALL);
1049 1051 }
1050 1052 if (reg & IA32_ARCH_CAP_RSBA) {
1051 1053 add_x86_feature(featureset,
1052 1054 X86FSET_RSBA);
1053 1055 }
1056 + if (reg & IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY) {
1057 + add_x86_feature(featureset,
1058 + X86FSET_L1D_VM_NO);
1059 + }
1054 1060 if (reg & IA32_ARCH_CAP_SSB_NO) {
1055 1061 add_x86_feature(featureset,
1056 1062 X86FSET_SSB_NO);
1057 1063 }
1058 1064 }
1059 1065 no_trap();
1060 1066 }
1061 1067 #endif /* !__xpv */
1062 1068
1063 1069 if (ecp->cp_edx & CPUID_INTC_EDX_7_0_SSBD)
1064 1070 add_x86_feature(featureset, X86FSET_SSBD);
1071 +
1072 + if (ecp->cp_edx & CPUID_INTC_EDX_7_0_FLUSH_CMD)
1073 + add_x86_feature(featureset, X86FSET_FLUSH_CMD);
1065 1074 }
1066 1075 }
1067 1076
1068 1077 /*
1069 1078 * Setup XFeature_Enabled_Mask register. Required by xsave feature.
1070 1079 */
1071 1080 void
1072 1081 setup_xfem(void)
1073 1082 {
1074 1083 uint64_t flags = XFEATURE_LEGACY_FP;
1075 1084
1076 1085 ASSERT(is_x86_feature(x86_featureset, X86FSET_XSAVE));
1077 1086
1078 1087 if (is_x86_feature(x86_featureset, X86FSET_SSE))
1079 1088 flags |= XFEATURE_SSE;
1080 1089
1081 1090 if (is_x86_feature(x86_featureset, X86FSET_AVX))
1082 1091 flags |= XFEATURE_AVX;
1083 1092
1084 1093 if (is_x86_feature(x86_featureset, X86FSET_AVX512F))
1085 1094 flags |= XFEATURE_AVX512;
1086 1095
1087 1096 set_xcr(XFEATURE_ENABLED_MASK, flags);
1088 1097
1089 1098 xsave_bv_all = flags;
1090 1099 }
1091 1100
1092 1101 void
1093 1102 cpuid_pass1(cpu_t *cpu, uchar_t *featureset)
1094 1103 {
1095 1104 uint32_t mask_ecx, mask_edx;
1096 1105 struct cpuid_info *cpi;
1097 1106 struct cpuid_regs *cp;
1098 1107 int xcpuid;
1099 1108 #if !defined(__xpv)
1100 1109 extern int idle_cpu_prefer_mwait;
1101 1110 #endif
1102 1111
1103 1112 /*
1104 1113 * Space statically allocated for BSP, ensure pointer is set
1105 1114 */
1106 1115 if (cpu->cpu_id == 0) {
1107 1116 if (cpu->cpu_m.mcpu_cpi == NULL)
1108 1117 cpu->cpu_m.mcpu_cpi = &cpuid_info0;
1109 1118 }
1110 1119
1111 1120 add_x86_feature(featureset, X86FSET_CPUID);
1112 1121
1113 1122 cpi = cpu->cpu_m.mcpu_cpi;
1114 1123 ASSERT(cpi != NULL);
1115 1124 cp = &cpi->cpi_std[0];
1116 1125 cp->cp_eax = 0;
1117 1126 cpi->cpi_maxeax = __cpuid_insn(cp);
1118 1127 {
1119 1128 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr;
1120 1129 *iptr++ = cp->cp_ebx;
1121 1130 *iptr++ = cp->cp_edx;
1122 1131 *iptr++ = cp->cp_ecx;
1123 1132 *(char *)&cpi->cpi_vendorstr[12] = '\0';
1124 1133 }
1125 1134
1126 1135 cpi->cpi_vendor = _cpuid_vendorstr_to_vendorcode(cpi->cpi_vendorstr);
1127 1136 x86_vendor = cpi->cpi_vendor; /* for compatibility */
1128 1137
1129 1138 /*
1130 1139 * Limit the range in case of weird hardware
1131 1140 */
1132 1141 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX)
1133 1142 cpi->cpi_maxeax = CPI_MAXEAX_MAX;
1134 1143 if (cpi->cpi_maxeax < 1)
1135 1144 goto pass1_done;
1136 1145
1137 1146 cp = &cpi->cpi_std[1];
1138 1147 cp->cp_eax = 1;
1139 1148 (void) __cpuid_insn(cp);
1140 1149
1141 1150 /*
1142 1151 * Extract identifying constants for easy access.
1143 1152 */
1144 1153 cpi->cpi_model = CPI_MODEL(cpi);
1145 1154 cpi->cpi_family = CPI_FAMILY(cpi);
1146 1155
1147 1156 if (cpi->cpi_family == 0xf)
1148 1157 cpi->cpi_family += CPI_FAMILY_XTD(cpi);
1149 1158
1150 1159 /*
1151 1160 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf.
1152 1161 * Intel, and presumably everyone else, uses model == 0xf, as
1153 1162 * one would expect (max value means possible overflow). Sigh.
1154 1163 */
1155 1164
1156 1165 switch (cpi->cpi_vendor) {
1157 1166 case X86_VENDOR_Intel:
1158 1167 if (IS_EXTENDED_MODEL_INTEL(cpi))
1159 1168 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
1160 1169 break;
1161 1170 case X86_VENDOR_AMD:
1162 1171 if (CPI_FAMILY(cpi) == 0xf)
1163 1172 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
1164 1173 break;
1165 1174 default:
1166 1175 if (cpi->cpi_model == 0xf)
1167 1176 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
1168 1177 break;
1169 1178 }
1170 1179
1171 1180 cpi->cpi_step = CPI_STEP(cpi);
1172 1181 cpi->cpi_brandid = CPI_BRANDID(cpi);
1173 1182
1174 1183 /*
1175 1184 * *default* assumptions:
1176 1185 * - believe %edx feature word
1177 1186 * - ignore %ecx feature word
1178 1187 * - 32-bit virtual and physical addressing
1179 1188 */
1180 1189 mask_edx = 0xffffffff;
1181 1190 mask_ecx = 0;
1182 1191
1183 1192 cpi->cpi_pabits = cpi->cpi_vabits = 32;
1184 1193
1185 1194 switch (cpi->cpi_vendor) {
1186 1195 case X86_VENDOR_Intel:
1187 1196 if (cpi->cpi_family == 5)
1188 1197 x86_type = X86_TYPE_P5;
1189 1198 else if (IS_LEGACY_P6(cpi)) {
1190 1199 x86_type = X86_TYPE_P6;
1191 1200 pentiumpro_bug4046376 = 1;
1192 1201 /*
1193 1202 * Clear the SEP bit when it was set erroneously
1194 1203 */
1195 1204 if (cpi->cpi_model < 3 && cpi->cpi_step < 3)
1196 1205 cp->cp_edx &= ~CPUID_INTC_EDX_SEP;
1197 1206 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) {
1198 1207 x86_type = X86_TYPE_P4;
1199 1208 /*
1200 1209 * We don't currently depend on any of the %ecx
1201 1210 * features until Prescott, so we'll only check
1202 1211 * this from P4 onwards. We might want to revisit
1203 1212 * that idea later.
1204 1213 */
1205 1214 mask_ecx = 0xffffffff;
1206 1215 } else if (cpi->cpi_family > 0xf)
1207 1216 mask_ecx = 0xffffffff;
1208 1217 /*
1209 1218 * We don't support MONITOR/MWAIT if leaf 5 is not available
1210 1219 * to obtain the monitor linesize.
1211 1220 */
1212 1221 if (cpi->cpi_maxeax < 5)
1213 1222 mask_ecx &= ~CPUID_INTC_ECX_MON;
1214 1223 break;
1215 1224 case X86_VENDOR_IntelClone:
1216 1225 default:
1217 1226 break;
1218 1227 case X86_VENDOR_AMD:
1219 1228 #if defined(OPTERON_ERRATUM_108)
1220 1229 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) {
1221 1230 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0;
1222 1231 cpi->cpi_model = 0xc;
1223 1232 } else
1224 1233 #endif
1225 1234 if (cpi->cpi_family == 5) {
1226 1235 /*
1227 1236 * AMD K5 and K6
1228 1237 *
1229 1238 * These CPUs have an incomplete implementation
1230 1239 * of MCA/MCE which we mask away.
1231 1240 */
1232 1241 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA);
1233 1242
1234 1243 /*
1235 1244 * Model 0 uses the wrong (APIC) bit
1236 1245 * to indicate PGE. Fix it here.
1237 1246 */
1238 1247 if (cpi->cpi_model == 0) {
1239 1248 if (cp->cp_edx & 0x200) {
1240 1249 cp->cp_edx &= ~0x200;
1241 1250 cp->cp_edx |= CPUID_INTC_EDX_PGE;
1242 1251 }
1243 1252 }
1244 1253
1245 1254 /*
1246 1255 * Early models had problems w/ MMX; disable.
1247 1256 */
1248 1257 if (cpi->cpi_model < 6)
1249 1258 mask_edx &= ~CPUID_INTC_EDX_MMX;
1250 1259 }
1251 1260
1252 1261 /*
1253 1262 * For newer families, SSE3 and CX16, at least, are valid;
1254 1263 * enable all
1255 1264 */
1256 1265 if (cpi->cpi_family >= 0xf)
1257 1266 mask_ecx = 0xffffffff;
1258 1267 /*
1259 1268 * We don't support MONITOR/MWAIT if leaf 5 is not available
1260 1269 * to obtain the monitor linesize.
1261 1270 */
1262 1271 if (cpi->cpi_maxeax < 5)
1263 1272 mask_ecx &= ~CPUID_INTC_ECX_MON;
1264 1273
1265 1274 #if !defined(__xpv)
1266 1275 /*
1267 1276 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD
1268 1277 * processors. AMD does not intend MWAIT to be used in the cpu
1269 1278 * idle loop on current and future processors. 10h and future
1270 1279 * AMD processors use more power in MWAIT than HLT.
1271 1280 * Pre-family-10h Opterons do not have the MWAIT instruction.
1272 1281 */
1273 1282 idle_cpu_prefer_mwait = 0;
1274 1283 #endif
1275 1284
1276 1285 break;
1277 1286 case X86_VENDOR_TM:
1278 1287 /*
1279 1288 * workaround the NT workaround in CMS 4.1
1280 1289 */
1281 1290 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 &&
1282 1291 (cpi->cpi_step == 2 || cpi->cpi_step == 3))
1283 1292 cp->cp_edx |= CPUID_INTC_EDX_CX8;
1284 1293 break;
1285 1294 case X86_VENDOR_Centaur:
1286 1295 /*
1287 1296 * workaround the NT workarounds again
1288 1297 */
1289 1298 if (cpi->cpi_family == 6)
1290 1299 cp->cp_edx |= CPUID_INTC_EDX_CX8;
1291 1300 break;
1292 1301 case X86_VENDOR_Cyrix:
1293 1302 /*
1294 1303 * We rely heavily on the probing in locore
1295 1304 * to actually figure out what parts, if any,
1296 1305 * of the Cyrix cpuid instruction to believe.
1297 1306 */
1298 1307 switch (x86_type) {
1299 1308 case X86_TYPE_CYRIX_486:
1300 1309 mask_edx = 0;
1301 1310 break;
1302 1311 case X86_TYPE_CYRIX_6x86:
1303 1312 mask_edx = 0;
1304 1313 break;
1305 1314 case X86_TYPE_CYRIX_6x86L:
1306 1315 mask_edx =
1307 1316 CPUID_INTC_EDX_DE |
1308 1317 CPUID_INTC_EDX_CX8;
1309 1318 break;
1310 1319 case X86_TYPE_CYRIX_6x86MX:
1311 1320 mask_edx =
1312 1321 CPUID_INTC_EDX_DE |
1313 1322 CPUID_INTC_EDX_MSR |
1314 1323 CPUID_INTC_EDX_CX8 |
1315 1324 CPUID_INTC_EDX_PGE |
1316 1325 CPUID_INTC_EDX_CMOV |
1317 1326 CPUID_INTC_EDX_MMX;
1318 1327 break;
1319 1328 case X86_TYPE_CYRIX_GXm:
1320 1329 mask_edx =
1321 1330 CPUID_INTC_EDX_MSR |
1322 1331 CPUID_INTC_EDX_CX8 |
1323 1332 CPUID_INTC_EDX_CMOV |
1324 1333 CPUID_INTC_EDX_MMX;
1325 1334 break;
1326 1335 case X86_TYPE_CYRIX_MediaGX:
1327 1336 break;
1328 1337 case X86_TYPE_CYRIX_MII:
1329 1338 case X86_TYPE_VIA_CYRIX_III:
1330 1339 mask_edx =
1331 1340 CPUID_INTC_EDX_DE |
1332 1341 CPUID_INTC_EDX_TSC |
1333 1342 CPUID_INTC_EDX_MSR |
1334 1343 CPUID_INTC_EDX_CX8 |
1335 1344 CPUID_INTC_EDX_PGE |
1336 1345 CPUID_INTC_EDX_CMOV |
1337 1346 CPUID_INTC_EDX_MMX;
1338 1347 break;
1339 1348 default:
1340 1349 break;
1341 1350 }
1342 1351 break;
1343 1352 }
1344 1353
1345 1354 #if defined(__xpv)
1346 1355 /*
1347 1356 * Do not support MONITOR/MWAIT under a hypervisor
1348 1357 */
1349 1358 mask_ecx &= ~CPUID_INTC_ECX_MON;
1350 1359 /*
1351 1360 * Do not support XSAVE under a hypervisor for now
1352 1361 */
1353 1362 xsave_force_disable = B_TRUE;
1354 1363
1355 1364 #endif /* __xpv */
1356 1365
1357 1366 if (xsave_force_disable) {
1358 1367 mask_ecx &= ~CPUID_INTC_ECX_XSAVE;
1359 1368 mask_ecx &= ~CPUID_INTC_ECX_AVX;
1360 1369 mask_ecx &= ~CPUID_INTC_ECX_F16C;
1361 1370 mask_ecx &= ~CPUID_INTC_ECX_FMA;
1362 1371 }
1363 1372
1364 1373 /*
1365 1374 * Now we've figured out the masks that determine
1366 1375 * which bits we choose to believe, apply the masks
1367 1376 * to the feature words, then map the kernel's view
1368 1377 * of these feature words into its feature word.
1369 1378 */
1370 1379 cp->cp_edx &= mask_edx;
1371 1380 cp->cp_ecx &= mask_ecx;
1372 1381
1373 1382 /*
1374 1383 * apply any platform restrictions (we don't call this
1375 1384 * immediately after __cpuid_insn here, because we need the
1376 1385 * workarounds applied above first)
1377 1386 */
1378 1387 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp);
1379 1388
1380 1389 /*
1381 1390 * In addition to ecx and edx, Intel and AMD are storing a bunch of
1382 1391 * instruction set extensions in leaf 7's ebx, ecx, and edx.
1383 1392 */
1384 1393 if (cpi->cpi_maxeax >= 7) {
1385 1394 struct cpuid_regs *ecp;
1386 1395 ecp = &cpi->cpi_std[7];
1387 1396 ecp->cp_eax = 7;
1388 1397 ecp->cp_ecx = 0;
1389 1398 (void) __cpuid_insn(ecp);
1390 1399
1391 1400 /*
1392 1401 * If XSAVE has been disabled, just ignore all of the
1393 1402 * extended-save-area dependent flags here.
1394 1403 */
1395 1404 if (xsave_force_disable) {
1396 1405 ecp->cp_ebx &= ~CPUID_INTC_EBX_7_0_BMI1;
1397 1406 ecp->cp_ebx &= ~CPUID_INTC_EBX_7_0_BMI2;
1398 1407 ecp->cp_ebx &= ~CPUID_INTC_EBX_7_0_AVX2;
1399 1408 ecp->cp_ebx &= ~CPUID_INTC_EBX_7_0_MPX;
1400 1409 ecp->cp_ebx &= ~CPUID_INTC_EBX_7_0_ALL_AVX512;
1401 1410 ecp->cp_ecx &= ~CPUID_INTC_ECX_7_0_ALL_AVX512;
1402 1411 ecp->cp_edx &= ~CPUID_INTC_EDX_7_0_ALL_AVX512;
1403 1412 }
1404 1413
1405 1414 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_SMEP)
1406 1415 add_x86_feature(featureset, X86FSET_SMEP);
1407 1416
1408 1417 /*
1409 1418 * We check disable_smap here in addition to in startup_smap()
1410 1419 * to ensure CPUs that aren't the boot CPU don't accidentally
1411 1420 * include it in the feature set and thus generate a mismatched
1412 1421 * x86 feature set across CPUs.
1413 1422 */
1414 1423 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_SMAP &&
1415 1424 disable_smap == 0)
1416 1425 add_x86_feature(featureset, X86FSET_SMAP);
1417 1426
1418 1427 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_RDSEED)
1419 1428 add_x86_feature(featureset, X86FSET_RDSEED);
1420 1429
1421 1430 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_ADX)
1422 1431 add_x86_feature(featureset, X86FSET_ADX);
1423 1432
1424 1433 if (cpi->cpi_vendor == X86_VENDOR_Intel) {
1425 1434 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_INVPCID)
1426 1435 add_x86_feature(featureset, X86FSET_INVPCID);
1427 1436
1428 1437 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_MPX)
1429 1438 add_x86_feature(featureset, X86FSET_MPX);
1430 1439 }
1431 1440 }
1432 1441
1433 1442 /*
1434 1443 * fold in overrides from the "eeprom" mechanism
1435 1444 */
1436 1445 cp->cp_edx |= cpuid_feature_edx_include;
1437 1446 cp->cp_edx &= ~cpuid_feature_edx_exclude;
1438 1447
1439 1448 cp->cp_ecx |= cpuid_feature_ecx_include;
1440 1449 cp->cp_ecx &= ~cpuid_feature_ecx_exclude;
1441 1450
1442 1451 if (cp->cp_edx & CPUID_INTC_EDX_PSE) {
1443 1452 add_x86_feature(featureset, X86FSET_LARGEPAGE);
1444 1453 }
1445 1454 if (cp->cp_edx & CPUID_INTC_EDX_TSC) {
1446 1455 add_x86_feature(featureset, X86FSET_TSC);
1447 1456 }
1448 1457 if (cp->cp_edx & CPUID_INTC_EDX_MSR) {
1449 1458 add_x86_feature(featureset, X86FSET_MSR);
1450 1459 }
1451 1460 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) {
1452 1461 add_x86_feature(featureset, X86FSET_MTRR);
1453 1462 }
1454 1463 if (cp->cp_edx & CPUID_INTC_EDX_PGE) {
1455 1464 add_x86_feature(featureset, X86FSET_PGE);
1456 1465 }
1457 1466 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) {
1458 1467 add_x86_feature(featureset, X86FSET_CMOV);
1459 1468 }
1460 1469 if (cp->cp_edx & CPUID_INTC_EDX_MMX) {
1461 1470 add_x86_feature(featureset, X86FSET_MMX);
1462 1471 }
1463 1472 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 &&
1464 1473 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) {
1465 1474 add_x86_feature(featureset, X86FSET_MCA);
1466 1475 }
1467 1476 if (cp->cp_edx & CPUID_INTC_EDX_PAE) {
1468 1477 add_x86_feature(featureset, X86FSET_PAE);
1469 1478 }
1470 1479 if (cp->cp_edx & CPUID_INTC_EDX_CX8) {
1471 1480 add_x86_feature(featureset, X86FSET_CX8);
1472 1481 }
1473 1482 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) {
1474 1483 add_x86_feature(featureset, X86FSET_CX16);
1475 1484 }
1476 1485 if (cp->cp_edx & CPUID_INTC_EDX_PAT) {
1477 1486 add_x86_feature(featureset, X86FSET_PAT);
1478 1487 }
1479 1488 if (cp->cp_edx & CPUID_INTC_EDX_SEP) {
1480 1489 add_x86_feature(featureset, X86FSET_SEP);
1481 1490 }
1482 1491 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) {
1483 1492 /*
1484 1493 * In our implementation, fxsave/fxrstor
1485 1494 * are prerequisites before we'll even
1486 1495 * try and do SSE things.
1487 1496 */
1488 1497 if (cp->cp_edx & CPUID_INTC_EDX_SSE) {
1489 1498 add_x86_feature(featureset, X86FSET_SSE);
1490 1499 }
1491 1500 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) {
1492 1501 add_x86_feature(featureset, X86FSET_SSE2);
1493 1502 }
1494 1503 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) {
1495 1504 add_x86_feature(featureset, X86FSET_SSE3);
1496 1505 }
1497 1506 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) {
1498 1507 add_x86_feature(featureset, X86FSET_SSSE3);
1499 1508 }
1500 1509 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) {
1501 1510 add_x86_feature(featureset, X86FSET_SSE4_1);
1502 1511 }
1503 1512 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) {
1504 1513 add_x86_feature(featureset, X86FSET_SSE4_2);
1505 1514 }
1506 1515 if (cp->cp_ecx & CPUID_INTC_ECX_AES) {
1507 1516 add_x86_feature(featureset, X86FSET_AES);
1508 1517 }
1509 1518 if (cp->cp_ecx & CPUID_INTC_ECX_PCLMULQDQ) {
1510 1519 add_x86_feature(featureset, X86FSET_PCLMULQDQ);
1511 1520 }
1512 1521
1513 1522 if (cpi->cpi_std[7].cp_ebx & CPUID_INTC_EBX_7_0_SHA)
1514 1523 add_x86_feature(featureset, X86FSET_SHA);
1515 1524
1516 1525 if (cpi->cpi_std[7].cp_ecx & CPUID_INTC_ECX_7_0_UMIP)
1517 1526 add_x86_feature(featureset, X86FSET_UMIP);
1518 1527 if (cpi->cpi_std[7].cp_ecx & CPUID_INTC_ECX_7_0_PKU)
1519 1528 add_x86_feature(featureset, X86FSET_PKU);
1520 1529 if (cpi->cpi_std[7].cp_ecx & CPUID_INTC_ECX_7_0_OSPKE)
1521 1530 add_x86_feature(featureset, X86FSET_OSPKE);
1522 1531
1523 1532 if (cp->cp_ecx & CPUID_INTC_ECX_XSAVE) {
1524 1533 add_x86_feature(featureset, X86FSET_XSAVE);
1525 1534
1526 1535 /* We only test AVX & AVX512 when there is XSAVE */
1527 1536
1528 1537 if (cp->cp_ecx & CPUID_INTC_ECX_AVX) {
1529 1538 add_x86_feature(featureset,
1530 1539 X86FSET_AVX);
1531 1540
1532 1541 /*
1533 1542 * Intel says we can't check these without also
1534 1543 * checking AVX.
1535 1544 */
1536 1545 if (cp->cp_ecx & CPUID_INTC_ECX_F16C)
1537 1546 add_x86_feature(featureset,
1538 1547 X86FSET_F16C);
1539 1548
1540 1549 if (cp->cp_ecx & CPUID_INTC_ECX_FMA)
1541 1550 add_x86_feature(featureset,
1542 1551 X86FSET_FMA);
1543 1552
1544 1553 if (cpi->cpi_std[7].cp_ebx &
1545 1554 CPUID_INTC_EBX_7_0_BMI1)
1546 1555 add_x86_feature(featureset,
1547 1556 X86FSET_BMI1);
1548 1557
1549 1558 if (cpi->cpi_std[7].cp_ebx &
1550 1559 CPUID_INTC_EBX_7_0_BMI2)
1551 1560 add_x86_feature(featureset,
1552 1561 X86FSET_BMI2);
1553 1562
1554 1563 if (cpi->cpi_std[7].cp_ebx &
1555 1564 CPUID_INTC_EBX_7_0_AVX2)
1556 1565 add_x86_feature(featureset,
1557 1566 X86FSET_AVX2);
1558 1567 }
1559 1568
1560 1569 if (cpi->cpi_vendor == X86_VENDOR_Intel &&
1561 1570 (cpi->cpi_std[7].cp_ebx &
1562 1571 CPUID_INTC_EBX_7_0_AVX512F) != 0) {
1563 1572 add_x86_feature(featureset, X86FSET_AVX512F);
1564 1573
1565 1574 if (cpi->cpi_std[7].cp_ebx &
1566 1575 CPUID_INTC_EBX_7_0_AVX512DQ)
1567 1576 add_x86_feature(featureset,
1568 1577 X86FSET_AVX512DQ);
1569 1578 if (cpi->cpi_std[7].cp_ebx &
1570 1579 CPUID_INTC_EBX_7_0_AVX512IFMA)
1571 1580 add_x86_feature(featureset,
1572 1581 X86FSET_AVX512FMA);
1573 1582 if (cpi->cpi_std[7].cp_ebx &
1574 1583 CPUID_INTC_EBX_7_0_AVX512PF)
1575 1584 add_x86_feature(featureset,
1576 1585 X86FSET_AVX512PF);
1577 1586 if (cpi->cpi_std[7].cp_ebx &
1578 1587 CPUID_INTC_EBX_7_0_AVX512ER)
1579 1588 add_x86_feature(featureset,
1580 1589 X86FSET_AVX512ER);
1581 1590 if (cpi->cpi_std[7].cp_ebx &
1582 1591 CPUID_INTC_EBX_7_0_AVX512CD)
1583 1592 add_x86_feature(featureset,
1584 1593 X86FSET_AVX512CD);
1585 1594 if (cpi->cpi_std[7].cp_ebx &
1586 1595 CPUID_INTC_EBX_7_0_AVX512BW)
1587 1596 add_x86_feature(featureset,
1588 1597 X86FSET_AVX512BW);
1589 1598 if (cpi->cpi_std[7].cp_ebx &
1590 1599 CPUID_INTC_EBX_7_0_AVX512VL)
1591 1600 add_x86_feature(featureset,
1592 1601 X86FSET_AVX512VL);
1593 1602
1594 1603 if (cpi->cpi_std[7].cp_ecx &
1595 1604 CPUID_INTC_ECX_7_0_AVX512VBMI)
1596 1605 add_x86_feature(featureset,
1597 1606 X86FSET_AVX512VBMI);
1598 1607 if (cpi->cpi_std[7].cp_ecx &
1599 1608 CPUID_INTC_ECX_7_0_AVX512VPOPCDQ)
1600 1609 add_x86_feature(featureset,
1601 1610 X86FSET_AVX512VPOPCDQ);
1602 1611
1603 1612 if (cpi->cpi_std[7].cp_edx &
1604 1613 CPUID_INTC_EDX_7_0_AVX5124NNIW)
1605 1614 add_x86_feature(featureset,
1606 1615 X86FSET_AVX512NNIW);
1607 1616 if (cpi->cpi_std[7].cp_edx &
1608 1617 CPUID_INTC_EDX_7_0_AVX5124FMAPS)
1609 1618 add_x86_feature(featureset,
1610 1619 X86FSET_AVX512FMAPS);
1611 1620 }
1612 1621 }
1613 1622 }
1614 1623
1615 1624 if (cpi->cpi_vendor == X86_VENDOR_Intel) {
1616 1625 if (cp->cp_ecx & CPUID_INTC_ECX_PCID) {
1617 1626 add_x86_feature(featureset, X86FSET_PCID);
1618 1627 }
1619 1628 }
1620 1629
1621 1630 if (cp->cp_ecx & CPUID_INTC_ECX_X2APIC) {
1622 1631 add_x86_feature(featureset, X86FSET_X2APIC);
1623 1632 }
1624 1633 if (cp->cp_edx & CPUID_INTC_EDX_DE) {
1625 1634 add_x86_feature(featureset, X86FSET_DE);
1626 1635 }
1627 1636 #if !defined(__xpv)
1628 1637 if (cp->cp_ecx & CPUID_INTC_ECX_MON) {
1629 1638
1630 1639 /*
1631 1640 * We require the CLFLUSH instruction for erratum workaround
1632 1641 * to use MONITOR/MWAIT.
1633 1642 */
1634 1643 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) {
1635 1644 cpi->cpi_mwait.support |= MWAIT_SUPPORT;
1636 1645 add_x86_feature(featureset, X86FSET_MWAIT);
1637 1646 } else {
1638 1647 extern int idle_cpu_assert_cflush_monitor;
1639 1648
1640 1649 /*
1641 1650 * All processors we are aware of which have
1642 1651 * MONITOR/MWAIT also have CLFLUSH.
1643 1652 */
1644 1653 if (idle_cpu_assert_cflush_monitor) {
1645 1654 ASSERT((cp->cp_ecx & CPUID_INTC_ECX_MON) &&
1646 1655 (cp->cp_edx & CPUID_INTC_EDX_CLFSH));
1647 1656 }
1648 1657 }
1649 1658 }
1650 1659 #endif /* __xpv */
1651 1660
1652 1661 if (cp->cp_ecx & CPUID_INTC_ECX_VMX) {
1653 1662 add_x86_feature(featureset, X86FSET_VMX);
1654 1663 }
1655 1664
1656 1665 if (cp->cp_ecx & CPUID_INTC_ECX_RDRAND)
1657 1666 add_x86_feature(featureset, X86FSET_RDRAND);
1658 1667
1659 1668 /*
1660 1669 * Only need it first time, rest of the cpus would follow suit.
1661 1670 * we only capture this for the bootcpu.
1662 1671 */
1663 1672 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) {
1664 1673 add_x86_feature(featureset, X86FSET_CLFSH);
1665 1674 x86_clflush_size = (BITX(cp->cp_ebx, 15, 8) * 8);
1666 1675 }
1667 1676 if (is_x86_feature(featureset, X86FSET_PAE))
1668 1677 cpi->cpi_pabits = 36;
1669 1678
1670 1679 /*
1671 1680 * Hyperthreading configuration is slightly tricky on Intel
1672 1681 * and pure clones, and even trickier on AMD.
1673 1682 *
1674 1683 * (AMD chose to set the HTT bit on their CMP processors,
1675 1684 * even though they're not actually hyperthreaded. Thus it
1676 1685 * takes a bit more work to figure out what's really going
1677 1686 * on ... see the handling of the CMP_LGCY bit below)
1678 1687 */
1679 1688 if (cp->cp_edx & CPUID_INTC_EDX_HTT) {
1680 1689 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi);
1681 1690 if (cpi->cpi_ncpu_per_chip > 1)
1682 1691 add_x86_feature(featureset, X86FSET_HTT);
1683 1692 } else {
1684 1693 cpi->cpi_ncpu_per_chip = 1;
1685 1694 }
1686 1695
1687 1696 if (cpi->cpi_maxeax >= 0xD && !xsave_force_disable) {
1688 1697 struct cpuid_regs r, *ecp;
1689 1698
1690 1699 ecp = &r;
1691 1700 ecp->cp_eax = 0xD;
1692 1701 ecp->cp_ecx = 1;
1693 1702 ecp->cp_edx = ecp->cp_ebx = 0;
1694 1703 (void) __cpuid_insn(ecp);
1695 1704
1696 1705 if (ecp->cp_eax & CPUID_INTC_EAX_D_1_XSAVEOPT)
1697 1706 add_x86_feature(featureset, X86FSET_XSAVEOPT);
1698 1707 if (ecp->cp_eax & CPUID_INTC_EAX_D_1_XSAVEC)
1699 1708 add_x86_feature(featureset, X86FSET_XSAVEC);
1700 1709 if (ecp->cp_eax & CPUID_INTC_EAX_D_1_XSAVES)
1701 1710 add_x86_feature(featureset, X86FSET_XSAVES);
1702 1711 }
1703 1712
1704 1713 /*
1705 1714 * Work on the "extended" feature information, doing
1706 1715 * some basic initialization for cpuid_pass2()
1707 1716 */
1708 1717 xcpuid = 0;
1709 1718 switch (cpi->cpi_vendor) {
1710 1719 case X86_VENDOR_Intel:
1711 1720 /*
1712 1721 * On KVM we know we will have proper support for extended
1713 1722 * cpuid.
1714 1723 */
1715 1724 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf ||
1716 1725 (get_hwenv() == HW_KVM && cpi->cpi_family == 6 &&
1717 1726 (cpi->cpi_model == 6 || cpi->cpi_model == 2)))
1718 1727 xcpuid++;
1719 1728 break;
1720 1729 case X86_VENDOR_AMD:
1721 1730 if (cpi->cpi_family > 5 ||
1722 1731 (cpi->cpi_family == 5 && cpi->cpi_model >= 1))
1723 1732 xcpuid++;
1724 1733 break;
1725 1734 case X86_VENDOR_Cyrix:
1726 1735 /*
1727 1736 * Only these Cyrix CPUs are -known- to support
1728 1737 * extended cpuid operations.
1729 1738 */
1730 1739 if (x86_type == X86_TYPE_VIA_CYRIX_III ||
1731 1740 x86_type == X86_TYPE_CYRIX_GXm)
1732 1741 xcpuid++;
1733 1742 break;
1734 1743 case X86_VENDOR_Centaur:
1735 1744 case X86_VENDOR_TM:
1736 1745 default:
1737 1746 xcpuid++;
1738 1747 break;
1739 1748 }
1740 1749
1741 1750 if (xcpuid) {
1742 1751 cp = &cpi->cpi_extd[0];
1743 1752 cp->cp_eax = 0x80000000;
1744 1753 cpi->cpi_xmaxeax = __cpuid_insn(cp);
1745 1754 }
1746 1755
1747 1756 if (cpi->cpi_xmaxeax & 0x80000000) {
1748 1757
1749 1758 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX)
1750 1759 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX;
1751 1760
1752 1761 switch (cpi->cpi_vendor) {
1753 1762 case X86_VENDOR_Intel:
1754 1763 case X86_VENDOR_AMD:
1755 1764 if (cpi->cpi_xmaxeax < 0x80000001)
1756 1765 break;
1757 1766 cp = &cpi->cpi_extd[1];
1758 1767 cp->cp_eax = 0x80000001;
1759 1768 (void) __cpuid_insn(cp);
1760 1769
1761 1770 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
1762 1771 cpi->cpi_family == 5 &&
1763 1772 cpi->cpi_model == 6 &&
1764 1773 cpi->cpi_step == 6) {
1765 1774 /*
1766 1775 * K6 model 6 uses bit 10 to indicate SYSC
1767 1776 * Later models use bit 11. Fix it here.
1768 1777 */
1769 1778 if (cp->cp_edx & 0x400) {
1770 1779 cp->cp_edx &= ~0x400;
1771 1780 cp->cp_edx |= CPUID_AMD_EDX_SYSC;
1772 1781 }
1773 1782 }
1774 1783
1775 1784 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp);
1776 1785
1777 1786 /*
1778 1787 * Compute the additions to the kernel's feature word.
1779 1788 */
1780 1789 if (cp->cp_edx & CPUID_AMD_EDX_NX) {
1781 1790 add_x86_feature(featureset, X86FSET_NX);
1782 1791 }
1783 1792
1784 1793 /*
1785 1794 * Regardless whether or not we boot 64-bit,
1786 1795 * we should have a way to identify whether
1787 1796 * the CPU is capable of running 64-bit.
1788 1797 */
1789 1798 if (cp->cp_edx & CPUID_AMD_EDX_LM) {
1790 1799 add_x86_feature(featureset, X86FSET_64);
1791 1800 }
1792 1801
1793 1802 #if defined(__amd64)
1794 1803 /* 1 GB large page - enable only for 64 bit kernel */
1795 1804 if (cp->cp_edx & CPUID_AMD_EDX_1GPG) {
1796 1805 add_x86_feature(featureset, X86FSET_1GPG);
1797 1806 }
1798 1807 #endif
1799 1808
1800 1809 if ((cpi->cpi_vendor == X86_VENDOR_AMD) &&
1801 1810 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) &&
1802 1811 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) {
1803 1812 add_x86_feature(featureset, X86FSET_SSE4A);
1804 1813 }
1805 1814
1806 1815 /*
1807 1816 * If both the HTT and CMP_LGCY bits are set,
1808 1817 * then we're not actually HyperThreaded. Read
1809 1818 * "AMD CPUID Specification" for more details.
1810 1819 */
1811 1820 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
1812 1821 is_x86_feature(featureset, X86FSET_HTT) &&
1813 1822 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) {
1814 1823 remove_x86_feature(featureset, X86FSET_HTT);
1815 1824 add_x86_feature(featureset, X86FSET_CMP);
1816 1825 }
1817 1826 #if defined(__amd64)
1818 1827 /*
1819 1828 * It's really tricky to support syscall/sysret in
1820 1829 * the i386 kernel; we rely on sysenter/sysexit
1821 1830 * instead. In the amd64 kernel, things are -way-
1822 1831 * better.
1823 1832 */
1824 1833 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) {
1825 1834 add_x86_feature(featureset, X86FSET_ASYSC);
1826 1835 }
1827 1836
1828 1837 /*
1829 1838 * While we're thinking about system calls, note
1830 1839 * that AMD processors don't support sysenter
1831 1840 * in long mode at all, so don't try to program them.
1832 1841 */
1833 1842 if (x86_vendor == X86_VENDOR_AMD) {
1834 1843 remove_x86_feature(featureset, X86FSET_SEP);
1835 1844 }
1836 1845 #endif
1837 1846 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) {
1838 1847 add_x86_feature(featureset, X86FSET_TSCP);
1839 1848 }
1840 1849
1841 1850 if (cp->cp_ecx & CPUID_AMD_ECX_SVM) {
1842 1851 add_x86_feature(featureset, X86FSET_SVM);
1843 1852 }
1844 1853
1845 1854 if (cp->cp_ecx & CPUID_AMD_ECX_TOPOEXT) {
1846 1855 add_x86_feature(featureset, X86FSET_TOPOEXT);
1847 1856 }
1848 1857 break;
1849 1858 default:
1850 1859 break;
1851 1860 }
1852 1861
1853 1862 /*
1854 1863 * Get CPUID data about processor cores and hyperthreads.
1855 1864 */
1856 1865 switch (cpi->cpi_vendor) {
1857 1866 case X86_VENDOR_Intel:
1858 1867 if (cpi->cpi_maxeax >= 4) {
1859 1868 cp = &cpi->cpi_std[4];
1860 1869 cp->cp_eax = 4;
1861 1870 cp->cp_ecx = 0;
1862 1871 (void) __cpuid_insn(cp);
1863 1872 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp);
1864 1873 }
1865 1874 /*FALLTHROUGH*/
1866 1875 case X86_VENDOR_AMD:
1867 1876 if (cpi->cpi_xmaxeax < 0x80000008)
1868 1877 break;
1869 1878 cp = &cpi->cpi_extd[8];
1870 1879 cp->cp_eax = 0x80000008;
1871 1880 (void) __cpuid_insn(cp);
1872 1881 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp);
1873 1882
1874 1883 /*
1875 1884 * Virtual and physical address limits from
1876 1885 * cpuid override previously guessed values.
1877 1886 */
1878 1887 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0);
1879 1888 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8);
1880 1889 break;
1881 1890 default:
1882 1891 break;
1883 1892 }
1884 1893
1885 1894 /*
1886 1895 * Derive the number of cores per chip
1887 1896 */
1888 1897 switch (cpi->cpi_vendor) {
1889 1898 case X86_VENDOR_Intel:
1890 1899 if (cpi->cpi_maxeax < 4) {
1891 1900 cpi->cpi_ncore_per_chip = 1;
1892 1901 break;
1893 1902 } else {
1894 1903 cpi->cpi_ncore_per_chip =
1895 1904 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1;
1896 1905 }
1897 1906 break;
1898 1907 case X86_VENDOR_AMD:
1899 1908 if (cpi->cpi_xmaxeax < 0x80000008) {
1900 1909 cpi->cpi_ncore_per_chip = 1;
1901 1910 break;
1902 1911 } else {
1903 1912 /*
1904 1913 * On family 0xf cpuid fn 2 ECX[7:0] "NC" is
1905 1914 * 1 less than the number of physical cores on
1906 1915 * the chip. In family 0x10 this value can
1907 1916 * be affected by "downcoring" - it reflects
1908 1917 * 1 less than the number of cores actually
1909 1918 * enabled on this node.
1910 1919 */
1911 1920 cpi->cpi_ncore_per_chip =
1912 1921 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1;
1913 1922 }
1914 1923 break;
1915 1924 default:
1916 1925 cpi->cpi_ncore_per_chip = 1;
1917 1926 break;
1918 1927 }
1919 1928
1920 1929 /*
1921 1930 * Get CPUID data about TSC Invariance in Deep C-State.
1922 1931 */
1923 1932 switch (cpi->cpi_vendor) {
1924 1933 case X86_VENDOR_Intel:
1925 1934 if (cpi->cpi_maxeax >= 7) {
1926 1935 cp = &cpi->cpi_extd[7];
1927 1936 cp->cp_eax = 0x80000007;
1928 1937 cp->cp_ecx = 0;
1929 1938 (void) __cpuid_insn(cp);
1930 1939 }
1931 1940 break;
1932 1941 default:
1933 1942 break;
1934 1943 }
1935 1944 } else {
1936 1945 cpi->cpi_ncore_per_chip = 1;
1937 1946 }
1938 1947
1939 1948 /*
1940 1949 * If more than one core, then this processor is CMP.
1941 1950 */
1942 1951 if (cpi->cpi_ncore_per_chip > 1) {
1943 1952 add_x86_feature(featureset, X86FSET_CMP);
1944 1953 }
1945 1954
1946 1955 /*
1947 1956 * If the number of cores is the same as the number
1948 1957 * of CPUs, then we cannot have HyperThreading.
1949 1958 */
1950 1959 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) {
1951 1960 remove_x86_feature(featureset, X86FSET_HTT);
1952 1961 }
1953 1962
1954 1963 cpi->cpi_apicid = CPI_APIC_ID(cpi);
1955 1964 cpi->cpi_procnodes_per_pkg = 1;
1956 1965 cpi->cpi_cores_per_compunit = 1;
1957 1966 if (is_x86_feature(featureset, X86FSET_HTT) == B_FALSE &&
1958 1967 is_x86_feature(featureset, X86FSET_CMP) == B_FALSE) {
1959 1968 /*
1960 1969 * Single-core single-threaded processors.
1961 1970 */
1962 1971 cpi->cpi_chipid = -1;
1963 1972 cpi->cpi_clogid = 0;
1964 1973 cpi->cpi_coreid = cpu->cpu_id;
1965 1974 cpi->cpi_pkgcoreid = 0;
1966 1975 if (cpi->cpi_vendor == X86_VENDOR_AMD)
1967 1976 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 3, 0);
1968 1977 else
1969 1978 cpi->cpi_procnodeid = cpi->cpi_chipid;
1970 1979 } else if (cpi->cpi_ncpu_per_chip > 1) {
1971 1980 if (cpi->cpi_vendor == X86_VENDOR_Intel)
1972 1981 cpuid_intel_getids(cpu, featureset);
1973 1982 else if (cpi->cpi_vendor == X86_VENDOR_AMD)
1974 1983 cpuid_amd_getids(cpu);
1975 1984 else {
1976 1985 /*
1977 1986 * All other processors are currently
1978 1987 * assumed to have single cores.
1979 1988 */
1980 1989 cpi->cpi_coreid = cpi->cpi_chipid;
1981 1990 cpi->cpi_pkgcoreid = 0;
1982 1991 cpi->cpi_procnodeid = cpi->cpi_chipid;
1983 1992 cpi->cpi_compunitid = cpi->cpi_chipid;
1984 1993 }
1985 1994 }
1986 1995
1987 1996 /*
1988 1997 * Synthesize chip "revision" and socket type
1989 1998 */
1990 1999 cpi->cpi_chiprev = _cpuid_chiprev(cpi->cpi_vendor, cpi->cpi_family,
1991 2000 cpi->cpi_model, cpi->cpi_step);
1992 2001 cpi->cpi_chiprevstr = _cpuid_chiprevstr(cpi->cpi_vendor,
1993 2002 cpi->cpi_family, cpi->cpi_model, cpi->cpi_step);
1994 2003 cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family,
1995 2004 cpi->cpi_model, cpi->cpi_step);
1996 2005
1997 2006 /*
1998 2007 * While we're here, check for the AMD "Error Pointer Zero/Restore"
1999 2008 * feature. This can be used to setup the FP save handlers
2000 2009 * appropriately.
2001 2010 */
2002 2011 if (cpi->cpi_vendor == X86_VENDOR_AMD) {
2003 2012 if (cpi->cpi_xmaxeax >= 0x80000008 &&
2004 2013 cpi->cpi_extd[8].cp_ebx & CPUID_AMD_EBX_ERR_PTR_ZERO) {
2005 2014 /* Special handling for AMD FP not necessary. */
2006 2015 cpi->cpi_fp_amd_save = 0;
2007 2016 } else {
2008 2017 cpi->cpi_fp_amd_save = 1;
2009 2018 }
2010 2019 }
2011 2020
2012 2021 /*
2013 2022 * Check the processor leaves that are used for security features.
2014 2023 */
2015 2024 cpuid_scan_security(cpu, featureset);
2016 2025
2017 2026 pass1_done:
2018 2027 cpi->cpi_pass = 1;
2019 2028 }
2020 2029
2021 2030 /*
2022 2031 * Make copies of the cpuid table entries we depend on, in
2023 2032 * part for ease of parsing now, in part so that we have only
2024 2033 * one place to correct any of it, in part for ease of
2025 2034 * later export to userland, and in part so we can look at
2026 2035 * this stuff in a crash dump.
2027 2036 */
2028 2037
2029 2038 /*ARGSUSED*/
2030 2039 void
2031 2040 cpuid_pass2(cpu_t *cpu)
2032 2041 {
2033 2042 uint_t n, nmax;
2034 2043 int i;
2035 2044 struct cpuid_regs *cp;
2036 2045 uint8_t *dp;
2037 2046 uint32_t *iptr;
2038 2047 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
2039 2048
2040 2049 ASSERT(cpi->cpi_pass == 1);
2041 2050
2042 2051 if (cpi->cpi_maxeax < 1)
2043 2052 goto pass2_done;
2044 2053
2045 2054 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD)
2046 2055 nmax = NMAX_CPI_STD;
2047 2056 /*
2048 2057 * (We already handled n == 0 and n == 1 in pass 1)
2049 2058 */
2050 2059 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) {
2051 2060 cp->cp_eax = n;
2052 2061
2053 2062 /*
2054 2063 * n == 7 was handled in pass 1
2055 2064 */
2056 2065 if (n == 7)
2057 2066 continue;
2058 2067
2059 2068 /*
2060 2069 * CPUID function 4 expects %ecx to be initialized
2061 2070 * with an index which indicates which cache to return
2062 2071 * information about. The OS is expected to call function 4
2063 2072 * with %ecx set to 0, 1, 2, ... until it returns with
2064 2073 * EAX[4:0] set to 0, which indicates there are no more
2065 2074 * caches.
2066 2075 *
2067 2076 * Here, populate cpi_std[4] with the information returned by
2068 2077 * function 4 when %ecx == 0, and do the rest in cpuid_pass3()
2069 2078 * when dynamic memory allocation becomes available.
2070 2079 *
2071 2080 * Note: we need to explicitly initialize %ecx here, since
2072 2081 * function 4 may have been previously invoked.
2073 2082 */
2074 2083 if (n == 4)
2075 2084 cp->cp_ecx = 0;
2076 2085
2077 2086 (void) __cpuid_insn(cp);
2078 2087 platform_cpuid_mangle(cpi->cpi_vendor, n, cp);
2079 2088 switch (n) {
2080 2089 case 2:
2081 2090 /*
2082 2091 * "the lower 8 bits of the %eax register
2083 2092 * contain a value that identifies the number
2084 2093 * of times the cpuid [instruction] has to be
2085 2094 * executed to obtain a complete image of the
2086 2095 * processor's caching systems."
2087 2096 *
2088 2097 * How *do* they make this stuff up?
2089 2098 */
2090 2099 cpi->cpi_ncache = sizeof (*cp) *
2091 2100 BITX(cp->cp_eax, 7, 0);
2092 2101 if (cpi->cpi_ncache == 0)
2093 2102 break;
2094 2103 cpi->cpi_ncache--; /* skip count byte */
2095 2104
2096 2105 /*
2097 2106 * Well, for now, rather than attempt to implement
2098 2107 * this slightly dubious algorithm, we just look
2099 2108 * at the first 15 ..
2100 2109 */
2101 2110 if (cpi->cpi_ncache > (sizeof (*cp) - 1))
2102 2111 cpi->cpi_ncache = sizeof (*cp) - 1;
2103 2112
2104 2113 dp = cpi->cpi_cacheinfo;
2105 2114 if (BITX(cp->cp_eax, 31, 31) == 0) {
2106 2115 uint8_t *p = (void *)&cp->cp_eax;
2107 2116 for (i = 1; i < 4; i++)
2108 2117 if (p[i] != 0)
2109 2118 *dp++ = p[i];
2110 2119 }
2111 2120 if (BITX(cp->cp_ebx, 31, 31) == 0) {
2112 2121 uint8_t *p = (void *)&cp->cp_ebx;
2113 2122 for (i = 0; i < 4; i++)
2114 2123 if (p[i] != 0)
2115 2124 *dp++ = p[i];
2116 2125 }
2117 2126 if (BITX(cp->cp_ecx, 31, 31) == 0) {
2118 2127 uint8_t *p = (void *)&cp->cp_ecx;
2119 2128 for (i = 0; i < 4; i++)
2120 2129 if (p[i] != 0)
2121 2130 *dp++ = p[i];
2122 2131 }
2123 2132 if (BITX(cp->cp_edx, 31, 31) == 0) {
2124 2133 uint8_t *p = (void *)&cp->cp_edx;
2125 2134 for (i = 0; i < 4; i++)
2126 2135 if (p[i] != 0)
2127 2136 *dp++ = p[i];
2128 2137 }
2129 2138 break;
2130 2139
2131 2140 case 3: /* Processor serial number, if PSN supported */
2132 2141 break;
2133 2142
2134 2143 case 4: /* Deterministic cache parameters */
2135 2144 break;
2136 2145
2137 2146 case 5: /* Monitor/Mwait parameters */
2138 2147 {
2139 2148 size_t mwait_size;
2140 2149
2141 2150 /*
2142 2151 * check cpi_mwait.support which was set in cpuid_pass1
2143 2152 */
2144 2153 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT))
2145 2154 break;
2146 2155
2147 2156 /*
2148 2157 * Protect ourself from insane mwait line size.
2149 2158 * Workaround for incomplete hardware emulator(s).
2150 2159 */
2151 2160 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi);
2152 2161 if (mwait_size < sizeof (uint32_t) ||
2153 2162 !ISP2(mwait_size)) {
2154 2163 #if DEBUG
2155 2164 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait "
2156 2165 "size %ld", cpu->cpu_id, (long)mwait_size);
2157 2166 #endif
2158 2167 break;
2159 2168 }
2160 2169
2161 2170 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi);
2162 2171 cpi->cpi_mwait.mon_max = mwait_size;
2163 2172 if (MWAIT_EXTENSION(cpi)) {
2164 2173 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS;
2165 2174 if (MWAIT_INT_ENABLE(cpi))
2166 2175 cpi->cpi_mwait.support |=
2167 2176 MWAIT_ECX_INT_ENABLE;
2168 2177 }
2169 2178 break;
2170 2179 }
2171 2180 default:
2172 2181 break;
2173 2182 }
2174 2183 }
2175 2184
2176 2185 if (cpi->cpi_maxeax >= 0xB && cpi->cpi_vendor == X86_VENDOR_Intel) {
2177 2186 struct cpuid_regs regs;
2178 2187
2179 2188 cp = ®s;
2180 2189 cp->cp_eax = 0xB;
2181 2190 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0;
2182 2191
2183 2192 (void) __cpuid_insn(cp);
2184 2193
2185 2194 /*
2186 2195 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which
2187 2196 * indicates that the extended topology enumeration leaf is
2188 2197 * available.
2189 2198 */
2190 2199 if (cp->cp_ebx) {
2191 2200 uint32_t x2apic_id;
2192 2201 uint_t coreid_shift = 0;
2193 2202 uint_t ncpu_per_core = 1;
2194 2203 uint_t chipid_shift = 0;
2195 2204 uint_t ncpu_per_chip = 1;
2196 2205 uint_t i;
2197 2206 uint_t level;
2198 2207
2199 2208 for (i = 0; i < CPI_FNB_ECX_MAX; i++) {
2200 2209 cp->cp_eax = 0xB;
2201 2210 cp->cp_ecx = i;
2202 2211
2203 2212 (void) __cpuid_insn(cp);
2204 2213 level = CPI_CPU_LEVEL_TYPE(cp);
2205 2214
2206 2215 if (level == 1) {
2207 2216 x2apic_id = cp->cp_edx;
2208 2217 coreid_shift = BITX(cp->cp_eax, 4, 0);
2209 2218 ncpu_per_core = BITX(cp->cp_ebx, 15, 0);
2210 2219 } else if (level == 2) {
2211 2220 x2apic_id = cp->cp_edx;
2212 2221 chipid_shift = BITX(cp->cp_eax, 4, 0);
2213 2222 ncpu_per_chip = BITX(cp->cp_ebx, 15, 0);
2214 2223 }
2215 2224 }
2216 2225
2217 2226 cpi->cpi_apicid = x2apic_id;
2218 2227 cpi->cpi_ncpu_per_chip = ncpu_per_chip;
2219 2228 cpi->cpi_ncore_per_chip = ncpu_per_chip /
2220 2229 ncpu_per_core;
2221 2230 cpi->cpi_chipid = x2apic_id >> chipid_shift;
2222 2231 cpi->cpi_clogid = x2apic_id & ((1 << chipid_shift) - 1);
2223 2232 cpi->cpi_coreid = x2apic_id >> coreid_shift;
2224 2233 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift;
2225 2234 }
2226 2235
2227 2236 /* Make cp NULL so that we don't stumble on others */
2228 2237 cp = NULL;
2229 2238 }
2230 2239
2231 2240 /*
2232 2241 * XSAVE enumeration
2233 2242 */
2234 2243 if (cpi->cpi_maxeax >= 0xD) {
2235 2244 struct cpuid_regs regs;
2236 2245 boolean_t cpuid_d_valid = B_TRUE;
2237 2246
2238 2247 cp = ®s;
2239 2248 cp->cp_eax = 0xD;
2240 2249 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0;
2241 2250
2242 2251 (void) __cpuid_insn(cp);
2243 2252
2244 2253 /*
2245 2254 * Sanity checks for debug
2246 2255 */
2247 2256 if ((cp->cp_eax & XFEATURE_LEGACY_FP) == 0 ||
2248 2257 (cp->cp_eax & XFEATURE_SSE) == 0) {
2249 2258 cpuid_d_valid = B_FALSE;
2250 2259 }
2251 2260
2252 2261 cpi->cpi_xsave.xsav_hw_features_low = cp->cp_eax;
2253 2262 cpi->cpi_xsave.xsav_hw_features_high = cp->cp_edx;
2254 2263 cpi->cpi_xsave.xsav_max_size = cp->cp_ecx;
2255 2264
2256 2265 /*
2257 2266 * If the hw supports AVX, get the size and offset in the save
2258 2267 * area for the ymm state.
2259 2268 */
2260 2269 if (cpi->cpi_xsave.xsav_hw_features_low & XFEATURE_AVX) {
2261 2270 cp->cp_eax = 0xD;
2262 2271 cp->cp_ecx = 2;
2263 2272 cp->cp_edx = cp->cp_ebx = 0;
2264 2273
2265 2274 (void) __cpuid_insn(cp);
2266 2275
2267 2276 if (cp->cp_ebx != CPUID_LEAFD_2_YMM_OFFSET ||
2268 2277 cp->cp_eax != CPUID_LEAFD_2_YMM_SIZE) {
2269 2278 cpuid_d_valid = B_FALSE;
2270 2279 }
2271 2280
2272 2281 cpi->cpi_xsave.ymm_size = cp->cp_eax;
2273 2282 cpi->cpi_xsave.ymm_offset = cp->cp_ebx;
2274 2283 }
2275 2284
2276 2285 /*
2277 2286 * If the hw supports MPX, get the size and offset in the
2278 2287 * save area for BNDREGS and BNDCSR.
2279 2288 */
2280 2289 if (cpi->cpi_xsave.xsav_hw_features_low & XFEATURE_MPX) {
2281 2290 cp->cp_eax = 0xD;
2282 2291 cp->cp_ecx = 3;
2283 2292 cp->cp_edx = cp->cp_ebx = 0;
2284 2293
2285 2294 (void) __cpuid_insn(cp);
2286 2295
2287 2296 cpi->cpi_xsave.bndregs_size = cp->cp_eax;
2288 2297 cpi->cpi_xsave.bndregs_offset = cp->cp_ebx;
2289 2298
2290 2299 cp->cp_eax = 0xD;
2291 2300 cp->cp_ecx = 4;
2292 2301 cp->cp_edx = cp->cp_ebx = 0;
2293 2302
2294 2303 (void) __cpuid_insn(cp);
2295 2304
2296 2305 cpi->cpi_xsave.bndcsr_size = cp->cp_eax;
2297 2306 cpi->cpi_xsave.bndcsr_offset = cp->cp_ebx;
2298 2307 }
2299 2308
2300 2309 /*
2301 2310 * If the hw supports AVX512, get the size and offset in the
2302 2311 * save area for the opmask registers and zmm state.
2303 2312 */
2304 2313 if (cpi->cpi_xsave.xsav_hw_features_low & XFEATURE_AVX512) {
2305 2314 cp->cp_eax = 0xD;
2306 2315 cp->cp_ecx = 5;
2307 2316 cp->cp_edx = cp->cp_ebx = 0;
2308 2317
2309 2318 (void) __cpuid_insn(cp);
2310 2319
2311 2320 cpi->cpi_xsave.opmask_size = cp->cp_eax;
2312 2321 cpi->cpi_xsave.opmask_offset = cp->cp_ebx;
2313 2322
2314 2323 cp->cp_eax = 0xD;
2315 2324 cp->cp_ecx = 6;
2316 2325 cp->cp_edx = cp->cp_ebx = 0;
2317 2326
2318 2327 (void) __cpuid_insn(cp);
2319 2328
2320 2329 cpi->cpi_xsave.zmmlo_size = cp->cp_eax;
2321 2330 cpi->cpi_xsave.zmmlo_offset = cp->cp_ebx;
2322 2331
2323 2332 cp->cp_eax = 0xD;
2324 2333 cp->cp_ecx = 7;
2325 2334 cp->cp_edx = cp->cp_ebx = 0;
2326 2335
2327 2336 (void) __cpuid_insn(cp);
2328 2337
2329 2338 cpi->cpi_xsave.zmmhi_size = cp->cp_eax;
2330 2339 cpi->cpi_xsave.zmmhi_offset = cp->cp_ebx;
2331 2340 }
2332 2341
2333 2342 if (is_x86_feature(x86_featureset, X86FSET_XSAVE)) {
2334 2343 xsave_state_size = 0;
2335 2344 } else if (cpuid_d_valid) {
2336 2345 xsave_state_size = cpi->cpi_xsave.xsav_max_size;
2337 2346 } else {
2338 2347 /* Broken CPUID 0xD, probably in HVM */
2339 2348 cmn_err(CE_WARN, "cpu%d: CPUID.0xD returns invalid "
2340 2349 "value: hw_low = %d, hw_high = %d, xsave_size = %d"
2341 2350 ", ymm_size = %d, ymm_offset = %d\n",
2342 2351 cpu->cpu_id, cpi->cpi_xsave.xsav_hw_features_low,
2343 2352 cpi->cpi_xsave.xsav_hw_features_high,
2344 2353 (int)cpi->cpi_xsave.xsav_max_size,
2345 2354 (int)cpi->cpi_xsave.ymm_size,
2346 2355 (int)cpi->cpi_xsave.ymm_offset);
2347 2356
2348 2357 if (xsave_state_size != 0) {
2349 2358 /*
2350 2359 * This must be a non-boot CPU. We cannot
2351 2360 * continue, because boot cpu has already
2352 2361 * enabled XSAVE.
2353 2362 */
2354 2363 ASSERT(cpu->cpu_id != 0);
2355 2364 cmn_err(CE_PANIC, "cpu%d: we have already "
2356 2365 "enabled XSAVE on boot cpu, cannot "
2357 2366 "continue.", cpu->cpu_id);
2358 2367 } else {
2359 2368 /*
2360 2369 * If we reached here on the boot CPU, it's also
2361 2370 * almost certain that we'll reach here on the
2362 2371 * non-boot CPUs. When we're here on a boot CPU
2363 2372 * we should disable the feature, on a non-boot
2364 2373 * CPU we need to confirm that we have.
2365 2374 */
2366 2375 if (cpu->cpu_id == 0) {
2367 2376 remove_x86_feature(x86_featureset,
2368 2377 X86FSET_XSAVE);
2369 2378 remove_x86_feature(x86_featureset,
2370 2379 X86FSET_AVX);
2371 2380 remove_x86_feature(x86_featureset,
2372 2381 X86FSET_F16C);
2373 2382 remove_x86_feature(x86_featureset,
2374 2383 X86FSET_BMI1);
2375 2384 remove_x86_feature(x86_featureset,
2376 2385 X86FSET_BMI2);
2377 2386 remove_x86_feature(x86_featureset,
2378 2387 X86FSET_FMA);
2379 2388 remove_x86_feature(x86_featureset,
2380 2389 X86FSET_AVX2);
2381 2390 remove_x86_feature(x86_featureset,
2382 2391 X86FSET_MPX);
2383 2392 remove_x86_feature(x86_featureset,
2384 2393 X86FSET_AVX512F);
2385 2394 remove_x86_feature(x86_featureset,
2386 2395 X86FSET_AVX512DQ);
2387 2396 remove_x86_feature(x86_featureset,
2388 2397 X86FSET_AVX512PF);
2389 2398 remove_x86_feature(x86_featureset,
2390 2399 X86FSET_AVX512ER);
2391 2400 remove_x86_feature(x86_featureset,
2392 2401 X86FSET_AVX512CD);
2393 2402 remove_x86_feature(x86_featureset,
2394 2403 X86FSET_AVX512BW);
2395 2404 remove_x86_feature(x86_featureset,
2396 2405 X86FSET_AVX512VL);
2397 2406 remove_x86_feature(x86_featureset,
2398 2407 X86FSET_AVX512FMA);
2399 2408 remove_x86_feature(x86_featureset,
2400 2409 X86FSET_AVX512VBMI);
2401 2410 remove_x86_feature(x86_featureset,
2402 2411 X86FSET_AVX512VPOPCDQ);
2403 2412 remove_x86_feature(x86_featureset,
2404 2413 X86FSET_AVX512NNIW);
2405 2414 remove_x86_feature(x86_featureset,
2406 2415 X86FSET_AVX512FMAPS);
2407 2416
2408 2417 CPI_FEATURES_ECX(cpi) &=
2409 2418 ~CPUID_INTC_ECX_XSAVE;
2410 2419 CPI_FEATURES_ECX(cpi) &=
2411 2420 ~CPUID_INTC_ECX_AVX;
2412 2421 CPI_FEATURES_ECX(cpi) &=
2413 2422 ~CPUID_INTC_ECX_F16C;
2414 2423 CPI_FEATURES_ECX(cpi) &=
2415 2424 ~CPUID_INTC_ECX_FMA;
2416 2425 CPI_FEATURES_7_0_EBX(cpi) &=
2417 2426 ~CPUID_INTC_EBX_7_0_BMI1;
2418 2427 CPI_FEATURES_7_0_EBX(cpi) &=
2419 2428 ~CPUID_INTC_EBX_7_0_BMI2;
2420 2429 CPI_FEATURES_7_0_EBX(cpi) &=
2421 2430 ~CPUID_INTC_EBX_7_0_AVX2;
2422 2431 CPI_FEATURES_7_0_EBX(cpi) &=
2423 2432 ~CPUID_INTC_EBX_7_0_MPX;
2424 2433 CPI_FEATURES_7_0_EBX(cpi) &=
2425 2434 ~CPUID_INTC_EBX_7_0_ALL_AVX512;
2426 2435
2427 2436 CPI_FEATURES_7_0_ECX(cpi) &=
2428 2437 ~CPUID_INTC_ECX_7_0_ALL_AVX512;
2429 2438
2430 2439 CPI_FEATURES_7_0_EDX(cpi) &=
2431 2440 ~CPUID_INTC_EDX_7_0_ALL_AVX512;
2432 2441
2433 2442 xsave_force_disable = B_TRUE;
2434 2443 } else {
2435 2444 VERIFY(is_x86_feature(x86_featureset,
2436 2445 X86FSET_XSAVE) == B_FALSE);
2437 2446 }
2438 2447 }
2439 2448 }
2440 2449 }
2441 2450
2442 2451
2443 2452 if ((cpi->cpi_xmaxeax & 0x80000000) == 0)
2444 2453 goto pass2_done;
2445 2454
2446 2455 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD)
2447 2456 nmax = NMAX_CPI_EXTD;
2448 2457 /*
2449 2458 * Copy the extended properties, fixing them as we go.
2450 2459 * (We already handled n == 0 and n == 1 in pass 1)
2451 2460 */
2452 2461 iptr = (void *)cpi->cpi_brandstr;
2453 2462 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) {
2454 2463 cp->cp_eax = 0x80000000 + n;
2455 2464 (void) __cpuid_insn(cp);
2456 2465 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp);
2457 2466 switch (n) {
2458 2467 case 2:
2459 2468 case 3:
2460 2469 case 4:
2461 2470 /*
2462 2471 * Extract the brand string
2463 2472 */
2464 2473 *iptr++ = cp->cp_eax;
2465 2474 *iptr++ = cp->cp_ebx;
2466 2475 *iptr++ = cp->cp_ecx;
2467 2476 *iptr++ = cp->cp_edx;
2468 2477 break;
2469 2478 case 5:
2470 2479 switch (cpi->cpi_vendor) {
2471 2480 case X86_VENDOR_AMD:
2472 2481 /*
2473 2482 * The Athlon and Duron were the first
2474 2483 * parts to report the sizes of the
2475 2484 * TLB for large pages. Before then,
2476 2485 * we don't trust the data.
2477 2486 */
2478 2487 if (cpi->cpi_family < 6 ||
2479 2488 (cpi->cpi_family == 6 &&
2480 2489 cpi->cpi_model < 1))
2481 2490 cp->cp_eax = 0;
2482 2491 break;
2483 2492 default:
2484 2493 break;
2485 2494 }
2486 2495 break;
2487 2496 case 6:
2488 2497 switch (cpi->cpi_vendor) {
2489 2498 case X86_VENDOR_AMD:
2490 2499 /*
2491 2500 * The Athlon and Duron were the first
2492 2501 * AMD parts with L2 TLB's.
2493 2502 * Before then, don't trust the data.
2494 2503 */
2495 2504 if (cpi->cpi_family < 6 ||
2496 2505 cpi->cpi_family == 6 &&
2497 2506 cpi->cpi_model < 1)
2498 2507 cp->cp_eax = cp->cp_ebx = 0;
2499 2508 /*
2500 2509 * AMD Duron rev A0 reports L2
2501 2510 * cache size incorrectly as 1K
2502 2511 * when it is really 64K
2503 2512 */
2504 2513 if (cpi->cpi_family == 6 &&
2505 2514 cpi->cpi_model == 3 &&
2506 2515 cpi->cpi_step == 0) {
2507 2516 cp->cp_ecx &= 0xffff;
2508 2517 cp->cp_ecx |= 0x400000;
2509 2518 }
2510 2519 break;
2511 2520 case X86_VENDOR_Cyrix: /* VIA C3 */
2512 2521 /*
2513 2522 * VIA C3 processors are a bit messed
2514 2523 * up w.r.t. encoding cache sizes in %ecx
2515 2524 */
2516 2525 if (cpi->cpi_family != 6)
2517 2526 break;
2518 2527 /*
2519 2528 * model 7 and 8 were incorrectly encoded
2520 2529 *
2521 2530 * xxx is model 8 really broken?
2522 2531 */
2523 2532 if (cpi->cpi_model == 7 ||
2524 2533 cpi->cpi_model == 8)
2525 2534 cp->cp_ecx =
2526 2535 BITX(cp->cp_ecx, 31, 24) << 16 |
2527 2536 BITX(cp->cp_ecx, 23, 16) << 12 |
2528 2537 BITX(cp->cp_ecx, 15, 8) << 8 |
2529 2538 BITX(cp->cp_ecx, 7, 0);
2530 2539 /*
2531 2540 * model 9 stepping 1 has wrong associativity
2532 2541 */
2533 2542 if (cpi->cpi_model == 9 && cpi->cpi_step == 1)
2534 2543 cp->cp_ecx |= 8 << 12;
2535 2544 break;
2536 2545 case X86_VENDOR_Intel:
2537 2546 /*
2538 2547 * Extended L2 Cache features function.
2539 2548 * First appeared on Prescott.
2540 2549 */
2541 2550 default:
2542 2551 break;
2543 2552 }
2544 2553 break;
2545 2554 default:
2546 2555 break;
2547 2556 }
2548 2557 }
2549 2558
2550 2559 pass2_done:
2551 2560 cpi->cpi_pass = 2;
2552 2561 }
2553 2562
2554 2563 static const char *
2555 2564 intel_cpubrand(const struct cpuid_info *cpi)
2556 2565 {
2557 2566 int i;
2558 2567
2559 2568 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) ||
2560 2569 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5)
2561 2570 return ("i486");
2562 2571
2563 2572 switch (cpi->cpi_family) {
2564 2573 case 5:
2565 2574 return ("Intel Pentium(r)");
2566 2575 case 6:
2567 2576 switch (cpi->cpi_model) {
2568 2577 uint_t celeron, xeon;
2569 2578 const struct cpuid_regs *cp;
2570 2579 case 0:
2571 2580 case 1:
2572 2581 case 2:
2573 2582 return ("Intel Pentium(r) Pro");
2574 2583 case 3:
2575 2584 case 4:
2576 2585 return ("Intel Pentium(r) II");
2577 2586 case 6:
2578 2587 return ("Intel Celeron(r)");
2579 2588 case 5:
2580 2589 case 7:
2581 2590 celeron = xeon = 0;
2582 2591 cp = &cpi->cpi_std[2]; /* cache info */
2583 2592
2584 2593 for (i = 1; i < 4; i++) {
2585 2594 uint_t tmp;
2586 2595
2587 2596 tmp = (cp->cp_eax >> (8 * i)) & 0xff;
2588 2597 if (tmp == 0x40)
2589 2598 celeron++;
2590 2599 if (tmp >= 0x44 && tmp <= 0x45)
2591 2600 xeon++;
2592 2601 }
2593 2602
2594 2603 for (i = 0; i < 2; i++) {
2595 2604 uint_t tmp;
2596 2605
2597 2606 tmp = (cp->cp_ebx >> (8 * i)) & 0xff;
2598 2607 if (tmp == 0x40)
2599 2608 celeron++;
2600 2609 else if (tmp >= 0x44 && tmp <= 0x45)
2601 2610 xeon++;
2602 2611 }
2603 2612
2604 2613 for (i = 0; i < 4; i++) {
2605 2614 uint_t tmp;
2606 2615
2607 2616 tmp = (cp->cp_ecx >> (8 * i)) & 0xff;
2608 2617 if (tmp == 0x40)
2609 2618 celeron++;
2610 2619 else if (tmp >= 0x44 && tmp <= 0x45)
2611 2620 xeon++;
2612 2621 }
2613 2622
2614 2623 for (i = 0; i < 4; i++) {
2615 2624 uint_t tmp;
2616 2625
2617 2626 tmp = (cp->cp_edx >> (8 * i)) & 0xff;
2618 2627 if (tmp == 0x40)
2619 2628 celeron++;
2620 2629 else if (tmp >= 0x44 && tmp <= 0x45)
2621 2630 xeon++;
2622 2631 }
2623 2632
2624 2633 if (celeron)
2625 2634 return ("Intel Celeron(r)");
2626 2635 if (xeon)
2627 2636 return (cpi->cpi_model == 5 ?
2628 2637 "Intel Pentium(r) II Xeon(tm)" :
2629 2638 "Intel Pentium(r) III Xeon(tm)");
2630 2639 return (cpi->cpi_model == 5 ?
2631 2640 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" :
2632 2641 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)");
2633 2642 default:
2634 2643 break;
2635 2644 }
2636 2645 default:
2637 2646 break;
2638 2647 }
2639 2648
2640 2649 /* BrandID is present if the field is nonzero */
2641 2650 if (cpi->cpi_brandid != 0) {
2642 2651 static const struct {
2643 2652 uint_t bt_bid;
2644 2653 const char *bt_str;
2645 2654 } brand_tbl[] = {
2646 2655 { 0x1, "Intel(r) Celeron(r)" },
2647 2656 { 0x2, "Intel(r) Pentium(r) III" },
2648 2657 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" },
2649 2658 { 0x4, "Intel(r) Pentium(r) III" },
2650 2659 { 0x6, "Mobile Intel(r) Pentium(r) III" },
2651 2660 { 0x7, "Mobile Intel(r) Celeron(r)" },
2652 2661 { 0x8, "Intel(r) Pentium(r) 4" },
2653 2662 { 0x9, "Intel(r) Pentium(r) 4" },
2654 2663 { 0xa, "Intel(r) Celeron(r)" },
2655 2664 { 0xb, "Intel(r) Xeon(tm)" },
2656 2665 { 0xc, "Intel(r) Xeon(tm) MP" },
2657 2666 { 0xe, "Mobile Intel(r) Pentium(r) 4" },
2658 2667 { 0xf, "Mobile Intel(r) Celeron(r)" },
2659 2668 { 0x11, "Mobile Genuine Intel(r)" },
2660 2669 { 0x12, "Intel(r) Celeron(r) M" },
2661 2670 { 0x13, "Mobile Intel(r) Celeron(r)" },
2662 2671 { 0x14, "Intel(r) Celeron(r)" },
2663 2672 { 0x15, "Mobile Genuine Intel(r)" },
2664 2673 { 0x16, "Intel(r) Pentium(r) M" },
2665 2674 { 0x17, "Mobile Intel(r) Celeron(r)" }
2666 2675 };
2667 2676 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]);
2668 2677 uint_t sgn;
2669 2678
2670 2679 sgn = (cpi->cpi_family << 8) |
2671 2680 (cpi->cpi_model << 4) | cpi->cpi_step;
2672 2681
2673 2682 for (i = 0; i < btblmax; i++)
2674 2683 if (brand_tbl[i].bt_bid == cpi->cpi_brandid)
2675 2684 break;
2676 2685 if (i < btblmax) {
2677 2686 if (sgn == 0x6b1 && cpi->cpi_brandid == 3)
2678 2687 return ("Intel(r) Celeron(r)");
2679 2688 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb)
2680 2689 return ("Intel(r) Xeon(tm) MP");
2681 2690 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe)
2682 2691 return ("Intel(r) Xeon(tm)");
2683 2692 return (brand_tbl[i].bt_str);
2684 2693 }
2685 2694 }
2686 2695
2687 2696 return (NULL);
2688 2697 }
2689 2698
2690 2699 static const char *
2691 2700 amd_cpubrand(const struct cpuid_info *cpi)
2692 2701 {
2693 2702 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) ||
2694 2703 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5)
2695 2704 return ("i486 compatible");
2696 2705
2697 2706 switch (cpi->cpi_family) {
2698 2707 case 5:
2699 2708 switch (cpi->cpi_model) {
2700 2709 case 0:
2701 2710 case 1:
2702 2711 case 2:
2703 2712 case 3:
2704 2713 case 4:
2705 2714 case 5:
2706 2715 return ("AMD-K5(r)");
2707 2716 case 6:
2708 2717 case 7:
2709 2718 return ("AMD-K6(r)");
2710 2719 case 8:
2711 2720 return ("AMD-K6(r)-2");
2712 2721 case 9:
2713 2722 return ("AMD-K6(r)-III");
2714 2723 default:
2715 2724 return ("AMD (family 5)");
2716 2725 }
2717 2726 case 6:
2718 2727 switch (cpi->cpi_model) {
2719 2728 case 1:
2720 2729 return ("AMD-K7(tm)");
2721 2730 case 0:
2722 2731 case 2:
2723 2732 case 4:
2724 2733 return ("AMD Athlon(tm)");
2725 2734 case 3:
2726 2735 case 7:
2727 2736 return ("AMD Duron(tm)");
2728 2737 case 6:
2729 2738 case 8:
2730 2739 case 10:
2731 2740 /*
2732 2741 * Use the L2 cache size to distinguish
2733 2742 */
2734 2743 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ?
2735 2744 "AMD Athlon(tm)" : "AMD Duron(tm)");
2736 2745 default:
2737 2746 return ("AMD (family 6)");
2738 2747 }
2739 2748 default:
2740 2749 break;
2741 2750 }
2742 2751
2743 2752 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 &&
2744 2753 cpi->cpi_brandid != 0) {
2745 2754 switch (BITX(cpi->cpi_brandid, 7, 5)) {
2746 2755 case 3:
2747 2756 return ("AMD Opteron(tm) UP 1xx");
2748 2757 case 4:
2749 2758 return ("AMD Opteron(tm) DP 2xx");
2750 2759 case 5:
2751 2760 return ("AMD Opteron(tm) MP 8xx");
2752 2761 default:
2753 2762 return ("AMD Opteron(tm)");
2754 2763 }
2755 2764 }
2756 2765
2757 2766 return (NULL);
2758 2767 }
2759 2768
2760 2769 static const char *
2761 2770 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type)
2762 2771 {
2763 2772 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) ||
2764 2773 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 ||
2765 2774 type == X86_TYPE_CYRIX_486)
2766 2775 return ("i486 compatible");
2767 2776
2768 2777 switch (type) {
2769 2778 case X86_TYPE_CYRIX_6x86:
2770 2779 return ("Cyrix 6x86");
2771 2780 case X86_TYPE_CYRIX_6x86L:
2772 2781 return ("Cyrix 6x86L");
2773 2782 case X86_TYPE_CYRIX_6x86MX:
2774 2783 return ("Cyrix 6x86MX");
2775 2784 case X86_TYPE_CYRIX_GXm:
2776 2785 return ("Cyrix GXm");
2777 2786 case X86_TYPE_CYRIX_MediaGX:
2778 2787 return ("Cyrix MediaGX");
2779 2788 case X86_TYPE_CYRIX_MII:
2780 2789 return ("Cyrix M2");
2781 2790 case X86_TYPE_VIA_CYRIX_III:
2782 2791 return ("VIA Cyrix M3");
2783 2792 default:
2784 2793 /*
2785 2794 * Have another wild guess ..
2786 2795 */
2787 2796 if (cpi->cpi_family == 4 && cpi->cpi_model == 9)
2788 2797 return ("Cyrix 5x86");
2789 2798 else if (cpi->cpi_family == 5) {
2790 2799 switch (cpi->cpi_model) {
2791 2800 case 2:
2792 2801 return ("Cyrix 6x86"); /* Cyrix M1 */
2793 2802 case 4:
2794 2803 return ("Cyrix MediaGX");
2795 2804 default:
2796 2805 break;
2797 2806 }
2798 2807 } else if (cpi->cpi_family == 6) {
2799 2808 switch (cpi->cpi_model) {
2800 2809 case 0:
2801 2810 return ("Cyrix 6x86MX"); /* Cyrix M2? */
2802 2811 case 5:
2803 2812 case 6:
2804 2813 case 7:
2805 2814 case 8:
2806 2815 case 9:
2807 2816 return ("VIA C3");
2808 2817 default:
2809 2818 break;
2810 2819 }
2811 2820 }
2812 2821 break;
2813 2822 }
2814 2823 return (NULL);
2815 2824 }
2816 2825
2817 2826 /*
2818 2827 * This only gets called in the case that the CPU extended
2819 2828 * feature brand string (0x80000002, 0x80000003, 0x80000004)
2820 2829 * aren't available, or contain null bytes for some reason.
2821 2830 */
2822 2831 static void
2823 2832 fabricate_brandstr(struct cpuid_info *cpi)
2824 2833 {
2825 2834 const char *brand = NULL;
2826 2835
2827 2836 switch (cpi->cpi_vendor) {
2828 2837 case X86_VENDOR_Intel:
2829 2838 brand = intel_cpubrand(cpi);
2830 2839 break;
2831 2840 case X86_VENDOR_AMD:
2832 2841 brand = amd_cpubrand(cpi);
2833 2842 break;
2834 2843 case X86_VENDOR_Cyrix:
2835 2844 brand = cyrix_cpubrand(cpi, x86_type);
2836 2845 break;
2837 2846 case X86_VENDOR_NexGen:
2838 2847 if (cpi->cpi_family == 5 && cpi->cpi_model == 0)
2839 2848 brand = "NexGen Nx586";
2840 2849 break;
2841 2850 case X86_VENDOR_Centaur:
2842 2851 if (cpi->cpi_family == 5)
2843 2852 switch (cpi->cpi_model) {
2844 2853 case 4:
2845 2854 brand = "Centaur C6";
2846 2855 break;
2847 2856 case 8:
2848 2857 brand = "Centaur C2";
2849 2858 break;
2850 2859 case 9:
2851 2860 brand = "Centaur C3";
2852 2861 break;
2853 2862 default:
2854 2863 break;
2855 2864 }
2856 2865 break;
2857 2866 case X86_VENDOR_Rise:
2858 2867 if (cpi->cpi_family == 5 &&
2859 2868 (cpi->cpi_model == 0 || cpi->cpi_model == 2))
2860 2869 brand = "Rise mP6";
2861 2870 break;
2862 2871 case X86_VENDOR_SiS:
2863 2872 if (cpi->cpi_family == 5 && cpi->cpi_model == 0)
2864 2873 brand = "SiS 55x";
2865 2874 break;
2866 2875 case X86_VENDOR_TM:
2867 2876 if (cpi->cpi_family == 5 && cpi->cpi_model == 4)
2868 2877 brand = "Transmeta Crusoe TM3x00 or TM5x00";
2869 2878 break;
2870 2879 case X86_VENDOR_NSC:
2871 2880 case X86_VENDOR_UMC:
2872 2881 default:
2873 2882 break;
2874 2883 }
2875 2884 if (brand) {
2876 2885 (void) strcpy((char *)cpi->cpi_brandstr, brand);
2877 2886 return;
2878 2887 }
2879 2888
2880 2889 /*
2881 2890 * If all else fails ...
2882 2891 */
2883 2892 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr),
2884 2893 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family,
2885 2894 cpi->cpi_model, cpi->cpi_step);
2886 2895 }
2887 2896
2888 2897 /*
2889 2898 * This routine is called just after kernel memory allocation
2890 2899 * becomes available on cpu0, and as part of mp_startup() on
2891 2900 * the other cpus.
2892 2901 *
2893 2902 * Fixup the brand string, and collect any information from cpuid
2894 2903 * that requires dynamically allocated storage to represent.
2895 2904 */
2896 2905 /*ARGSUSED*/
2897 2906 void
2898 2907 cpuid_pass3(cpu_t *cpu)
2899 2908 {
2900 2909 int i, max, shft, level, size;
2901 2910 struct cpuid_regs regs;
2902 2911 struct cpuid_regs *cp;
2903 2912 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
2904 2913
2905 2914 ASSERT(cpi->cpi_pass == 2);
2906 2915
2907 2916 /*
2908 2917 * Function 4: Deterministic cache parameters
2909 2918 *
2910 2919 * Take this opportunity to detect the number of threads
2911 2920 * sharing the last level cache, and construct a corresponding
2912 2921 * cache id. The respective cpuid_info members are initialized
2913 2922 * to the default case of "no last level cache sharing".
2914 2923 */
2915 2924 cpi->cpi_ncpu_shr_last_cache = 1;
2916 2925 cpi->cpi_last_lvl_cacheid = cpu->cpu_id;
2917 2926
2918 2927 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) {
2919 2928
2920 2929 /*
2921 2930 * Find the # of elements (size) returned by fn 4, and along
2922 2931 * the way detect last level cache sharing details.
2923 2932 */
2924 2933 bzero(®s, sizeof (regs));
2925 2934 cp = ®s;
2926 2935 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) {
2927 2936 cp->cp_eax = 4;
2928 2937 cp->cp_ecx = i;
2929 2938
2930 2939 (void) __cpuid_insn(cp);
2931 2940
2932 2941 if (CPI_CACHE_TYPE(cp) == 0)
2933 2942 break;
2934 2943 level = CPI_CACHE_LVL(cp);
2935 2944 if (level > max) {
2936 2945 max = level;
2937 2946 cpi->cpi_ncpu_shr_last_cache =
2938 2947 CPI_NTHR_SHR_CACHE(cp) + 1;
2939 2948 }
2940 2949 }
2941 2950 cpi->cpi_std_4_size = size = i;
2942 2951
2943 2952 /*
2944 2953 * Allocate the cpi_std_4 array. The first element
2945 2954 * references the regs for fn 4, %ecx == 0, which
2946 2955 * cpuid_pass2() stashed in cpi->cpi_std[4].
2947 2956 */
2948 2957 if (size > 0) {
2949 2958 cpi->cpi_std_4 =
2950 2959 kmem_alloc(size * sizeof (cp), KM_SLEEP);
2951 2960 cpi->cpi_std_4[0] = &cpi->cpi_std[4];
2952 2961
2953 2962 /*
2954 2963 * Allocate storage to hold the additional regs
2955 2964 * for function 4, %ecx == 1 .. cpi_std_4_size.
2956 2965 *
2957 2966 * The regs for fn 4, %ecx == 0 has already
2958 2967 * been allocated as indicated above.
2959 2968 */
2960 2969 for (i = 1; i < size; i++) {
2961 2970 cp = cpi->cpi_std_4[i] =
2962 2971 kmem_zalloc(sizeof (regs), KM_SLEEP);
2963 2972 cp->cp_eax = 4;
2964 2973 cp->cp_ecx = i;
2965 2974
2966 2975 (void) __cpuid_insn(cp);
2967 2976 }
2968 2977 }
2969 2978 /*
2970 2979 * Determine the number of bits needed to represent
2971 2980 * the number of CPUs sharing the last level cache.
2972 2981 *
2973 2982 * Shift off that number of bits from the APIC id to
2974 2983 * derive the cache id.
2975 2984 */
2976 2985 shft = 0;
2977 2986 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1)
2978 2987 shft++;
2979 2988 cpi->cpi_last_lvl_cacheid = cpi->cpi_apicid >> shft;
2980 2989 }
2981 2990
2982 2991 /*
2983 2992 * Now fixup the brand string
2984 2993 */
2985 2994 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) {
2986 2995 fabricate_brandstr(cpi);
2987 2996 } else {
2988 2997
2989 2998 /*
2990 2999 * If we successfully extracted a brand string from the cpuid
2991 3000 * instruction, clean it up by removing leading spaces and
2992 3001 * similar junk.
2993 3002 */
2994 3003 if (cpi->cpi_brandstr[0]) {
2995 3004 size_t maxlen = sizeof (cpi->cpi_brandstr);
2996 3005 char *src, *dst;
2997 3006
2998 3007 dst = src = (char *)cpi->cpi_brandstr;
2999 3008 src[maxlen - 1] = '\0';
3000 3009 /*
3001 3010 * strip leading spaces
3002 3011 */
3003 3012 while (*src == ' ')
3004 3013 src++;
3005 3014 /*
3006 3015 * Remove any 'Genuine' or "Authentic" prefixes
3007 3016 */
3008 3017 if (strncmp(src, "Genuine ", 8) == 0)
3009 3018 src += 8;
3010 3019 if (strncmp(src, "Authentic ", 10) == 0)
3011 3020 src += 10;
3012 3021
3013 3022 /*
3014 3023 * Now do an in-place copy.
3015 3024 * Map (R) to (r) and (TM) to (tm).
3016 3025 * The era of teletypes is long gone, and there's
3017 3026 * -really- no need to shout.
3018 3027 */
3019 3028 while (*src != '\0') {
3020 3029 if (src[0] == '(') {
3021 3030 if (strncmp(src + 1, "R)", 2) == 0) {
3022 3031 (void) strncpy(dst, "(r)", 3);
3023 3032 src += 3;
3024 3033 dst += 3;
3025 3034 continue;
3026 3035 }
3027 3036 if (strncmp(src + 1, "TM)", 3) == 0) {
3028 3037 (void) strncpy(dst, "(tm)", 4);
3029 3038 src += 4;
3030 3039 dst += 4;
3031 3040 continue;
3032 3041 }
3033 3042 }
3034 3043 *dst++ = *src++;
3035 3044 }
3036 3045 *dst = '\0';
3037 3046
3038 3047 /*
3039 3048 * Finally, remove any trailing spaces
3040 3049 */
3041 3050 while (--dst > cpi->cpi_brandstr)
3042 3051 if (*dst == ' ')
3043 3052 *dst = '\0';
3044 3053 else
3045 3054 break;
3046 3055 } else
3047 3056 fabricate_brandstr(cpi);
3048 3057 }
3049 3058 cpi->cpi_pass = 3;
3050 3059 }
3051 3060
3052 3061 /*
3053 3062 * This routine is called out of bind_hwcap() much later in the life
3054 3063 * of the kernel (post_startup()). The job of this routine is to resolve
3055 3064 * the hardware feature support and kernel support for those features into
3056 3065 * what we're actually going to tell applications via the aux vector.
3057 3066 */
3058 3067 void
3059 3068 cpuid_pass4(cpu_t *cpu, uint_t *hwcap_out)
3060 3069 {
3061 3070 struct cpuid_info *cpi;
3062 3071 uint_t hwcap_flags = 0, hwcap_flags_2 = 0;
3063 3072
3064 3073 if (cpu == NULL)
3065 3074 cpu = CPU;
3066 3075 cpi = cpu->cpu_m.mcpu_cpi;
3067 3076
3068 3077 ASSERT(cpi->cpi_pass == 3);
3069 3078
3070 3079 if (cpi->cpi_maxeax >= 1) {
3071 3080 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES];
3072 3081 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES];
3073 3082 uint32_t *ebx = &cpi->cpi_support[STD_EBX_FEATURES];
3074 3083
3075 3084 *edx = CPI_FEATURES_EDX(cpi);
3076 3085 *ecx = CPI_FEATURES_ECX(cpi);
3077 3086 *ebx = CPI_FEATURES_7_0_EBX(cpi);
3078 3087
3079 3088 /*
3080 3089 * [these require explicit kernel support]
3081 3090 */
3082 3091 if (!is_x86_feature(x86_featureset, X86FSET_SEP))
3083 3092 *edx &= ~CPUID_INTC_EDX_SEP;
3084 3093
3085 3094 if (!is_x86_feature(x86_featureset, X86FSET_SSE))
3086 3095 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE);
3087 3096 if (!is_x86_feature(x86_featureset, X86FSET_SSE2))
3088 3097 *edx &= ~CPUID_INTC_EDX_SSE2;
3089 3098
3090 3099 if (!is_x86_feature(x86_featureset, X86FSET_HTT))
3091 3100 *edx &= ~CPUID_INTC_EDX_HTT;
3092 3101
3093 3102 if (!is_x86_feature(x86_featureset, X86FSET_SSE3))
3094 3103 *ecx &= ~CPUID_INTC_ECX_SSE3;
3095 3104
3096 3105 if (!is_x86_feature(x86_featureset, X86FSET_SSSE3))
3097 3106 *ecx &= ~CPUID_INTC_ECX_SSSE3;
3098 3107 if (!is_x86_feature(x86_featureset, X86FSET_SSE4_1))
3099 3108 *ecx &= ~CPUID_INTC_ECX_SSE4_1;
3100 3109 if (!is_x86_feature(x86_featureset, X86FSET_SSE4_2))
3101 3110 *ecx &= ~CPUID_INTC_ECX_SSE4_2;
3102 3111 if (!is_x86_feature(x86_featureset, X86FSET_AES))
3103 3112 *ecx &= ~CPUID_INTC_ECX_AES;
3104 3113 if (!is_x86_feature(x86_featureset, X86FSET_PCLMULQDQ))
3105 3114 *ecx &= ~CPUID_INTC_ECX_PCLMULQDQ;
3106 3115 if (!is_x86_feature(x86_featureset, X86FSET_XSAVE))
3107 3116 *ecx &= ~(CPUID_INTC_ECX_XSAVE |
3108 3117 CPUID_INTC_ECX_OSXSAVE);
3109 3118 if (!is_x86_feature(x86_featureset, X86FSET_AVX))
3110 3119 *ecx &= ~CPUID_INTC_ECX_AVX;
3111 3120 if (!is_x86_feature(x86_featureset, X86FSET_F16C))
3112 3121 *ecx &= ~CPUID_INTC_ECX_F16C;
3113 3122 if (!is_x86_feature(x86_featureset, X86FSET_FMA))
3114 3123 *ecx &= ~CPUID_INTC_ECX_FMA;
3115 3124 if (!is_x86_feature(x86_featureset, X86FSET_BMI1))
3116 3125 *ebx &= ~CPUID_INTC_EBX_7_0_BMI1;
3117 3126 if (!is_x86_feature(x86_featureset, X86FSET_BMI2))
3118 3127 *ebx &= ~CPUID_INTC_EBX_7_0_BMI2;
3119 3128 if (!is_x86_feature(x86_featureset, X86FSET_AVX2))
3120 3129 *ebx &= ~CPUID_INTC_EBX_7_0_AVX2;
3121 3130 if (!is_x86_feature(x86_featureset, X86FSET_RDSEED))
3122 3131 *ebx &= ~CPUID_INTC_EBX_7_0_RDSEED;
3123 3132 if (!is_x86_feature(x86_featureset, X86FSET_ADX))
3124 3133 *ebx &= ~CPUID_INTC_EBX_7_0_ADX;
3125 3134
3126 3135 /*
3127 3136 * [no explicit support required beyond x87 fp context]
3128 3137 */
3129 3138 if (!fpu_exists)
3130 3139 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX);
3131 3140
3132 3141 /*
3133 3142 * Now map the supported feature vector to things that we
3134 3143 * think userland will care about.
3135 3144 */
3136 3145 if (*edx & CPUID_INTC_EDX_SEP)
3137 3146 hwcap_flags |= AV_386_SEP;
3138 3147 if (*edx & CPUID_INTC_EDX_SSE)
3139 3148 hwcap_flags |= AV_386_FXSR | AV_386_SSE;
3140 3149 if (*edx & CPUID_INTC_EDX_SSE2)
3141 3150 hwcap_flags |= AV_386_SSE2;
3142 3151 if (*ecx & CPUID_INTC_ECX_SSE3)
3143 3152 hwcap_flags |= AV_386_SSE3;
3144 3153 if (*ecx & CPUID_INTC_ECX_SSSE3)
3145 3154 hwcap_flags |= AV_386_SSSE3;
3146 3155 if (*ecx & CPUID_INTC_ECX_SSE4_1)
3147 3156 hwcap_flags |= AV_386_SSE4_1;
3148 3157 if (*ecx & CPUID_INTC_ECX_SSE4_2)
3149 3158 hwcap_flags |= AV_386_SSE4_2;
3150 3159 if (*ecx & CPUID_INTC_ECX_MOVBE)
3151 3160 hwcap_flags |= AV_386_MOVBE;
3152 3161 if (*ecx & CPUID_INTC_ECX_AES)
3153 3162 hwcap_flags |= AV_386_AES;
3154 3163 if (*ecx & CPUID_INTC_ECX_PCLMULQDQ)
3155 3164 hwcap_flags |= AV_386_PCLMULQDQ;
3156 3165 if ((*ecx & CPUID_INTC_ECX_XSAVE) &&
3157 3166 (*ecx & CPUID_INTC_ECX_OSXSAVE)) {
3158 3167 hwcap_flags |= AV_386_XSAVE;
3159 3168
3160 3169 if (*ecx & CPUID_INTC_ECX_AVX) {
3161 3170 uint32_t *ecx_7 = &CPI_FEATURES_7_0_ECX(cpi);
3162 3171 uint32_t *edx_7 = &CPI_FEATURES_7_0_EDX(cpi);
3163 3172
3164 3173 hwcap_flags |= AV_386_AVX;
3165 3174 if (*ecx & CPUID_INTC_ECX_F16C)
3166 3175 hwcap_flags_2 |= AV_386_2_F16C;
3167 3176 if (*ecx & CPUID_INTC_ECX_FMA)
3168 3177 hwcap_flags_2 |= AV_386_2_FMA;
3169 3178
3170 3179 if (*ebx & CPUID_INTC_EBX_7_0_BMI1)
3171 3180 hwcap_flags_2 |= AV_386_2_BMI1;
3172 3181 if (*ebx & CPUID_INTC_EBX_7_0_BMI2)
3173 3182 hwcap_flags_2 |= AV_386_2_BMI2;
3174 3183 if (*ebx & CPUID_INTC_EBX_7_0_AVX2)
3175 3184 hwcap_flags_2 |= AV_386_2_AVX2;
3176 3185 if (*ebx & CPUID_INTC_EBX_7_0_AVX512F)
3177 3186 hwcap_flags_2 |= AV_386_2_AVX512F;
3178 3187 if (*ebx & CPUID_INTC_EBX_7_0_AVX512DQ)
3179 3188 hwcap_flags_2 |= AV_386_2_AVX512DQ;
3180 3189 if (*ebx & CPUID_INTC_EBX_7_0_AVX512IFMA)
3181 3190 hwcap_flags_2 |= AV_386_2_AVX512IFMA;
3182 3191 if (*ebx & CPUID_INTC_EBX_7_0_AVX512PF)
3183 3192 hwcap_flags_2 |= AV_386_2_AVX512PF;
3184 3193 if (*ebx & CPUID_INTC_EBX_7_0_AVX512ER)
3185 3194 hwcap_flags_2 |= AV_386_2_AVX512ER;
3186 3195 if (*ebx & CPUID_INTC_EBX_7_0_AVX512CD)
3187 3196 hwcap_flags_2 |= AV_386_2_AVX512CD;
3188 3197 if (*ebx & CPUID_INTC_EBX_7_0_AVX512BW)
3189 3198 hwcap_flags_2 |= AV_386_2_AVX512BW;
3190 3199 if (*ebx & CPUID_INTC_EBX_7_0_AVX512VL)
3191 3200 hwcap_flags_2 |= AV_386_2_AVX512VL;
3192 3201
3193 3202 if (*ecx_7 & CPUID_INTC_ECX_7_0_AVX512VBMI)
3194 3203 hwcap_flags_2 |= AV_386_2_AVX512VBMI;
3195 3204 if (*ecx_7 & CPUID_INTC_ECX_7_0_AVX512VPOPCDQ)
3196 3205 hwcap_flags_2 |= AV_386_2_AVX512VPOPCDQ;
3197 3206
3198 3207 if (*edx_7 & CPUID_INTC_EDX_7_0_AVX5124NNIW)
3199 3208 hwcap_flags_2 |= AV_386_2_AVX512_4NNIW;
3200 3209 if (*edx_7 & CPUID_INTC_EDX_7_0_AVX5124FMAPS)
3201 3210 hwcap_flags_2 |= AV_386_2_AVX512_4FMAPS;
3202 3211 }
3203 3212 }
3204 3213 if (*ecx & CPUID_INTC_ECX_VMX)
3205 3214 hwcap_flags |= AV_386_VMX;
3206 3215 if (*ecx & CPUID_INTC_ECX_POPCNT)
3207 3216 hwcap_flags |= AV_386_POPCNT;
3208 3217 if (*edx & CPUID_INTC_EDX_FPU)
3209 3218 hwcap_flags |= AV_386_FPU;
3210 3219 if (*edx & CPUID_INTC_EDX_MMX)
3211 3220 hwcap_flags |= AV_386_MMX;
3212 3221
3213 3222 if (*edx & CPUID_INTC_EDX_TSC)
3214 3223 hwcap_flags |= AV_386_TSC;
3215 3224 if (*edx & CPUID_INTC_EDX_CX8)
3216 3225 hwcap_flags |= AV_386_CX8;
3217 3226 if (*edx & CPUID_INTC_EDX_CMOV)
3218 3227 hwcap_flags |= AV_386_CMOV;
3219 3228 if (*ecx & CPUID_INTC_ECX_CX16)
3220 3229 hwcap_flags |= AV_386_CX16;
3221 3230
3222 3231 if (*ecx & CPUID_INTC_ECX_RDRAND)
3223 3232 hwcap_flags_2 |= AV_386_2_RDRAND;
3224 3233 if (*ebx & CPUID_INTC_EBX_7_0_ADX)
3225 3234 hwcap_flags_2 |= AV_386_2_ADX;
3226 3235 if (*ebx & CPUID_INTC_EBX_7_0_RDSEED)
3227 3236 hwcap_flags_2 |= AV_386_2_RDSEED;
3228 3237 if (*ebx & CPUID_INTC_EBX_7_0_SHA)
3229 3238 hwcap_flags_2 |= AV_386_2_SHA;
3230 3239
3231 3240 }
3232 3241
3233 3242 if (cpi->cpi_xmaxeax < 0x80000001)
3234 3243 goto pass4_done;
3235 3244
3236 3245 switch (cpi->cpi_vendor) {
3237 3246 struct cpuid_regs cp;
3238 3247 uint32_t *edx, *ecx;
3239 3248
3240 3249 case X86_VENDOR_Intel:
3241 3250 /*
3242 3251 * Seems like Intel duplicated what we necessary
3243 3252 * here to make the initial crop of 64-bit OS's work.
3244 3253 * Hopefully, those are the only "extended" bits
3245 3254 * they'll add.
3246 3255 */
3247 3256 /*FALLTHROUGH*/
3248 3257
3249 3258 case X86_VENDOR_AMD:
3250 3259 edx = &cpi->cpi_support[AMD_EDX_FEATURES];
3251 3260 ecx = &cpi->cpi_support[AMD_ECX_FEATURES];
3252 3261
3253 3262 *edx = CPI_FEATURES_XTD_EDX(cpi);
3254 3263 *ecx = CPI_FEATURES_XTD_ECX(cpi);
3255 3264
3256 3265 /*
3257 3266 * [these features require explicit kernel support]
3258 3267 */
3259 3268 switch (cpi->cpi_vendor) {
3260 3269 case X86_VENDOR_Intel:
3261 3270 if (!is_x86_feature(x86_featureset, X86FSET_TSCP))
3262 3271 *edx &= ~CPUID_AMD_EDX_TSCP;
3263 3272 break;
3264 3273
3265 3274 case X86_VENDOR_AMD:
3266 3275 if (!is_x86_feature(x86_featureset, X86FSET_TSCP))
3267 3276 *edx &= ~CPUID_AMD_EDX_TSCP;
3268 3277 if (!is_x86_feature(x86_featureset, X86FSET_SSE4A))
3269 3278 *ecx &= ~CPUID_AMD_ECX_SSE4A;
3270 3279 break;
3271 3280
3272 3281 default:
3273 3282 break;
3274 3283 }
3275 3284
3276 3285 /*
3277 3286 * [no explicit support required beyond
3278 3287 * x87 fp context and exception handlers]
3279 3288 */
3280 3289 if (!fpu_exists)
3281 3290 *edx &= ~(CPUID_AMD_EDX_MMXamd |
3282 3291 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx);
3283 3292
3284 3293 if (!is_x86_feature(x86_featureset, X86FSET_NX))
3285 3294 *edx &= ~CPUID_AMD_EDX_NX;
3286 3295 #if !defined(__amd64)
3287 3296 *edx &= ~CPUID_AMD_EDX_LM;
3288 3297 #endif
3289 3298 /*
3290 3299 * Now map the supported feature vector to
3291 3300 * things that we think userland will care about.
3292 3301 */
3293 3302 #if defined(__amd64)
3294 3303 if (*edx & CPUID_AMD_EDX_SYSC)
3295 3304 hwcap_flags |= AV_386_AMD_SYSC;
3296 3305 #endif
3297 3306 if (*edx & CPUID_AMD_EDX_MMXamd)
3298 3307 hwcap_flags |= AV_386_AMD_MMX;
3299 3308 if (*edx & CPUID_AMD_EDX_3DNow)
3300 3309 hwcap_flags |= AV_386_AMD_3DNow;
3301 3310 if (*edx & CPUID_AMD_EDX_3DNowx)
3302 3311 hwcap_flags |= AV_386_AMD_3DNowx;
3303 3312 if (*ecx & CPUID_AMD_ECX_SVM)
3304 3313 hwcap_flags |= AV_386_AMD_SVM;
3305 3314
3306 3315 switch (cpi->cpi_vendor) {
3307 3316 case X86_VENDOR_AMD:
3308 3317 if (*edx & CPUID_AMD_EDX_TSCP)
3309 3318 hwcap_flags |= AV_386_TSCP;
3310 3319 if (*ecx & CPUID_AMD_ECX_AHF64)
3311 3320 hwcap_flags |= AV_386_AHF;
3312 3321 if (*ecx & CPUID_AMD_ECX_SSE4A)
3313 3322 hwcap_flags |= AV_386_AMD_SSE4A;
3314 3323 if (*ecx & CPUID_AMD_ECX_LZCNT)
3315 3324 hwcap_flags |= AV_386_AMD_LZCNT;
3316 3325 break;
3317 3326
3318 3327 case X86_VENDOR_Intel:
3319 3328 if (*edx & CPUID_AMD_EDX_TSCP)
3320 3329 hwcap_flags |= AV_386_TSCP;
3321 3330 /*
3322 3331 * Aarrgh.
3323 3332 * Intel uses a different bit in the same word.
3324 3333 */
3325 3334 if (*ecx & CPUID_INTC_ECX_AHF64)
3326 3335 hwcap_flags |= AV_386_AHF;
3327 3336 break;
3328 3337
3329 3338 default:
3330 3339 break;
3331 3340 }
3332 3341 break;
3333 3342
3334 3343 case X86_VENDOR_TM:
3335 3344 cp.cp_eax = 0x80860001;
3336 3345 (void) __cpuid_insn(&cp);
3337 3346 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx;
3338 3347 break;
3339 3348
3340 3349 default:
3341 3350 break;
3342 3351 }
3343 3352
3344 3353 pass4_done:
3345 3354 cpi->cpi_pass = 4;
3346 3355 if (hwcap_out != NULL) {
3347 3356 hwcap_out[0] = hwcap_flags;
3348 3357 hwcap_out[1] = hwcap_flags_2;
3349 3358 }
3350 3359 }
3351 3360
3352 3361
3353 3362 /*
3354 3363 * Simulate the cpuid instruction using the data we previously
3355 3364 * captured about this CPU. We try our best to return the truth
3356 3365 * about the hardware, independently of kernel support.
3357 3366 */
3358 3367 uint32_t
3359 3368 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp)
3360 3369 {
3361 3370 struct cpuid_info *cpi;
3362 3371 struct cpuid_regs *xcp;
3363 3372
3364 3373 if (cpu == NULL)
3365 3374 cpu = CPU;
3366 3375 cpi = cpu->cpu_m.mcpu_cpi;
3367 3376
3368 3377 ASSERT(cpuid_checkpass(cpu, 3));
3369 3378
3370 3379 /*
3371 3380 * CPUID data is cached in two separate places: cpi_std for standard
3372 3381 * CPUID functions, and cpi_extd for extended CPUID functions.
3373 3382 */
3374 3383 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD)
3375 3384 xcp = &cpi->cpi_std[cp->cp_eax];
3376 3385 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax &&
3377 3386 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD)
3378 3387 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000];
3379 3388 else
3380 3389 /*
3381 3390 * The caller is asking for data from an input parameter which
3382 3391 * the kernel has not cached. In this case we go fetch from
3383 3392 * the hardware and return the data directly to the user.
3384 3393 */
3385 3394 return (__cpuid_insn(cp));
3386 3395
3387 3396 cp->cp_eax = xcp->cp_eax;
3388 3397 cp->cp_ebx = xcp->cp_ebx;
3389 3398 cp->cp_ecx = xcp->cp_ecx;
3390 3399 cp->cp_edx = xcp->cp_edx;
3391 3400 return (cp->cp_eax);
3392 3401 }
3393 3402
3394 3403 int
3395 3404 cpuid_checkpass(cpu_t *cpu, int pass)
3396 3405 {
3397 3406 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL &&
3398 3407 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass);
3399 3408 }
3400 3409
3401 3410 int
3402 3411 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n)
3403 3412 {
3404 3413 ASSERT(cpuid_checkpass(cpu, 3));
3405 3414
3406 3415 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr));
3407 3416 }
3408 3417
3409 3418 int
3410 3419 cpuid_is_cmt(cpu_t *cpu)
3411 3420 {
3412 3421 if (cpu == NULL)
3413 3422 cpu = CPU;
3414 3423
3415 3424 ASSERT(cpuid_checkpass(cpu, 1));
3416 3425
3417 3426 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0);
3418 3427 }
3419 3428
3420 3429 /*
3421 3430 * AMD and Intel both implement the 64-bit variant of the syscall
3422 3431 * instruction (syscallq), so if there's -any- support for syscall,
3423 3432 * cpuid currently says "yes, we support this".
3424 3433 *
3425 3434 * However, Intel decided to -not- implement the 32-bit variant of the
3426 3435 * syscall instruction, so we provide a predicate to allow our caller
3427 3436 * to test that subtlety here.
3428 3437 *
3429 3438 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor,
3430 3439 * even in the case where the hardware would in fact support it.
3431 3440 */
3432 3441 /*ARGSUSED*/
3433 3442 int
3434 3443 cpuid_syscall32_insn(cpu_t *cpu)
3435 3444 {
3436 3445 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1));
3437 3446
3438 3447 #if !defined(__xpv)
3439 3448 if (cpu == NULL)
3440 3449 cpu = CPU;
3441 3450
3442 3451 /*CSTYLED*/
3443 3452 {
3444 3453 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
3445 3454
3446 3455 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
3447 3456 cpi->cpi_xmaxeax >= 0x80000001 &&
3448 3457 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC))
3449 3458 return (1);
3450 3459 }
3451 3460 #endif
3452 3461 return (0);
3453 3462 }
3454 3463
3455 3464 int
3456 3465 cpuid_getidstr(cpu_t *cpu, char *s, size_t n)
3457 3466 {
3458 3467 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
3459 3468
3460 3469 static const char fmt[] =
3461 3470 "x86 (%s %X family %d model %d step %d clock %d MHz)";
3462 3471 static const char fmt_ht[] =
3463 3472 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)";
3464 3473
3465 3474 ASSERT(cpuid_checkpass(cpu, 1));
3466 3475
3467 3476 if (cpuid_is_cmt(cpu))
3468 3477 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid,
3469 3478 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax,
3470 3479 cpi->cpi_family, cpi->cpi_model,
3471 3480 cpi->cpi_step, cpu->cpu_type_info.pi_clock));
3472 3481 return (snprintf(s, n, fmt,
3473 3482 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax,
3474 3483 cpi->cpi_family, cpi->cpi_model,
3475 3484 cpi->cpi_step, cpu->cpu_type_info.pi_clock));
3476 3485 }
3477 3486
3478 3487 const char *
3479 3488 cpuid_getvendorstr(cpu_t *cpu)
3480 3489 {
3481 3490 ASSERT(cpuid_checkpass(cpu, 1));
3482 3491 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr);
3483 3492 }
3484 3493
3485 3494 uint_t
3486 3495 cpuid_getvendor(cpu_t *cpu)
3487 3496 {
3488 3497 ASSERT(cpuid_checkpass(cpu, 1));
3489 3498 return (cpu->cpu_m.mcpu_cpi->cpi_vendor);
3490 3499 }
3491 3500
3492 3501 uint_t
3493 3502 cpuid_getfamily(cpu_t *cpu)
3494 3503 {
3495 3504 ASSERT(cpuid_checkpass(cpu, 1));
3496 3505 return (cpu->cpu_m.mcpu_cpi->cpi_family);
3497 3506 }
3498 3507
3499 3508 uint_t
3500 3509 cpuid_getmodel(cpu_t *cpu)
3501 3510 {
3502 3511 ASSERT(cpuid_checkpass(cpu, 1));
3503 3512 return (cpu->cpu_m.mcpu_cpi->cpi_model);
3504 3513 }
3505 3514
3506 3515 uint_t
3507 3516 cpuid_get_ncpu_per_chip(cpu_t *cpu)
3508 3517 {
3509 3518 ASSERT(cpuid_checkpass(cpu, 1));
3510 3519 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip);
3511 3520 }
3512 3521
3513 3522 uint_t
3514 3523 cpuid_get_ncore_per_chip(cpu_t *cpu)
3515 3524 {
3516 3525 ASSERT(cpuid_checkpass(cpu, 1));
3517 3526 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip);
3518 3527 }
3519 3528
3520 3529 uint_t
3521 3530 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu)
3522 3531 {
3523 3532 ASSERT(cpuid_checkpass(cpu, 2));
3524 3533 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache);
3525 3534 }
3526 3535
3527 3536 id_t
3528 3537 cpuid_get_last_lvl_cacheid(cpu_t *cpu)
3529 3538 {
3530 3539 ASSERT(cpuid_checkpass(cpu, 2));
3531 3540 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid);
3532 3541 }
3533 3542
3534 3543 uint_t
3535 3544 cpuid_getstep(cpu_t *cpu)
3536 3545 {
3537 3546 ASSERT(cpuid_checkpass(cpu, 1));
3538 3547 return (cpu->cpu_m.mcpu_cpi->cpi_step);
3539 3548 }
3540 3549
3541 3550 uint_t
3542 3551 cpuid_getsig(struct cpu *cpu)
3543 3552 {
3544 3553 ASSERT(cpuid_checkpass(cpu, 1));
3545 3554 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax);
3546 3555 }
3547 3556
3548 3557 uint32_t
3549 3558 cpuid_getchiprev(struct cpu *cpu)
3550 3559 {
3551 3560 ASSERT(cpuid_checkpass(cpu, 1));
3552 3561 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev);
3553 3562 }
3554 3563
3555 3564 const char *
3556 3565 cpuid_getchiprevstr(struct cpu *cpu)
3557 3566 {
3558 3567 ASSERT(cpuid_checkpass(cpu, 1));
3559 3568 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr);
3560 3569 }
3561 3570
3562 3571 uint32_t
3563 3572 cpuid_getsockettype(struct cpu *cpu)
3564 3573 {
3565 3574 ASSERT(cpuid_checkpass(cpu, 1));
3566 3575 return (cpu->cpu_m.mcpu_cpi->cpi_socket);
3567 3576 }
3568 3577
3569 3578 const char *
3570 3579 cpuid_getsocketstr(cpu_t *cpu)
3571 3580 {
3572 3581 static const char *socketstr = NULL;
3573 3582 struct cpuid_info *cpi;
3574 3583
3575 3584 ASSERT(cpuid_checkpass(cpu, 1));
3576 3585 cpi = cpu->cpu_m.mcpu_cpi;
3577 3586
3578 3587 /* Assume that socket types are the same across the system */
3579 3588 if (socketstr == NULL)
3580 3589 socketstr = _cpuid_sktstr(cpi->cpi_vendor, cpi->cpi_family,
3581 3590 cpi->cpi_model, cpi->cpi_step);
3582 3591
3583 3592
3584 3593 return (socketstr);
3585 3594 }
3586 3595
3587 3596 int
3588 3597 cpuid_get_chipid(cpu_t *cpu)
3589 3598 {
3590 3599 ASSERT(cpuid_checkpass(cpu, 1));
3591 3600
3592 3601 if (cpuid_is_cmt(cpu))
3593 3602 return (cpu->cpu_m.mcpu_cpi->cpi_chipid);
3594 3603 return (cpu->cpu_id);
3595 3604 }
3596 3605
3597 3606 id_t
3598 3607 cpuid_get_coreid(cpu_t *cpu)
3599 3608 {
3600 3609 ASSERT(cpuid_checkpass(cpu, 1));
3601 3610 return (cpu->cpu_m.mcpu_cpi->cpi_coreid);
3602 3611 }
3603 3612
3604 3613 int
3605 3614 cpuid_get_pkgcoreid(cpu_t *cpu)
3606 3615 {
3607 3616 ASSERT(cpuid_checkpass(cpu, 1));
3608 3617 return (cpu->cpu_m.mcpu_cpi->cpi_pkgcoreid);
3609 3618 }
3610 3619
3611 3620 int
3612 3621 cpuid_get_clogid(cpu_t *cpu)
3613 3622 {
3614 3623 ASSERT(cpuid_checkpass(cpu, 1));
3615 3624 return (cpu->cpu_m.mcpu_cpi->cpi_clogid);
3616 3625 }
3617 3626
3618 3627 int
3619 3628 cpuid_get_cacheid(cpu_t *cpu)
3620 3629 {
3621 3630 ASSERT(cpuid_checkpass(cpu, 1));
3622 3631 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid);
3623 3632 }
3624 3633
3625 3634 uint_t
3626 3635 cpuid_get_procnodeid(cpu_t *cpu)
3627 3636 {
3628 3637 ASSERT(cpuid_checkpass(cpu, 1));
3629 3638 return (cpu->cpu_m.mcpu_cpi->cpi_procnodeid);
3630 3639 }
3631 3640
3632 3641 uint_t
3633 3642 cpuid_get_procnodes_per_pkg(cpu_t *cpu)
3634 3643 {
3635 3644 ASSERT(cpuid_checkpass(cpu, 1));
3636 3645 return (cpu->cpu_m.mcpu_cpi->cpi_procnodes_per_pkg);
3637 3646 }
3638 3647
3639 3648 uint_t
3640 3649 cpuid_get_compunitid(cpu_t *cpu)
3641 3650 {
3642 3651 ASSERT(cpuid_checkpass(cpu, 1));
3643 3652 return (cpu->cpu_m.mcpu_cpi->cpi_compunitid);
3644 3653 }
3645 3654
3646 3655 uint_t
3647 3656 cpuid_get_cores_per_compunit(cpu_t *cpu)
3648 3657 {
3649 3658 ASSERT(cpuid_checkpass(cpu, 1));
3650 3659 return (cpu->cpu_m.mcpu_cpi->cpi_cores_per_compunit);
3651 3660 }
3652 3661
3653 3662 /*ARGSUSED*/
3654 3663 int
3655 3664 cpuid_have_cr8access(cpu_t *cpu)
3656 3665 {
3657 3666 #if defined(__amd64)
3658 3667 return (1);
3659 3668 #else
3660 3669 struct cpuid_info *cpi;
3661 3670
3662 3671 ASSERT(cpu != NULL);
3663 3672 cpi = cpu->cpu_m.mcpu_cpi;
3664 3673 if (cpi->cpi_vendor == X86_VENDOR_AMD && cpi->cpi_maxeax >= 1 &&
3665 3674 (CPI_FEATURES_XTD_ECX(cpi) & CPUID_AMD_ECX_CR8D) != 0)
3666 3675 return (1);
3667 3676 return (0);
3668 3677 #endif
3669 3678 }
3670 3679
3671 3680 uint32_t
3672 3681 cpuid_get_apicid(cpu_t *cpu)
3673 3682 {
3674 3683 ASSERT(cpuid_checkpass(cpu, 1));
3675 3684 if (cpu->cpu_m.mcpu_cpi->cpi_maxeax < 1) {
3676 3685 return (UINT32_MAX);
3677 3686 } else {
3678 3687 return (cpu->cpu_m.mcpu_cpi->cpi_apicid);
3679 3688 }
3680 3689 }
3681 3690
3682 3691 void
3683 3692 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits)
3684 3693 {
3685 3694 struct cpuid_info *cpi;
3686 3695
3687 3696 if (cpu == NULL)
3688 3697 cpu = CPU;
3689 3698 cpi = cpu->cpu_m.mcpu_cpi;
3690 3699
3691 3700 ASSERT(cpuid_checkpass(cpu, 1));
3692 3701
3693 3702 if (pabits)
3694 3703 *pabits = cpi->cpi_pabits;
3695 3704 if (vabits)
3696 3705 *vabits = cpi->cpi_vabits;
3697 3706 }
3698 3707
3699 3708 size_t
3700 3709 cpuid_get_xsave_size()
3701 3710 {
3702 3711 return (MAX(cpuid_info0.cpi_xsave.xsav_max_size,
3703 3712 sizeof (struct xsave_state)));
3704 3713 }
3705 3714
3706 3715 /*
3707 3716 * Return true if the CPUs on this system require 'pointer clearing' for the
3708 3717 * floating point error pointer exception handling. In the past, this has been
3709 3718 * true for all AMD K7 & K8 CPUs, although newer AMD CPUs have been changed to
3710 3719 * behave the same as Intel. This is checked via the CPUID_AMD_EBX_ERR_PTR_ZERO
3711 3720 * feature bit and is reflected in the cpi_fp_amd_save member.
3712 3721 */
3713 3722 boolean_t
3714 3723 cpuid_need_fp_excp_handling()
3715 3724 {
3716 3725 return (cpuid_info0.cpi_vendor == X86_VENDOR_AMD &&
3717 3726 cpuid_info0.cpi_fp_amd_save != 0);
3718 3727 }
3719 3728
3720 3729 /*
3721 3730 * Returns the number of data TLB entries for a corresponding
3722 3731 * pagesize. If it can't be computed, or isn't known, the
3723 3732 * routine returns zero. If you ask about an architecturally
3724 3733 * impossible pagesize, the routine will panic (so that the
3725 3734 * hat implementor knows that things are inconsistent.)
3726 3735 */
3727 3736 uint_t
3728 3737 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize)
3729 3738 {
3730 3739 struct cpuid_info *cpi;
3731 3740 uint_t dtlb_nent = 0;
3732 3741
3733 3742 if (cpu == NULL)
3734 3743 cpu = CPU;
3735 3744 cpi = cpu->cpu_m.mcpu_cpi;
3736 3745
3737 3746 ASSERT(cpuid_checkpass(cpu, 1));
3738 3747
3739 3748 /*
3740 3749 * Check the L2 TLB info
3741 3750 */
3742 3751 if (cpi->cpi_xmaxeax >= 0x80000006) {
3743 3752 struct cpuid_regs *cp = &cpi->cpi_extd[6];
3744 3753
3745 3754 switch (pagesize) {
3746 3755
3747 3756 case 4 * 1024:
3748 3757 /*
3749 3758 * All zero in the top 16 bits of the register
3750 3759 * indicates a unified TLB. Size is in low 16 bits.
3751 3760 */
3752 3761 if ((cp->cp_ebx & 0xffff0000) == 0)
3753 3762 dtlb_nent = cp->cp_ebx & 0x0000ffff;
3754 3763 else
3755 3764 dtlb_nent = BITX(cp->cp_ebx, 27, 16);
3756 3765 break;
3757 3766
3758 3767 case 2 * 1024 * 1024:
3759 3768 if ((cp->cp_eax & 0xffff0000) == 0)
3760 3769 dtlb_nent = cp->cp_eax & 0x0000ffff;
3761 3770 else
3762 3771 dtlb_nent = BITX(cp->cp_eax, 27, 16);
3763 3772 break;
3764 3773
3765 3774 default:
3766 3775 panic("unknown L2 pagesize");
3767 3776 /*NOTREACHED*/
3768 3777 }
3769 3778 }
3770 3779
3771 3780 if (dtlb_nent != 0)
3772 3781 return (dtlb_nent);
3773 3782
3774 3783 /*
3775 3784 * No L2 TLB support for this size, try L1.
3776 3785 */
3777 3786 if (cpi->cpi_xmaxeax >= 0x80000005) {
3778 3787 struct cpuid_regs *cp = &cpi->cpi_extd[5];
3779 3788
3780 3789 switch (pagesize) {
3781 3790 case 4 * 1024:
3782 3791 dtlb_nent = BITX(cp->cp_ebx, 23, 16);
3783 3792 break;
3784 3793 case 2 * 1024 * 1024:
3785 3794 dtlb_nent = BITX(cp->cp_eax, 23, 16);
3786 3795 break;
3787 3796 default:
3788 3797 panic("unknown L1 d-TLB pagesize");
3789 3798 /*NOTREACHED*/
3790 3799 }
3791 3800 }
3792 3801
3793 3802 return (dtlb_nent);
3794 3803 }
3795 3804
3796 3805 /*
3797 3806 * Return 0 if the erratum is not present or not applicable, positive
3798 3807 * if it is, and negative if the status of the erratum is unknown.
3799 3808 *
3800 3809 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm)
3801 3810 * Processors" #25759, Rev 3.57, August 2005
3802 3811 */
3803 3812 int
3804 3813 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum)
3805 3814 {
3806 3815 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
3807 3816 uint_t eax;
3808 3817
3809 3818 /*
3810 3819 * Bail out if this CPU isn't an AMD CPU, or if it's
3811 3820 * a legacy (32-bit) AMD CPU.
3812 3821 */
3813 3822 if (cpi->cpi_vendor != X86_VENDOR_AMD ||
3814 3823 cpi->cpi_family == 4 || cpi->cpi_family == 5 ||
3815 3824 cpi->cpi_family == 6)
3816 3825
3817 3826 return (0);
3818 3827
3819 3828 eax = cpi->cpi_std[1].cp_eax;
3820 3829
3821 3830 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50)
3822 3831 #define SH_B3(eax) (eax == 0xf51)
3823 3832 #define B(eax) (SH_B0(eax) || SH_B3(eax))
3824 3833
3825 3834 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58)
3826 3835
3827 3836 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a)
3828 3837 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0)
3829 3838 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2)
3830 3839 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax))
3831 3840
3832 3841 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70)
3833 3842 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0)
3834 3843 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0)
3835 3844 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax))
3836 3845
3837 3846 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70)
3838 3847 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */
3839 3848 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0)
3840 3849 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71)
3841 3850 #define BH_E4(eax) (eax == 0x20fb1)
3842 3851 #define SH_E5(eax) (eax == 0x20f42)
3843 3852 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2)
3844 3853 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32)
3845 3854 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \
3846 3855 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \
3847 3856 DH_E6(eax) || JH_E6(eax))
3848 3857
3849 3858 #define DR_AX(eax) (eax == 0x100f00 || eax == 0x100f01 || eax == 0x100f02)
3850 3859 #define DR_B0(eax) (eax == 0x100f20)
3851 3860 #define DR_B1(eax) (eax == 0x100f21)
3852 3861 #define DR_BA(eax) (eax == 0x100f2a)
3853 3862 #define DR_B2(eax) (eax == 0x100f22)
3854 3863 #define DR_B3(eax) (eax == 0x100f23)
3855 3864 #define RB_C0(eax) (eax == 0x100f40)
3856 3865
3857 3866 switch (erratum) {
3858 3867 case 1:
3859 3868 return (cpi->cpi_family < 0x10);
3860 3869 case 51: /* what does the asterisk mean? */
3861 3870 return (B(eax) || SH_C0(eax) || CG(eax));
3862 3871 case 52:
3863 3872 return (B(eax));
3864 3873 case 57:
3865 3874 return (cpi->cpi_family <= 0x11);
3866 3875 case 58:
3867 3876 return (B(eax));
3868 3877 case 60:
3869 3878 return (cpi->cpi_family <= 0x11);
3870 3879 case 61:
3871 3880 case 62:
3872 3881 case 63:
3873 3882 case 64:
3874 3883 case 65:
3875 3884 case 66:
3876 3885 case 68:
3877 3886 case 69:
3878 3887 case 70:
3879 3888 case 71:
3880 3889 return (B(eax));
3881 3890 case 72:
3882 3891 return (SH_B0(eax));
3883 3892 case 74:
3884 3893 return (B(eax));
3885 3894 case 75:
3886 3895 return (cpi->cpi_family < 0x10);
3887 3896 case 76:
3888 3897 return (B(eax));
3889 3898 case 77:
3890 3899 return (cpi->cpi_family <= 0x11);
3891 3900 case 78:
3892 3901 return (B(eax) || SH_C0(eax));
3893 3902 case 79:
3894 3903 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
3895 3904 case 80:
3896 3905 case 81:
3897 3906 case 82:
3898 3907 return (B(eax));
3899 3908 case 83:
3900 3909 return (B(eax) || SH_C0(eax) || CG(eax));
3901 3910 case 85:
3902 3911 return (cpi->cpi_family < 0x10);
3903 3912 case 86:
3904 3913 return (SH_C0(eax) || CG(eax));
3905 3914 case 88:
3906 3915 #if !defined(__amd64)
3907 3916 return (0);
3908 3917 #else
3909 3918 return (B(eax) || SH_C0(eax));
3910 3919 #endif
3911 3920 case 89:
3912 3921 return (cpi->cpi_family < 0x10);
3913 3922 case 90:
3914 3923 return (B(eax) || SH_C0(eax) || CG(eax));
3915 3924 case 91:
3916 3925 case 92:
3917 3926 return (B(eax) || SH_C0(eax));
3918 3927 case 93:
3919 3928 return (SH_C0(eax));
3920 3929 case 94:
3921 3930 return (B(eax) || SH_C0(eax) || CG(eax));
3922 3931 case 95:
3923 3932 #if !defined(__amd64)
3924 3933 return (0);
3925 3934 #else
3926 3935 return (B(eax) || SH_C0(eax));
3927 3936 #endif
3928 3937 case 96:
3929 3938 return (B(eax) || SH_C0(eax) || CG(eax));
3930 3939 case 97:
3931 3940 case 98:
3932 3941 return (SH_C0(eax) || CG(eax));
3933 3942 case 99:
3934 3943 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
3935 3944 case 100:
3936 3945 return (B(eax) || SH_C0(eax));
3937 3946 case 101:
3938 3947 case 103:
3939 3948 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
3940 3949 case 104:
3941 3950 return (SH_C0(eax) || CG(eax) || D0(eax));
3942 3951 case 105:
3943 3952 case 106:
3944 3953 case 107:
3945 3954 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
3946 3955 case 108:
3947 3956 return (DH_CG(eax));
3948 3957 case 109:
3949 3958 return (SH_C0(eax) || CG(eax) || D0(eax));
3950 3959 case 110:
3951 3960 return (D0(eax) || EX(eax));
3952 3961 case 111:
3953 3962 return (CG(eax));
3954 3963 case 112:
3955 3964 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
3956 3965 case 113:
3957 3966 return (eax == 0x20fc0);
3958 3967 case 114:
3959 3968 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax));
3960 3969 case 115:
3961 3970 return (SH_E0(eax) || JH_E1(eax));
3962 3971 case 116:
3963 3972 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax));
3964 3973 case 117:
3965 3974 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
3966 3975 case 118:
3967 3976 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) ||
3968 3977 JH_E6(eax));
3969 3978 case 121:
3970 3979 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
3971 3980 case 122:
3972 3981 return (cpi->cpi_family < 0x10 || cpi->cpi_family == 0x11);
3973 3982 case 123:
3974 3983 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax));
3975 3984 case 131:
3976 3985 return (cpi->cpi_family < 0x10);
3977 3986 case 6336786:
3978 3987 /*
3979 3988 * Test for AdvPowerMgmtInfo.TscPStateInvariant
3980 3989 * if this is a K8 family or newer processor
3981 3990 */
3982 3991 if (CPI_FAMILY(cpi) == 0xf) {
3983 3992 struct cpuid_regs regs;
3984 3993 regs.cp_eax = 0x80000007;
3985 3994 (void) __cpuid_insn(®s);
3986 3995 return (!(regs.cp_edx & 0x100));
3987 3996 }
3988 3997 return (0);
3989 3998 case 6323525:
3990 3999 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) |
3991 4000 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40);
3992 4001
3993 4002 case 6671130:
3994 4003 /*
3995 4004 * check for processors (pre-Shanghai) that do not provide
3996 4005 * optimal management of 1gb ptes in its tlb.
3997 4006 */
3998 4007 return (cpi->cpi_family == 0x10 && cpi->cpi_model < 4);
3999 4008
4000 4009 case 298:
4001 4010 return (DR_AX(eax) || DR_B0(eax) || DR_B1(eax) || DR_BA(eax) ||
4002 4011 DR_B2(eax) || RB_C0(eax));
4003 4012
4004 4013 case 721:
4005 4014 #if defined(__amd64)
4006 4015 return (cpi->cpi_family == 0x10 || cpi->cpi_family == 0x12);
4007 4016 #else
4008 4017 return (0);
4009 4018 #endif
4010 4019
4011 4020 default:
4012 4021 return (-1);
4013 4022
4014 4023 }
4015 4024 }
4016 4025
4017 4026 /*
4018 4027 * Determine if specified erratum is present via OSVW (OS Visible Workaround).
4019 4028 * Return 1 if erratum is present, 0 if not present and -1 if indeterminate.
4020 4029 */
4021 4030 int
4022 4031 osvw_opteron_erratum(cpu_t *cpu, uint_t erratum)
4023 4032 {
4024 4033 struct cpuid_info *cpi;
4025 4034 uint_t osvwid;
4026 4035 static int osvwfeature = -1;
4027 4036 uint64_t osvwlength;
4028 4037
4029 4038
4030 4039 cpi = cpu->cpu_m.mcpu_cpi;
4031 4040
4032 4041 /* confirm OSVW supported */
4033 4042 if (osvwfeature == -1) {
4034 4043 osvwfeature = cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW;
4035 4044 } else {
4036 4045 /* assert that osvw feature setting is consistent on all cpus */
4037 4046 ASSERT(osvwfeature ==
4038 4047 (cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW));
4039 4048 }
4040 4049 if (!osvwfeature)
4041 4050 return (-1);
4042 4051
4043 4052 osvwlength = rdmsr(MSR_AMD_OSVW_ID_LEN) & OSVW_ID_LEN_MASK;
4044 4053
4045 4054 switch (erratum) {
4046 4055 case 298: /* osvwid is 0 */
4047 4056 osvwid = 0;
4048 4057 if (osvwlength <= (uint64_t)osvwid) {
4049 4058 /* osvwid 0 is unknown */
4050 4059 return (-1);
4051 4060 }
4052 4061
4053 4062 /*
4054 4063 * Check the OSVW STATUS MSR to determine the state
4055 4064 * of the erratum where:
4056 4065 * 0 - fixed by HW
4057 4066 * 1 - BIOS has applied the workaround when BIOS
4058 4067 * workaround is available. (Or for other errata,
4059 4068 * OS workaround is required.)
4060 4069 * For a value of 1, caller will confirm that the
4061 4070 * erratum 298 workaround has indeed been applied by BIOS.
4062 4071 *
4063 4072 * A 1 may be set in cpus that have a HW fix
4064 4073 * in a mixed cpu system. Regarding erratum 298:
4065 4074 * In a multiprocessor platform, the workaround above
4066 4075 * should be applied to all processors regardless of
4067 4076 * silicon revision when an affected processor is
4068 4077 * present.
4069 4078 */
4070 4079
4071 4080 return (rdmsr(MSR_AMD_OSVW_STATUS +
4072 4081 (osvwid / OSVW_ID_CNT_PER_MSR)) &
4073 4082 (1ULL << (osvwid % OSVW_ID_CNT_PER_MSR)));
4074 4083
4075 4084 default:
4076 4085 return (-1);
4077 4086 }
4078 4087 }
4079 4088
4080 4089 static const char assoc_str[] = "associativity";
4081 4090 static const char line_str[] = "line-size";
4082 4091 static const char size_str[] = "size";
4083 4092
4084 4093 static void
4085 4094 add_cache_prop(dev_info_t *devi, const char *label, const char *type,
4086 4095 uint32_t val)
4087 4096 {
4088 4097 char buf[128];
4089 4098
4090 4099 /*
4091 4100 * ndi_prop_update_int() is used because it is desirable for
4092 4101 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set.
4093 4102 */
4094 4103 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf))
4095 4104 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val);
4096 4105 }
4097 4106
4098 4107 /*
4099 4108 * Intel-style cache/tlb description
4100 4109 *
4101 4110 * Standard cpuid level 2 gives a randomly ordered
4102 4111 * selection of tags that index into a table that describes
4103 4112 * cache and tlb properties.
4104 4113 */
4105 4114
4106 4115 static const char l1_icache_str[] = "l1-icache";
4107 4116 static const char l1_dcache_str[] = "l1-dcache";
4108 4117 static const char l2_cache_str[] = "l2-cache";
4109 4118 static const char l3_cache_str[] = "l3-cache";
4110 4119 static const char itlb4k_str[] = "itlb-4K";
4111 4120 static const char dtlb4k_str[] = "dtlb-4K";
4112 4121 static const char itlb2M_str[] = "itlb-2M";
4113 4122 static const char itlb4M_str[] = "itlb-4M";
4114 4123 static const char dtlb4M_str[] = "dtlb-4M";
4115 4124 static const char dtlb24_str[] = "dtlb0-2M-4M";
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4116 4125 static const char itlb424_str[] = "itlb-4K-2M-4M";
4117 4126 static const char itlb24_str[] = "itlb-2M-4M";
4118 4127 static const char dtlb44_str[] = "dtlb-4K-4M";
4119 4128 static const char sl1_dcache_str[] = "sectored-l1-dcache";
4120 4129 static const char sl2_cache_str[] = "sectored-l2-cache";
4121 4130 static const char itrace_str[] = "itrace-cache";
4122 4131 static const char sl3_cache_str[] = "sectored-l3-cache";
4123 4132 static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k";
4124 4133
4125 4134 static const struct cachetab {
4126 - uint8_t ct_code;
4135 + uint8_t ct_code;
4127 4136 uint8_t ct_assoc;
4128 4137 uint16_t ct_line_size;
4129 4138 size_t ct_size;
4130 4139 const char *ct_label;
4131 4140 } intel_ctab[] = {
4132 4141 /*
4133 4142 * maintain descending order!
4134 4143 *
4135 4144 * Codes ignored - Reason
4136 4145 * ----------------------
4137 4146 * 40H - intel_cpuid_4_cache_info() disambiguates l2/l3 cache
4138 4147 * f0H/f1H - Currently we do not interpret prefetch size by design
4139 4148 */
4140 4149 { 0xe4, 16, 64, 8*1024*1024, l3_cache_str},
4141 4150 { 0xe3, 16, 64, 4*1024*1024, l3_cache_str},
4142 4151 { 0xe2, 16, 64, 2*1024*1024, l3_cache_str},
4143 4152 { 0xde, 12, 64, 6*1024*1024, l3_cache_str},
4144 4153 { 0xdd, 12, 64, 3*1024*1024, l3_cache_str},
4145 4154 { 0xdc, 12, 64, ((1*1024*1024)+(512*1024)), l3_cache_str},
4146 4155 { 0xd8, 8, 64, 4*1024*1024, l3_cache_str},
4147 4156 { 0xd7, 8, 64, 2*1024*1024, l3_cache_str},
4148 4157 { 0xd6, 8, 64, 1*1024*1024, l3_cache_str},
4149 4158 { 0xd2, 4, 64, 2*1024*1024, l3_cache_str},
4150 4159 { 0xd1, 4, 64, 1*1024*1024, l3_cache_str},
4151 4160 { 0xd0, 4, 64, 512*1024, l3_cache_str},
4152 4161 { 0xca, 4, 0, 512, sh_l2_tlb4k_str},
4153 4162 { 0xc0, 4, 0, 8, dtlb44_str },
4154 4163 { 0xba, 4, 0, 64, dtlb4k_str },
4155 4164 { 0xb4, 4, 0, 256, dtlb4k_str },
4156 4165 { 0xb3, 4, 0, 128, dtlb4k_str },
4157 4166 { 0xb2, 4, 0, 64, itlb4k_str },
4158 4167 { 0xb0, 4, 0, 128, itlb4k_str },
4159 4168 { 0x87, 8, 64, 1024*1024, l2_cache_str},
4160 4169 { 0x86, 4, 64, 512*1024, l2_cache_str},
4161 4170 { 0x85, 8, 32, 2*1024*1024, l2_cache_str},
4162 4171 { 0x84, 8, 32, 1024*1024, l2_cache_str},
4163 4172 { 0x83, 8, 32, 512*1024, l2_cache_str},
4164 4173 { 0x82, 8, 32, 256*1024, l2_cache_str},
4165 4174 { 0x80, 8, 64, 512*1024, l2_cache_str},
4166 4175 { 0x7f, 2, 64, 512*1024, l2_cache_str},
4167 4176 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str},
4168 4177 { 0x7c, 8, 64, 1024*1024, sl2_cache_str},
4169 4178 { 0x7b, 8, 64, 512*1024, sl2_cache_str},
4170 4179 { 0x7a, 8, 64, 256*1024, sl2_cache_str},
4171 4180 { 0x79, 8, 64, 128*1024, sl2_cache_str},
4172 4181 { 0x78, 8, 64, 1024*1024, l2_cache_str},
4173 4182 { 0x73, 8, 0, 64*1024, itrace_str},
4174 4183 { 0x72, 8, 0, 32*1024, itrace_str},
4175 4184 { 0x71, 8, 0, 16*1024, itrace_str},
4176 4185 { 0x70, 8, 0, 12*1024, itrace_str},
4177 4186 { 0x68, 4, 64, 32*1024, sl1_dcache_str},
4178 4187 { 0x67, 4, 64, 16*1024, sl1_dcache_str},
4179 4188 { 0x66, 4, 64, 8*1024, sl1_dcache_str},
4180 4189 { 0x60, 8, 64, 16*1024, sl1_dcache_str},
4181 4190 { 0x5d, 0, 0, 256, dtlb44_str},
4182 4191 { 0x5c, 0, 0, 128, dtlb44_str},
4183 4192 { 0x5b, 0, 0, 64, dtlb44_str},
4184 4193 { 0x5a, 4, 0, 32, dtlb24_str},
4185 4194 { 0x59, 0, 0, 16, dtlb4k_str},
4186 4195 { 0x57, 4, 0, 16, dtlb4k_str},
4187 4196 { 0x56, 4, 0, 16, dtlb4M_str},
4188 4197 { 0x55, 0, 0, 7, itlb24_str},
4189 4198 { 0x52, 0, 0, 256, itlb424_str},
4190 4199 { 0x51, 0, 0, 128, itlb424_str},
4191 4200 { 0x50, 0, 0, 64, itlb424_str},
4192 4201 { 0x4f, 0, 0, 32, itlb4k_str},
4193 4202 { 0x4e, 24, 64, 6*1024*1024, l2_cache_str},
4194 4203 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str},
4195 4204 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str},
4196 4205 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str},
4197 4206 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str},
4198 4207 { 0x49, 16, 64, 4*1024*1024, l3_cache_str},
4199 4208 { 0x48, 12, 64, 3*1024*1024, l2_cache_str},
4200 4209 { 0x47, 8, 64, 8*1024*1024, l3_cache_str},
4201 4210 { 0x46, 4, 64, 4*1024*1024, l3_cache_str},
4202 4211 { 0x45, 4, 32, 2*1024*1024, l2_cache_str},
4203 4212 { 0x44, 4, 32, 1024*1024, l2_cache_str},
4204 4213 { 0x43, 4, 32, 512*1024, l2_cache_str},
4205 4214 { 0x42, 4, 32, 256*1024, l2_cache_str},
4206 4215 { 0x41, 4, 32, 128*1024, l2_cache_str},
4207 4216 { 0x3e, 4, 64, 512*1024, sl2_cache_str},
4208 4217 { 0x3d, 6, 64, 384*1024, sl2_cache_str},
4209 4218 { 0x3c, 4, 64, 256*1024, sl2_cache_str},
4210 4219 { 0x3b, 2, 64, 128*1024, sl2_cache_str},
4211 4220 { 0x3a, 6, 64, 192*1024, sl2_cache_str},
4212 4221 { 0x39, 4, 64, 128*1024, sl2_cache_str},
4213 4222 { 0x30, 8, 64, 32*1024, l1_icache_str},
4214 4223 { 0x2c, 8, 64, 32*1024, l1_dcache_str},
4215 4224 { 0x29, 8, 64, 4096*1024, sl3_cache_str},
4216 4225 { 0x25, 8, 64, 2048*1024, sl3_cache_str},
4217 4226 { 0x23, 8, 64, 1024*1024, sl3_cache_str},
4218 4227 { 0x22, 4, 64, 512*1024, sl3_cache_str},
4219 4228 { 0x0e, 6, 64, 24*1024, l1_dcache_str},
4220 4229 { 0x0d, 4, 32, 16*1024, l1_dcache_str},
4221 4230 { 0x0c, 4, 32, 16*1024, l1_dcache_str},
4222 4231 { 0x0b, 4, 0, 4, itlb4M_str},
4223 4232 { 0x0a, 2, 32, 8*1024, l1_dcache_str},
4224 4233 { 0x08, 4, 32, 16*1024, l1_icache_str},
4225 4234 { 0x06, 4, 32, 8*1024, l1_icache_str},
4226 4235 { 0x05, 4, 0, 32, dtlb4M_str},
4227 4236 { 0x04, 4, 0, 8, dtlb4M_str},
4228 4237 { 0x03, 4, 0, 64, dtlb4k_str},
4229 4238 { 0x02, 4, 0, 2, itlb4M_str},
4230 4239 { 0x01, 4, 0, 32, itlb4k_str},
4231 4240 { 0 }
4232 4241 };
4233 4242
4234 4243 static const struct cachetab cyrix_ctab[] = {
4235 4244 { 0x70, 4, 0, 32, "tlb-4K" },
4236 4245 { 0x80, 4, 16, 16*1024, "l1-cache" },
4237 4246 { 0 }
4238 4247 };
4239 4248
4240 4249 /*
4241 4250 * Search a cache table for a matching entry
4242 4251 */
4243 4252 static const struct cachetab *
4244 4253 find_cacheent(const struct cachetab *ct, uint_t code)
4245 4254 {
4246 4255 if (code != 0) {
4247 4256 for (; ct->ct_code != 0; ct++)
4248 4257 if (ct->ct_code <= code)
4249 4258 break;
4250 4259 if (ct->ct_code == code)
4251 4260 return (ct);
4252 4261 }
4253 4262 return (NULL);
4254 4263 }
4255 4264
4256 4265 /*
4257 4266 * Populate cachetab entry with L2 or L3 cache-information using
4258 4267 * cpuid function 4. This function is called from intel_walk_cacheinfo()
4259 4268 * when descriptor 0x49 is encountered. It returns 0 if no such cache
4260 4269 * information is found.
4261 4270 */
4262 4271 static int
4263 4272 intel_cpuid_4_cache_info(struct cachetab *ct, struct cpuid_info *cpi)
4264 4273 {
4265 4274 uint32_t level, i;
4266 4275 int ret = 0;
4267 4276
4268 4277 for (i = 0; i < cpi->cpi_std_4_size; i++) {
4269 4278 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]);
4270 4279
4271 4280 if (level == 2 || level == 3) {
4272 4281 ct->ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1;
4273 4282 ct->ct_line_size =
4274 4283 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1;
4275 4284 ct->ct_size = ct->ct_assoc *
4276 4285 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) *
4277 4286 ct->ct_line_size *
4278 4287 (cpi->cpi_std_4[i]->cp_ecx + 1);
4279 4288
4280 4289 if (level == 2) {
4281 4290 ct->ct_label = l2_cache_str;
4282 4291 } else if (level == 3) {
4283 4292 ct->ct_label = l3_cache_str;
4284 4293 }
4285 4294 ret = 1;
4286 4295 }
4287 4296 }
4288 4297
4289 4298 return (ret);
4290 4299 }
4291 4300
4292 4301 /*
4293 4302 * Walk the cacheinfo descriptor, applying 'func' to every valid element
4294 4303 * The walk is terminated if the walker returns non-zero.
4295 4304 */
4296 4305 static void
4297 4306 intel_walk_cacheinfo(struct cpuid_info *cpi,
4298 4307 void *arg, int (*func)(void *, const struct cachetab *))
4299 4308 {
4300 4309 const struct cachetab *ct;
4301 4310 struct cachetab des_49_ct, des_b1_ct;
4302 4311 uint8_t *dp;
4303 4312 int i;
4304 4313
4305 4314 if ((dp = cpi->cpi_cacheinfo) == NULL)
4306 4315 return;
4307 4316 for (i = 0; i < cpi->cpi_ncache; i++, dp++) {
4308 4317 /*
4309 4318 * For overloaded descriptor 0x49 we use cpuid function 4
4310 4319 * if supported by the current processor, to create
4311 4320 * cache information.
4312 4321 * For overloaded descriptor 0xb1 we use X86_PAE flag
4313 4322 * to disambiguate the cache information.
4314 4323 */
4315 4324 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4 &&
4316 4325 intel_cpuid_4_cache_info(&des_49_ct, cpi) == 1) {
4317 4326 ct = &des_49_ct;
4318 4327 } else if (*dp == 0xb1) {
4319 4328 des_b1_ct.ct_code = 0xb1;
4320 4329 des_b1_ct.ct_assoc = 4;
4321 4330 des_b1_ct.ct_line_size = 0;
4322 4331 if (is_x86_feature(x86_featureset, X86FSET_PAE)) {
4323 4332 des_b1_ct.ct_size = 8;
4324 4333 des_b1_ct.ct_label = itlb2M_str;
4325 4334 } else {
4326 4335 des_b1_ct.ct_size = 4;
4327 4336 des_b1_ct.ct_label = itlb4M_str;
4328 4337 }
4329 4338 ct = &des_b1_ct;
4330 4339 } else {
4331 4340 if ((ct = find_cacheent(intel_ctab, *dp)) == NULL) {
4332 4341 continue;
4333 4342 }
4334 4343 }
4335 4344
4336 4345 if (func(arg, ct) != 0) {
4337 4346 break;
4338 4347 }
4339 4348 }
4340 4349 }
4341 4350
4342 4351 /*
4343 4352 * (Like the Intel one, except for Cyrix CPUs)
4344 4353 */
4345 4354 static void
4346 4355 cyrix_walk_cacheinfo(struct cpuid_info *cpi,
4347 4356 void *arg, int (*func)(void *, const struct cachetab *))
4348 4357 {
4349 4358 const struct cachetab *ct;
4350 4359 uint8_t *dp;
4351 4360 int i;
4352 4361
4353 4362 if ((dp = cpi->cpi_cacheinfo) == NULL)
4354 4363 return;
4355 4364 for (i = 0; i < cpi->cpi_ncache; i++, dp++) {
4356 4365 /*
4357 4366 * Search Cyrix-specific descriptor table first ..
4358 4367 */
4359 4368 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) {
4360 4369 if (func(arg, ct) != 0)
4361 4370 break;
4362 4371 continue;
4363 4372 }
4364 4373 /*
4365 4374 * .. else fall back to the Intel one
4366 4375 */
4367 4376 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) {
4368 4377 if (func(arg, ct) != 0)
4369 4378 break;
4370 4379 continue;
4371 4380 }
4372 4381 }
4373 4382 }
4374 4383
4375 4384 /*
4376 4385 * A cacheinfo walker that adds associativity, line-size, and size properties
4377 4386 * to the devinfo node it is passed as an argument.
4378 4387 */
4379 4388 static int
4380 4389 add_cacheent_props(void *arg, const struct cachetab *ct)
4381 4390 {
4382 4391 dev_info_t *devi = arg;
4383 4392
4384 4393 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc);
4385 4394 if (ct->ct_line_size != 0)
4386 4395 add_cache_prop(devi, ct->ct_label, line_str,
4387 4396 ct->ct_line_size);
4388 4397 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size);
4389 4398 return (0);
4390 4399 }
4391 4400
4392 4401
4393 4402 static const char fully_assoc[] = "fully-associative?";
4394 4403
4395 4404 /*
4396 4405 * AMD style cache/tlb description
4397 4406 *
4398 4407 * Extended functions 5 and 6 directly describe properties of
4399 4408 * tlbs and various cache levels.
4400 4409 */
4401 4410 static void
4402 4411 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc)
4403 4412 {
4404 4413 switch (assoc) {
4405 4414 case 0: /* reserved; ignore */
4406 4415 break;
4407 4416 default:
4408 4417 add_cache_prop(devi, label, assoc_str, assoc);
4409 4418 break;
4410 4419 case 0xff:
4411 4420 add_cache_prop(devi, label, fully_assoc, 1);
4412 4421 break;
4413 4422 }
4414 4423 }
4415 4424
4416 4425 static void
4417 4426 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size)
4418 4427 {
4419 4428 if (size == 0)
4420 4429 return;
4421 4430 add_cache_prop(devi, label, size_str, size);
4422 4431 add_amd_assoc(devi, label, assoc);
4423 4432 }
4424 4433
4425 4434 static void
4426 4435 add_amd_cache(dev_info_t *devi, const char *label,
4427 4436 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size)
4428 4437 {
4429 4438 if (size == 0 || line_size == 0)
4430 4439 return;
4431 4440 add_amd_assoc(devi, label, assoc);
4432 4441 /*
4433 4442 * Most AMD parts have a sectored cache. Multiple cache lines are
4434 4443 * associated with each tag. A sector consists of all cache lines
4435 4444 * associated with a tag. For example, the AMD K6-III has a sector
4436 4445 * size of 2 cache lines per tag.
4437 4446 */
4438 4447 if (lines_per_tag != 0)
4439 4448 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag);
4440 4449 add_cache_prop(devi, label, line_str, line_size);
4441 4450 add_cache_prop(devi, label, size_str, size * 1024);
4442 4451 }
4443 4452
4444 4453 static void
4445 4454 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc)
4446 4455 {
4447 4456 switch (assoc) {
4448 4457 case 0: /* off */
4449 4458 break;
4450 4459 case 1:
4451 4460 case 2:
4452 4461 case 4:
4453 4462 add_cache_prop(devi, label, assoc_str, assoc);
4454 4463 break;
4455 4464 case 6:
4456 4465 add_cache_prop(devi, label, assoc_str, 8);
4457 4466 break;
4458 4467 case 8:
4459 4468 add_cache_prop(devi, label, assoc_str, 16);
4460 4469 break;
4461 4470 case 0xf:
4462 4471 add_cache_prop(devi, label, fully_assoc, 1);
4463 4472 break;
4464 4473 default: /* reserved; ignore */
4465 4474 break;
4466 4475 }
4467 4476 }
4468 4477
4469 4478 static void
4470 4479 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size)
4471 4480 {
4472 4481 if (size == 0 || assoc == 0)
4473 4482 return;
4474 4483 add_amd_l2_assoc(devi, label, assoc);
4475 4484 add_cache_prop(devi, label, size_str, size);
4476 4485 }
4477 4486
4478 4487 static void
4479 4488 add_amd_l2_cache(dev_info_t *devi, const char *label,
4480 4489 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size)
4481 4490 {
4482 4491 if (size == 0 || assoc == 0 || line_size == 0)
4483 4492 return;
4484 4493 add_amd_l2_assoc(devi, label, assoc);
4485 4494 if (lines_per_tag != 0)
4486 4495 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag);
4487 4496 add_cache_prop(devi, label, line_str, line_size);
4488 4497 add_cache_prop(devi, label, size_str, size * 1024);
4489 4498 }
4490 4499
4491 4500 static void
4492 4501 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi)
4493 4502 {
4494 4503 struct cpuid_regs *cp;
4495 4504
4496 4505 if (cpi->cpi_xmaxeax < 0x80000005)
4497 4506 return;
4498 4507 cp = &cpi->cpi_extd[5];
4499 4508
4500 4509 /*
4501 4510 * 4M/2M L1 TLB configuration
4502 4511 *
4503 4512 * We report the size for 2M pages because AMD uses two
4504 4513 * TLB entries for one 4M page.
4505 4514 */
4506 4515 add_amd_tlb(devi, "dtlb-2M",
4507 4516 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16));
4508 4517 add_amd_tlb(devi, "itlb-2M",
4509 4518 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0));
4510 4519
4511 4520 /*
4512 4521 * 4K L1 TLB configuration
4513 4522 */
4514 4523
4515 4524 switch (cpi->cpi_vendor) {
4516 4525 uint_t nentries;
4517 4526 case X86_VENDOR_TM:
4518 4527 if (cpi->cpi_family >= 5) {
4519 4528 /*
4520 4529 * Crusoe processors have 256 TLB entries, but
4521 4530 * cpuid data format constrains them to only
4522 4531 * reporting 255 of them.
4523 4532 */
4524 4533 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255)
4525 4534 nentries = 256;
4526 4535 /*
4527 4536 * Crusoe processors also have a unified TLB
4528 4537 */
4529 4538 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24),
4530 4539 nentries);
4531 4540 break;
4532 4541 }
4533 4542 /*FALLTHROUGH*/
4534 4543 default:
4535 4544 add_amd_tlb(devi, itlb4k_str,
4536 4545 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16));
4537 4546 add_amd_tlb(devi, dtlb4k_str,
4538 4547 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0));
4539 4548 break;
4540 4549 }
4541 4550
4542 4551 /*
4543 4552 * data L1 cache configuration
4544 4553 */
4545 4554
4546 4555 add_amd_cache(devi, l1_dcache_str,
4547 4556 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16),
4548 4557 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0));
4549 4558
4550 4559 /*
4551 4560 * code L1 cache configuration
4552 4561 */
4553 4562
4554 4563 add_amd_cache(devi, l1_icache_str,
4555 4564 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16),
4556 4565 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0));
4557 4566
4558 4567 if (cpi->cpi_xmaxeax < 0x80000006)
4559 4568 return;
4560 4569 cp = &cpi->cpi_extd[6];
4561 4570
4562 4571 /* Check for a unified L2 TLB for large pages */
4563 4572
4564 4573 if (BITX(cp->cp_eax, 31, 16) == 0)
4565 4574 add_amd_l2_tlb(devi, "l2-tlb-2M",
4566 4575 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
4567 4576 else {
4568 4577 add_amd_l2_tlb(devi, "l2-dtlb-2M",
4569 4578 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));
4570 4579 add_amd_l2_tlb(devi, "l2-itlb-2M",
4571 4580 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
4572 4581 }
4573 4582
4574 4583 /* Check for a unified L2 TLB for 4K pages */
4575 4584
4576 4585 if (BITX(cp->cp_ebx, 31, 16) == 0) {
4577 4586 add_amd_l2_tlb(devi, "l2-tlb-4K",
4578 4587 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
4579 4588 } else {
4580 4589 add_amd_l2_tlb(devi, "l2-dtlb-4K",
4581 4590 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));
4582 4591 add_amd_l2_tlb(devi, "l2-itlb-4K",
4583 4592 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
4584 4593 }
4585 4594
4586 4595 add_amd_l2_cache(devi, l2_cache_str,
4587 4596 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12),
4588 4597 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0));
4589 4598 }
4590 4599
4591 4600 /*
4592 4601 * There are two basic ways that the x86 world describes it cache
4593 4602 * and tlb architecture - Intel's way and AMD's way.
4594 4603 *
4595 4604 * Return which flavor of cache architecture we should use
4596 4605 */
4597 4606 static int
4598 4607 x86_which_cacheinfo(struct cpuid_info *cpi)
4599 4608 {
4600 4609 switch (cpi->cpi_vendor) {
4601 4610 case X86_VENDOR_Intel:
4602 4611 if (cpi->cpi_maxeax >= 2)
4603 4612 return (X86_VENDOR_Intel);
4604 4613 break;
4605 4614 case X86_VENDOR_AMD:
4606 4615 /*
4607 4616 * The K5 model 1 was the first part from AMD that reported
4608 4617 * cache sizes via extended cpuid functions.
4609 4618 */
4610 4619 if (cpi->cpi_family > 5 ||
4611 4620 (cpi->cpi_family == 5 && cpi->cpi_model >= 1))
4612 4621 return (X86_VENDOR_AMD);
4613 4622 break;
4614 4623 case X86_VENDOR_TM:
4615 4624 if (cpi->cpi_family >= 5)
4616 4625 return (X86_VENDOR_AMD);
4617 4626 /*FALLTHROUGH*/
4618 4627 default:
4619 4628 /*
4620 4629 * If they have extended CPU data for 0x80000005
4621 4630 * then we assume they have AMD-format cache
4622 4631 * information.
4623 4632 *
4624 4633 * If not, and the vendor happens to be Cyrix,
4625 4634 * then try our-Cyrix specific handler.
4626 4635 *
4627 4636 * If we're not Cyrix, then assume we're using Intel's
4628 4637 * table-driven format instead.
4629 4638 */
4630 4639 if (cpi->cpi_xmaxeax >= 0x80000005)
4631 4640 return (X86_VENDOR_AMD);
4632 4641 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix)
4633 4642 return (X86_VENDOR_Cyrix);
4634 4643 else if (cpi->cpi_maxeax >= 2)
4635 4644 return (X86_VENDOR_Intel);
4636 4645 break;
4637 4646 }
4638 4647 return (-1);
4639 4648 }
4640 4649
4641 4650 void
4642 4651 cpuid_set_cpu_properties(void *dip, processorid_t cpu_id,
4643 4652 struct cpuid_info *cpi)
4644 4653 {
4645 4654 dev_info_t *cpu_devi;
4646 4655 int create;
4647 4656
4648 4657 cpu_devi = (dev_info_t *)dip;
4649 4658
4650 4659 /* device_type */
4651 4660 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
4652 4661 "device_type", "cpu");
4653 4662
4654 4663 /* reg */
4655 4664 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4656 4665 "reg", cpu_id);
4657 4666
4658 4667 /* cpu-mhz, and clock-frequency */
4659 4668 if (cpu_freq > 0) {
4660 4669 long long mul;
4661 4670
4662 4671 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4663 4672 "cpu-mhz", cpu_freq);
4664 4673 if ((mul = cpu_freq * 1000000LL) <= INT_MAX)
4665 4674 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4666 4675 "clock-frequency", (int)mul);
4667 4676 }
4668 4677
4669 4678 if (!is_x86_feature(x86_featureset, X86FSET_CPUID)) {
4670 4679 return;
4671 4680 }
4672 4681
4673 4682 /* vendor-id */
4674 4683 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
4675 4684 "vendor-id", cpi->cpi_vendorstr);
4676 4685
4677 4686 if (cpi->cpi_maxeax == 0) {
4678 4687 return;
4679 4688 }
4680 4689
4681 4690 /*
4682 4691 * family, model, and step
4683 4692 */
4684 4693 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4685 4694 "family", CPI_FAMILY(cpi));
4686 4695 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4687 4696 "cpu-model", CPI_MODEL(cpi));
4688 4697 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4689 4698 "stepping-id", CPI_STEP(cpi));
4690 4699
4691 4700 /* type */
4692 4701 switch (cpi->cpi_vendor) {
4693 4702 case X86_VENDOR_Intel:
4694 4703 create = 1;
4695 4704 break;
4696 4705 default:
4697 4706 create = 0;
4698 4707 break;
4699 4708 }
4700 4709 if (create)
4701 4710 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4702 4711 "type", CPI_TYPE(cpi));
4703 4712
4704 4713 /* ext-family */
4705 4714 switch (cpi->cpi_vendor) {
4706 4715 case X86_VENDOR_Intel:
4707 4716 case X86_VENDOR_AMD:
4708 4717 create = cpi->cpi_family >= 0xf;
4709 4718 break;
4710 4719 default:
4711 4720 create = 0;
4712 4721 break;
4713 4722 }
4714 4723 if (create)
4715 4724 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4716 4725 "ext-family", CPI_FAMILY_XTD(cpi));
4717 4726
4718 4727 /* ext-model */
4719 4728 switch (cpi->cpi_vendor) {
4720 4729 case X86_VENDOR_Intel:
4721 4730 create = IS_EXTENDED_MODEL_INTEL(cpi);
4722 4731 break;
4723 4732 case X86_VENDOR_AMD:
4724 4733 create = CPI_FAMILY(cpi) == 0xf;
4725 4734 break;
4726 4735 default:
4727 4736 create = 0;
4728 4737 break;
4729 4738 }
4730 4739 if (create)
4731 4740 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4732 4741 "ext-model", CPI_MODEL_XTD(cpi));
4733 4742
4734 4743 /* generation */
4735 4744 switch (cpi->cpi_vendor) {
4736 4745 case X86_VENDOR_AMD:
4737 4746 /*
4738 4747 * AMD K5 model 1 was the first part to support this
4739 4748 */
4740 4749 create = cpi->cpi_xmaxeax >= 0x80000001;
4741 4750 break;
4742 4751 default:
4743 4752 create = 0;
4744 4753 break;
4745 4754 }
4746 4755 if (create)
4747 4756 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4748 4757 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8));
4749 4758
4750 4759 /* brand-id */
4751 4760 switch (cpi->cpi_vendor) {
4752 4761 case X86_VENDOR_Intel:
4753 4762 /*
4754 4763 * brand id first appeared on Pentium III Xeon model 8,
4755 4764 * and Celeron model 8 processors and Opteron
4756 4765 */
4757 4766 create = cpi->cpi_family > 6 ||
4758 4767 (cpi->cpi_family == 6 && cpi->cpi_model >= 8);
4759 4768 break;
4760 4769 case X86_VENDOR_AMD:
4761 4770 create = cpi->cpi_family >= 0xf;
4762 4771 break;
4763 4772 default:
4764 4773 create = 0;
4765 4774 break;
4766 4775 }
4767 4776 if (create && cpi->cpi_brandid != 0) {
4768 4777 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4769 4778 "brand-id", cpi->cpi_brandid);
4770 4779 }
4771 4780
4772 4781 /* chunks, and apic-id */
4773 4782 switch (cpi->cpi_vendor) {
4774 4783 /*
4775 4784 * first available on Pentium IV and Opteron (K8)
4776 4785 */
4777 4786 case X86_VENDOR_Intel:
4778 4787 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf;
4779 4788 break;
4780 4789 case X86_VENDOR_AMD:
4781 4790 create = cpi->cpi_family >= 0xf;
4782 4791 break;
4783 4792 default:
4784 4793 create = 0;
4785 4794 break;
4786 4795 }
4787 4796 if (create) {
4788 4797 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4789 4798 "chunks", CPI_CHUNKS(cpi));
4790 4799 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4791 4800 "apic-id", cpi->cpi_apicid);
4792 4801 if (cpi->cpi_chipid >= 0) {
4793 4802 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4794 4803 "chip#", cpi->cpi_chipid);
4795 4804 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4796 4805 "clog#", cpi->cpi_clogid);
4797 4806 }
4798 4807 }
4799 4808
4800 4809 /* cpuid-features */
4801 4810 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4802 4811 "cpuid-features", CPI_FEATURES_EDX(cpi));
4803 4812
4804 4813
4805 4814 /* cpuid-features-ecx */
4806 4815 switch (cpi->cpi_vendor) {
4807 4816 case X86_VENDOR_Intel:
4808 4817 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf;
4809 4818 break;
4810 4819 case X86_VENDOR_AMD:
4811 4820 create = cpi->cpi_family >= 0xf;
4812 4821 break;
4813 4822 default:
4814 4823 create = 0;
4815 4824 break;
4816 4825 }
4817 4826 if (create)
4818 4827 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4819 4828 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi));
4820 4829
4821 4830 /* ext-cpuid-features */
4822 4831 switch (cpi->cpi_vendor) {
4823 4832 case X86_VENDOR_Intel:
4824 4833 case X86_VENDOR_AMD:
4825 4834 case X86_VENDOR_Cyrix:
4826 4835 case X86_VENDOR_TM:
4827 4836 case X86_VENDOR_Centaur:
4828 4837 create = cpi->cpi_xmaxeax >= 0x80000001;
4829 4838 break;
4830 4839 default:
4831 4840 create = 0;
4832 4841 break;
4833 4842 }
4834 4843 if (create) {
4835 4844 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4836 4845 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi));
4837 4846 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4838 4847 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi));
4839 4848 }
4840 4849
4841 4850 /*
4842 4851 * Brand String first appeared in Intel Pentium IV, AMD K5
4843 4852 * model 1, and Cyrix GXm. On earlier models we try and
4844 4853 * simulate something similar .. so this string should always
4845 4854 * same -something- about the processor, however lame.
4846 4855 */
4847 4856 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
4848 4857 "brand-string", cpi->cpi_brandstr);
4849 4858
4850 4859 /*
4851 4860 * Finally, cache and tlb information
4852 4861 */
4853 4862 switch (x86_which_cacheinfo(cpi)) {
4854 4863 case X86_VENDOR_Intel:
4855 4864 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props);
4856 4865 break;
4857 4866 case X86_VENDOR_Cyrix:
4858 4867 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props);
4859 4868 break;
4860 4869 case X86_VENDOR_AMD:
4861 4870 amd_cache_info(cpi, cpu_devi);
4862 4871 break;
4863 4872 default:
4864 4873 break;
4865 4874 }
4866 4875 }
4867 4876
4868 4877 struct l2info {
4869 4878 int *l2i_csz;
4870 4879 int *l2i_lsz;
4871 4880 int *l2i_assoc;
4872 4881 int l2i_ret;
4873 4882 };
4874 4883
4875 4884 /*
4876 4885 * A cacheinfo walker that fetches the size, line-size and associativity
4877 4886 * of the L2 cache
4878 4887 */
4879 4888 static int
4880 4889 intel_l2cinfo(void *arg, const struct cachetab *ct)
4881 4890 {
4882 4891 struct l2info *l2i = arg;
4883 4892 int *ip;
4884 4893
4885 4894 if (ct->ct_label != l2_cache_str &&
4886 4895 ct->ct_label != sl2_cache_str)
4887 4896 return (0); /* not an L2 -- keep walking */
4888 4897
4889 4898 if ((ip = l2i->l2i_csz) != NULL)
4890 4899 *ip = ct->ct_size;
4891 4900 if ((ip = l2i->l2i_lsz) != NULL)
4892 4901 *ip = ct->ct_line_size;
4893 4902 if ((ip = l2i->l2i_assoc) != NULL)
4894 4903 *ip = ct->ct_assoc;
4895 4904 l2i->l2i_ret = ct->ct_size;
4896 4905 return (1); /* was an L2 -- terminate walk */
4897 4906 }
4898 4907
4899 4908 /*
4900 4909 * AMD L2/L3 Cache and TLB Associativity Field Definition:
4901 4910 *
4902 4911 * Unlike the associativity for the L1 cache and tlb where the 8 bit
4903 4912 * value is the associativity, the associativity for the L2 cache and
4904 4913 * tlb is encoded in the following table. The 4 bit L2 value serves as
4905 4914 * an index into the amd_afd[] array to determine the associativity.
4906 4915 * -1 is undefined. 0 is fully associative.
4907 4916 */
4908 4917
4909 4918 static int amd_afd[] =
4910 4919 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0};
4911 4920
4912 4921 static void
4913 4922 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i)
4914 4923 {
4915 4924 struct cpuid_regs *cp;
4916 4925 uint_t size, assoc;
4917 4926 int i;
4918 4927 int *ip;
4919 4928
4920 4929 if (cpi->cpi_xmaxeax < 0x80000006)
4921 4930 return;
4922 4931 cp = &cpi->cpi_extd[6];
4923 4932
4924 4933 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 &&
4925 4934 (size = BITX(cp->cp_ecx, 31, 16)) != 0) {
4926 4935 uint_t cachesz = size * 1024;
4927 4936 assoc = amd_afd[i];
4928 4937
4929 4938 ASSERT(assoc != -1);
4930 4939
4931 4940 if ((ip = l2i->l2i_csz) != NULL)
4932 4941 *ip = cachesz;
4933 4942 if ((ip = l2i->l2i_lsz) != NULL)
4934 4943 *ip = BITX(cp->cp_ecx, 7, 0);
4935 4944 if ((ip = l2i->l2i_assoc) != NULL)
4936 4945 *ip = assoc;
4937 4946 l2i->l2i_ret = cachesz;
4938 4947 }
4939 4948 }
4940 4949
4941 4950 int
4942 4951 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc)
4943 4952 {
4944 4953 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
4945 4954 struct l2info __l2info, *l2i = &__l2info;
4946 4955
4947 4956 l2i->l2i_csz = csz;
4948 4957 l2i->l2i_lsz = lsz;
4949 4958 l2i->l2i_assoc = assoc;
4950 4959 l2i->l2i_ret = -1;
4951 4960
4952 4961 switch (x86_which_cacheinfo(cpi)) {
4953 4962 case X86_VENDOR_Intel:
4954 4963 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
4955 4964 break;
4956 4965 case X86_VENDOR_Cyrix:
4957 4966 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
4958 4967 break;
4959 4968 case X86_VENDOR_AMD:
4960 4969 amd_l2cacheinfo(cpi, l2i);
4961 4970 break;
4962 4971 default:
4963 4972 break;
4964 4973 }
4965 4974 return (l2i->l2i_ret);
4966 4975 }
4967 4976
4968 4977 #if !defined(__xpv)
4969 4978
4970 4979 uint32_t *
4971 4980 cpuid_mwait_alloc(cpu_t *cpu)
4972 4981 {
4973 4982 uint32_t *ret;
4974 4983 size_t mwait_size;
4975 4984
4976 4985 ASSERT(cpuid_checkpass(CPU, 2));
4977 4986
4978 4987 mwait_size = CPU->cpu_m.mcpu_cpi->cpi_mwait.mon_max;
4979 4988 if (mwait_size == 0)
4980 4989 return (NULL);
4981 4990
4982 4991 /*
4983 4992 * kmem_alloc() returns cache line size aligned data for mwait_size
4984 4993 * allocations. mwait_size is currently cache line sized. Neither
4985 4994 * of these implementation details are guarantied to be true in the
4986 4995 * future.
4987 4996 *
4988 4997 * First try allocating mwait_size as kmem_alloc() currently returns
4989 4998 * correctly aligned memory. If kmem_alloc() does not return
4990 4999 * mwait_size aligned memory, then use mwait_size ROUNDUP.
4991 5000 *
4992 5001 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we
4993 5002 * decide to free this memory.
4994 5003 */
4995 5004 ret = kmem_zalloc(mwait_size, KM_SLEEP);
4996 5005 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) {
4997 5006 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret;
4998 5007 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size;
4999 5008 *ret = MWAIT_RUNNING;
5000 5009 return (ret);
5001 5010 } else {
5002 5011 kmem_free(ret, mwait_size);
5003 5012 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP);
5004 5013 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret;
5005 5014 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2;
5006 5015 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size);
5007 5016 *ret = MWAIT_RUNNING;
5008 5017 return (ret);
5009 5018 }
5010 5019 }
5011 5020
5012 5021 void
5013 5022 cpuid_mwait_free(cpu_t *cpu)
5014 5023 {
5015 5024 if (cpu->cpu_m.mcpu_cpi == NULL) {
5016 5025 return;
5017 5026 }
5018 5027
5019 5028 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL &&
5020 5029 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) {
5021 5030 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual,
5022 5031 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual);
5023 5032 }
5024 5033
5025 5034 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL;
5026 5035 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0;
5027 5036 }
5028 5037
5029 5038 void
5030 5039 patch_tsc_read(int flag)
5031 5040 {
5032 5041 size_t cnt;
5033 5042
5034 5043 switch (flag) {
5035 5044 case TSC_NONE:
5036 5045 cnt = &_no_rdtsc_end - &_no_rdtsc_start;
5037 5046 (void) memcpy((void *)tsc_read, (void *)&_no_rdtsc_start, cnt);
5038 5047 break;
5039 5048 case TSC_RDTSC_MFENCE:
5040 5049 cnt = &_tsc_mfence_end - &_tsc_mfence_start;
5041 5050 (void) memcpy((void *)tsc_read,
5042 5051 (void *)&_tsc_mfence_start, cnt);
5043 5052 break;
5044 5053 case TSC_RDTSC_LFENCE:
5045 5054 cnt = &_tsc_lfence_end - &_tsc_lfence_start;
5046 5055 (void) memcpy((void *)tsc_read,
5047 5056 (void *)&_tsc_lfence_start, cnt);
5048 5057 break;
5049 5058 case TSC_TSCP:
5050 5059 cnt = &_tscp_end - &_tscp_start;
5051 5060 (void) memcpy((void *)tsc_read, (void *)&_tscp_start, cnt);
5052 5061 break;
5053 5062 default:
5054 5063 /* Bail for unexpected TSC types. (TSC_NONE covers 0) */
5055 5064 cmn_err(CE_PANIC, "Unrecogized TSC type: %d", flag);
5056 5065 break;
5057 5066 }
5058 5067 tsc_type = flag;
5059 5068 }
5060 5069
5061 5070 int
5062 5071 cpuid_deep_cstates_supported(void)
5063 5072 {
5064 5073 struct cpuid_info *cpi;
5065 5074 struct cpuid_regs regs;
5066 5075
5067 5076 ASSERT(cpuid_checkpass(CPU, 1));
5068 5077
5069 5078 cpi = CPU->cpu_m.mcpu_cpi;
5070 5079
5071 5080 if (!is_x86_feature(x86_featureset, X86FSET_CPUID))
5072 5081 return (0);
5073 5082
5074 5083 switch (cpi->cpi_vendor) {
5075 5084 case X86_VENDOR_Intel:
5076 5085 if (cpi->cpi_xmaxeax < 0x80000007)
5077 5086 return (0);
5078 5087
5079 5088 /*
5080 5089 * TSC run at a constant rate in all ACPI C-states?
5081 5090 */
5082 5091 regs.cp_eax = 0x80000007;
5083 5092 (void) __cpuid_insn(®s);
5084 5093 return (regs.cp_edx & CPUID_TSC_CSTATE_INVARIANCE);
5085 5094
5086 5095 default:
5087 5096 return (0);
5088 5097 }
5089 5098 }
5090 5099
5091 5100 #endif /* !__xpv */
5092 5101
5093 5102 void
5094 5103 post_startup_cpu_fixups(void)
5095 5104 {
5096 5105 #ifndef __xpv
5097 5106 /*
5098 5107 * Some AMD processors support C1E state. Entering this state will
5099 5108 * cause the local APIC timer to stop, which we can't deal with at
5100 5109 * this time.
5101 5110 */
5102 5111 if (cpuid_getvendor(CPU) == X86_VENDOR_AMD) {
5103 5112 on_trap_data_t otd;
5104 5113 uint64_t reg;
5105 5114
5106 5115 if (!on_trap(&otd, OT_DATA_ACCESS)) {
5107 5116 reg = rdmsr(MSR_AMD_INT_PENDING_CMP_HALT);
5108 5117 /* Disable C1E state if it is enabled by BIOS */
5109 5118 if ((reg >> AMD_ACTONCMPHALT_SHIFT) &
5110 5119 AMD_ACTONCMPHALT_MASK) {
5111 5120 reg &= ~(AMD_ACTONCMPHALT_MASK <<
5112 5121 AMD_ACTONCMPHALT_SHIFT);
5113 5122 wrmsr(MSR_AMD_INT_PENDING_CMP_HALT, reg);
5114 5123 }
5115 5124 }
5116 5125 no_trap();
5117 5126 }
5118 5127 #endif /* !__xpv */
5119 5128 }
5120 5129
5121 5130 void
5122 5131 enable_pcid(void)
5123 5132 {
5124 5133 if (x86_use_pcid == -1)
5125 5134 x86_use_pcid = is_x86_feature(x86_featureset, X86FSET_PCID);
5126 5135
5127 5136 if (x86_use_invpcid == -1) {
5128 5137 x86_use_invpcid = is_x86_feature(x86_featureset,
5129 5138 X86FSET_INVPCID);
5130 5139 }
5131 5140
5132 5141 if (!x86_use_pcid)
5133 5142 return;
5134 5143
5135 5144 /*
5136 5145 * Intel say that on setting PCIDE, it immediately starts using the PCID
5137 5146 * bits; better make sure there's nothing there.
5138 5147 */
5139 5148 ASSERT((getcr3() & MMU_PAGEOFFSET) == PCID_NONE);
5140 5149
5141 5150 setcr4(getcr4() | CR4_PCIDE);
5142 5151 }
5143 5152
5144 5153 /*
5145 5154 * Setup necessary registers to enable XSAVE feature on this processor.
5146 5155 * This function needs to be called early enough, so that no xsave/xrstor
5147 5156 * ops will execute on the processor before the MSRs are properly set up.
5148 5157 *
5149 5158 * Current implementation has the following assumption:
5150 5159 * - cpuid_pass1() is done, so that X86 features are known.
5151 5160 * - fpu_probe() is done, so that fp_save_mech is chosen.
5152 5161 */
5153 5162 void
5154 5163 xsave_setup_msr(cpu_t *cpu)
5155 5164 {
5156 5165 ASSERT(fp_save_mech == FP_XSAVE);
5157 5166 ASSERT(is_x86_feature(x86_featureset, X86FSET_XSAVE));
5158 5167
5159 5168 /* Enable OSXSAVE in CR4. */
5160 5169 setcr4(getcr4() | CR4_OSXSAVE);
5161 5170 /*
5162 5171 * Update SW copy of ECX, so that /dev/cpu/self/cpuid will report
5163 5172 * correct value.
5164 5173 */
5165 5174 cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_ecx |= CPUID_INTC_ECX_OSXSAVE;
5166 5175 setup_xfem();
5167 5176 }
5168 5177
5169 5178 /*
5170 5179 * Starting with the Westmere processor the local
5171 5180 * APIC timer will continue running in all C-states,
5172 5181 * including the deepest C-states.
5173 5182 */
5174 5183 int
5175 5184 cpuid_arat_supported(void)
5176 5185 {
5177 5186 struct cpuid_info *cpi;
5178 5187 struct cpuid_regs regs;
5179 5188
5180 5189 ASSERT(cpuid_checkpass(CPU, 1));
5181 5190 ASSERT(is_x86_feature(x86_featureset, X86FSET_CPUID));
5182 5191
5183 5192 cpi = CPU->cpu_m.mcpu_cpi;
5184 5193
5185 5194 switch (cpi->cpi_vendor) {
5186 5195 case X86_VENDOR_Intel:
5187 5196 /*
5188 5197 * Always-running Local APIC Timer is
5189 5198 * indicated by CPUID.6.EAX[2].
5190 5199 */
5191 5200 if (cpi->cpi_maxeax >= 6) {
5192 5201 regs.cp_eax = 6;
5193 5202 (void) cpuid_insn(NULL, ®s);
5194 5203 return (regs.cp_eax & CPUID_CSTATE_ARAT);
5195 5204 } else {
5196 5205 return (0);
5197 5206 }
5198 5207 default:
5199 5208 return (0);
5200 5209 }
5201 5210 }
5202 5211
5203 5212 /*
5204 5213 * Check support for Intel ENERGY_PERF_BIAS feature
5205 5214 */
5206 5215 int
5207 5216 cpuid_iepb_supported(struct cpu *cp)
5208 5217 {
5209 5218 struct cpuid_info *cpi = cp->cpu_m.mcpu_cpi;
5210 5219 struct cpuid_regs regs;
5211 5220
5212 5221 ASSERT(cpuid_checkpass(cp, 1));
5213 5222
5214 5223 if (!(is_x86_feature(x86_featureset, X86FSET_CPUID)) ||
5215 5224 !(is_x86_feature(x86_featureset, X86FSET_MSR))) {
5216 5225 return (0);
5217 5226 }
5218 5227
5219 5228 /*
5220 5229 * Intel ENERGY_PERF_BIAS MSR is indicated by
5221 5230 * capability bit CPUID.6.ECX.3
5222 5231 */
5223 5232 if ((cpi->cpi_vendor != X86_VENDOR_Intel) || (cpi->cpi_maxeax < 6))
5224 5233 return (0);
5225 5234
5226 5235 regs.cp_eax = 0x6;
5227 5236 (void) cpuid_insn(NULL, ®s);
5228 5237 return (regs.cp_ecx & CPUID_EPB_SUPPORT);
5229 5238 }
5230 5239
5231 5240 /*
5232 5241 * Check support for TSC deadline timer
5233 5242 *
5234 5243 * TSC deadline timer provides a superior software programming
5235 5244 * model over local APIC timer that eliminates "time drifts".
5236 5245 * Instead of specifying a relative time, software specifies an
5237 5246 * absolute time as the target at which the processor should
5238 5247 * generate a timer event.
5239 5248 */
5240 5249 int
5241 5250 cpuid_deadline_tsc_supported(void)
5242 5251 {
5243 5252 struct cpuid_info *cpi = CPU->cpu_m.mcpu_cpi;
5244 5253 struct cpuid_regs regs;
5245 5254
5246 5255 ASSERT(cpuid_checkpass(CPU, 1));
5247 5256 ASSERT(is_x86_feature(x86_featureset, X86FSET_CPUID));
5248 5257
5249 5258 switch (cpi->cpi_vendor) {
5250 5259 case X86_VENDOR_Intel:
5251 5260 if (cpi->cpi_maxeax >= 1) {
5252 5261 regs.cp_eax = 1;
5253 5262 (void) cpuid_insn(NULL, ®s);
5254 5263 return (regs.cp_ecx & CPUID_DEADLINE_TSC);
5255 5264 } else {
5256 5265 return (0);
5257 5266 }
5258 5267 default:
5259 5268 return (0);
5260 5269 }
5261 5270 }
5262 5271
5263 5272 #if defined(__amd64) && !defined(__xpv)
5264 5273 /*
5265 5274 * Patch in versions of bcopy for high performance Intel Nhm processors
5266 5275 * and later...
5267 5276 */
5268 5277 void
5269 5278 patch_memops(uint_t vendor)
5270 5279 {
5271 5280 size_t cnt, i;
5272 5281 caddr_t to, from;
5273 5282
5274 5283 if ((vendor == X86_VENDOR_Intel) &&
5275 5284 is_x86_feature(x86_featureset, X86FSET_SSE4_2)) {
5276 5285 cnt = &bcopy_patch_end - &bcopy_patch_start;
5277 5286 to = &bcopy_ck_size;
5278 5287 from = &bcopy_patch_start;
5279 5288 for (i = 0; i < cnt; i++) {
5280 5289 *to++ = *from++;
5281 5290 }
5282 5291 }
5283 5292 }
5284 5293 #endif /* __amd64 && !__xpv */
5285 5294
5286 5295 /*
5287 5296 * This function finds the number of bits to represent the number of cores per
5288 5297 * chip and the number of strands per core for the Intel platforms.
5289 5298 * It re-uses the x2APIC cpuid code of the cpuid_pass2().
5290 5299 */
5291 5300 void
5292 5301 cpuid_get_ext_topo(uint_t vendor, uint_t *core_nbits, uint_t *strand_nbits)
5293 5302 {
5294 5303 struct cpuid_regs regs;
5295 5304 struct cpuid_regs *cp = ®s;
5296 5305
5297 5306 if (vendor != X86_VENDOR_Intel) {
5298 5307 return;
5299 5308 }
5300 5309
5301 5310 /* if the cpuid level is 0xB, extended topo is available. */
5302 5311 cp->cp_eax = 0;
5303 5312 if (__cpuid_insn(cp) >= 0xB) {
5304 5313
5305 5314 cp->cp_eax = 0xB;
5306 5315 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0;
5307 5316 (void) __cpuid_insn(cp);
5308 5317
5309 5318 /*
5310 5319 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which
5311 5320 * indicates that the extended topology enumeration leaf is
5312 5321 * available.
5313 5322 */
5314 5323 if (cp->cp_ebx) {
5315 5324 uint_t coreid_shift = 0;
5316 5325 uint_t chipid_shift = 0;
5317 5326 uint_t i;
5318 5327 uint_t level;
5319 5328
5320 5329 for (i = 0; i < CPI_FNB_ECX_MAX; i++) {
5321 5330 cp->cp_eax = 0xB;
5322 5331 cp->cp_ecx = i;
5323 5332
5324 5333 (void) __cpuid_insn(cp);
5325 5334 level = CPI_CPU_LEVEL_TYPE(cp);
5326 5335
5327 5336 if (level == 1) {
5328 5337 /*
5329 5338 * Thread level processor topology
5330 5339 * Number of bits shift right APIC ID
5331 5340 * to get the coreid.
5332 5341 */
5333 5342 coreid_shift = BITX(cp->cp_eax, 4, 0);
5334 5343 } else if (level == 2) {
5335 5344 /*
5336 5345 * Core level processor topology
5337 5346 * Number of bits shift right APIC ID
5338 5347 * to get the chipid.
5339 5348 */
5340 5349 chipid_shift = BITX(cp->cp_eax, 4, 0);
5341 5350 }
5342 5351 }
5343 5352
5344 5353 if (coreid_shift > 0 && chipid_shift > coreid_shift) {
5345 5354 *strand_nbits = coreid_shift;
5346 5355 *core_nbits = chipid_shift - coreid_shift;
5347 5356 }
5348 5357 }
5349 5358 }
5350 5359 }
5351 5360
5352 5361 void
5353 5362 cpuid_pass_ucode(cpu_t *cpu, uchar_t *fset)
5354 5363 {
5355 5364 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
5356 5365 struct cpuid_regs cp;
5357 5366
5358 5367 /*
5359 5368 * Reread the CPUID portions that we need for various security
5360 5369 * information.
5361 5370 */
5362 5371 if (cpi->cpi_vendor == X86_VENDOR_Intel) {
5363 5372 /*
5364 5373 * Check if we now have leaf 7 available to us.
5365 5374 */
5366 5375 if (cpi->cpi_maxeax < 7) {
5367 5376 bzero(&cp, sizeof (cp));
5368 5377 cp.cp_eax = 0;
5369 5378 cpi->cpi_maxeax = __cpuid_insn(&cp);
5370 5379 if (cpi->cpi_maxeax < 7)
5371 5380 return;
5372 5381 }
5373 5382
5374 5383 bzero(&cp, sizeof (cp));
5375 5384 cp.cp_eax = 7;
5376 5385 cp.cp_ecx = 0;
5377 5386 (void) __cpuid_insn(&cp);
5378 5387 cpi->cpi_std[7] = cp;
5379 5388 } else if (cpi->cpi_vendor == X86_VENDOR_AMD) {
5380 5389 /* No xcpuid support */
5381 5390 if (cpi->cpi_family < 5 ||
5382 5391 (cpi->cpi_family == 5 && cpi->cpi_model < 1))
5383 5392 return;
5384 5393
5385 5394 if (cpi->cpi_xmaxeax < 0x80000008) {
5386 5395 bzero(&cp, sizeof (cp));
5387 5396 cp.cp_eax = 0x80000000;
5388 5397 cpi->cpi_xmaxeax = __cpuid_insn(&cp);
5389 5398 if (cpi->cpi_xmaxeax < 0x80000008) {
5390 5399 return;
5391 5400 }
5392 5401 }
5393 5402
5394 5403 bzero(&cp, sizeof (cp));
5395 5404 cp.cp_eax = 0x80000008;
5396 5405 (void) __cpuid_insn(&cp);
5397 5406 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, &cp);
5398 5407 cpi->cpi_extd[8] = cp;
5399 5408 } else {
5400 5409 /*
5401 5410 * Nothing to do here. Return an empty set which has already
5402 5411 * been zeroed for us.
5403 5412 */
5404 5413 return;
5405 5414 }
5406 5415 cpuid_scan_security(cpu, fset);
5407 5416 }
5408 5417
5409 5418 /* ARGSUSED */
5410 5419 static int
5411 5420 cpuid_post_ucodeadm_xc(xc_arg_t arg0, xc_arg_t arg1, xc_arg_t arg2)
5412 5421 {
5413 5422 uchar_t *fset;
5414 5423
5415 5424 fset = (uchar_t *)(arg0 + sizeof (x86_featureset) * CPU->cpu_id);
5416 5425 cpuid_pass_ucode(CPU, fset);
5417 5426
5418 5427 return (0);
5419 5428 }
5420 5429
5421 5430 /*
5422 5431 * After a microcode update where the version has changed, then we need to
5423 5432 * rescan CPUID. To do this we check every CPU to make sure that they have the
5424 5433 * same microcode. Then we perform a cross call to all such CPUs. It's the
5425 5434 * caller's job to make sure that no one else can end up doing an update while
5426 5435 * this is going on.
5427 5436 *
5428 5437 * We assume that the system is microcode capable if we're called.
5429 5438 */
5430 5439 void
5431 5440 cpuid_post_ucodeadm(void)
5432 5441 {
5433 5442 uint32_t rev;
5434 5443 int i;
5435 5444 struct cpu *cpu;
5436 5445 cpuset_t cpuset;
5437 5446 void *argdata;
5438 5447 uchar_t *f0;
5439 5448
5440 5449 argdata = kmem_zalloc(sizeof (x86_featureset) * NCPU, KM_SLEEP);
5441 5450
5442 5451 mutex_enter(&cpu_lock);
5443 5452 cpu = cpu_get(0);
5444 5453 rev = cpu->cpu_m.mcpu_ucode_info->cui_rev;
5445 5454 CPUSET_ONLY(cpuset, 0);
5446 5455 for (i = 1; i < max_ncpus; i++) {
5447 5456 if ((cpu = cpu_get(i)) == NULL)
5448 5457 continue;
5449 5458
5450 5459 if (cpu->cpu_m.mcpu_ucode_info->cui_rev != rev) {
5451 5460 panic("post microcode update CPU %d has differing "
5452 5461 "microcode revision (%u) from CPU 0 (%u)",
5453 5462 i, cpu->cpu_m.mcpu_ucode_info->cui_rev, rev);
5454 5463 }
5455 5464 CPUSET_ADD(cpuset, i);
5456 5465 }
5457 5466
5458 5467 kpreempt_disable();
5459 5468 xc_sync((xc_arg_t)argdata, 0, 0, CPUSET2BV(cpuset),
5460 5469 cpuid_post_ucodeadm_xc);
5461 5470 kpreempt_enable();
5462 5471
5463 5472 /*
5464 5473 * OK, now look at each CPU and see if their feature sets are equal.
5465 5474 */
5466 5475 f0 = argdata;
5467 5476 for (i = 1; i < max_ncpus; i++) {
5468 5477 uchar_t *fset;
5469 5478 if (!CPU_IN_SET(cpuset, i))
5470 5479 continue;
5471 5480
5472 5481 fset = (uchar_t *)((uintptr_t)argdata +
5473 5482 sizeof (x86_featureset) * i);
5474 5483
5475 5484 if (!compare_x86_featureset(f0, fset)) {
5476 5485 panic("Post microcode update CPU %d has "
5477 5486 "differing security feature (%p) set from CPU 0 "
5478 5487 "(%p), not appending to feature set", i,
5479 5488 (void *)fset, (void *)f0);
5480 5489 }
5481 5490 }
5482 5491
5483 5492 mutex_exit(&cpu_lock);
5484 5493
5485 5494 for (i = 0; i < NUM_X86_FEATURES; i++) {
5486 5495 cmn_err(CE_CONT, "?post-ucode x86_feature: %s\n",
5487 5496 x86_feature_names[i]);
5488 5497 if (is_x86_feature(f0, i)) {
5489 5498 add_x86_feature(x86_featureset, i);
5490 5499 }
5491 5500 }
5492 5501 kmem_free(argdata, sizeof (x86_featureset) * NCPU);
5493 5502 }
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