10208 Add x86 features for L1TF

@@ -30,11 +30,11 @@
  */
 /*
  * Portions Copyright 2009 Advanced Micro Devices, Inc.
  */
 /*
- * Copyright 2018 Joyent, Inc.
+ * Copyright (c) 2019, Joyent, Inc.
  */
 /*
  * Various routines to handle identification
  * and classification of x86 processors.
  */

@@ -215,11 +215,13 @@
         "ssbd_virt",
         "rdcl_no",
         "ibrs_all",
         "rsba",
         "ssb_no",
-        "stibp_all"
+        "stibp_all",
+        "flush_cmd",
+        "l1d_vmentry_no"
 };
 
 boolean_t
 is_x86_feature(void *featureset, uint_t feature)
 {

@@ -1049,10 +1051,14 @@
                                 }
                                 if (reg & IA32_ARCH_CAP_RSBA) {
                                         add_x86_feature(featureset,
                                             X86FSET_RSBA);
                                 }
+                                if (reg & IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY) {
+                                        add_x86_feature(featureset,
+                                            X86FSET_L1D_VM_NO);
+                                }
                                 if (reg & IA32_ARCH_CAP_SSB_NO) {
                                         add_x86_feature(featureset,
                                             X86FSET_SSB_NO);
                                 }
                         }

@@ -1060,10 +1066,13 @@
                 }
 #endif  /* !__xpv */
 
                 if (ecp->cp_edx & CPUID_INTC_EDX_7_0_SSBD)
                         add_x86_feature(featureset, X86FSET_SSBD);
+
+                if (ecp->cp_edx & CPUID_INTC_EDX_7_0_FLUSH_CMD)
+                        add_x86_feature(featureset, X86FSET_FLUSH_CMD);
         }
 }
 
 /*
  * Setup XFeature_Enabled_Mask register. Required by xsave feature.