Print this page
10208 Add x86 features for L1TF
*** 30,40 ****
*/
/*
* Portions Copyright 2009 Advanced Micro Devices, Inc.
*/
/*
! * Copyright 2018 Joyent, Inc.
*/
/*
* Various routines to handle identification
* and classification of x86 processors.
*/
--- 30,40 ----
*/
/*
* Portions Copyright 2009 Advanced Micro Devices, Inc.
*/
/*
! * Copyright (c) 2019, Joyent, Inc.
*/
/*
* Various routines to handle identification
* and classification of x86 processors.
*/
*** 215,225 ****
"ssbd_virt",
"rdcl_no",
"ibrs_all",
"rsba",
"ssb_no",
! "stibp_all"
};
boolean_t
is_x86_feature(void *featureset, uint_t feature)
{
--- 215,227 ----
"ssbd_virt",
"rdcl_no",
"ibrs_all",
"rsba",
"ssb_no",
! "stibp_all",
! "flush_cmd",
! "l1d_vmentry_no"
};
boolean_t
is_x86_feature(void *featureset, uint_t feature)
{
*** 1049,1058 ****
--- 1051,1064 ----
}
if (reg & IA32_ARCH_CAP_RSBA) {
add_x86_feature(featureset,
X86FSET_RSBA);
}
+ if (reg & IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY) {
+ add_x86_feature(featureset,
+ X86FSET_L1D_VM_NO);
+ }
if (reg & IA32_ARCH_CAP_SSB_NO) {
add_x86_feature(featureset,
X86FSET_SSB_NO);
}
}
*** 1060,1069 ****
--- 1066,1078 ----
}
#endif /* !__xpv */
if (ecp->cp_edx & CPUID_INTC_EDX_7_0_SSBD)
add_x86_feature(featureset, X86FSET_SSBD);
+
+ if (ecp->cp_edx & CPUID_INTC_EDX_7_0_FLUSH_CMD)
+ add_x86_feature(featureset, X86FSET_FLUSH_CMD);
}
}
/*
* Setup XFeature_Enabled_Mask register. Required by xsave feature.