1 Why hacking on sparse 2 ===================== 3 4 1. sparse is small. 5 The full project compiles in less than 10 seconds on old and not performing laptop. 6 2. sparse is fast. 7 Typically, sparse can check a C file 1/10 of time it takes for gcc to generate object files. 8 3. sparse can digest the full kernel source files. 9 With sparse-llvm, sparse uses llvm as back end to emit real machine code. 10 11 New developer hacking on sparse 12 ============================== 13 14 15 * All sparse warning messages should include the option how 16 to disable it. 17 e.g. "pre-process.c:20*:28: warning: Variable length array is used." 18 should be something like 19 "pre-process.c:20*:28: warning: Variable length array is 20 used. (-Wno-vla)" 21 * extend test-inspect to inspect more AST fields. 22 * extend test-inspect to inspect instructions. 23 * adding architecture handling in sparse similar to cgcc 24 * parallel processing of test-suite 25 * Howto: fix the kernel rcu related checker warnings 26 * option to disable AST level inline. 27 * debug: debug version of sparse do all the verification double check 28 * test suite: verify and compare IR (suggested by Dibyendu Majumdar) 29 * checker error output database 30 31 For experienced developers 32 ========================== 33 34 * merge C type on incremental declare of C type and function prototype. 35 * move attribute out of ctype to allow easier to add new attribute. 36 * serialize, general object walking driven by data structures. 37 * serialize, write sparse byte code into file 38 * serialize, load sparse byte code from file. 39 * symbol index/linker, know which symbol in which byte code file. 40 * inline function in instruction level 41 * cross function checking 42 * debug: optimization step by step log 43 * debug: fancy animation of CFG 44 * phi node location (Luc has patch) 45 * revisit crazy programmer warning, invalid SSA form. 46 * ptrlist, looping while modify inside the loop. 47 * dead code elimination using ssa 48 * constant propagation using ssa. 49 * x86/arm back end instruction set define 50 * register allocation. 51 * emit x86/arm machine level code 52