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8902 Panic with debug kernel on AMD Ryzen hardware
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--- old/usr/src/uts/i86pc/io/amd_iommu/amd_iommu_acpi.h
+++ new/usr/src/uts/i86pc/io/amd_iommu/amd_iommu_acpi.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
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12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 + * Copyright 2017 Gary Mills
22 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
23 24 */
24 25
25 26 #ifndef _AMD_IOMMU_ACPI_H
26 27 #define _AMD_IOMMU_ACPI_H
27 28
28 29 #ifdef __cplusplus
29 30 extern "C" {
30 31 #endif
31 32
32 33 #include <sys/sunddi.h>
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33 34 #include <sys/acpi/acpi.h>
34 35 #include <sys/acpica.h>
35 36 #include <sys/amd_iommu.h>
36 37 #include "amd_iommu_impl.h"
37 38
38 39 #ifdef _KERNEL
39 40
40 41 #define IVRS_SIG "IVRS"
41 42
42 43 /*
43 - * IVINFO settings
44 + * IVINFO bit fields
45 + * Documented at: http://support.amd.com/TechDocs/48882_IOMMU.pdf
44 46 */
45 47 #define AMD_IOMMU_ACPI_IVINFO_RSV1 (31 << 16 | 23)
46 48 #define AMD_IOMMU_ACPI_HT_ATSRSV (22 << 16 | 22)
47 49 #define AMD_IOMMU_ACPI_VA_SIZE (21 << 16 | 15)
48 50 #define AMD_IOMMU_ACPI_PA_SIZE (14 << 16 | 8)
49 -#define AMD_IOMMU_ACPI_IVINFO_RSV2 (7 << 16 | 0)
51 +#define AMD_IOMMU_ACPI_GVA_SIZE (7 << 16 | 5)
52 +#define AMD_IOMMU_ACPI_IVINFO_RSV2 (4 << 16 | 1)
53 +#define AMD_IOMMU_ACPI_IVINFO_EFRSUP (0 << 16 | 0)
50 54
51 55 /*
52 56 * IVHD Device entry len field
53 57 */
54 58 #define AMD_IOMMU_ACPI_DEVENTRY_LEN (7 << 16 | 6)
55 59
56 60 /*
57 61 * IVHD flag fields definition
58 62 */
59 63 #define AMD_IOMMU_ACPI_IVHD_FLAGS_RSV (7 << 16 | 5)
60 64 #define AMD_IOMMU_ACPI_IVHD_FLAGS_IOTLBSUP (4 << 16 | 4)
61 65 #define AMD_IOMMU_ACPI_IVHD_FLAGS_ISOC (3 << 16 | 3)
62 66 #define AMD_IOMMU_ACPI_IVHD_FLAGS_RESPASSPW (2 << 16 | 2)
63 67 #define AMD_IOMMU_ACPI_IVHD_FLAGS_PASSPW (1 << 16 | 1)
64 68 #define AMD_IOMMU_ACPI_IVHD_FLAGS_HTTUNEN (0 << 16 | 0)
65 69
66 70 /*
67 71 * IVHD IOMMU info fields
68 72 */
69 73 #define AMD_IOMMU_ACPI_IOMMU_INFO_RSV1 (15 << 16 | 13)
70 74 #define AMD_IOMMU_ACPI_IOMMU_INFO_UNITID (12 << 16 | 8)
71 75 #define AMD_IOMMU_ACPI_IOMMU_INFO_RSV2 (7 << 16 | 5)
72 76 #define AMD_IOMMU_ACPI_IOMMU_INFO_MSINUM (4 << 16 | 0)
73 77
74 78 /*
75 79 * IVHD deventry data settings
76 80 */
77 81 #define AMD_IOMMU_ACPI_LINT1PASS (7 << 16 | 7)
78 82 #define AMD_IOMMU_ACPI_LINT0PASS (6 << 16 | 6)
79 83 #define AMD_IOMMU_ACPI_SYSMGT (5 << 16 | 4)
80 84 #define AMD_IOMMU_ACPI_DATRSV (3 << 16 | 3)
81 85 #define AMD_IOMMU_ACPI_NMIPASS (2 << 16 | 2)
82 86 #define AMD_IOMMU_ACPI_EXTINTPASS (1 << 16 | 1)
83 87 #define AMD_IOMMU_ACPI_INITPASS (0 << 16 | 0)
84 88
85 89 /*
86 90 * IVHD deventry extended data settings
87 91 */
88 92 #define AMD_IOMMU_ACPI_ATSDISABLED (31 << 16 | 31)
89 93 #define AMD_IOMMU_ACPI_EXTDATRSV (30 << 16 | 0)
90 94
91 95 /*
92 96 * IVMD flags fields settings
93 97 */
94 98 #define AMD_IOMMU_ACPI_IVMD_RSV (7 << 16 | 4)
95 99 #define AMD_IOMMU_ACPI_IVMD_EXCL_RANGE (3 << 16 | 3)
96 100 #define AMD_IOMMU_ACPI_IVMD_IW (2 << 16 | 2)
97 101 #define AMD_IOMMU_ACPI_IVMD_IR (1 << 16 | 1)
98 102 #define AMD_IOMMU_ACPI_IVMD_UNITY (0 << 16 | 0)
99 103
100 104 #define AMD_IOMMU_ACPI_INFO_HASH_SZ (256)
101 105
102 106 /*
103 107 * Deventry special device "variety"
104 108 */
105 109 #define AMD_IOMMU_ACPI_SPECIAL_APIC 0x1
106 110 #define AMD_IOMMU_ACPI_SPECIAL_HPET 0x2
107 111
108 112 typedef enum {
109 113 DEVENTRY_INVALID = 0,
110 114 DEVENTRY_ALL = 1,
111 115 DEVENTRY_SELECT,
112 116 DEVENTRY_RANGE,
113 117 DEVENTRY_RANGE_END,
114 118 DEVENTRY_ALIAS_SELECT,
115 119 DEVENTRY_ALIAS_RANGE,
116 120 DEVENTRY_EXTENDED_SELECT,
117 121 DEVENTRY_EXTENDED_RANGE,
118 122 DEVENTRY_SPECIAL_DEVICE
119 123 } ivhd_deventry_type_t;
120 124
121 125 typedef enum {
122 126 IVMD_DEVICE_INVALID = 0,
123 127 IVMD_DEVICEID_ALL,
124 128 IVMD_DEVICEID_SELECT,
125 129 IVMD_DEVICEID_RANGE
126 130 } ivmd_deviceid_type_t;
127 131
128 132 typedef struct ivhd_deventry {
129 133 uint8_t idev_len;
130 134 ivhd_deventry_type_t idev_type;
131 135 int32_t idev_deviceid;
132 136 int32_t idev_src_deviceid;
133 137 uint8_t idev_handle;
134 138 uint8_t idev_variety;
135 139 uint8_t idev_Lint1Pass;
136 140 uint8_t idev_Lint0Pass;
137 141 uint8_t idev_SysMgt;
138 142 uint8_t idev_NMIPass;
139 143 uint8_t idev_ExtIntPass;
140 144 uint8_t idev_INITPass;
141 145 uint8_t idev_AtsDisabled;
142 146 struct ivhd_deventry *idev_next;
143 147 } ivhd_deventry_t;
144 148
145 149 typedef struct ivhd {
146 150 uint8_t ivhd_type;
147 151 uint8_t ivhd_flags;
148 152 uint16_t ivhd_len;
149 153 uint16_t ivhd_deviceid;
150 154 uint16_t ivhd_cap_off;
151 155 uint64_t ivhd_reg_base;
152 156 uint16_t ivhd_pci_seg;
153 157 uint16_t ivhd_iommu_info;
154 158 uint32_t ivhd_resv;
155 159 } ivhd_t;
156 160
157 161 typedef struct ivhd_container {
158 162 ivhd_t *ivhdc_ivhd;
159 163 ivhd_deventry_t *ivhdc_first_deventry;
160 164 ivhd_deventry_t *ivhdc_last_deventry;
161 165 struct ivhd_container *ivhdc_next;
162 166 } ivhd_container_t;
163 167
164 168 typedef struct ivmd {
165 169 uint8_t ivmd_type;
166 170 uint8_t ivmd_flags;
167 171 uint16_t ivmd_len;
168 172 uint16_t ivmd_deviceid;
169 173 uint16_t ivmd_auxdata;
170 174 uint64_t ivmd_resv;
171 175 uint64_t ivmd_phys_start;
172 176 uint64_t ivmd_phys_len;
173 177 } ivmd_t;
174 178
175 179 typedef struct ivmd_container {
176 180 ivmd_t *ivmdc_ivmd;
177 181 struct ivmd_container *ivmdc_next;
178 182 } ivmd_container_t;
179 183
180 184 typedef struct ivrs {
181 185 struct acpi_table_header ivrs_hdr;
182 186 uint32_t ivrs_ivinfo;
183 187 uint64_t ivrs_resv;
184 188 } ivrs_t;
185 189
186 190 typedef struct amd_iommu_acpi {
187 191 struct ivrs *acp_ivrs;
188 192 ivhd_container_t *acp_first_ivhdc;
189 193 ivhd_container_t *acp_last_ivhdc;
190 194 ivmd_container_t *acp_first_ivmdc;
191 195 ivmd_container_t *acp_last_ivmdc;
192 196 } amd_iommu_acpi_t;
193 197
194 198
195 199 /* Global IVINFo fields */
196 200 typedef struct amd_iommu_acpi_global {
197 201 uint8_t acg_HtAtsResv;
198 202 uint8_t acg_VAsize;
199 203 uint8_t acg_PAsize;
200 204 } amd_iommu_acpi_global_t;
201 205
202 206 typedef struct amd_iommu_acpi_ivhd {
203 207 int32_t ach_deviceid_start;
204 208 int32_t ach_deviceid_end;
205 209
206 210 /* IVHD deventry type */
207 211 ivhd_deventry_type_t ach_dev_type;
208 212
209 213 /* IVHD flag fields */
210 214 uint8_t ach_IotlbSup;
211 215 uint8_t ach_Isoc;
212 216 uint8_t ach_ResPassPW;
213 217 uint8_t ach_PassPW;
214 218 uint8_t ach_HtTunEn;
215 219
216 220 /* IVHD fields */
217 221 uint16_t ach_IOMMU_deviceid;
218 222 uint16_t ach_IOMMU_cap_off;
219 223 uint64_t ach_IOMMU_reg_base;
220 224 uint16_t ach_IOMMU_pci_seg;
221 225
222 226 /* IVHD IOMMU info fields */
223 227 uint8_t ach_IOMMU_UnitID;
224 228 uint8_t ach_IOMMU_MSInum;
225 229
226 230 /* IVHD deventry data settings */
227 231 uint8_t ach_Lint1Pass;
228 232 uint8_t ach_Lint0Pass;
229 233 uint8_t ach_SysMgt;
230 234 uint8_t ach_NMIPass;
231 235 uint8_t ach_ExtIntPass;
232 236 uint8_t ach_INITPass;
233 237
234 238 /* alias */
235 239 int32_t ach_src_deviceid;
236 240
237 241 /* IVHD deventry extended data settings */
238 242 uint8_t ach_AtsDisabled;
239 243
240 244 /* IVHD deventry special device */
241 245 uint8_t ach_special_handle;
242 246 uint8_t ach_special_variety;
243 247
244 248 struct amd_iommu_acpi_ivhd *ach_next;
245 249 } amd_iommu_acpi_ivhd_t;
246 250
247 251 typedef struct amd_iommu_acpi_ivmd {
248 252 int32_t acm_deviceid_start;
249 253 int32_t acm_deviceid_end;
250 254
251 255 /* IVMD type */
252 256 ivmd_deviceid_type_t acm_dev_type;
253 257
254 258 /* IVMD flags */
255 259 uint8_t acm_ExclRange;
256 260 uint8_t acm_IW;
257 261 uint8_t acm_IR;
258 262 uint8_t acm_Unity;
259 263
260 264 /* IVMD mem block */
261 265 uint64_t acm_ivmd_phys_start;
262 266 uint64_t acm_ivmd_phys_len;
263 267
264 268 struct amd_iommu_acpi_ivmd *acm_next;
265 269 } amd_iommu_acpi_ivmd_t;
266 270
267 271 typedef union {
268 272 uint16_t ent16;
269 273 uint8_t ent8[2];
270 274 } align_16_t;
271 275
272 276 typedef union {
273 277 uint32_t ent32;
274 278 uint8_t ent8[4];
275 279 } align_32_t;
276 280
277 281 typedef union {
278 282 ivhd_t *ivhdp;
279 283 char *cp;
280 284 } align_ivhd_t;
281 285
282 286 typedef union {
283 287 ivmd_t *ivmdp;
284 288 char *cp;
285 289 } align_ivmd_t;
286 290
287 291 #pragma pack()
288 292
289 293 int amd_iommu_acpi_init(void);
290 294 void amd_iommu_acpi_fini(void);
291 295 amd_iommu_acpi_ivhd_t *amd_iommu_lookup_all_ivhd(void);
292 296 amd_iommu_acpi_ivmd_t *amd_iommu_lookup_all_ivmd(void);
293 297 amd_iommu_acpi_ivhd_t *amd_iommu_lookup_any_ivhd(amd_iommu_t *);
294 298 amd_iommu_acpi_ivmd_t *amd_iommu_lookup_any_ivmd(void);
295 299 amd_iommu_acpi_global_t *amd_iommu_lookup_acpi_global(void);
296 300 amd_iommu_acpi_ivhd_t *amd_iommu_lookup_ivhd(int32_t deviceid);
297 301 amd_iommu_acpi_ivmd_t *amd_iommu_lookup_ivmd(int32_t deviceid);
298 302 int amd_iommu_acpi_init_devtbl(amd_iommu_t *iommu);
299 303
300 304 #endif /* _KERNEL */
301 305
302 306 #ifdef __cplusplus
303 307 }
304 308 #endif
305 309
306 310 #endif /* _AMD_IOMMU_ACPI_H */
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