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8465 aggressive-loop-optimizations error in rt2860.c
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--- old/usr/src/uts/common/io/rwn/rt2860.c
+++ new/usr/src/uts/common/io/rwn/rt2860.c
1 1 /*
2 + * Copyright 2017 Gary Mills
2 3 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
3 4 * Use is subject to license terms.
4 5 */
5 6
6 7 /*
7 8 * Copyright (c) 2007, 2008
8 9 * Damien Bergamini <damien.bergamini@free.fr>
9 10 *
10 11 * Permission to use, copy, modify, and distribute this software for any
11 12 * purpose with or without fee is hereby granted, provided that the above
12 13 * copyright notice and this permission notice appear in all copies.
13 14 *
14 15 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15 16 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
16 17 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17 18 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
18 19 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
19 20 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
20 21 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 22 */
22 23
23 24 /*
24 25 * Ralink Technology RT2860 chipset driver
25 26 * http://www.ralinktech.com/
26 27 */
27 28
28 29 #include <sys/types.h>
29 30 #include <sys/byteorder.h>
30 31 #include <sys/conf.h>
31 32 #include <sys/cmn_err.h>
32 33 #include <sys/stat.h>
33 34 #include <sys/ddi.h>
34 35 #include <sys/sunddi.h>
35 36 #include <sys/strsubr.h>
36 37 #include <inet/common.h>
37 38 #include <sys/note.h>
38 39 #include <sys/stream.h>
39 40 #include <sys/strsun.h>
40 41 #include <sys/modctl.h>
41 42 #include <sys/devops.h>
42 43 #include <sys/mac_provider.h>
43 44 #include <sys/mac_wifi.h>
44 45 #include <sys/net80211.h>
45 46 #include <sys/net80211_proto.h>
46 47 #include <sys/varargs.h>
47 48 #include <sys/pci.h>
48 49 #include <sys/crypto/common.h>
49 50 #include <sys/crypto/api.h>
50 51 #include <inet/wifi_ioctl.h>
51 52
52 53 #include "rt2860_reg.h"
53 54 #include "rt2860_var.h"
54 55
55 56 #define RT2860_DBG_80211 (1 << 0)
56 57 #define RT2860_DBG_DMA (1 << 1)
57 58 #define RT2860_DBG_EEPROM (1 << 2)
58 59 #define RT2860_DBG_FW (1 << 3)
59 60 #define RT2860_DBG_HW (1 << 4)
60 61 #define RT2860_DBG_INTR (1 << 5)
61 62 #define RT2860_DBG_RX (1 << 6)
62 63 #define RT2860_DBG_SCAN (1 << 7)
63 64 #define RT2860_DBG_TX (1 << 8)
64 65 #define RT2860_DBG_RADIO (1 << 9)
65 66 #define RT2860_DBG_RESUME (1 << 10)
66 67 #define RT2860_DBG_MSG (1 << 11)
67 68
68 69 uint32_t rt2860_dbg_flags = 0x0;
69 70
70 71 #ifdef DEBUG
71 72 #define RWN_DEBUG \
72 73 rt2860_debug
73 74 #else
74 75 #define RWN_DEBUG
75 76 #endif
76 77
77 78 static void *rt2860_soft_state_p = NULL;
78 79 static uint8_t rt2860_fw_bin [] = {
79 80 #include "fw-rt2860/rt2860.ucode"
80 81 };
81 82
82 83 static const struct ieee80211_rateset rt2860_rateset_11b =
83 84 { 4, { 2, 4, 11, 22 } };
84 85
85 86 static const struct ieee80211_rateset rt2860_rateset_11g =
86 87 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
87 88
88 89 static const struct {
89 90 uint32_t reg;
90 91 uint32_t val;
91 92 } rt2860_def_mac[] = {
92 93 RT2860_DEF_MAC
93 94 };
94 95
95 96 static const struct {
96 97 uint8_t reg;
97 98 uint8_t val;
98 99 } rt2860_def_bbp[] = {
99 100 RT2860_DEF_BBP
100 101 };
101 102
102 103 static const struct rfprog {
103 104 uint8_t chan;
104 105 uint32_t r1, r2, r3, r4;
105 106 } rt2860_rf2850[] = {
106 107 RT2860_RF2850
107 108 };
108 109
109 110 /*
110 111 * PIO access attributes for registers
111 112 */
112 113 static ddi_device_acc_attr_t rwn_csr_accattr = {
113 114 DDI_DEVICE_ATTR_V0,
114 115 DDI_STRUCTURE_LE_ACC,
115 116 DDI_STRICTORDER_ACC
116 117 };
117 118
118 119 /*
119 120 * DMA access attributes for descriptors: NOT to be byte swapped.
120 121 */
121 122 static ddi_device_acc_attr_t rt2860_desc_accattr = {
122 123 DDI_DEVICE_ATTR_V0,
123 124 DDI_STRUCTURE_LE_ACC,
124 125 DDI_STRICTORDER_ACC
125 126 };
126 127
127 128 static ddi_device_acc_attr_t rt2860_buf_accattr = {
128 129 DDI_DEVICE_ATTR_V0,
129 130 DDI_NEVERSWAP_ACC,
130 131 DDI_STRICTORDER_ACC,
131 132 DDI_DEFAULT_ACC
132 133 };
133 134
134 135 /*
135 136 * Describes the chip's DMA engine
136 137 */
137 138 static ddi_dma_attr_t rt2860_dma_attr = {
138 139 DMA_ATTR_V0, /* dma_attr version */
139 140 0x0, /* dma_attr_addr_lo */
140 141 0xffffffffU, /* dma_attr_addr_hi */
141 142 0xffffffffU, /* dma_attr_count_max */
142 143 16, /* dma_attr_align */
143 144 0x00000fff, /* dma_attr_burstsizes */
144 145 1, /* dma_attr_minxfer */
145 146 0xffffffffU, /* dma_attr_maxxfer */
146 147 0xffffffffU, /* dma_attr_seg */
147 148 1, /* dma_attr_sgllen */
148 149 1, /* dma_attr_granular */
149 150 0 /* dma_attr_flags */
150 151 };
151 152
152 153 static uint16_t rt2860_eeprom_read(struct rt2860_softc *, uint8_t);
153 154 static int rt2860_read_eeprom(struct rt2860_softc *);
154 155 const char *rt2860_get_rf(uint8_t);
155 156 static int rt2860_alloc_dma_mem(dev_info_t *, ddi_dma_attr_t *, size_t,
156 157 ddi_device_acc_attr_t *, uint_t, uint_t, struct dma_area *);
157 158 static void rt2860_free_dma_mem(struct dma_area *);
158 159 static int rt2860_alloc_tx_ring(struct rt2860_softc *,
159 160 struct rt2860_tx_ring *);
160 161 static void rt2860_free_tx_ring(struct rt2860_softc *,
161 162 struct rt2860_tx_ring *);
162 163 static int rt2860_alloc_rx_ring(struct rt2860_softc *,
163 164 struct rt2860_rx_ring *);
164 165 static void rt2860_free_rx_ring(struct rt2860_softc *,
165 166 struct rt2860_rx_ring *);
166 167 static int rt2860_alloc_tx_pool(struct rt2860_softc *);
167 168 static void rt2860_free_tx_pool(struct rt2860_softc *);
168 169 static uint16_t rt2860_txtime(int, int, uint32_t);
169 170 static int rt2860_ack_rate(struct ieee80211com *, int);
170 171 static int rt2860_send(ieee80211com_t *, mblk_t *, uint8_t);
171 172 static uint8_t rt2860_maxrssi_chain(struct rt2860_softc *,
172 173 const struct rt2860_rxwi *);
173 174 static void rt2860_drain_stats_fifo(struct rt2860_softc *);
174 175 static void rt2860_tx_intr(struct rt2860_softc *, int);
175 176 static void rt2860_rx_intr(struct rt2860_softc *);
176 177 static uint_t rt2860_softintr(caddr_t);
177 178 static uint_t rt2860_intr(caddr_t);
178 179 static void rt2860_set_region_4(struct rt2860_softc *,
179 180 uint32_t, uint32_t, int);
180 181 static int rt2860_load_microcode(struct rt2860_softc *);
181 182 static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *);
182 183 static int rt2860_bbp_init(struct rt2860_softc *);
183 184 static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t);
184 185 static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t);
185 186 static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t);
186 187 static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t);
187 188 static void rt2860_select_chan_group(struct rt2860_softc *, int);
188 189 static void rt2860_set_chan(struct rt2860_softc *,
189 190 struct ieee80211_channel *);
190 191 static void rt2860_updateprot(struct ieee80211com *);
191 192 static void rt2860_set_leds(struct rt2860_softc *, uint16_t);
192 193 static void rt2860_next_scan(void *);
193 194 static void rt2860_iter_func(void *, struct ieee80211_node *);
194 195 static void rt2860_updateslot(struct rt2860_softc *);
195 196 static uint8_t rt2860_rate2mcs(uint8_t);
196 197 static void rt2860_enable_mrr(struct rt2860_softc *);
197 198 static void rt2860_set_txpreamble(struct rt2860_softc *);
198 199 static void rt2860_set_basicrates(struct rt2860_softc *);
199 200 static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *);
200 201 static void rt2860_amrr_node_init(const struct rt2860_amrr *,
201 202 struct rt2860_amrr_node *);
202 203 static void rt2860_amrr_choose(struct rt2860_amrr *,
203 204 struct ieee80211_node *, struct rt2860_amrr_node *);
204 205 static void rt2860_newassoc(struct ieee80211com *, struct ieee80211_node *,
205 206 int);
206 207 static void rt2860_enable_tsf_sync(struct rt2860_softc *);
207 208 static int rt2860_newstate(struct ieee80211com *,
208 209 enum ieee80211_state, int);
209 210 static int rt2860_init(struct rt2860_softc *);
210 211 static void rt2860_stop(struct rt2860_softc *);
211 212 static int rt2860_quiesce(dev_info_t *t);
212 213
213 214 /*
214 215 * device operations
215 216 */
216 217 static int rt2860_attach(dev_info_t *, ddi_attach_cmd_t);
217 218 static int rt2860_detach(dev_info_t *, ddi_detach_cmd_t);
218 219
219 220 /*
220 221 * Module Loading Data & Entry Points
221 222 */
222 223 DDI_DEFINE_STREAM_OPS(rwn_dev_ops, nulldev, nulldev, rt2860_attach,
223 224 rt2860_detach, nodev, NULL, D_MP, NULL, rt2860_quiesce);
224 225
225 226 static struct modldrv rwn_modldrv = {
226 227 &mod_driverops, /* Type of module. This one is a driver */
227 228 "Ralink RT2700/2800 driver v1.2", /* short description */
228 229 &rwn_dev_ops /* driver specific ops */
229 230 };
230 231
231 232 static struct modlinkage modlinkage = {
232 233 MODREV_1,
233 234 (void *)&rwn_modldrv,
234 235 NULL
235 236 };
236 237
237 238 static int rt2860_m_stat(void *, uint_t, uint64_t *);
238 239 static int rt2860_m_start(void *);
239 240 static void rt2860_m_stop(void *);
240 241 static int rt2860_m_promisc(void *, boolean_t);
241 242 static int rt2860_m_multicst(void *, boolean_t, const uint8_t *);
242 243 static int rt2860_m_unicst(void *, const uint8_t *);
243 244 static mblk_t *rt2860_m_tx(void *, mblk_t *);
244 245 static void rt2860_m_ioctl(void *, queue_t *, mblk_t *);
245 246 static int rt2860_m_setprop(void *arg, const char *pr_name,
246 247 mac_prop_id_t wldp_pr_num,
247 248 uint_t wldp_length, const void *wldp_buf);
248 249 static void rt2860_m_propinfo(void *arg, const char *pr_name,
249 250 mac_prop_id_t wldp_pr_num, mac_prop_info_handle_t prh);
250 251 static int rt2860_m_getprop(void *arg, const char *pr_name,
251 252 mac_prop_id_t wldp_pr_num, uint_t wldp_length,
252 253 void *wldp_buf);
253 254
254 255 static mac_callbacks_t rt2860_m_callbacks = {
255 256 MC_IOCTL | MC_SETPROP | MC_GETPROP | MC_PROPINFO,
256 257 rt2860_m_stat,
257 258 rt2860_m_start,
258 259 rt2860_m_stop,
259 260 rt2860_m_promisc,
260 261 rt2860_m_multicst,
261 262 rt2860_m_unicst,
262 263 rt2860_m_tx,
263 264 NULL,
264 265 rt2860_m_ioctl,
265 266 NULL,
266 267 NULL,
267 268 NULL,
268 269 rt2860_m_setprop,
269 270 rt2860_m_getprop,
270 271 rt2860_m_propinfo
271 272 };
272 273
273 274 #ifdef DEBUG
274 275 void
275 276 rt2860_debug(uint32_t dbg_flags, const int8_t *fmt, ...)
276 277 {
277 278 va_list args;
278 279
279 280 if (dbg_flags & rt2860_dbg_flags) {
280 281 va_start(args, fmt);
281 282 vcmn_err(CE_CONT, fmt, args);
282 283 va_end(args);
283 284 }
284 285 }
285 286 #endif
286 287
287 288 const char *
288 289 rt2860_get_rf(uint8_t rev)
289 290 {
290 291 switch (rev) {
291 292 case RT2860_RF_2820: return "RT2820";
292 293 case RT2860_RF_2850: return "RT2850";
293 294 case RT2860_RF_2720: return "RT2720";
294 295 case RT2860_RF_2750: return "RT2750";
295 296 default: return "unknown";
296 297 }
297 298 }
298 299
299 300 /*
300 301 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46,
301 302 * 93C66 or 93C86).
302 303 */
303 304 static uint16_t
304 305 rt2860_eeprom_read(struct rt2860_softc *sc, uint8_t addr)
305 306 {
306 307 int n;
307 308 uint16_t val;
308 309 uint32_t tmp;
309 310
310 311 /* clock C once before the first command */
311 312 RT2860_EEPROM_CTL(sc, 0);
312 313
313 314 RT2860_EEPROM_CTL(sc, RT2860_S);
314 315 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
315 316 RT2860_EEPROM_CTL(sc, RT2860_S);
316 317
317 318 /* write start bit (1) */
318 319 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D);
319 320 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C);
320 321
321 322 /* write READ opcode (10) */
322 323 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D);
323 324 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C);
324 325 RT2860_EEPROM_CTL(sc, RT2860_S);
325 326 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
326 327
327 328 /* write address (A5-A0 or A7-A0) */
328 329 n = ((RT2860_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7;
329 330 for (; n >= 0; n--) {
330 331 RT2860_EEPROM_CTL(sc, RT2860_S |
331 332 (((addr >> n) & 1) << RT2860_SHIFT_D));
332 333 RT2860_EEPROM_CTL(sc, RT2860_S |
333 334 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C);
334 335 }
335 336
336 337 RT2860_EEPROM_CTL(sc, RT2860_S);
337 338
338 339 /* read data Q15-Q0 */
339 340 val = 0;
340 341 for (n = 15; n >= 0; n--) {
341 342 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
342 343 tmp = RT2860_READ(sc, RT2860_PCI_EECTRL);
343 344 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n;
344 345 RT2860_EEPROM_CTL(sc, RT2860_S);
345 346 }
346 347
347 348 RT2860_EEPROM_CTL(sc, 0);
348 349
349 350 /* clear Chip Select and clock C */
350 351 RT2860_EEPROM_CTL(sc, RT2860_S);
351 352 RT2860_EEPROM_CTL(sc, 0);
352 353 RT2860_EEPROM_CTL(sc, RT2860_C);
353 354
354 355 return (val);
355 356 }
356 357
357 358 /*
358 359 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word.
359 360 * Used to adjust per-rate Tx power registers.
360 361 */
361 362 static inline uint32_t
362 363 b4inc(uint32_t b32, int8_t delta)
363 364 {
364 365 int8_t i, b4;
365 366
366 367 for (i = 0; i < 8; i++) {
367 368 b4 = b32 & 0xf;
368 369 b4 += delta;
369 370 if (b4 < 0)
370 371 b4 = 0;
371 372 else if (b4 > 0xf)
372 373 b4 = 0xf;
373 374 b32 = b32 >> 4 | b4 << 28;
374 375 }
375 376 return (b32);
376 377 }
377 378
378 379 static int
379 380 rt2860_read_eeprom(struct rt2860_softc *sc)
380 381 {
381 382 struct ieee80211com *ic = &sc->sc_ic;
382 383 int ridx, ant, i;
383 384 int8_t delta_2ghz, delta_5ghz;
384 385 uint16_t val;
385 386
386 387 /* read EEPROM version */
387 388 val = rt2860_eeprom_read(sc, RT2860_EEPROM_VERSION);
388 389 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
389 390 "EEPROM rev=%d, FAE=%d\n",
390 391 val & 0xff, val >> 8);
391 392
392 393 /* read MAC address */
393 394 val = rt2860_eeprom_read(sc, RT2860_EEPROM_MAC01);
394 395 ic->ic_macaddr[0] = val & 0xff;
395 396 ic->ic_macaddr[1] = val >> 8;
396 397 val = rt2860_eeprom_read(sc, RT2860_EEPROM_MAC23);
397 398 ic->ic_macaddr[2] = val & 0xff;
398 399 ic->ic_macaddr[3] = val >> 8;
399 400 val = rt2860_eeprom_read(sc, RT2860_EEPROM_MAC45);
400 401 ic->ic_macaddr[4] = val & 0xff;
401 402 ic->ic_macaddr[5] = val >> 8;
402 403 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
403 404 "MAC address is: %x:%x:%x:%x:%x:%x\n",
404 405 ic->ic_macaddr[0], ic->ic_macaddr[1],
405 406 ic->ic_macaddr[2], ic->ic_macaddr[3],
406 407 ic->ic_macaddr[4], ic->ic_macaddr[5]);
407 408
408 409 /* read country code */
409 410 val = rt2860_eeprom_read(sc, RT2860_EEPROM_COUNTRY);
410 411 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
411 412 "EEPROM region code=0x%04x\n", val);
412 413
413 414 /* read default BBP settings */
414 415 for (i = 0; i < 8; i++) {
415 416 val = rt2860_eeprom_read(sc, RT2860_EEPROM_BBP_BASE + i);
416 417 sc->bbp[i].val = val & 0xff;
417 418 sc->bbp[i].reg = val >> 8;
418 419 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
419 420 "BBP%d=0x%02x\n",
420 421 sc->bbp[i].reg, sc->bbp[i].val);
421 422 }
422 423
423 424 /* read RF frequency offset from EEPROM */
424 425 val = rt2860_eeprom_read(sc, RT2860_EEPROM_FREQ_LEDS);
425 426 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0;
426 427 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
427 428 "EEPROM freq offset %d\n", sc->freq & 0xff);
428 429
429 430 if ((sc->leds = val >> 8) != 0xff) {
430 431 /* read LEDs operating mode */
431 432 sc->led[0] = rt2860_eeprom_read(sc, RT2860_EEPROM_LED1);
432 433 sc->led[1] = rt2860_eeprom_read(sc, RT2860_EEPROM_LED2);
433 434 sc->led[2] = rt2860_eeprom_read(sc, RT2860_EEPROM_LED3);
434 435 } else {
435 436 /* broken EEPROM, use default settings */
436 437 sc->leds = 0x01;
437 438 sc->led[0] = 0x5555;
438 439 sc->led[1] = 0x2221;
439 440 sc->led[2] = 0xa9f8;
440 441 }
441 442 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
442 443 "EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n",
443 444 sc->leds, sc->led[0], sc->led[1], sc->led[2]);
444 445
445 446 /* read RF information */
446 447 val = rt2860_eeprom_read(sc, RT2860_EEPROM_ANTENNA);
447 448 if (val == 0xffff) {
448 449 /* broken EEPROM, default to RF2820 1T2R */
449 450 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
450 451 "invalid EEPROM antenna info, using default\n");
451 452 sc->rf_rev = RT2860_RF_2820;
452 453 sc->ntxchains = 1;
453 454 sc->nrxchains = 2;
454 455 } else {
455 456 sc->rf_rev = (val >> 8) & 0xf;
456 457 sc->ntxchains = (val >> 4) & 0xf;
457 458 sc->nrxchains = val & 0xf;
458 459 }
459 460 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
460 461 "EEPROM RF rev=0x%02x chains=%dT%dR\n",
461 462 sc->rf_rev, sc->ntxchains, sc->nrxchains);
462 463
463 464 /* check if RF supports automatic Tx access gain control */
464 465 val = rt2860_eeprom_read(sc, RT2860_EEPROM_CONFIG);
465 466 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
466 467 "EEPROM CFG 0x%04x\n", val);
467 468 if ((val & 0xff) != 0xff)
468 469 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */;
469 470
470 471 if (sc->sc_flags & RT2860_ADVANCED_PS) {
471 472 /* read PCIe power save level */
472 473 val = rt2860_eeprom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL);
473 474 if ((val & 0xff) != 0xff) {
474 475 sc->pslevel = val & 0x3;
475 476 val = rt2860_eeprom_read(sc, RT2860_EEPROM_REV);
476 477 if (val >> 8 != 0x92 || !(val & 0x80))
477 478 sc->pslevel = MIN(sc->pslevel, 1);
478 479 RWN_DEBUG(RT2860_DBG_EEPROM,
479 480 "rwn: rt2860_read_eeprom(): "
480 481 "EEPROM PCIe PS Level=%d\n",
481 482 sc->pslevel);
482 483 }
483 484 }
484 485 /* read power settings for 2GHz channels */
485 486 for (i = 0; i < 14; i += 2) {
486 487 val = rt2860_eeprom_read(sc,
487 488 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2);
488 489 sc->txpow1[i + 0] = (int8_t)(val & 0xff);
489 490 sc->txpow1[i + 1] = (int8_t)(val >> 8);
490 491
491 492 val = rt2860_eeprom_read(sc,
492 493 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2);
493 494 sc->txpow2[i + 0] = (int8_t)(val & 0xff);
494 495 sc->txpow2[i + 1] = (int8_t)(val >> 8);
495 496 }
496 497 /* fix broken Tx power entries */
497 498 for (i = 0; i < 14; i++) {
498 499 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31)
499 500 sc->txpow1[i] = 5;
500 501 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31)
501 502 sc->txpow2[i] = 5;
502 503 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
503 504 "chan %d: power1=%d, power2=%d\n",
504 505 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i]);
505 506 }
506 507 /* read power settings for 5GHz channels */
507 508 for (i = 0; i < 36; i += 2) {
508 509 val = rt2860_eeprom_read(sc,
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509 510 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2);
510 511 sc->txpow1[i + 14] = (int8_t)(val & 0xff);
511 512 sc->txpow1[i + 15] = (int8_t)(val >> 8);
512 513
513 514 val = rt2860_eeprom_read(sc,
514 515 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2);
515 516 sc->txpow2[i + 14] = (int8_t)(val & 0xff);
516 517 sc->txpow2[i + 15] = (int8_t)(val >> 8);
517 518 }
518 519 /* fix broken Tx power entries */
519 - for (i = 0; i < 36; i++) {
520 + for (i = 0; i < 35; i++) {
520 521 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15)
521 522 sc->txpow1[14 + i] = 5;
522 523 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15)
523 524 sc->txpow2[14 + i] = 5;
524 525 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
525 526 "chan %d: power1=%d, power2=%d\n",
526 527 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i],
527 528 sc->txpow2[14 + i]);
528 529 }
529 530
530 531 /* read Tx power compensation for each Tx rate */
531 532 val = rt2860_eeprom_read(sc, RT2860_EEPROM_DELTAPWR);
532 533 delta_2ghz = delta_5ghz = 0;
533 534 if ((val & 0xff) != 0xff && (val & 0x80)) {
534 535 delta_2ghz = val & 0xf;
535 536 if (!(val & 0x40)) /* negative number */
536 537 delta_2ghz = -delta_2ghz;
537 538 }
538 539 val >>= 8;
539 540 if ((val & 0xff) != 0xff && (val & 0x80)) {
540 541 delta_5ghz = val & 0xf;
541 542 if (!(val & 0x40)) /* negative number */
542 543 delta_5ghz = -delta_5ghz;
543 544 }
544 545 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
545 546 "power compensation=%d (2GHz), %d (5GHz) \n",
546 547 delta_2ghz, delta_5ghz);
547 548
548 549 for (ridx = 0; ridx < 5; ridx++) {
549 550 uint32_t reg;
550 551
551 552 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RPWR + ridx);
552 553 reg = (uint32_t)val << 16;
553 554 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RPWR + ridx + 1);
554 555 reg |= val;
555 556
556 557 sc->txpow20mhz[ridx] = reg;
557 558 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);
558 559 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);
559 560
560 561 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
561 562 "ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, "
562 563 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx],
563 564 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx]);
564 565 }
565 566
566 567 /* read factory-calibrated samples for temperature compensation */
567 568 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI1_2GHZ);
568 569 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */
569 570 sc->tssi_2ghz[1] = val >> 8; /* [-3] */
570 571 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI2_2GHZ);
571 572 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */
572 573 sc->tssi_2ghz[3] = val >> 8; /* [-1] */
573 574 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI3_2GHZ);
574 575 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */
575 576 sc->tssi_2ghz[5] = val >> 8; /* [+1] */
576 577 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI4_2GHZ);
577 578 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */
578 579 sc->tssi_2ghz[7] = val >> 8; /* [+3] */
579 580 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI5_2GHZ);
580 581 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */
581 582 sc->step_2ghz = val >> 8;
582 583 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
583 584 "TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x "
584 585 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1],
585 586 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4],
586 587 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7],
587 588 sc->tssi_2ghz[8], sc->step_2ghz);
588 589 /* check that ref value is correct, otherwise disable calibration */
589 590 if (sc->tssi_2ghz[4] == 0xff)
590 591 sc->calib_2ghz = 0;
591 592
592 593 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI1_5GHZ);
593 594 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */
594 595 sc->tssi_5ghz[1] = val >> 8; /* [-3] */
595 596 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI2_5GHZ);
596 597 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */
597 598 sc->tssi_5ghz[3] = val >> 8; /* [-1] */
598 599 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI3_5GHZ);
599 600 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */
600 601 sc->tssi_5ghz[5] = val >> 8; /* [+1] */
601 602 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI4_5GHZ);
602 603 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */
603 604 sc->tssi_5ghz[7] = val >> 8; /* [+3] */
604 605 val = rt2860_eeprom_read(sc, RT2860_EEPROM_TSSI5_5GHZ);
605 606 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */
606 607 sc->step_5ghz = val >> 8;
607 608 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
608 609 "TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x "
609 610 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1],
610 611 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4],
611 612 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7],
612 613 sc->tssi_5ghz[8], sc->step_5ghz);
613 614 /* check that ref value is correct, otherwise disable calibration */
614 615 if (sc->tssi_5ghz[4] == 0xff)
615 616 sc->calib_5ghz = 0;
616 617
617 618 /* read RSSI offsets and LNA gains from EEPROM */
618 619 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RSSI1_2GHZ);
619 620 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */
620 621 sc->rssi_2ghz[1] = val >> 8; /* Ant B */
621 622 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RSSI2_2GHZ);
622 623 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */
623 624 sc->lna[2] = val >> 8; /* channel group 2 */
624 625
625 626 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RSSI1_5GHZ);
626 627 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */
627 628 sc->rssi_5ghz[1] = val >> 8; /* Ant B */
628 629 val = rt2860_eeprom_read(sc, RT2860_EEPROM_RSSI2_5GHZ);
629 630 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */
630 631 sc->lna[3] = val >> 8; /* channel group 3 */
631 632
632 633 val = rt2860_eeprom_read(sc, RT2860_EEPROM_LNA);
633 634 sc->lna[0] = val & 0xff; /* channel group 0 */
634 635 sc->lna[1] = val >> 8; /* channel group 1 */
635 636
636 637 /* fix broken 5GHz LNA entries */
637 638 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) {
638 639 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
639 640 "invalid LNA for channel group %d\n", 2);
640 641 sc->lna[2] = sc->lna[1];
641 642 }
642 643 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) {
643 644 RWN_DEBUG(RT2860_DBG_EEPROM, "rwn: rt2860_read_eeprom(): "
644 645 "invalid LNA for channel group %d\n", 3);
645 646 sc->lna[3] = sc->lna[1];
646 647 }
647 648
648 649 /* fix broken RSSI offset entries */
649 650 for (ant = 0; ant < 3; ant++) {
650 651 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) {
651 652 RWN_DEBUG(RT2860_DBG_EEPROM,
652 653 "rwn: rt2860_read_eeprom(): "
653 654 "invalid RSSI%d offset: %d (2GHz)\n",
654 655 ant + 1, sc->rssi_2ghz[ant]);
655 656 sc->rssi_2ghz[ant] = 0;
656 657 }
657 658 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) {
658 659 RWN_DEBUG(RT2860_DBG_EEPROM,
659 660 "rwn: rt2860_read_eeprom(): "
660 661 "invalid RSSI%d offset: %d (2GHz)\n",
661 662 ant + 1, sc->rssi_5ghz[ant]);
662 663 sc->rssi_5ghz[ant] = 0;
663 664 }
664 665 }
665 666
666 667 return (RT2860_SUCCESS);
667 668 }
668 669
669 670 /*
670 671 * Allocate an DMA memory and a DMA handle for accessing it
671 672 */
672 673 static int
673 674 rt2860_alloc_dma_mem(dev_info_t *devinfo, ddi_dma_attr_t *dma_attr,
674 675 size_t memsize, ddi_device_acc_attr_t *attr_p, uint_t alloc_flags,
675 676 uint_t bind_flags, struct dma_area *dma_p)
676 677 {
677 678 int err;
678 679
679 680 /*
680 681 * Allocate handle
681 682 */
682 683 err = ddi_dma_alloc_handle(devinfo, dma_attr,
683 684 DDI_DMA_SLEEP, NULL, &dma_p->dma_hdl);
684 685 if (err != DDI_SUCCESS) {
685 686 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rwn_allo_dma_mem(): "
686 687 "failed to alloc handle\n");
687 688 goto fail1;
688 689 }
689 690
690 691 /*
691 692 * Allocate memory
692 693 */
693 694 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p,
694 695 alloc_flags, DDI_DMA_SLEEP, NULL, &dma_p->mem_va,
695 696 &dma_p->alength, &dma_p->acc_hdl);
696 697 if (err != DDI_SUCCESS) {
697 698 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rwn_alloc_dma_mem(): "
698 699 "failed to alloc mem\n");
699 700 goto fail2;
700 701 }
701 702
702 703 /*
703 704 * Bind the two together
704 705 */
705 706 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL,
706 707 dma_p->mem_va, dma_p->alength, bind_flags,
707 708 DDI_DMA_SLEEP, NULL, &dma_p->cookie, &dma_p->ncookies);
708 709 if (err != DDI_DMA_MAPPED) {
709 710 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rwn_alloc_dma_mem(): "
710 711 "failed to bind handle\n");
711 712 goto fail3;
712 713 }
713 714
714 715 if (dma_p->ncookies != 1) {
715 716 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rwn_alloc_dma_mem(): "
716 717 "failed to alloc cookies\n");
717 718 goto fail4;
718 719 }
719 720
720 721 dma_p->nslots = ~0U;
721 722 dma_p->size = ~0U;
722 723 dma_p->token = ~0U;
723 724 dma_p->offset = 0;
724 725 return (DDI_SUCCESS);
725 726
726 727 fail4:
727 728 (void) ddi_dma_unbind_handle(dma_p->dma_hdl);
728 729 fail3:
729 730 ddi_dma_mem_free(&dma_p->acc_hdl);
730 731 fail2:
731 732 ddi_dma_free_handle(&dma_p->dma_hdl);
732 733 fail1:
733 734 return (err);
734 735 }
735 736
736 737 static void
737 738 rt2860_free_dma_mem(struct dma_area *dma_p)
738 739 {
739 740 if (dma_p->dma_hdl != NULL) {
740 741 (void) ddi_dma_unbind_handle(dma_p->dma_hdl);
741 742 if (dma_p->acc_hdl != NULL) {
742 743 ddi_dma_mem_free(&dma_p->acc_hdl);
743 744 dma_p->acc_hdl = NULL;
744 745 }
745 746 ddi_dma_free_handle(&dma_p->dma_hdl);
746 747 dma_p->ncookies = 0;
747 748 dma_p->dma_hdl = NULL;
748 749 }
749 750 }
750 751
751 752 /*ARGSUSED*/
752 753 static int
753 754 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
754 755 {
755 756 int size, err;
756 757
757 758 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd);
758 759
759 760 err = rt2860_alloc_dma_mem(sc->sc_dev, &rt2860_dma_attr, size,
760 761 &rt2860_desc_accattr, DDI_DMA_CONSISTENT,
761 762 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
762 763 &ring->txdesc_dma);
763 764 if (err != DDI_SUCCESS) {
764 765 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rt2860_alloc_tx_ring(): "
765 766 "failed to alloc dma mem\n");
766 767 goto fail1;
767 768 }
768 769
769 770 ring->txd = (struct rt2860_txd *)ring->txdesc_dma.mem_va;
770 771 ring->paddr = ring->txdesc_dma.cookie.dmac_address;
771 772
772 773 ring->cur = 0;
773 774 ring->next = 0;
774 775 ring->queued = 0;
775 776
776 777 (void) bzero(ring->txd, size);
777 778 RT2860_DMA_SYNC(ring->txdesc_dma, DDI_DMA_SYNC_FORDEV);
778 779 return (DDI_SUCCESS);
779 780 fail1:
780 781 return (err);
781 782 }
782 783
783 784 void
784 785 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
785 786 {
786 787 struct rt2860_tx_data *data;
787 788 int i;
788 789
789 790 for (i = 0; i < RT2860_TX_RING_COUNT; i++) {
790 791 ring->txd[i].sdl0 &= ~LE_16(RT2860_TX_DDONE);
791 792
792 793 if ((data = ring->data[i]) == NULL)
793 794 continue; /* nothing mapped in this slot */
794 795
795 796 /* by pass if it's quiesced */
796 797 if (!(sc->sc_flags & RT2860_F_QUIESCE))
797 798 RT2860_DMA_SYNC(data->txbuf_dma, DDI_DMA_SYNC_FORDEV);
798 799
799 800 if (data->ni != NULL) {
800 801 ieee80211_free_node(data->ni);
801 802 data->ni = NULL; /* node already freed */
802 803 }
803 804
804 805 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
805 806 ring->data[i] = NULL;
806 807 }
807 808
808 809 /* by pass if it's quiesced */
809 810 if (!(sc->sc_flags & RT2860_F_QUIESCE))
810 811 RT2860_DMA_SYNC(ring->txdesc_dma, DDI_DMA_SYNC_FORDEV);
811 812
812 813 ring->queued = 0;
813 814 ring->cur = ring->next = 0;
814 815 }
815 816
816 817 /*ARGSUSED*/
817 818 static void
818 819 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
819 820 {
820 821 if (ring->txd != NULL) {
821 822 rt2860_free_dma_mem(&ring->txdesc_dma);
822 823 }
823 824 }
824 825
825 826 static int
826 827 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
827 828 {
828 829 struct rt2860_rx_data *data;
829 830 struct rt2860_rxd *rxd;
830 831 int i, err, size, datalen;
831 832
832 833 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd);
833 834
834 835 err = rt2860_alloc_dma_mem(sc->sc_dev, &rt2860_dma_attr, size,
835 836 &rt2860_desc_accattr, DDI_DMA_CONSISTENT,
836 837 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
837 838 &ring->rxdesc_dma);
838 839 if (err != DDI_SUCCESS) {
839 840 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rt2860_alloc_rx_ring(): "
840 841 "failed to alloc dma mem\n");
841 842 goto fail1;
842 843 }
843 844
844 845 ring->rxd = (struct rt2860_rxd *)ring->rxdesc_dma.mem_va;
845 846 ring->paddr = ring->rxdesc_dma.cookie.dmac_address;
846 847 bzero(ring->rxd, size);
847 848
848 849 /*
849 850 * Pre-allocate Rx buffers and populate Rx ring.
850 851 */
851 852 datalen = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rx_data);
852 853 bzero(ring->data, datalen);
853 854 for (i = 0; i < RT2860_RX_RING_COUNT; i++) {
854 855 rxd = &ring->rxd[i];
855 856 data = &ring->data[i];
856 857 /* alloc DMA memory */
857 858 (void) rt2860_alloc_dma_mem(sc->sc_dev, &rt2860_dma_attr,
858 859 sc->sc_dmabuf_size,
859 860 &rt2860_buf_accattr,
860 861 DDI_DMA_STREAMING,
861 862 DDI_DMA_READ | DDI_DMA_STREAMING,
862 863 &data->rxbuf_dma);
863 864 rxd->sdp0 = LE_32(data->rxbuf_dma.cookie.dmac_address);
864 865 rxd->sdl0 = LE_16(sc->sc_dmabuf_size);
865 866 }
866 867
867 868 ring->cur = 0;
868 869
869 870 RT2860_DMA_SYNC(ring->rxdesc_dma, DDI_DMA_SYNC_FORDEV);
870 871 return (DDI_SUCCESS);
871 872 fail2:
872 873 rt2860_free_dma_mem(&ring->rxdesc_dma);
873 874 fail1:
874 875 return (err);
875 876 }
876 877
877 878 /*ARGSUSED*/
878 879 void
879 880 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
880 881 {
881 882 int i;
882 883
883 884 for (i = 0; i < RT2860_RX_RING_COUNT; i++)
884 885 ring->rxd[i].sdl0 &= ~LE_16(RT2860_RX_DDONE);
885 886
886 887 RT2860_DMA_SYNC(ring->rxdesc_dma, DDI_DMA_SYNC_FORDEV);
887 888
888 889 ring->cur = 0;
889 890 }
890 891
891 892 /*ARGSUSED*/
892 893 static void
893 894 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
894 895 {
895 896 struct rt2860_rx_data *data;
896 897 int i, count;
897 898
898 899 if (ring->rxd != NULL)
899 900 rt2860_free_dma_mem(&ring->rxdesc_dma);
900 901
901 902 count = RT2860_RX_RING_COUNT;
902 903 if (ring->data != NULL) {
903 904 for (i = 0; i < count; i++) {
904 905 data = &ring->data[i];
905 906 rt2860_free_dma_mem(&data->rxbuf_dma);
906 907 }
907 908 }
908 909 }
909 910
910 911 static int
911 912 rt2860_alloc_tx_pool(struct rt2860_softc *sc)
912 913 {
913 914 struct rt2860_tx_data *data;
914 915 int i, err, size;
915 916
916 917 size = RT2860_TX_POOL_COUNT * sizeof (struct rt2860_txwi);
917 918
918 919 /* init data_pool early in case of failure.. */
919 920 SLIST_INIT(&sc->data_pool);
920 921
921 922 err = rt2860_alloc_dma_mem(sc->sc_dev, &rt2860_dma_attr, size,
922 923 &rt2860_desc_accattr, DDI_DMA_CONSISTENT,
923 924 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
924 925 &sc->txpool_dma);
925 926 if (err != DDI_SUCCESS) {
926 927 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rt2860_alloc_tx_pool(): "
927 928 "failed to alloc dma mem\n");
928 929 goto fail1;
929 930 }
930 931
931 932 sc->txwi = (struct rt2860_txwi *)sc->txpool_dma.mem_va;
932 933 (void) bzero(sc->txwi, size);
933 934 RT2860_DMA_SYNC(sc->txpool_dma, DDI_DMA_SYNC_FORDEV);
934 935
935 936 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) {
936 937 data = &sc->data[i];
937 938
938 939 err = rt2860_alloc_dma_mem(sc->sc_dev, &rt2860_dma_attr,
939 940 sc->sc_dmabuf_size,
940 941 &rt2860_buf_accattr, DDI_DMA_CONSISTENT,
941 942 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
942 943 &data->txbuf_dma);
943 944 if (err != DDI_SUCCESS) {
944 945 RWN_DEBUG(RT2860_DBG_DMA,
945 946 "rwn: rt2860_alloc_tx_pool(): "
946 947 "failed to alloc dma mem\n");
947 948 goto fail2;
948 949 }
949 950 data->txwi = &sc->txwi[i];
950 951 data->paddr = sc->txpool_dma.cookie.dmac_address +
951 952 i * sizeof (struct rt2860_txwi);
952 953
953 954 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
954 955 }
955 956 return (DDI_SUCCESS);
956 957 fail2:
957 958 rt2860_free_dma_mem(&sc->txpool_dma);
958 959 fail1:
959 960 return (err);
960 961 }
961 962
962 963 static void
963 964 rt2860_free_tx_pool(struct rt2860_softc *sc)
964 965 {
965 966 struct rt2860_tx_data *data;
966 967 int i;
967 968
968 969 if (sc->txwi != NULL) {
969 970 rt2860_free_dma_mem(&sc->txpool_dma);
970 971 }
971 972
972 973 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) {
973 974 data = &sc->data[i];
974 975 rt2860_free_dma_mem(&data->txbuf_dma);
975 976 }
976 977 }
977 978
978 979 /* quickly determine if a given rate is CCK or OFDM */
979 980 #define RT2860_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22)
980 981
981 982 #define RT2860_ACK_SIZE 14 /* 10 + 4(FCS) */
982 983 #define RT2860_SIFS_TIME 10
983 984
984 985 static uint8_t
985 986 rt2860_rate2mcs(uint8_t rate)
986 987 {
987 988 switch (rate) {
988 989 /* CCK rates */
989 990 case 2:
990 991 return (0);
991 992 case 4:
992 993 return (1);
993 994 case 11:
994 995 return (2);
995 996 case 22:
996 997 return (3);
997 998 /* OFDM rates */
998 999 case 12:
999 1000 return (0);
1000 1001 case 18:
1001 1002 return (1);
1002 1003 case 24:
1003 1004 return (2);
1004 1005 case 36:
1005 1006 return (3);
1006 1007 case 48:
1007 1008 return (4);
1008 1009 case 72:
1009 1010 return (5);
1010 1011 case 96:
1011 1012 return (6);
1012 1013 case 108:
1013 1014 return (7);
1014 1015 }
1015 1016
1016 1017 return (0); /* shouldn't get there */
1017 1018 }
1018 1019
1019 1020 /*
1020 1021 * Return the expected ack rate for a frame transmitted at rate `rate'.
1021 1022 */
1022 1023 static int
1023 1024 rt2860_ack_rate(struct ieee80211com *ic, int rate)
1024 1025 {
1025 1026 switch (rate) {
1026 1027 /* CCK rates */
1027 1028 case 2:
1028 1029 return (2);
1029 1030 case 4:
1030 1031 case 11:
1031 1032 case 22:
1032 1033 return ((ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate);
1033 1034
1034 1035 /* OFDM rates */
1035 1036 case 12:
1036 1037 case 18:
1037 1038 return (12);
1038 1039 case 24:
1039 1040 case 36:
1040 1041 return (24);
1041 1042 case 48:
1042 1043 case 72:
1043 1044 case 96:
1044 1045 case 108:
1045 1046 return (48);
1046 1047 }
1047 1048
1048 1049 /* default to 1Mbps */
1049 1050 return (2);
1050 1051 }
1051 1052
1052 1053
1053 1054 /*
1054 1055 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'.
1055 1056 * The function automatically determines the operating mode depending on the
1056 1057 * given rate. `flags' indicates whether short preamble is in use or not.
1057 1058 */
1058 1059 static uint16_t
1059 1060 rt2860_txtime(int len, int rate, uint32_t flags)
1060 1061 {
1061 1062 uint16_t txtime;
1062 1063
1063 1064 if (RT2860_RATE_IS_OFDM(rate)) {
1064 1065 /* IEEE Std 802.11g-2003, pp. 44 */
1065 1066 txtime = (8 + 4 * len + 3 + rate - 1) / rate;
1066 1067 txtime = 16 + 4 + 4 * txtime + 6;
1067 1068 } else {
1068 1069 /* IEEE Std 802.11b-1999, pp. 28 */
1069 1070 txtime = (16 * len + rate - 1) / rate;
1070 1071 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE))
1071 1072 txtime += 72 + 24;
1072 1073 else
1073 1074 txtime += 144 + 48;
1074 1075 }
1075 1076 return (txtime);
1076 1077 }
1077 1078
1078 1079 static int
1079 1080 rt2860_send(ieee80211com_t *ic, mblk_t *mp, uint8_t type)
1080 1081 {
1081 1082 struct rt2860_softc *sc = (struct rt2860_softc *)ic;
1082 1083 struct rt2860_tx_ring *ring;
1083 1084 struct rt2860_tx_data *data;
1084 1085 struct rt2860_txd *txd;
1085 1086 struct rt2860_txwi *txwi;
1086 1087 struct ieee80211_frame *wh;
1087 1088 struct ieee80211_node *ni;
1088 1089 int qid, off, rate, err;
1089 1090 int mblen, pktlen;
1090 1091 uint_t hdrlen;
1091 1092 uint8_t mcs, pid, qsel;
1092 1093 uint16_t dur;
1093 1094 mblk_t *m, *m0;
1094 1095
1095 1096 err = DDI_SUCCESS;
1096 1097
1097 1098 mutex_enter(&sc->sc_txlock);
1098 1099 if (RT2860_IS_SUSPEND(sc)) {
1099 1100 err = ENXIO;
1100 1101 goto fail1;
1101 1102 }
1102 1103
1103 1104 if ((type & IEEE80211_FC0_TYPE_MASK) !=
1104 1105 IEEE80211_FC0_TYPE_DATA)
1105 1106 qid = sc->mgtqid;
1106 1107 else
1107 1108 qid = EDCA_AC_BE;
1108 1109 ring = &sc->txq[qid];
1109 1110
1110 1111 if (SLIST_EMPTY(&sc->data_pool) || (ring->queued > 15)) {
1111 1112 sc->sc_need_sched = 1;
1112 1113 sc->sc_tx_nobuf++;
1113 1114 err = ENOMEM;
1114 1115 goto fail1;
1115 1116 }
1116 1117
1117 1118 /* the data pool contains at least one element, pick the first */
1118 1119 data = SLIST_FIRST(&sc->data_pool);
1119 1120
1120 1121 m = allocb(msgdsize(mp) + 32, BPRI_MED);
1121 1122 if (m == NULL) {
1122 1123 RWN_DEBUG(RT2860_DBG_TX, "rwn: rt2860_send():"
1123 1124 "rt2860_mgmt_send: can't alloc mblk.\n");
1124 1125 err = DDI_FAILURE;
1125 1126 goto fail1;
1126 1127 }
1127 1128
1128 1129 for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) {
1129 1130 mblen = MBLKL(m0);
1130 1131 (void) bcopy(m0->b_rptr, m->b_rptr + off, mblen);
1131 1132 off += mblen;
1132 1133 }
1133 1134 m->b_wptr += off;
1134 1135
1135 1136 wh = (struct ieee80211_frame *)m->b_rptr;
1136 1137 ni = ieee80211_find_txnode(ic, wh->i_addr1);
1137 1138 if (ni == NULL) {
1138 1139 err = DDI_FAILURE;
1139 1140 sc->sc_tx_err++;
1140 1141 goto fail2;
1141 1142 }
1142 1143
1143 1144 if ((type & IEEE80211_FC0_TYPE_MASK) ==
1144 1145 IEEE80211_FC0_TYPE_DATA)
1145 1146 (void) ieee80211_encap(ic, m, ni);
1146 1147
1147 1148 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1148 1149 struct ieee80211_key *k;
1149 1150 k = ieee80211_crypto_encap(ic, m);
1150 1151 if (k == NULL) {
1151 1152 sc->sc_tx_err++;
1152 1153 err = DDI_FAILURE;
1153 1154 goto fail3;
1154 1155 }
1155 1156 /* packet header may have moved, reset our local pointer */
1156 1157 wh = (struct ieee80211_frame *)m->b_rptr;
1157 1158 }
1158 1159 pktlen = msgdsize(m);
1159 1160 hdrlen = sizeof (*wh);
1160 1161
1161 1162 /* pickup a rate */
1162 1163 if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
1163 1164 ((type & IEEE80211_FC0_TYPE_MASK) !=
1164 1165 IEEE80211_FC0_TYPE_DATA))
1165 1166 rate = ni->in_rates.ir_rates[0];
1166 1167 else {
1167 1168 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE)
1168 1169 rate = ic->ic_fixed_rate;
1169 1170 else
1170 1171 rate = ni->in_rates.ir_rates[ni->in_txrate];
1171 1172 }
1172 1173 rate &= IEEE80211_RATE_VAL;
1173 1174
1174 1175 /* get MCS code from rate */
1175 1176 mcs = rt2860_rate2mcs(rate);
1176 1177
1177 1178 /* setup TX Wireless Information */
1178 1179 txwi = data->txwi;
1179 1180 (void) bzero(txwi, sizeof (struct rt2860_txwi));
1180 1181 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ?
1181 1182 RT2860_AID2WCID(ni->in_associd) : 0xff;
1182 1183 txwi->len = LE_16(pktlen);
1183 1184 if (!RT2860_RATE_IS_OFDM(rate)) {
1184 1185 txwi->phy = LE_16(RT2860_PHY_CCK);
1185 1186 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1186 1187 mcs |= RT2860_PHY_SHPRE;
1187 1188 } else
1188 1189 txwi->phy = LE_16(RT2860_PHY_OFDM);
1189 1190 txwi->phy |= LE_16(mcs);
1190 1191
1191 1192 /*
1192 1193 * We store the MCS code into the driver-private PacketID field.
1193 1194 * The PacketID is latched into TX_STAT_FIFO when Tx completes so
1194 1195 * that we know at which initial rate the frame was transmitted.
1195 1196 * We add 1 to the MCS code because setting the PacketID field to
1196 1197 * 0 means that we don't want feedback in TX_STAT_FIFO.
1197 1198 */
1198 1199 pid = (mcs + 1) & 0xf;
1199 1200 txwi->len |= LE_16(pid << RT2860_TX_PID_SHIFT);
1200 1201
1201 1202 /* check if RTS/CTS or CTS-to-self protection is required */
1202 1203 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1203 1204 (pktlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold ||
1204 1205 ((ic->ic_flags &
1205 1206 IEEE80211_F_USEPROT) && RT2860_RATE_IS_OFDM(rate))))
1206 1207 txwi->txop = RT2860_TX_TXOP_HT;
1207 1208 else
1208 1209 txwi->txop = RT2860_TX_TXOP_BACKOFF;
1209 1210
1210 1211 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1211 1212 txwi->xflags |= RT2860_TX_ACK;
1212 1213
1213 1214 dur = rt2860_txtime(RT2860_ACK_SIZE, rt2860_ack_rate(ic, rate),
1214 1215 ic->ic_flags) + sc->sifs;
1215 1216 *(uint16_t *)wh->i_dur = LE_16(dur);
1216 1217 }
1217 1218
1218 1219 /* copy and trim 802.11 header */
1219 1220 bcopy(wh, &txwi->wh, hdrlen);
1220 1221 m->b_rptr += hdrlen;
1221 1222 bcopy(m->b_rptr, data->txbuf_dma.mem_va, pktlen - hdrlen);
1222 1223
1223 1224 qsel = (qid < EDCA_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT;
1224 1225
1225 1226 /* first segment is TXWI + 802.11 header */
1226 1227 txd = &ring->txd[ring->cur];
1227 1228 txd->sdp0 = LE_32(data->paddr);
1228 1229 txd->sdl0 = LE_16(16 + hdrlen);
1229 1230 txd->flags = qsel;
1230 1231
1231 1232 /* finalize last segment */
1232 1233 txd->sdp1 = LE_32(data->txbuf_dma.cookie.dmac_address);
1233 1234 txd->sdl1 = LE_16(pktlen - hdrlen | RT2860_TX_LS1);
1234 1235
1235 1236 /* remove from the free pool and link it into the SW Tx slot */
1236 1237 SLIST_REMOVE_HEAD(&sc->data_pool, next);
1237 1238 data->ni = ieee80211_ref_node(ni);
1238 1239 ring->data[ring->cur] = data;
1239 1240
1240 1241 (void) ddi_dma_sync(sc->txpool_dma.dma_hdl,
1241 1242 _PTRDIFF(txwi, sc->txwi),
1242 1243 (hdrlen + 16 + 2),
1243 1244 DDI_DMA_SYNC_FORDEV);
1244 1245 RT2860_DMA_SYNC(data->txbuf_dma, DDI_DMA_SYNC_FORDEV);
1245 1246 RT2860_DMA_SYNC(ring->txdesc_dma, DDI_DMA_SYNC_FORDEV);
1246 1247
1247 1248 RWN_DEBUG(RT2860_DBG_TX, "rwn: rt2860_send():"
1248 1249 "sending frame qid=%d wcid=%d rate=%d cur = %x\n",
1249 1250 qid, txwi->wcid, rate, ring->cur);
1250 1251
1251 1252 ring->queued++;
1252 1253 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1253 1254
1254 1255 /* kick Tx */
1255 1256 RT2860_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur);
1256 1257
1257 1258 sc->sc_tx_timer = 5;
1258 1259
1259 1260 ic->ic_stats.is_tx_frags++;
1260 1261 ic->ic_stats.is_tx_bytes += pktlen;
1261 1262
1262 1263 fail3:
1263 1264 ieee80211_free_node(ni);
1264 1265 fail2:
1265 1266 freemsg(m);
1266 1267 fail1:
1267 1268 if ((type & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_DATA ||
1268 1269 err == DDI_SUCCESS)
1269 1270 freemsg(mp);
1270 1271 mutex_exit(&sc->sc_txlock);
1271 1272 return (err);
1272 1273 }
1273 1274
1274 1275 /*
1275 1276 * This function is called periodically (every 200ms) during scanning to
1276 1277 * switch from one channel to another.
1277 1278 */
1278 1279 static void
1279 1280 rt2860_next_scan(void *arg)
1280 1281 {
1281 1282 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
1282 1283 struct ieee80211com *ic = &sc->sc_ic;
1283 1284
1284 1285 if (ic->ic_state == IEEE80211_S_SCAN)
1285 1286 (void) ieee80211_next_scan(ic);
1286 1287 }
1287 1288
1288 1289 static void
1289 1290 rt2860_updateslot(struct rt2860_softc *sc)
1290 1291 {
1291 1292 struct ieee80211com *ic = &sc->sc_ic;
1292 1293 uint32_t tmp;
1293 1294
1294 1295 tmp = RT2860_READ(sc, RT2860_BKOFF_SLOT_CFG);
1295 1296 tmp &= ~0xff;
1296 1297 tmp |= (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20;
1297 1298 RT2860_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp);
1298 1299 }
1299 1300
1300 1301 static void
1301 1302 rt2860_iter_func(void *arg, struct ieee80211_node *ni)
1302 1303 {
1303 1304 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
1304 1305 uint8_t wcid;
1305 1306
1306 1307 wcid = RT2860_AID2WCID(ni->in_associd);
1307 1308 rt2860_amrr_choose(&sc->amrr, ni, &sc->amn[wcid]);
1308 1309 }
1309 1310
1310 1311 static void
1311 1312 rt2860_updatestats(void *arg)
1312 1313 {
1313 1314 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
1314 1315 struct ieee80211com *ic = &sc->sc_ic;
1315 1316
1316 1317 if (ic->ic_opmode == IEEE80211_M_STA)
1317 1318 rt2860_iter_func(sc, ic->ic_bss);
1318 1319 else
1319 1320 ieee80211_iterate_nodes(&ic->ic_sta, rt2860_iter_func, arg);
1320 1321
1321 1322 sc->sc_rssadapt_id = timeout(rt2860_updatestats, (void *)sc,
1322 1323 drv_usectohz(500 * 1000));
1323 1324 }
1324 1325
1325 1326 static void
1326 1327 rt2860_enable_mrr(struct rt2860_softc *sc)
1327 1328 {
1328 1329 #define CCK(mcs) (mcs)
1329 1330 #define OFDM(mcs) ((uint32_t)1 << 3 | (mcs))
1330 1331 RT2860_WRITE(sc, RT2860_LG_FBK_CFG0,
1331 1332 OFDM(6) << 28 | /* 54->48 */
1332 1333 OFDM(5) << 24 | /* 48->36 */
1333 1334 OFDM(4) << 20 | /* 36->24 */
1334 1335 OFDM(3) << 16 | /* 24->18 */
1335 1336 OFDM(2) << 12 | /* 18->12 */
1336 1337 OFDM(1) << 8 | /* 12-> 9 */
1337 1338 OFDM(0) << 4 | /* 9-> 6 */
1338 1339 OFDM(0)); /* 6-> 6 */
1339 1340
1340 1341 RT2860_WRITE(sc, RT2860_LG_FBK_CFG1,
1341 1342 CCK(2) << 12 | /* 11->5.5 */
1342 1343 CCK(1) << 8 | /* 5.5-> 2 */
1343 1344 CCK(0) << 4 | /* 2-> 1 */
1344 1345 CCK(0)); /* 1-> 1 */
1345 1346 #undef OFDM
1346 1347 #undef CCK
1347 1348 }
1348 1349
1349 1350 static void
1350 1351 rt2860_set_txpreamble(struct rt2860_softc *sc)
1351 1352 {
1352 1353 uint32_t tmp;
1353 1354
1354 1355 tmp = RT2860_READ(sc, RT2860_AUTO_RSP_CFG);
1355 1356 tmp &= ~RT2860_CCK_SHORT_EN;
1356 1357 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE)
1357 1358 tmp |= RT2860_CCK_SHORT_EN;
1358 1359 RT2860_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp);
1359 1360 }
1360 1361
1361 1362 static void
1362 1363 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid)
1363 1364 {
1364 1365 RT2860_WRITE(sc, RT2860_MAC_BSSID_DW0,
1365 1366 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24);
1366 1367 RT2860_WRITE(sc, RT2860_MAC_BSSID_DW1,
1367 1368 bssid[4] | bssid[5] << 8);
1368 1369 }
1369 1370
1370 1371 static void
1371 1372 rt2860_set_basicrates(struct rt2860_softc *sc)
1372 1373 {
1373 1374 struct ieee80211com *ic = &sc->sc_ic;
1374 1375
1375 1376 /* set basic rates mask */
1376 1377 if (ic->ic_curmode == IEEE80211_MODE_11B)
1377 1378 RT2860_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x003);
1378 1379 else if (ic->ic_curmode == IEEE80211_MODE_11A)
1379 1380 RT2860_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x150);
1380 1381 else /* 11g */
1381 1382 RT2860_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x15f);
1382 1383 }
1383 1384
1384 1385 static void
1385 1386 rt2860_amrr_node_init(const struct rt2860_amrr *amrr,
1386 1387 struct rt2860_amrr_node *amn)
1387 1388 {
1388 1389 amn->amn_success = 0;
1389 1390 amn->amn_recovery = 0;
1390 1391 amn->amn_txcnt = amn->amn_retrycnt = 0;
1391 1392 amn->amn_success_threshold = amrr->amrr_min_success_threshold;
1392 1393 }
1393 1394
1394 1395 static void
1395 1396 rt2860_amrr_choose(struct rt2860_amrr *amrr, struct ieee80211_node *ni,
1396 1397 struct rt2860_amrr_node *amn)
1397 1398 {
1398 1399 #define RV(rate) ((rate) & IEEE80211_RATE_VAL)
1399 1400 #define is_success(amn) \
1400 1401 ((amn)->amn_retrycnt < (amn)->amn_txcnt / 10)
1401 1402 #define is_failure(amn) \
1402 1403 ((amn)->amn_retrycnt > (amn)->amn_txcnt / 3)
1403 1404 #define is_enough(amn) \
1404 1405 ((amn)->amn_txcnt > 10)
1405 1406 #define is_min_rate(ni) \
1406 1407 ((ni)->in_txrate == 0)
1407 1408 #define is_max_rate(ni) \
1408 1409 ((ni)->in_txrate == (ni)->in_rates.ir_nrates - 1)
1409 1410 #define increase_rate(ni) \
1410 1411 ((ni)->in_txrate++)
1411 1412 #define decrease_rate(ni) \
1412 1413 ((ni)->in_txrate--)
1413 1414 #define reset_cnt(amn) \
1414 1415 { (amn)->amn_txcnt = (amn)->amn_retrycnt = 0; }
1415 1416
1416 1417 int need_change = 0;
1417 1418
1418 1419 if (is_success(amn) && is_enough(amn)) {
1419 1420 amn->amn_success++;
1420 1421 if (amn->amn_success >= amn->amn_success_threshold &&
1421 1422 !is_max_rate(ni)) {
1422 1423 amn->amn_recovery = 1;
1423 1424 amn->amn_success = 0;
1424 1425 increase_rate(ni);
1425 1426 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_amrr_choose(): "
1426 1427 "increase rate = %d, #tx = %d, #retries = %d\n",
1427 1428 RV(ni->in_rates.ir_rates[ni->in_txrate]),
1428 1429 amn->amn_txcnt, amn->amn_retrycnt);
1429 1430 need_change = 1;
1430 1431 } else {
1431 1432 amn->amn_recovery = 0;
1432 1433 }
1433 1434 } else if (is_failure(amn)) {
1434 1435 amn->amn_success = 0;
1435 1436 if (!is_min_rate(ni)) {
1436 1437 if (amn->amn_recovery) {
1437 1438 amn->amn_success_threshold *= 2;
1438 1439 if (amn->amn_success_threshold >
1439 1440 amrr->amrr_max_success_threshold)
1440 1441 amn->amn_success_threshold =
1441 1442 amrr->amrr_max_success_threshold;
1442 1443 } else {
1443 1444 amn->amn_success_threshold =
1444 1445 amrr->amrr_min_success_threshold;
1445 1446 }
1446 1447 decrease_rate(ni);
1447 1448 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_amrr_choose(): "
1448 1449 "decrease rate = %d, #tx = %d, #retries = %d\n",
1449 1450 RV(ni->in_rates.ir_rates[ni->in_txrate]),
1450 1451 amn->amn_txcnt, amn->amn_retrycnt);
1451 1452 need_change = 1;
1452 1453 }
1453 1454 amn->amn_recovery = 0;
1454 1455 }
1455 1456
1456 1457 if (is_enough(amn) || need_change)
1457 1458 reset_cnt(amn);
1458 1459 #undef RV
1459 1460 }
1460 1461
1461 1462 static void
1462 1463 rt2860_newassoc(struct ieee80211com *ic, struct ieee80211_node *in, int isnew)
1463 1464 {
1464 1465 struct rt2860_softc *sc = (struct rt2860_softc *)ic;
1465 1466 uint32_t off;
1466 1467 uint8_t *fptr, wcid = 0;
1467 1468 int i;
1468 1469
1469 1470 if (isnew && in->in_associd != 0) {
1470 1471 /* only interested in true associations */
1471 1472 wcid = RT2860_AID2WCID(in->in_associd);
1472 1473
1473 1474 /* init WCID table entry */
1474 1475 off = RT2860_WCID_ENTRY(wcid);
1475 1476 fptr = in->in_macaddr;
1476 1477 for (i = 0; i < IEEE80211_ADDR_LEN; i++)
1477 1478 rt2860_mem_write1(sc, off++, *fptr++);
1478 1479 }
1479 1480 rt2860_amrr_node_init(&sc->amrr, &sc->amn[wcid]);
1480 1481
1481 1482 /* set rate to some reasonable initial value */
1482 1483 i = in->in_rates.ir_nrates - 1;
1483 1484 for (; i > 0 && (in->in_rates.ir_rates[i] & IEEE80211_RATE_VAL) > 72; )
1484 1485 i--;
1485 1486 in->in_txrate = i;
1486 1487
1487 1488 RWN_DEBUG(RT2860_DBG_80211, "rwn: rt2860_newassoc(): "
1488 1489 "new assoc isnew=%d WCID=%d, initial rate=%d\n",
1489 1490 isnew, wcid,
1490 1491 in->in_rates.ir_rates[i] & IEEE80211_RATE_VAL);
1491 1492 RWN_DEBUG(RT2860_DBG_80211, "rwn: rt2860_newassoc(): "
1492 1493 "addr=%x:%x:%x:%x:%x:%x\n",
1493 1494 in->in_macaddr[0], in->in_macaddr[1], in->in_macaddr[2],
1494 1495 in->in_macaddr[3], in->in_macaddr[4], in->in_macaddr[5]);
1495 1496 }
1496 1497
1497 1498 void
1498 1499 rt2860_enable_tsf_sync(struct rt2860_softc *sc)
1499 1500 {
1500 1501 struct ieee80211com *ic = &sc->sc_ic;
1501 1502 uint32_t tmp;
1502 1503
1503 1504 tmp = RT2860_READ(sc, RT2860_BCN_TIME_CFG);
1504 1505
1505 1506 tmp &= ~0x1fffff;
1506 1507 tmp |= ic->ic_bss->in_intval * 16;
1507 1508 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN;
1508 1509 if (ic->ic_opmode == IEEE80211_M_STA) {
1509 1510 /*
1510 1511 * Local TSF is always updated with remote TSF on beacon
1511 1512 * reception.
1512 1513 */
1513 1514 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT;
1514 1515 }
1515 1516
1516 1517 RT2860_WRITE(sc, RT2860_BCN_TIME_CFG, tmp);
1517 1518 }
1518 1519
1519 1520 static int
1520 1521 rt2860_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
1521 1522 {
1522 1523 struct rt2860_softc *sc = (struct rt2860_softc *)ic;
1523 1524 enum ieee80211_state ostate;
1524 1525 int err;
1525 1526 uint32_t tmp;
1526 1527
1527 1528 ostate = ic->ic_state;
1528 1529 RWN_DEBUG(RT2860_DBG_80211, "rwn: rt2860_newstate(): "
1529 1530 "%x -> %x!\n", ostate, nstate);
1530 1531
1531 1532 RT2860_GLOCK(sc);
1532 1533 if (sc->sc_scan_id != 0) {
1533 1534 (void) untimeout(sc->sc_scan_id);
1534 1535 sc->sc_scan_id = 0;
1535 1536 }
1536 1537 if (sc->sc_rssadapt_id != 0) {
1537 1538 (void) untimeout(sc->sc_rssadapt_id);
1538 1539 sc->sc_rssadapt_id = 0;
1539 1540 }
1540 1541 if (ostate == IEEE80211_S_RUN) {
1541 1542 /* turn link LED off */
1542 1543 rt2860_set_leds(sc, RT2860_LED_RADIO);
1543 1544 }
1544 1545
1545 1546 switch (nstate) {
1546 1547 case IEEE80211_S_INIT:
1547 1548 if (ostate == IEEE80211_S_RUN) {
1548 1549 /* abort TSF synchronization */
1549 1550 tmp = RT2860_READ(sc, RT2860_BCN_TIME_CFG);
1550 1551 RT2860_WRITE(sc, RT2860_BCN_TIME_CFG,
1551 1552 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN |
1552 1553 RT2860_TBTT_TIMER_EN));
1553 1554 }
1554 1555 break;
1555 1556
1556 1557 case IEEE80211_S_SCAN:
1557 1558 rt2860_set_chan(sc, ic->ic_curchan);
1558 1559 sc->sc_scan_id = timeout(rt2860_next_scan, (void *)sc,
1559 1560 drv_usectohz(200000));
1560 1561 break;
1561 1562
1562 1563 case IEEE80211_S_AUTH:
1563 1564 case IEEE80211_S_ASSOC:
1564 1565 rt2860_set_chan(sc, ic->ic_curchan);
1565 1566 break;
1566 1567
1567 1568 case IEEE80211_S_RUN:
1568 1569 rt2860_set_chan(sc, ic->ic_curchan);
1569 1570
1570 1571 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1571 1572 rt2860_updateslot(sc);
1572 1573 rt2860_enable_mrr(sc);
1573 1574 rt2860_set_txpreamble(sc);
1574 1575 rt2860_set_basicrates(sc);
1575 1576 rt2860_set_bssid(sc, ic->ic_bss->in_bssid);
1576 1577 }
1577 1578 if (ic->ic_opmode == IEEE80211_M_STA) {
1578 1579 /* fake a join to init the tx rate */
1579 1580 rt2860_newassoc(ic, ic->ic_bss, 1);
1580 1581 }
1581 1582
1582 1583 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1583 1584 rt2860_enable_tsf_sync(sc);
1584 1585 sc->sc_rssadapt_id = timeout(rt2860_updatestats,
1585 1586 (void *)sc, drv_usectohz(500 * 1000));
1586 1587 }
1587 1588
1588 1589 /* turn link LED on */
1589 1590 rt2860_set_leds(sc, RT2860_LED_RADIO |
1590 1591 (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) ?
1591 1592 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ));
1592 1593 break;
1593 1594 }
1594 1595
1595 1596 RT2860_GUNLOCK(sc);
1596 1597
1597 1598 err = sc->sc_newstate(ic, nstate, arg);
1598 1599
1599 1600 return (err);
1600 1601 }
1601 1602
1602 1603 /*
1603 1604 * Return the Rx chain with the highest RSSI for a given frame.
1604 1605 */
1605 1606 static uint8_t
1606 1607 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi)
1607 1608 {
1608 1609 uint8_t rxchain = 0;
1609 1610
1610 1611 if (sc->nrxchains > 1)
1611 1612 if (rxwi->rssi[1] > rxwi->rssi[rxchain])
1612 1613 rxchain = 1;
1613 1614 if (sc->nrxchains > 2)
1614 1615 if (rxwi->rssi[2] > rxwi->rssi[rxchain])
1615 1616 rxchain = 2;
1616 1617
1617 1618 return (rxchain);
1618 1619 }
1619 1620
1620 1621 static void
1621 1622 rt2860_drain_stats_fifo(struct rt2860_softc *sc)
1622 1623 {
1623 1624 struct rt2860_amrr_node *amn;
1624 1625 uint32_t stat;
1625 1626 uint8_t wcid, mcs, pid;
1626 1627
1627 1628 /* drain Tx status FIFO (maxsize = 16) */
1628 1629 while ((stat = RT2860_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) {
1629 1630 RWN_DEBUG(RT2860_DBG_TX, "rwn: rt2860_drain_stats_fifo(): "
1630 1631 "tx stat 0x%08\n", stat);
1631 1632
1632 1633 wcid = (stat >> 8) & 0xff;
1633 1634
1634 1635 /* if no ACK was requested, no feedback is available */
1635 1636 if (!(stat & RT2860_TXQ_ACKREQ) || wcid == 0xff)
1636 1637 continue;
1637 1638 /* update per-STA AMRR stats */
1638 1639 amn = &sc->amn[wcid];
1639 1640 amn->amn_txcnt++;
1640 1641 if (stat & RT2860_TXQ_OK) {
1641 1642 /*
1642 1643 * Check if there were retries, ie if the Tx success
1643 1644 * rate is different from the requested rate. Note
1644 1645 * that it works only because we do not allow rate
1645 1646 * fallback from OFDM to CCK.
1646 1647 */
1647 1648 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f;
1648 1649 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf;
1649 1650 if (mcs + 1 != pid)
1650 1651 amn->amn_retrycnt++;
1651 1652 } else
1652 1653 amn->amn_retrycnt++;
1653 1654 }
1654 1655 }
1655 1656
1656 1657 /*ARGSUSED*/
1657 1658 static void
1658 1659 rt2860_tx_intr(struct rt2860_softc *sc, int qid)
1659 1660 {
1660 1661 struct rt2860_tx_ring *ring = &sc->txq[qid];
1661 1662 struct ieee80211com *ic = &sc->sc_ic;
1662 1663 uint32_t hw;
1663 1664
1664 1665 rt2860_drain_stats_fifo(sc);
1665 1666
1666 1667 mutex_enter(&sc->sc_txlock);
1667 1668 hw = RT2860_READ(sc, RT2860_TX_DTX_IDX(qid));
1668 1669 RWN_DEBUG(RT2860_DBG_TX, "rwn: rwn_tx_intr():"
1669 1670 "hw = %x, ring->next = %x, queued = %d\n",
1670 1671 hw, ring->next, ring->queued);
1671 1672 while (ring->next != hw) {
1672 1673 struct rt2860_txd *txd = &ring->txd[ring->next];
1673 1674 struct rt2860_tx_data *data = ring->data[ring->next];
1674 1675
1675 1676 if (data != NULL) {
1676 1677 RT2860_DMA_SYNC(data->txbuf_dma, DDI_DMA_SYNC_FORDEV);
1677 1678 if (data->ni != NULL) {
1678 1679 ieee80211_free_node(data->ni);
1679 1680 data->ni = NULL;
1680 1681 }
1681 1682 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
1682 1683 ring->data[ring->next] = NULL;
1683 1684 }
1684 1685
1685 1686 txd->sdl0 &= ~LE_16(RT2860_TX_DDONE);
1686 1687
1687 1688 (void) ddi_dma_sync(ring->txdesc_dma.dma_hdl,
1688 1689 ring->next * sizeof (struct rt2860_txd),
1689 1690 sizeof (struct rt2860_txd),
1690 1691 DDI_DMA_SYNC_FORDEV);
1691 1692
1692 1693 ring->queued--;
1693 1694 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT;
1694 1695
1695 1696 if (sc->sc_need_sched &&
1696 1697 (ring->queued < RT2860_TX_RING_COUNT)) {
1697 1698 sc->sc_need_sched = 0;
1698 1699 mac_tx_update(ic->ic_mach);
1699 1700 }
1700 1701 }
1701 1702 sc->sc_tx_timer = 0;
1702 1703 mutex_exit(&sc->sc_txlock);
1703 1704 }
1704 1705
1705 1706 static void
1706 1707 rt2860_rx_intr(struct rt2860_softc *sc)
1707 1708 {
1708 1709 struct ieee80211com *ic = &sc->sc_ic;
1709 1710 struct ieee80211_node *ni;
1710 1711 struct ieee80211_frame *wh;
1711 1712 int pktlen;
1712 1713 uint8_t ant, rssi, *rxbuf;
1713 1714 mblk_t *mp0;
1714 1715
1715 1716 mutex_enter(&sc->sc_rxlock);
1716 1717 for (;;) {
1717 1718 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur];
1718 1719 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur];
1719 1720 struct rt2860_rxwi *rxwi;
1720 1721
1721 1722 (void) ddi_dma_sync(sc->rxq.rxdesc_dma.dma_hdl,
1722 1723 sc->rxq.cur * sizeof (struct rt2860_rxd),
1723 1724 sizeof (struct rt2860_rxd),
1724 1725 DDI_DMA_SYNC_FORKERNEL);
1725 1726
1726 1727 if (!(rxd->sdl0 & LE_16(RT2860_RX_DDONE))) {
1727 1728 RWN_DEBUG(RT2860_DBG_RX, "rwn: rt2860_rx_intr(): "
1728 1729 "rx done!\n");
1729 1730 break;
1730 1731 }
1731 1732
1732 1733 if (rxd->flags &
1733 1734 LE_32(RT2860_RX_CRCERR | RT2860_RX_ICVERR)) {
1734 1735 RWN_DEBUG(RT2860_DBG_RX, "rwn: rt2860_rx_intr(): "
1735 1736 "rx crc error & rx icv error!\n");
1736 1737 sc->sc_rx_err++;
1737 1738 goto skip;
1738 1739 }
1739 1740
1740 1741 if (rxd->flags & LE_32(RT2860_RX_MICERR)) {
1741 1742 RWN_DEBUG(RT2860_DBG_RX, "rwn: rt2860_rx_intr(): "
1742 1743 "rx mic error!\n");
1743 1744 sc->sc_rx_err++;
1744 1745 goto skip;
1745 1746 }
1746 1747
1747 1748 (void) ddi_dma_sync(data->rxbuf_dma.dma_hdl,
1748 1749 data->rxbuf_dma.offset,
1749 1750 data->rxbuf_dma.alength,
1750 1751 DDI_DMA_SYNC_FORCPU);
1751 1752
1752 1753 rxbuf = (uint8_t *)data->rxbuf_dma.mem_va;
1753 1754 rxd->sdp0 = LE_32(data->rxbuf_dma.cookie.dmac_address);
1754 1755 rxwi = (struct rt2860_rxwi *)rxbuf;
1755 1756 rxbuf = (uint8_t *)(rxwi + 1);
1756 1757 pktlen = LE_16(rxwi->len) & 0xfff;
1757 1758
1758 1759 mp0 = allocb(sc->sc_dmabuf_size, BPRI_MED);
1759 1760 if (mp0 == NULL) {
1760 1761 RWN_DEBUG(RT2860_DBG_RX, "rwn: rt2860_rx_intr():"
1761 1762 "alloc mblk error\n");
1762 1763 sc->sc_rx_nobuf++;
1763 1764 goto skip;
1764 1765 }
1765 1766 bcopy(rxbuf, mp0->b_rptr, pktlen);
1766 1767 mp0->b_wptr += pktlen;
1767 1768
1768 1769 wh = (struct ieee80211_frame *)mp0->b_rptr;
1769 1770
1770 1771 /* HW may insert 2 padding bytes after 802.11 header */
1771 1772 if (rxd->flags & LE_32(RT2860_RX_L2PAD)) {
1772 1773 RWN_DEBUG(RT2860_DBG_RX, "rwn: rt2860_rx_intr():"
1773 1774 "2 padding bytes after 80211 header!\n");
1774 1775 }
1775 1776
1776 1777 ant = rt2860_maxrssi_chain(sc, rxwi);
1777 1778 rssi = RT2860_RSSI_OFFSET - rxwi->rssi[ant];
1778 1779 /* grab a reference to the source node */
1779 1780 ni = ieee80211_find_rxnode(ic, wh);
1780 1781
1781 1782 (void) ieee80211_input(ic, mp0, ni, rssi, 0);
1782 1783
1783 1784 /* node is no longer needed */
1784 1785 ieee80211_free_node(ni);
1785 1786 skip:
1786 1787 rxd->sdl0 &= ~LE_16(RT2860_RX_DDONE);
1787 1788
1788 1789 (void) ddi_dma_sync(sc->rxq.rxdesc_dma.dma_hdl,
1789 1790 sc->rxq.cur * sizeof (struct rt2860_rxd),
1790 1791 sizeof (struct rt2860_rxd),
1791 1792 DDI_DMA_SYNC_FORDEV);
1792 1793
1793 1794 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT;
1794 1795 }
1795 1796 mutex_exit(&sc->sc_rxlock);
1796 1797
1797 1798 /* tell HW what we have processed */
1798 1799 RT2860_WRITE(sc, RT2860_RX_CALC_IDX,
1799 1800 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT);
1800 1801 }
1801 1802
1802 1803 static uint_t
1803 1804 rt2860_softintr(caddr_t data)
1804 1805 {
1805 1806 struct rt2860_softc *sc = (struct rt2860_softc *)data;
1806 1807
1807 1808 /*
1808 1809 * Check if the soft interrupt is triggered by another
1809 1810 * driver at the same level.
1810 1811 */
1811 1812 RT2860_GLOCK(sc);
1812 1813 if (sc->sc_rx_pend) {
1813 1814 sc->sc_rx_pend = 0;
1814 1815 RT2860_GUNLOCK(sc);
1815 1816 rt2860_rx_intr(sc);
1816 1817 return (DDI_INTR_CLAIMED);
1817 1818 }
1818 1819 RT2860_GUNLOCK(sc);
1819 1820
1820 1821 return (DDI_INTR_UNCLAIMED);
1821 1822 }
1822 1823
1823 1824 static uint_t
1824 1825 rt2860_intr(caddr_t arg)
1825 1826 {
1826 1827 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
1827 1828 uint32_t r;
1828 1829
1829 1830 RT2860_GLOCK(sc);
1830 1831
1831 1832 if ((!RT2860_IS_RUNNING(sc)) || RT2860_IS_SUSPEND(sc)) {
1832 1833 /*
1833 1834 * The hardware is not ready/present, don't touch anything.
1834 1835 * Note this can happen early on if the IRQ is shared.
1835 1836 */
1836 1837 RT2860_GUNLOCK(sc);
1837 1838 return (DDI_INTR_UNCLAIMED);
1838 1839 }
1839 1840
1840 1841 r = RT2860_READ(sc, RT2860_INT_STATUS);
1841 1842 if (r == 0xffffffff) {
1842 1843 RT2860_GUNLOCK(sc);
1843 1844 return (DDI_INTR_UNCLAIMED);
1844 1845 }
1845 1846 if (r == 0) {
1846 1847 RT2860_GUNLOCK(sc);
1847 1848 return (DDI_INTR_UNCLAIMED);
1848 1849 }
1849 1850
1850 1851 /* acknowledge interrupts */
1851 1852 RT2860_WRITE(sc, RT2860_INT_STATUS, r);
1852 1853
1853 1854 if (r & RT2860_TX_COHERENT)
1854 1855 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr()"
1855 1856 "RT2860_TX_COHERENT\n");
1856 1857
1857 1858 if (r & RT2860_RX_COHERENT)
1858 1859 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr()"
1859 1860 "RT2860_RX_COHERENT\n");
1860 1861
1861 1862 if (r & RT2860_MAC_INT_2) {
1862 1863 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1863 1864 "RT2860_MAC_INT_2\n");
1864 1865 rt2860_drain_stats_fifo(sc);
1865 1866 }
1866 1867
1867 1868 if (r & RT2860_TX_DONE_INT5) {
1868 1869 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1869 1870 "RT2860_TX_DONE_INT5\n");
1870 1871 rt2860_tx_intr(sc, 5);
1871 1872 }
1872 1873
1873 1874 if (r & RT2860_RX_DONE_INT) {
1874 1875 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr()"
1875 1876 "RT2860_RX_INT\n");
1876 1877 sc->sc_rx_pend = 1;
1877 1878 ddi_trigger_softintr(sc->sc_softintr_hdl);
1878 1879 }
1879 1880
1880 1881 if (r & RT2860_TX_DONE_INT4) {
1881 1882 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1882 1883 "RT2860_TX_DONE_INT4\n");
1883 1884 rt2860_tx_intr(sc, 4);
1884 1885 }
1885 1886
1886 1887 if (r & RT2860_TX_DONE_INT3) {
1887 1888 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1888 1889 "RT2860_TX_DONE_INT3\n");
1889 1890 rt2860_tx_intr(sc, 3);
1890 1891 }
1891 1892
1892 1893 if (r & RT2860_TX_DONE_INT2) {
1893 1894 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1894 1895 "RT2860_TX_DONE_INT2\n");
1895 1896 rt2860_tx_intr(sc, 2);
1896 1897 }
1897 1898
1898 1899 if (r & RT2860_TX_DONE_INT1) {
1899 1900 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1900 1901 "RT2860_TX_DONE_INT1\n");
1901 1902 rt2860_tx_intr(sc, 1);
1902 1903 }
1903 1904
1904 1905 if (r & RT2860_TX_DONE_INT0) {
1905 1906 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1906 1907 "RT2860_TX_DONE_INT0\n");
1907 1908 rt2860_tx_intr(sc, 0);
1908 1909 }
1909 1910
1910 1911 if (r & RT2860_MAC_INT_0) {
1911 1912 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1912 1913 "RT2860_MAC_INT_0\n");
1913 1914 struct ieee80211com *ic = &sc->sc_ic;
1914 1915 /* check if protection mode has changed */
1915 1916 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) {
1916 1917 rt2860_updateprot(ic);
1917 1918 sc->sc_ic_flags = ic->ic_flags;
1918 1919 }
1919 1920 }
1920 1921
1921 1922 if (r & RT2860_MAC_INT_3)
1922 1923 RWN_DEBUG(RT2860_DBG_INTR, "rwn: rt2860_intr(): "
1923 1924 "RT2860_MAC_INT_3\n");
1924 1925
1925 1926 RT2860_GUNLOCK(sc);
1926 1927
1927 1928 return (DDI_INTR_CLAIMED);
1928 1929 }
1929 1930
1930 1931 static void
1931 1932 rt2860_set_region_4(struct rt2860_softc *sc,
1932 1933 uint32_t addr, uint32_t data, int size)
1933 1934 {
1934 1935 for (; size > 0; size--, data++, addr += 4)
1935 1936 ddi_put32((sc)->sc_io_handle,
1936 1937 (uint32_t *)((uintptr_t)(sc)->sc_io_base + addr), data);
1937 1938 }
1938 1939
1939 1940 static int
1940 1941 rt2860_load_microcode(struct rt2860_softc *sc)
1941 1942 {
1942 1943 int ntries;
1943 1944 size_t size;
1944 1945 uint8_t *ucode, *fptr;
1945 1946 uint32_t off, i;
1946 1947
1947 1948 ucode = rt2860_fw_bin;
1948 1949 size = sizeof (rt2860_fw_bin);
1949 1950 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_load_microcode(): "
1950 1951 "The size of ucode is: %x\n", size);
1951 1952
1952 1953 /* set "host program ram write selection" bit */
1953 1954 RT2860_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL);
1954 1955 /* write microcode image */
1955 1956 fptr = ucode;
1956 1957 off = RT2860_FW_BASE;
1957 1958 for (i = 0; i < size; i++) {
1958 1959 rt2860_mem_write1(sc, off++, *fptr++);
1959 1960 }
1960 1961 /* kick microcontroller unit */
1961 1962 RT2860_WRITE(sc, RT2860_SYS_CTRL, 0);
1962 1963 RT2860_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET);
1963 1964
1964 1965 RT2860_WRITE(sc, RT2860_H2M_BBPAGENT, 0);
1965 1966 RT2860_WRITE(sc, RT2860_H2M_MAILBOX, 0);
1966 1967
1967 1968 /* wait until microcontroller is ready */
1968 1969 for (ntries = 0; ntries < 1000; ntries++) {
1969 1970 if (RT2860_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY)
1970 1971 break;
1971 1972 DELAY(1000);
1972 1973 }
1973 1974 if (ntries == 1000) {
1974 1975 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_load_microcode(): "
1975 1976 "timeout waiting for MCU to initialie\n");
1976 1977 return (ETIMEDOUT);
1977 1978 }
1978 1979
1979 1980 return (0);
1980 1981 }
1981 1982
1982 1983 static void
1983 1984 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr)
1984 1985 {
1985 1986 RT2860_WRITE(sc, RT2860_MAC_ADDR_DW0,
1986 1987 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
1987 1988 RT2860_WRITE(sc, RT2860_MAC_ADDR_DW1,
1988 1989 addr[4] | addr[5] << 8);
1989 1990 }
1990 1991
1991 1992 /*
1992 1993 * Send a command to the 8051 microcontroller unit.
1993 1994 */
1994 1995 static int
1995 1996 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg)
1996 1997 {
1997 1998 int ntries;
1998 1999
1999 2000 for (ntries = 0; ntries < 100; ntries++) {
2000 2001 if (!(RT2860_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY))
2001 2002 break;
2002 2003 DELAY(2);
2003 2004 }
2004 2005 if (ntries == 100)
2005 2006 return (EIO);
2006 2007
2007 2008 RT2860_WRITE(sc, RT2860_H2M_MAILBOX,
2008 2009 RT2860_H2M_BUSY | RT2860_TOKEN_NO_INTR << 16 | arg);
2009 2010 RT2860_WRITE(sc, RT2860_HOST_CMD, cmd);
2010 2011
2011 2012 return (RT2860_SUCCESS);
2012 2013 }
2013 2014
2014 2015 /*
2015 2016 * Reading and writing from/to the BBP is different from RT2560 and RT2661.
2016 2017 * We access the BBP through the 8051 microcontroller unit which means that
2017 2018 * the microcode must be loaded first.
2018 2019 */
2019 2020 static uint8_t
2020 2021 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg)
2021 2022 {
2022 2023 uint32_t val;
2023 2024 int ntries;
2024 2025
2025 2026 for (ntries = 0; ntries < 100; ntries++) {
2026 2027 if (!(RT2860_READ(sc,
2027 2028 RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK))
2028 2029 break;
2029 2030 DELAY(1);
2030 2031 }
2031 2032 if (ntries == 100) {
2032 2033 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_mcu_bbp_read():"
2033 2034 "could not read from BBP through MCU\n");
2034 2035 return (0);
2035 2036 }
2036 2037
2037 2038 RT2860_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL |
2038 2039 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8);
2039 2040
2040 2041 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0);
2041 2042 DELAY(1000);
2042 2043
2043 2044 for (ntries = 0; ntries < 100; ntries++) {
2044 2045 val = RT2860_READ(sc, RT2860_H2M_BBPAGENT);
2045 2046 if (!(val & RT2860_BBP_CSR_KICK))
2046 2047 return (val & 0xff);
2047 2048 DELAY(1);
2048 2049 }
2049 2050 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_mcu_bbp_read():"
2050 2051 "could not read from BBP through MCU\n");
2051 2052
2052 2053 return (0);
2053 2054 }
2054 2055
2055 2056 static void
2056 2057 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)
2057 2058 {
2058 2059 int ntries;
2059 2060
2060 2061 for (ntries = 0; ntries < 100; ntries++) {
2061 2062 if (!(RT2860_READ(sc,
2062 2063 RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK))
2063 2064 break;
2064 2065 DELAY(1);
2065 2066 }
2066 2067 if (ntries == 100) {
2067 2068 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_mcu_bbp_write():"
2068 2069 "could not write to BBP through MCU\n");
2069 2070 return;
2070 2071 }
2071 2072
2072 2073 RT2860_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL |
2073 2074 RT2860_BBP_CSR_KICK | reg << 8 | val);
2074 2075
2075 2076 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0);
2076 2077 DELAY(1000);
2077 2078 }
2078 2079
2079 2080 static int
2080 2081 rt2860_bbp_init(struct rt2860_softc *sc)
2081 2082 {
2082 2083 int i, ntries;
2083 2084
2084 2085 /* wait for BBP to wake up */
2085 2086 for (ntries = 0; ntries < 20; ntries++) {
2086 2087 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0);
2087 2088 if (bbp0 != 0 && bbp0 != 0xff)
2088 2089 break;
2089 2090 }
2090 2091 if (ntries == 20) {
2091 2092 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_bbp_init():"
2092 2093 "timeout waiting for BBP to wake up\n");
2093 2094 return (ETIMEDOUT);
2094 2095 }
2095 2096
2096 2097 /* initialize BBP registers to default values */
2097 2098 for (i = 0; i < 12; i++) {
2098 2099 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg,
2099 2100 rt2860_def_bbp[i].val);
2100 2101 }
2101 2102
2102 2103 /* fix BBP69 and BBP73 for RT2860C */
2103 2104 if (sc->mac_rev == 0x28600100) {
2104 2105 rt2860_mcu_bbp_write(sc, 69, 0x16);
2105 2106 rt2860_mcu_bbp_write(sc, 73, 0x12);
2106 2107 }
2107 2108
2108 2109 return (0);
2109 2110 }
2110 2111
2111 2112 static void
2112 2113 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val)
2113 2114 {
2114 2115 uint32_t tmp;
2115 2116 int ntries;
2116 2117
2117 2118 for (ntries = 0; ntries < 100; ntries++) {
2118 2119 if (!(RT2860_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL))
2119 2120 break;
2120 2121 DELAY(1);
2121 2122 }
2122 2123 if (ntries == 100) {
2123 2124 RWN_DEBUG(RT2860_DBG_FW, "rwn: rwn_init()"
2124 2125 "could not write to RF\n");
2125 2126 return;
2126 2127 }
2127 2128
2128 2129 /* RF registers are 24-bit on the RT2860 */
2129 2130 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT |
2130 2131 (val & 0x3fffff) << 2 | (reg & 3);
2131 2132 RT2860_WRITE(sc, RT2860_RF_CSR_CFG0, tmp);
2132 2133 }
2133 2134
2134 2135 static void
2135 2136 rt2860_select_chan_group(struct rt2860_softc *sc, int group)
2136 2137 {
2137 2138 uint32_t tmp;
2138 2139
2139 2140 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]);
2140 2141 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]);
2141 2142 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]);
2142 2143 rt2860_mcu_bbp_write(sc, 82, (group == 0) ? 0x62 : 0xf2);
2143 2144
2144 2145 tmp = RT2860_READ(sc, RT2860_TX_BAND_CFG);
2145 2146 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P);
2146 2147 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P;
2147 2148 RT2860_WRITE(sc, RT2860_TX_BAND_CFG, tmp);
2148 2149
2149 2150 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */
2150 2151 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN;
2151 2152 if (group == 0) { /* 2GHz */
2152 2153 tmp |= RT2860_PA_PE_G0_EN | RT2860_LNA_PE_G0_EN;
2153 2154 if (sc->ntxchains > 1)
2154 2155 tmp |= RT2860_PA_PE_G1_EN;
2155 2156 if (sc->nrxchains > 1)
2156 2157 tmp |= RT2860_LNA_PE_G1_EN;
2157 2158 } else { /* 5GHz */
2158 2159 tmp |= RT2860_PA_PE_A0_EN | RT2860_LNA_PE_A0_EN;
2159 2160 if (sc->ntxchains > 1)
2160 2161 tmp |= RT2860_PA_PE_A1_EN;
2161 2162 if (sc->nrxchains > 1)
2162 2163 tmp |= RT2860_LNA_PE_A1_EN;
2163 2164 }
2164 2165 RT2860_WRITE(sc, RT2860_TX_PIN_CFG, tmp);
2165 2166
2166 2167 rt2860_mcu_bbp_write(sc, 66, 0x2e + sc->lna[group]);
2167 2168 }
2168 2169 static void
2169 2170 rt2860_set_chan(struct rt2860_softc *sc, struct ieee80211_channel *c)
2170 2171 {
2171 2172 struct ieee80211com *ic = &sc->sc_ic;
2172 2173 const struct rfprog *rfprog = rt2860_rf2850;
2173 2174 uint_t i, chan, group;
2174 2175 uint8_t txpow1, txpow2;
2175 2176 uint32_t r2, r3, r4;
2176 2177
2177 2178 chan = ieee80211_chan2ieee(ic, c);
2178 2179 if (chan == 0 || chan == IEEE80211_CHAN_ANY) {
2179 2180 RWN_DEBUG(RT2860_DBG_FW, "Unkonwn channel!\n");
2180 2181 return;
2181 2182 }
2182 2183
2183 2184 /* find the settings for this channel (we know it exists) */
2184 2185 for (i = 0; rfprog[i].chan != chan; )
2185 2186 i++;
2186 2187
2187 2188 r2 = rfprog[i].r2;
2188 2189 if (sc->ntxchains == 1)
2189 2190 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */
2190 2191 if (sc->nrxchains == 1)
2191 2192 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */
2192 2193 else if (sc->nrxchains == 2)
2193 2194 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */
2194 2195
2195 2196 /* use Tx power values from EEPROM */
2196 2197 txpow1 = sc->txpow1[i];
2197 2198 txpow2 = sc->txpow2[i];
2198 2199 if (IEEE80211_IS_CHAN_5GHZ(c)) {
2199 2200 txpow1 = txpow1 << 1 | 1;
2200 2201 txpow2 = txpow2 << 1 | 1;
2201 2202 }
2202 2203 r3 = rfprog[i].r3 | txpow1 << 7;
2203 2204 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4;
2204 2205
2205 2206 rt2860_rf_write(sc, RAL_RF1, rfprog[i].r1);
2206 2207 rt2860_rf_write(sc, RAL_RF2, r2);
2207 2208 rt2860_rf_write(sc, RAL_RF3, r3);
2208 2209 rt2860_rf_write(sc, RAL_RF4, r4);
2209 2210
2210 2211 DELAY(200);
2211 2212
2212 2213 rt2860_rf_write(sc, RAL_RF1, rfprog[i].r1);
2213 2214 rt2860_rf_write(sc, RAL_RF2, r2);
2214 2215 rt2860_rf_write(sc, RAL_RF3, r3 | 1);
2215 2216 rt2860_rf_write(sc, RAL_RF4, r4);
2216 2217
2217 2218 DELAY(200);
2218 2219
2219 2220 rt2860_rf_write(sc, RAL_RF1, rfprog[i].r1);
2220 2221 rt2860_rf_write(sc, RAL_RF2, r2);
2221 2222 rt2860_rf_write(sc, RAL_RF3, r3);
2222 2223 rt2860_rf_write(sc, RAL_RF4, r4);
2223 2224
2224 2225 /* 802.11a uses a 16 microseconds short interframe space */
2225 2226 sc->sifs = IEEE80211_IS_CHAN_5GHZ(c) ? 16 : 10;
2226 2227
2227 2228 /* determine channel group */
2228 2229 if (chan <= 14)
2229 2230 group = 0;
2230 2231 else if (chan <= 64)
2231 2232 group = 1;
2232 2233 else if (chan <= 128)
2233 2234 group = 2;
2234 2235 else
2235 2236 group = 3;
2236 2237
2237 2238 /* XXX necessary only when group has changed! */
2238 2239 rt2860_select_chan_group(sc, group);
2239 2240
2240 2241 DELAY(1000);
2241 2242 }
2242 2243
2243 2244 static void
2244 2245 rt2860_updateprot(struct ieee80211com *ic)
2245 2246 {
2246 2247 struct rt2860_softc *sc = (struct rt2860_softc *)ic;
2247 2248 uint32_t tmp;
2248 2249
2249 2250 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL;
2250 2251 /* setup protection frame rate (MCS code) */
2251 2252 tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ? 0 : 3;
2252 2253
2253 2254 /* CCK frames don't require protection */
2254 2255 RT2860_WRITE(sc, RT2860_CCK_PROT_CFG, tmp);
2255 2256
2256 2257 if (ic->ic_flags & IEEE80211_F_USEPROT) {
2257 2258 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
2258 2259 tmp |= RT2860_PROT_CTRL_RTS_CTS;
2259 2260 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
2260 2261 tmp |= RT2860_PROT_CTRL_CTS;
2261 2262 }
2262 2263 RT2860_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp);
2263 2264 }
2264 2265
2265 2266 static void
2266 2267 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which)
2267 2268 {
2268 2269 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS,
2269 2270 which | (sc->leds & 0x7f));
2270 2271 }
2271 2272
2272 2273 static int
2273 2274 rt2860_init(struct rt2860_softc *sc)
2274 2275 {
2275 2276 #define N(a) (sizeof (a) / sizeof ((a)[0]))
2276 2277 struct ieee80211com *ic;
2277 2278 int i, err, qid, ridx, ntries;
2278 2279 uint8_t bbp1, bbp3;
2279 2280 uint32_t tmp;
2280 2281
2281 2282 ic = &sc->sc_ic;
2282 2283
2283 2284 rt2860_stop(sc);
2284 2285 tmp = RT2860_READ(sc, RT2860_WPDMA_GLO_CFG);
2285 2286 tmp &= 0xff0;
2286 2287 RT2860_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp | RT2860_TX_WB_DDONE);
2287 2288
2288 2289 RT2860_WRITE(sc, RT2860_WPDMA_RST_IDX, 0xffffffff);
2289 2290
2290 2291 /* PBF hardware reset */
2291 2292 RT2860_WRITE(sc, RT2860_SYS_CTRL, 0xe1f);
2292 2293 RT2860_WRITE(sc, RT2860_SYS_CTRL, 0xe00);
2293 2294
2294 2295 if (!(sc->sc_flags & RT2860_FWLOADED)) {
2295 2296 if ((err = rt2860_load_microcode(sc)) != 0) {
2296 2297 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_init(): "
2297 2298 "could not load 8051 microcode\n");
2298 2299 rt2860_stop(sc);
2299 2300 return (err);
2300 2301 }
2301 2302 RT2860_GLOCK(sc);
2302 2303 sc->sc_flags |= RT2860_FWLOADED;
2303 2304 RT2860_GUNLOCK(sc);
2304 2305 }
2305 2306
2306 2307 rt2860_set_macaddr(sc, ic->ic_macaddr);
2307 2308
2308 2309 /* init Tx power for all Tx rates (from EEPROM) */
2309 2310 for (ridx = 0; ridx < 5; ridx++) {
2310 2311 if (sc->txpow20mhz[ridx] == 0xffffffff)
2311 2312 continue;
2312 2313 RT2860_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]);
2313 2314 }
2314 2315
2315 2316 for (ntries = 0; ntries < 100; ntries++) {
2316 2317 tmp = RT2860_READ(sc, RT2860_WPDMA_GLO_CFG);
2317 2318 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
2318 2319 break;
2319 2320 DELAY(1000);
2320 2321 }
2321 2322 if (ntries == 100) {
2322 2323 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rt2860_init():"
2323 2324 "timeout waiting for DMA engine\n");
2324 2325 rt2860_stop(sc);
2325 2326 return (ETIMEDOUT);
2326 2327 }
2327 2328 tmp &= 0xff0;
2328 2329 RT2860_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp | RT2860_TX_WB_DDONE);
2329 2330
2330 2331 /* reset Rx ring and all 6 Tx rings */
2331 2332 RT2860_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f);
2332 2333
2333 2334 /* PBF hardware reset */
2334 2335 RT2860_WRITE(sc, RT2860_SYS_CTRL, 0xe1f);
2335 2336 RT2860_WRITE(sc, RT2860_SYS_CTRL, 0xe00);
2336 2337
2337 2338 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL,
2338 2339 RT2860_BBP_HRST | RT2860_MAC_SRST);
2339 2340 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL, 0);
2340 2341
2341 2342 for (i = 0; i < N(rt2860_def_mac); i++)
2342 2343 RT2860_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val);
2343 2344
2344 2345 /* wait while MAC is busy */
2345 2346 for (ntries = 0; ntries < 100; ntries++) {
2346 2347 if (!(RT2860_READ(sc, RT2860_MAC_STATUS_REG) &
2347 2348 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY)))
2348 2349 break;
2349 2350 DELAY(1000);
2350 2351 }
2351 2352 if (ntries == 100) {
2352 2353 RWN_DEBUG(RT2860_DBG_FW, "rwn: rt2860_init():"
2353 2354 "timeout waiting for MAC\n");
2354 2355 rt2860_stop(sc);
2355 2356 return (ETIMEDOUT);
2356 2357 }
2357 2358
2358 2359 /* clear Host to MCU mailbox */
2359 2360 RT2860_WRITE(sc, RT2860_H2M_BBPAGENT, 0);
2360 2361 RT2860_WRITE(sc, RT2860_H2M_MAILBOX, 0);
2361 2362
2362 2363 if ((err = rt2860_bbp_init(sc)) != 0) {
2363 2364 rt2860_stop(sc);
2364 2365 return (err);
2365 2366 }
2366 2367
2367 2368 /* init Tx rings (4 EDCAs + HCCA + Mgt) */
2368 2369 for (qid = 0; qid < 6; qid++) {
2369 2370 RT2860_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr);
2370 2371 RT2860_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT);
2371 2372 RT2860_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0);
2372 2373 }
2373 2374
2374 2375 /* init Rx ring */
2375 2376 RT2860_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr);
2376 2377 RT2860_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT);
2377 2378 RT2860_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1);
2378 2379
2379 2380 /* setup maximum buffer sizes */
2380 2381 RT2860_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 |
2381 2382 (sc->sc_dmabuf_size - sizeof (struct rt2860_rxwi) - 2));
2382 2383
2383 2384 for (ntries = 0; ntries < 100; ntries++) {
2384 2385 tmp = RT2860_READ(sc, RT2860_WPDMA_GLO_CFG);
2385 2386 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
2386 2387 break;
2387 2388 DELAY(1000);
2388 2389 }
2389 2390 if (ntries == 100) {
2390 2391 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rt2860_init():"
2391 2392 "timeout waiting for DMA engine\n");
2392 2393 rt2860_stop(sc);
2393 2394 return (ETIMEDOUT);
2394 2395 }
2395 2396 tmp &= 0xff0;
2396 2397 RT2860_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp | RT2860_TX_WB_DDONE);
2397 2398
2398 2399 /* disable interrupts mitigation */
2399 2400 RT2860_WRITE(sc, RT2860_DELAY_INT_CFG, 0);
2400 2401
2401 2402 /* write vendor-specific BBP values (from EEPROM) */
2402 2403 for (i = 0; i < 8; i++) {
2403 2404 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff)
2404 2405 continue;
2405 2406 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);
2406 2407 }
2407 2408
2408 2409 /* send LEDs operating mode to microcontroller */
2409 2410 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0]);
2410 2411 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1]);
2411 2412 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2]);
2412 2413
2413 2414 /* disable non-existing Rx chains */
2414 2415 bbp3 = rt2860_mcu_bbp_read(sc, 3);
2415 2416 bbp3 &= ~(1 << 3 | 1 << 4);
2416 2417 if (sc->nrxchains == 2)
2417 2418 bbp3 |= 1 << 3;
2418 2419 else if (sc->nrxchains == 3)
2419 2420 bbp3 |= 1 << 4;
2420 2421 rt2860_mcu_bbp_write(sc, 3, bbp3);
2421 2422
2422 2423 /* disable non-existing Tx chains */
2423 2424 bbp1 = rt2860_mcu_bbp_read(sc, 1);
2424 2425 if (sc->ntxchains == 1)
2425 2426 bbp1 &= ~(1 << 3 | 1 << 4);
2426 2427 rt2860_mcu_bbp_write(sc, 1, bbp1);
2427 2428
2428 2429 /* select default channel */
2429 2430 rt2860_set_chan(sc, ic->ic_curchan);
2430 2431
2431 2432 /* XXX not clear what the following 8051 command does.. */
2432 2433 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BOOT, 0);
2433 2434
2434 2435 /* set RTS threshold */
2435 2436 tmp = RT2860_READ(sc, RT2860_TX_RTS_CFG);
2436 2437 tmp &= ~0xffff00;
2437 2438 tmp |= ic->ic_rtsthreshold << 8;
2438 2439
2439 2440 /* setup initial protection mode */
2440 2441 sc->sc_ic_flags = ic->ic_flags;
2441 2442 rt2860_updateprot(ic);
2442 2443
2443 2444 /* enable Tx/Rx DMA engine */
2444 2445 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN);
2445 2446 for (ntries = 0; ntries < 200; ntries++) {
2446 2447 tmp = RT2860_READ(sc, RT2860_WPDMA_GLO_CFG);
2447 2448 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
2448 2449 break;
2449 2450 DELAY(1000);
2450 2451 }
2451 2452 if (ntries == 200) {
2452 2453 RWN_DEBUG(RT2860_DBG_DMA, "rwn: rt2860_int():"
2453 2454 "timeout waiting for DMA engine\n");
2454 2455 rt2860_stop(sc);
2455 2456 return (ETIMEDOUT);
2456 2457 }
2457 2458
2458 2459 DELAY(50);
2459 2460
2460 2461 tmp |= RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN |
2461 2462 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT;
2462 2463 RT2860_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
2463 2464
2464 2465 /* turn radio LED on */
2465 2466 rt2860_set_leds(sc, RT2860_LED_RADIO);
2466 2467
2467 2468 /* set Rx filter */
2468 2469 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR;
2469 2470 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2470 2471 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL |
2471 2472 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK |
2472 2473 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV |
2473 2474 RT2860_DROP_CFACK | RT2860_DROP_CFEND;
2474 2475 if (ic->ic_opmode == IEEE80211_M_STA)
2475 2476 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL;
2476 2477 }
2477 2478 RT2860_WRITE(sc, RT2860_RX_FILTR_CFG, tmp);
2478 2479
2479 2480 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL,
2480 2481 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
2481 2482
2482 2483 /* clear pending interrupts */
2483 2484 RT2860_WRITE(sc, RT2860_INT_STATUS, 0xffffffff);
2484 2485 /* enable interrupts */
2485 2486 RT2860_WRITE(sc, RT2860_INT_MASK, 0x3fffc);
2486 2487
2487 2488 if (sc->sc_flags & RT2860_ADVANCED_PS)
2488 2489 (void) rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel);
2489 2490
2490 2491 return (DDI_SUCCESS);
2491 2492 }
2492 2493
2493 2494 static int
2494 2495 rt2860_quiesce(dev_info_t *dip)
2495 2496 {
2496 2497 struct rt2860_softc *sc;
2497 2498
2498 2499 sc = ddi_get_soft_state(rt2860_soft_state_p, ddi_get_instance(dip));
2499 2500 if (sc == NULL)
2500 2501 return (DDI_FAILURE);
2501 2502
2502 2503 #ifdef DEBUG
2503 2504 rt2860_dbg_flags = 0;
2504 2505 #endif
2505 2506
2506 2507 /*
2507 2508 * No more blocking is allowed while we are in quiesce(9E) entry point
2508 2509 */
2509 2510 sc->sc_flags |= RT2860_F_QUIESCE;
2510 2511
2511 2512 /*
2512 2513 * Disable and mask all interrupts
2513 2514 */
2514 2515 rt2860_stop(sc);
2515 2516 return (DDI_SUCCESS);
2516 2517 }
2517 2518
2518 2519 static void
2519 2520 rt2860_stop(struct rt2860_softc *sc)
2520 2521 {
2521 2522 int qid;
2522 2523 uint32_t tmp;
2523 2524
2524 2525 /* by pass if it's quiesced */
2525 2526 if (!(sc->sc_flags & RT2860_F_QUIESCE))
2526 2527 RT2860_GLOCK(sc);
2527 2528 if (sc->sc_flags == RT2860_F_RUNNING)
2528 2529 rt2860_set_leds(sc, 0); /* turn all LEDs off */
2529 2530 sc->sc_tx_timer = 0;
2530 2531 /* by pass if it's quiesced */
2531 2532 if (!(sc->sc_flags & RT2860_F_QUIESCE))
2532 2533 RT2860_GUNLOCK(sc);
2533 2534
2534 2535 /* clear RX WCID search table */
2535 2536 rt2860_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512);
2536 2537 /* clear pairwise key table */
2537 2538 rt2860_set_region_4(sc, RT2860_PKEY(0), 0, 2048);
2538 2539 /* clear IV/EIV table */
2539 2540 rt2860_set_region_4(sc, RT2860_IVEIV(0), 0, 512);
2540 2541 /* clear WCID attribute table */
2541 2542 rt2860_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 256);
2542 2543 /* clear shared key table */
2543 2544 rt2860_set_region_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32);
2544 2545 /* clear shared key mode */
2545 2546 rt2860_set_region_4(sc, RT2860_SKEY_MODE_0_7, 0, 4);
2546 2547
2547 2548 /* disable interrupts */
2548 2549 RT2860_WRITE(sc, RT2860_INT_MASK, 0);
2549 2550
2550 2551 /* disable Rx */
2551 2552 tmp = RT2860_READ(sc, RT2860_MAC_SYS_CTRL);
2552 2553 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
2553 2554 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp);
2554 2555
2555 2556 /* reset adapter */
2556 2557 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL,
2557 2558 RT2860_BBP_HRST | RT2860_MAC_SRST);
2558 2559 RT2860_WRITE(sc, RT2860_MAC_SYS_CTRL, 0);
2559 2560
2560 2561 /* reset Tx and Rx rings (and reclaim TXWIs) */
2561 2562 for (qid = 0; qid < 6; qid++)
2562 2563 rt2860_reset_tx_ring(sc, &sc->txq[qid]);
2563 2564 rt2860_reset_rx_ring(sc, &sc->rxq);
2564 2565
2565 2566 /* by pass if it's quiesced */
2566 2567 if (!(sc->sc_flags & RT2860_F_QUIESCE))
2567 2568 RT2860_GLOCK(sc);
2568 2569 sc->sc_flags &= ~RT2860_UPD_BEACON;
2569 2570 /* by pass if it's quiesced */
2570 2571 if (!(sc->sc_flags & RT2860_F_QUIESCE))
2571 2572 RT2860_GUNLOCK(sc);
2572 2573 }
2573 2574
2574 2575 static int
2575 2576 rt2860_m_start(void *arg)
2576 2577 {
2577 2578 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2578 2579 struct ieee80211com *ic = &sc->sc_ic;
2579 2580 int err;
2580 2581
2581 2582 err = rt2860_init(sc);
2582 2583 if (err != DDI_SUCCESS) {
2583 2584 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_m_start():"
2584 2585 "Hardware initialization failed\n");
2585 2586 goto fail1;
2586 2587 }
2587 2588
2588 2589 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
2589 2590
2590 2591 RT2860_GLOCK(sc);
2591 2592 sc->sc_flags |= RT2860_F_RUNNING;
2592 2593 RT2860_GUNLOCK(sc);
2593 2594
2594 2595 return (err);
2595 2596 fail1:
2596 2597 rt2860_stop(sc);
2597 2598 return (err);
2598 2599 }
2599 2600
2600 2601 static void
2601 2602 rt2860_m_stop(void *arg)
2602 2603 {
2603 2604 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2604 2605
2605 2606 (void) rt2860_stop(sc);
2606 2607
2607 2608 ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1);
2608 2609
2609 2610 RT2860_GLOCK(sc);
2610 2611 sc->sc_flags &= ~RT2860_F_RUNNING;
2611 2612 RT2860_GUNLOCK(sc);
2612 2613 }
2613 2614
2614 2615 static void
2615 2616 rt2860_m_ioctl(void* arg, queue_t *wq, mblk_t *mp)
2616 2617 {
2617 2618 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2618 2619 struct ieee80211com *ic = &sc->sc_ic;
2619 2620 int err;
2620 2621
2621 2622 err = ieee80211_ioctl(ic, wq, mp);
2622 2623 RT2860_GLOCK(sc);
2623 2624 if (err == ENETRESET) {
2624 2625 if (ic->ic_des_esslen) {
2625 2626 if (RT2860_IS_RUNNING(sc)) {
2626 2627 RT2860_GUNLOCK(sc);
2627 2628 (void) rt2860_init(sc);
2628 2629 (void) ieee80211_new_state(ic,
2629 2630 IEEE80211_S_SCAN, -1);
2630 2631 RT2860_GLOCK(sc);
2631 2632 }
2632 2633 }
2633 2634 }
2634 2635 RT2860_GUNLOCK(sc);
2635 2636 }
2636 2637
2637 2638 /*
2638 2639 * Call back function for get/set proporty
2639 2640 */
2640 2641 static int
2641 2642 rt2860_m_getprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
2642 2643 uint_t wldp_length, void *wldp_buf)
2643 2644 {
2644 2645 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2645 2646 int err = 0;
2646 2647
2647 2648 err = ieee80211_getprop(&sc->sc_ic, pr_name, wldp_pr_num,
2648 2649 wldp_length, wldp_buf);
2649 2650
2650 2651 return (err);
2651 2652 }
2652 2653
2653 2654 static void
2654 2655 rt2860_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
2655 2656 mac_prop_info_handle_t prh)
2656 2657 {
2657 2658 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2658 2659
2659 2660 ieee80211_propinfo(&sc->sc_ic, pr_name, wldp_pr_num, prh);
2660 2661 }
2661 2662
2662 2663 static int
2663 2664 rt2860_m_setprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
2664 2665 uint_t wldp_length, const void *wldp_buf)
2665 2666 {
2666 2667 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2667 2668 ieee80211com_t *ic = &sc->sc_ic;
2668 2669 int err;
2669 2670
2670 2671 err = ieee80211_setprop(ic, pr_name, wldp_pr_num, wldp_length,
2671 2672 wldp_buf);
2672 2673 RT2860_GLOCK(sc);
2673 2674 if (err == ENETRESET) {
2674 2675 if (ic->ic_des_esslen) {
2675 2676 if (RT2860_IS_RUNNING(sc)) {
2676 2677 RT2860_GUNLOCK(sc);
2677 2678 (void) rt2860_init(sc);
2678 2679 (void) ieee80211_new_state(ic,
2679 2680 IEEE80211_S_SCAN, -1);
2680 2681 RT2860_GLOCK(sc);
2681 2682 }
2682 2683 }
2683 2684 err = 0;
2684 2685 }
2685 2686 RT2860_GUNLOCK(sc);
2686 2687 return (err);
2687 2688 }
2688 2689
2689 2690 static mblk_t *
2690 2691 rt2860_m_tx(void *arg, mblk_t *mp)
2691 2692 {
2692 2693 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2693 2694 struct ieee80211com *ic = &sc->sc_ic;
2694 2695 mblk_t *next;
2695 2696
2696 2697 if (RT2860_IS_SUSPEND(sc)) {
2697 2698 freemsgchain(mp);
2698 2699 return (NULL);
2699 2700 }
2700 2701
2701 2702 /*
2702 2703 * No data frames go out unless we're associated; this
2703 2704 * should not happen as the 802.11 layer does not enable
2704 2705 * the xmit queue until we enter the RUN state.
2705 2706 */
2706 2707 if (ic->ic_state != IEEE80211_S_RUN) {
2707 2708 RWN_DEBUG(RT2860_DBG_TX, "rwn: rt2860_tx_data(): "
2708 2709 "discard, state %u\n", ic->ic_state);
2709 2710 freemsgchain(mp);
2710 2711 return (NULL);
2711 2712 }
2712 2713
2713 2714 while (mp != NULL) {
2714 2715 next = mp->b_next;
2715 2716 mp->b_next = NULL;
2716 2717 if (rt2860_send(ic, mp, IEEE80211_FC0_TYPE_DATA) !=
2717 2718 DDI_SUCCESS) {
2718 2719 mp->b_next = next;
2719 2720 break;
2720 2721 }
2721 2722 mp = next;
2722 2723 }
2723 2724 return (mp);
2724 2725 }
2725 2726
2726 2727 /*ARGSUSED*/
2727 2728 static int
2728 2729 rt2860_m_unicst(void *arg, const uint8_t *macaddr)
2729 2730 {
2730 2731 return (ENOTSUP);
2731 2732 }
2732 2733
2733 2734 /*ARGSUSED*/
2734 2735 static int
2735 2736 rt2860_m_multicst(void *arg, boolean_t add, const uint8_t *mca)
2736 2737 {
2737 2738 return (ENOTSUP);
2738 2739 }
2739 2740
2740 2741 /*ARGSUSED*/
2741 2742 static int
2742 2743 rt2860_m_promisc(void *arg, boolean_t on)
2743 2744 {
2744 2745 return (0);
2745 2746 }
2746 2747
2747 2748 static int
2748 2749 rt2860_m_stat(void *arg, uint_t stat, uint64_t *val)
2749 2750 {
2750 2751 struct rt2860_softc *sc = (struct rt2860_softc *)arg;
2751 2752 ieee80211com_t *ic = &sc->sc_ic;
2752 2753 ieee80211_node_t *ni = ic->ic_bss;
2753 2754 struct ieee80211_rateset *rs = &ni->in_rates;
2754 2755
2755 2756 RT2860_GLOCK(sc);
2756 2757 switch (stat) {
2757 2758 case MAC_STAT_IFSPEED:
2758 2759 *val = ((ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) ?
2759 2760 (rs->ir_rates[ni->in_txrate] & IEEE80211_RATE_VAL)
2760 2761 : ic->ic_fixed_rate) / 2 * 1000000;
2761 2762 break;
2762 2763 case MAC_STAT_NOXMTBUF:
2763 2764 *val = sc->sc_tx_nobuf;
2764 2765 break;
2765 2766 case MAC_STAT_NORCVBUF:
2766 2767 *val = sc->sc_rx_nobuf;
2767 2768 break;
2768 2769 case MAC_STAT_IERRORS:
2769 2770 *val = sc->sc_rx_err;
2770 2771 break;
2771 2772 case MAC_STAT_RBYTES:
2772 2773 *val = ic->ic_stats.is_rx_bytes;
2773 2774 break;
2774 2775 case MAC_STAT_IPACKETS:
2775 2776 *val = ic->ic_stats.is_rx_frags;
2776 2777 break;
2777 2778 case MAC_STAT_OBYTES:
2778 2779 *val = ic->ic_stats.is_tx_bytes;
2779 2780 break;
2780 2781 case MAC_STAT_OPACKETS:
2781 2782 *val = ic->ic_stats.is_tx_frags;
2782 2783 break;
2783 2784 case MAC_STAT_OERRORS:
2784 2785 case WIFI_STAT_TX_FAILED:
2785 2786 *val = sc->sc_tx_err;
2786 2787 break;
2787 2788 case WIFI_STAT_TX_RETRANS:
2788 2789 *val = sc->sc_tx_retries;
2789 2790 break;
2790 2791 case WIFI_STAT_FCS_ERRORS:
2791 2792 case WIFI_STAT_WEP_ERRORS:
2792 2793 case WIFI_STAT_TX_FRAGS:
2793 2794 case WIFI_STAT_MCAST_TX:
2794 2795 case WIFI_STAT_RTS_SUCCESS:
2795 2796 case WIFI_STAT_RTS_FAILURE:
2796 2797 case WIFI_STAT_ACK_FAILURE:
2797 2798 case WIFI_STAT_RX_FRAGS:
2798 2799 case WIFI_STAT_MCAST_RX:
2799 2800 case WIFI_STAT_RX_DUPS:
2800 2801 RT2860_GUNLOCK(sc);
2801 2802 return (ieee80211_stat(ic, stat, val));
2802 2803 default:
2803 2804 RT2860_GUNLOCK(sc);
2804 2805 return (ENOTSUP);
2805 2806 }
2806 2807 RT2860_GUNLOCK(sc);
2807 2808
2808 2809 return (0);
2809 2810 }
2810 2811
2811 2812 static int
2812 2813 rt2860_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
2813 2814 {
2814 2815 struct rt2860_softc *sc;
2815 2816 struct ieee80211com *ic;
2816 2817 int i, err, qid, ntries, instance;
2817 2818 uint8_t cachelsz;
2818 2819 uint16_t command, vendor_id, device_id;
2819 2820 char strbuf[32];
2820 2821 wifi_data_t wd = { 0 };
2821 2822 mac_register_t *macp;
2822 2823
2823 2824 switch (cmd) {
2824 2825 case DDI_ATTACH:
2825 2826 break;
2826 2827 case DDI_RESUME:
2827 2828 sc = ddi_get_soft_state(rt2860_soft_state_p,
2828 2829 ddi_get_instance(devinfo));
2829 2830 ASSERT(sc != NULL);
2830 2831 RT2860_GLOCK(sc);
2831 2832 sc->sc_flags &= ~RT2860_F_SUSPEND;
2832 2833 RT2860_GUNLOCK(sc);
2833 2834 if (RT2860_IS_RUNNING(sc))
2834 2835 (void) rt2860_init(sc);
2835 2836 RWN_DEBUG(RT2860_DBG_RESUME, "rwn: rt2860_attach(): "
2836 2837 "resume now\n");
2837 2838 return (DDI_SUCCESS);
2838 2839 default:
2839 2840 return (DDI_FAILURE);
2840 2841 }
2841 2842
2842 2843 instance = ddi_get_instance(devinfo);
2843 2844
2844 2845 err = ddi_soft_state_zalloc(rt2860_soft_state_p, instance);
2845 2846 if (err != DDI_SUCCESS) {
2846 2847 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2847 2848 "unable to alloc soft_state_p\n");
2848 2849 return (err);
2849 2850 }
2850 2851
2851 2852 sc = ddi_get_soft_state(rt2860_soft_state_p, instance);
2852 2853 ic = (ieee80211com_t *)&sc->sc_ic;
2853 2854 sc->sc_dev = devinfo;
2854 2855
2855 2856 /* pci configuration */
2856 2857 err = ddi_regs_map_setup(devinfo, 0, &sc->sc_cfg_base, 0, 0,
2857 2858 &rwn_csr_accattr, &sc->sc_cfg_handle);
2858 2859 if (err != DDI_SUCCESS) {
2859 2860 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2860 2861 "ddi_regs_map_setup() failed");
2861 2862 goto fail1;
2862 2863 }
2863 2864
2864 2865 cachelsz = ddi_get8(sc->sc_cfg_handle,
2865 2866 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_CACHE_LINESZ));
2866 2867 if (cachelsz == 0)
2867 2868 cachelsz = 0x10;
2868 2869 sc->sc_cachelsz = cachelsz << 2;
2869 2870 sc->sc_dmabuf_size = roundup(IEEE80211_MAX_LEN, sc->sc_cachelsz);
2870 2871
2871 2872 vendor_id = ddi_get16(sc->sc_cfg_handle,
2872 2873 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_VENID));
2873 2874 device_id = ddi_get16(sc->sc_cfg_handle,
2874 2875 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_DEVID));
2875 2876 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2876 2877 "vendor 0x%x, device id 0x%x, cache size %d\n",
2877 2878 vendor_id, device_id, cachelsz);
2878 2879
2879 2880 /*
2880 2881 * Enable response to memory space accesses,
2881 2882 * and enabe bus master.
2882 2883 */
2883 2884 command = PCI_COMM_MAE | PCI_COMM_ME;
2884 2885 ddi_put16(sc->sc_cfg_handle,
2885 2886 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_COMM),
2886 2887 command);
2887 2888 ddi_put8(sc->sc_cfg_handle,
2888 2889 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_LATENCY_TIMER), 0xa8);
2889 2890 ddi_put8(sc->sc_cfg_handle,
2890 2891 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_ILINE), 0x10);
2891 2892
2892 2893 /* pci i/o space */
2893 2894 err = ddi_regs_map_setup(devinfo, 1,
2894 2895 &sc->sc_io_base, 0, 0, &rwn_csr_accattr, &sc->sc_io_handle);
2895 2896 if (err != DDI_SUCCESS) {
2896 2897 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2897 2898 "ddi_regs_map_setup() failed");
2898 2899 goto fail2;
2899 2900 }
2900 2901 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2901 2902 "PCI configuration is done successfully\n");
2902 2903
2903 2904 sc->amrr.amrr_min_success_threshold = 1;
2904 2905 sc->amrr.amrr_max_success_threshold = 15;
2905 2906
2906 2907 /* wait for NIC to initialize */
2907 2908 for (ntries = 0; ntries < 100; ntries++) {
2908 2909 sc->mac_rev = RT2860_READ(sc, RT2860_ASIC_VER_ID);
2909 2910 if (sc->mac_rev != 0 && sc->mac_rev != 0xffffffff)
2910 2911 break;
2911 2912 DELAY(10);
2912 2913 }
2913 2914 if (ntries == 100) {
2914 2915 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2915 2916 "timeout waiting for NIC initialize\n");
2916 2917 return (DDI_FAILURE);
2917 2918 }
2918 2919
2919 2920 if ((sc->mac_rev >> 16) != 0x2860 &&
2920 2921 (device_id == PRODUCT_RALINK_RT2890 ||
2921 2922 device_id == PRODUCT_RALINK_RT2790 ||
2922 2923 device_id == PRODUCT_AWT_RT2890))
2923 2924 sc->sc_flags |= RT2860_ADVANCED_PS;
2924 2925
2925 2926 /* retrieve RF rev. no and various other things from EEPROM */
2926 2927 (void) rt2860_read_eeprom(sc);
2927 2928 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2928 2929 "MAC/BBP RT%X (rev 0x%04X), RF %s (%dT%dR)\n",
2929 2930 sc->mac_rev >> 16, sc->mac_rev & 0xffff,
2930 2931 rt2860_get_rf(sc->rf_rev), sc->ntxchains, sc->nrxchains);
2931 2932
2932 2933 /*
2933 2934 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings.
2934 2935 */
2935 2936 for (qid = 0; qid < 6; qid++) {
2936 2937 if ((err = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) {
2937 2938 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2938 2939 "could not allocate Tx ring %d\n", qid);
2939 2940 goto fail3;
2940 2941 }
2941 2942 }
2942 2943
2943 2944 if ((err = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) {
2944 2945 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2945 2946 "could not allocte Rx ring\n");
2946 2947 goto fail4;
2947 2948 }
2948 2949
2949 2950 if ((err = rt2860_alloc_tx_pool(sc)) != 0) {
2950 2951 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
2951 2952 "could not allocte Tx pool\n");
2952 2953 goto fail5;
2953 2954 }
2954 2955
2955 2956 mutex_init(&sc->sc_genlock, NULL, MUTEX_DRIVER, NULL);
2956 2957 mutex_init(&sc->sc_txlock, NULL, MUTEX_DRIVER, NULL);
2957 2958 mutex_init(&sc->sc_rxlock, NULL, MUTEX_DRIVER, NULL);
2958 2959
2959 2960 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */
2960 2961 sc->mgtqid = (sc->mac_rev == 0x28600100) ? EDCA_AC_VO : 5;
2961 2962 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach():"
2962 2963 "mgtqid = %x\n", sc->mgtqid);
2963 2964
2964 2965 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
2965 2966 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
2966 2967 ic->ic_state = IEEE80211_S_INIT;
2967 2968
2968 2969 /* set device capabilities */
2969 2970 ic->ic_caps =
2970 2971 IEEE80211_C_TXPMGT | /* tx power management */
2971 2972 IEEE80211_C_SHPREAMBLE | /* short preamble supported */
2972 2973 IEEE80211_C_SHSLOT; /* short slot time supported */
2973 2974
2974 2975 /* WPA/WPA2 support */
2975 2976 ic->ic_caps |= IEEE80211_C_WPA; /* Support WPA/WPA2 */
2976 2977
2977 2978 /* set supported .11b and .11g rates */
2978 2979 ic->ic_sup_rates[IEEE80211_MODE_11B] = rt2860_rateset_11b;
2979 2980 ic->ic_sup_rates[IEEE80211_MODE_11G] = rt2860_rateset_11g;
2980 2981
2981 2982 /* set supported .11b and .11g channels (1 through 14) */
2982 2983 for (i = 1; i <= 14; i++) {
2983 2984 ic->ic_sup_channels[i].ich_freq =
2984 2985 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
2985 2986 ic->ic_sup_channels[i].ich_flags =
2986 2987 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM |
2987 2988 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ;
2988 2989 }
2989 2990
2990 2991 ic->ic_maxrssi = 63;
2991 2992 ic->ic_xmit = rt2860_send;
2992 2993
2993 2994 ieee80211_attach(ic);
2994 2995
2995 2996 /* register WPA door */
2996 2997 ieee80211_register_door(ic, ddi_driver_name(devinfo),
2997 2998 ddi_get_instance(devinfo));
2998 2999
2999 3000 /* override state transition machine */
3000 3001 sc->sc_newstate = ic->ic_newstate;
3001 3002 ic->ic_newstate = rt2860_newstate;
3002 3003 ieee80211_media_init(ic);
3003 3004 ic->ic_def_txkey = 0;
3004 3005
3005 3006 err = ddi_add_softintr(devinfo, DDI_SOFTINT_LOW,
3006 3007 &sc->sc_softintr_hdl, NULL, 0, rt2860_softintr, (caddr_t)sc);
3007 3008 if (err != DDI_SUCCESS) {
3008 3009 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
3009 3010 "ddi_add_softintr() failed");
3010 3011 goto fail8;
3011 3012 }
3012 3013
3013 3014 err = ddi_get_iblock_cookie(devinfo, 0, &sc->sc_iblock);
3014 3015 if (err != DDI_SUCCESS) {
3015 3016 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
3016 3017 "Can not get iblock cookie for INT\n");
3017 3018 goto fail7;
3018 3019 }
3019 3020
3020 3021 err = ddi_add_intr(devinfo, 0, NULL, NULL, rt2860_intr, (caddr_t)sc);
3021 3022 if (err != DDI_SUCCESS) {
3022 3023 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
3023 3024 "unable to add device interrupt handler\n");
3024 3025 goto fail7;
3025 3026 }
3026 3027
3027 3028 /*
3028 3029 * Provide initial settings for the WiFi plugin; whenever this
3029 3030 * information changes, we need to call mac_plugindata_update()
3030 3031 */
3031 3032 wd.wd_opmode = ic->ic_opmode;
3032 3033 wd.wd_secalloc = WIFI_SEC_NONE;
3033 3034 IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_bss->in_bssid);
3034 3035
3035 3036 if ((macp = mac_alloc(MAC_VERSION)) == NULL) {
3036 3037 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
3037 3038 "MAC version mismatch\n");
3038 3039 goto fail9;
3039 3040 }
3040 3041
3041 3042 macp->m_type_ident = MAC_PLUGIN_IDENT_WIFI;
3042 3043 macp->m_driver = sc;
3043 3044 macp->m_dip = devinfo;
3044 3045 macp->m_src_addr = ic->ic_macaddr;
3045 3046 macp->m_callbacks = &rt2860_m_callbacks;
3046 3047 macp->m_min_sdu = 0;
3047 3048 macp->m_max_sdu = IEEE80211_MTU;
3048 3049 macp->m_pdata = &wd;
3049 3050 macp->m_pdata_size = sizeof (wd);
3050 3051
3051 3052 err = mac_register(macp, &ic->ic_mach);
3052 3053 mac_free(macp);
3053 3054 if (err != 0) {
3054 3055 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach(): "
3055 3056 "mac_register err %x\n", err);
3056 3057 goto fail9;
3057 3058 }
3058 3059
3059 3060 /*
3060 3061 * Create minor node of type DDI_NT_NET_WIFI
3061 3062 */
3062 3063 (void) snprintf(strbuf, sizeof (strbuf), "%s%d",
3063 3064 "rwn", instance);
3064 3065 err = ddi_create_minor_node(devinfo, strbuf, S_IFCHR,
3065 3066 instance + 1, DDI_NT_NET_WIFI, 0);
3066 3067
3067 3068 /*
3068 3069 * Notify link is down now
3069 3070 */
3070 3071 mac_link_update(ic->ic_mach, LINK_STATE_DOWN);
3071 3072
3072 3073 sc->sc_flags &= ~RT2860_F_RUNNING;
3073 3074
3074 3075 RWN_DEBUG(RT2860_DBG_MSG, "rwn: rt2860_attach() successfully.\n");
3075 3076 return (DDI_SUCCESS);
3076 3077 fail9:
3077 3078 ddi_remove_softintr(sc->sc_softintr_hdl);
3078 3079 fail8:
3079 3080 ddi_remove_intr(devinfo, 0, sc->sc_iblock);
3080 3081 fail7:
3081 3082 mutex_destroy(&sc->sc_genlock);
3082 3083 mutex_destroy(&sc->sc_txlock);
3083 3084 mutex_destroy(&sc->sc_rxlock);
3084 3085 fail6:
3085 3086 rt2860_free_tx_pool(sc);
3086 3087 fail5:
3087 3088 rt2860_free_rx_ring(sc, &sc->rxq);
3088 3089 fail4:
3089 3090 while (--qid >= 0)
3090 3091 rt2860_free_tx_ring(sc, &sc->txq[qid]);
3091 3092 fail3:
3092 3093 ddi_regs_map_free(&sc->sc_io_handle);
3093 3094 fail2:
3094 3095 ddi_regs_map_free(&sc->sc_cfg_handle);
3095 3096 fail1:
3096 3097 return (err);
3097 3098 }
3098 3099
3099 3100 static int
3100 3101 rt2860_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
3101 3102 {
3102 3103 struct rt2860_softc *sc;
3103 3104 int qid;
3104 3105
3105 3106 sc = ddi_get_soft_state(rt2860_soft_state_p, ddi_get_instance(devinfo));
3106 3107
3107 3108 switch (cmd) {
3108 3109 case DDI_DETACH:
3109 3110 break;
3110 3111 case DDI_SUSPEND:
3111 3112 if (RT2860_IS_RUNNING(sc))
3112 3113 rt2860_stop(sc);
3113 3114 RT2860_GLOCK(sc);
3114 3115 sc->sc_flags &= ~RT2860_FWLOADED;
3115 3116 sc->sc_flags |= RT2860_F_SUSPEND;
3116 3117 RT2860_GUNLOCK(sc);
3117 3118 RWN_DEBUG(RT2860_DBG_RESUME, "rwn: rt2860_detach(): "
3118 3119 "suspend now\n");
3119 3120 return (DDI_SUCCESS);
3120 3121 default:
3121 3122 return (DDI_FAILURE);
3122 3123 }
3123 3124
3124 3125 if (mac_disable(sc->sc_ic.ic_mach) != 0)
3125 3126 return (DDI_FAILURE);
3126 3127
3127 3128 rt2860_stop(sc);
3128 3129
3129 3130 /*
3130 3131 * Unregister from the MAC layer subsystem
3131 3132 */
3132 3133 (void) mac_unregister(sc->sc_ic.ic_mach);
3133 3134
3134 3135 ddi_remove_intr(devinfo, 0, sc->sc_iblock);
3135 3136 ddi_remove_softintr(sc->sc_softintr_hdl);
3136 3137
3137 3138 /*
3138 3139 * detach ieee80211 layer
3139 3140 */
3140 3141 ieee80211_detach(&sc->sc_ic);
3141 3142
3142 3143 rt2860_free_tx_pool(sc);
3143 3144 rt2860_free_rx_ring(sc, &sc->rxq);
3144 3145 for (qid = 0; qid < 6; qid++)
3145 3146 rt2860_free_tx_ring(sc, &sc->txq[qid]);
3146 3147
3147 3148 ddi_regs_map_free(&sc->sc_io_handle);
3148 3149
3149 3150 mutex_destroy(&sc->sc_genlock);
3150 3151 mutex_destroy(&sc->sc_txlock);
3151 3152 mutex_destroy(&sc->sc_rxlock);
3152 3153
3153 3154 ddi_remove_minor_node(devinfo, NULL);
3154 3155 ddi_soft_state_free(rt2860_soft_state_p, ddi_get_instance(devinfo));
3155 3156
3156 3157 return (DDI_SUCCESS);
3157 3158 }
3158 3159
3159 3160 int
3160 3161 _info(struct modinfo *modinfop)
3161 3162 {
3162 3163 return (mod_info(&modlinkage, modinfop));
3163 3164 }
3164 3165
3165 3166 int
3166 3167 _init(void)
3167 3168 {
3168 3169 int status;
3169 3170
3170 3171 status = ddi_soft_state_init(&rt2860_soft_state_p,
3171 3172 sizeof (struct rt2860_softc), 1);
3172 3173 if (status != 0)
3173 3174 return (status);
3174 3175
3175 3176 mac_init_ops(&rwn_dev_ops, "rwn");
3176 3177 status = mod_install(&modlinkage);
3177 3178 if (status != 0) {
3178 3179 mac_fini_ops(&rwn_dev_ops);
3179 3180 ddi_soft_state_fini(&rt2860_soft_state_p);
3180 3181 }
3181 3182 return (status);
3182 3183 }
3183 3184
3184 3185 int
3185 3186 _fini(void)
3186 3187 {
3187 3188 int status;
3188 3189
3189 3190 status = mod_remove(&modlinkage);
3190 3191 if (status == 0) {
3191 3192 mac_fini_ops(&rwn_dev_ops);
3192 3193 ddi_soft_state_fini(&rt2860_soft_state_p);
3193 3194 }
3194 3195 return (status);
3195 3196 }
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