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212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
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          --- old/usr/src/uts/common/io/atge/atge_l1e_reg.h
          +++ new/usr/src/uts/common/io/atge/atge_l1e_reg.h
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  12   12   *
  13   13   * When distributing Covered Code, include this CDDL HEADER in each
  14   14   * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15   15   * If applicable, add the following below this CDDL HEADER, with the
  16   16   * fields enclosed by brackets "[]" replaced with your own identifying
  17   17   * information: Portions Copyright [yyyy] [name of copyright owner]
  18   18   *
  19   19   * CDDL HEADER END
  20   20   */
  21   21  /*
       22 + * Copyright (c) 2012 Gary Mills
       23 + *
  22   24   * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  23   25   * Use is subject to license terms.
  24   26   */
  25   27  
  26   28  #ifndef _ATGE_L1E_REG_H
  27   29  #define _ATGE_L1E_REG_H
  28   30  
  29   31  #ifdef __cplusplus
  30   32          extern "C" {
  31   33  #endif
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  41   43          uint32_t        length;
  42   44          uint32_t        flags;
  43   45          uint32_t        vtags;
  44   46  } rx_rs_t;
  45   47  
  46   48  typedef struct  rx_cmb {
  47   49          uint32_t        cmb[L1E_RX_PAGES];
  48   50  } rx_cmb_t;
  49   51  #pragma pack()
  50   52  
       53 +/* Master configuration */
       54 +#define L1E_MASTER_CFG                  0x1400
       55 +#define L1E_MASTER_RESET                0x00000001
       56 +#define L1E_MASTER_MTIMER_ENB           0x00000002
       57 +#define L1E_MASTER_IM_TX_TIMER_ENB      0x00000004
       58 +#define L1E_MASTER_MANUAL_INT_ENB       0x00000008
       59 +#define L1E_MASTER_IM_RX_TIMER_ENB      0x00000020
       60 +#define L1E_MASTER_CHIP_REV_MASK        0x00FF0000
       61 +#define L1E_MASTER_CHIP_ID_MASK         0xFF000000
       62 +#define L1E_MASTER_CHIP_REV_SHIFT       16
       63 +#define L1E_MASTER_CHIP_ID_SHIFT        24
       64 +
       65 +
  51   66  /*
  52   67   * DMA CFG registers (L1E specific).
  53   68   */
  54   69  #define DMA_CFG_RD_REQ_PRI              0x00000400
  55      -#define DMA_CFG_RD_DELAY_CNT_MASK       0x0000F800
  56      -#define DMA_CFG_WR_DELAY_CNT_MASK       0x000F0000
  57   70  #define DMA_CFG_TXCMB_ENB               0x00100000
  58      -#define DMA_CFG_RXCMB_ENB               0x00200000
  59   71  #define DMA_CFG_RD_BURST_MASK           0x07
  60   72  #define DMA_CFG_RD_BURST_SHIFT          4
  61   73  #define DMA_CFG_WR_BURST_MASK           0x07
  62   74  #define DMA_CFG_WR_BURST_SHIFT          7
  63      -#define DMA_CFG_RD_DELAY_CNT_SHIFT      11
  64      -#define DMA_CFG_WR_DELAY_CNT_SHIFT      16
  65      -#define DMA_CFG_RD_DELAY_CNT_DEFAULT    15
  66      -#define DMA_CFG_WR_DELAY_CNT_DEFAULT    4
  67   75  
  68   76  #define L1E_TX_RING_CNT_MIN             32
  69   77  #define L1E_TX_RING_CNT_MAX             1020
  70   78  #define L1E_TX_RING_ALIGN               8
  71   79  #define L1E_RX_PAGE_ALIGN               32
  72   80  #define L1E_CMB_ALIGN                   32
  73   81  #define L1E_MAX_FRAMELEN                ETHERMAX
  74   82  
  75   83  #define L1E_RX_PAGE_SZ_MIN              (8 * 1024)
  76   84  #define L1E_RX_PAGE_SZ_MAX              (1024 * 1024)
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