1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26 #ifndef _ATGE_L1E_REG_H
27 #define _ATGE_L1E_REG_H
28
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32
33 /*
34 * Number of RX Rings (or pages) we use.
35 */
36 #define L1E_RX_PAGES 2
37
38 #pragma pack(1)
39 typedef struct rx_rs {
40 uint32_t seqno;
41 uint32_t length;
42 uint32_t flags;
43 uint32_t vtags;
44 } rx_rs_t;
45
46 typedef struct rx_cmb {
47 uint32_t cmb[L1E_RX_PAGES];
48 } rx_cmb_t;
49 #pragma pack()
50
51 /*
52 * DMA CFG registers (L1E specific).
53 */
54 #define DMA_CFG_RD_REQ_PRI 0x00000400
55 #define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800
56 #define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000
57 #define DMA_CFG_TXCMB_ENB 0x00100000
58 #define DMA_CFG_RXCMB_ENB 0x00200000
59 #define DMA_CFG_RD_BURST_MASK 0x07
60 #define DMA_CFG_RD_BURST_SHIFT 4
61 #define DMA_CFG_WR_BURST_MASK 0x07
62 #define DMA_CFG_WR_BURST_SHIFT 7
63 #define DMA_CFG_RD_DELAY_CNT_SHIFT 11
64 #define DMA_CFG_WR_DELAY_CNT_SHIFT 16
65 #define DMA_CFG_RD_DELAY_CNT_DEFAULT 15
66 #define DMA_CFG_WR_DELAY_CNT_DEFAULT 4
67
68 #define L1E_TX_RING_CNT_MIN 32
69 #define L1E_TX_RING_CNT_MAX 1020
70 #define L1E_TX_RING_ALIGN 8
71 #define L1E_RX_PAGE_ALIGN 32
72 #define L1E_CMB_ALIGN 32
73 #define L1E_MAX_FRAMELEN ETHERMAX
74
75 #define L1E_RX_PAGE_SZ_MIN (8 * 1024)
76 #define L1E_RX_PAGE_SZ_MAX (1024 * 1024)
77 #define L1E_RX_FRAMES_PAGE 128
78 #define L1E_RX_PAGE_SZ \
79 (ROUNDUP(L1E_MAX_FRAMELEN, L1E_RX_PAGE_ALIGN) * L1E_RX_FRAMES_PAGE)
80 #define L1E_TX_CMB_SZ (sizeof (uint32_t))
81 #define L1E_RX_CMB_SZ (sizeof (uint32_t))
82
83 #define L1E_PROC_MAX \
84 ((L1E_RX_PAGE_SZ * L1E_RX_PAGES) / ETHERMAX)
85 #define L1E_PROC_DEFAULT (L1E_PROC_MAX / 4)
86
87 #define L1E_INTRS \
88 (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \
89 INTR_RX_PKT | INTR_TX_PKT | INTR_RX_FIFO_OFLOW | \
90 INTR_TX_FIFO_UNDERRUN | INTR_SMB)
91
92 #define L1E_RSS_IDT_TABLE0 0x1560
93 #define L1E_RSS_CPU 0x157C
94
95 #define L1E_SRAM_RX_FIFO_LEN 0x1524
96
97 #define L1E_PHY_STATUS 0x1418
98 #define PHY_STATUS_100M 0x00020000
99
100 #define L1E_SMB_STAT_TIMER 0x15C4
101
102 #define GPHY_CTRL_EXT_RESET 0x0001
103 #define GPHY_CTRL_PIPE_MOD 0x0002
104 #define GPHY_CTRL_BERT_START 0x0010
105 #define GPHY_CTRL_GL1E_25M_ENB 0x0020
106 #define GPHY_CTRL_LPW_EXIT 0x0040
107 #define GPHY_CTRL_PHY_IDDQ 0x0080
108 #define GPHY_CTRL_PHY_IDDQ_DIS 0x0100
109 #define GPHY_CTRL_PCLK_SEL_DIS 0x0200
110 #define GPHY_CTRL_HIB_EN 0x0400
111 #define GPHY_CTRL_HIB_PULSE 0x0800
112 #define GPHY_CTRL_SEL_ANA_RESET 0x1000
113 #define GPHY_CTRL_PHY_PLL_ON 0x2000
114 #define GPHY_CTRL_PWDOWN_HW 0x4000
115
116 #define RXF_VALID 0x01
117
118 #define L1E_RXF0_PAGE0 0x15F4
119 #define L1E_RXF0_PAGE1 0x15F5
120
121 #define L1E_RXF0_PAGE0_ADDR_LO 0x1544
122 #define L1E_RXF0_PAGE1_ADDR_LO 0x1548
123
124 #define L1E_RXF_PAGE_SIZE 0x1558
125
126 #define L1E_INT_TRIG_THRESH 0x15C8
127 #define INT_TRIG_TX_THRESH_MASK 0x0000FFFF
128 #define INT_TRIG_RX_THRESH_MASK 0xFFFF0000
129 #define INT_TRIG_TX_THRESH_SHIFT 0
130 #define INT_TRIG_RX_THRESH_SHIFT 16
131
132 #define L1E_INT_TRIG_TIMER 0x15CC
133 #define INT_TRIG_TX_TIMER_MASK 0x0000FFFF
134 #define INT_TRIG_RX_TIMER_MASK 0x0000FFFF
135 #define INT_TRIG_TX_TIMER_SHIFT 0
136 #define INT_TRIG_RX_TIMER_SHIFT 16
137
138 #define TX_COALSC_PKT_1e 0x15C8 /* W: L1E */
139 #define RX_COALSC_PKT_1e 0x15CA /* W: L1E */
140 #define TX_COALSC_TO_1e 0x15CC /* W: L1E */
141 #define RX_COALSC_TO_1e 0x15CE /* W: L1E */
142
143 #define L1E_HOST_RXF0_PAGEOFF 0x1800
144 #define L1E_TPD_CONS_IDX 0x1804
145 #define L1E_HOST_RXF1_PAGEOFF 0x1808
146 #define L1E_HOST_RXF2_PAGEOFF 0x180C
147 #define L1E_HOST_RXF3_PAGEOFF 0x1810
148 #define L1E_RXF0_CMB0_ADDR_LO 0x1820
149 #define L1E_RXF0_CMB1_ADDR_LO 0x1824
150 #define L1E_RXF1_CMB0_ADDR_LO 0x1828
151 #define L1E_RXF1_CMB1_ADDR_LO 0x182C
152 #define L1E_RXF2_CMB0_ADDR_LO 0x1830
153 #define L1E_RXF2_CMB1_ADDR_LO 0x1834
154 #define L1E_RXF3_CMB0_ADDR_LO 0x1838
155 #define L1E_RXF3_CMB1_ADDR_LO 0x183C
156 #define L1E_TX_CMB_ADDR_LO 0x1840
157 #define L1E_SMB_ADDR_LO 0x1844
158
159 #define L1E_RD_SEQNO_MASK 0x0000FFFF
160 #define L1E_RD_HASH_MASK 0xFFFF0000
161 #define L1E_RD_SEQNO_SHIFT 0
162 #define L1E_RD_HASH_SHIFT 16
163 #define L1E_RX_SEQNO(x) \
164 (((x) & L1E_RD_SEQNO_MASK) >> L1E_RD_SEQNO_SHIFT)
165 #define L1E_RD_CSUM_MASK 0x0000FFFF
166 #define L1E_RD_LEN_MASK 0x3FFF0000
167 #define L1E_RD_CPU_MASK 0xC0000000
168 #define L1E_RD_CSUM_SHIFT 0
169 #define L1E_RD_LEN_SHIFT 16
170 #define L1E_RD_CPU_SHIFT 30
171 #define L1E_RX_CSUM(x) \
172 (((x) & L1E_RD_CSUM_MASK) >> L1E_RD_CSUM_SHIFT)
173 #define L1E_RX_BYTES(x) \
174 (((x) & L1E_RD_LEN_MASK) >> L1E_RD_LEN_SHIFT)
175 #define L1E_RX_CPU(x) \
176 (((x) & L1E_RD_CPU_MASK) >> L1E_RD_CPU_SHIFT)
177
178 #define L1E_RD_RSS_IPV4 0x00000001
179 #define L1E_RD_RSS_IPV4_TCP 0x00000002
180 #define L1E_RD_RSS_IPV6 0x00000004
181 #define L1E_RD_RSS_IPV6_TCP 0x00000008
182 #define L1E_RD_IPV6 0x00000010
183 #define L1E_RD_IPV4_FRAG 0x00000020
184 #define L1E_RD_IPV4_DF 0x00000040
185 #define L1E_RD_802_3 0x00000080
186 #define L1E_RD_VLAN 0x00000100
187 #define L1E_RD_ERROR 0x00000200
188 #define L1E_RD_IPV4 0x00000400
189 #define L1E_RD_UDP 0x00000800
190 #define L1E_RD_TCP 0x00001000
191 #define L1E_RD_BCAST 0x00002000
192 #define L1E_RD_MCAST 0x00004000
193 #define L1E_RD_PAUSE 0x00008000
194 #define L1E_RD_CRC 0x00010000
195 #define L1E_RD_CODE 0x00020000
196 #define L1E_RD_DRIBBLE 0x00040000
197 #define L1E_RD_RUNT 0x00080000
198 #define L1E_RD_OFLOW 0x00100000
199 #define L1E_RD_TRUNC 0x00200000
200 #define L1E_RD_IPCSUM_NOK 0x00400000
201 #define L1E_RD_TCP_UDPCSUM_NOK 0x00800000
202 #define L1E_RD_LENGTH_NOK 0x01000000
203 #define L1E_RD_DES_ADDR_FILTERED 0x02000000
204
205 /* TX descriptor fields */
206 #define L1E_TD_VLAN_MASK 0xFFFF0000
207 #define L1E_TD_PKT_INT 0x00008000
208 #define L1E_TD_DMA_INT 0x00004000
209 #define L1E_TD_VLAN_SHIFT 16
210 #define L1E_TX_VLAN_TAG(x) \
211 (((x) << 4) | ((x) >> 13) | (((x) >> 9) & 8))
212 #define L1E_TD_BUFLEN_SHIFT 0
213 #define L1E_TD_MSS 0xFFF80000
214 #define L1E_TD_TSO_HDR 0x00040000
215 #define L1E_TD_TCPHDR_LEN 0x0003C000
216 #define L1E_TD_IPHDR_LEN 0x00003C00
217 #define L1E_TD_IPV6HDR_LEN2 0x00003C00
218 #define L1E_TD_LLC_SNAP 0x00000200
219 #define L1E_TD_VLAN_TAGGED 0x00000100
220 #define L1E_TD_UDPCSUM 0x00000080
221 #define L1E_TD_TCPCSUM 0x00000040
222 #define L1E_TD_IPCSUM 0x00000020
223 #define L1E_TD_IPV6HDR_LEN1 0x000000E0
224 #define L1E_TD_TSO 0x00000010
225 #define L1E_TD_CXSUM 0x00000008
226 #define L1E_TD_INSERT_VLAN_TAG 0x00000004
227 #define L1E_TD_IPV6 0x00000002
228
229 #define L1E_TD_CSUM_PLOADOFFSET 0x00FF0000
230 #define L1E_TD_CSUM_XSUMOFFSET 0xFF000000
231 #define L1E_TD_CSUM_XSUMOFFSET_SHIFT 24
232 #define L1E_TD_CSUM_PLOADOFFSET_SHIFT 16
233 #define L1E_TD_MSS_SHIFT 19
234 #define L1E_TD_TCPHDR_LEN_SHIFT 14
235 #define L1E_TD_IPHDR_LEN_SHIFT 10
236
237 #define L1E_JUMBO_FRAMELEN 8132
238
239 #define L1E_TX_JUMBO_THRESH 0x1584
240 #define TX_JUMBO_THRESH_MASK 0x000007FF
241 #define TX_JUMBO_THRESH_SHIFT 0
242 #define TX_JUMBO_THRESH_UNIT 8
243 #define TX_JUMBO_THRESH_UNIT_SHIFT 3
244
245 /*
246 * Statistics counters collected by the MAC.
247 * AR81xx requires register access to get MAC statistics
248 * and the format of statistics seems to be the same of L1
249 * except for tx_abort field in TX stats. So keep it separate for simplicity.
250 */
251 #define L1E_RX_MIB_BASE 0x1700
252 #define L1E_TX_MIB_BASE 0x1760
253
254 #pragma pack(1)
255 typedef struct smb {
256 /* Rx stats. */
257 uint32_t rx_frames;
258 uint32_t rx_bcast_frames;
259 uint32_t rx_mcast_frames;
260 uint32_t rx_pause_frames;
261 uint32_t rx_control_frames;
262 uint32_t rx_crcerrs;
263 uint32_t rx_lenerrs;
264 uint32_t rx_bytes;
265 uint32_t rx_runts;
266 uint32_t rx_fragments;
267 uint32_t rx_pkts_64;
268 uint32_t rx_pkts_65_127;
269 uint32_t rx_pkts_128_255;
270 uint32_t rx_pkts_256_511;
271 uint32_t rx_pkts_512_1023;
272 uint32_t rx_pkts_1024_1518;
273 uint32_t rx_pkts_1519_max;
274 uint32_t rx_pkts_truncated;
275 uint32_t rx_fifo_oflows;
276 uint32_t rx_rrs_errs;
277 uint32_t rx_alignerrs;
278 uint32_t rx_bcast_bytes;
279 uint32_t rx_mcast_bytes;
280 uint32_t rx_pkts_filtered;
281 /* Tx stats. */
282 uint32_t tx_frames;
283 uint32_t tx_bcast_frames;
284 uint32_t tx_mcast_frames;
285 uint32_t tx_pause_frames;
286 uint32_t tx_excess_defer;
287 uint32_t tx_control_frames;
288 uint32_t tx_deferred;
289 uint32_t tx_bytes;
290 uint32_t tx_pkts_64;
291 uint32_t tx_pkts_65_127;
292 uint32_t tx_pkts_128_255;
293 uint32_t tx_pkts_256_511;
294 uint32_t tx_pkts_512_1023;
295 uint32_t tx_pkts_1024_1518;
296 uint32_t tx_pkts_1519_max;
297 uint32_t tx_single_colls;
298 uint32_t tx_multi_colls;
299 uint32_t tx_late_colls;
300 uint32_t tx_excess_colls;
301 uint32_t tx_abort;
302 uint32_t tx_underrun;
303 uint32_t tx_desc_underrun;
304 uint32_t tx_lenerrs;
305 uint32_t tx_pkts_truncated;
306 uint32_t tx_bcast_bytes;
307 uint32_t tx_mcast_bytes;
308 } atge_l1e_smb_t;
309 #pragma pack()
310
311 #ifdef __cplusplus
312 }
313 #endif
314
315 #endif /* _ATGE_L1E_REG_H */