3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
24 * Use is subject to license terms.
25 */
26
27 #include <sys/types.h>
28 #include <sys/stream.h>
29 #include <sys/strsun.h>
30 #include <sys/stat.h>
31 #include <sys/modctl.h>
32 #include <sys/ethernet.h>
33 #include <sys/debug.h>
34 #include <sys/conf.h>
35 #include <sys/mii.h>
36 #include <sys/miiregs.h>
37 #include <sys/sysmacros.h>
38 #include <sys/dditypes.h>
39 #include <sys/ddi.h>
40 #include <sys/sunddi.h>
41 #include <sys/byteorder.h>
42 #include <sys/note.h>
384 /* Tell hardware that we're ready to load DMA blocks. */
385 OUTL(atgep, ATGE_DMA_BLOCK, DMA_BLOCK_LOAD);
386
387 /* Set Rx/Tx interrupt trigger threshold. */
388 OUTL(atgep, L1E_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) |
389 (4 << INT_TRIG_TX_THRESH_SHIFT));
390
391 /*
392 * Set interrupt trigger timer, its purpose and relation
393 * with interrupt moderation mechanism is not clear yet.
394 */
395 OUTL(atgep, L1E_INT_TRIG_TIMER,
396 ((ATGE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) |
397 (ATGE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT)));
398
399 reg = ATGE_USECS(ATGE_IM_RX_TIMER_DEFAULT) << IM_TIMER_RX_SHIFT;
400 reg |= ATGE_USECS(ATGE_IM_TX_TIMER_DEFAULT) << IM_TIMER_TX_SHIFT;
401 OUTL(atgep, ATGE_IM_TIMER, reg);
402
403 reg = INL(atgep, ATGE_MASTER_CFG);
404 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
405 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
406 reg |= MASTER_IM_RX_TIMER_ENB;
407 reg |= MASTER_IM_TX_TIMER_ENB;
408 OUTL(atgep, ATGE_MASTER_CFG, reg);
409
410 OUTW(atgep, RX_COALSC_PKT_1e, 0);
411 OUTW(atgep, RX_COALSC_TO_1e, 0);
412 OUTW(atgep, TX_COALSC_PKT_1e, 1);
413 OUTW(atgep, TX_COALSC_TO_1e, 4000/2); /* 4mS */
414 }
415
416 mblk_t *
417 atge_l1e_receive(atge_t *atgep)
418 {
419 atge_l1e_data_t *l1e;
420 atge_dma_t *dma_rx_page;
421 atge_dma_t *dma_rx_cmb;
422 uint32_t *ptr;
423 uint32_t cons, current_page;
424 uchar_t *pageaddr, *bufp;
425 rx_rs_t *rs;
426 int prog;
427 uint32_t seqno, len, flags;
|
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2012 Gary Mills
24 *
25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
26 * Use is subject to license terms.
27 */
28
29 #include <sys/types.h>
30 #include <sys/stream.h>
31 #include <sys/strsun.h>
32 #include <sys/stat.h>
33 #include <sys/modctl.h>
34 #include <sys/ethernet.h>
35 #include <sys/debug.h>
36 #include <sys/conf.h>
37 #include <sys/mii.h>
38 #include <sys/miiregs.h>
39 #include <sys/sysmacros.h>
40 #include <sys/dditypes.h>
41 #include <sys/ddi.h>
42 #include <sys/sunddi.h>
43 #include <sys/byteorder.h>
44 #include <sys/note.h>
386 /* Tell hardware that we're ready to load DMA blocks. */
387 OUTL(atgep, ATGE_DMA_BLOCK, DMA_BLOCK_LOAD);
388
389 /* Set Rx/Tx interrupt trigger threshold. */
390 OUTL(atgep, L1E_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) |
391 (4 << INT_TRIG_TX_THRESH_SHIFT));
392
393 /*
394 * Set interrupt trigger timer, its purpose and relation
395 * with interrupt moderation mechanism is not clear yet.
396 */
397 OUTL(atgep, L1E_INT_TRIG_TIMER,
398 ((ATGE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) |
399 (ATGE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT)));
400
401 reg = ATGE_USECS(ATGE_IM_RX_TIMER_DEFAULT) << IM_TIMER_RX_SHIFT;
402 reg |= ATGE_USECS(ATGE_IM_TX_TIMER_DEFAULT) << IM_TIMER_TX_SHIFT;
403 OUTL(atgep, ATGE_IM_TIMER, reg);
404
405 reg = INL(atgep, ATGE_MASTER_CFG);
406 reg &= ~(L1E_MASTER_CHIP_REV_MASK | L1E_MASTER_CHIP_ID_MASK);
407 reg &= ~(L1E_MASTER_IM_RX_TIMER_ENB | L1E_MASTER_IM_TX_TIMER_ENB);
408 reg |= L1E_MASTER_IM_RX_TIMER_ENB;
409 reg |= L1E_MASTER_IM_TX_TIMER_ENB;
410 OUTL(atgep, ATGE_MASTER_CFG, reg);
411
412 OUTW(atgep, RX_COALSC_PKT_1e, 0);
413 OUTW(atgep, RX_COALSC_TO_1e, 0);
414 OUTW(atgep, TX_COALSC_PKT_1e, 1);
415 OUTW(atgep, TX_COALSC_TO_1e, 4000/2); /* 4mS */
416 }
417
418 mblk_t *
419 atge_l1e_receive(atge_t *atgep)
420 {
421 atge_l1e_data_t *l1e;
422 atge_dma_t *dma_rx_page;
423 atge_dma_t *dma_rx_cmb;
424 uint32_t *ptr;
425 uint32_t cons, current_page;
426 uchar_t *pageaddr, *bufp;
427 rx_rs_t *rs;
428 int prog;
429 uint32_t seqno, len, flags;
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