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212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
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--- old/usr/src/uts/common/io/atge/atge_l1_reg.h
+++ new/usr/src/uts/common/io/atge/atge_l1_reg.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 23 * Use is subject to license terms.
24 24 */
25 25
26 26 #ifndef _ATGE_L1_REG_H
27 27 #define _ATGE_L1_REG_H
28 28
29 29 #ifdef __cplusplus
30 30 extern "C" {
31 31 #endif
32 32
33 33 #pragma pack(1)
34 34 typedef struct l1_cmb {
35 35 uint32_t intr_status;
36 36 uint32_t rx_prod_cons;
37 37 uint32_t tx_prod_cons;
38 38 } l1_cmb_t;
39 39
40 40 typedef struct l1_rx_desc {
41 41 uint64_t addr;
42 42 uint32_t len;
43 43 } l1_rx_desc_t;
44 44
45 45 typedef struct l1_rx_rdesc {
46 46 uint32_t index;
47 47 uint32_t len;
48 48 uint32_t flags;
49 49 uint32_t vtags;
50 50 } l1_rx_rdesc_t;
51 51
52 52 /*
53 53 * Statistics counters collected by the MAC
54 54 */
55 55 typedef struct l1_smb {
56 56 /* Rx stats. */
57 57 uint32_t rx_frames;
58 58 uint32_t rx_bcast_frames;
59 59 uint32_t rx_mcast_frames;
60 60 uint32_t rx_pause_frames;
61 61 uint32_t rx_control_frames;
62 62 uint32_t rx_crcerrs;
63 63 uint32_t rx_lenerrs;
64 64 uint32_t rx_bytes;
65 65 uint32_t rx_runts;
66 66 uint32_t rx_fragments;
67 67 uint32_t rx_pkts_64;
68 68 uint32_t rx_pkts_65_127;
69 69 uint32_t rx_pkts_128_255;
70 70 uint32_t rx_pkts_256_511;
71 71 uint32_t rx_pkts_512_1023;
72 72 uint32_t rx_pkts_1024_1518;
73 73 uint32_t rx_pkts_1519_max;
74 74 uint32_t rx_pkts_truncated;
75 75 uint32_t rx_fifo_oflows;
76 76 uint32_t rx_desc_oflows;
77 77 uint32_t rx_alignerrs;
78 78 uint32_t rx_bcast_bytes;
79 79 uint32_t rx_mcast_bytes;
80 80 uint32_t rx_pkts_filtered;
81 81 /* Tx stats. */
82 82 uint32_t tx_frames;
83 83 uint32_t tx_bcast_frames;
84 84 uint32_t tx_mcast_frames;
85 85 uint32_t tx_pause_frames;
86 86 uint32_t tx_excess_defer;
87 87 uint32_t tx_control_frames;
88 88 uint32_t tx_deferred;
89 89 uint32_t tx_bytes;
90 90 uint32_t tx_pkts_64;
91 91 uint32_t tx_pkts_65_127;
92 92 uint32_t tx_pkts_128_255;
93 93 uint32_t tx_pkts_256_511;
94 94 uint32_t tx_pkts_512_1023;
95 95 uint32_t tx_pkts_1024_1518;
96 96 uint32_t tx_pkts_1519_max;
97 97 uint32_t tx_single_colls;
98 98 uint32_t tx_multi_colls;
99 99 uint32_t tx_late_colls;
100 100 uint32_t tx_excess_colls;
101 101 uint32_t tx_underrun;
102 102 uint32_t tx_desc_underrun;
103 103 uint32_t tx_lenerrs;
104 104 uint32_t tx_pkts_truncated;
105 105 uint32_t tx_bcast_bytes;
106 106 uint32_t tx_mcast_bytes;
107 107 uint32_t updated;
108 108 } atge_l1_smb_t;
109 109 #pragma pack()
110 110
111 111 #define L1_RX_RING_CNT 256
112 112 #define L1_RR_RING_CNT (ATGE_TX_RING_CNT + L1_RX_RING_CNT)
113 113
114 114 #define L1_RING_ALIGN 16
115 115 #define L1_TX_RING_ALIGN 16
116 116 #define L1_RX_RING_ALIGN 16
117 117 #define L1_RR_RING_ALIGN 16
118 118 #define L1_CMB_ALIGN 16
119 119 #define L1_SMB_ALIGN 16
120 120
121 121 #define L1_CMB_BLOCK_SZ sizeof (struct l1_cmb)
122 122 #define L1_SMB_BLOCK_SZ sizeof (struct l1_smb)
123 123
124 124 #define L1_RX_RING_SZ \
125 125 (sizeof (struct l1_rx_desc) * L1_RX_RING_CNT)
126 126
127 127 #define L1_RR_RING_SZ \
128 128 (sizeof (struct l1_rx_rdesc) * L1_RR_RING_CNT)
129 129
130 130 /*
131 131 * For RX
132 132 */
133 133 #define L1_RRD_CONS_SHIFT 16
134 134 #define L1_RRD_NSEGS_MASK 0x000000FF
135 135 #define L1_RRD_CONS_MASK 0xFFFF0000
136 136 #define L1_RRD_NSEGS_SHIFT 0
137 137 #define L1_RRD_LEN_MASK 0xFFFF0000
138 138 #define L1_RRD_CSUM_MASK 0x0000FFFF
139 139 #define L1_RRD_CSUM_SHIFT 0
140 140 #define L1_RRD_LEN_SHIFT 16
141 141 #define L1_RRD_ETHERNET 0x00000080
142 142 #define L1_RRD_VLAN 0x00000100
143 143 #define L1_RRD_ERROR 0x00000200
144 144 #define L1_RRD_IPV4 0x00000400
145 145 #define L1_RRD_UDP 0x00000800
146 146 #define L1_RRD_TCP 0x00001000
147 147 #define L1_RRD_BCAST 0x00002000
148 148 #define L1_RRD_MCAST 0x00004000
149 149 #define L1_RRD_PAUSE 0x00008000
150 150 #define L1_RRD_CRC 0x00010000
151 151 #define L1_RRD_CODE 0x00020000
152 152 #define L1_RRD_DRIBBLE 0x00040000
153 153 #define L1_RRD_RUNT 0x00080000
154 154 #define L1_RRD_OFLOW 0x00100000
155 155 #define L1_RRD_TRUNC 0x00200000
156 156 #define L1_RRD_IPCSUM_NOK 0x00400000
157 157 #define L1_RRD_TCP_UDPCSUM_NOK 0x00800000
158 158 #define L1_RRD_LENGTH_NOK 0x01000000
159 159 #define L1_RRD_DES_ADDR_FILTERED 0x02000000
160 160 #define RRD_PROD_MASK 0x0000FFFF
161 161 #define TPD_CONS_MASK 0xFFFF0000
162 162 #define TPD_CONS_SHIFT 16
163 163 #define CMB_UPDATED 0x00000001
164 164 #define RRD_PROD_SHIFT 0
165 165
166 166 /*
167 167 * All descriptors and CMB/SMB share the same high address.
168 168 */
169 169 #define L1_DESC_ADDR_HI 0x1540
170 170 #define L1_DESC_RD_ADDR_LO 0x1544
171 171 #define L1_DESC_RRD_ADDR_LO 0x1548
172 172 #define L1_DESC_TPD_ADDR_LO 0x154C
173 173 #define L1_DESC_CMB_ADDR_LO 0x1550
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174 174 #define L1_DESC_SMB_ADDR_LO 0x1554
175 175 #define L1_DESC_RRD_RD_CNT 0x1558
176 176 #define DESC_RRD_CNT_SHIFT 16
177 177 #define DESC_RRD_CNT_MASK 0x07FF0000
178 178 #define DESC_RD_CNT_SHIFT 0
179 179 #define DESC_RD_CNT_MASK 0x000007FF
180 180
181 181 /*
182 182 * PHY registers.
183 183 */
184 -#define L1_CSMB_CTRL 0x15D0
185 184 #define PHY_CDTS_STAT_OK 0x0000
186 185 #define PHY_CDTS_STAT_SHORT 0x0100
187 186 #define PHY_CDTS_STAT_OPEN 0x0200
188 187 #define PHY_CDTS_STAT_INVAL 0x0300
189 188 #define PHY_CDTS_STAT_MASK 0x0300
190 189
191 190 /*
192 191 * DMA CFG registers (L1 specific)
193 192 */
194 193 #define DMA_CFG_RD_ENB 0x00000400
195 194 #define DMA_CFG_WR_ENB 0x00000800
196 195 #define DMA_CFG_RD_BURST_MASK 0x07
197 196 #define DMA_CFG_RD_BURST_SHIFT 4
198 197 #define DMA_CFG_WR_BURST_MASK 0x07
199 198 #define DMA_CFG_WR_BURST_SHIFT 7
200 199
201 -#define RXQ_CFG_ENB 0x80000000
202 -
203 200 #define L1_RD_LEN_MASK 0x0000FFFF
204 201 #define L1_RD_LEN_SHIFT 0
205 202
206 203 #define L1_SRAM_RD_ADDR 0x1500
207 204 #define L1_SRAM_RD_LEN 0x1504
208 205 #define L1_SRAM_RRD_ADDR 0x1508
209 206 #define L1_SRAM_RRD_LEN 0x150C
210 207 #define L1_SRAM_TPD_ADDR 0x1510
211 208 #define L1_SRAM_TPD_LEN 0x1514
212 209 #define L1_SRAM_TRD_ADDR 0x1518
213 210 #define L1_SRAM_TRD_LEN 0x151C
214 211 #define L1_SRAM_RX_FIFO_ADDR 0x1520
215 212 #define L1_SRAM_RX_FIFO_LEN 0x1524
216 213 #define L1_SRAM_TX_FIFO_ADDR 0x1528
217 214 #define L1_SRAM_TX_FIFO_LEN 0x152C
218 215
219 216 #define RXQ_CFG_RD_BURST_MASK 0x000000FF
220 217 #define RXQ_CFG_RRD_BURST_THRESH_MASK 0x0000FF00
221 218 #define RXQ_CFG_RD_PREF_MIN_IPG_MASK 0x001F0000
222 -#define RXQ_CFG_CUT_THROUGH_ENB 0x40000000
223 -#define RXQ_CFG_ENB 0x80000000
224 219 #define RXQ_CFG_RD_BURST_SHIFT 0
225 220 #define RXQ_CFG_RD_BURST_DEFAULT 8
226 221 #define RXQ_CFG_RRD_BURST_THRESH_SHIFT 8
227 222 #define RXQ_CFG_RRD_BURST_THRESH_DEFAULT 8
228 223 #define RXQ_CFG_RD_PREF_MIN_IPG_SHIFT 16
229 224 #define RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT 1
230 225
231 -#define TXQ_CFG_ENB 0x00000020
232 -#define TXQ_CFG_ENHANCED_MODE 0x00000040
233 226 #define TXQ_CFG_TPD_FETCH_THRESH_MASK 0x00003F00
234 -#define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000
235 -#define TXQ_CFG_TPD_BURST_SHIFT 0
236 -#define TXQ_CFG_TPD_BURST_DEFAULT 4
237 227 #define TXQ_CFG_TPD_FETCH_THRESH_SHIFT 8
238 228 #define TXQ_CFG_TPD_FETCH_DEFAULT 16
239 -#define TXQ_CFG_TX_FIFO_BURST_SHIFT 16
240 -#define TXQ_CFG_TX_FIFO_BURST_DEFAULT 256
241 229
242 230 #define L1_TX_JUMBO_TPD_TH_IPG 0x1584
243 231 #define TX_JUMBO_TPD_TH_MASK 0x000007FF
244 232 #define TX_JUMBO_TPD_IPG_MASK 0x001F0000
245 233 #define TX_JUMBO_TPD_TH_SHIFT 0
246 234 #define TX_JUMBO_TPD_IPG_SHIFT 16
247 235 #define TX_JUMBO_TPD_IPG_DEFAULT 1
248 236
249 237 /* CMB DMA Write Threshold Register */
250 238 #define L1_CMB_WR_THRESH 0x15D4
251 239 #define CMB_WR_THRESH_RRD_MASK 0x000007FF
252 240 #define CMB_WR_THRESH_TPD_MASK 0x07FF0000
253 241 #define CMB_WR_THRESH_RRD_SHIFT 0
254 242 #define CMB_WR_THRESH_RRD_DEFAULT 4
255 243 #define CMB_WR_THRESH_TPD_SHIFT 16
256 244 #define CMB_WR_THRESH_TPD_DEFAULT 4
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257 245
258 246 /* SMB auto DMA timer register */
259 247 #define L1_SMB_TIMER 0x15E4
260 248
261 249 #define L1_CSMB_CTRL 0x15D0
262 250 #define CSMB_CTRL_CMB_KICK 0x00000001
263 251 #define CSMB_CTRL_SMB_KICK 0x00000002
264 252 #define CSMB_CTRL_CMB_ENB 0x00000004
265 253 #define CSMB_CTRL_SMB_ENB 0x00000008
266 254
267 -#define INTR_TX_FIFO_UNDERRUN 0x00000040
268 -#define INTR_RX_FIFO_OFLOW 0x00000008
269 -#define INTR_TX_DMA 0x00040000
270 255 #define INTR_RX_DMA 0x00080000
271 256 #define INTR_CMB_RX 0x00100000
272 257 #define INTR_CMB_TX 0x00200000
273 -#define INTR_MAC_RX 0x00400000
274 -#define INTR_MAC_TX 0x00800000
275 -#define INTR_UNDERRUN 0x01000000
276 -#define INTR_FRAME_ERROR 0x02000000
277 -#define INTR_FRAME_OK 0x04000000
278 -#define INTR_CSUM_ERROR 0x08000000
279 -#define INTR_PHY_LINK_DOWN 0x10000000
280 258 #define INTR_DIS_SMB 0x20000000
281 -#define INTR_DIS_DMA 0x40000000
282 -#define INTR_DIS_INT 0x80000000
283 259
284 260 #define L1_INTRS \
285 261 (INTR_SMB | INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \
286 262 INTR_CMB_TX | INTR_CMB_RX | INTR_RX_FIFO_OFLOW | INTR_TX_FIFO_UNDERRUN)
287 263
288 264 #define L1_RXQ_RRD_PAUSE_THRESH 0x15AC
289 265 #define RXQ_RRD_PAUSE_THRESH_HI_MASK 0x00000FFF
290 266 #define RXQ_RRD_PAUSE_THRESH_LO_MASK 0x0FFF0000
291 267 #define RXQ_RRD_PAUSE_THRESH_HI_SHIFT 0
292 268 #define RXQ_RRD_PAUSE_THRESH_LO_SHIFT 16
293 269
294 270 /* RX/TX count-down timer to trigger CMB-write. */
295 271 #define L1_CMB_WR_TIMER 0x15D8
296 272 #define CMB_WR_TIMER_RX_MASK 0x0000FFFF
297 273 #define CMB_WR_TIMER_TX_MASK 0xFFFF0000
298 274 #define CMB_WR_TIMER_RX_SHIFT 0
299 275 #define CMB_WR_TIMER_TX_SHIFT 16
300 276
301 277 /*
302 278 * Useful macros.
303 279 */
304 280 #define L1_RX_NSEGS(x) \
305 281 (((x) & L1_RRD_NSEGS_MASK) >> L1_RRD_NSEGS_SHIFT)
306 282 #define L1_RX_CONS(x) \
307 283 (((x) & L1_RRD_CONS_MASK) >> L1_RRD_CONS_SHIFT)
308 284 #define L1_RX_CSUM(x) \
309 285 (((x) & L1_RRD_CSUM_MASK) >> L1_RRD_CSUM_SHIFT)
310 286 #define L1_RX_BYTES(x) \
311 287 (((x) & L1_RRD_LEN_MASK) >> L1_RRD_LEN_SHIFT)
312 288
313 289
314 290 #ifdef __cplusplus
315 291 }
316 292 #endif
317 293
318 294 #endif /* _ATGE_L1_REG_H */
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