212 Atheros AR8132 / L1c Gigabit Ethernet Adapter

@@ -179,11 +179,10 @@
 #define DESC_RD_CNT_MASK        0x000007FF
 
 /*
  * PHY registers.
  */
-#define L1_CSMB_CTRL            0x15D0
 #define PHY_CDTS_STAT_OK        0x0000
 #define PHY_CDTS_STAT_SHORT     0x0100
 #define PHY_CDTS_STAT_OPEN      0x0200
 #define PHY_CDTS_STAT_INVAL     0x0300
 #define PHY_CDTS_STAT_MASK      0x0300

@@ -196,12 +195,10 @@
 #define DMA_CFG_RD_BURST_MASK   0x07
 #define DMA_CFG_RD_BURST_SHIFT  4
 #define DMA_CFG_WR_BURST_MASK   0x07
 #define DMA_CFG_WR_BURST_SHIFT  7
 
-#define RXQ_CFG_ENB             0x80000000
-
 #define L1_RD_LEN_MASK          0x0000FFFF
 #define L1_RD_LEN_SHIFT 0
 
 #define L1_SRAM_RD_ADDR         0x1500
 #define L1_SRAM_RD_LEN                  0x1504

@@ -217,29 +214,20 @@
 #define L1_SRAM_TX_FIFO_LEN             0x152C
 
 #define RXQ_CFG_RD_BURST_MASK           0x000000FF
 #define RXQ_CFG_RRD_BURST_THRESH_MASK   0x0000FF00
 #define RXQ_CFG_RD_PREF_MIN_IPG_MASK    0x001F0000
-#define RXQ_CFG_CUT_THROUGH_ENB         0x40000000
-#define RXQ_CFG_ENB                     0x80000000
 #define RXQ_CFG_RD_BURST_SHIFT          0
 #define RXQ_CFG_RD_BURST_DEFAULT        8
 #define RXQ_CFG_RRD_BURST_THRESH_SHIFT  8
 #define RXQ_CFG_RRD_BURST_THRESH_DEFAULT 8
 #define RXQ_CFG_RD_PREF_MIN_IPG_SHIFT   16
 #define RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT 1
 
-#define TXQ_CFG_ENB                     0x00000020
-#define TXQ_CFG_ENHANCED_MODE           0x00000040
 #define TXQ_CFG_TPD_FETCH_THRESH_MASK   0x00003F00
-#define TXQ_CFG_TX_FIFO_BURST_MASK      0xFFFF0000
-#define TXQ_CFG_TPD_BURST_SHIFT         0
-#define TXQ_CFG_TPD_BURST_DEFAULT       4
 #define TXQ_CFG_TPD_FETCH_THRESH_SHIFT  8
 #define TXQ_CFG_TPD_FETCH_DEFAULT       16
-#define TXQ_CFG_TX_FIFO_BURST_SHIFT     16
-#define TXQ_CFG_TX_FIFO_BURST_DEFAULT   256
 
 #define L1_TX_JUMBO_TPD_TH_IPG          0x1584
 #define TX_JUMBO_TPD_TH_MASK            0x000007FF
 #define TX_JUMBO_TPD_IPG_MASK           0x001F0000
 #define TX_JUMBO_TPD_TH_SHIFT           0

@@ -262,26 +250,14 @@
 #define CSMB_CTRL_CMB_KICK              0x00000001
 #define CSMB_CTRL_SMB_KICK              0x00000002
 #define CSMB_CTRL_CMB_ENB               0x00000004
 #define CSMB_CTRL_SMB_ENB               0x00000008
 
-#define INTR_TX_FIFO_UNDERRUN           0x00000040
-#define INTR_RX_FIFO_OFLOW              0x00000008
-#define INTR_TX_DMA                     0x00040000
 #define INTR_RX_DMA                     0x00080000
 #define INTR_CMB_RX                     0x00100000
 #define INTR_CMB_TX                     0x00200000
-#define INTR_MAC_RX                     0x00400000
-#define INTR_MAC_TX                     0x00800000
-#define INTR_UNDERRUN                   0x01000000
-#define INTR_FRAME_ERROR                0x02000000
-#define INTR_FRAME_OK                   0x04000000
-#define INTR_CSUM_ERROR                 0x08000000
-#define INTR_PHY_LINK_DOWN              0x10000000
 #define INTR_DIS_SMB                    0x20000000
-#define INTR_DIS_DMA                    0x40000000
-#define INTR_DIS_INT                    0x80000000
 
 #define L1_INTRS        \
         (INTR_SMB | INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST |   \
         INTR_CMB_TX | INTR_CMB_RX | INTR_RX_FIFO_OFLOW | INTR_TX_FIFO_UNDERRUN)