1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26 #ifndef _ATGE_L1_REG_H
27 #define _ATGE_L1_REG_H
28
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32
33 #pragma pack(1)
34 typedef struct l1_cmb {
35 uint32_t intr_status;
36 uint32_t rx_prod_cons;
37 uint32_t tx_prod_cons;
38 } l1_cmb_t;
39
40 typedef struct l1_rx_desc {
41 uint64_t addr;
42 uint32_t len;
43 } l1_rx_desc_t;
44
45 typedef struct l1_rx_rdesc {
46 uint32_t index;
47 uint32_t len;
48 uint32_t flags;
49 uint32_t vtags;
50 } l1_rx_rdesc_t;
51
52 /*
53 * Statistics counters collected by the MAC
54 */
55 typedef struct l1_smb {
56 /* Rx stats. */
57 uint32_t rx_frames;
58 uint32_t rx_bcast_frames;
59 uint32_t rx_mcast_frames;
60 uint32_t rx_pause_frames;
61 uint32_t rx_control_frames;
62 uint32_t rx_crcerrs;
63 uint32_t rx_lenerrs;
64 uint32_t rx_bytes;
65 uint32_t rx_runts;
66 uint32_t rx_fragments;
67 uint32_t rx_pkts_64;
68 uint32_t rx_pkts_65_127;
69 uint32_t rx_pkts_128_255;
70 uint32_t rx_pkts_256_511;
71 uint32_t rx_pkts_512_1023;
72 uint32_t rx_pkts_1024_1518;
73 uint32_t rx_pkts_1519_max;
74 uint32_t rx_pkts_truncated;
75 uint32_t rx_fifo_oflows;
76 uint32_t rx_desc_oflows;
77 uint32_t rx_alignerrs;
78 uint32_t rx_bcast_bytes;
79 uint32_t rx_mcast_bytes;
80 uint32_t rx_pkts_filtered;
81 /* Tx stats. */
82 uint32_t tx_frames;
83 uint32_t tx_bcast_frames;
84 uint32_t tx_mcast_frames;
85 uint32_t tx_pause_frames;
86 uint32_t tx_excess_defer;
87 uint32_t tx_control_frames;
88 uint32_t tx_deferred;
89 uint32_t tx_bytes;
90 uint32_t tx_pkts_64;
91 uint32_t tx_pkts_65_127;
92 uint32_t tx_pkts_128_255;
93 uint32_t tx_pkts_256_511;
94 uint32_t tx_pkts_512_1023;
95 uint32_t tx_pkts_1024_1518;
96 uint32_t tx_pkts_1519_max;
97 uint32_t tx_single_colls;
98 uint32_t tx_multi_colls;
99 uint32_t tx_late_colls;
100 uint32_t tx_excess_colls;
101 uint32_t tx_underrun;
102 uint32_t tx_desc_underrun;
103 uint32_t tx_lenerrs;
104 uint32_t tx_pkts_truncated;
105 uint32_t tx_bcast_bytes;
106 uint32_t tx_mcast_bytes;
107 uint32_t updated;
108 } atge_l1_smb_t;
109 #pragma pack()
110
111 #define L1_RX_RING_CNT 256
112 #define L1_RR_RING_CNT (ATGE_TX_RING_CNT + L1_RX_RING_CNT)
113
114 #define L1_RING_ALIGN 16
115 #define L1_TX_RING_ALIGN 16
116 #define L1_RX_RING_ALIGN 16
117 #define L1_RR_RING_ALIGN 16
118 #define L1_CMB_ALIGN 16
119 #define L1_SMB_ALIGN 16
120
121 #define L1_CMB_BLOCK_SZ sizeof (struct l1_cmb)
122 #define L1_SMB_BLOCK_SZ sizeof (struct l1_smb)
123
124 #define L1_RX_RING_SZ \
125 (sizeof (struct l1_rx_desc) * L1_RX_RING_CNT)
126
127 #define L1_RR_RING_SZ \
128 (sizeof (struct l1_rx_rdesc) * L1_RR_RING_CNT)
129
130 /*
131 * For RX
132 */
133 #define L1_RRD_CONS_SHIFT 16
134 #define L1_RRD_NSEGS_MASK 0x000000FF
135 #define L1_RRD_CONS_MASK 0xFFFF0000
136 #define L1_RRD_NSEGS_SHIFT 0
137 #define L1_RRD_LEN_MASK 0xFFFF0000
138 #define L1_RRD_CSUM_MASK 0x0000FFFF
139 #define L1_RRD_CSUM_SHIFT 0
140 #define L1_RRD_LEN_SHIFT 16
141 #define L1_RRD_ETHERNET 0x00000080
142 #define L1_RRD_VLAN 0x00000100
143 #define L1_RRD_ERROR 0x00000200
144 #define L1_RRD_IPV4 0x00000400
145 #define L1_RRD_UDP 0x00000800
146 #define L1_RRD_TCP 0x00001000
147 #define L1_RRD_BCAST 0x00002000
148 #define L1_RRD_MCAST 0x00004000
149 #define L1_RRD_PAUSE 0x00008000
150 #define L1_RRD_CRC 0x00010000
151 #define L1_RRD_CODE 0x00020000
152 #define L1_RRD_DRIBBLE 0x00040000
153 #define L1_RRD_RUNT 0x00080000
154 #define L1_RRD_OFLOW 0x00100000
155 #define L1_RRD_TRUNC 0x00200000
156 #define L1_RRD_IPCSUM_NOK 0x00400000
157 #define L1_RRD_TCP_UDPCSUM_NOK 0x00800000
158 #define L1_RRD_LENGTH_NOK 0x01000000
159 #define L1_RRD_DES_ADDR_FILTERED 0x02000000
160 #define RRD_PROD_MASK 0x0000FFFF
161 #define TPD_CONS_MASK 0xFFFF0000
162 #define TPD_CONS_SHIFT 16
163 #define CMB_UPDATED 0x00000001
164 #define RRD_PROD_SHIFT 0
165
166 /*
167 * All descriptors and CMB/SMB share the same high address.
168 */
169 #define L1_DESC_ADDR_HI 0x1540
170 #define L1_DESC_RD_ADDR_LO 0x1544
171 #define L1_DESC_RRD_ADDR_LO 0x1548
172 #define L1_DESC_TPD_ADDR_LO 0x154C
173 #define L1_DESC_CMB_ADDR_LO 0x1550
174 #define L1_DESC_SMB_ADDR_LO 0x1554
175 #define L1_DESC_RRD_RD_CNT 0x1558
176 #define DESC_RRD_CNT_SHIFT 16
177 #define DESC_RRD_CNT_MASK 0x07FF0000
178 #define DESC_RD_CNT_SHIFT 0
179 #define DESC_RD_CNT_MASK 0x000007FF
180
181 /*
182 * PHY registers.
183 */
184 #define L1_CSMB_CTRL 0x15D0
185 #define PHY_CDTS_STAT_OK 0x0000
186 #define PHY_CDTS_STAT_SHORT 0x0100
187 #define PHY_CDTS_STAT_OPEN 0x0200
188 #define PHY_CDTS_STAT_INVAL 0x0300
189 #define PHY_CDTS_STAT_MASK 0x0300
190
191 /*
192 * DMA CFG registers (L1 specific)
193 */
194 #define DMA_CFG_RD_ENB 0x00000400
195 #define DMA_CFG_WR_ENB 0x00000800
196 #define DMA_CFG_RD_BURST_MASK 0x07
197 #define DMA_CFG_RD_BURST_SHIFT 4
198 #define DMA_CFG_WR_BURST_MASK 0x07
199 #define DMA_CFG_WR_BURST_SHIFT 7
200
201 #define RXQ_CFG_ENB 0x80000000
202
203 #define L1_RD_LEN_MASK 0x0000FFFF
204 #define L1_RD_LEN_SHIFT 0
205
206 #define L1_SRAM_RD_ADDR 0x1500
207 #define L1_SRAM_RD_LEN 0x1504
208 #define L1_SRAM_RRD_ADDR 0x1508
209 #define L1_SRAM_RRD_LEN 0x150C
210 #define L1_SRAM_TPD_ADDR 0x1510
211 #define L1_SRAM_TPD_LEN 0x1514
212 #define L1_SRAM_TRD_ADDR 0x1518
213 #define L1_SRAM_TRD_LEN 0x151C
214 #define L1_SRAM_RX_FIFO_ADDR 0x1520
215 #define L1_SRAM_RX_FIFO_LEN 0x1524
216 #define L1_SRAM_TX_FIFO_ADDR 0x1528
217 #define L1_SRAM_TX_FIFO_LEN 0x152C
218
219 #define RXQ_CFG_RD_BURST_MASK 0x000000FF
220 #define RXQ_CFG_RRD_BURST_THRESH_MASK 0x0000FF00
221 #define RXQ_CFG_RD_PREF_MIN_IPG_MASK 0x001F0000
222 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000
223 #define RXQ_CFG_ENB 0x80000000
224 #define RXQ_CFG_RD_BURST_SHIFT 0
225 #define RXQ_CFG_RD_BURST_DEFAULT 8
226 #define RXQ_CFG_RRD_BURST_THRESH_SHIFT 8
227 #define RXQ_CFG_RRD_BURST_THRESH_DEFAULT 8
228 #define RXQ_CFG_RD_PREF_MIN_IPG_SHIFT 16
229 #define RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT 1
230
231 #define TXQ_CFG_ENB 0x00000020
232 #define TXQ_CFG_ENHANCED_MODE 0x00000040
233 #define TXQ_CFG_TPD_FETCH_THRESH_MASK 0x00003F00
234 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000
235 #define TXQ_CFG_TPD_BURST_SHIFT 0
236 #define TXQ_CFG_TPD_BURST_DEFAULT 4
237 #define TXQ_CFG_TPD_FETCH_THRESH_SHIFT 8
238 #define TXQ_CFG_TPD_FETCH_DEFAULT 16
239 #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16
240 #define TXQ_CFG_TX_FIFO_BURST_DEFAULT 256
241
242 #define L1_TX_JUMBO_TPD_TH_IPG 0x1584
243 #define TX_JUMBO_TPD_TH_MASK 0x000007FF
244 #define TX_JUMBO_TPD_IPG_MASK 0x001F0000
245 #define TX_JUMBO_TPD_TH_SHIFT 0
246 #define TX_JUMBO_TPD_IPG_SHIFT 16
247 #define TX_JUMBO_TPD_IPG_DEFAULT 1
248
249 /* CMB DMA Write Threshold Register */
250 #define L1_CMB_WR_THRESH 0x15D4
251 #define CMB_WR_THRESH_RRD_MASK 0x000007FF
252 #define CMB_WR_THRESH_TPD_MASK 0x07FF0000
253 #define CMB_WR_THRESH_RRD_SHIFT 0
254 #define CMB_WR_THRESH_RRD_DEFAULT 4
255 #define CMB_WR_THRESH_TPD_SHIFT 16
256 #define CMB_WR_THRESH_TPD_DEFAULT 4
257
258 /* SMB auto DMA timer register */
259 #define L1_SMB_TIMER 0x15E4
260
261 #define L1_CSMB_CTRL 0x15D0
262 #define CSMB_CTRL_CMB_KICK 0x00000001
263 #define CSMB_CTRL_SMB_KICK 0x00000002
264 #define CSMB_CTRL_CMB_ENB 0x00000004
265 #define CSMB_CTRL_SMB_ENB 0x00000008
266
267 #define INTR_TX_FIFO_UNDERRUN 0x00000040
268 #define INTR_RX_FIFO_OFLOW 0x00000008
269 #define INTR_TX_DMA 0x00040000
270 #define INTR_RX_DMA 0x00080000
271 #define INTR_CMB_RX 0x00100000
272 #define INTR_CMB_TX 0x00200000
273 #define INTR_MAC_RX 0x00400000
274 #define INTR_MAC_TX 0x00800000
275 #define INTR_UNDERRUN 0x01000000
276 #define INTR_FRAME_ERROR 0x02000000
277 #define INTR_FRAME_OK 0x04000000
278 #define INTR_CSUM_ERROR 0x08000000
279 #define INTR_PHY_LINK_DOWN 0x10000000
280 #define INTR_DIS_SMB 0x20000000
281 #define INTR_DIS_DMA 0x40000000
282 #define INTR_DIS_INT 0x80000000
283
284 #define L1_INTRS \
285 (INTR_SMB | INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \
286 INTR_CMB_TX | INTR_CMB_RX | INTR_RX_FIFO_OFLOW | INTR_TX_FIFO_UNDERRUN)
287
288 #define L1_RXQ_RRD_PAUSE_THRESH 0x15AC
289 #define RXQ_RRD_PAUSE_THRESH_HI_MASK 0x00000FFF
290 #define RXQ_RRD_PAUSE_THRESH_LO_MASK 0x0FFF0000
291 #define RXQ_RRD_PAUSE_THRESH_HI_SHIFT 0
292 #define RXQ_RRD_PAUSE_THRESH_LO_SHIFT 16
293
294 /* RX/TX count-down timer to trigger CMB-write. */
295 #define L1_CMB_WR_TIMER 0x15D8
296 #define CMB_WR_TIMER_RX_MASK 0x0000FFFF
297 #define CMB_WR_TIMER_TX_MASK 0xFFFF0000
298 #define CMB_WR_TIMER_RX_SHIFT 0
299 #define CMB_WR_TIMER_TX_SHIFT 16
300
301 /*
302 * Useful macros.
303 */
304 #define L1_RX_NSEGS(x) \
305 (((x) & L1_RRD_NSEGS_MASK) >> L1_RRD_NSEGS_SHIFT)
306 #define L1_RX_CONS(x) \
307 (((x) & L1_RRD_CONS_MASK) >> L1_RRD_CONS_SHIFT)
308 #define L1_RX_CSUM(x) \
309 (((x) & L1_RRD_CSUM_MASK) >> L1_RRD_CSUM_SHIFT)
310 #define L1_RX_BYTES(x) \
311 (((x) & L1_RRD_LEN_MASK) >> L1_RRD_LEN_SHIFT)
312
313
314 #ifdef __cplusplus
315 }
316 #endif
317
318 #endif /* _ATGE_L1_REG_H */