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212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
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--- old/usr/src/uts/common/io/atge/atge_cmn_reg.h
+++ new/usr/src/uts/common/io/atge/atge_cmn_reg.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
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12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 + * Copyright (c) 2012 Gary Mills
23 + *
22 24 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 25 * Use is subject to license terms.
24 26 */
27 +/*
28 + * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org>
29 + * All rights reserved.
30 + *
31 + * Redistribution and use in source and binary forms, with or without
32 + * modification, are permitted provided that the following conditions
33 + * are met:
34 + * 1. Redistributions of source code must retain the above copyright
35 + * notice unmodified, this list of conditions, and the following
36 + * disclaimer.
37 + * 2. Redistributions in binary form must reproduce the above copyright
38 + * notice, this list of conditions and the following disclaimer in the
39 + * documentation and/or other materials provided with the distribution.
40 + *
41 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
51 + * SUCH DAMAGE.
52 + */
25 53
26 54 #ifndef _ATGE_CMN_REG_H
27 55 #define _ATGE_CMN_REG_H
28 56
29 57 #ifdef __cplusplus
30 58 extern "C" {
31 59 #endif
32 60
33 61 #define ATGE_SPI_CTRL 0x200
34 62 #define SPI_VPD_ENB 0x00002000
35 63
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36 64 #define PCIE_DEVCTRL 0x0060 /* L1 */
37 65
38 66 /*
39 67 * Station Address
40 68 */
41 69 #define ATGE_PAR0 0x1488
42 70 #define ATGE_PAR1 0x148C
43 71
44 72 #define ATGE_MASTER_CFG 0x1400
45 73 #define MASTER_RESET 0x00000001
46 -#define MASTER_MTIMER_ENB 0x00000002
47 74 #define MASTER_ITIMER_ENB 0x00000004 /* L1 */
48 -#define MASTER_IM_TX_TIMER_ENB 0x00000004 /* L1E */
49 75 #define MASTER_MANUAL_INT_ENB 0x00000008
50 -#define MASTER_IM_RX_TIMER_ENB 0x00000020
51 76 #define MASTER_INT_RDCLR 0x00000040
77 +#define MASTER_SA_TIMER_ENB 0x00000080
78 +#define MASTER_MTIMER_ENB 0x00000100
52 79 #define MASTER_LED_MODE 0x00000200
80 +#define MASTER_MANUAL_INTR_ENB 0x00000200
81 +#define MASTER_IM_TX_TIMER_ENB 0x00000400
82 +#define MASTER_IM_RX_TIMER_ENB 0x00000800
83 +#define MASTER_CLK_SEL_DIS 0x00001000
84 +#define MASTER_CLK_SWH_MODE 0x00002000
85 +#define MASTER_INTR_RD_CLR 0x00004000
53 86 #define MASTER_CHIP_REV_MASK 0x00FF0000
54 87 #define MASTER_CHIP_ID_MASK 0xFF000000
88 +#define MASTER_CHIP_ID_MASKXXX 0x7F000000 /* XXX */
89 +#define MASTER_OTP_SEL 0x80000000
90 +#define MASTER_TEST_MODE_SHIFT 2
55 91 #define MASTER_CHIP_REV_SHIFT 16
56 92 #define MASTER_CHIP_ID_SHIFT 24
57 93
58 94 #define ATGE_RESET_TIMEOUT 100
59 95
60 96 #define ATGE_IDLE_STATUS 0x1410
61 97 #define IDLE_STATUS_RXMAC 0x00000001
62 98 #define IDLE_STATUS_TXMAC 0x00000002
63 99 #define IDLE_STATUS_RXQ 0x00000004
64 100 #define IDLE_STATUS_TXQ 0x00000008
65 101 #define IDLE_STATUS_DMARD 0x00000010
66 102 #define IDLE_STATUS_DMAWR 0x00000020
67 103 #define IDLE_STATUS_SMB 0x00000040
68 104 #define IDLE_STATUS_CMB 0x00000080
69 105
106 +#define ATGE_SERDES_LOCK 0x1424
107 +#define SERDES_LOCK_DET 0x00000001
108 +#define SERDES_LOCK_DET_ENB 0x00000002
109 +#define SERDES_MAC_CLK_SLOWDOWN 0x00020000
110 +#define SERDES_PHY_CLK_SLOWDOWN 0x00040000
111 +
70 112 #define ATGE_MAC_CFG 0x1480
71 113 #define ATGE_CFG_TX_ENB 0x00000001
72 114 #define ATGE_CFG_RX_ENB 0x00000002
73 115 #define ATGE_CFG_TX_FC 0x00000004
74 116 #define ATGE_CFG_RX_FC 0x00000008
75 117 #define ATGE_CFG_LOOP 0x00000010
76 118 #define ATGE_CFG_FULL_DUPLEX 0x00000020
77 119 #define ATGE_CFG_TX_CRC_ENB 0x00000040
78 120 #define ATGE_CFG_TX_AUTO_PAD 0x00000080
79 121 #define ATGE_CFG_TX_LENCHK 0x00000100
80 122 #define ATGE_CFG_RX_JUMBO_ENB 0x00000200
81 123 #define ATGE_CFG_PREAMBLE_MASK 0x00003C00
82 124 #define ATGE_CFG_VLAN_TAG_STRIP 0x00004000
83 125 #define ATGE_CFG_PROMISC 0x00008000
84 126 #define ATGE_CFG_TX_PAUSE 0x00010000
85 127 #define ATGE_CFG_SCNT 0x00020000
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86 128 #define ATGE_CFG_SYNC_RST_TX 0x00040000
87 129 #define ATGE_CFG_SPEED_MASK 0x00300000
88 130 #define ATGE_CFG_SPEED_10_100 0x00100000
89 131 #define ATGE_CFG_SPEED_1000 0x00200000
90 132 #define ATGE_CFG_DBG_TX_BACKOFF 0x00400000
91 133 #define ATGE_CFG_TX_JUMBO_ENB 0x00800000
92 134 #define ATGE_CFG_RXCSUM_ENB 0x01000000
93 135 #define ATGE_CFG_ALLMULTI 0x02000000
94 136 #define ATGE_CFG_BCAST 0x04000000
95 137 #define ATGE_CFG_DBG 0x08000000
138 +#define ATGE_CFG_SINGLE_PAUSE_ENB 0x10000000
139 +#define ATGE_CFG_HASH_ALG_CRC32 0x20000000
140 +#define ATGE_CFG_SPEED_MODE_SW 0x40000000
96 141 #define ATGE_CFG_PREAMBLE_SHIFT 10
97 142 #define ATGE_CFG_PREAMBLE_DEFAULT 7
98 143
99 144 /*
100 145 * Interrupt related registers.
101 146 */
102 147 #define ATGE_INTR_MASK 0x1604
103 148 #define ATGE_INTR_STATUS 0x1600
104 149 #define INTR_SMB 0x00000001
105 150 #define INTR_MOD_TIMER 0x00000002
106 151 #define INTR_MANUAL_TIMER 0x00000004
107 152 #define INTR_RX_FIFO_OFLOW 0x00000008
108 153 #define INTR_RD_UNDERRUN 0x00000010
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109 154 #define INTR_RRD_OFLOW 0x00000020
110 155 #define INTR_TX_FIFO_UNDERRUN 0x00000040
111 156 #define INTR_LINK_CHG 0x00000080
112 157 #define INTR_HOST_RD_UNDERRUN 0x00000100
113 158 #define INTR_HOST_RRD_OFLOW 0x00000200
114 159 #define INTR_DMA_RD_TO_RST 0x00000400
115 160 #define INTR_DMA_WR_TO_RST 0x00000800
116 161 #define INTR_GPHY 0x00001000
117 162 #define INTR_RX_PKT 0x00010000
118 163 #define INTR_TX_PKT 0x00020000
119 -#define INTR_TX_DMA 0x00040000
164 +#define INTR_TX_DMA 0x00040000 /* L1 intr status */
120 165 #define INTR_MAC_RX 0x00400000
121 166 #define INTR_MAC_TX 0x00800000
122 167 #define INTR_UNDERRUN 0x01000000
123 168 #define INTR_FRAME_ERROR 0x02000000
124 169 #define INTR_FRAME_OK 0x04000000
125 170 #define INTR_CSUM_ERROR 0x08000000
126 171 #define INTR_PHY_LINK_DOWN 0x10000000
127 172 #define INTR_DIS_SM 0x20000000
128 173 #define INTR_DIS_DMA 0x40000000
129 174 #define INTR_DIS_INT 0x80000000
130 175
131 176 /* L1E intr status */
132 177 #define INTR_RX_PKT1 0x00080000
133 178 #define INTR_RX_PKT2 0x00100000
134 179 #define INTR_RX_PKT3 0x00200000
135 180
136 -/* L1 intr status */
137 -#define INTR_TX_DMA 0x00040000
138 -
139 181 /*
140 182 * L1E specific errors. We keep it here since some errors are common for
141 183 * both L1 and L1E chip.
142 184 *
143 185 */
144 186 #define L1E_INTR_ERRORS \
145 187 (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)
146 188
147 189 /*
148 190 * TXQ CFG registers.
149 191 */
150 192 #define ATGE_TXQ_CFG 0x1580
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151 193 #define TXQ_CFG_TPD_BURST_MASK 0x0000000F
152 194 #define TXQ_CFG_ENB 0x00000020
153 195 #define TXQ_CFG_ENHANCED_MODE 0x00000040
154 196 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000
155 197 #define TXQ_CFG_TPD_BURST_SHIFT 0
156 198 #define TXQ_CFG_TPD_BURST_DEFAULT 4
157 199 #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16
158 200 #define TXQ_CFG_TX_FIFO_BURST_DEFAULT 256
159 201
160 202 /*
161 - * RXQ CFG register.
162 - */
163 -#define ATGE_RXQ_CFG 0x15A0
164 -
165 -/*
166 203 * Common registers for DMA CFG.
167 204 */
168 205 #define ATGE_DMA_CFG 0x15C0
169 206 #define DMA_CFG_IN_ORDER 0x00000001
170 207 #define DMA_CFG_ENH_ORDER 0x00000002
171 208 #define DMA_CFG_OUT_ORDER 0x00000004
172 209 #define DMA_CFG_RCB_64 0x00000000
173 210 #define DMA_CFG_RCB_128 0x00000008
174 211 #define DMA_CFG_RD_BURST_128 0x00000000
175 212 #define DMA_CFG_RD_BURST_256 0x00000010
176 213 #define DMA_CFG_RD_BURST_512 0x00000020
177 214 #define DMA_CFG_RD_BURST_1024 0x00000030
178 215 #define DMA_CFG_RD_BURST_2048 0x00000040
179 216 #define DMA_CFG_RD_BURST_4096 0x00000050
180 217 #define DMA_CFG_WR_BURST_128 0x00000000
181 218 #define DMA_CFG_WR_BURST_256 0x00000080
182 219 #define DMA_CFG_WR_BURST_512 0x00000100
183 220 #define DMA_CFG_WR_BURST_1024 0x00000180
184 221 #define DMA_CFG_WR_BURST_2048 0x00000200
185 222 #define DMA_CFG_WR_BURST_4096 0x00000280
186 223
187 224 /* L1E specific but can go into common regs */
188 225 #define DMA_CFG_RXCMB_ENB 0x00200000
189 226 #define DMA_CFG_RD_DELAY_CNT_DEFAULT 15
190 227 #define DMA_CFG_RD_DELAY_CNT_SHIFT 11
191 228 #define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800
192 229 #define DMA_CFG_WR_DELAY_CNT_DEFAULT 4
193 230 #define DMA_CFG_WR_DELAY_CNT_SHIFT 16
194 231 #define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000
195 232
196 233 /*
197 234 * Common PHY registers.
198 235 */
199 236 #define ATGE_MDIO 0x1414
200 237 #define MDIO_DATA_MASK 0x0000FFFF
201 238 #define MDIO_REG_ADDR_MASK 0x001F0000
202 239 #define MDIO_OP_READ 0x00200000
203 240 #define MDIO_OP_WRITE 0x00000000
204 241 #define MDIO_SUP_PREAMBLE 0x00400000
205 242 #define MDIO_OP_EXECUTE 0x00800000
206 243 #define MDIO_CLK_25_4 0x00000000
207 244 #define MDIO_CLK_25_6 0x02000000
208 245 #define MDIO_CLK_25_8 0x03000000
209 246 #define MDIO_CLK_25_10 0x04000000
210 247 #define MDIO_CLK_25_14 0x05000000
211 248 #define MDIO_CLK_25_20 0x06000000
212 249 #define MDIO_CLK_25_28 0x07000000
213 250 #define MDIO_OP_BUSY 0x08000000
214 251 #define MDIO_DATA_SHIFT 0
215 252 #define MDIO_REG_ADDR_SHIFT 16
216 253
217 254 #define MDIO_REG_ADDR(x) \
218 255 (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK)
219 256
220 257 #define ATGE_GPHY_CTRL 0x140C /* 16-bits */
221 258 #define GPHY_CTRL_RST 0x0000
222 259 #define GPHY_CTRL_CLR 0x0001
223 260 #define ATPHY_CDTC 0x16
224 261 #define PHY_CDTC_ENB 0x0001
225 262 #define PHY_CDTC_POFF 0x8
226 263 #define ATPHY_CDTS 0x1C
227 264
228 265
229 266 #define ATGE_PHY_ADDR 0
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230 267 #define ATGE_PHY_STATUS 0x1418
231 268 #define PHY_TIMEOUT 1000
232 269
233 270 #define ATGE_DESC_TPD_CNT 0x155C
234 271 #define DESC_TPD_CNT_MASK 0x00003FF
235 272 #define DESC_TPD_CNT_SHIFT 0
236 273
237 274 #define ATGE_DMA_BLOCK 0x1534
238 275 #define DMA_BLOCK_LOAD 0x00000001
239 276
277 +/* From Freebsd if_alcreg.h */
278 +/* 0x0000 - 0x02FF : PCIe configuration space */
279 +
280 +#define ATGE_PEX_UNC_ERR_SEV 0x10C
281 +#define PEX_UNC_ERR_SEV_TRN 0x00000001
282 +#define PEX_UNC_ERR_SEV_DLP 0x00000010
283 +#define PEX_UNC_ERR_SEV_PSN_TLP 0x00001000
284 +#define PEX_UNC_ERR_SEV_FCP 0x00002000
285 +#define PEX_UNC_ERR_SEV_CPL_TO 0x00004000
286 +#define PEX_UNC_ERR_SEV_CA 0x00008000
287 +#define PEX_UNC_ERR_SEV_UC 0x00010000
288 +#define PEX_UNC_ERR_SEV_ROV 0x00020000
289 +#define PEX_UNC_ERR_SEV_MLFP 0x00040000
290 +#define PEX_UNC_ERR_SEV_ECRC 0x00080000
291 +#define PEX_UNC_ERR_SEV_UR 0x00100000
292 +
293 +#define ATGE_PCIE_PHYMISC 0x1000
294 +#define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004
295 +
296 +#define ATGE_PCIE_PHYMISC2 0x1004
297 +#define PCIE_PHYMISC2_SERDES_CDR_MASK 0x00030000
298 +#define PCIE_PHYMISC2_SERDES_TH_MASK 0x000C0000
299 +#define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16
300 +#define PCIE_PHYMISC2_SERDES_TH_SHIFT 18
301 +
302 +#define ATGE_LTSSM_ID_CFG 0x12FC
303 +#define LTSSM_ID_WRO_ENB 0x00001000
304 +
305 +#define ATGE_SMB_STAT_TIMER 0x15C4
306 +#define SMB_STAT_TIMER_MASK 0x00FFFFFF
307 +#define SMB_STAT_TIMER_SHIFT 0
308 +
309 +#define ATGE_CMB_TD_THRESH 0x15C8
310 +#define CMB_TD_THRESH_MASK 0x0000FFFF
311 +#define CMB_TD_THRESH_SHIFT 0
312 +
313 +#define ATGE_CMB_TX_TIMER 0x15CC
314 +#define CMB_TX_TIMER_MASK 0x0000FFFF
315 +#define CMB_TX_TIMER_SHIFT 0
316 +
317 +#define ATGE_MBOX_RD0_PROD_IDX 0x15E0
318 +
319 +#define ATGE_MBOX_RD1_PROD_IDX 0x15E4
320 +
321 +#define ATGE_MBOX_RD2_PROD_IDX 0x15E8
322 +
323 +#define ATGE_MBOX_RD3_PROD_IDX 0x15EC
324 +
325 +#define ATGE_MBOX_RD_PROD_MASK 0x0000FFFF
326 +#define MBOX_RD_PROD_SHIFT 0
327 +
328 +#define ATGE_MBOX_TD_PROD_IDX 0x15F0
329 +#define MBOX_TD_PROD_HI_IDX_MASK 0x0000FFFF
330 +#define MBOX_TD_PROD_LO_IDX_MASK 0xFFFF0000
331 +#define MBOX_TD_PROD_HI_IDX_SHIFT 0
332 +#define MBOX_TD_PROD_LO_IDX_SHIFT 16
333 +
334 +#define ATGE_MBOX_TD_CONS_IDX 0x15F4
335 +#define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF
336 +#define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000
337 +#define MBOX_TD_CONS_HI_IDX_SHIFT 0
338 +#define MBOX_TD_CONS_LO_IDX_SHIFT 16
339 +
340 +#define ATGE_MBOX_RD01_CONS_IDX 0x15F8
341 +#define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF
342 +#define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000
343 +#define MBOX_RD0_CONS_IDX_SHIFT 0
344 +#define MBOX_RD1_CONS_IDX_SHIFT 16
345 +
346 +#define ATGE_MBOX_RD23_CONS_IDX 0x15FC
347 +#define MBOX_RD2_CONS_IDX_MASK 0x0000FFFF
348 +#define MBOX_RD3_CONS_IDX_MASK 0xFFFF0000
349 +#define MBOX_RD2_CONS_IDX_SHIFT 0
350 +#define MBOX_RD3_CONS_IDX_SHIFT 16
351 +
352 +#define ATGE_INTR_RETRIG_TIMER 0x1608
353 +#define INTR_RETRIG_TIMER_MASK 0x0000FFFF
354 +#define INTR_RETRIG_TIMER_SHIFT 0
355 +
356 +#define ATGE_HDS_CFG 0x160C
357 +#define HDS_CFG_ENB 0x00000001
358 +#define HDS_CFG_BACKFILLSIZE_MASK 0x000FFF00
359 +#define HDS_CFG_MAX_HDRSIZE_MASK 0xFFF00000
360 +#define HDS_CFG_BACKFILLSIZE_SHIFT 8
361 +#define HDS_CFG_MAX_HDRSIZE_SHIFT 20
362 +
363 +/* AR813x/AR815x registers for MAC statistics */
364 +#define ATGE_RX_MIB_BASE 0x1700
365 +
366 +#define ATGE_TX_MIB_BASE 0x1760
367 +
368 +#define ATGE_CLK_GATING_CFG 0x1814
369 +#define CLK_GATING_DMAW_ENB 0x0001
370 +#define CLK_GATING_DMAR_ENB 0x0002
371 +#define CLK_GATING_TXQ_ENB 0x0004
372 +#define CLK_GATING_RXQ_ENB 0x0008
373 +#define CLK_GATING_TXMAC_ENB 0x0010
374 +#define CLK_GATING_RXMAC_ENB 0x0020
375 +
376 +#define ATGE_DEBUG_DATA0 0x1900
377 +
378 +#define ATGE_DEBUG_DATA1 0x1904
379 +
380 +#define ATGE_MII_DBG_ADDR 0x1D
381 +#define ATGE_MII_DBG_DATA 0x1E
382 +/* End Freebsd if_alcreg.h */
383 +
240 384 #define ATGE_MBOX 0x15F0
241 385 #define MBOX_RD_PROD_IDX_MASK 0x000007FF
242 386 #define MBOX_RRD_CONS_IDX_MASK 0x003FF800
243 387 #define MBOX_TD_PROD_IDX_MASK 0xFFC00000
244 388 #define MBOX_RD_PROD_IDX_SHIFT 0
245 389 #define MBOX_RRD_CONS_IDX_SHIFT 11
246 390 #define MBOX_TD_PROD_IDX_SHIFT 22
247 391
248 392
249 393 #define ATGE_IPG_IFG_CFG 0x1484
250 394 #define IPG_IFG_IPGT_MASK 0x0000007F
251 395 #define IPG_IFG_MIFG_MASK 0x0000FF00
252 396 #define IPG_IFG_IPG1_MASK 0x007F0000
253 397 #define IPG_IFG_IPG2_MASK 0x7F000000
254 398 #define IPG_IFG_IPGT_SHIFT 0
255 399 #define IPG_IFG_IPGT_DEFAULT 0x60
256 400 #define IPG_IFG_MIFG_SHIFT 8
257 401 #define IPG_IFG_MIFG_DEFAULT 0x50
258 402 #define IPG_IFG_IPG1_SHIFT 16
259 403 #define IPG_IFG_IPG1_DEFAULT 0x40
260 404 #define IPG_IFG_IPG2_SHIFT 24
261 405 #define IPG_IFG_IPG2_DEFAULT 0x60
262 406
263 407 /* half-duplex parameter configuration. */
264 408 #define ATGE_HDPX_CFG 0x1498
265 409 #define HDPX_CFG_LCOL_MASK 0x000003FF
266 410 #define HDPX_CFG_RETRY_MASK 0x0000F000
267 411 #define HDPX_CFG_EXC_DEF_EN 0x00010000
268 412 #define HDPX_CFG_NO_BACK_C 0x00020000
269 413 #define HDPX_CFG_NO_BACK_P 0x00040000
270 414 #define HDPX_CFG_ABEBE 0x00080000
271 415 #define HDPX_CFG_ABEBT_MASK 0x00F00000
272 416 #define HDPX_CFG_JAMIPG_MASK 0x0F000000
273 417 #define HDPX_CFG_LCOL_SHIFT 0
274 418 #define HDPX_CFG_LCOL_DEFAULT 0x37
275 419 #define HDPX_CFG_RETRY_SHIFT 12
276 420 #define HDPX_CFG_RETRY_DEFAULT 0x0F
277 421 #define HDPX_CFG_ABEBT_SHIFT 20
278 422 #define HDPX_CFG_ABEBT_DEFAULT 0x0A
279 423 #define HDPX_CFG_JAMIPG_SHIFT 24
280 424 #define HDPX_CFG_JAMIPG_DEFAULT 0x07
281 425
282 426 #define ATGE_FRAME_SIZE 0x149C
283 427
284 428 #define ATGE_WOL_CFG 0x14A0
285 429 #define WOL_CFG_PATTERN 0x00000001
286 430 #define WOL_CFG_PATTERN_ENB 0x00000002
287 431 #define WOL_CFG_MAGIC 0x00000004
288 432 #define WOL_CFG_MAGIC_ENB 0x00000008
289 433 #define WOL_CFG_LINK_CHG 0x00000010
290 434 #define WOL_CFG_LINK_CHG_ENB 0x00000020
291 435 #define WOL_CFG_PATTERN_DET 0x00000100
292 436 #define WOL_CFG_MAGIC_DET 0x00000200
293 437 #define WOL_CFG_LINK_CHG_DET 0x00000400
294 438 #define WOL_CFG_CLK_SWITCH_ENB 0x00008000
295 439 #define WOL_CFG_PATTERN0 0x00010000
296 440 #define WOL_CFG_PATTERN1 0x00020000
297 441 #define WOL_CFG_PATTERN2 0x00040000
298 442 #define WOL_CFG_PATTERN3 0x00080000
299 443 #define WOL_CFG_PATTERN4 0x00100000
300 444 #define WOL_CFG_PATTERN5 0x00200000
301 445 #define WOL_CFG_PATTERN6 0x00400000
302 446
303 447 /* WOL pattern length. */
304 448 #define ATGE_PATTERN_CFG0 0x14A4
305 449 #define PATTERN_CFG_0_LEN_MASK 0x0000007F
306 450 #define PATTERN_CFG_1_LEN_MASK 0x00007F00
307 451 #define PATTERN_CFG_2_LEN_MASK 0x007F0000
308 452 #define PATTERN_CFG_3_LEN_MASK 0x7F000000
309 453
310 454 #define ATGE_PATTERN_CFG1 0x14A8
311 455 #define PATTERN_CFG_4_LEN_MASK 0x0000007F
312 456 #define PATTERN_CFG_5_LEN_MASK 0x00007F00
313 457 #define PATTERN_CFG_6_LEN_MASK 0x007F0000
314 458
315 459 #define ATGE_TICK_USECS 2
316 460 #define ATGE_USECS(x) ((x) / ATGE_TICK_USECS)
317 461
318 462 #define ATGE_INTR_CLR_TIMER 0x140E /* 16-bits */
319 463 #define ATGE_IM_TIMER 0x1408
320 464 #define ATGE_IM_TIMER2 0x140A
321 465 #define ATGE_IM_TIMER_MIN 0
322 466 #define ATGE_IM_TIMER_MAX 130000 /* 130 ms */
323 467 #define ATGE_IM_TIMER_DEFAULT 100
324 468 #define ATGE_IM_RX_TIMER_DEFAULT 1
325 469 #define ATGE_IM_TX_TIMER_DEFAULT 1
326 470 #define IM_TIMER_TX_SHIFT 0
327 471 #define IM_TIMER_RX_SHIFT 16
328 472
329 473 #define ATGE_DESC_ADDR_HI 0x1540
330 474 #define ATGE_DESC_RD_ADDR_LO 0x1544
331 475 #define ATGE_DESC_RRD_ADDR_LO 0x1548
332 476 #define ATGE_DESC_TPD_ADDR_LO 0x154C
333 477 #define ATGE_DESC_CMB_ADDR_LO 0x1550
334 478 #define ATGE_DESC_SMB_ADDR_LO 0x1554
335 479 #define ATGE_DESC_RRD_RD_CNT 0x1558
336 480
337 481 #define ATGE_RXQ_JUMBO_CFG 0x15A4
338 482 #define RXQ_JUMBO_CFG_SZ_THRESH_SHIFT 0
339 483 #define RXQ_JUMBO_CFG_SZ_THRESH_MASK 0x000007FF
340 484 #define RXQ_JUMBO_CFG_LKAH_DEFAULT 0x01
341 485 #define RXQ_JUMBO_CFG_LKAH_SHIFT 11
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342 486 #define RXQ_JUMBO_CFG_LKAH_MASK 0x00007800
343 487 #define RXQ_JUMBO_CFG_RRD_TIMER_SHIFT 16
344 488 #define RXQ_JUMBO_CFG_RRD_TIMER_MASK 0xFFFF0000
345 489
346 490 #define ATGE_RXQ_FIFO_PAUSE_THRESH 0x15A8
347 491 #define RXQ_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF
348 492 #define RXQ_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF000
349 493 #define RXQ_FIFO_PAUSE_THRESH_LO_SHIFT 0
350 494 #define RXQ_FIFO_PAUSE_THRESH_HI_SHIFT 16
351 495
496 +/*
497 + * RXQ CFG register.
498 + */
352 499 #define ATGE_RXQ_CFG 0x15A0
353 -#define ATGE_TXQ_CFG 0x1580
354 500 #define RXQ_CFG_ALIGN_32 0x00000000
355 501 #define RXQ_CFG_ALIGN_64 0x00000001
356 502 #define RXQ_CFG_ALIGN_128 0x00000002
357 503 #define RXQ_CFG_ALIGN_256 0x00000003
358 504 #define RXQ_CFG_QUEUE1_ENB 0x00000010
359 505 #define RXQ_CFG_QUEUE2_ENB 0x00000020
360 506 #define RXQ_CFG_QUEUE3_ENB 0x00000040
361 507 #define RXQ_CFG_IPV6_CSUM_VERIFY 0x00000080
362 508 #define RXQ_CFG_RSS_HASH_TBL_LEN_MASK 0x0000FF00
363 509 #define RXQ_CFG_RSS_HASH_IPV4 0x00010000
364 510 #define RXQ_CFG_RSS_HASH_IPV4_TCP 0x00020000
365 511 #define RXQ_CFG_RSS_HASH_IPV6 0x00040000
366 512 #define RXQ_CFG_RSS_HASH_IPV6_TCP 0x00080000
367 513 #define RXQ_CFG_RSS_MODE_DIS 0x00000000
368 514 #define RXQ_CFG_RSS_MODE_SQSINT 0x04000000
369 515 #define RXQ_CFG_RSS_MODE_MQUESINT 0x08000000
370 516 #define RXQ_CFG_RSS_MODE_MQUEMINT 0x0C000000
371 517 #define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000
372 518 #define RXQ_CFG_RSS_HASH_ENB 0x20000000
373 519 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000
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374 520 #define RXQ_CFG_ENB 0x80000000
375 521 #define RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT 8
376 522
377 523 /* 64bit multicast hash register. */
378 524 #define ATGE_MAR0 0x1490
379 525 #define ATGE_MAR1 0x1494
380 526
381 527 #define ATPHY_DBG_ADDR 0x1D
382 528 #define ATPHY_DBG_DATA 0x1E
383 529
530 +/* From Freebsd if_alcreg.h */
531 +#define MII_ANA_CFG0 0x00
532 +#define ANA_RESTART_CAL 0x0001
533 +#define ANA_MANUL_SWICH_ON_MASK 0x001E
534 +#define ANA_MAN_ENABLE 0x0020
535 +#define ANA_SEL_HSP 0x0040
536 +#define ANA_EN_HB 0x0080
537 +#define ANA_EN_HBIAS 0x0100
538 +#define ANA_OEN_125M 0x0200
539 +#define ANA_EN_LCKDT 0x0400
540 +#define ANA_LCKDT_PHY 0x0800
541 +#define ANA_AFE_MODE 0x1000
542 +#define ANA_VCO_SLOW 0x2000
543 +#define ANA_VCO_FAST 0x4000
544 +#define ANA_SEL_CLK125M_DSP 0x8000
545 +#define ANA_MANUL_SWICH_ON_SHIFT 1
546 +
547 +#define MII_ANA_CFG4 0x04
548 +#define ANA_IECHO_ADJ_MASK 0x0F
549 +#define ANA_IECHO_ADJ_3_MASK 0x000F
550 +#define ANA_IECHO_ADJ_2_MASK 0x00F0
551 +#define ANA_IECHO_ADJ_1_MASK 0x0F00
552 +#define ANA_IECHO_ADJ_0_MASK 0xF000
553 +#define ANA_IECHO_ADJ_3_SHIFT 0
554 +#define ANA_IECHO_ADJ_2_SHIFT 4
555 +#define ANA_IECHO_ADJ_1_SHIFT 8
556 +#define ANA_IECHO_ADJ_0_SHIFT 12
557 +
558 +#define MII_ANA_CFG5 0x05
559 +#define ANA_SERDES_CDR_BW_MASK 0x0003
560 +#define ANA_MS_PAD_DBG 0x0004
561 +#define ANA_SPEEDUP_DBG 0x0008
562 +#define ANA_SERDES_TH_LOS_MASK 0x0030
563 +#define ANA_SERDES_EN_DEEM 0x0040
564 +#define ANA_SERDES_TXELECIDLE 0x0080
565 +#define ANA_SERDES_BEACON 0x0100
566 +#define ANA_SERDES_HALFTXDR 0x0200
567 +#define ANA_SERDES_SEL_HSP 0x0400
568 +#define ANA_SERDES_EN_PLL 0x0800
569 +#define ANA_SERDES_EN 0x1000
570 +#define ANA_SERDES_EN_LCKDT 0x2000
571 +#define ANA_SERDES_CDR_BW_SHIFT 0
572 +#define ANA_SERDES_TH_LOS_SHIFT 4
573 +
574 +#define MII_ANA_CFG11 0x0B
575 +#define ANA_PS_HIB_EN 0x8000
576 +
577 +#define MII_ANA_CFG18 0x12
578 +#define ANA_TEST_MODE_10BT_01MASK 0x0003
579 +#define ANA_LOOP_SEL_10BT 0x0004
580 +#define ANA_RGMII_MODE_SW 0x0008
581 +#define ANA_EN_LONGECABLE 0x0010
582 +#define ANA_TEST_MODE_10BT_2 0x0020
583 +#define ANA_EN_10BT_IDLE 0x0400
584 +#define ANA_EN_MASK_TB 0x0800
585 +#define ANA_TRIGGER_SEL_TIMER_MASK 0x3000
586 +#define ANA_INTERVAL_SEL_TIMER_MASK 0xC000
587 +#define ANA_TEST_MODE_10BT_01SHIFT 0
588 +#define ANA_TRIGGER_SEL_TIMER_SHIFT 12
589 +#define ANA_INTERVAL_SEL_TIMER_SHIFT 14
590 +
591 +#define MII_ANA_CFG41 0x29
592 +#define ANA_TOP_PS_EN 0x8000
593 +
594 +#define MII_ANA_CFG54 0x36
595 +#define ANA_LONG_CABLE_TH_100_MASK 0x003F
596 +#define ANA_DESERVED 0x0040
597 +#define ANA_EN_LIT_CH 0x0080
598 +#define ANA_SHORT_CABLE_TH_100_MASK 0x3F00
599 +#define ANA_BP_BAD_LINK_ACCUM 0x4000
600 +#define ANA_BP_SMALL_BW 0x8000
601 +#define ANA_LONG_CABLE_TH_100_SHIFT 0
602 +#define ANA_SHORT_CABLE_TH_100_SHIFT 8
603 +/* End Freebsd if_alcreg.h */
604 +
384 605 #define ATGE_TD_EOP 0x00000001
385 606 #define ATGE_TD_BUFLEN_MASK 0x00003FFF
386 607 #define ATGE_TD_BUFLEN_SHIFT 0
387 608 #define ATGE_TX_BYTES(x) \
388 609 (((x) << ATGE_TD_BUFLEN_SHIFT) & ATGE_TD_BUFLEN_MASK)
389 610
390 611 #define ATGE_ISR_ACK_GPHY 19
391 612
392 613 #ifdef __cplusplus
393 614 }
394 615 #endif
395 616
396 617 #endif /* _ATGE_CMN_REG_H */
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