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212 Atheros AR8132 / L1c Gigabit Ethernet Adapter
@@ -17,13 +17,41 @@
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
+ * Copyright (c) 2012 Gary Mills
+ *
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
+/*
+ * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
#ifndef _ATGE_CMN_REG_H
#define _ATGE_CMN_REG_H
#ifdef __cplusplus
@@ -41,19 +69,27 @@
#define ATGE_PAR0 0x1488
#define ATGE_PAR1 0x148C
#define ATGE_MASTER_CFG 0x1400
#define MASTER_RESET 0x00000001
-#define MASTER_MTIMER_ENB 0x00000002
#define MASTER_ITIMER_ENB 0x00000004 /* L1 */
-#define MASTER_IM_TX_TIMER_ENB 0x00000004 /* L1E */
#define MASTER_MANUAL_INT_ENB 0x00000008
-#define MASTER_IM_RX_TIMER_ENB 0x00000020
#define MASTER_INT_RDCLR 0x00000040
+#define MASTER_SA_TIMER_ENB 0x00000080
+#define MASTER_MTIMER_ENB 0x00000100
#define MASTER_LED_MODE 0x00000200
+#define MASTER_MANUAL_INTR_ENB 0x00000200
+#define MASTER_IM_TX_TIMER_ENB 0x00000400
+#define MASTER_IM_RX_TIMER_ENB 0x00000800
+#define MASTER_CLK_SEL_DIS 0x00001000
+#define MASTER_CLK_SWH_MODE 0x00002000
+#define MASTER_INTR_RD_CLR 0x00004000
#define MASTER_CHIP_REV_MASK 0x00FF0000
#define MASTER_CHIP_ID_MASK 0xFF000000
+#define MASTER_CHIP_ID_MASKXXX 0x7F000000 /* XXX */
+#define MASTER_OTP_SEL 0x80000000
+#define MASTER_TEST_MODE_SHIFT 2
#define MASTER_CHIP_REV_SHIFT 16
#define MASTER_CHIP_ID_SHIFT 24
#define ATGE_RESET_TIMEOUT 100
@@ -65,10 +101,16 @@
#define IDLE_STATUS_DMARD 0x00000010
#define IDLE_STATUS_DMAWR 0x00000020
#define IDLE_STATUS_SMB 0x00000040
#define IDLE_STATUS_CMB 0x00000080
+#define ATGE_SERDES_LOCK 0x1424
+#define SERDES_LOCK_DET 0x00000001
+#define SERDES_LOCK_DET_ENB 0x00000002
+#define SERDES_MAC_CLK_SLOWDOWN 0x00020000
+#define SERDES_PHY_CLK_SLOWDOWN 0x00040000
+
#define ATGE_MAC_CFG 0x1480
#define ATGE_CFG_TX_ENB 0x00000001
#define ATGE_CFG_RX_ENB 0x00000002
#define ATGE_CFG_TX_FC 0x00000004
#define ATGE_CFG_RX_FC 0x00000008
@@ -91,10 +133,13 @@
#define ATGE_CFG_TX_JUMBO_ENB 0x00800000
#define ATGE_CFG_RXCSUM_ENB 0x01000000
#define ATGE_CFG_ALLMULTI 0x02000000
#define ATGE_CFG_BCAST 0x04000000
#define ATGE_CFG_DBG 0x08000000
+#define ATGE_CFG_SINGLE_PAUSE_ENB 0x10000000
+#define ATGE_CFG_HASH_ALG_CRC32 0x20000000
+#define ATGE_CFG_SPEED_MODE_SW 0x40000000
#define ATGE_CFG_PREAMBLE_SHIFT 10
#define ATGE_CFG_PREAMBLE_DEFAULT 7
/*
* Interrupt related registers.
@@ -114,11 +159,11 @@
#define INTR_DMA_RD_TO_RST 0x00000400
#define INTR_DMA_WR_TO_RST 0x00000800
#define INTR_GPHY 0x00001000
#define INTR_RX_PKT 0x00010000
#define INTR_TX_PKT 0x00020000
-#define INTR_TX_DMA 0x00040000
+#define INTR_TX_DMA 0x00040000 /* L1 intr status */
#define INTR_MAC_RX 0x00400000
#define INTR_MAC_TX 0x00800000
#define INTR_UNDERRUN 0x01000000
#define INTR_FRAME_ERROR 0x02000000
#define INTR_FRAME_OK 0x04000000
@@ -131,13 +176,10 @@
/* L1E intr status */
#define INTR_RX_PKT1 0x00080000
#define INTR_RX_PKT2 0x00100000
#define INTR_RX_PKT3 0x00200000
-/* L1 intr status */
-#define INTR_TX_DMA 0x00040000
-
/*
* L1E specific errors. We keep it here since some errors are common for
* both L1 and L1E chip.
*
*/
@@ -156,15 +198,10 @@
#define TXQ_CFG_TPD_BURST_DEFAULT 4
#define TXQ_CFG_TX_FIFO_BURST_SHIFT 16
#define TXQ_CFG_TX_FIFO_BURST_DEFAULT 256
/*
- * RXQ CFG register.
- */
-#define ATGE_RXQ_CFG 0x15A0
-
-/*
* Common registers for DMA CFG.
*/
#define ATGE_DMA_CFG 0x15C0
#define DMA_CFG_IN_ORDER 0x00000001
#define DMA_CFG_ENH_ORDER 0x00000002
@@ -235,10 +272,117 @@
#define DESC_TPD_CNT_SHIFT 0
#define ATGE_DMA_BLOCK 0x1534
#define DMA_BLOCK_LOAD 0x00000001
+/* From Freebsd if_alcreg.h */
+/* 0x0000 - 0x02FF : PCIe configuration space */
+
+#define ATGE_PEX_UNC_ERR_SEV 0x10C
+#define PEX_UNC_ERR_SEV_TRN 0x00000001
+#define PEX_UNC_ERR_SEV_DLP 0x00000010
+#define PEX_UNC_ERR_SEV_PSN_TLP 0x00001000
+#define PEX_UNC_ERR_SEV_FCP 0x00002000
+#define PEX_UNC_ERR_SEV_CPL_TO 0x00004000
+#define PEX_UNC_ERR_SEV_CA 0x00008000
+#define PEX_UNC_ERR_SEV_UC 0x00010000
+#define PEX_UNC_ERR_SEV_ROV 0x00020000
+#define PEX_UNC_ERR_SEV_MLFP 0x00040000
+#define PEX_UNC_ERR_SEV_ECRC 0x00080000
+#define PEX_UNC_ERR_SEV_UR 0x00100000
+
+#define ATGE_PCIE_PHYMISC 0x1000
+#define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004
+
+#define ATGE_PCIE_PHYMISC2 0x1004
+#define PCIE_PHYMISC2_SERDES_CDR_MASK 0x00030000
+#define PCIE_PHYMISC2_SERDES_TH_MASK 0x000C0000
+#define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16
+#define PCIE_PHYMISC2_SERDES_TH_SHIFT 18
+
+#define ATGE_LTSSM_ID_CFG 0x12FC
+#define LTSSM_ID_WRO_ENB 0x00001000
+
+#define ATGE_SMB_STAT_TIMER 0x15C4
+#define SMB_STAT_TIMER_MASK 0x00FFFFFF
+#define SMB_STAT_TIMER_SHIFT 0
+
+#define ATGE_CMB_TD_THRESH 0x15C8
+#define CMB_TD_THRESH_MASK 0x0000FFFF
+#define CMB_TD_THRESH_SHIFT 0
+
+#define ATGE_CMB_TX_TIMER 0x15CC
+#define CMB_TX_TIMER_MASK 0x0000FFFF
+#define CMB_TX_TIMER_SHIFT 0
+
+#define ATGE_MBOX_RD0_PROD_IDX 0x15E0
+
+#define ATGE_MBOX_RD1_PROD_IDX 0x15E4
+
+#define ATGE_MBOX_RD2_PROD_IDX 0x15E8
+
+#define ATGE_MBOX_RD3_PROD_IDX 0x15EC
+
+#define ATGE_MBOX_RD_PROD_MASK 0x0000FFFF
+#define MBOX_RD_PROD_SHIFT 0
+
+#define ATGE_MBOX_TD_PROD_IDX 0x15F0
+#define MBOX_TD_PROD_HI_IDX_MASK 0x0000FFFF
+#define MBOX_TD_PROD_LO_IDX_MASK 0xFFFF0000
+#define MBOX_TD_PROD_HI_IDX_SHIFT 0
+#define MBOX_TD_PROD_LO_IDX_SHIFT 16
+
+#define ATGE_MBOX_TD_CONS_IDX 0x15F4
+#define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF
+#define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000
+#define MBOX_TD_CONS_HI_IDX_SHIFT 0
+#define MBOX_TD_CONS_LO_IDX_SHIFT 16
+
+#define ATGE_MBOX_RD01_CONS_IDX 0x15F8
+#define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF
+#define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000
+#define MBOX_RD0_CONS_IDX_SHIFT 0
+#define MBOX_RD1_CONS_IDX_SHIFT 16
+
+#define ATGE_MBOX_RD23_CONS_IDX 0x15FC
+#define MBOX_RD2_CONS_IDX_MASK 0x0000FFFF
+#define MBOX_RD3_CONS_IDX_MASK 0xFFFF0000
+#define MBOX_RD2_CONS_IDX_SHIFT 0
+#define MBOX_RD3_CONS_IDX_SHIFT 16
+
+#define ATGE_INTR_RETRIG_TIMER 0x1608
+#define INTR_RETRIG_TIMER_MASK 0x0000FFFF
+#define INTR_RETRIG_TIMER_SHIFT 0
+
+#define ATGE_HDS_CFG 0x160C
+#define HDS_CFG_ENB 0x00000001
+#define HDS_CFG_BACKFILLSIZE_MASK 0x000FFF00
+#define HDS_CFG_MAX_HDRSIZE_MASK 0xFFF00000
+#define HDS_CFG_BACKFILLSIZE_SHIFT 8
+#define HDS_CFG_MAX_HDRSIZE_SHIFT 20
+
+/* AR813x/AR815x registers for MAC statistics */
+#define ATGE_RX_MIB_BASE 0x1700
+
+#define ATGE_TX_MIB_BASE 0x1760
+
+#define ATGE_CLK_GATING_CFG 0x1814
+#define CLK_GATING_DMAW_ENB 0x0001
+#define CLK_GATING_DMAR_ENB 0x0002
+#define CLK_GATING_TXQ_ENB 0x0004
+#define CLK_GATING_RXQ_ENB 0x0008
+#define CLK_GATING_TXMAC_ENB 0x0010
+#define CLK_GATING_RXMAC_ENB 0x0020
+
+#define ATGE_DEBUG_DATA0 0x1900
+
+#define ATGE_DEBUG_DATA1 0x1904
+
+#define ATGE_MII_DBG_ADDR 0x1D
+#define ATGE_MII_DBG_DATA 0x1E
+/* End Freebsd if_alcreg.h */
+
#define ATGE_MBOX 0x15F0
#define MBOX_RD_PROD_IDX_MASK 0x000007FF
#define MBOX_RRD_CONS_IDX_MASK 0x003FF800
#define MBOX_TD_PROD_IDX_MASK 0xFFC00000
#define MBOX_RD_PROD_IDX_SHIFT 0
@@ -347,12 +491,14 @@
#define RXQ_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF
#define RXQ_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF000
#define RXQ_FIFO_PAUSE_THRESH_LO_SHIFT 0
#define RXQ_FIFO_PAUSE_THRESH_HI_SHIFT 16
+/*
+ * RXQ CFG register.
+ */
#define ATGE_RXQ_CFG 0x15A0
-#define ATGE_TXQ_CFG 0x1580
#define RXQ_CFG_ALIGN_32 0x00000000
#define RXQ_CFG_ALIGN_64 0x00000001
#define RXQ_CFG_ALIGN_128 0x00000002
#define RXQ_CFG_ALIGN_256 0x00000003
#define RXQ_CFG_QUEUE1_ENB 0x00000010
@@ -379,10 +525,85 @@
#define ATGE_MAR1 0x1494
#define ATPHY_DBG_ADDR 0x1D
#define ATPHY_DBG_DATA 0x1E
+/* From Freebsd if_alcreg.h */
+#define MII_ANA_CFG0 0x00
+#define ANA_RESTART_CAL 0x0001
+#define ANA_MANUL_SWICH_ON_MASK 0x001E
+#define ANA_MAN_ENABLE 0x0020
+#define ANA_SEL_HSP 0x0040
+#define ANA_EN_HB 0x0080
+#define ANA_EN_HBIAS 0x0100
+#define ANA_OEN_125M 0x0200
+#define ANA_EN_LCKDT 0x0400
+#define ANA_LCKDT_PHY 0x0800
+#define ANA_AFE_MODE 0x1000
+#define ANA_VCO_SLOW 0x2000
+#define ANA_VCO_FAST 0x4000
+#define ANA_SEL_CLK125M_DSP 0x8000
+#define ANA_MANUL_SWICH_ON_SHIFT 1
+
+#define MII_ANA_CFG4 0x04
+#define ANA_IECHO_ADJ_MASK 0x0F
+#define ANA_IECHO_ADJ_3_MASK 0x000F
+#define ANA_IECHO_ADJ_2_MASK 0x00F0
+#define ANA_IECHO_ADJ_1_MASK 0x0F00
+#define ANA_IECHO_ADJ_0_MASK 0xF000
+#define ANA_IECHO_ADJ_3_SHIFT 0
+#define ANA_IECHO_ADJ_2_SHIFT 4
+#define ANA_IECHO_ADJ_1_SHIFT 8
+#define ANA_IECHO_ADJ_0_SHIFT 12
+
+#define MII_ANA_CFG5 0x05
+#define ANA_SERDES_CDR_BW_MASK 0x0003
+#define ANA_MS_PAD_DBG 0x0004
+#define ANA_SPEEDUP_DBG 0x0008
+#define ANA_SERDES_TH_LOS_MASK 0x0030
+#define ANA_SERDES_EN_DEEM 0x0040
+#define ANA_SERDES_TXELECIDLE 0x0080
+#define ANA_SERDES_BEACON 0x0100
+#define ANA_SERDES_HALFTXDR 0x0200
+#define ANA_SERDES_SEL_HSP 0x0400
+#define ANA_SERDES_EN_PLL 0x0800
+#define ANA_SERDES_EN 0x1000
+#define ANA_SERDES_EN_LCKDT 0x2000
+#define ANA_SERDES_CDR_BW_SHIFT 0
+#define ANA_SERDES_TH_LOS_SHIFT 4
+
+#define MII_ANA_CFG11 0x0B
+#define ANA_PS_HIB_EN 0x8000
+
+#define MII_ANA_CFG18 0x12
+#define ANA_TEST_MODE_10BT_01MASK 0x0003
+#define ANA_LOOP_SEL_10BT 0x0004
+#define ANA_RGMII_MODE_SW 0x0008
+#define ANA_EN_LONGECABLE 0x0010
+#define ANA_TEST_MODE_10BT_2 0x0020
+#define ANA_EN_10BT_IDLE 0x0400
+#define ANA_EN_MASK_TB 0x0800
+#define ANA_TRIGGER_SEL_TIMER_MASK 0x3000
+#define ANA_INTERVAL_SEL_TIMER_MASK 0xC000
+#define ANA_TEST_MODE_10BT_01SHIFT 0
+#define ANA_TRIGGER_SEL_TIMER_SHIFT 12
+#define ANA_INTERVAL_SEL_TIMER_SHIFT 14
+
+#define MII_ANA_CFG41 0x29
+#define ANA_TOP_PS_EN 0x8000
+
+#define MII_ANA_CFG54 0x36
+#define ANA_LONG_CABLE_TH_100_MASK 0x003F
+#define ANA_DESERVED 0x0040
+#define ANA_EN_LIT_CH 0x0080
+#define ANA_SHORT_CABLE_TH_100_MASK 0x3F00
+#define ANA_BP_BAD_LINK_ACCUM 0x4000
+#define ANA_BP_SMALL_BW 0x8000
+#define ANA_LONG_CABLE_TH_100_SHIFT 0
+#define ANA_SHORT_CABLE_TH_100_SHIFT 8
+/* End Freebsd if_alcreg.h */
+
#define ATGE_TD_EOP 0x00000001
#define ATGE_TD_BUFLEN_MASK 0x00003FFF
#define ATGE_TD_BUFLEN_SHIFT 0
#define ATGE_TX_BYTES(x) \
(((x) << ATGE_TD_BUFLEN_SHIFT) & ATGE_TD_BUFLEN_MASK)