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--- old/usr/src/uts/i86pc/os/pci_cfgspace.c
+++ new/usr/src/uts/i86pc/os/pci_cfgspace.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 */
25 25
26 26 /*
27 27 * PCI configuration space access routines
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28 28 */
29 29
30 30 #include <sys/systm.h>
31 31 #include <sys/psw.h>
32 32 #include <sys/bootconf.h>
33 33 #include <sys/reboot.h>
34 34 #include <sys/pci_impl.h>
35 35 #include <sys/pci_cfgspace.h>
36 36 #include <sys/pci_cfgspace_impl.h>
37 37 #include <sys/pci_cfgacc.h>
38 +#include <sys/machsystm.h>
38 39 #if defined(__xpv)
39 40 #include <sys/hypervisor.h>
40 41 #endif
41 42
42 -#if defined(__xpv)
43 43 int pci_max_nbus = 0xFE;
44 -#endif
45 44 int pci_bios_cfg_type = PCI_MECHANISM_UNKNOWN;
46 45 int pci_bios_maxbus;
47 46 int pci_bios_mech;
48 47 int pci_bios_vers;
49 48
50 49 /*
51 50 * These two variables can be used to force a configuration mechanism or
52 51 * to force which function is used to probe for the presence of the PCI bus.
53 52 */
54 53 int PCI_CFG_TYPE = 0;
55 54 int PCI_PROBE_TYPE = 0;
56 55
57 56 /*
58 57 * No valid mcfg_mem_base by default, and accessing pci config space
59 58 * in mem-mapped way is disabled.
60 59 */
61 60 uint64_t mcfg_mem_base = 0;
62 61 uint8_t mcfg_bus_start = 0;
63 62 uint8_t mcfg_bus_end = 0xff;
64 63
65 64 /*
66 65 * Maximum offset in config space when not using MMIO
67 66 */
68 67 uint_t pci_iocfg_max_offset = 0xff;
69 68
70 69 /*
71 70 * These function pointers lead to the actual implementation routines
72 71 * for configuration space access. Normally they lead to either the
73 72 * pci_mech1_* or pci_mech2_* routines, but they can also lead to
74 73 * routines that work around chipset bugs.
75 74 * These functions are accessing pci config space via I/O way.
76 75 * Pci_cfgacc_get/put functions shoul be used as more common interfaces,
77 76 * which also provide accessing pci config space via mem-mapped way.
78 77 */
79 78 uint8_t (*pci_getb_func)(int bus, int dev, int func, int reg);
80 79 uint16_t (*pci_getw_func)(int bus, int dev, int func, int reg);
81 80 uint32_t (*pci_getl_func)(int bus, int dev, int func, int reg);
82 81 void (*pci_putb_func)(int bus, int dev, int func, int reg, uint8_t val);
83 82 void (*pci_putw_func)(int bus, int dev, int func, int reg, uint16_t val);
84 83 void (*pci_putl_func)(int bus, int dev, int func, int reg, uint32_t val);
85 84
86 85 extern void (*pci_cfgacc_acc_p)(pci_cfgacc_req_t *req);
87 86
88 87 /*
89 88 * Internal routines
90 89 */
91 90 static int pci_check(void);
92 91
93 92 #if !defined(__xpv)
94 93 static int pci_check_bios(void);
95 94 static int pci_get_cfg_type(void);
96 95 #endif
97 96
98 97 /* for legacy io-based config space access */
99 98 kmutex_t pcicfg_mutex;
100 99
101 100 /* for mmio-based config space access */
102 101 kmutex_t pcicfg_mmio_mutex;
103 102
104 103 /* ..except Orion and Neptune, which have to have their own */
105 104 kmutex_t pcicfg_chipset_mutex;
106 105
107 106 void
108 107 pci_cfgspace_init(void)
109 108 {
110 109 mutex_init(&pcicfg_mutex, NULL, MUTEX_SPIN,
111 110 (ddi_iblock_cookie_t)ipltospl(15));
112 111 mutex_init(&pcicfg_mmio_mutex, NULL, MUTEX_SPIN,
113 112 (ddi_iblock_cookie_t)ipltospl(DISP_LEVEL));
114 113 mutex_init(&pcicfg_chipset_mutex, NULL, MUTEX_SPIN,
115 114 (ddi_iblock_cookie_t)ipltospl(15));
116 115 if (!pci_check()) {
117 116 mutex_destroy(&pcicfg_mutex);
118 117 mutex_destroy(&pcicfg_mmio_mutex);
119 118 mutex_destroy(&pcicfg_chipset_mutex);
120 119 }
121 120 }
122 121
123 122 /*
124 123 * This code determines if this system supports PCI/PCIE and which
125 124 * type of configuration access method is used
126 125 */
127 126 static int
128 127 pci_check(void)
129 128 {
130 129 uint64_t ecfginfo[4];
131 130
132 131 /*
133 132 * Only do this once. NB: If this is not a PCI system, and we
134 133 * get called twice, we can't detect it and will probably die
135 134 * horribly when we try to ask the BIOS whether PCI is present.
136 135 * This code is safe *ONLY* during system startup when the
137 136 * BIOS is still available.
138 137 */
139 138 if (pci_bios_cfg_type != PCI_MECHANISM_UNKNOWN)
140 139 return (TRUE);
141 140
142 141 #if defined(__xpv)
143 142 /*
144 143 * only support PCI config mechanism 1 in i86xpv. This should be fine
145 144 * since the other ones are workarounds for old broken H/W which won't
146 145 * be supported in i86xpv anyway.
147 146 */
148 147 if (DOMAIN_IS_INITDOMAIN(xen_info)) {
149 148 pci_bios_cfg_type = PCI_MECHANISM_1;
150 149 pci_getb_func = pci_mech1_getb;
151 150 pci_getw_func = pci_mech1_getw;
152 151 pci_getl_func = pci_mech1_getl;
153 152 pci_putb_func = pci_mech1_putb;
154 153 pci_putw_func = pci_mech1_putw;
155 154 pci_putl_func = pci_mech1_putl;
156 155
157 156 /*
158 157 * Since we can't get the BIOS info in i86xpv, we will do an
159 158 * exhaustive search of all PCI buses. We have to do this until
160 159 * we start using the PCI information in ACPI.
161 160 */
162 161 pci_bios_maxbus = pci_max_nbus;
163 162 }
164 163 #else /* !__xpv */
165 164
166 165 pci_bios_cfg_type = pci_check_bios();
167 166
168 167 if (pci_bios_cfg_type == PCI_MECHANISM_NONE)
169 168 pci_bios_cfg_type = PCI_MECHANISM_1; /* default to mech 1 */
170 169
171 170 switch (pci_get_cfg_type()) {
172 171 case PCI_MECHANISM_1:
173 172 if (pci_is_broken_orion()) {
174 173 pci_getb_func = pci_orion_getb;
175 174 pci_getw_func = pci_orion_getw;
176 175 pci_getl_func = pci_orion_getl;
177 176 pci_putb_func = pci_orion_putb;
178 177 pci_putw_func = pci_orion_putw;
179 178 pci_putl_func = pci_orion_putl;
180 179 } else if (pci_check_amd_ioecs()) {
181 180 pci_getb_func = pci_mech1_amd_getb;
182 181 pci_getw_func = pci_mech1_amd_getw;
183 182 pci_getl_func = pci_mech1_amd_getl;
184 183 pci_putb_func = pci_mech1_amd_putb;
185 184 pci_putw_func = pci_mech1_amd_putw;
186 185 pci_putl_func = pci_mech1_amd_putl;
187 186 pci_iocfg_max_offset = 0xfff;
188 187 } else {
189 188 pci_getb_func = pci_mech1_getb;
190 189 pci_getw_func = pci_mech1_getw;
191 190 pci_getl_func = pci_mech1_getl;
192 191 pci_putb_func = pci_mech1_putb;
193 192 pci_putw_func = pci_mech1_putw;
194 193 pci_putl_func = pci_mech1_putl;
195 194 }
196 195 break;
197 196
198 197 case PCI_MECHANISM_2:
199 198 if (pci_check_neptune()) {
200 199 /*
201 200 * The BIOS for some systems with the Intel
202 201 * Neptune chipset seem to default to #2 even
203 202 * though the chipset can do #1. Override
204 203 * the BIOS so that MP systems will work
205 204 * correctly.
206 205 */
207 206
208 207 pci_getb_func = pci_neptune_getb;
209 208 pci_getw_func = pci_neptune_getw;
210 209 pci_getl_func = pci_neptune_getl;
211 210 pci_putb_func = pci_neptune_putb;
212 211 pci_putw_func = pci_neptune_putw;
213 212 pci_putl_func = pci_neptune_putl;
214 213 } else {
215 214 pci_getb_func = pci_mech2_getb;
216 215 pci_getw_func = pci_mech2_getw;
217 216 pci_getl_func = pci_mech2_getl;
218 217 pci_putb_func = pci_mech2_putb;
219 218 pci_putw_func = pci_mech2_putw;
220 219 pci_putl_func = pci_mech2_putl;
221 220 }
222 221 break;
223 222
224 223 default:
225 224 return (FALSE);
226 225 }
227 226 #endif /* __xpv */
228 227
229 228 /*
230 229 * Try to get a valid mcfg_mem_base in early boot
231 230 * If failed, leave mem-mapped pci config space accessing disabled
232 231 * until pci boot code (pci_autoconfig) makes sure this is a PCIE
233 232 * platform.
234 233 */
235 234 if (do_bsys_getprop(NULL, MCFG_PROPNAME, ecfginfo) != -1) {
236 235 mcfg_mem_base = ecfginfo[0];
237 236 mcfg_bus_start = ecfginfo[2];
238 237 mcfg_bus_end = ecfginfo[3];
239 238 }
240 239
241 240 /* See pci_cfgacc.c */
242 241 pci_cfgacc_acc_p = pci_cfgacc_acc;
243 242
244 243 return (TRUE);
245 244 }
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246 245
247 246 #if !defined(__xpv)
248 247
249 248 static int
250 249 pci_check_bios(void)
251 250 {
252 251 struct bop_regs regs;
253 252 uint32_t carryflag;
254 253 uint16_t ax, dx;
255 254
255 + if (!bios_calls_available) {
256 + /*
257 + * If this system does not support BIOS calls, we must fall
258 + * back to default values and a search of all of the possible
259 + * PCI buses.
260 + */
261 + pci_bios_mech = 1;
262 + pci_bios_vers = 0;
263 + pci_bios_maxbus = pci_max_nbus;
264 + return (PCI_MECHANISM_1);
265 + }
266 +
256 267 bzero(®s, sizeof (regs));
257 268 regs.eax.word.ax = (PCI_FUNCTION_ID << 8) | PCI_BIOS_PRESENT;
258 269
259 270 BOP_DOINT(bootops, 0x1a, ®s);
260 271 carryflag = regs.eflags & PS_C;
261 272 ax = regs.eax.word.ax;
262 273 dx = regs.edx.word.dx;
263 274
264 275 /* the carry flag must not be set */
265 276 if (carryflag != 0)
266 277 return (PCI_MECHANISM_NONE);
267 278
268 279 if (dx != ('P' | 'C'<<8))
269 280 return (PCI_MECHANISM_NONE);
270 281
271 282 /* ah (the high byte of ax) must be zero */
272 283 if ((ax & 0xff00) != 0)
273 284 return (PCI_MECHANISM_NONE);
274 285
275 286 pci_bios_mech = (ax & 0x3);
276 287 pci_bios_vers = regs.ebx.word.bx;
277 288 pci_bios_maxbus = (regs.ecx.word.cx & 0xff);
278 289
279 290 switch (pci_bios_mech) {
280 291 default: /* ?!? */
281 292 case 0: /* supports neither? */
282 293 return (PCI_MECHANISM_NONE);
283 294
284 295 case 1:
285 296 case 3: /* supports both */
286 297 return (PCI_MECHANISM_1);
287 298
288 299 case 2:
289 300 return (PCI_MECHANISM_2);
290 301 }
291 302 }
292 303
293 304 static int
294 305 pci_get_cfg_type(void)
295 306 {
296 307 /* Check to see if the config mechanism has been set in /etc/system */
297 308 switch (PCI_CFG_TYPE) {
298 309 default:
299 310 case 0:
300 311 break;
301 312 case 1:
302 313 return (PCI_MECHANISM_1);
303 314 case 2:
304 315 return (PCI_MECHANISM_2);
305 316 case -1:
306 317 return (PCI_MECHANISM_NONE);
307 318 }
308 319
309 320 /* call one of the PCI detection algorithms */
310 321 switch (PCI_PROBE_TYPE) {
311 322 default:
312 323 case 0:
313 324 /* From pci_check() and pci_check_bios() */
314 325 return (pci_bios_cfg_type);
315 326 case -1:
316 327 return (PCI_MECHANISM_NONE);
317 328 }
318 329 }
319 330
320 331 #endif /* __xpv */
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