1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25
26 /*
27 * PCI configuration space access routines
28 */
29
30 #include <sys/systm.h>
31 #include <sys/psw.h>
32 #include <sys/bootconf.h>
33 #include <sys/reboot.h>
34 #include <sys/pci_impl.h>
35 #include <sys/pci_cfgspace.h>
36 #include <sys/pci_cfgspace_impl.h>
37 #include <sys/pci_cfgacc.h>
38 #include <sys/machsystm.h>
39 #if defined(__xpv)
40 #include <sys/hypervisor.h>
41 #endif
42
43 int pci_max_nbus = 0xFE;
44 int pci_bios_cfg_type = PCI_MECHANISM_UNKNOWN;
45 int pci_bios_maxbus;
46 int pci_bios_mech;
47 int pci_bios_vers;
48
49 /*
50 * These two variables can be used to force a configuration mechanism or
51 * to force which function is used to probe for the presence of the PCI bus.
52 */
53 int PCI_CFG_TYPE = 0;
54 int PCI_PROBE_TYPE = 0;
55
56 /*
57 * No valid mcfg_mem_base by default, and accessing pci config space
58 * in mem-mapped way is disabled.
59 */
60 uint64_t mcfg_mem_base = 0;
61 uint8_t mcfg_bus_start = 0;
62 uint8_t mcfg_bus_end = 0xff;
63
64 /*
65 * Maximum offset in config space when not using MMIO
66 */
67 uint_t pci_iocfg_max_offset = 0xff;
68
69 /*
70 * These function pointers lead to the actual implementation routines
71 * for configuration space access. Normally they lead to either the
72 * pci_mech1_* or pci_mech2_* routines, but they can also lead to
73 * routines that work around chipset bugs.
74 * These functions are accessing pci config space via I/O way.
75 * Pci_cfgacc_get/put functions shoul be used as more common interfaces,
76 * which also provide accessing pci config space via mem-mapped way.
77 */
78 uint8_t (*pci_getb_func)(int bus, int dev, int func, int reg);
79 uint16_t (*pci_getw_func)(int bus, int dev, int func, int reg);
80 uint32_t (*pci_getl_func)(int bus, int dev, int func, int reg);
81 void (*pci_putb_func)(int bus, int dev, int func, int reg, uint8_t val);
82 void (*pci_putw_func)(int bus, int dev, int func, int reg, uint16_t val);
83 void (*pci_putl_func)(int bus, int dev, int func, int reg, uint32_t val);
84
85 extern void (*pci_cfgacc_acc_p)(pci_cfgacc_req_t *req);
86
87 /*
88 * Internal routines
89 */
90 static int pci_check(void);
91
92 #if !defined(__xpv)
93 static int pci_check_bios(void);
94 static int pci_get_cfg_type(void);
95 #endif
96
97 /* for legacy io-based config space access */
98 kmutex_t pcicfg_mutex;
99
100 /* for mmio-based config space access */
101 kmutex_t pcicfg_mmio_mutex;
102
103 /* ..except Orion and Neptune, which have to have their own */
104 kmutex_t pcicfg_chipset_mutex;
105
106 void
107 pci_cfgspace_init(void)
108 {
109 mutex_init(&pcicfg_mutex, NULL, MUTEX_SPIN,
110 (ddi_iblock_cookie_t)ipltospl(15));
111 mutex_init(&pcicfg_mmio_mutex, NULL, MUTEX_SPIN,
112 (ddi_iblock_cookie_t)ipltospl(DISP_LEVEL));
113 mutex_init(&pcicfg_chipset_mutex, NULL, MUTEX_SPIN,
114 (ddi_iblock_cookie_t)ipltospl(15));
115 if (!pci_check()) {
116 mutex_destroy(&pcicfg_mutex);
117 mutex_destroy(&pcicfg_mmio_mutex);
118 mutex_destroy(&pcicfg_chipset_mutex);
119 }
120 }
121
122 /*
123 * This code determines if this system supports PCI/PCIE and which
124 * type of configuration access method is used
125 */
126 static int
127 pci_check(void)
128 {
129 uint64_t ecfginfo[4];
130
131 /*
132 * Only do this once. NB: If this is not a PCI system, and we
133 * get called twice, we can't detect it and will probably die
134 * horribly when we try to ask the BIOS whether PCI is present.
135 * This code is safe *ONLY* during system startup when the
136 * BIOS is still available.
137 */
138 if (pci_bios_cfg_type != PCI_MECHANISM_UNKNOWN)
139 return (TRUE);
140
141 #if defined(__xpv)
142 /*
143 * only support PCI config mechanism 1 in i86xpv. This should be fine
144 * since the other ones are workarounds for old broken H/W which won't
145 * be supported in i86xpv anyway.
146 */
147 if (DOMAIN_IS_INITDOMAIN(xen_info)) {
148 pci_bios_cfg_type = PCI_MECHANISM_1;
149 pci_getb_func = pci_mech1_getb;
150 pci_getw_func = pci_mech1_getw;
151 pci_getl_func = pci_mech1_getl;
152 pci_putb_func = pci_mech1_putb;
153 pci_putw_func = pci_mech1_putw;
154 pci_putl_func = pci_mech1_putl;
155
156 /*
157 * Since we can't get the BIOS info in i86xpv, we will do an
158 * exhaustive search of all PCI buses. We have to do this until
159 * we start using the PCI information in ACPI.
160 */
161 pci_bios_maxbus = pci_max_nbus;
162 }
163 #else /* !__xpv */
164
165 pci_bios_cfg_type = pci_check_bios();
166
167 if (pci_bios_cfg_type == PCI_MECHANISM_NONE)
168 pci_bios_cfg_type = PCI_MECHANISM_1; /* default to mech 1 */
169
170 switch (pci_get_cfg_type()) {
171 case PCI_MECHANISM_1:
172 if (pci_is_broken_orion()) {
173 pci_getb_func = pci_orion_getb;
174 pci_getw_func = pci_orion_getw;
175 pci_getl_func = pci_orion_getl;
176 pci_putb_func = pci_orion_putb;
177 pci_putw_func = pci_orion_putw;
178 pci_putl_func = pci_orion_putl;
179 } else if (pci_check_amd_ioecs()) {
180 pci_getb_func = pci_mech1_amd_getb;
181 pci_getw_func = pci_mech1_amd_getw;
182 pci_getl_func = pci_mech1_amd_getl;
183 pci_putb_func = pci_mech1_amd_putb;
184 pci_putw_func = pci_mech1_amd_putw;
185 pci_putl_func = pci_mech1_amd_putl;
186 pci_iocfg_max_offset = 0xfff;
187 } else {
188 pci_getb_func = pci_mech1_getb;
189 pci_getw_func = pci_mech1_getw;
190 pci_getl_func = pci_mech1_getl;
191 pci_putb_func = pci_mech1_putb;
192 pci_putw_func = pci_mech1_putw;
193 pci_putl_func = pci_mech1_putl;
194 }
195 break;
196
197 case PCI_MECHANISM_2:
198 if (pci_check_neptune()) {
199 /*
200 * The BIOS for some systems with the Intel
201 * Neptune chipset seem to default to #2 even
202 * though the chipset can do #1. Override
203 * the BIOS so that MP systems will work
204 * correctly.
205 */
206
207 pci_getb_func = pci_neptune_getb;
208 pci_getw_func = pci_neptune_getw;
209 pci_getl_func = pci_neptune_getl;
210 pci_putb_func = pci_neptune_putb;
211 pci_putw_func = pci_neptune_putw;
212 pci_putl_func = pci_neptune_putl;
213 } else {
214 pci_getb_func = pci_mech2_getb;
215 pci_getw_func = pci_mech2_getw;
216 pci_getl_func = pci_mech2_getl;
217 pci_putb_func = pci_mech2_putb;
218 pci_putw_func = pci_mech2_putw;
219 pci_putl_func = pci_mech2_putl;
220 }
221 break;
222
223 default:
224 return (FALSE);
225 }
226 #endif /* __xpv */
227
228 /*
229 * Try to get a valid mcfg_mem_base in early boot
230 * If failed, leave mem-mapped pci config space accessing disabled
231 * until pci boot code (pci_autoconfig) makes sure this is a PCIE
232 * platform.
233 */
234 if (do_bsys_getprop(NULL, MCFG_PROPNAME, ecfginfo) != -1) {
235 mcfg_mem_base = ecfginfo[0];
236 mcfg_bus_start = ecfginfo[2];
237 mcfg_bus_end = ecfginfo[3];
238 }
239
240 /* See pci_cfgacc.c */
241 pci_cfgacc_acc_p = pci_cfgacc_acc;
242
243 return (TRUE);
244 }
245
246 #if !defined(__xpv)
247
248 static int
249 pci_check_bios(void)
250 {
251 struct bop_regs regs;
252 uint32_t carryflag;
253 uint16_t ax, dx;
254
255 if (!bios_calls_available) {
256 /*
257 * If this system does not support BIOS calls, we must fall
258 * back to default values and a search of all of the possible
259 * PCI buses.
260 */
261 pci_bios_mech = 1;
262 pci_bios_vers = 0;
263 pci_bios_maxbus = pci_max_nbus;
264 return (PCI_MECHANISM_1);
265 }
266
267 bzero(®s, sizeof (regs));
268 regs.eax.word.ax = (PCI_FUNCTION_ID << 8) | PCI_BIOS_PRESENT;
269
270 BOP_DOINT(bootops, 0x1a, ®s);
271 carryflag = regs.eflags & PS_C;
272 ax = regs.eax.word.ax;
273 dx = regs.edx.word.dx;
274
275 /* the carry flag must not be set */
276 if (carryflag != 0)
277 return (PCI_MECHANISM_NONE);
278
279 if (dx != ('P' | 'C'<<8))
280 return (PCI_MECHANISM_NONE);
281
282 /* ah (the high byte of ax) must be zero */
283 if ((ax & 0xff00) != 0)
284 return (PCI_MECHANISM_NONE);
285
286 pci_bios_mech = (ax & 0x3);
287 pci_bios_vers = regs.ebx.word.bx;
288 pci_bios_maxbus = (regs.ecx.word.cx & 0xff);
289
290 switch (pci_bios_mech) {
291 default: /* ?!? */
292 case 0: /* supports neither? */
293 return (PCI_MECHANISM_NONE);
294
295 case 1:
296 case 3: /* supports both */
297 return (PCI_MECHANISM_1);
298
299 case 2:
300 return (PCI_MECHANISM_2);
301 }
302 }
303
304 static int
305 pci_get_cfg_type(void)
306 {
307 /* Check to see if the config mechanism has been set in /etc/system */
308 switch (PCI_CFG_TYPE) {
309 default:
310 case 0:
311 break;
312 case 1:
313 return (PCI_MECHANISM_1);
314 case 2:
315 return (PCI_MECHANISM_2);
316 case -1:
317 return (PCI_MECHANISM_NONE);
318 }
319
320 /* call one of the PCI detection algorithms */
321 switch (PCI_PROBE_TYPE) {
322 default:
323 case 0:
324 /* From pci_check() and pci_check_bios() */
325 return (pci_bios_cfg_type);
326 case -1:
327 return (PCI_MECHANISM_NONE);
328 }
329 }
330
331 #endif /* __xpv */