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--- old/usr/src/uts/i86pc/os/mlsetup.c
+++ new/usr/src/uts/i86pc/os/mlsetup.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 2012 Gary Mills
23 23 *
24 24 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
25 25 * Copyright (c) 2011 by Delphix. All rights reserved.
26 26 * Copyright 2016 Joyent, Inc.
27 27 */
28 28 /*
29 29 * Copyright (c) 2010, Intel Corporation.
30 30 * All rights reserved.
31 31 */
32 32
33 33 #include <sys/types.h>
34 34 #include <sys/sysmacros.h>
35 35 #include <sys/disp.h>
36 36 #include <sys/promif.h>
37 37 #include <sys/clock.h>
38 38 #include <sys/cpuvar.h>
39 39 #include <sys/stack.h>
40 40 #include <vm/as.h>
41 41 #include <vm/hat.h>
42 42 #include <sys/reboot.h>
43 43 #include <sys/avintr.h>
44 44 #include <sys/vtrace.h>
45 45 #include <sys/proc.h>
46 46 #include <sys/thread.h>
47 47 #include <sys/cpupart.h>
48 48 #include <sys/pset.h>
49 49 #include <sys/copyops.h>
50 50 #include <sys/pg.h>
51 51 #include <sys/disp.h>
52 52 #include <sys/debug.h>
53 53 #include <sys/sunddi.h>
54 54 #include <sys/x86_archext.h>
55 55 #include <sys/privregs.h>
56 56 #include <sys/machsystm.h>
57 57 #include <sys/ontrap.h>
58 58 #include <sys/bootconf.h>
59 59 #include <sys/boot_console.h>
60 60 #include <sys/kdi_machimpl.h>
61 61 #include <sys/archsystm.h>
62 62 #include <sys/promif.h>
63 63 #include <sys/pci_cfgspace.h>
64 64 #include <sys/bootvfs.h>
65 65 #include <sys/tsc.h>
66 66 #ifdef __xpv
67 67 #include <sys/hypervisor.h>
68 68 #else
69 69 #include <sys/xpv_support.h>
70 70 #endif
71 71
72 72 /*
73 73 * some globals for patching the result of cpuid
74 74 * to solve problems w/ creative cpu vendors
75 75 */
76 76
77 77 extern uint32_t cpuid_feature_ecx_include;
78 78 extern uint32_t cpuid_feature_ecx_exclude;
79 79 extern uint32_t cpuid_feature_edx_include;
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80 80 extern uint32_t cpuid_feature_edx_exclude;
81 81
82 82 /*
83 83 * Set console mode
84 84 */
85 85 static void
86 86 set_console_mode(uint8_t val)
87 87 {
88 88 struct bop_regs rp = {0};
89 89
90 + if (!bios_calls_available)
91 + return;
92 +
90 93 rp.eax.byte.ah = 0x0;
91 94 rp.eax.byte.al = val;
92 95 rp.ebx.word.bx = 0x0;
93 96
94 97 BOP_DOINT(bootops, 0x10, &rp);
95 98 }
96 99
97 100
98 101 /*
99 102 * Setup routine called right before main(). Interposing this function
100 103 * before main() allows us to call it in a machine-independent fashion.
101 104 */
102 105 void
103 106 mlsetup(struct regs *rp)
104 107 {
105 108 u_longlong_t prop_value;
106 109 extern struct classfuncs sys_classfuncs;
107 110 extern disp_t cpu0_disp;
108 111 extern char t0stack[];
109 112 extern int post_fastreboot;
110 113 extern uint64_t plat_dr_options;
111 114
112 115 ASSERT_STACK_ALIGNED();
113 116
114 117 /*
115 118 * initialize cpu_self
116 119 */
117 120 cpu[0]->cpu_self = cpu[0];
118 121
119 122 #if defined(__xpv)
120 123 /*
121 124 * Point at the hypervisor's virtual cpu structure
122 125 */
123 126 cpu[0]->cpu_m.mcpu_vcpu_info = &HYPERVISOR_shared_info->vcpu_info[0];
124 127 #endif
125 128
126 129 /*
127 130 * check if we've got special bits to clear or set
128 131 * when checking cpu features
129 132 */
130 133
131 134 if (bootprop_getval("cpuid_feature_ecx_include", &prop_value) != 0)
132 135 cpuid_feature_ecx_include = 0;
133 136 else
134 137 cpuid_feature_ecx_include = (uint32_t)prop_value;
135 138
136 139 if (bootprop_getval("cpuid_feature_ecx_exclude", &prop_value) != 0)
137 140 cpuid_feature_ecx_exclude = 0;
138 141 else
139 142 cpuid_feature_ecx_exclude = (uint32_t)prop_value;
140 143
141 144 if (bootprop_getval("cpuid_feature_edx_include", &prop_value) != 0)
142 145 cpuid_feature_edx_include = 0;
143 146 else
144 147 cpuid_feature_edx_include = (uint32_t)prop_value;
145 148
146 149 if (bootprop_getval("cpuid_feature_edx_exclude", &prop_value) != 0)
147 150 cpuid_feature_edx_exclude = 0;
148 151 else
149 152 cpuid_feature_edx_exclude = (uint32_t)prop_value;
150 153
151 154 /*
152 155 * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss.
153 156 */
154 157 init_desctbls();
155 158
156 159 /*
157 160 * lgrp_init() and possibly cpuid_pass1() need PCI config
158 161 * space access
159 162 */
160 163 #if defined(__xpv)
161 164 if (DOMAIN_IS_INITDOMAIN(xen_info))
162 165 pci_cfgspace_init();
163 166 #else
164 167 pci_cfgspace_init();
165 168 /*
166 169 * Initialize the platform type from CPU 0 to ensure that
167 170 * determine_platform() is only ever called once.
168 171 */
169 172 determine_platform();
170 173 #endif
171 174
172 175 /*
173 176 * The first lightweight pass (pass0) through the cpuid data
174 177 * was done in locore before mlsetup was called. Do the next
175 178 * pass in C code.
176 179 *
177 180 * The x86_featureset is initialized here based on the capabilities
178 181 * of the boot CPU. Note that if we choose to support CPUs that have
179 182 * different feature sets (at which point we would almost certainly
180 183 * want to set the feature bits to correspond to the feature
181 184 * minimum) this value may be altered.
182 185 */
183 186 cpuid_pass1(cpu[0], x86_featureset);
184 187
185 188 #if !defined(__xpv)
186 189 if ((get_hwenv() & HW_XEN_HVM) != 0)
187 190 xen_hvm_init();
188 191
189 192 /*
190 193 * Before we do anything with the TSCs, we need to work around
191 194 * Intel erratum BT81. On some CPUs, warm reset does not
192 195 * clear the TSC. If we are on such a CPU, we will clear TSC ourselves
193 196 * here. Other CPUs will clear it when we boot them later, and the
194 197 * resulting skew will be handled by tsc_sync_master()/_slave();
195 198 * note that such skew already exists and has to be handled anyway.
196 199 *
197 200 * We do this only on metal. This same problem can occur with a
198 201 * hypervisor that does not happen to virtualise a TSC that starts from
199 202 * zero, regardless of CPU type; however, we do not expect hypervisors
200 203 * that do not virtualise TSC that way to handle writes to TSC
201 204 * correctly, either.
202 205 */
203 206 if (get_hwenv() == HW_NATIVE &&
204 207 cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
205 208 cpuid_getfamily(CPU) == 6 &&
206 209 (cpuid_getmodel(CPU) == 0x2d || cpuid_getmodel(CPU) == 0x3e) &&
207 210 is_x86_feature(x86_featureset, X86FSET_TSC)) {
208 211 (void) wrmsr(REG_TSC, 0UL);
209 212 }
210 213
211 214 /*
212 215 * Patch the tsc_read routine with appropriate set of instructions,
213 216 * depending on the processor family and architecure, to read the
214 217 * time-stamp counter while ensuring no out-of-order execution.
215 218 * Patch it while the kernel text is still writable.
216 219 *
217 220 * Note: tsc_read is not patched for intel processors whose family
218 221 * is >6 and for amd whose family >f (in case they don't support rdtscp
219 222 * instruction, unlikely). By default tsc_read will use cpuid for
220 223 * serialization in such cases. The following code needs to be
221 224 * revisited if intel processors of family >= f retains the
222 225 * instruction serialization nature of mfence instruction.
223 226 * Note: tsc_read is not patched for x86 processors which do
224 227 * not support "mfence". By default tsc_read will use cpuid for
225 228 * serialization in such cases.
226 229 *
227 230 * The Xen hypervisor does not correctly report whether rdtscp is
228 231 * supported or not, so we must assume that it is not.
229 232 */
230 233 if ((get_hwenv() & HW_XEN_HVM) == 0 &&
231 234 is_x86_feature(x86_featureset, X86FSET_TSCP))
232 235 patch_tsc_read(TSC_TSCP);
233 236 else if (cpuid_getvendor(CPU) == X86_VENDOR_AMD &&
234 237 cpuid_getfamily(CPU) <= 0xf &&
235 238 is_x86_feature(x86_featureset, X86FSET_SSE2))
236 239 patch_tsc_read(TSC_RDTSC_MFENCE);
237 240 else if (cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
238 241 cpuid_getfamily(CPU) <= 6 &&
239 242 is_x86_feature(x86_featureset, X86FSET_SSE2))
240 243 patch_tsc_read(TSC_RDTSC_LFENCE);
241 244
242 245 #endif /* !__xpv */
243 246
244 247 #if defined(__i386) && !defined(__xpv)
245 248 /*
246 249 * Some i386 processors do not implement the rdtsc instruction,
247 250 * or at least they do not implement it correctly. Patch them to
248 251 * return 0.
249 252 */
250 253 if (!is_x86_feature(x86_featureset, X86FSET_TSC))
251 254 patch_tsc_read(TSC_NONE);
252 255 #endif /* __i386 && !__xpv */
253 256
254 257 #if defined(__amd64) && !defined(__xpv)
255 258 patch_memops(cpuid_getvendor(CPU));
256 259 #endif /* __amd64 && !__xpv */
257 260
258 261 #if !defined(__xpv)
259 262 /* XXPV what, if anything, should be dorked with here under xen? */
260 263
261 264 /*
262 265 * While we're thinking about the TSC, let's set up %cr4 so that
263 266 * userland can issue rdtsc, and initialize the TSC_AUX value
264 267 * (the cpuid) for the rdtscp instruction on appropriately
265 268 * capable hardware.
266 269 */
267 270 if (is_x86_feature(x86_featureset, X86FSET_TSC))
268 271 setcr4(getcr4() & ~CR4_TSD);
269 272
270 273 if (is_x86_feature(x86_featureset, X86FSET_TSCP))
271 274 (void) wrmsr(MSR_AMD_TSCAUX, 0);
272 275
273 276 /*
274 277 * Let's get the other %cr4 stuff while we're here. Note, we defer
275 278 * enabling CR4_SMAP until startup_end(); however, that's importantly
276 279 * before we start other CPUs. That ensures that it will be synced out
277 280 * to other CPUs.
278 281 */
279 282 if (is_x86_feature(x86_featureset, X86FSET_DE))
280 283 setcr4(getcr4() | CR4_DE);
281 284
282 285 if (is_x86_feature(x86_featureset, X86FSET_SMEP))
283 286 setcr4(getcr4() | CR4_SMEP);
284 287 #endif /* __xpv */
285 288
286 289 /*
287 290 * initialize t0
288 291 */
289 292 t0.t_stk = (caddr_t)rp - MINFRAME;
290 293 t0.t_stkbase = t0stack;
291 294 t0.t_pri = maxclsyspri - 3;
292 295 t0.t_schedflag = TS_LOAD | TS_DONT_SWAP;
293 296 t0.t_procp = &p0;
294 297 t0.t_plockp = &p0lock.pl_lock;
295 298 t0.t_lwp = &lwp0;
296 299 t0.t_forw = &t0;
297 300 t0.t_back = &t0;
298 301 t0.t_next = &t0;
299 302 t0.t_prev = &t0;
300 303 t0.t_cpu = cpu[0];
301 304 t0.t_disp_queue = &cpu0_disp;
302 305 t0.t_bind_cpu = PBIND_NONE;
303 306 t0.t_bind_pset = PS_NONE;
304 307 t0.t_bindflag = (uchar_t)default_binding_mode;
305 308 t0.t_cpupart = &cp_default;
306 309 t0.t_clfuncs = &sys_classfuncs.thread;
307 310 t0.t_copyops = NULL;
308 311 THREAD_ONPROC(&t0, CPU);
309 312
310 313 lwp0.lwp_thread = &t0;
311 314 lwp0.lwp_regs = (void *)rp;
312 315 lwp0.lwp_procp = &p0;
313 316 t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1;
314 317
315 318 p0.p_exec = NULL;
316 319 p0.p_stat = SRUN;
317 320 p0.p_flag = SSYS;
318 321 p0.p_tlist = &t0;
319 322 p0.p_stksize = 2*PAGESIZE;
320 323 p0.p_stkpageszc = 0;
321 324 p0.p_as = &kas;
322 325 p0.p_lockp = &p0lock;
323 326 p0.p_brkpageszc = 0;
324 327 p0.p_t1_lgrpid = LGRP_NONE;
325 328 p0.p_tr_lgrpid = LGRP_NONE;
326 329 psecflags_default(&p0.p_secflags);
327 330
328 331 sigorset(&p0.p_ignore, &ignoredefault);
329 332
330 333 CPU->cpu_thread = &t0;
331 334 bzero(&cpu0_disp, sizeof (disp_t));
332 335 CPU->cpu_disp = &cpu0_disp;
333 336 CPU->cpu_disp->disp_cpu = CPU;
334 337 CPU->cpu_dispthread = &t0;
335 338 CPU->cpu_idle_thread = &t0;
336 339 CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE;
337 340 CPU->cpu_dispatch_pri = t0.t_pri;
338 341
339 342 CPU->cpu_id = 0;
340 343
341 344 CPU->cpu_pri = 12; /* initial PIL for the boot CPU */
342 345
343 346 /*
344 347 * The kernel doesn't use LDTs unless a process explicitly requests one.
345 348 */
346 349 p0.p_ldt_desc = null_sdesc;
347 350
348 351 /*
349 352 * Initialize thread/cpu microstate accounting
350 353 */
351 354 init_mstate(&t0, LMS_SYSTEM);
352 355 init_cpu_mstate(CPU, CMS_SYSTEM);
353 356
354 357 /*
355 358 * Initialize lists of available and active CPUs.
356 359 */
357 360 cpu_list_init(CPU);
358 361
359 362 pg_cpu_bootstrap(CPU);
360 363
361 364 /*
362 365 * Now that we have taken over the GDT, IDT and have initialized
363 366 * active CPU list it's time to inform kmdb if present.
364 367 */
365 368 if (boothowto & RB_DEBUG)
366 369 kdi_idt_sync();
367 370
368 371 /*
369 372 * Explicitly set console to text mode (0x3) if this is a boot
370 373 * post Fast Reboot, and the console is set to CONS_SCREEN_TEXT.
371 374 */
372 375 if (post_fastreboot && boot_console_type(NULL) == CONS_SCREEN_TEXT)
373 376 set_console_mode(0x3);
374 377
375 378 /*
376 379 * If requested (boot -d) drop into kmdb.
377 380 *
378 381 * This must be done after cpu_list_init() on the 64-bit kernel
379 382 * since taking a trap requires that we re-compute gsbase based
380 383 * on the cpu list.
381 384 */
382 385 if (boothowto & RB_DEBUGENTER)
383 386 kmdb_enter();
384 387
385 388 cpu_vm_data_init(CPU);
386 389
387 390 rp->r_fp = 0; /* terminate kernel stack traces! */
388 391
389 392 prom_init("kernel", (void *)NULL);
390 393
391 394 /* User-set option overrides firmware value. */
392 395 if (bootprop_getval(PLAT_DR_OPTIONS_NAME, &prop_value) == 0) {
393 396 plat_dr_options = (uint64_t)prop_value;
394 397 }
395 398 #if defined(__xpv)
396 399 /* No support of DR operations on xpv */
397 400 plat_dr_options = 0;
398 401 #else /* __xpv */
399 402 /* Flag PLAT_DR_FEATURE_ENABLED should only be set by DR driver. */
400 403 plat_dr_options &= ~PLAT_DR_FEATURE_ENABLED;
401 404 #ifndef __amd64
402 405 /* Only enable CPU/memory DR on 64 bits kernel. */
403 406 plat_dr_options &= ~PLAT_DR_FEATURE_MEMORY;
404 407 plat_dr_options &= ~PLAT_DR_FEATURE_CPU;
405 408 #endif /* __amd64 */
406 409 #endif /* __xpv */
407 410
408 411 /*
409 412 * Get value of "plat_dr_physmax" boot option.
410 413 * It overrides values calculated from MSCT or SRAT table.
411 414 */
412 415 if (bootprop_getval(PLAT_DR_PHYSMAX_NAME, &prop_value) == 0) {
413 416 plat_dr_physmax = ((uint64_t)prop_value) >> PAGESHIFT;
414 417 }
415 418
416 419 /* Get value of boot_ncpus. */
417 420 if (bootprop_getval(BOOT_NCPUS_NAME, &prop_value) != 0) {
418 421 boot_ncpus = NCPU;
419 422 } else {
420 423 boot_ncpus = (int)prop_value;
421 424 if (boot_ncpus <= 0 || boot_ncpus > NCPU)
422 425 boot_ncpus = NCPU;
423 426 }
424 427
425 428 /*
426 429 * Set max_ncpus and boot_max_ncpus to boot_ncpus if platform doesn't
427 430 * support CPU DR operations.
428 431 */
429 432 if (plat_dr_support_cpu() == 0) {
430 433 max_ncpus = boot_max_ncpus = boot_ncpus;
431 434 } else {
432 435 if (bootprop_getval(PLAT_MAX_NCPUS_NAME, &prop_value) != 0) {
433 436 max_ncpus = NCPU;
434 437 } else {
435 438 max_ncpus = (int)prop_value;
436 439 if (max_ncpus <= 0 || max_ncpus > NCPU) {
437 440 max_ncpus = NCPU;
438 441 }
439 442 if (boot_ncpus > max_ncpus) {
440 443 boot_ncpus = max_ncpus;
441 444 }
442 445 }
443 446
444 447 if (bootprop_getval(BOOT_MAX_NCPUS_NAME, &prop_value) != 0) {
445 448 boot_max_ncpus = boot_ncpus;
446 449 } else {
447 450 boot_max_ncpus = (int)prop_value;
448 451 if (boot_max_ncpus <= 0 || boot_max_ncpus > NCPU) {
449 452 boot_max_ncpus = boot_ncpus;
450 453 } else if (boot_max_ncpus > max_ncpus) {
451 454 boot_max_ncpus = max_ncpus;
452 455 }
453 456 }
454 457 }
455 458
456 459 /*
457 460 * Initialize the lgrp framework
458 461 */
459 462 lgrp_init(LGRP_INIT_STAGE1);
460 463
461 464 if (boothowto & RB_HALT) {
462 465 prom_printf("unix: kernel halted by -h flag\n");
463 466 prom_enter_mon();
464 467 }
465 468
466 469 ASSERT_STACK_ALIGNED();
467 470
468 471 /*
469 472 * Fill out cpu_ucode_info. Update microcode if necessary.
470 473 */
471 474 ucode_check(CPU);
472 475
473 476 if (workaround_errata(CPU) != 0)
474 477 panic("critical workaround(s) missing for boot cpu");
475 478 }
476 479
477 480
478 481 void
479 482 mach_modpath(char *path, const char *filename)
480 483 {
481 484 /*
482 485 * Construct the directory path from the filename.
483 486 */
484 487
485 488 int len;
486 489 char *p;
487 490 const char isastr[] = "/amd64";
488 491 size_t isalen = strlen(isastr);
489 492
490 493 len = strlen(SYSTEM_BOOT_PATH "/kernel");
491 494 (void) strcpy(path, SYSTEM_BOOT_PATH "/kernel ");
492 495 path += len + 1;
493 496
494 497 if ((p = strrchr(filename, '/')) == NULL)
495 498 return;
496 499
497 500 while (p > filename && *(p - 1) == '/')
498 501 p--; /* remove trailing '/' characters */
499 502 if (p == filename)
500 503 p++; /* so "/" -is- the modpath in this case */
501 504
502 505 /*
503 506 * Remove optional isa-dependent directory name - the module
504 507 * subsystem will put this back again (!)
505 508 */
506 509 len = p - filename;
507 510 if (len > isalen &&
508 511 strncmp(&filename[len - isalen], isastr, isalen) == 0)
509 512 p -= isalen;
510 513
511 514 /*
512 515 * "/platform/mumblefrotz" + " " + MOD_DEFPATH
513 516 */
514 517 len += (p - filename) + 1 + strlen(MOD_DEFPATH) + 1;
515 518 (void) strncpy(path, filename, p - filename);
516 519 }
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