1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 2012 Gary Mills
23 *
24 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
25 * Copyright (c) 2011 by Delphix. All rights reserved.
26 * Copyright 2016 Joyent, Inc.
27 */
28 /*
29 * Copyright (c) 2010, Intel Corporation.
30 * All rights reserved.
31 */
32
33 #include <sys/types.h>
34 #include <sys/sysmacros.h>
35 #include <sys/disp.h>
36 #include <sys/promif.h>
37 #include <sys/clock.h>
38 #include <sys/cpuvar.h>
39 #include <sys/stack.h>
40 #include <vm/as.h>
41 #include <vm/hat.h>
42 #include <sys/reboot.h>
43 #include <sys/avintr.h>
44 #include <sys/vtrace.h>
45 #include <sys/proc.h>
46 #include <sys/thread.h>
47 #include <sys/cpupart.h>
48 #include <sys/pset.h>
49 #include <sys/copyops.h>
50 #include <sys/pg.h>
51 #include <sys/disp.h>
52 #include <sys/debug.h>
53 #include <sys/sunddi.h>
54 #include <sys/x86_archext.h>
55 #include <sys/privregs.h>
56 #include <sys/machsystm.h>
57 #include <sys/ontrap.h>
58 #include <sys/bootconf.h>
59 #include <sys/boot_console.h>
60 #include <sys/kdi_machimpl.h>
61 #include <sys/archsystm.h>
62 #include <sys/promif.h>
63 #include <sys/pci_cfgspace.h>
64 #include <sys/bootvfs.h>
65 #include <sys/tsc.h>
66 #ifdef __xpv
67 #include <sys/hypervisor.h>
68 #else
69 #include <sys/xpv_support.h>
70 #endif
71
72 /*
73 * some globals for patching the result of cpuid
74 * to solve problems w/ creative cpu vendors
75 */
76
77 extern uint32_t cpuid_feature_ecx_include;
78 extern uint32_t cpuid_feature_ecx_exclude;
79 extern uint32_t cpuid_feature_edx_include;
80 extern uint32_t cpuid_feature_edx_exclude;
81
82 /*
83 * Set console mode
84 */
85 static void
86 set_console_mode(uint8_t val)
87 {
88 struct bop_regs rp = {0};
89
90 if (!bios_calls_available)
91 return;
92
93 rp.eax.byte.ah = 0x0;
94 rp.eax.byte.al = val;
95 rp.ebx.word.bx = 0x0;
96
97 BOP_DOINT(bootops, 0x10, &rp);
98 }
99
100
101 /*
102 * Setup routine called right before main(). Interposing this function
103 * before main() allows us to call it in a machine-independent fashion.
104 */
105 void
106 mlsetup(struct regs *rp)
107 {
108 u_longlong_t prop_value;
109 extern struct classfuncs sys_classfuncs;
110 extern disp_t cpu0_disp;
111 extern char t0stack[];
112 extern int post_fastreboot;
113 extern uint64_t plat_dr_options;
114
115 ASSERT_STACK_ALIGNED();
116
117 /*
118 * initialize cpu_self
119 */
120 cpu[0]->cpu_self = cpu[0];
121
122 #if defined(__xpv)
123 /*
124 * Point at the hypervisor's virtual cpu structure
125 */
126 cpu[0]->cpu_m.mcpu_vcpu_info = &HYPERVISOR_shared_info->vcpu_info[0];
127 #endif
128
129 /*
130 * check if we've got special bits to clear or set
131 * when checking cpu features
132 */
133
134 if (bootprop_getval("cpuid_feature_ecx_include", &prop_value) != 0)
135 cpuid_feature_ecx_include = 0;
136 else
137 cpuid_feature_ecx_include = (uint32_t)prop_value;
138
139 if (bootprop_getval("cpuid_feature_ecx_exclude", &prop_value) != 0)
140 cpuid_feature_ecx_exclude = 0;
141 else
142 cpuid_feature_ecx_exclude = (uint32_t)prop_value;
143
144 if (bootprop_getval("cpuid_feature_edx_include", &prop_value) != 0)
145 cpuid_feature_edx_include = 0;
146 else
147 cpuid_feature_edx_include = (uint32_t)prop_value;
148
149 if (bootprop_getval("cpuid_feature_edx_exclude", &prop_value) != 0)
150 cpuid_feature_edx_exclude = 0;
151 else
152 cpuid_feature_edx_exclude = (uint32_t)prop_value;
153
154 /*
155 * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss.
156 */
157 init_desctbls();
158
159 /*
160 * lgrp_init() and possibly cpuid_pass1() need PCI config
161 * space access
162 */
163 #if defined(__xpv)
164 if (DOMAIN_IS_INITDOMAIN(xen_info))
165 pci_cfgspace_init();
166 #else
167 pci_cfgspace_init();
168 /*
169 * Initialize the platform type from CPU 0 to ensure that
170 * determine_platform() is only ever called once.
171 */
172 determine_platform();
173 #endif
174
175 /*
176 * The first lightweight pass (pass0) through the cpuid data
177 * was done in locore before mlsetup was called. Do the next
178 * pass in C code.
179 *
180 * The x86_featureset is initialized here based on the capabilities
181 * of the boot CPU. Note that if we choose to support CPUs that have
182 * different feature sets (at which point we would almost certainly
183 * want to set the feature bits to correspond to the feature
184 * minimum) this value may be altered.
185 */
186 cpuid_pass1(cpu[0], x86_featureset);
187
188 #if !defined(__xpv)
189 if ((get_hwenv() & HW_XEN_HVM) != 0)
190 xen_hvm_init();
191
192 /*
193 * Before we do anything with the TSCs, we need to work around
194 * Intel erratum BT81. On some CPUs, warm reset does not
195 * clear the TSC. If we are on such a CPU, we will clear TSC ourselves
196 * here. Other CPUs will clear it when we boot them later, and the
197 * resulting skew will be handled by tsc_sync_master()/_slave();
198 * note that such skew already exists and has to be handled anyway.
199 *
200 * We do this only on metal. This same problem can occur with a
201 * hypervisor that does not happen to virtualise a TSC that starts from
202 * zero, regardless of CPU type; however, we do not expect hypervisors
203 * that do not virtualise TSC that way to handle writes to TSC
204 * correctly, either.
205 */
206 if (get_hwenv() == HW_NATIVE &&
207 cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
208 cpuid_getfamily(CPU) == 6 &&
209 (cpuid_getmodel(CPU) == 0x2d || cpuid_getmodel(CPU) == 0x3e) &&
210 is_x86_feature(x86_featureset, X86FSET_TSC)) {
211 (void) wrmsr(REG_TSC, 0UL);
212 }
213
214 /*
215 * Patch the tsc_read routine with appropriate set of instructions,
216 * depending on the processor family and architecure, to read the
217 * time-stamp counter while ensuring no out-of-order execution.
218 * Patch it while the kernel text is still writable.
219 *
220 * Note: tsc_read is not patched for intel processors whose family
221 * is >6 and for amd whose family >f (in case they don't support rdtscp
222 * instruction, unlikely). By default tsc_read will use cpuid for
223 * serialization in such cases. The following code needs to be
224 * revisited if intel processors of family >= f retains the
225 * instruction serialization nature of mfence instruction.
226 * Note: tsc_read is not patched for x86 processors which do
227 * not support "mfence". By default tsc_read will use cpuid for
228 * serialization in such cases.
229 *
230 * The Xen hypervisor does not correctly report whether rdtscp is
231 * supported or not, so we must assume that it is not.
232 */
233 if ((get_hwenv() & HW_XEN_HVM) == 0 &&
234 is_x86_feature(x86_featureset, X86FSET_TSCP))
235 patch_tsc_read(TSC_TSCP);
236 else if (cpuid_getvendor(CPU) == X86_VENDOR_AMD &&
237 cpuid_getfamily(CPU) <= 0xf &&
238 is_x86_feature(x86_featureset, X86FSET_SSE2))
239 patch_tsc_read(TSC_RDTSC_MFENCE);
240 else if (cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
241 cpuid_getfamily(CPU) <= 6 &&
242 is_x86_feature(x86_featureset, X86FSET_SSE2))
243 patch_tsc_read(TSC_RDTSC_LFENCE);
244
245 #endif /* !__xpv */
246
247 #if defined(__i386) && !defined(__xpv)
248 /*
249 * Some i386 processors do not implement the rdtsc instruction,
250 * or at least they do not implement it correctly. Patch them to
251 * return 0.
252 */
253 if (!is_x86_feature(x86_featureset, X86FSET_TSC))
254 patch_tsc_read(TSC_NONE);
255 #endif /* __i386 && !__xpv */
256
257 #if defined(__amd64) && !defined(__xpv)
258 patch_memops(cpuid_getvendor(CPU));
259 #endif /* __amd64 && !__xpv */
260
261 #if !defined(__xpv)
262 /* XXPV what, if anything, should be dorked with here under xen? */
263
264 /*
265 * While we're thinking about the TSC, let's set up %cr4 so that
266 * userland can issue rdtsc, and initialize the TSC_AUX value
267 * (the cpuid) for the rdtscp instruction on appropriately
268 * capable hardware.
269 */
270 if (is_x86_feature(x86_featureset, X86FSET_TSC))
271 setcr4(getcr4() & ~CR4_TSD);
272
273 if (is_x86_feature(x86_featureset, X86FSET_TSCP))
274 (void) wrmsr(MSR_AMD_TSCAUX, 0);
275
276 /*
277 * Let's get the other %cr4 stuff while we're here. Note, we defer
278 * enabling CR4_SMAP until startup_end(); however, that's importantly
279 * before we start other CPUs. That ensures that it will be synced out
280 * to other CPUs.
281 */
282 if (is_x86_feature(x86_featureset, X86FSET_DE))
283 setcr4(getcr4() | CR4_DE);
284
285 if (is_x86_feature(x86_featureset, X86FSET_SMEP))
286 setcr4(getcr4() | CR4_SMEP);
287 #endif /* __xpv */
288
289 /*
290 * initialize t0
291 */
292 t0.t_stk = (caddr_t)rp - MINFRAME;
293 t0.t_stkbase = t0stack;
294 t0.t_pri = maxclsyspri - 3;
295 t0.t_schedflag = TS_LOAD | TS_DONT_SWAP;
296 t0.t_procp = &p0;
297 t0.t_plockp = &p0lock.pl_lock;
298 t0.t_lwp = &lwp0;
299 t0.t_forw = &t0;
300 t0.t_back = &t0;
301 t0.t_next = &t0;
302 t0.t_prev = &t0;
303 t0.t_cpu = cpu[0];
304 t0.t_disp_queue = &cpu0_disp;
305 t0.t_bind_cpu = PBIND_NONE;
306 t0.t_bind_pset = PS_NONE;
307 t0.t_bindflag = (uchar_t)default_binding_mode;
308 t0.t_cpupart = &cp_default;
309 t0.t_clfuncs = &sys_classfuncs.thread;
310 t0.t_copyops = NULL;
311 THREAD_ONPROC(&t0, CPU);
312
313 lwp0.lwp_thread = &t0;
314 lwp0.lwp_regs = (void *)rp;
315 lwp0.lwp_procp = &p0;
316 t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1;
317
318 p0.p_exec = NULL;
319 p0.p_stat = SRUN;
320 p0.p_flag = SSYS;
321 p0.p_tlist = &t0;
322 p0.p_stksize = 2*PAGESIZE;
323 p0.p_stkpageszc = 0;
324 p0.p_as = &kas;
325 p0.p_lockp = &p0lock;
326 p0.p_brkpageszc = 0;
327 p0.p_t1_lgrpid = LGRP_NONE;
328 p0.p_tr_lgrpid = LGRP_NONE;
329 psecflags_default(&p0.p_secflags);
330
331 sigorset(&p0.p_ignore, &ignoredefault);
332
333 CPU->cpu_thread = &t0;
334 bzero(&cpu0_disp, sizeof (disp_t));
335 CPU->cpu_disp = &cpu0_disp;
336 CPU->cpu_disp->disp_cpu = CPU;
337 CPU->cpu_dispthread = &t0;
338 CPU->cpu_idle_thread = &t0;
339 CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE;
340 CPU->cpu_dispatch_pri = t0.t_pri;
341
342 CPU->cpu_id = 0;
343
344 CPU->cpu_pri = 12; /* initial PIL for the boot CPU */
345
346 /*
347 * The kernel doesn't use LDTs unless a process explicitly requests one.
348 */
349 p0.p_ldt_desc = null_sdesc;
350
351 /*
352 * Initialize thread/cpu microstate accounting
353 */
354 init_mstate(&t0, LMS_SYSTEM);
355 init_cpu_mstate(CPU, CMS_SYSTEM);
356
357 /*
358 * Initialize lists of available and active CPUs.
359 */
360 cpu_list_init(CPU);
361
362 pg_cpu_bootstrap(CPU);
363
364 /*
365 * Now that we have taken over the GDT, IDT and have initialized
366 * active CPU list it's time to inform kmdb if present.
367 */
368 if (boothowto & RB_DEBUG)
369 kdi_idt_sync();
370
371 /*
372 * Explicitly set console to text mode (0x3) if this is a boot
373 * post Fast Reboot, and the console is set to CONS_SCREEN_TEXT.
374 */
375 if (post_fastreboot && boot_console_type(NULL) == CONS_SCREEN_TEXT)
376 set_console_mode(0x3);
377
378 /*
379 * If requested (boot -d) drop into kmdb.
380 *
381 * This must be done after cpu_list_init() on the 64-bit kernel
382 * since taking a trap requires that we re-compute gsbase based
383 * on the cpu list.
384 */
385 if (boothowto & RB_DEBUGENTER)
386 kmdb_enter();
387
388 cpu_vm_data_init(CPU);
389
390 rp->r_fp = 0; /* terminate kernel stack traces! */
391
392 prom_init("kernel", (void *)NULL);
393
394 /* User-set option overrides firmware value. */
395 if (bootprop_getval(PLAT_DR_OPTIONS_NAME, &prop_value) == 0) {
396 plat_dr_options = (uint64_t)prop_value;
397 }
398 #if defined(__xpv)
399 /* No support of DR operations on xpv */
400 plat_dr_options = 0;
401 #else /* __xpv */
402 /* Flag PLAT_DR_FEATURE_ENABLED should only be set by DR driver. */
403 plat_dr_options &= ~PLAT_DR_FEATURE_ENABLED;
404 #ifndef __amd64
405 /* Only enable CPU/memory DR on 64 bits kernel. */
406 plat_dr_options &= ~PLAT_DR_FEATURE_MEMORY;
407 plat_dr_options &= ~PLAT_DR_FEATURE_CPU;
408 #endif /* __amd64 */
409 #endif /* __xpv */
410
411 /*
412 * Get value of "plat_dr_physmax" boot option.
413 * It overrides values calculated from MSCT or SRAT table.
414 */
415 if (bootprop_getval(PLAT_DR_PHYSMAX_NAME, &prop_value) == 0) {
416 plat_dr_physmax = ((uint64_t)prop_value) >> PAGESHIFT;
417 }
418
419 /* Get value of boot_ncpus. */
420 if (bootprop_getval(BOOT_NCPUS_NAME, &prop_value) != 0) {
421 boot_ncpus = NCPU;
422 } else {
423 boot_ncpus = (int)prop_value;
424 if (boot_ncpus <= 0 || boot_ncpus > NCPU)
425 boot_ncpus = NCPU;
426 }
427
428 /*
429 * Set max_ncpus and boot_max_ncpus to boot_ncpus if platform doesn't
430 * support CPU DR operations.
431 */
432 if (plat_dr_support_cpu() == 0) {
433 max_ncpus = boot_max_ncpus = boot_ncpus;
434 } else {
435 if (bootprop_getval(PLAT_MAX_NCPUS_NAME, &prop_value) != 0) {
436 max_ncpus = NCPU;
437 } else {
438 max_ncpus = (int)prop_value;
439 if (max_ncpus <= 0 || max_ncpus > NCPU) {
440 max_ncpus = NCPU;
441 }
442 if (boot_ncpus > max_ncpus) {
443 boot_ncpus = max_ncpus;
444 }
445 }
446
447 if (bootprop_getval(BOOT_MAX_NCPUS_NAME, &prop_value) != 0) {
448 boot_max_ncpus = boot_ncpus;
449 } else {
450 boot_max_ncpus = (int)prop_value;
451 if (boot_max_ncpus <= 0 || boot_max_ncpus > NCPU) {
452 boot_max_ncpus = boot_ncpus;
453 } else if (boot_max_ncpus > max_ncpus) {
454 boot_max_ncpus = max_ncpus;
455 }
456 }
457 }
458
459 /*
460 * Initialize the lgrp framework
461 */
462 lgrp_init(LGRP_INIT_STAGE1);
463
464 if (boothowto & RB_HALT) {
465 prom_printf("unix: kernel halted by -h flag\n");
466 prom_enter_mon();
467 }
468
469 ASSERT_STACK_ALIGNED();
470
471 /*
472 * Fill out cpu_ucode_info. Update microcode if necessary.
473 */
474 ucode_check(CPU);
475
476 if (workaround_errata(CPU) != 0)
477 panic("critical workaround(s) missing for boot cpu");
478 }
479
480
481 void
482 mach_modpath(char *path, const char *filename)
483 {
484 /*
485 * Construct the directory path from the filename.
486 */
487
488 int len;
489 char *p;
490 const char isastr[] = "/amd64";
491 size_t isalen = strlen(isastr);
492
493 len = strlen(SYSTEM_BOOT_PATH "/kernel");
494 (void) strcpy(path, SYSTEM_BOOT_PATH "/kernel ");
495 path += len + 1;
496
497 if ((p = strrchr(filename, '/')) == NULL)
498 return;
499
500 while (p > filename && *(p - 1) == '/')
501 p--; /* remove trailing '/' characters */
502 if (p == filename)
503 p++; /* so "/" -is- the modpath in this case */
504
505 /*
506 * Remove optional isa-dependent directory name - the module
507 * subsystem will put this back again (!)
508 */
509 len = p - filename;
510 if (len > isalen &&
511 strncmp(&filename[len - isalen], isastr, isalen) == 0)
512 p -= isalen;
513
514 /*
515 * "/platform/mumblefrotz" + " " + MOD_DEFPATH
516 */
517 len += (p - filename) + 1 + strlen(MOD_DEFPATH) + 1;
518 (void) strncpy(path, filename, p - filename);
519 }