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LOCAL: mpt_sas: expose drive ID via ioctl
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--- old/usr/src/uts/common/io/scsi/adapters/mpt_sas/mptsas.c
+++ new/usr/src/uts/common/io/scsi/adapters/mpt_sas/mptsas.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
25 + * Copyright (c) 2012, Joyent, Inc. All rights reserved.
25 26 */
26 27
27 28 /*
28 29 * Copyright (c) 2000 to 2010, LSI Corporation.
29 30 * All rights reserved.
30 31 *
31 32 * Redistribution and use in source and binary forms of all code within
32 33 * this file that is exclusively owned by LSI, with or without
33 34 * modification, is permitted provided that, in addition to the CDDL 1.0
34 35 * License requirements, the following conditions are met:
35 36 *
36 37 * Neither the name of the author nor the names of its contributors may be
37 38 * used to endorse or promote products derived from this software without
38 39 * specific prior written permission.
39 40 *
40 41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
41 42 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
42 43 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
43 44 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
44 45 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
45 46 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
46 47 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
47 48 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
48 49 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
49 50 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
50 51 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
51 52 * DAMAGE.
52 53 */
53 54
54 55 /*
55 56 * mptsas - This is a driver based on LSI Logic's MPT2.0 interface.
56 57 *
57 58 */
58 59
59 60 #if defined(lint) || defined(DEBUG)
60 61 #define MPTSAS_DEBUG
61 62 #endif
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62 63
63 64 /*
64 65 * standard header files.
65 66 */
66 67 #include <sys/note.h>
67 68 #include <sys/scsi/scsi.h>
68 69 #include <sys/pci.h>
69 70 #include <sys/file.h>
70 71 #include <sys/cpuvar.h>
71 72 #include <sys/policy.h>
73 +#include <sys/model.h>
72 74 #include <sys/sysevent.h>
73 75 #include <sys/sysevent/eventdefs.h>
74 76 #include <sys/sysevent/dr.h>
75 77 #include <sys/sata/sata_defs.h>
76 78 #include <sys/scsi/generic/sas.h>
77 79 #include <sys/scsi/impl/scsi_sas.h>
78 80
79 81 #pragma pack(1)
80 82 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h>
81 83 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2.h>
82 84 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h>
83 85 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h>
84 86 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h>
85 87 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h>
86 88 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h>
87 89 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h>
88 90 #pragma pack()
89 91
90 92 /*
91 93 * private header files.
92 94 *
93 95 */
94 96 #include <sys/scsi/impl/scsi_reset_notify.h>
95 97 #include <sys/scsi/adapters/mpt_sas/mptsas_var.h>
96 98 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h>
97 99 #include <sys/scsi/adapters/mpt_sas/mptsas_smhba.h>
98 100
99 101 #include <sys/raidioctl.h>
100 102
101 103 #include <sys/fs/dv_node.h> /* devfs_clean */
102 104
103 105 /*
104 106 * FMA header files
105 107 */
106 108 #include <sys/ddifm.h>
107 109 #include <sys/fm/protocol.h>
108 110 #include <sys/fm/util.h>
109 111 #include <sys/fm/io/ddi.h>
110 112
111 113 /*
112 114 * For anyone who would modify the code in mptsas_driver, it must be awared
113 115 * that from snv_145 where CR6910752(mpt_sas driver performance can be
114 116 * improved) is integrated, the per_instance mutex m_mutex is not hold
115 117 * in the key IO code path, including mptsas_scsi_start(), mptsas_intr()
116 118 * and all of the recursive functions called in them, so don't
117 119 * make it for granted that all operations are sync/exclude correctly. Before
118 120 * doing any modification in key code path, and even other code path such as
119 121 * DR, watchsubr, ioctl, passthrough etc, make sure the elements modified have
120 122 * no releationship to elements shown in the fastpath
121 123 * (function mptsas_handle_io_fastpath()) in ISR and its recursive functions.
122 124 * otherwise, you have to use the new introduced mutex to protect them.
123 125 * As to how to do correctly, refer to the comments in mptsas_intr().
124 126 */
125 127
126 128 /*
127 129 * autoconfiguration data and routines.
128 130 */
129 131 static int mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
130 132 static int mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd);
131 133 static int mptsas_power(dev_info_t *dip, int component, int level);
132 134
133 135 /*
134 136 * cb_ops function
135 137 */
136 138 static int mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode,
137 139 cred_t *credp, int *rval);
138 140 #ifdef __sparc
139 141 static int mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd);
140 142 #else /* __sparc */
141 143 static int mptsas_quiesce(dev_info_t *devi);
142 144 #endif /* __sparc */
143 145
144 146 /*
145 147 * Resource initilaization for hardware
146 148 */
147 149 static void mptsas_setup_cmd_reg(mptsas_t *mpt);
148 150 static void mptsas_disable_bus_master(mptsas_t *mpt);
149 151 static void mptsas_hba_fini(mptsas_t *mpt);
150 152 static void mptsas_cfg_fini(mptsas_t *mptsas_blkp);
151 153 static int mptsas_hba_setup(mptsas_t *mpt);
152 154 static void mptsas_hba_teardown(mptsas_t *mpt);
153 155 static int mptsas_config_space_init(mptsas_t *mpt);
154 156 static void mptsas_config_space_fini(mptsas_t *mpt);
155 157 static void mptsas_iport_register(mptsas_t *mpt);
156 158 static int mptsas_smp_setup(mptsas_t *mpt);
157 159 static void mptsas_smp_teardown(mptsas_t *mpt);
158 160 static int mptsas_cache_create(mptsas_t *mpt);
159 161 static void mptsas_cache_destroy(mptsas_t *mpt);
160 162 static int mptsas_alloc_request_frames(mptsas_t *mpt);
161 163 static int mptsas_alloc_reply_frames(mptsas_t *mpt);
162 164 static int mptsas_alloc_free_queue(mptsas_t *mpt);
163 165 static int mptsas_alloc_post_queue(mptsas_t *mpt);
164 166 static void mptsas_alloc_reply_args(mptsas_t *mpt);
165 167 static int mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd);
166 168 static void mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd);
167 169 static int mptsas_init_chip(mptsas_t *mpt, int first_time);
168 170
169 171 /*
170 172 * SCSA function prototypes
171 173 */
172 174 static int mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt);
173 175 static int mptsas_scsi_reset(struct scsi_address *ap, int level);
174 176 static int mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt);
175 177 static int mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly);
176 178 static int mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value,
177 179 int tgtonly);
178 180 static void mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt);
179 181 static struct scsi_pkt *mptsas_scsi_init_pkt(struct scsi_address *ap,
180 182 struct scsi_pkt *pkt, struct buf *bp, int cmdlen, int statuslen,
181 183 int tgtlen, int flags, int (*callback)(), caddr_t arg);
182 184 static void mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt);
183 185 static void mptsas_scsi_destroy_pkt(struct scsi_address *ap,
184 186 struct scsi_pkt *pkt);
185 187 static int mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
186 188 scsi_hba_tran_t *hba_tran, struct scsi_device *sd);
187 189 static void mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
188 190 scsi_hba_tran_t *hba_tran, struct scsi_device *sd);
189 191 static int mptsas_scsi_reset_notify(struct scsi_address *ap, int flag,
190 192 void (*callback)(caddr_t), caddr_t arg);
191 193 static int mptsas_get_name(struct scsi_device *sd, char *name, int len);
192 194 static int mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len);
193 195 static int mptsas_scsi_quiesce(dev_info_t *dip);
194 196 static int mptsas_scsi_unquiesce(dev_info_t *dip);
195 197 static int mptsas_bus_config(dev_info_t *pdip, uint_t flags,
196 198 ddi_bus_config_op_t op, void *arg, dev_info_t **childp);
197 199
198 200 /*
199 201 * SMP functions
200 202 */
201 203 static int mptsas_smp_start(struct smp_pkt *smp_pkt);
202 204
203 205 /*
204 206 * internal function prototypes.
205 207 */
206 208 static void mptsas_list_add(mptsas_t *mpt);
207 209 static void mptsas_list_del(mptsas_t *mpt);
208 210
209 211 static int mptsas_quiesce_bus(mptsas_t *mpt);
210 212 static int mptsas_unquiesce_bus(mptsas_t *mpt);
211 213
212 214 static int mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size);
213 215 static void mptsas_free_handshake_msg(mptsas_t *mpt);
214 216
215 217 static void mptsas_ncmds_checkdrain(void *arg);
216 218
217 219 static int mptsas_prepare_pkt(mptsas_cmd_t *cmd);
218 220 static int mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *sp);
219 221
220 222 static int mptsas_do_detach(dev_info_t *dev);
221 223 static int mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl);
222 224 static int mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun,
223 225 struct scsi_pkt *pkt);
224 226 static int mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp);
225 227
226 228 static void mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd);
227 229 static void mptsas_handle_event(void *args);
228 230 static int mptsas_handle_event_sync(void *args);
229 231 static void mptsas_handle_dr(void *args);
230 232 static void mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node,
231 233 dev_info_t *pdip);
232 234
233 235 static void mptsas_restart_cmd(void *);
234 236
235 237 static void mptsas_flush_hba(mptsas_t *mpt);
236 238 static void mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun,
237 239 uint8_t tasktype);
238 240 static void mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd,
239 241 uchar_t reason, uint_t stat);
240 242
241 243 static uint_t mptsas_intr(caddr_t arg1, caddr_t arg2);
242 244 static void mptsas_process_intr(mptsas_t *mpt,
243 245 pMpi2ReplyDescriptorsUnion_t reply_desc_union);
244 246 static int mptsas_handle_io_fastpath(mptsas_t *mpt, uint16_t SMID);
245 247 static void mptsas_handle_scsi_io_success(mptsas_t *mpt,
246 248 pMpi2ReplyDescriptorsUnion_t reply_desc);
247 249 static void mptsas_handle_address_reply(mptsas_t *mpt,
248 250 pMpi2ReplyDescriptorsUnion_t reply_desc);
249 251 static int mptsas_wait_intr(mptsas_t *mpt, int polltime);
250 252 static void mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd,
251 253 uint32_t *control, pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl);
252 254
253 255 static void mptsas_watch(void *arg);
254 256 static void mptsas_watchsubr(mptsas_t *mpt);
255 257 static void mptsas_cmd_timeout(mptsas_t *mpt, uint16_t devhdl);
256 258
257 259 static void mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd);
258 260 static int mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply,
259 261 uint8_t *data, uint32_t request_size, uint32_t reply_size,
260 262 uint32_t data_size, uint32_t direction, uint8_t *dataout,
261 263 uint32_t dataout_size, short timeout, int mode);
262 264 static int mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl);
263 265
264 266 static uint8_t mptsas_get_fw_diag_buffer_number(mptsas_t *mpt,
265 267 uint32_t unique_id);
266 268 static void mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd);
267 269 static int mptsas_post_fw_diag_buffer(mptsas_t *mpt,
268 270 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code);
269 271 static int mptsas_release_fw_diag_buffer(mptsas_t *mpt,
270 272 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code,
271 273 uint32_t diag_type);
272 274 static int mptsas_diag_register(mptsas_t *mpt,
273 275 mptsas_fw_diag_register_t *diag_register, uint32_t *return_code);
274 276 static int mptsas_diag_unregister(mptsas_t *mpt,
275 277 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code);
276 278 static int mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query,
277 279 uint32_t *return_code);
278 280 static int mptsas_diag_read_buffer(mptsas_t *mpt,
279 281 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf,
280 282 uint32_t *return_code, int ioctl_mode);
281 283 static int mptsas_diag_release(mptsas_t *mpt,
282 284 mptsas_fw_diag_release_t *diag_release, uint32_t *return_code);
283 285 static int mptsas_do_diag_action(mptsas_t *mpt, uint32_t action,
284 286 uint8_t *diag_action, uint32_t length, uint32_t *return_code,
285 287 int ioctl_mode);
286 288 static int mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *data,
287 289 int mode);
288 290
289 291 static int mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd,
290 292 int cmdlen, int tgtlen, int statuslen, int kf);
291 293 static void mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd);
292 294
293 295 static int mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags);
294 296 static void mptsas_kmem_cache_destructor(void *buf, void *cdrarg);
295 297
296 298 static int mptsas_cache_frames_constructor(void *buf, void *cdrarg,
297 299 int kmflags);
298 300 static void mptsas_cache_frames_destructor(void *buf, void *cdrarg);
299 301
300 302 static void mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply,
301 303 mptsas_cmd_t *cmd);
302 304 static void mptsas_check_task_mgt(mptsas_t *mpt,
303 305 pMpi2SCSIManagementReply_t reply, mptsas_cmd_t *cmd);
304 306 static int mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap,
305 307 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp,
306 308 int *resid);
307 309
308 310 static int mptsas_alloc_active_slots(mptsas_t *mpt, int flag);
309 311 static void mptsas_free_active_slots(mptsas_t *mpt);
310 312 static int mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
311 313 static int mptsas_start_cmd0(mptsas_t *mpt, mptsas_cmd_t *cmd);
312 314
313 315 static void mptsas_restart_hba(mptsas_t *mpt);
314 316
315 317 static void mptsas_deliver_doneq_thread(mptsas_t *mpt);
316 318 static void mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd);
317 319 static inline void mptsas_doneq_add0(mptsas_t *mpt, mptsas_cmd_t *cmd);
318 320 static void mptsas_doneq_mv(mptsas_t *mpt, uint64_t t);
319 321
320 322 static mptsas_cmd_t *mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t);
321 323 static void mptsas_doneq_empty(mptsas_t *mpt);
322 324 static void mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg);
323 325
324 326 static mptsas_cmd_t *mptsas_waitq_rm(mptsas_t *mpt);
325 327 static void mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd);
326 328
327 329 static void mptsas_start_watch_reset_delay();
328 330 static void mptsas_setup_bus_reset_delay(mptsas_t *mpt);
329 331 static void mptsas_watch_reset_delay(void *arg);
330 332 static int mptsas_watch_reset_delay_subr(mptsas_t *mpt);
331 333
332 334 static int mptsas_outstanding_cmds_n(mptsas_t *mpt);
333 335 /*
334 336 * helper functions
335 337 */
336 338 static void mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
337 339
338 340 static dev_info_t *mptsas_find_child(dev_info_t *pdip, char *name);
339 341 static dev_info_t *mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy);
340 342 static dev_info_t *mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr,
341 343 int lun);
342 344 static mdi_pathinfo_t *mptsas_find_path_addr(dev_info_t *pdip, uint64_t sasaddr,
343 345 int lun);
344 346 static mdi_pathinfo_t *mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy);
345 347 static dev_info_t *mptsas_find_smp_child(dev_info_t *pdip, char *str_wwn);
346 348
347 349 static int mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy,
348 350 int *lun);
349 351 static int mptsas_parse_smp_name(char *name, uint64_t *wwn);
350 352
351 353 static mptsas_target_t *mptsas_phy_to_tgt(mptsas_t *mpt, int phymask,
352 354 uint8_t phy);
353 355 static mptsas_target_t *mptsas_wwid_to_ptgt(mptsas_t *mpt, int phymask,
354 356 uint64_t wwid);
355 357 static mptsas_smp_t *mptsas_wwid_to_psmp(mptsas_t *mpt, int phymask,
356 358 uint64_t wwid);
357 359
358 360 static int mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun,
359 361 uchar_t page, unsigned char *buf, int len, int *rlen, uchar_t evpd);
360 362
361 363 static int mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address,
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362 364 uint16_t *handle, mptsas_target_t **pptgt);
363 365 static void mptsas_update_phymask(mptsas_t *mpt);
364 366 static inline void mptsas_remove_cmd0(mptsas_t *mpt, mptsas_cmd_t *cmd);
365 367
366 368 static int mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt,
367 369 uint32_t *status, uint8_t cmd);
368 370 static dev_info_t *mptsas_get_dip_from_dev(dev_t dev,
369 371 mptsas_phymask_t *phymask);
370 372 static mptsas_target_t *mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr,
371 373 mptsas_phymask_t phymask);
372 -static int mptsas_set_led_status(mptsas_t *mpt, mptsas_target_t *ptgt,
373 - uint32_t slotstatus);
374 +static int mptsas_flush_led_status(mptsas_t *mpt, mptsas_target_t *ptgt);
374 375
375 376
376 377 /*
377 378 * Enumeration / DR functions
378 379 */
379 380 static void mptsas_config_all(dev_info_t *pdip);
380 381 static int mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun,
381 382 dev_info_t **lundip);
382 383 static int mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun,
383 384 dev_info_t **lundip);
384 385
385 386 static int mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt);
386 387 static int mptsas_offline_target(dev_info_t *pdip, char *name);
387 388
388 389 static int mptsas_config_raid(dev_info_t *pdip, uint16_t target,
389 390 dev_info_t **dip);
390 391
391 392 static int mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt);
392 393 static int mptsas_probe_lun(dev_info_t *pdip, int lun,
393 394 dev_info_t **dip, mptsas_target_t *ptgt);
394 395
395 396 static int mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq,
396 397 dev_info_t **dip, mptsas_target_t *ptgt, int lun);
397 398
398 399 static int mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *sd,
399 400 char *guid, dev_info_t **dip, mptsas_target_t *ptgt, int lun);
400 401 static int mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *sd,
401 402 char *guid, dev_info_t **dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt,
402 403 int lun);
403 404
404 405 static void mptsas_offline_missed_luns(dev_info_t *pdip,
405 406 uint16_t *repluns, int lun_cnt, mptsas_target_t *ptgt);
406 407 static int mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip,
407 408 mdi_pathinfo_t *rpip, uint_t flags);
408 409
409 410 static int mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn,
410 411 dev_info_t **smp_dip);
411 412 static int mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
412 413 uint_t flags);
413 414
414 415 static int mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data,
415 416 int mode, int *rval);
416 417 static int mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data,
417 418 int mode, int *rval);
418 419 static int mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data,
419 420 int mode, int *rval);
420 421 static void mptsas_record_event(void *args);
421 422 static int mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data,
422 423 int mode);
423 424
424 425 static void mptsas_hash_init(mptsas_hash_table_t *hashtab);
425 426 static void mptsas_hash_uninit(mptsas_hash_table_t *hashtab, size_t datalen);
426 427 static void mptsas_hash_add(mptsas_hash_table_t *hashtab, void *data);
427 428 static void * mptsas_hash_rem(mptsas_hash_table_t *hashtab, uint64_t key1,
428 429 mptsas_phymask_t key2);
429 430 static void * mptsas_hash_search(mptsas_hash_table_t *hashtab, uint64_t key1,
430 431 mptsas_phymask_t key2);
431 432 static void * mptsas_hash_traverse(mptsas_hash_table_t *hashtab, int pos);
432 433
433 434 mptsas_target_t *mptsas_tgt_alloc(mptsas_hash_table_t *, uint16_t, uint64_t,
434 435 uint32_t, mptsas_phymask_t, uint8_t, mptsas_t *);
435 436 static mptsas_smp_t *mptsas_smp_alloc(mptsas_hash_table_t *hashtab,
436 437 mptsas_smp_t *data);
437 438 static void mptsas_smp_free(mptsas_hash_table_t *hashtab, uint64_t wwid,
438 439 mptsas_phymask_t phymask);
439 440 static void mptsas_tgt_free(mptsas_hash_table_t *, uint64_t, mptsas_phymask_t);
440 441 static void * mptsas_search_by_devhdl(mptsas_hash_table_t *, uint16_t);
441 442 static int mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
442 443 dev_info_t **smp_dip);
443 444
444 445 /*
445 446 * Power management functions
446 447 */
447 448 static int mptsas_get_pci_cap(mptsas_t *mpt);
448 449 static int mptsas_init_pm(mptsas_t *mpt);
449 450
450 451 /*
451 452 * MPT MSI tunable:
452 453 *
453 454 * By default MSI is enabled on all supported platforms.
454 455 */
455 456 boolean_t mptsas_enable_msi = B_TRUE;
456 457 boolean_t mptsas_physical_bind_failed_page_83 = B_FALSE;
457 458
458 459 static int mptsas_register_intrs(mptsas_t *);
459 460 static void mptsas_unregister_intrs(mptsas_t *);
460 461 static int mptsas_add_intrs(mptsas_t *, int);
461 462 static void mptsas_rem_intrs(mptsas_t *);
462 463
463 464 /*
464 465 * FMA Prototypes
465 466 */
466 467 static void mptsas_fm_init(mptsas_t *mpt);
467 468 static void mptsas_fm_fini(mptsas_t *mpt);
468 469 static int mptsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *, const void *);
469 470
470 471 extern pri_t minclsyspri, maxclsyspri;
471 472
472 473 /*
473 474 * This device is created by the SCSI pseudo nexus driver (SCSI vHCI). It is
474 475 * under this device that the paths to a physical device are created when
475 476 * MPxIO is used.
476 477 */
477 478 extern dev_info_t *scsi_vhci_dip;
478 479
479 480 /*
480 481 * Tunable timeout value for Inquiry VPD page 0x83
481 482 * By default the value is 30 seconds.
482 483 */
483 484 int mptsas_inq83_retry_timeout = 30;
484 485
485 486 /*
486 487 * This is used to allocate memory for message frame storage, not for
487 488 * data I/O DMA. All message frames must be stored in the first 4G of
488 489 * physical memory.
489 490 */
490 491 ddi_dma_attr_t mptsas_dma_attrs = {
491 492 DMA_ATTR_V0, /* attribute layout version */
492 493 0x0ull, /* address low - should be 0 (longlong) */
493 494 0xffffffffull, /* address high - 32-bit max range */
494 495 0x00ffffffull, /* count max - max DMA object size */
495 496 4, /* allocation alignment requirements */
496 497 0x78, /* burstsizes - binary encoded values */
497 498 1, /* minxfer - gran. of DMA engine */
498 499 0x00ffffffull, /* maxxfer - gran. of DMA engine */
499 500 0xffffffffull, /* max segment size (DMA boundary) */
500 501 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */
501 502 512, /* granularity - device transfer size */
502 503 0 /* flags, set to 0 */
503 504 };
504 505
505 506 /*
506 507 * This is used for data I/O DMA memory allocation. (full 64-bit DMA
507 508 * physical addresses are supported.)
508 509 */
509 510 ddi_dma_attr_t mptsas_dma_attrs64 = {
510 511 DMA_ATTR_V0, /* attribute layout version */
511 512 0x0ull, /* address low - should be 0 (longlong) */
512 513 0xffffffffffffffffull, /* address high - 64-bit max */
513 514 0x00ffffffull, /* count max - max DMA object size */
514 515 4, /* allocation alignment requirements */
515 516 0x78, /* burstsizes - binary encoded values */
516 517 1, /* minxfer - gran. of DMA engine */
517 518 0x00ffffffull, /* maxxfer - gran. of DMA engine */
518 519 0xffffffffull, /* max segment size (DMA boundary) */
519 520 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */
520 521 512, /* granularity - device transfer size */
521 522 DDI_DMA_RELAXED_ORDERING /* flags, enable relaxed ordering */
522 523 };
523 524
524 525 ddi_device_acc_attr_t mptsas_dev_attr = {
525 526 DDI_DEVICE_ATTR_V1,
526 527 DDI_STRUCTURE_LE_ACC,
527 528 DDI_STRICTORDER_ACC,
528 529 DDI_DEFAULT_ACC
529 530 };
530 531
531 532 static struct cb_ops mptsas_cb_ops = {
532 533 scsi_hba_open, /* open */
533 534 scsi_hba_close, /* close */
534 535 nodev, /* strategy */
535 536 nodev, /* print */
536 537 nodev, /* dump */
537 538 nodev, /* read */
538 539 nodev, /* write */
539 540 mptsas_ioctl, /* ioctl */
540 541 nodev, /* devmap */
541 542 nodev, /* mmap */
542 543 nodev, /* segmap */
543 544 nochpoll, /* chpoll */
544 545 ddi_prop_op, /* cb_prop_op */
545 546 NULL, /* streamtab */
546 547 D_MP, /* cb_flag */
547 548 CB_REV, /* rev */
548 549 nodev, /* aread */
549 550 nodev /* awrite */
550 551 };
551 552
552 553 static struct dev_ops mptsas_ops = {
553 554 DEVO_REV, /* devo_rev, */
554 555 0, /* refcnt */
555 556 ddi_no_info, /* info */
556 557 nulldev, /* identify */
557 558 nulldev, /* probe */
558 559 mptsas_attach, /* attach */
559 560 mptsas_detach, /* detach */
560 561 #ifdef __sparc
561 562 mptsas_reset,
562 563 #else
563 564 nodev, /* reset */
564 565 #endif /* __sparc */
565 566 &mptsas_cb_ops, /* driver operations */
566 567 NULL, /* bus operations */
567 568 mptsas_power, /* power management */
568 569 #ifdef __sparc
569 570 ddi_quiesce_not_needed
570 571 #else
571 572 mptsas_quiesce /* quiesce */
572 573 #endif /* __sparc */
573 574 };
574 575
575 576
576 577 #define MPTSAS_MOD_STRING "MPTSAS HBA Driver 00.00.00.24"
577 578
578 579 static struct modldrv modldrv = {
579 580 &mod_driverops, /* Type of module. This one is a driver */
580 581 MPTSAS_MOD_STRING, /* Name of the module. */
581 582 &mptsas_ops, /* driver ops */
582 583 };
583 584
584 585 static struct modlinkage modlinkage = {
585 586 MODREV_1, &modldrv, NULL
586 587 };
587 588 #define TARGET_PROP "target"
588 589 #define LUN_PROP "lun"
589 590 #define LUN64_PROP "lun64"
590 591 #define SAS_PROP "sas-mpt"
591 592 #define MDI_GUID "wwn"
592 593 #define NDI_GUID "guid"
593 594 #define MPTSAS_DEV_GONE "mptsas_dev_gone"
594 595
595 596 /*
596 597 * Local static data
597 598 */
598 599 #if defined(MPTSAS_DEBUG)
599 600 uint32_t mptsas_debug_flags = 0;
600 601 #endif /* defined(MPTSAS_DEBUG) */
601 602 uint32_t mptsas_debug_resets = 0;
602 603
603 604 static kmutex_t mptsas_global_mutex;
604 605 static void *mptsas_state; /* soft state ptr */
605 606 static krwlock_t mptsas_global_rwlock;
606 607
607 608 static kmutex_t mptsas_log_mutex;
608 609 static char mptsas_log_buf[256];
609 610 _NOTE(MUTEX_PROTECTS_DATA(mptsas_log_mutex, mptsas_log_buf))
610 611
611 612 static mptsas_t *mptsas_head, *mptsas_tail;
612 613 static clock_t mptsas_scsi_watchdog_tick;
613 614 static clock_t mptsas_tick;
614 615 static timeout_id_t mptsas_reset_watch;
615 616 static timeout_id_t mptsas_timeout_id;
616 617 static int mptsas_timeouts_enabled = 0;
617 618 /*
618 619 * warlock directives
619 620 */
620 621 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", scsi_pkt \
621 622 mptsas_cmd NcrTableIndirect buf scsi_cdb scsi_status))
622 623 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", smp_pkt))
623 624 _NOTE(SCHEME_PROTECTS_DATA("stable data", scsi_device scsi_address))
624 625 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", mptsas_tgt_private))
625 626 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", scsi_hba_tran::tran_tgt_private))
626 627
627 628 /*
628 629 * SM - HBA statics
629 630 */
630 631 char *mptsas_driver_rev = MPTSAS_MOD_STRING;
631 632
632 633 #ifdef MPTSAS_DEBUG
633 634 void debug_enter(char *);
634 635 #endif
635 636
636 637 /*
637 638 * Notes:
638 639 * - scsi_hba_init(9F) initializes SCSI HBA modules
639 640 * - must call scsi_hba_fini(9F) if modload() fails
640 641 */
641 642 int
642 643 _init(void)
643 644 {
644 645 int status;
645 646 /* CONSTCOND */
646 647 ASSERT(NO_COMPETING_THREADS);
647 648
648 649 NDBG0(("_init"));
649 650
650 651 status = ddi_soft_state_init(&mptsas_state, MPTSAS_SIZE,
651 652 MPTSAS_INITIAL_SOFT_SPACE);
652 653 if (status != 0) {
653 654 return (status);
654 655 }
655 656
656 657 if ((status = scsi_hba_init(&modlinkage)) != 0) {
657 658 ddi_soft_state_fini(&mptsas_state);
658 659 return (status);
659 660 }
660 661
661 662 mutex_init(&mptsas_global_mutex, NULL, MUTEX_DRIVER, NULL);
662 663 rw_init(&mptsas_global_rwlock, NULL, RW_DRIVER, NULL);
663 664 mutex_init(&mptsas_log_mutex, NULL, MUTEX_DRIVER, NULL);
664 665
665 666 if ((status = mod_install(&modlinkage)) != 0) {
666 667 mutex_destroy(&mptsas_log_mutex);
667 668 rw_destroy(&mptsas_global_rwlock);
668 669 mutex_destroy(&mptsas_global_mutex);
669 670 ddi_soft_state_fini(&mptsas_state);
670 671 scsi_hba_fini(&modlinkage);
671 672 }
672 673
673 674 return (status);
674 675 }
675 676
676 677 /*
677 678 * Notes:
678 679 * - scsi_hba_fini(9F) uninitializes SCSI HBA modules
679 680 */
680 681 int
681 682 _fini(void)
682 683 {
683 684 int status;
684 685 /* CONSTCOND */
685 686 ASSERT(NO_COMPETING_THREADS);
686 687
687 688 NDBG0(("_fini"));
688 689
689 690 if ((status = mod_remove(&modlinkage)) == 0) {
690 691 ddi_soft_state_fini(&mptsas_state);
691 692 scsi_hba_fini(&modlinkage);
692 693 mutex_destroy(&mptsas_global_mutex);
693 694 rw_destroy(&mptsas_global_rwlock);
694 695 mutex_destroy(&mptsas_log_mutex);
695 696 }
696 697 return (status);
697 698 }
698 699
699 700 /*
700 701 * The loadable-module _info(9E) entry point
701 702 */
702 703 int
703 704 _info(struct modinfo *modinfop)
704 705 {
705 706 /* CONSTCOND */
706 707 ASSERT(NO_COMPETING_THREADS);
707 708 NDBG0(("mptsas _info"));
708 709
709 710 return (mod_info(&modlinkage, modinfop));
710 711 }
711 712
712 713
713 714 static int
714 715 mptsas_iport_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
715 716 {
716 717 dev_info_t *pdip;
717 718 mptsas_t *mpt;
718 719 scsi_hba_tran_t *hba_tran;
719 720 char *iport = NULL;
720 721 char phymask[MPTSAS_MAX_PHYS];
721 722 mptsas_phymask_t phy_mask = 0;
722 723 int dynamic_port = 0;
723 724 uint32_t page_address;
724 725 char initiator_wwnstr[MPTSAS_WWN_STRLEN];
725 726 int rval = DDI_FAILURE;
726 727 int i = 0;
727 728 uint8_t numphys = 0;
728 729 uint8_t phy_id;
729 730 uint8_t phy_port = 0;
730 731 uint16_t attached_devhdl = 0;
731 732 uint32_t dev_info;
732 733 uint64_t attached_sas_wwn;
733 734 uint16_t dev_hdl;
734 735 uint16_t pdev_hdl;
735 736 uint16_t bay_num, enclosure;
736 737 char attached_wwnstr[MPTSAS_WWN_STRLEN];
737 738
738 739 /* CONSTCOND */
739 740 ASSERT(NO_COMPETING_THREADS);
740 741
741 742 switch (cmd) {
742 743 case DDI_ATTACH:
743 744 break;
744 745
745 746 case DDI_RESUME:
746 747 /*
747 748 * If this a scsi-iport node, nothing to do here.
748 749 */
749 750 return (DDI_SUCCESS);
750 751
751 752 default:
752 753 return (DDI_FAILURE);
753 754 }
754 755
755 756 pdip = ddi_get_parent(dip);
756 757
757 758 if ((hba_tran = ndi_flavorv_get(pdip, SCSA_FLAVOR_SCSI_DEVICE)) ==
758 759 NULL) {
759 760 cmn_err(CE_WARN, "Failed attach iport because fail to "
760 761 "get tran vector for the HBA node");
761 762 return (DDI_FAILURE);
762 763 }
763 764
764 765 mpt = TRAN2MPT(hba_tran);
765 766 ASSERT(mpt != NULL);
766 767 if (mpt == NULL)
767 768 return (DDI_FAILURE);
768 769
769 770 if ((hba_tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) ==
770 771 NULL) {
771 772 mptsas_log(mpt, CE_WARN, "Failed attach iport because fail to "
772 773 "get tran vector for the iport node");
773 774 return (DDI_FAILURE);
774 775 }
775 776
776 777 /*
777 778 * Overwrite parent's tran_hba_private to iport's tran vector
778 779 */
779 780 hba_tran->tran_hba_private = mpt;
780 781
781 782 ddi_report_dev(dip);
782 783
783 784 /*
784 785 * Get SAS address for initiator port according dev_handle
785 786 */
786 787 iport = ddi_get_name_addr(dip);
787 788 if (iport && strncmp(iport, "v0", 2) == 0) {
788 789 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
789 790 MPTSAS_VIRTUAL_PORT, 1) !=
790 791 DDI_PROP_SUCCESS) {
791 792 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
792 793 MPTSAS_VIRTUAL_PORT);
793 794 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
794 795 "prop update failed");
795 796 return (DDI_FAILURE);
796 797 }
797 798 return (DDI_SUCCESS);
798 799 }
799 800
800 801 mutex_enter(&mpt->m_mutex);
801 802 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
802 803 bzero(phymask, sizeof (phymask));
803 804 (void) sprintf(phymask,
804 805 "%x", mpt->m_phy_info[i].phy_mask);
805 806 if (strcmp(phymask, iport) == 0) {
806 807 break;
807 808 }
808 809 }
809 810
810 811 if (i == MPTSAS_MAX_PHYS) {
811 812 mptsas_log(mpt, CE_WARN, "Failed attach port %s because port"
812 813 "seems not exist", iport);
813 814 mutex_exit(&mpt->m_mutex);
814 815 return (DDI_FAILURE);
815 816 }
816 817
817 818 phy_mask = mpt->m_phy_info[i].phy_mask;
818 819
819 820 if (mpt->m_phy_info[i].port_flags & AUTO_PORT_CONFIGURATION)
820 821 dynamic_port = 1;
821 822 else
822 823 dynamic_port = 0;
823 824
824 825 /*
825 826 * Update PHY info for smhba
826 827 */
827 828 if (mptsas_smhba_phy_init(mpt)) {
828 829 mutex_exit(&mpt->m_mutex);
829 830 mptsas_log(mpt, CE_WARN, "mptsas phy update "
830 831 "failed");
831 832 return (DDI_FAILURE);
832 833 }
833 834
834 835 mutex_exit(&mpt->m_mutex);
835 836
836 837 numphys = 0;
837 838 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
838 839 if ((phy_mask >> i) & 0x01) {
839 840 numphys++;
840 841 }
841 842 }
842 843
843 844 bzero(initiator_wwnstr, sizeof (initiator_wwnstr));
844 845 (void) sprintf(initiator_wwnstr, "w%016"PRIx64,
845 846 mpt->un.m_base_wwid);
846 847
847 848 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip,
848 849 SCSI_ADDR_PROP_INITIATOR_PORT, initiator_wwnstr) !=
849 850 DDI_PROP_SUCCESS) {
850 851 (void) ddi_prop_remove(DDI_DEV_T_NONE,
851 852 dip, SCSI_ADDR_PROP_INITIATOR_PORT);
852 853 mptsas_log(mpt, CE_WARN, "mptsas Initiator port "
853 854 "prop update failed");
854 855 return (DDI_FAILURE);
855 856 }
856 857 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
857 858 MPTSAS_NUM_PHYS, numphys) !=
858 859 DDI_PROP_SUCCESS) {
859 860 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, MPTSAS_NUM_PHYS);
860 861 return (DDI_FAILURE);
861 862 }
862 863
863 864 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
864 865 "phymask", phy_mask) !=
865 866 DDI_PROP_SUCCESS) {
866 867 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "phymask");
867 868 mptsas_log(mpt, CE_WARN, "mptsas phy mask "
868 869 "prop update failed");
869 870 return (DDI_FAILURE);
870 871 }
871 872
872 873 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
873 874 "dynamic-port", dynamic_port) !=
874 875 DDI_PROP_SUCCESS) {
875 876 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "dynamic-port");
876 877 mptsas_log(mpt, CE_WARN, "mptsas dynamic port "
877 878 "prop update failed");
878 879 return (DDI_FAILURE);
879 880 }
880 881 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
881 882 MPTSAS_VIRTUAL_PORT, 0) !=
882 883 DDI_PROP_SUCCESS) {
883 884 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
884 885 MPTSAS_VIRTUAL_PORT);
885 886 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
886 887 "prop update failed");
887 888 return (DDI_FAILURE);
888 889 }
889 890 mptsas_smhba_set_phy_props(mpt,
890 891 iport, dip, numphys, &attached_devhdl);
891 892
892 893 mutex_enter(&mpt->m_mutex);
893 894 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
894 895 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)attached_devhdl;
895 896 rval = mptsas_get_sas_device_page0(mpt, page_address, &dev_hdl,
896 897 &attached_sas_wwn, &dev_info, &phy_port, &phy_id,
897 898 &pdev_hdl, &bay_num, &enclosure);
898 899 if (rval != DDI_SUCCESS) {
899 900 mptsas_log(mpt, CE_WARN,
900 901 "Failed to get device page0 for handle:%d",
901 902 attached_devhdl);
902 903 mutex_exit(&mpt->m_mutex);
903 904 return (DDI_FAILURE);
904 905 }
905 906
906 907 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
907 908 bzero(phymask, sizeof (phymask));
908 909 (void) sprintf(phymask, "%x", mpt->m_phy_info[i].phy_mask);
909 910 if (strcmp(phymask, iport) == 0) {
910 911 (void) sprintf(&mpt->m_phy_info[i].smhba_info.path[0],
911 912 "%x",
912 913 mpt->m_phy_info[i].phy_mask);
913 914 }
914 915 }
915 916 mutex_exit(&mpt->m_mutex);
916 917
917 918 bzero(attached_wwnstr, sizeof (attached_wwnstr));
918 919 (void) sprintf(attached_wwnstr, "w%016"PRIx64,
919 920 attached_sas_wwn);
920 921 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip,
921 922 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
922 923 DDI_PROP_SUCCESS) {
923 924 (void) ddi_prop_remove(DDI_DEV_T_NONE,
924 925 dip, SCSI_ADDR_PROP_ATTACHED_PORT);
925 926 return (DDI_FAILURE);
926 927 }
927 928
928 929 /* Create kstats for each phy on this iport */
929 930
930 931 mptsas_create_phy_stats(mpt, iport, dip);
931 932
932 933 /*
933 934 * register sas hba iport with mdi (MPxIO/vhci)
934 935 */
935 936 if (mdi_phci_register(MDI_HCI_CLASS_SCSI,
936 937 dip, 0) == MDI_SUCCESS) {
937 938 mpt->m_mpxio_enable = TRUE;
938 939 }
939 940 return (DDI_SUCCESS);
940 941 }
941 942
942 943 /*
943 944 * Notes:
944 945 * Set up all device state and allocate data structures,
945 946 * mutexes, condition variables, etc. for device operation.
946 947 * Add interrupts needed.
947 948 * Return DDI_SUCCESS if device is ready, else return DDI_FAILURE.
948 949 */
949 950 static int
950 951 mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
951 952 {
952 953 mptsas_t *mpt = NULL;
953 954 int instance, i, j;
954 955 int doneq_thread_num;
955 956 char intr_added = 0;
956 957 char map_setup = 0;
957 958 char config_setup = 0;
958 959 char hba_attach_setup = 0;
959 960 char smp_attach_setup = 0;
960 961 char mutex_init_done = 0;
961 962 char event_taskq_create = 0;
962 963 char dr_taskq_create = 0;
963 964 char doneq_thread_create = 0;
964 965 scsi_hba_tran_t *hba_tran;
965 966 uint_t mem_bar = MEM_SPACE;
966 967 int rval = DDI_FAILURE;
967 968
968 969 /* CONSTCOND */
969 970 ASSERT(NO_COMPETING_THREADS);
970 971
971 972 if (scsi_hba_iport_unit_address(dip)) {
972 973 return (mptsas_iport_attach(dip, cmd));
973 974 }
974 975
975 976 switch (cmd) {
976 977 case DDI_ATTACH:
977 978 break;
978 979
979 980 case DDI_RESUME:
980 981 if ((hba_tran = ddi_get_driver_private(dip)) == NULL)
981 982 return (DDI_FAILURE);
982 983
983 984 mpt = TRAN2MPT(hba_tran);
984 985
985 986 if (!mpt) {
986 987 return (DDI_FAILURE);
987 988 }
988 989
989 990 /*
990 991 * Reset hardware and softc to "no outstanding commands"
991 992 * Note that a check condition can result on first command
992 993 * to a target.
993 994 */
994 995 mutex_enter(&mpt->m_mutex);
995 996
996 997 /*
997 998 * raise power.
998 999 */
999 1000 if (mpt->m_options & MPTSAS_OPT_PM) {
1000 1001 mutex_exit(&mpt->m_mutex);
1001 1002 (void) pm_busy_component(dip, 0);
1002 1003 rval = pm_power_has_changed(dip, 0, PM_LEVEL_D0);
1003 1004 if (rval == DDI_SUCCESS) {
1004 1005 mutex_enter(&mpt->m_mutex);
1005 1006 } else {
1006 1007 /*
1007 1008 * The pm_raise_power() call above failed,
1008 1009 * and that can only occur if we were unable
1009 1010 * to reset the hardware. This is probably
1010 1011 * due to unhealty hardware, and because
1011 1012 * important filesystems(such as the root
1012 1013 * filesystem) could be on the attached disks,
1013 1014 * it would not be a good idea to continue,
1014 1015 * as we won't be entirely certain we are
1015 1016 * writing correct data. So we panic() here
1016 1017 * to not only prevent possible data corruption,
1017 1018 * but to give developers or end users a hope
1018 1019 * of identifying and correcting any problems.
1019 1020 */
1020 1021 fm_panic("mptsas could not reset hardware "
1021 1022 "during resume");
1022 1023 }
1023 1024 }
1024 1025
1025 1026 mpt->m_suspended = 0;
1026 1027
1027 1028 /*
1028 1029 * Reinitialize ioc
1029 1030 */
1030 1031 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1031 1032 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) {
1032 1033 mutex_exit(&mpt->m_mutex);
1033 1034 if (mpt->m_options & MPTSAS_OPT_PM) {
1034 1035 (void) pm_idle_component(dip, 0);
1035 1036 }
1036 1037 fm_panic("mptsas init chip fail during resume");
1037 1038 }
1038 1039 /*
1039 1040 * mptsas_update_driver_data needs interrupts so enable them
1040 1041 * first.
1041 1042 */
1042 1043 MPTSAS_ENABLE_INTR(mpt);
1043 1044 mptsas_update_driver_data(mpt);
1044 1045
1045 1046 /* start requests, if possible */
1046 1047 mptsas_restart_hba(mpt);
1047 1048
1048 1049 mutex_exit(&mpt->m_mutex);
1049 1050
1050 1051 /*
1051 1052 * Restart watch thread
1052 1053 */
1053 1054 mutex_enter(&mptsas_global_mutex);
1054 1055 if (mptsas_timeout_id == 0) {
1055 1056 mptsas_timeout_id = timeout(mptsas_watch, NULL,
1056 1057 mptsas_tick);
1057 1058 mptsas_timeouts_enabled = 1;
1058 1059 }
1059 1060 mutex_exit(&mptsas_global_mutex);
1060 1061
1061 1062 /* report idle status to pm framework */
1062 1063 if (mpt->m_options & MPTSAS_OPT_PM) {
1063 1064 (void) pm_idle_component(dip, 0);
1064 1065 }
1065 1066
1066 1067 return (DDI_SUCCESS);
1067 1068
1068 1069 default:
1069 1070 return (DDI_FAILURE);
1070 1071
1071 1072 }
1072 1073
1073 1074 instance = ddi_get_instance(dip);
1074 1075
1075 1076 /*
1076 1077 * Allocate softc information.
1077 1078 */
1078 1079 if (ddi_soft_state_zalloc(mptsas_state, instance) != DDI_SUCCESS) {
1079 1080 mptsas_log(NULL, CE_WARN,
1080 1081 "mptsas%d: cannot allocate soft state", instance);
1081 1082 goto fail;
↓ open down ↓ |
698 lines elided |
↑ open up ↑ |
1082 1083 }
1083 1084
1084 1085 mpt = ddi_get_soft_state(mptsas_state, instance);
1085 1086
1086 1087 if (mpt == NULL) {
1087 1088 mptsas_log(NULL, CE_WARN,
1088 1089 "mptsas%d: cannot get soft state", instance);
1089 1090 goto fail;
1090 1091 }
1091 1092
1093 + /* Mark us as a primary ioctl node for an instance. */
1094 + (void) ddi_prop_update_int(DDI_DEV_T_NONE, dip, "primary-ioctl-node",
1095 + instance);
1096 +
1092 1097 /* Indicate that we are 'sizeof (scsi_*(9S))' clean. */
1093 1098 scsi_size_clean(dip);
1094 1099
1095 1100 mpt->m_dip = dip;
1096 1101 mpt->m_instance = instance;
1097 1102
1098 1103 /* Make a per-instance copy of the structures */
1099 1104 mpt->m_io_dma_attr = mptsas_dma_attrs64;
1100 1105 mpt->m_msg_dma_attr = mptsas_dma_attrs;
1101 1106 mpt->m_reg_acc_attr = mptsas_dev_attr;
1102 1107 mpt->m_dev_acc_attr = mptsas_dev_attr;
1103 1108
1104 1109 /*
1105 1110 * Initialize FMA
1106 1111 */
1107 1112 mpt->m_fm_capabilities = ddi_getprop(DDI_DEV_T_ANY, mpt->m_dip,
1108 1113 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable",
1109 1114 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
1110 1115 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
1111 1116
1112 1117 mptsas_fm_init(mpt);
1113 1118
1114 1119 if (mptsas_alloc_handshake_msg(mpt,
1115 1120 sizeof (Mpi2SCSITaskManagementRequest_t)) == DDI_FAILURE) {
1116 1121 mptsas_log(mpt, CE_WARN, "cannot initialize handshake msg.");
1117 1122 goto fail;
1118 1123 }
1119 1124
1120 1125 /*
1121 1126 * Setup configuration space
1122 1127 */
1123 1128 if (mptsas_config_space_init(mpt) == FALSE) {
1124 1129 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init failed");
1125 1130 goto fail;
1126 1131 }
1127 1132 config_setup++;
1128 1133
1129 1134 if (ddi_regs_map_setup(dip, mem_bar, (caddr_t *)&mpt->m_reg,
1130 1135 0, 0, &mpt->m_reg_acc_attr, &mpt->m_datap) != DDI_SUCCESS) {
1131 1136 mptsas_log(mpt, CE_WARN, "map setup failed");
1132 1137 goto fail;
1133 1138 }
1134 1139 map_setup++;
1135 1140
1136 1141 /*
1137 1142 * A taskq is created for dealing with the event handler
1138 1143 */
1139 1144 if ((mpt->m_event_taskq = ddi_taskq_create(dip, "mptsas_event_taskq",
1140 1145 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
1141 1146 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create failed");
1142 1147 goto fail;
1143 1148 }
1144 1149 event_taskq_create++;
1145 1150
1146 1151 /*
1147 1152 * A taskq is created for dealing with dr events
1148 1153 */
1149 1154 if ((mpt->m_dr_taskq = ddi_taskq_create(dip,
1150 1155 "mptsas_dr_taskq",
1151 1156 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
1152 1157 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create for discovery "
1153 1158 "failed");
1154 1159 goto fail;
1155 1160 }
1156 1161 dr_taskq_create++;
1157 1162
1158 1163 mpt->m_doneq_thread_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1159 1164 0, "mptsas_doneq_thread_threshold_prop", 10);
1160 1165 mpt->m_doneq_length_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1161 1166 0, "mptsas_doneq_length_threshold_prop", 8);
1162 1167 mpt->m_doneq_thread_n = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1163 1168 0, "mptsas_doneq_thread_n_prop", 8);
1164 1169
1165 1170 if (mpt->m_doneq_thread_n) {
1166 1171 cv_init(&mpt->m_doneq_thread_cv, NULL, CV_DRIVER, NULL);
1167 1172 mutex_init(&mpt->m_doneq_mutex, NULL, MUTEX_DRIVER, NULL);
1168 1173
1169 1174 mutex_enter(&mpt->m_doneq_mutex);
1170 1175 mpt->m_doneq_thread_id =
1171 1176 kmem_zalloc(sizeof (mptsas_doneq_thread_list_t)
1172 1177 * mpt->m_doneq_thread_n, KM_SLEEP);
1173 1178
1174 1179 for (j = 0; j < mpt->m_doneq_thread_n; j++) {
1175 1180 cv_init(&mpt->m_doneq_thread_id[j].cv, NULL,
1176 1181 CV_DRIVER, NULL);
1177 1182 mutex_init(&mpt->m_doneq_thread_id[j].mutex, NULL,
1178 1183 MUTEX_DRIVER, NULL);
1179 1184 mutex_enter(&mpt->m_doneq_thread_id[j].mutex);
1180 1185 mpt->m_doneq_thread_id[j].flag |=
1181 1186 MPTSAS_DONEQ_THREAD_ACTIVE;
1182 1187 mpt->m_doneq_thread_id[j].arg.mpt = mpt;
1183 1188 mpt->m_doneq_thread_id[j].arg.t = j;
1184 1189 mpt->m_doneq_thread_id[j].threadp =
1185 1190 thread_create(NULL, 0, mptsas_doneq_thread,
1186 1191 &mpt->m_doneq_thread_id[j].arg,
1187 1192 0, &p0, TS_RUN, minclsyspri);
1188 1193 mpt->m_doneq_thread_id[j].donetail =
1189 1194 &mpt->m_doneq_thread_id[j].doneq;
1190 1195 mutex_exit(&mpt->m_doneq_thread_id[j].mutex);
1191 1196 }
1192 1197 mutex_exit(&mpt->m_doneq_mutex);
1193 1198 doneq_thread_create++;
1194 1199 }
1195 1200
1196 1201 /* Initialize mutex used in interrupt handler */
1197 1202 mutex_init(&mpt->m_mutex, NULL, MUTEX_DRIVER,
1198 1203 DDI_INTR_PRI(mpt->m_intr_pri));
1199 1204 mutex_init(&mpt->m_passthru_mutex, NULL, MUTEX_DRIVER, NULL);
1200 1205 mutex_init(&mpt->m_intr_mutex, NULL, MUTEX_DRIVER,
1201 1206 DDI_INTR_PRI(mpt->m_intr_pri));
1202 1207 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1203 1208 mutex_init(&mpt->m_phy_info[i].smhba_info.phy_mutex,
1204 1209 NULL, MUTEX_DRIVER,
1205 1210 DDI_INTR_PRI(mpt->m_intr_pri));
1206 1211 }
1207 1212
1208 1213 cv_init(&mpt->m_cv, NULL, CV_DRIVER, NULL);
1209 1214 cv_init(&mpt->m_passthru_cv, NULL, CV_DRIVER, NULL);
1210 1215 cv_init(&mpt->m_fw_cv, NULL, CV_DRIVER, NULL);
1211 1216 cv_init(&mpt->m_config_cv, NULL, CV_DRIVER, NULL);
1212 1217 cv_init(&mpt->m_fw_diag_cv, NULL, CV_DRIVER, NULL);
1213 1218 mutex_init_done++;
1214 1219
1215 1220 /*
1216 1221 * Disable hardware interrupt since we're not ready to
1217 1222 * handle it yet.
1218 1223 */
1219 1224 MPTSAS_DISABLE_INTR(mpt);
1220 1225 if (mptsas_register_intrs(mpt) == FALSE)
1221 1226 goto fail;
1222 1227 intr_added++;
1223 1228
1224 1229 mutex_enter(&mpt->m_mutex);
1225 1230 /*
1226 1231 * Initialize power management component
1227 1232 */
1228 1233 if (mpt->m_options & MPTSAS_OPT_PM) {
1229 1234 if (mptsas_init_pm(mpt)) {
1230 1235 mutex_exit(&mpt->m_mutex);
1231 1236 mptsas_log(mpt, CE_WARN, "mptsas pm initialization "
1232 1237 "failed");
1233 1238 goto fail;
1234 1239 }
1235 1240 }
1236 1241
1237 1242 /*
1238 1243 * Initialize chip using Message Unit Reset, if allowed
1239 1244 */
1240 1245 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1241 1246 if (mptsas_init_chip(mpt, TRUE) == DDI_FAILURE) {
1242 1247 mutex_exit(&mpt->m_mutex);
1243 1248 mptsas_log(mpt, CE_WARN, "mptsas chip initialization failed");
1244 1249 goto fail;
1245 1250 }
1246 1251
1247 1252 /*
1248 1253 * Fill in the phy_info structure and get the base WWID
1249 1254 */
1250 1255 if (mptsas_get_manufacture_page5(mpt) == DDI_FAILURE) {
1251 1256 mptsas_log(mpt, CE_WARN,
1252 1257 "mptsas_get_manufacture_page5 failed!");
1253 1258 goto fail;
1254 1259 }
1255 1260
1256 1261 if (mptsas_get_sas_io_unit_page_hndshk(mpt)) {
1257 1262 mptsas_log(mpt, CE_WARN,
1258 1263 "mptsas_get_sas_io_unit_page_hndshk failed!");
1259 1264 goto fail;
1260 1265 }
1261 1266
1262 1267 if (mptsas_get_manufacture_page0(mpt) == DDI_FAILURE) {
1263 1268 mptsas_log(mpt, CE_WARN,
1264 1269 "mptsas_get_manufacture_page0 failed!");
1265 1270 goto fail;
1266 1271 }
1267 1272
1268 1273 mutex_exit(&mpt->m_mutex);
1269 1274
1270 1275 /*
1271 1276 * Register the iport for multiple port HBA
1272 1277 */
1273 1278 mptsas_iport_register(mpt);
1274 1279
1275 1280 /*
1276 1281 * initialize SCSI HBA transport structure
1277 1282 */
1278 1283 if (mptsas_hba_setup(mpt) == FALSE)
1279 1284 goto fail;
1280 1285 hba_attach_setup++;
1281 1286
1282 1287 if (mptsas_smp_setup(mpt) == FALSE)
1283 1288 goto fail;
1284 1289 smp_attach_setup++;
1285 1290
1286 1291 if (mptsas_cache_create(mpt) == FALSE)
1287 1292 goto fail;
1288 1293
1289 1294 mpt->m_scsi_reset_delay = ddi_prop_get_int(DDI_DEV_T_ANY,
1290 1295 dip, 0, "scsi-reset-delay", SCSI_DEFAULT_RESET_DELAY);
1291 1296 if (mpt->m_scsi_reset_delay == 0) {
1292 1297 mptsas_log(mpt, CE_NOTE,
1293 1298 "scsi_reset_delay of 0 is not recommended,"
1294 1299 " resetting to SCSI_DEFAULT_RESET_DELAY\n");
1295 1300 mpt->m_scsi_reset_delay = SCSI_DEFAULT_RESET_DELAY;
1296 1301 }
1297 1302
1298 1303 /*
1299 1304 * Initialize the wait and done FIFO queue
1300 1305 */
1301 1306 mpt->m_donetail = &mpt->m_doneq;
1302 1307 mpt->m_waitqtail = &mpt->m_waitq;
1303 1308
1304 1309 /*
1305 1310 * ioc cmd queue initialize
1306 1311 */
1307 1312 mpt->m_ioc_event_cmdtail = &mpt->m_ioc_event_cmdq;
1308 1313 mpt->m_dev_handle = 0xFFFF;
1309 1314
1310 1315 MPTSAS_ENABLE_INTR(mpt);
1311 1316
1312 1317 /*
1313 1318 * enable event notification
1314 1319 */
1315 1320 mutex_enter(&mpt->m_mutex);
1316 1321 if (mptsas_ioc_enable_event_notification(mpt)) {
1317 1322 mutex_exit(&mpt->m_mutex);
1318 1323 goto fail;
1319 1324 }
1320 1325 mutex_exit(&mpt->m_mutex);
1321 1326
1322 1327 /*
1323 1328 * Initialize PHY info for smhba
1324 1329 */
1325 1330 if (mptsas_smhba_setup(mpt)) {
1326 1331 mptsas_log(mpt, CE_WARN, "mptsas phy initialization "
1327 1332 "failed");
1328 1333 goto fail;
1329 1334 }
1330 1335
1331 1336 /* Check all dma handles allocated in attach */
1332 1337 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl)
1333 1338 != DDI_SUCCESS) ||
1334 1339 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl)
1335 1340 != DDI_SUCCESS) ||
1336 1341 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl)
1337 1342 != DDI_SUCCESS) ||
1338 1343 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl)
1339 1344 != DDI_SUCCESS) ||
1340 1345 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl)
1341 1346 != DDI_SUCCESS)) {
1342 1347 goto fail;
1343 1348 }
1344 1349
1345 1350 /* Check all acc handles allocated in attach */
1346 1351 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) ||
1347 1352 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl)
1348 1353 != DDI_SUCCESS) ||
1349 1354 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl)
1350 1355 != DDI_SUCCESS) ||
1351 1356 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl)
1352 1357 != DDI_SUCCESS) ||
1353 1358 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl)
1354 1359 != DDI_SUCCESS) ||
1355 1360 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl)
1356 1361 != DDI_SUCCESS) ||
1357 1362 (mptsas_check_acc_handle(mpt->m_config_handle)
1358 1363 != DDI_SUCCESS)) {
1359 1364 goto fail;
1360 1365 }
1361 1366
1362 1367 /*
1363 1368 * After this point, we are not going to fail the attach.
1364 1369 */
1365 1370 /*
1366 1371 * used for mptsas_watch
1367 1372 */
1368 1373 mptsas_list_add(mpt);
1369 1374
1370 1375 mutex_enter(&mptsas_global_mutex);
1371 1376 if (mptsas_timeouts_enabled == 0) {
1372 1377 mptsas_scsi_watchdog_tick = ddi_prop_get_int(DDI_DEV_T_ANY,
1373 1378 dip, 0, "scsi-watchdog-tick", DEFAULT_WD_TICK);
1374 1379
1375 1380 mptsas_tick = mptsas_scsi_watchdog_tick *
1376 1381 drv_usectohz((clock_t)1000000);
1377 1382
1378 1383 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick);
1379 1384 mptsas_timeouts_enabled = 1;
1380 1385 }
1381 1386 mutex_exit(&mptsas_global_mutex);
1382 1387
1383 1388 /* Print message of HBA present */
1384 1389 ddi_report_dev(dip);
1385 1390
1386 1391 /* report idle status to pm framework */
1387 1392 if (mpt->m_options & MPTSAS_OPT_PM) {
1388 1393 (void) pm_idle_component(dip, 0);
1389 1394 }
1390 1395
1391 1396 return (DDI_SUCCESS);
1392 1397
1393 1398 fail:
1394 1399 mptsas_log(mpt, CE_WARN, "attach failed");
1395 1400 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE);
1396 1401 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST);
1397 1402 if (mpt) {
1398 1403 mutex_enter(&mptsas_global_mutex);
1399 1404
1400 1405 if (mptsas_timeout_id && (mptsas_head == NULL)) {
1401 1406 timeout_id_t tid = mptsas_timeout_id;
1402 1407 mptsas_timeouts_enabled = 0;
1403 1408 mptsas_timeout_id = 0;
1404 1409 mutex_exit(&mptsas_global_mutex);
1405 1410 (void) untimeout(tid);
1406 1411 mutex_enter(&mptsas_global_mutex);
1407 1412 }
1408 1413 mutex_exit(&mptsas_global_mutex);
1409 1414 /* deallocate in reverse order */
1410 1415 mptsas_cache_destroy(mpt);
1411 1416
1412 1417 if (smp_attach_setup) {
1413 1418 mptsas_smp_teardown(mpt);
1414 1419 }
1415 1420 if (hba_attach_setup) {
1416 1421 mptsas_hba_teardown(mpt);
1417 1422 }
1418 1423
1419 1424 if (mpt->m_active) {
1420 1425 mptsas_hash_uninit(&mpt->m_active->m_smptbl,
1421 1426 sizeof (mptsas_smp_t));
1422 1427 mptsas_hash_uninit(&mpt->m_active->m_tgttbl,
1423 1428 sizeof (mptsas_target_t));
1424 1429 mptsas_free_active_slots(mpt);
1425 1430 }
1426 1431 if (intr_added) {
1427 1432 mptsas_unregister_intrs(mpt);
1428 1433 }
1429 1434
1430 1435 if (doneq_thread_create) {
1431 1436 mutex_enter(&mpt->m_doneq_mutex);
1432 1437 doneq_thread_num = mpt->m_doneq_thread_n;
1433 1438 for (j = 0; j < mpt->m_doneq_thread_n; j++) {
1434 1439 mutex_enter(&mpt->m_doneq_thread_id[j].mutex);
1435 1440 mpt->m_doneq_thread_id[j].flag &=
1436 1441 (~MPTSAS_DONEQ_THREAD_ACTIVE);
1437 1442 cv_signal(&mpt->m_doneq_thread_id[j].cv);
1438 1443 mutex_exit(&mpt->m_doneq_thread_id[j].mutex);
1439 1444 }
1440 1445 while (mpt->m_doneq_thread_n) {
1441 1446 cv_wait(&mpt->m_doneq_thread_cv,
1442 1447 &mpt->m_doneq_mutex);
1443 1448 }
1444 1449 for (j = 0; j < doneq_thread_num; j++) {
1445 1450 cv_destroy(&mpt->m_doneq_thread_id[j].cv);
1446 1451 mutex_destroy(&mpt->m_doneq_thread_id[j].mutex);
1447 1452 }
1448 1453 kmem_free(mpt->m_doneq_thread_id,
1449 1454 sizeof (mptsas_doneq_thread_list_t)
1450 1455 * doneq_thread_num);
1451 1456 mutex_exit(&mpt->m_doneq_mutex);
1452 1457 cv_destroy(&mpt->m_doneq_thread_cv);
1453 1458 mutex_destroy(&mpt->m_doneq_mutex);
1454 1459 }
1455 1460 if (event_taskq_create) {
1456 1461 ddi_taskq_destroy(mpt->m_event_taskq);
1457 1462 }
1458 1463 if (dr_taskq_create) {
1459 1464 ddi_taskq_destroy(mpt->m_dr_taskq);
1460 1465 }
1461 1466 if (mutex_init_done) {
1462 1467 mutex_destroy(&mpt->m_intr_mutex);
1463 1468 mutex_destroy(&mpt->m_passthru_mutex);
1464 1469 mutex_destroy(&mpt->m_mutex);
1465 1470 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1466 1471 mutex_destroy(
1467 1472 &mpt->m_phy_info[i].smhba_info.phy_mutex);
1468 1473 }
1469 1474 cv_destroy(&mpt->m_cv);
1470 1475 cv_destroy(&mpt->m_passthru_cv);
1471 1476 cv_destroy(&mpt->m_fw_cv);
1472 1477 cv_destroy(&mpt->m_config_cv);
1473 1478 cv_destroy(&mpt->m_fw_diag_cv);
1474 1479 }
1475 1480
1476 1481 if (map_setup) {
1477 1482 mptsas_cfg_fini(mpt);
1478 1483 }
1479 1484 if (config_setup) {
1480 1485 mptsas_config_space_fini(mpt);
1481 1486 }
1482 1487 mptsas_free_handshake_msg(mpt);
1483 1488 mptsas_hba_fini(mpt);
1484 1489
1485 1490 mptsas_fm_fini(mpt);
1486 1491 ddi_soft_state_free(mptsas_state, instance);
1487 1492 ddi_prop_remove_all(dip);
1488 1493 }
1489 1494 return (DDI_FAILURE);
1490 1495 }
1491 1496
1492 1497 static int
1493 1498 mptsas_suspend(dev_info_t *devi)
1494 1499 {
1495 1500 mptsas_t *mpt, *g;
1496 1501 scsi_hba_tran_t *tran;
1497 1502
1498 1503 if (scsi_hba_iport_unit_address(devi)) {
1499 1504 return (DDI_SUCCESS);
1500 1505 }
1501 1506
1502 1507 if ((tran = ddi_get_driver_private(devi)) == NULL)
1503 1508 return (DDI_SUCCESS);
1504 1509
1505 1510 mpt = TRAN2MPT(tran);
1506 1511 if (!mpt) {
1507 1512 return (DDI_SUCCESS);
1508 1513 }
1509 1514
1510 1515 mutex_enter(&mpt->m_mutex);
1511 1516
1512 1517 if (mpt->m_suspended++) {
1513 1518 mutex_exit(&mpt->m_mutex);
1514 1519 return (DDI_SUCCESS);
1515 1520 }
1516 1521
1517 1522 /*
1518 1523 * Cancel timeout threads for this mpt
1519 1524 */
1520 1525 if (mpt->m_quiesce_timeid) {
1521 1526 timeout_id_t tid = mpt->m_quiesce_timeid;
1522 1527 mpt->m_quiesce_timeid = 0;
1523 1528 mutex_exit(&mpt->m_mutex);
1524 1529 (void) untimeout(tid);
1525 1530 mutex_enter(&mpt->m_mutex);
1526 1531 }
1527 1532
1528 1533 if (mpt->m_restart_cmd_timeid) {
1529 1534 timeout_id_t tid = mpt->m_restart_cmd_timeid;
1530 1535 mpt->m_restart_cmd_timeid = 0;
1531 1536 mutex_exit(&mpt->m_mutex);
1532 1537 (void) untimeout(tid);
1533 1538 mutex_enter(&mpt->m_mutex);
1534 1539 }
1535 1540
1536 1541 mutex_exit(&mpt->m_mutex);
1537 1542
1538 1543 (void) pm_idle_component(mpt->m_dip, 0);
1539 1544
1540 1545 /*
1541 1546 * Cancel watch threads if all mpts suspended
1542 1547 */
1543 1548 rw_enter(&mptsas_global_rwlock, RW_WRITER);
1544 1549 for (g = mptsas_head; g != NULL; g = g->m_next) {
1545 1550 if (!g->m_suspended)
1546 1551 break;
1547 1552 }
1548 1553 rw_exit(&mptsas_global_rwlock);
1549 1554
1550 1555 mutex_enter(&mptsas_global_mutex);
1551 1556 if (g == NULL) {
1552 1557 timeout_id_t tid;
1553 1558
1554 1559 mptsas_timeouts_enabled = 0;
1555 1560 if (mptsas_timeout_id) {
1556 1561 tid = mptsas_timeout_id;
1557 1562 mptsas_timeout_id = 0;
1558 1563 mutex_exit(&mptsas_global_mutex);
1559 1564 (void) untimeout(tid);
1560 1565 mutex_enter(&mptsas_global_mutex);
1561 1566 }
1562 1567 if (mptsas_reset_watch) {
1563 1568 tid = mptsas_reset_watch;
1564 1569 mptsas_reset_watch = 0;
1565 1570 mutex_exit(&mptsas_global_mutex);
1566 1571 (void) untimeout(tid);
1567 1572 mutex_enter(&mptsas_global_mutex);
1568 1573 }
1569 1574 }
1570 1575 mutex_exit(&mptsas_global_mutex);
1571 1576
1572 1577 mutex_enter(&mpt->m_mutex);
1573 1578
1574 1579 /*
1575 1580 * If this mpt is not in full power(PM_LEVEL_D0), just return.
1576 1581 */
1577 1582 if ((mpt->m_options & MPTSAS_OPT_PM) &&
1578 1583 (mpt->m_power_level != PM_LEVEL_D0)) {
1579 1584 mutex_exit(&mpt->m_mutex);
1580 1585 return (DDI_SUCCESS);
1581 1586 }
1582 1587
1583 1588 /* Disable HBA interrupts in hardware */
1584 1589 MPTSAS_DISABLE_INTR(mpt);
1585 1590 /*
1586 1591 * Send RAID action system shutdown to sync IR
1587 1592 */
1588 1593 mptsas_raid_action_system_shutdown(mpt);
1589 1594
1590 1595 mutex_exit(&mpt->m_mutex);
1591 1596
1592 1597 /* drain the taskq */
1593 1598 ddi_taskq_wait(mpt->m_event_taskq);
1594 1599 ddi_taskq_wait(mpt->m_dr_taskq);
1595 1600
1596 1601 return (DDI_SUCCESS);
1597 1602 }
1598 1603
1599 1604 #ifdef __sparc
1600 1605 /*ARGSUSED*/
1601 1606 static int
1602 1607 mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd)
1603 1608 {
1604 1609 mptsas_t *mpt;
1605 1610 scsi_hba_tran_t *tran;
1606 1611
1607 1612 /*
1608 1613 * If this call is for iport, just return.
1609 1614 */
1610 1615 if (scsi_hba_iport_unit_address(devi))
1611 1616 return (DDI_SUCCESS);
1612 1617
1613 1618 if ((tran = ddi_get_driver_private(devi)) == NULL)
1614 1619 return (DDI_SUCCESS);
1615 1620
1616 1621 if ((mpt = TRAN2MPT(tran)) == NULL)
1617 1622 return (DDI_SUCCESS);
1618 1623
1619 1624 /*
1620 1625 * Send RAID action system shutdown to sync IR. Disable HBA
1621 1626 * interrupts in hardware first.
1622 1627 */
1623 1628 MPTSAS_DISABLE_INTR(mpt);
1624 1629 mptsas_raid_action_system_shutdown(mpt);
1625 1630
1626 1631 return (DDI_SUCCESS);
1627 1632 }
1628 1633 #else /* __sparc */
1629 1634 /*
1630 1635 * quiesce(9E) entry point.
1631 1636 *
1632 1637 * This function is called when the system is single-threaded at high
1633 1638 * PIL with preemption disabled. Therefore, this function must not be
1634 1639 * blocked.
1635 1640 *
1636 1641 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
1637 1642 * DDI_FAILURE indicates an error condition and should almost never happen.
1638 1643 */
1639 1644 static int
1640 1645 mptsas_quiesce(dev_info_t *devi)
1641 1646 {
1642 1647 mptsas_t *mpt;
1643 1648 scsi_hba_tran_t *tran;
1644 1649
1645 1650 /*
1646 1651 * If this call is for iport, just return.
1647 1652 */
1648 1653 if (scsi_hba_iport_unit_address(devi))
1649 1654 return (DDI_SUCCESS);
1650 1655
1651 1656 if ((tran = ddi_get_driver_private(devi)) == NULL)
1652 1657 return (DDI_SUCCESS);
1653 1658
1654 1659 if ((mpt = TRAN2MPT(tran)) == NULL)
1655 1660 return (DDI_SUCCESS);
1656 1661
1657 1662 /* Disable HBA interrupts in hardware */
1658 1663 MPTSAS_DISABLE_INTR(mpt);
1659 1664 /* Send RAID action system shutdonw to sync IR */
1660 1665 mptsas_raid_action_system_shutdown(mpt);
1661 1666
1662 1667 return (DDI_SUCCESS);
1663 1668 }
1664 1669 #endif /* __sparc */
1665 1670
1666 1671 /*
1667 1672 * detach(9E). Remove all device allocations and system resources;
1668 1673 * disable device interrupts.
1669 1674 * Return DDI_SUCCESS if done; DDI_FAILURE if there's a problem.
1670 1675 */
1671 1676 static int
1672 1677 mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd)
1673 1678 {
1674 1679 /* CONSTCOND */
1675 1680 ASSERT(NO_COMPETING_THREADS);
1676 1681 NDBG0(("mptsas_detach: dip=0x%p cmd=0x%p", (void *)devi, (void *)cmd));
1677 1682
1678 1683 switch (cmd) {
1679 1684 case DDI_DETACH:
1680 1685 return (mptsas_do_detach(devi));
1681 1686
1682 1687 case DDI_SUSPEND:
1683 1688 return (mptsas_suspend(devi));
1684 1689
1685 1690 default:
1686 1691 return (DDI_FAILURE);
1687 1692 }
1688 1693 /* NOTREACHED */
1689 1694 }
1690 1695
1691 1696 static int
1692 1697 mptsas_do_detach(dev_info_t *dip)
1693 1698 {
1694 1699 mptsas_t *mpt;
1695 1700 scsi_hba_tran_t *tran;
1696 1701 int circ = 0;
1697 1702 int circ1 = 0;
1698 1703 mdi_pathinfo_t *pip = NULL;
1699 1704 int i;
1700 1705 int doneq_thread_num = 0;
1701 1706
1702 1707 NDBG0(("mptsas_do_detach: dip=0x%p", (void *)dip));
1703 1708
1704 1709 if ((tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == NULL)
1705 1710 return (DDI_FAILURE);
1706 1711
1707 1712 mpt = TRAN2MPT(tran);
1708 1713 if (!mpt) {
1709 1714 return (DDI_FAILURE);
1710 1715 }
1711 1716 /*
1712 1717 * Still have pathinfo child, should not detach mpt driver
1713 1718 */
1714 1719 if (scsi_hba_iport_unit_address(dip)) {
1715 1720 if (mpt->m_mpxio_enable) {
1716 1721 /*
1717 1722 * MPxIO enabled for the iport
1718 1723 */
1719 1724 ndi_devi_enter(scsi_vhci_dip, &circ1);
1720 1725 ndi_devi_enter(dip, &circ);
1721 1726 while (pip = mdi_get_next_client_path(dip, NULL)) {
1722 1727 if (mdi_pi_free(pip, 0) == MDI_SUCCESS) {
1723 1728 continue;
1724 1729 }
1725 1730 ndi_devi_exit(dip, circ);
1726 1731 ndi_devi_exit(scsi_vhci_dip, circ1);
1727 1732 NDBG12(("detach failed because of "
1728 1733 "outstanding path info"));
1729 1734 return (DDI_FAILURE);
1730 1735 }
1731 1736 ndi_devi_exit(dip, circ);
1732 1737 ndi_devi_exit(scsi_vhci_dip, circ1);
1733 1738 (void) mdi_phci_unregister(dip, 0);
1734 1739 }
1735 1740
1736 1741 ddi_prop_remove_all(dip);
1737 1742
1738 1743 return (DDI_SUCCESS);
1739 1744 }
1740 1745
1741 1746 /* Make sure power level is D0 before accessing registers */
1742 1747 if (mpt->m_options & MPTSAS_OPT_PM) {
1743 1748 (void) pm_busy_component(dip, 0);
1744 1749 if (mpt->m_power_level != PM_LEVEL_D0) {
1745 1750 if (pm_raise_power(dip, 0, PM_LEVEL_D0) !=
1746 1751 DDI_SUCCESS) {
1747 1752 mptsas_log(mpt, CE_WARN,
1748 1753 "mptsas%d: Raise power request failed.",
1749 1754 mpt->m_instance);
1750 1755 (void) pm_idle_component(dip, 0);
1751 1756 return (DDI_FAILURE);
1752 1757 }
1753 1758 }
1754 1759 }
1755 1760
1756 1761 /*
1757 1762 * Send RAID action system shutdown to sync IR. After action, send a
1758 1763 * Message Unit Reset. Since after that DMA resource will be freed,
1759 1764 * set ioc to READY state will avoid HBA initiated DMA operation.
1760 1765 */
1761 1766 mutex_enter(&mpt->m_mutex);
1762 1767 MPTSAS_DISABLE_INTR(mpt);
1763 1768 mptsas_raid_action_system_shutdown(mpt);
1764 1769 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1765 1770 (void) mptsas_ioc_reset(mpt, FALSE);
1766 1771 mutex_exit(&mpt->m_mutex);
1767 1772 mptsas_rem_intrs(mpt);
1768 1773 ddi_taskq_destroy(mpt->m_event_taskq);
1769 1774 ddi_taskq_destroy(mpt->m_dr_taskq);
1770 1775
1771 1776 if (mpt->m_doneq_thread_n) {
1772 1777 mutex_enter(&mpt->m_doneq_mutex);
1773 1778 doneq_thread_num = mpt->m_doneq_thread_n;
1774 1779 for (i = 0; i < mpt->m_doneq_thread_n; i++) {
1775 1780 mutex_enter(&mpt->m_doneq_thread_id[i].mutex);
1776 1781 mpt->m_doneq_thread_id[i].flag &=
1777 1782 (~MPTSAS_DONEQ_THREAD_ACTIVE);
1778 1783 cv_signal(&mpt->m_doneq_thread_id[i].cv);
1779 1784 mutex_exit(&mpt->m_doneq_thread_id[i].mutex);
1780 1785 }
1781 1786 while (mpt->m_doneq_thread_n) {
1782 1787 cv_wait(&mpt->m_doneq_thread_cv,
1783 1788 &mpt->m_doneq_mutex);
1784 1789 }
1785 1790 for (i = 0; i < doneq_thread_num; i++) {
1786 1791 cv_destroy(&mpt->m_doneq_thread_id[i].cv);
1787 1792 mutex_destroy(&mpt->m_doneq_thread_id[i].mutex);
1788 1793 }
1789 1794 kmem_free(mpt->m_doneq_thread_id,
1790 1795 sizeof (mptsas_doneq_thread_list_t)
1791 1796 * doneq_thread_num);
1792 1797 mutex_exit(&mpt->m_doneq_mutex);
1793 1798 cv_destroy(&mpt->m_doneq_thread_cv);
1794 1799 mutex_destroy(&mpt->m_doneq_mutex);
1795 1800 }
1796 1801
1797 1802 scsi_hba_reset_notify_tear_down(mpt->m_reset_notify_listf);
1798 1803
1799 1804 mptsas_list_del(mpt);
1800 1805
1801 1806 /*
1802 1807 * Cancel timeout threads for this mpt
1803 1808 */
1804 1809 mutex_enter(&mpt->m_mutex);
1805 1810 if (mpt->m_quiesce_timeid) {
1806 1811 timeout_id_t tid = mpt->m_quiesce_timeid;
1807 1812 mpt->m_quiesce_timeid = 0;
1808 1813 mutex_exit(&mpt->m_mutex);
1809 1814 (void) untimeout(tid);
1810 1815 mutex_enter(&mpt->m_mutex);
1811 1816 }
1812 1817
1813 1818 if (mpt->m_restart_cmd_timeid) {
1814 1819 timeout_id_t tid = mpt->m_restart_cmd_timeid;
1815 1820 mpt->m_restart_cmd_timeid = 0;
1816 1821 mutex_exit(&mpt->m_mutex);
1817 1822 (void) untimeout(tid);
1818 1823 mutex_enter(&mpt->m_mutex);
1819 1824 }
1820 1825
1821 1826 mutex_exit(&mpt->m_mutex);
1822 1827
1823 1828 /*
1824 1829 * last mpt? ... if active, CANCEL watch threads.
1825 1830 */
1826 1831 mutex_enter(&mptsas_global_mutex);
1827 1832 if (mptsas_head == NULL) {
1828 1833 timeout_id_t tid;
1829 1834 /*
1830 1835 * Clear mptsas_timeouts_enable so that the watch thread
1831 1836 * gets restarted on DDI_ATTACH
1832 1837 */
1833 1838 mptsas_timeouts_enabled = 0;
1834 1839 if (mptsas_timeout_id) {
1835 1840 tid = mptsas_timeout_id;
1836 1841 mptsas_timeout_id = 0;
1837 1842 mutex_exit(&mptsas_global_mutex);
1838 1843 (void) untimeout(tid);
1839 1844 mutex_enter(&mptsas_global_mutex);
1840 1845 }
1841 1846 if (mptsas_reset_watch) {
1842 1847 tid = mptsas_reset_watch;
1843 1848 mptsas_reset_watch = 0;
1844 1849 mutex_exit(&mptsas_global_mutex);
1845 1850 (void) untimeout(tid);
1846 1851 mutex_enter(&mptsas_global_mutex);
1847 1852 }
1848 1853 }
1849 1854 mutex_exit(&mptsas_global_mutex);
1850 1855
1851 1856 /*
1852 1857 * Delete Phy stats
1853 1858 */
1854 1859 mptsas_destroy_phy_stats(mpt);
1855 1860
1856 1861 /*
1857 1862 * Delete nt_active.
1858 1863 */
1859 1864 mutex_enter(&mpt->m_mutex);
1860 1865 mptsas_hash_uninit(&mpt->m_active->m_tgttbl, sizeof (mptsas_target_t));
1861 1866 mptsas_hash_uninit(&mpt->m_active->m_smptbl, sizeof (mptsas_smp_t));
1862 1867 mptsas_free_active_slots(mpt);
1863 1868 mutex_exit(&mpt->m_mutex);
1864 1869
1865 1870 /* deallocate everything that was allocated in mptsas_attach */
1866 1871 mptsas_cache_destroy(mpt);
1867 1872
1868 1873 mptsas_hba_fini(mpt);
1869 1874 mptsas_cfg_fini(mpt);
1870 1875
1871 1876 /* Lower the power informing PM Framework */
1872 1877 if (mpt->m_options & MPTSAS_OPT_PM) {
1873 1878 if (pm_lower_power(dip, 0, PM_LEVEL_D3) != DDI_SUCCESS)
1874 1879 mptsas_log(mpt, CE_WARN,
1875 1880 "!mptsas%d: Lower power request failed "
1876 1881 "during detach, ignoring.",
1877 1882 mpt->m_instance);
1878 1883 }
1879 1884
1880 1885 mutex_destroy(&mpt->m_intr_mutex);
1881 1886 mutex_destroy(&mpt->m_passthru_mutex);
1882 1887 mutex_destroy(&mpt->m_mutex);
1883 1888 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1884 1889 mutex_destroy(&mpt->m_phy_info[i].smhba_info.phy_mutex);
1885 1890 }
1886 1891 cv_destroy(&mpt->m_cv);
1887 1892 cv_destroy(&mpt->m_passthru_cv);
1888 1893 cv_destroy(&mpt->m_fw_cv);
1889 1894 cv_destroy(&mpt->m_config_cv);
1890 1895 cv_destroy(&mpt->m_fw_diag_cv);
1891 1896
1892 1897
1893 1898 mptsas_smp_teardown(mpt);
1894 1899 mptsas_hba_teardown(mpt);
1895 1900
1896 1901 mptsas_config_space_fini(mpt);
1897 1902
1898 1903 mptsas_free_handshake_msg(mpt);
1899 1904
1900 1905 mptsas_fm_fini(mpt);
1901 1906 ddi_soft_state_free(mptsas_state, ddi_get_instance(dip));
1902 1907 ddi_prop_remove_all(dip);
1903 1908
1904 1909 return (DDI_SUCCESS);
1905 1910 }
1906 1911
1907 1912 static void
1908 1913 mptsas_list_add(mptsas_t *mpt)
1909 1914 {
1910 1915 rw_enter(&mptsas_global_rwlock, RW_WRITER);
1911 1916
1912 1917 if (mptsas_head == NULL) {
1913 1918 mptsas_head = mpt;
1914 1919 } else {
1915 1920 mptsas_tail->m_next = mpt;
1916 1921 }
1917 1922 mptsas_tail = mpt;
1918 1923 rw_exit(&mptsas_global_rwlock);
1919 1924 }
1920 1925
1921 1926 static void
1922 1927 mptsas_list_del(mptsas_t *mpt)
1923 1928 {
1924 1929 mptsas_t *m;
1925 1930 /*
1926 1931 * Remove device instance from the global linked list
1927 1932 */
1928 1933 rw_enter(&mptsas_global_rwlock, RW_WRITER);
1929 1934 if (mptsas_head == mpt) {
1930 1935 m = mptsas_head = mpt->m_next;
1931 1936 } else {
1932 1937 for (m = mptsas_head; m != NULL; m = m->m_next) {
1933 1938 if (m->m_next == mpt) {
1934 1939 m->m_next = mpt->m_next;
1935 1940 break;
1936 1941 }
1937 1942 }
1938 1943 if (m == NULL) {
1939 1944 mptsas_log(mpt, CE_PANIC, "Not in softc list!");
1940 1945 }
1941 1946 }
1942 1947
1943 1948 if (mptsas_tail == mpt) {
1944 1949 mptsas_tail = m;
1945 1950 }
1946 1951 rw_exit(&mptsas_global_rwlock);
1947 1952 }
1948 1953
1949 1954 static int
1950 1955 mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size)
1951 1956 {
1952 1957 ddi_dma_attr_t task_dma_attrs;
1953 1958
1954 1959 task_dma_attrs = mpt->m_msg_dma_attr;
1955 1960 task_dma_attrs.dma_attr_sgllen = 1;
1956 1961 task_dma_attrs.dma_attr_granular = (uint32_t)(alloc_size);
1957 1962
1958 1963 /* allocate Task Management ddi_dma resources */
1959 1964 if (mptsas_dma_addr_create(mpt, task_dma_attrs,
1960 1965 &mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl, &mpt->m_hshk_memp,
1961 1966 alloc_size, NULL) == FALSE) {
1962 1967 return (DDI_FAILURE);
1963 1968 }
1964 1969 mpt->m_hshk_dma_size = alloc_size;
1965 1970
1966 1971 return (DDI_SUCCESS);
1967 1972 }
1968 1973
1969 1974 static void
1970 1975 mptsas_free_handshake_msg(mptsas_t *mpt)
1971 1976 {
1972 1977 mptsas_dma_addr_destroy(&mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl);
1973 1978 mpt->m_hshk_dma_size = 0;
1974 1979 }
1975 1980
1976 1981 static int
1977 1982 mptsas_hba_setup(mptsas_t *mpt)
1978 1983 {
1979 1984 scsi_hba_tran_t *hba_tran;
1980 1985 int tran_flags;
1981 1986
1982 1987 /* Allocate a transport structure */
1983 1988 hba_tran = mpt->m_tran = scsi_hba_tran_alloc(mpt->m_dip,
1984 1989 SCSI_HBA_CANSLEEP);
1985 1990 ASSERT(mpt->m_tran != NULL);
1986 1991
1987 1992 hba_tran->tran_hba_private = mpt;
1988 1993 hba_tran->tran_tgt_private = NULL;
1989 1994
1990 1995 hba_tran->tran_tgt_init = mptsas_scsi_tgt_init;
1991 1996 hba_tran->tran_tgt_free = mptsas_scsi_tgt_free;
1992 1997
1993 1998 hba_tran->tran_start = mptsas_scsi_start;
1994 1999 hba_tran->tran_reset = mptsas_scsi_reset;
1995 2000 hba_tran->tran_abort = mptsas_scsi_abort;
1996 2001 hba_tran->tran_getcap = mptsas_scsi_getcap;
1997 2002 hba_tran->tran_setcap = mptsas_scsi_setcap;
1998 2003 hba_tran->tran_init_pkt = mptsas_scsi_init_pkt;
1999 2004 hba_tran->tran_destroy_pkt = mptsas_scsi_destroy_pkt;
2000 2005
2001 2006 hba_tran->tran_dmafree = mptsas_scsi_dmafree;
2002 2007 hba_tran->tran_sync_pkt = mptsas_scsi_sync_pkt;
2003 2008 hba_tran->tran_reset_notify = mptsas_scsi_reset_notify;
2004 2009
2005 2010 hba_tran->tran_get_bus_addr = mptsas_get_bus_addr;
2006 2011 hba_tran->tran_get_name = mptsas_get_name;
2007 2012
2008 2013 hba_tran->tran_quiesce = mptsas_scsi_quiesce;
2009 2014 hba_tran->tran_unquiesce = mptsas_scsi_unquiesce;
2010 2015 hba_tran->tran_bus_reset = NULL;
2011 2016
2012 2017 hba_tran->tran_add_eventcall = NULL;
2013 2018 hba_tran->tran_get_eventcookie = NULL;
2014 2019 hba_tran->tran_post_event = NULL;
2015 2020 hba_tran->tran_remove_eventcall = NULL;
2016 2021
2017 2022 hba_tran->tran_bus_config = mptsas_bus_config;
2018 2023
2019 2024 hba_tran->tran_interconnect_type = INTERCONNECT_SAS;
2020 2025
2021 2026 /*
2022 2027 * All children of the HBA are iports. We need tran was cloned.
2023 2028 * So we pass the flags to SCSA. SCSI_HBA_TRAN_CLONE will be
2024 2029 * inherited to iport's tran vector.
2025 2030 */
2026 2031 tran_flags = (SCSI_HBA_HBA | SCSI_HBA_TRAN_CLONE);
2027 2032
2028 2033 if (scsi_hba_attach_setup(mpt->m_dip, &mpt->m_msg_dma_attr,
2029 2034 hba_tran, tran_flags) != DDI_SUCCESS) {
2030 2035 mptsas_log(mpt, CE_WARN, "hba attach setup failed");
2031 2036 scsi_hba_tran_free(hba_tran);
2032 2037 mpt->m_tran = NULL;
2033 2038 return (FALSE);
2034 2039 }
2035 2040 return (TRUE);
2036 2041 }
2037 2042
2038 2043 static void
2039 2044 mptsas_hba_teardown(mptsas_t *mpt)
2040 2045 {
2041 2046 (void) scsi_hba_detach(mpt->m_dip);
2042 2047 if (mpt->m_tran != NULL) {
2043 2048 scsi_hba_tran_free(mpt->m_tran);
2044 2049 mpt->m_tran = NULL;
2045 2050 }
2046 2051 }
2047 2052
2048 2053 static void
2049 2054 mptsas_iport_register(mptsas_t *mpt)
2050 2055 {
2051 2056 int i, j;
2052 2057 mptsas_phymask_t mask = 0x0;
2053 2058 /*
2054 2059 * initial value of mask is 0
2055 2060 */
2056 2061 mutex_enter(&mpt->m_mutex);
2057 2062 for (i = 0; i < mpt->m_num_phys; i++) {
2058 2063 mptsas_phymask_t phy_mask = 0x0;
2059 2064 char phy_mask_name[MPTSAS_MAX_PHYS];
2060 2065 uint8_t current_port;
2061 2066
2062 2067 if (mpt->m_phy_info[i].attached_devhdl == 0)
2063 2068 continue;
2064 2069
2065 2070 bzero(phy_mask_name, sizeof (phy_mask_name));
2066 2071
2067 2072 current_port = mpt->m_phy_info[i].port_num;
2068 2073
2069 2074 if ((mask & (1 << i)) != 0)
2070 2075 continue;
2071 2076
2072 2077 for (j = 0; j < mpt->m_num_phys; j++) {
2073 2078 if (mpt->m_phy_info[j].attached_devhdl &&
2074 2079 (mpt->m_phy_info[j].port_num == current_port)) {
2075 2080 phy_mask |= (1 << j);
2076 2081 }
2077 2082 }
2078 2083 mask = mask | phy_mask;
2079 2084
2080 2085 for (j = 0; j < mpt->m_num_phys; j++) {
2081 2086 if ((phy_mask >> j) & 0x01) {
2082 2087 mpt->m_phy_info[j].phy_mask = phy_mask;
2083 2088 }
2084 2089 }
2085 2090
2086 2091 (void) sprintf(phy_mask_name, "%x", phy_mask);
2087 2092
2088 2093 mutex_exit(&mpt->m_mutex);
2089 2094 /*
2090 2095 * register a iport
2091 2096 */
2092 2097 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name);
2093 2098 mutex_enter(&mpt->m_mutex);
2094 2099 }
2095 2100 mutex_exit(&mpt->m_mutex);
2096 2101 /*
2097 2102 * register a virtual port for RAID volume always
2098 2103 */
2099 2104 (void) scsi_hba_iport_register(mpt->m_dip, "v0");
2100 2105
2101 2106 }
2102 2107
2103 2108 static int
2104 2109 mptsas_smp_setup(mptsas_t *mpt)
2105 2110 {
2106 2111 mpt->m_smptran = smp_hba_tran_alloc(mpt->m_dip);
2107 2112 ASSERT(mpt->m_smptran != NULL);
2108 2113 mpt->m_smptran->smp_tran_hba_private = mpt;
2109 2114 mpt->m_smptran->smp_tran_start = mptsas_smp_start;
2110 2115 if (smp_hba_attach_setup(mpt->m_dip, mpt->m_smptran) != DDI_SUCCESS) {
2111 2116 mptsas_log(mpt, CE_WARN, "smp attach setup failed");
2112 2117 smp_hba_tran_free(mpt->m_smptran);
2113 2118 mpt->m_smptran = NULL;
2114 2119 return (FALSE);
2115 2120 }
2116 2121 /*
2117 2122 * Initialize smp hash table
2118 2123 */
2119 2124 mptsas_hash_init(&mpt->m_active->m_smptbl);
2120 2125 mpt->m_smp_devhdl = 0xFFFF;
2121 2126
2122 2127 return (TRUE);
2123 2128 }
2124 2129
2125 2130 static void
2126 2131 mptsas_smp_teardown(mptsas_t *mpt)
2127 2132 {
2128 2133 (void) smp_hba_detach(mpt->m_dip);
2129 2134 if (mpt->m_smptran != NULL) {
2130 2135 smp_hba_tran_free(mpt->m_smptran);
2131 2136 mpt->m_smptran = NULL;
2132 2137 }
2133 2138 mpt->m_smp_devhdl = 0;
2134 2139 }
2135 2140
2136 2141 static int
2137 2142 mptsas_cache_create(mptsas_t *mpt)
2138 2143 {
2139 2144 int instance = mpt->m_instance;
2140 2145 char buf[64];
2141 2146
2142 2147 /*
2143 2148 * create kmem cache for packets
2144 2149 */
2145 2150 (void) sprintf(buf, "mptsas%d_cache", instance);
2146 2151 mpt->m_kmem_cache = kmem_cache_create(buf,
2147 2152 sizeof (struct mptsas_cmd) + scsi_pkt_size(), 8,
2148 2153 mptsas_kmem_cache_constructor, mptsas_kmem_cache_destructor,
2149 2154 NULL, (void *)mpt, NULL, 0);
2150 2155
2151 2156 if (mpt->m_kmem_cache == NULL) {
2152 2157 mptsas_log(mpt, CE_WARN, "creating kmem cache failed");
2153 2158 return (FALSE);
2154 2159 }
2155 2160
2156 2161 /*
2157 2162 * create kmem cache for extra SGL frames if SGL cannot
2158 2163 * be accomodated into main request frame.
2159 2164 */
2160 2165 (void) sprintf(buf, "mptsas%d_cache_frames", instance);
2161 2166 mpt->m_cache_frames = kmem_cache_create(buf,
2162 2167 sizeof (mptsas_cache_frames_t), 8,
2163 2168 mptsas_cache_frames_constructor, mptsas_cache_frames_destructor,
2164 2169 NULL, (void *)mpt, NULL, 0);
2165 2170
2166 2171 if (mpt->m_cache_frames == NULL) {
2167 2172 mptsas_log(mpt, CE_WARN, "creating cache for frames failed");
2168 2173 return (FALSE);
2169 2174 }
2170 2175
2171 2176 return (TRUE);
2172 2177 }
2173 2178
2174 2179 static void
2175 2180 mptsas_cache_destroy(mptsas_t *mpt)
2176 2181 {
2177 2182 /* deallocate in reverse order */
2178 2183 if (mpt->m_cache_frames) {
2179 2184 kmem_cache_destroy(mpt->m_cache_frames);
2180 2185 mpt->m_cache_frames = NULL;
2181 2186 }
2182 2187 if (mpt->m_kmem_cache) {
2183 2188 kmem_cache_destroy(mpt->m_kmem_cache);
2184 2189 mpt->m_kmem_cache = NULL;
2185 2190 }
2186 2191 }
2187 2192
2188 2193 static int
2189 2194 mptsas_power(dev_info_t *dip, int component, int level)
2190 2195 {
2191 2196 #ifndef __lock_lint
2192 2197 _NOTE(ARGUNUSED(component))
2193 2198 #endif
2194 2199 mptsas_t *mpt;
2195 2200 int rval = DDI_SUCCESS;
2196 2201 int polls = 0;
2197 2202 uint32_t ioc_status;
2198 2203
2199 2204 if (scsi_hba_iport_unit_address(dip) != 0)
2200 2205 return (DDI_SUCCESS);
2201 2206
2202 2207 mpt = ddi_get_soft_state(mptsas_state, ddi_get_instance(dip));
2203 2208 if (mpt == NULL) {
2204 2209 return (DDI_FAILURE);
2205 2210 }
2206 2211
2207 2212 mutex_enter(&mpt->m_mutex);
2208 2213
2209 2214 /*
2210 2215 * If the device is busy, don't lower its power level
2211 2216 */
2212 2217 if (mpt->m_busy && (mpt->m_power_level > level)) {
2213 2218 mutex_exit(&mpt->m_mutex);
2214 2219 return (DDI_FAILURE);
2215 2220 }
2216 2221 switch (level) {
2217 2222 case PM_LEVEL_D0:
2218 2223 NDBG11(("mptsas%d: turning power ON.", mpt->m_instance));
2219 2224 MPTSAS_POWER_ON(mpt);
2220 2225 /*
2221 2226 * Wait up to 30 seconds for IOC to come out of reset.
2222 2227 */
2223 2228 while (((ioc_status = ddi_get32(mpt->m_datap,
2224 2229 &mpt->m_reg->Doorbell)) &
2225 2230 MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
2226 2231 if (polls++ > 3000) {
2227 2232 break;
2228 2233 }
2229 2234 delay(drv_usectohz(10000));
2230 2235 }
2231 2236 /*
2232 2237 * If IOC is not in operational state, try to hard reset it.
2233 2238 */
2234 2239 if ((ioc_status & MPI2_IOC_STATE_MASK) !=
2235 2240 MPI2_IOC_STATE_OPERATIONAL) {
2236 2241 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
2237 2242 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) {
2238 2243 mptsas_log(mpt, CE_WARN,
2239 2244 "mptsas_power: hard reset failed");
2240 2245 mutex_exit(&mpt->m_mutex);
2241 2246 return (DDI_FAILURE);
2242 2247 }
2243 2248 }
2244 2249 mutex_enter(&mpt->m_intr_mutex);
2245 2250 mpt->m_power_level = PM_LEVEL_D0;
2246 2251 mutex_exit(&mpt->m_intr_mutex);
2247 2252 break;
2248 2253 case PM_LEVEL_D3:
2249 2254 NDBG11(("mptsas%d: turning power OFF.", mpt->m_instance));
2250 2255 MPTSAS_POWER_OFF(mpt);
2251 2256 break;
2252 2257 default:
2253 2258 mptsas_log(mpt, CE_WARN, "mptsas%d: unknown power level <%x>.",
2254 2259 mpt->m_instance, level);
2255 2260 rval = DDI_FAILURE;
2256 2261 break;
2257 2262 }
2258 2263 mutex_exit(&mpt->m_mutex);
2259 2264 return (rval);
2260 2265 }
2261 2266
2262 2267 /*
2263 2268 * Initialize configuration space and figure out which
2264 2269 * chip and revison of the chip the mpt driver is using.
2265 2270 */
2266 2271 static int
2267 2272 mptsas_config_space_init(mptsas_t *mpt)
2268 2273 {
2269 2274 NDBG0(("mptsas_config_space_init"));
2270 2275
2271 2276 if (mpt->m_config_handle != NULL)
2272 2277 return (TRUE);
2273 2278
2274 2279 if (pci_config_setup(mpt->m_dip,
2275 2280 &mpt->m_config_handle) != DDI_SUCCESS) {
2276 2281 mptsas_log(mpt, CE_WARN, "cannot map configuration space.");
2277 2282 return (FALSE);
2278 2283 }
2279 2284
2280 2285 /*
2281 2286 * This is a workaround for a XMITS ASIC bug which does not
2282 2287 * drive the CBE upper bits.
2283 2288 */
2284 2289 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) &
2285 2290 PCI_STAT_PERROR) {
2286 2291 pci_config_put16(mpt->m_config_handle, PCI_CONF_STAT,
2287 2292 PCI_STAT_PERROR);
2288 2293 }
2289 2294
2290 2295 mptsas_setup_cmd_reg(mpt);
2291 2296
2292 2297 /*
2293 2298 * Get the chip device id:
2294 2299 */
2295 2300 mpt->m_devid = pci_config_get16(mpt->m_config_handle, PCI_CONF_DEVID);
2296 2301
2297 2302 /*
2298 2303 * Save the revision.
2299 2304 */
2300 2305 mpt->m_revid = pci_config_get8(mpt->m_config_handle, PCI_CONF_REVID);
2301 2306
2302 2307 /*
2303 2308 * Save the SubSystem Vendor and Device IDs
2304 2309 */
2305 2310 mpt->m_svid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBVENID);
2306 2311 mpt->m_ssid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBSYSID);
2307 2312
2308 2313 /*
2309 2314 * Set the latency timer to 0x40 as specified by the upa -> pci
2310 2315 * bridge chip design team. This may be done by the sparc pci
2311 2316 * bus nexus driver, but the driver should make sure the latency
2312 2317 * timer is correct for performance reasons.
2313 2318 */
2314 2319 pci_config_put8(mpt->m_config_handle, PCI_CONF_LATENCY_TIMER,
2315 2320 MPTSAS_LATENCY_TIMER);
2316 2321
2317 2322 (void) mptsas_get_pci_cap(mpt);
2318 2323 return (TRUE);
2319 2324 }
2320 2325
2321 2326 static void
2322 2327 mptsas_config_space_fini(mptsas_t *mpt)
2323 2328 {
2324 2329 if (mpt->m_config_handle != NULL) {
2325 2330 mptsas_disable_bus_master(mpt);
2326 2331 pci_config_teardown(&mpt->m_config_handle);
2327 2332 mpt->m_config_handle = NULL;
2328 2333 }
2329 2334 }
2330 2335
2331 2336 static void
2332 2337 mptsas_setup_cmd_reg(mptsas_t *mpt)
2333 2338 {
2334 2339 ushort_t cmdreg;
2335 2340
2336 2341 /*
2337 2342 * Set the command register to the needed values.
2338 2343 */
2339 2344 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM);
2340 2345 cmdreg |= (PCI_COMM_ME | PCI_COMM_SERR_ENABLE |
2341 2346 PCI_COMM_PARITY_DETECT | PCI_COMM_MAE);
2342 2347 cmdreg &= ~PCI_COMM_IO;
2343 2348 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg);
2344 2349 }
2345 2350
2346 2351 static void
2347 2352 mptsas_disable_bus_master(mptsas_t *mpt)
2348 2353 {
2349 2354 ushort_t cmdreg;
2350 2355
2351 2356 /*
2352 2357 * Clear the master enable bit in the PCI command register.
2353 2358 * This prevents any bus mastering activity like DMA.
2354 2359 */
2355 2360 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM);
2356 2361 cmdreg &= ~PCI_COMM_ME;
2357 2362 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg);
2358 2363 }
2359 2364
2360 2365 int
2361 2366 mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep)
2362 2367 {
2363 2368 ddi_dma_attr_t attrs;
2364 2369
2365 2370 attrs = mpt->m_io_dma_attr;
2366 2371 attrs.dma_attr_sgllen = 1;
2367 2372
2368 2373 ASSERT(dma_statep != NULL);
2369 2374
2370 2375 if (mptsas_dma_addr_create(mpt, attrs, &dma_statep->handle,
2371 2376 &dma_statep->accessp, &dma_statep->memp, dma_statep->size,
2372 2377 &dma_statep->cookie) == FALSE) {
2373 2378 return (DDI_FAILURE);
2374 2379 }
2375 2380
2376 2381 return (DDI_SUCCESS);
2377 2382 }
2378 2383
2379 2384 void
2380 2385 mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep)
2381 2386 {
2382 2387 ASSERT(dma_statep != NULL);
2383 2388 mptsas_dma_addr_destroy(&dma_statep->handle, &dma_statep->accessp);
2384 2389 dma_statep->size = 0;
2385 2390 }
2386 2391
2387 2392 int
2388 2393 mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)())
2389 2394 {
2390 2395 ddi_dma_attr_t attrs;
2391 2396 ddi_dma_handle_t dma_handle;
2392 2397 caddr_t memp;
2393 2398 ddi_acc_handle_t accessp;
2394 2399 int rval;
2395 2400
2396 2401 ASSERT(mutex_owned(&mpt->m_mutex));
2397 2402
2398 2403 attrs = mpt->m_msg_dma_attr;
2399 2404 attrs.dma_attr_sgllen = 1;
2400 2405 attrs.dma_attr_granular = size;
2401 2406
2402 2407 if (mptsas_dma_addr_create(mpt, attrs, &dma_handle,
2403 2408 &accessp, &memp, size, NULL) == FALSE) {
2404 2409 return (DDI_FAILURE);
2405 2410 }
2406 2411
2407 2412 rval = (*callback) (mpt, memp, var, accessp);
2408 2413
2409 2414 if ((mptsas_check_dma_handle(dma_handle) != DDI_SUCCESS) ||
2410 2415 (mptsas_check_acc_handle(accessp) != DDI_SUCCESS)) {
2411 2416 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
2412 2417 rval = DDI_FAILURE;
2413 2418 }
2414 2419
2415 2420 mptsas_dma_addr_destroy(&dma_handle, &accessp);
2416 2421 return (rval);
2417 2422
2418 2423 }
2419 2424
2420 2425 static int
2421 2426 mptsas_alloc_request_frames(mptsas_t *mpt)
2422 2427 {
2423 2428 ddi_dma_attr_t frame_dma_attrs;
2424 2429 caddr_t memp;
2425 2430 ddi_dma_cookie_t cookie;
2426 2431 size_t mem_size;
2427 2432
2428 2433 /*
2429 2434 * re-alloc when it has already alloced
2430 2435 */
2431 2436 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl,
2432 2437 &mpt->m_acc_req_frame_hdl);
2433 2438
2434 2439 /*
2435 2440 * The size of the request frame pool is:
2436 2441 * Number of Request Frames * Request Frame Size
2437 2442 */
2438 2443 mem_size = mpt->m_max_requests * mpt->m_req_frame_size;
2439 2444
2440 2445 /*
2441 2446 * set the DMA attributes. System Request Message Frames must be
2442 2447 * aligned on a 16-byte boundry.
2443 2448 */
2444 2449 frame_dma_attrs = mpt->m_msg_dma_attr;
2445 2450 frame_dma_attrs.dma_attr_align = 16;
2446 2451 frame_dma_attrs.dma_attr_sgllen = 1;
2447 2452
2448 2453 /*
2449 2454 * allocate the request frame pool.
2450 2455 */
2451 2456 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2452 2457 &mpt->m_dma_req_frame_hdl, &mpt->m_acc_req_frame_hdl, &memp,
2453 2458 mem_size, &cookie) == FALSE) {
2454 2459 return (DDI_FAILURE);
2455 2460 }
2456 2461
2457 2462 /*
2458 2463 * Store the request frame memory address. This chip uses this
2459 2464 * address to dma to and from the driver's frame. The second
2460 2465 * address is the address mpt uses to fill in the frame.
2461 2466 */
2462 2467 mpt->m_req_frame_dma_addr = cookie.dmac_laddress;
2463 2468 mpt->m_req_frame = memp;
2464 2469
2465 2470 /*
2466 2471 * Clear the request frame pool.
2467 2472 */
2468 2473 bzero(mpt->m_req_frame, mem_size);
2469 2474
2470 2475 return (DDI_SUCCESS);
2471 2476 }
2472 2477
2473 2478 static int
2474 2479 mptsas_alloc_reply_frames(mptsas_t *mpt)
2475 2480 {
2476 2481 ddi_dma_attr_t frame_dma_attrs;
2477 2482 caddr_t memp;
2478 2483 ddi_dma_cookie_t cookie;
2479 2484 size_t mem_size;
2480 2485
2481 2486 /*
2482 2487 * re-alloc when it has already alloced
2483 2488 */
2484 2489 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl,
2485 2490 &mpt->m_acc_reply_frame_hdl);
2486 2491
2487 2492 /*
2488 2493 * The size of the reply frame pool is:
2489 2494 * Number of Reply Frames * Reply Frame Size
2490 2495 */
2491 2496 mem_size = mpt->m_max_replies * mpt->m_reply_frame_size;
2492 2497
2493 2498 /*
2494 2499 * set the DMA attributes. System Reply Message Frames must be
2495 2500 * aligned on a 4-byte boundry. This is the default.
2496 2501 */
2497 2502 frame_dma_attrs = mpt->m_msg_dma_attr;
2498 2503 frame_dma_attrs.dma_attr_sgllen = 1;
2499 2504
2500 2505 /*
2501 2506 * allocate the reply frame pool
2502 2507 */
2503 2508 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2504 2509 &mpt->m_dma_reply_frame_hdl, &mpt->m_acc_reply_frame_hdl, &memp,
2505 2510 mem_size, &cookie) == FALSE) {
2506 2511 return (DDI_FAILURE);
2507 2512 }
2508 2513
2509 2514 /*
2510 2515 * Store the reply frame memory address. This chip uses this
2511 2516 * address to dma to and from the driver's frame. The second
2512 2517 * address is the address mpt uses to process the frame.
2513 2518 */
2514 2519 mpt->m_reply_frame_dma_addr = cookie.dmac_laddress;
2515 2520 mpt->m_reply_frame = memp;
2516 2521
2517 2522 /*
2518 2523 * Clear the reply frame pool.
2519 2524 */
2520 2525 bzero(mpt->m_reply_frame, mem_size);
2521 2526
2522 2527 return (DDI_SUCCESS);
2523 2528 }
2524 2529
2525 2530 static int
2526 2531 mptsas_alloc_free_queue(mptsas_t *mpt)
2527 2532 {
2528 2533 ddi_dma_attr_t frame_dma_attrs;
2529 2534 caddr_t memp;
2530 2535 ddi_dma_cookie_t cookie;
2531 2536 size_t mem_size;
2532 2537
2533 2538 /*
2534 2539 * re-alloc when it has already alloced
2535 2540 */
2536 2541 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl,
2537 2542 &mpt->m_acc_free_queue_hdl);
2538 2543
2539 2544 /*
2540 2545 * The reply free queue size is:
2541 2546 * Reply Free Queue Depth * 4
2542 2547 * The "4" is the size of one 32 bit address (low part of 64-bit
2543 2548 * address)
2544 2549 */
2545 2550 mem_size = mpt->m_free_queue_depth * 4;
2546 2551
2547 2552 /*
2548 2553 * set the DMA attributes The Reply Free Queue must be aligned on a
2549 2554 * 16-byte boundry.
2550 2555 */
2551 2556 frame_dma_attrs = mpt->m_msg_dma_attr;
2552 2557 frame_dma_attrs.dma_attr_align = 16;
2553 2558 frame_dma_attrs.dma_attr_sgllen = 1;
2554 2559
2555 2560 /*
2556 2561 * allocate the reply free queue
2557 2562 */
2558 2563 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2559 2564 &mpt->m_dma_free_queue_hdl, &mpt->m_acc_free_queue_hdl, &memp,
2560 2565 mem_size, &cookie) == FALSE) {
2561 2566 return (DDI_FAILURE);
2562 2567 }
2563 2568
2564 2569 /*
2565 2570 * Store the reply free queue memory address. This chip uses this
2566 2571 * address to read from the reply free queue. The second address
2567 2572 * is the address mpt uses to manage the queue.
2568 2573 */
2569 2574 mpt->m_free_queue_dma_addr = cookie.dmac_laddress;
2570 2575 mpt->m_free_queue = memp;
2571 2576
2572 2577 /*
2573 2578 * Clear the reply free queue memory.
2574 2579 */
2575 2580 bzero(mpt->m_free_queue, mem_size);
2576 2581
2577 2582 return (DDI_SUCCESS);
2578 2583 }
2579 2584
2580 2585 static int
2581 2586 mptsas_alloc_post_queue(mptsas_t *mpt)
2582 2587 {
2583 2588 ddi_dma_attr_t frame_dma_attrs;
2584 2589 caddr_t memp;
2585 2590 ddi_dma_cookie_t cookie;
2586 2591 size_t mem_size;
2587 2592
2588 2593 /*
2589 2594 * re-alloc when it has already alloced
2590 2595 */
2591 2596 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl,
2592 2597 &mpt->m_acc_post_queue_hdl);
2593 2598
2594 2599 /*
2595 2600 * The reply descriptor post queue size is:
2596 2601 * Reply Descriptor Post Queue Depth * 8
2597 2602 * The "8" is the size of each descriptor (8 bytes or 64 bits).
2598 2603 */
2599 2604 mem_size = mpt->m_post_queue_depth * 8;
2600 2605
2601 2606 /*
2602 2607 * set the DMA attributes. The Reply Descriptor Post Queue must be
2603 2608 * aligned on a 16-byte boundry.
2604 2609 */
2605 2610 frame_dma_attrs = mpt->m_msg_dma_attr;
2606 2611 frame_dma_attrs.dma_attr_align = 16;
2607 2612 frame_dma_attrs.dma_attr_sgllen = 1;
2608 2613
2609 2614 /*
2610 2615 * allocate the reply post queue
2611 2616 */
2612 2617 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2613 2618 &mpt->m_dma_post_queue_hdl, &mpt->m_acc_post_queue_hdl, &memp,
2614 2619 mem_size, &cookie) == FALSE) {
2615 2620 return (DDI_FAILURE);
2616 2621 }
2617 2622
2618 2623 /*
2619 2624 * Store the reply descriptor post queue memory address. This chip
2620 2625 * uses this address to write to the reply descriptor post queue. The
2621 2626 * second address is the address mpt uses to manage the queue.
2622 2627 */
2623 2628 mpt->m_post_queue_dma_addr = cookie.dmac_laddress;
2624 2629 mpt->m_post_queue = memp;
2625 2630
2626 2631 /*
2627 2632 * Clear the reply post queue memory.
2628 2633 */
2629 2634 bzero(mpt->m_post_queue, mem_size);
2630 2635
2631 2636 return (DDI_SUCCESS);
2632 2637 }
2633 2638
2634 2639 static void
2635 2640 mptsas_alloc_reply_args(mptsas_t *mpt)
2636 2641 {
2637 2642 if (mpt->m_replyh_args != NULL) {
2638 2643 kmem_free(mpt->m_replyh_args, sizeof (m_replyh_arg_t)
2639 2644 * mpt->m_max_replies);
2640 2645 mpt->m_replyh_args = NULL;
2641 2646 }
2642 2647 mpt->m_replyh_args = kmem_zalloc(sizeof (m_replyh_arg_t) *
2643 2648 mpt->m_max_replies, KM_SLEEP);
2644 2649 }
2645 2650
2646 2651 static int
2647 2652 mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd)
2648 2653 {
2649 2654 mptsas_cache_frames_t *frames = NULL;
2650 2655 if (cmd->cmd_extra_frames == NULL) {
2651 2656 frames = kmem_cache_alloc(mpt->m_cache_frames, KM_NOSLEEP);
2652 2657 if (frames == NULL) {
2653 2658 return (DDI_FAILURE);
2654 2659 }
2655 2660 cmd->cmd_extra_frames = frames;
2656 2661 }
2657 2662 return (DDI_SUCCESS);
2658 2663 }
2659 2664
2660 2665 static void
2661 2666 mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd)
2662 2667 {
2663 2668 if (cmd->cmd_extra_frames) {
2664 2669 kmem_cache_free(mpt->m_cache_frames,
2665 2670 (void *)cmd->cmd_extra_frames);
2666 2671 cmd->cmd_extra_frames = NULL;
2667 2672 }
2668 2673 }
2669 2674
2670 2675 static void
2671 2676 mptsas_cfg_fini(mptsas_t *mpt)
2672 2677 {
2673 2678 NDBG0(("mptsas_cfg_fini"));
2674 2679 ddi_regs_map_free(&mpt->m_datap);
2675 2680 }
2676 2681
2677 2682 static void
2678 2683 mptsas_hba_fini(mptsas_t *mpt)
2679 2684 {
2680 2685 NDBG0(("mptsas_hba_fini"));
2681 2686
2682 2687 /*
2683 2688 * Free up any allocated memory
2684 2689 */
2685 2690 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl,
2686 2691 &mpt->m_acc_req_frame_hdl);
2687 2692
2688 2693 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl,
2689 2694 &mpt->m_acc_reply_frame_hdl);
2690 2695
2691 2696 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl,
2692 2697 &mpt->m_acc_free_queue_hdl);
2693 2698
2694 2699 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl,
2695 2700 &mpt->m_acc_post_queue_hdl);
2696 2701
2697 2702 if (mpt->m_replyh_args != NULL) {
2698 2703 kmem_free(mpt->m_replyh_args, sizeof (m_replyh_arg_t)
2699 2704 * mpt->m_max_replies);
2700 2705 }
2701 2706 }
2702 2707
2703 2708 static int
2704 2709 mptsas_name_child(dev_info_t *lun_dip, char *name, int len)
2705 2710 {
2706 2711 int lun = 0;
2707 2712 char *sas_wwn = NULL;
2708 2713 int phynum = -1;
2709 2714 int reallen = 0;
2710 2715
2711 2716 /* Get the target num */
2712 2717 lun = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, DDI_PROP_DONTPASS,
2713 2718 LUN_PROP, 0);
2714 2719
2715 2720 if ((phynum = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip,
2716 2721 DDI_PROP_DONTPASS, "sata-phy", -1)) != -1) {
2717 2722 /*
2718 2723 * Stick in the address of form "pPHY,LUN"
2719 2724 */
2720 2725 reallen = snprintf(name, len, "p%x,%x", phynum, lun);
2721 2726 } else if (ddi_prop_lookup_string(DDI_DEV_T_ANY, lun_dip,
2722 2727 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &sas_wwn)
2723 2728 == DDI_PROP_SUCCESS) {
2724 2729 /*
2725 2730 * Stick in the address of the form "wWWN,LUN"
2726 2731 */
2727 2732 reallen = snprintf(name, len, "%s,%x", sas_wwn, lun);
2728 2733 ddi_prop_free(sas_wwn);
2729 2734 } else {
2730 2735 return (DDI_FAILURE);
2731 2736 }
2732 2737
2733 2738 ASSERT(reallen < len);
2734 2739 if (reallen >= len) {
2735 2740 mptsas_log(0, CE_WARN, "!mptsas_get_name: name parameter "
2736 2741 "length too small, it needs to be %d bytes", reallen + 1);
2737 2742 }
2738 2743 return (DDI_SUCCESS);
2739 2744 }
2740 2745
2741 2746 /*
2742 2747 * tran_tgt_init(9E) - target device instance initialization
2743 2748 */
2744 2749 static int
2745 2750 mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
2746 2751 scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
2747 2752 {
2748 2753 #ifndef __lock_lint
2749 2754 _NOTE(ARGUNUSED(hba_tran))
2750 2755 #endif
2751 2756
2752 2757 /*
2753 2758 * At this point, the scsi_device structure already exists
2754 2759 * and has been initialized.
2755 2760 *
2756 2761 * Use this function to allocate target-private data structures,
2757 2762 * if needed by this HBA. Add revised flow-control and queue
2758 2763 * properties for child here, if desired and if you can tell they
2759 2764 * support tagged queueing by now.
2760 2765 */
2761 2766 mptsas_t *mpt;
2762 2767 int lun = sd->sd_address.a_lun;
2763 2768 mdi_pathinfo_t *pip = NULL;
2764 2769 mptsas_tgt_private_t *tgt_private = NULL;
2765 2770 mptsas_target_t *ptgt = NULL;
2766 2771 char *psas_wwn = NULL;
2767 2772 int phymask = 0;
2768 2773 uint64_t sas_wwn = 0;
2769 2774 mpt = SDEV2MPT(sd);
2770 2775
2771 2776 ASSERT(scsi_hba_iport_unit_address(hba_dip) != 0);
2772 2777
2773 2778 NDBG0(("mptsas_scsi_tgt_init: hbadip=0x%p tgtdip=0x%p lun=%d",
2774 2779 (void *)hba_dip, (void *)tgt_dip, lun));
2775 2780
2776 2781 if (ndi_dev_is_persistent_node(tgt_dip) == 0) {
2777 2782 (void) ndi_merge_node(tgt_dip, mptsas_name_child);
2778 2783 ddi_set_name_addr(tgt_dip, NULL);
2779 2784 return (DDI_FAILURE);
2780 2785 }
2781 2786 /*
2782 2787 * phymask is 0 means the virtual port for RAID
2783 2788 */
2784 2789 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, hba_dip, 0,
2785 2790 "phymask", 0);
2786 2791 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) {
2787 2792 if ((pip = (void *)(sd->sd_private)) == NULL) {
2788 2793 /*
2789 2794 * Very bad news if this occurs. Somehow scsi_vhci has
2790 2795 * lost the pathinfo node for this target.
2791 2796 */
2792 2797 return (DDI_NOT_WELL_FORMED);
2793 2798 }
2794 2799
2795 2800 if (mdi_prop_lookup_int(pip, LUN_PROP, &lun) !=
2796 2801 DDI_PROP_SUCCESS) {
2797 2802 mptsas_log(mpt, CE_WARN, "Get lun property failed\n");
2798 2803 return (DDI_FAILURE);
2799 2804 }
2800 2805
2801 2806 if (mdi_prop_lookup_string(pip, SCSI_ADDR_PROP_TARGET_PORT,
2802 2807 &psas_wwn) == MDI_SUCCESS) {
2803 2808 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) {
2804 2809 sas_wwn = 0;
2805 2810 }
2806 2811 (void) mdi_prop_free(psas_wwn);
2807 2812 }
2808 2813 } else {
2809 2814 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tgt_dip,
2810 2815 DDI_PROP_DONTPASS, LUN_PROP, 0);
2811 2816 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, tgt_dip,
2812 2817 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &psas_wwn) ==
2813 2818 DDI_PROP_SUCCESS) {
2814 2819 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) {
2815 2820 sas_wwn = 0;
2816 2821 }
2817 2822 ddi_prop_free(psas_wwn);
2818 2823 } else {
2819 2824 sas_wwn = 0;
2820 2825 }
2821 2826 }
2822 2827 ASSERT((sas_wwn != 0) || (phymask != 0));
2823 2828 mutex_enter(&mpt->m_mutex);
2824 2829 ptgt = mptsas_hash_search(&mpt->m_active->m_tgttbl, sas_wwn, phymask);
2825 2830 mutex_exit(&mpt->m_mutex);
2826 2831 if (ptgt == NULL) {
2827 2832 mptsas_log(mpt, CE_WARN, "!tgt_init: target doesn't exist or "
2828 2833 "gone already! phymask:%x, saswwn %"PRIx64, phymask,
2829 2834 sas_wwn);
2830 2835 return (DDI_FAILURE);
2831 2836 }
2832 2837 if (hba_tran->tran_tgt_private == NULL) {
2833 2838 tgt_private = kmem_zalloc(sizeof (mptsas_tgt_private_t),
2834 2839 KM_SLEEP);
2835 2840 tgt_private->t_lun = lun;
2836 2841 tgt_private->t_private = ptgt;
2837 2842 hba_tran->tran_tgt_private = tgt_private;
2838 2843 }
2839 2844
2840 2845 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) {
2841 2846 return (DDI_SUCCESS);
2842 2847 }
2843 2848 mutex_enter(&mpt->m_mutex);
2844 2849
2845 2850 if (ptgt->m_deviceinfo &
2846 2851 (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
2847 2852 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
2848 2853 uchar_t *inq89 = NULL;
2849 2854 int inq89_len = 0x238;
2850 2855 int reallen = 0;
2851 2856 int rval = 0;
2852 2857 struct sata_id *sid = NULL;
2853 2858 char model[SATA_ID_MODEL_LEN + 1];
2854 2859 char fw[SATA_ID_FW_LEN + 1];
2855 2860 char *vid, *pid;
2856 2861 int i;
2857 2862
2858 2863 mutex_exit(&mpt->m_mutex);
2859 2864 /*
2860 2865 * According SCSI/ATA Translation -2 (SAT-2) revision 01a
2861 2866 * chapter 12.4.2 VPD page 89h includes 512 bytes ATA IDENTIFY
2862 2867 * DEVICE data or ATA IDENTIFY PACKET DEVICE data.
2863 2868 */
2864 2869 inq89 = kmem_zalloc(inq89_len, KM_SLEEP);
2865 2870 rval = mptsas_inquiry(mpt, ptgt, 0, 0x89,
2866 2871 inq89, inq89_len, &reallen, 1);
2867 2872
2868 2873 if (rval != 0) {
2869 2874 if (inq89 != NULL) {
2870 2875 kmem_free(inq89, inq89_len);
2871 2876 }
2872 2877
2873 2878 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
2874 2879 "0x89 for SATA target:%x failed!", ptgt->m_devhdl);
2875 2880 return (DDI_SUCCESS);
2876 2881 }
2877 2882 sid = (void *)(&inq89[60]);
2878 2883
2879 2884 swab(sid->ai_model, model, SATA_ID_MODEL_LEN);
2880 2885 swab(sid->ai_fw, fw, SATA_ID_FW_LEN);
2881 2886
2882 2887 model[SATA_ID_MODEL_LEN] = 0;
2883 2888 fw[SATA_ID_FW_LEN] = 0;
2884 2889
2885 2890 /*
2886 2891 * split model into into vid/pid
2887 2892 */
2888 2893 for (i = 0, pid = model; i < SATA_ID_MODEL_LEN; i++, pid++)
2889 2894 if ((*pid == ' ') || (*pid == '\t'))
2890 2895 break;
2891 2896 if (i < SATA_ID_MODEL_LEN) {
2892 2897 vid = model;
2893 2898 /*
2894 2899 * terminate vid, establish pid
2895 2900 */
2896 2901 *pid++ = 0;
2897 2902 } else {
2898 2903 /*
2899 2904 * vid will stay "ATA ", the rule is same
2900 2905 * as sata framework implementation.
2901 2906 */
2902 2907 vid = NULL;
2903 2908 /*
2904 2909 * model is all pid
2905 2910 */
2906 2911 pid = model;
2907 2912 }
2908 2913
2909 2914 /*
2910 2915 * override SCSA "inquiry-*" properties
2911 2916 */
2912 2917 if (vid)
2913 2918 (void) scsi_device_prop_update_inqstring(sd,
2914 2919 INQUIRY_VENDOR_ID, vid, strlen(vid));
2915 2920 if (pid)
2916 2921 (void) scsi_device_prop_update_inqstring(sd,
2917 2922 INQUIRY_PRODUCT_ID, pid, strlen(pid));
2918 2923 (void) scsi_device_prop_update_inqstring(sd,
2919 2924 INQUIRY_REVISION_ID, fw, strlen(fw));
2920 2925
2921 2926 if (inq89 != NULL) {
2922 2927 kmem_free(inq89, inq89_len);
2923 2928 }
2924 2929 } else {
2925 2930 mutex_exit(&mpt->m_mutex);
2926 2931 }
2927 2932
2928 2933 return (DDI_SUCCESS);
2929 2934 }
2930 2935 /*
2931 2936 * tran_tgt_free(9E) - target device instance deallocation
2932 2937 */
2933 2938 static void
2934 2939 mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
2935 2940 scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
2936 2941 {
2937 2942 #ifndef __lock_lint
2938 2943 _NOTE(ARGUNUSED(hba_dip, tgt_dip, hba_tran, sd))
2939 2944 #endif
2940 2945
2941 2946 mptsas_tgt_private_t *tgt_private = hba_tran->tran_tgt_private;
2942 2947
2943 2948 if (tgt_private != NULL) {
2944 2949 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t));
2945 2950 hba_tran->tran_tgt_private = NULL;
2946 2951 }
2947 2952 }
2948 2953
2949 2954 /*
2950 2955 * scsi_pkt handling
2951 2956 *
2952 2957 * Visible to the external world via the transport structure.
2953 2958 */
2954 2959
2955 2960 /*
2956 2961 * Notes:
2957 2962 * - transport the command to the addressed SCSI target/lun device
2958 2963 * - normal operation is to schedule the command to be transported,
2959 2964 * and return TRAN_ACCEPT if this is successful.
2960 2965 * - if NO_INTR, tran_start must poll device for command completion
2961 2966 */
2962 2967 static int
2963 2968 mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt)
2964 2969 {
2965 2970 #ifndef __lock_lint
2966 2971 _NOTE(ARGUNUSED(ap))
2967 2972 #endif
2968 2973 mptsas_t *mpt = PKT2MPT(pkt);
2969 2974 mptsas_cmd_t *cmd = PKT2CMD(pkt);
2970 2975 int rval;
2971 2976 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
2972 2977
2973 2978 NDBG1(("mptsas_scsi_start: pkt=0x%p", (void *)pkt));
2974 2979 ASSERT(ptgt);
2975 2980 if (ptgt == NULL)
2976 2981 return (TRAN_FATAL_ERROR);
2977 2982
2978 2983 /*
2979 2984 * prepare the pkt before taking mutex.
2980 2985 */
2981 2986 rval = mptsas_prepare_pkt(cmd);
2982 2987 if (rval != TRAN_ACCEPT) {
2983 2988 return (rval);
2984 2989 }
2985 2990
2986 2991 /*
2987 2992 * Send the command to target/lun, however your HBA requires it.
2988 2993 * If busy, return TRAN_BUSY; if there's some other formatting error
2989 2994 * in the packet, return TRAN_BADPKT; otherwise, fall through to the
2990 2995 * return of TRAN_ACCEPT.
2991 2996 *
2992 2997 * Remember that access to shared resources, including the mptsas_t
2993 2998 * data structure and the HBA hardware registers, must be protected
2994 2999 * with mutexes, here and everywhere.
2995 3000 *
2996 3001 * Also remember that at interrupt time, you'll get an argument
2997 3002 * to the interrupt handler which is a pointer to your mptsas_t
2998 3003 * structure; you'll have to remember which commands are outstanding
2999 3004 * and which scsi_pkt is the currently-running command so the
3000 3005 * interrupt handler can refer to the pkt to set completion
3001 3006 * status, call the target driver back through pkt_comp, etc.
3002 3007 */
3003 3008
3004 3009 mutex_enter(&ptgt->m_tgt_intr_mutex);
3005 3010 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3006 3011 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3007 3012 /*
3008 3013 * commands should be allowed to retry by
3009 3014 * returning TRAN_BUSY to stall the I/O's
3010 3015 * which come from scsi_vhci since the device/
3011 3016 * path is in unstable state now.
3012 3017 */
3013 3018 mutex_exit(&ptgt->m_tgt_intr_mutex);
3014 3019 return (TRAN_BUSY);
3015 3020 } else {
3016 3021 /*
3017 3022 * The device is offline, just fail the
3018 3023 * command by returning TRAN_FATAL_ERROR.
3019 3024 */
3020 3025 mutex_exit(&ptgt->m_tgt_intr_mutex);
3021 3026 return (TRAN_FATAL_ERROR);
3022 3027 }
3023 3028 }
3024 3029 mutex_exit(&ptgt->m_tgt_intr_mutex);
3025 3030 rval = mptsas_accept_pkt(mpt, cmd);
3026 3031
3027 3032 return (rval);
3028 3033 }
3029 3034
3030 3035 static int
3031 3036 mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd)
3032 3037 {
3033 3038 int rval = TRAN_ACCEPT;
3034 3039 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3035 3040
3036 3041 NDBG1(("mptsas_accept_pkt: cmd=0x%p", (void *)cmd));
3037 3042
3038 3043 if ((cmd->cmd_flags & CFLAG_PREPARED) == 0) {
3039 3044 rval = mptsas_prepare_pkt(cmd);
3040 3045 if (rval != TRAN_ACCEPT) {
3041 3046 cmd->cmd_flags &= ~CFLAG_TRANFLAG;
3042 3047 return (rval);
3043 3048 }
3044 3049 }
3045 3050
3046 3051 /*
3047 3052 * reset the throttle if we were draining
3048 3053 */
3049 3054 mutex_enter(&ptgt->m_tgt_intr_mutex);
3050 3055 if ((ptgt->m_t_ncmds == 0) &&
3051 3056 (ptgt->m_t_throttle == DRAIN_THROTTLE)) {
3052 3057 NDBG23(("reset throttle"));
3053 3058 ASSERT(ptgt->m_reset_delay == 0);
3054 3059 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
3055 3060 }
3056 3061
3057 3062 /*
3058 3063 * If device handle has already been invalidated, just
3059 3064 * fail the command. In theory, command from scsi_vhci
3060 3065 * client is impossible send down command with invalid
3061 3066 * devhdl since devhdl is set after path offline, target
3062 3067 * driver is not suppose to select a offlined path.
3063 3068 */
3064 3069 if (ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) {
3065 3070 NDBG20(("rejecting command, it might because invalid devhdl "
3066 3071 "request."));
3067 3072 mutex_exit(&ptgt->m_tgt_intr_mutex);
3068 3073 mutex_enter(&mpt->m_mutex);
3069 3074 /*
3070 3075 * If HBA is being reset, the DevHandles are being
3071 3076 * re-initialized, which means that they could be invalid
3072 3077 * even if the target is still attached. Check if being reset
3073 3078 * and if DevHandle is being re-initialized. If this is the
3074 3079 * case, return BUSY so the I/O can be retried later.
3075 3080 */
3076 3081 if (mpt->m_in_reset) {
3077 3082 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET,
3078 3083 STAT_BUS_RESET);
3079 3084 if (cmd->cmd_flags & CFLAG_TXQ) {
3080 3085 mptsas_doneq_add(mpt, cmd);
3081 3086 mptsas_doneq_empty(mpt);
3082 3087 mutex_exit(&mpt->m_mutex);
3083 3088 return (rval);
3084 3089 } else {
3085 3090 mutex_exit(&mpt->m_mutex);
3086 3091 return (TRAN_BUSY);
3087 3092 }
3088 3093 }
3089 3094 mptsas_set_pkt_reason(mpt, cmd, CMD_DEV_GONE, STAT_TERMINATED);
3090 3095 if (cmd->cmd_flags & CFLAG_TXQ) {
3091 3096 mptsas_doneq_add(mpt, cmd);
3092 3097 mptsas_doneq_empty(mpt);
3093 3098 mutex_exit(&mpt->m_mutex);
3094 3099 return (rval);
3095 3100 } else {
3096 3101 mutex_exit(&mpt->m_mutex);
3097 3102 return (TRAN_FATAL_ERROR);
3098 3103 }
3099 3104 }
3100 3105 mutex_exit(&ptgt->m_tgt_intr_mutex);
3101 3106 /*
3102 3107 * The first case is the normal case. mpt gets a command from the
3103 3108 * target driver and starts it.
3104 3109 * Since SMID 0 is reserved and the TM slot is reserved, the actual max
3105 3110 * commands is m_max_requests - 2.
3106 3111 */
3107 3112 mutex_enter(&ptgt->m_tgt_intr_mutex);
3108 3113 if ((ptgt->m_t_throttle > HOLD_THROTTLE) &&
3109 3114 (ptgt->m_t_ncmds < ptgt->m_t_throttle) &&
3110 3115 (ptgt->m_reset_delay == 0) &&
3111 3116 (ptgt->m_t_nwait == 0) &&
3112 3117 ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0)) {
3113 3118 mutex_exit(&ptgt->m_tgt_intr_mutex);
3114 3119 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
3115 3120 (void) mptsas_start_cmd0(mpt, cmd);
3116 3121 } else {
3117 3122 mutex_enter(&mpt->m_mutex);
3118 3123 mptsas_waitq_add(mpt, cmd);
3119 3124 mutex_exit(&mpt->m_mutex);
3120 3125 }
3121 3126 } else {
3122 3127 /*
3123 3128 * Add this pkt to the work queue
3124 3129 */
3125 3130 mutex_exit(&ptgt->m_tgt_intr_mutex);
3126 3131 mutex_enter(&mpt->m_mutex);
3127 3132 mptsas_waitq_add(mpt, cmd);
3128 3133
3129 3134 if (cmd->cmd_pkt_flags & FLAG_NOINTR) {
3130 3135 (void) mptsas_poll(mpt, cmd, MPTSAS_POLL_TIME);
3131 3136
3132 3137 /*
3133 3138 * Only flush the doneq if this is not a TM
3134 3139 * cmd. For TM cmds the flushing of the
3135 3140 * doneq will be done in those routines.
3136 3141 */
3137 3142 if ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) {
3138 3143 mptsas_doneq_empty(mpt);
3139 3144 }
3140 3145 }
3141 3146 mutex_exit(&mpt->m_mutex);
3142 3147 }
3143 3148 return (rval);
3144 3149 }
3145 3150
3146 3151 int
3147 3152 mptsas_save_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
3148 3153 {
3149 3154 mptsas_slots_t *slots;
3150 3155 int slot;
3151 3156 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3152 3157 mptsas_slot_free_e_t *pe;
3153 3158 int qn, qn_first;
3154 3159
3155 3160 slots = mpt->m_active;
3156 3161
3157 3162 /*
3158 3163 * Account for reserved TM request slot and reserved SMID of 0.
3159 3164 */
3160 3165 ASSERT(slots->m_n_slots == (mpt->m_max_requests - 2));
3161 3166
3162 3167 qn = qn_first = CPU->cpu_seqid & (mpt->m_slot_freeq_pair_n - 1);
3163 3168
3164 3169 qpair_retry:
3165 3170 ASSERT(qn < mpt->m_slot_freeq_pair_n);
3166 3171 mutex_enter(&mpt->m_slot_freeq_pairp[qn].m_slot_allocq.s.m_fq_mutex);
3167 3172 pe = list_head(&mpt->m_slot_freeq_pairp[qn].m_slot_allocq.
3168 3173 s.m_fq_list);
3169 3174 if (!pe) { /* switch the allocq and releq */
3170 3175 mutex_enter(&mpt->m_slot_freeq_pairp[qn].m_slot_releq.
3171 3176 s.m_fq_mutex);
3172 3177 if (mpt->m_slot_freeq_pairp[qn].m_slot_releq.s.m_fq_n) {
3173 3178 mpt->m_slot_freeq_pairp[qn].
3174 3179 m_slot_allocq.s.m_fq_n =
3175 3180 mpt->m_slot_freeq_pairp[qn].
3176 3181 m_slot_releq.s.m_fq_n;
3177 3182 mpt->m_slot_freeq_pairp[qn].
3178 3183 m_slot_allocq.s.m_fq_list.list_head.list_next =
3179 3184 mpt->m_slot_freeq_pairp[qn].
3180 3185 m_slot_releq.s.m_fq_list.list_head.list_next;
3181 3186 mpt->m_slot_freeq_pairp[qn].
3182 3187 m_slot_allocq.s.m_fq_list.list_head.list_prev =
3183 3188 mpt->m_slot_freeq_pairp[qn].
3184 3189 m_slot_releq.s.m_fq_list.list_head.list_prev;
3185 3190 mpt->m_slot_freeq_pairp[qn].
3186 3191 m_slot_releq.s.m_fq_list.list_head.list_prev->
3187 3192 list_next =
3188 3193 &mpt->m_slot_freeq_pairp[qn].
3189 3194 m_slot_allocq.s.m_fq_list.list_head;
3190 3195 mpt->m_slot_freeq_pairp[qn].
3191 3196 m_slot_releq.s.m_fq_list.list_head.list_next->
3192 3197 list_prev =
3193 3198 &mpt->m_slot_freeq_pairp[qn].
3194 3199 m_slot_allocq.s.m_fq_list.list_head;
3195 3200
3196 3201 mpt->m_slot_freeq_pairp[qn].
3197 3202 m_slot_releq.s.m_fq_list.list_head.list_next =
3198 3203 mpt->m_slot_freeq_pairp[qn].
3199 3204 m_slot_releq.s.m_fq_list.list_head.list_prev =
3200 3205 &mpt->m_slot_freeq_pairp[qn].
3201 3206 m_slot_releq.s.m_fq_list.list_head;
3202 3207 mpt->m_slot_freeq_pairp[qn].
3203 3208 m_slot_releq.s.m_fq_n = 0;
3204 3209 } else {
3205 3210 mutex_exit(&mpt->m_slot_freeq_pairp[qn].
3206 3211 m_slot_releq.s.m_fq_mutex);
3207 3212 mutex_exit(&mpt->m_slot_freeq_pairp[qn].
3208 3213 m_slot_allocq.s.m_fq_mutex);
3209 3214 qn = (qn + 1) & (mpt->m_slot_freeq_pair_n - 1);
3210 3215 if (qn == qn_first)
3211 3216 return (FALSE);
3212 3217 else
3213 3218 goto qpair_retry;
3214 3219 }
3215 3220 mutex_exit(&mpt->m_slot_freeq_pairp[qn].
3216 3221 m_slot_releq.s.m_fq_mutex);
3217 3222 pe = list_head(&mpt->m_slot_freeq_pairp[qn].
3218 3223 m_slot_allocq.s.m_fq_list);
3219 3224 ASSERT(pe);
3220 3225 }
3221 3226 list_remove(&mpt->m_slot_freeq_pairp[qn].
3222 3227 m_slot_allocq.s.m_fq_list, pe);
3223 3228 slot = pe->slot;
3224 3229 /*
3225 3230 * Make sure SMID is not using reserved value of 0
3226 3231 * and the TM request slot.
3227 3232 */
3228 3233 ASSERT((slot > 0) && (slot <= slots->m_n_slots) &&
3229 3234 mpt->m_slot_freeq_pairp[qn].m_slot_allocq.s.m_fq_n > 0);
3230 3235 cmd->cmd_slot = slot;
3231 3236 mpt->m_slot_freeq_pairp[qn].m_slot_allocq.s.m_fq_n--;
3232 3237 ASSERT(mpt->m_slot_freeq_pairp[qn].m_slot_allocq.s.m_fq_n >= 0);
3233 3238
3234 3239 mutex_exit(&mpt->m_slot_freeq_pairp[qn].m_slot_allocq.s.m_fq_mutex);
3235 3240 /*
3236 3241 * only increment per target ncmds if this is not a
3237 3242 * command that has no target associated with it (i.e. a
3238 3243 * event acknoledgment)
3239 3244 */
3240 3245 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
3241 3246 mutex_enter(&ptgt->m_tgt_intr_mutex);
3242 3247 ptgt->m_t_ncmds++;
3243 3248 mutex_exit(&ptgt->m_tgt_intr_mutex);
3244 3249 }
3245 3250 cmd->cmd_active_timeout = cmd->cmd_pkt->pkt_time;
3246 3251
3247 3252 /*
3248 3253 * If initial timout is less than or equal to one tick, bump
3249 3254 * the timeout by a tick so that command doesn't timeout before
3250 3255 * its allotted time.
3251 3256 */
3252 3257 if (cmd->cmd_active_timeout <= mptsas_scsi_watchdog_tick) {
3253 3258 cmd->cmd_active_timeout += mptsas_scsi_watchdog_tick;
3254 3259 }
3255 3260 return (TRUE);
3256 3261 }
3257 3262
3258 3263 /*
3259 3264 * prepare the pkt:
3260 3265 * the pkt may have been resubmitted or just reused so
3261 3266 * initialize some fields and do some checks.
3262 3267 */
3263 3268 static int
3264 3269 mptsas_prepare_pkt(mptsas_cmd_t *cmd)
3265 3270 {
3266 3271 struct scsi_pkt *pkt = CMD2PKT(cmd);
3267 3272
3268 3273 NDBG1(("mptsas_prepare_pkt: cmd=0x%p", (void *)cmd));
3269 3274
3270 3275 /*
3271 3276 * Reinitialize some fields that need it; the packet may
3272 3277 * have been resubmitted
3273 3278 */
3274 3279 pkt->pkt_reason = CMD_CMPLT;
3275 3280 pkt->pkt_state = 0;
3276 3281 pkt->pkt_statistics = 0;
3277 3282 pkt->pkt_resid = 0;
3278 3283 cmd->cmd_age = 0;
3279 3284 cmd->cmd_pkt_flags = pkt->pkt_flags;
3280 3285
3281 3286 /*
3282 3287 * zero status byte.
3283 3288 */
3284 3289 *(pkt->pkt_scbp) = 0;
3285 3290
3286 3291 if (cmd->cmd_flags & CFLAG_DMAVALID) {
3287 3292 pkt->pkt_resid = cmd->cmd_dmacount;
3288 3293
3289 3294 /*
3290 3295 * consistent packets need to be sync'ed first
3291 3296 * (only for data going out)
3292 3297 */
3293 3298 if ((cmd->cmd_flags & CFLAG_CMDIOPB) &&
3294 3299 (cmd->cmd_flags & CFLAG_DMASEND)) {
3295 3300 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
3296 3301 DDI_DMA_SYNC_FORDEV);
3297 3302 }
3298 3303 }
3299 3304
3300 3305 cmd->cmd_flags =
3301 3306 (cmd->cmd_flags & ~(CFLAG_TRANFLAG)) |
3302 3307 CFLAG_PREPARED | CFLAG_IN_TRANSPORT;
3303 3308
3304 3309 return (TRAN_ACCEPT);
3305 3310 }
3306 3311
3307 3312 /*
3308 3313 * tran_init_pkt(9E) - allocate scsi_pkt(9S) for command
3309 3314 *
3310 3315 * One of three possibilities:
3311 3316 * - allocate scsi_pkt
3312 3317 * - allocate scsi_pkt and DMA resources
3313 3318 * - allocate DMA resources to an already-allocated pkt
3314 3319 */
3315 3320 static struct scsi_pkt *
3316 3321 mptsas_scsi_init_pkt(struct scsi_address *ap, struct scsi_pkt *pkt,
3317 3322 struct buf *bp, int cmdlen, int statuslen, int tgtlen, int flags,
3318 3323 int (*callback)(), caddr_t arg)
3319 3324 {
3320 3325 mptsas_cmd_t *cmd, *new_cmd;
3321 3326 mptsas_t *mpt = ADDR2MPT(ap);
3322 3327 int failure = 1;
3323 3328 #ifndef __sparc
3324 3329 uint_t oldcookiec;
3325 3330 #endif /* __sparc */
3326 3331 mptsas_target_t *ptgt = NULL;
3327 3332 int rval;
3328 3333 mptsas_tgt_private_t *tgt_private;
3329 3334 int kf;
3330 3335
3331 3336 kf = (callback == SLEEP_FUNC)? KM_SLEEP: KM_NOSLEEP;
3332 3337
3333 3338 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->
3334 3339 tran_tgt_private;
3335 3340 ASSERT(tgt_private != NULL);
3336 3341 if (tgt_private == NULL) {
3337 3342 return (NULL);
3338 3343 }
3339 3344 ptgt = tgt_private->t_private;
3340 3345 ASSERT(ptgt != NULL);
3341 3346 if (ptgt == NULL)
3342 3347 return (NULL);
3343 3348 ap->a_target = ptgt->m_devhdl;
3344 3349 ap->a_lun = tgt_private->t_lun;
3345 3350
3346 3351 ASSERT(callback == NULL_FUNC || callback == SLEEP_FUNC);
3347 3352 #ifdef MPTSAS_TEST_EXTRN_ALLOC
3348 3353 statuslen *= 100; tgtlen *= 4;
3349 3354 #endif
3350 3355 NDBG3(("mptsas_scsi_init_pkt:\n"
3351 3356 "\ttgt=%d in=0x%p bp=0x%p clen=%d slen=%d tlen=%d flags=%x",
3352 3357 ap->a_target, (void *)pkt, (void *)bp,
3353 3358 cmdlen, statuslen, tgtlen, flags));
3354 3359
3355 3360 /*
3356 3361 * Allocate the new packet.
3357 3362 */
3358 3363 if (pkt == NULL) {
3359 3364 ddi_dma_handle_t save_dma_handle;
3360 3365 ddi_dma_handle_t save_arq_dma_handle;
3361 3366 struct buf *save_arq_bp;
3362 3367 ddi_dma_cookie_t save_arqcookie;
3363 3368 #ifdef __sparc
3364 3369 mptti_t *save_sg;
3365 3370 #endif /* __sparc */
3366 3371
3367 3372 cmd = kmem_cache_alloc(mpt->m_kmem_cache, kf);
3368 3373
3369 3374 if (cmd) {
3370 3375 save_dma_handle = cmd->cmd_dmahandle;
3371 3376 save_arq_dma_handle = cmd->cmd_arqhandle;
3372 3377 save_arq_bp = cmd->cmd_arq_buf;
3373 3378 save_arqcookie = cmd->cmd_arqcookie;
3374 3379 #ifdef __sparc
3375 3380 save_sg = cmd->cmd_sg;
3376 3381 #endif /* __sparc */
3377 3382 bzero(cmd, sizeof (*cmd) + scsi_pkt_size());
3378 3383 cmd->cmd_dmahandle = save_dma_handle;
3379 3384 cmd->cmd_arqhandle = save_arq_dma_handle;
3380 3385 cmd->cmd_arq_buf = save_arq_bp;
3381 3386 cmd->cmd_arqcookie = save_arqcookie;
3382 3387 #ifdef __sparc
3383 3388 cmd->cmd_sg = save_sg;
3384 3389 #endif /* __sparc */
3385 3390 pkt = (void *)((uchar_t *)cmd +
3386 3391 sizeof (struct mptsas_cmd));
3387 3392 pkt->pkt_ha_private = (opaque_t)cmd;
3388 3393 pkt->pkt_address = *ap;
3389 3394 pkt->pkt_private = (opaque_t)cmd->cmd_pkt_private;
3390 3395 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb;
3391 3396 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb;
3392 3397 cmd->cmd_pkt = (struct scsi_pkt *)pkt;
3393 3398 cmd->cmd_cdblen = (uchar_t)cmdlen;
3394 3399 cmd->cmd_scblen = statuslen;
3395 3400 cmd->cmd_rqslen = SENSE_LENGTH;
3396 3401 cmd->cmd_tgt_addr = ptgt;
3397 3402 failure = 0;
3398 3403 }
3399 3404
3400 3405 if (failure || (cmdlen > sizeof (cmd->cmd_cdb)) ||
3401 3406 (tgtlen > PKT_PRIV_LEN) ||
3402 3407 (statuslen > EXTCMDS_STATUS_SIZE)) {
3403 3408 if (failure == 0) {
3404 3409 /*
3405 3410 * if extern alloc fails, all will be
3406 3411 * deallocated, including cmd
3407 3412 */
3408 3413 failure = mptsas_pkt_alloc_extern(mpt, cmd,
3409 3414 cmdlen, tgtlen, statuslen, kf);
3410 3415 }
3411 3416 if (failure) {
3412 3417 /*
3413 3418 * if extern allocation fails, it will
3414 3419 * deallocate the new pkt as well
3415 3420 */
3416 3421 return (NULL);
3417 3422 }
3418 3423 }
3419 3424 new_cmd = cmd;
3420 3425
3421 3426 } else {
3422 3427 cmd = PKT2CMD(pkt);
3423 3428 new_cmd = NULL;
3424 3429 }
3425 3430
3426 3431
3427 3432 #ifndef __sparc
3428 3433 /* grab cmd->cmd_cookiec here as oldcookiec */
3429 3434
3430 3435 oldcookiec = cmd->cmd_cookiec;
3431 3436 #endif /* __sparc */
3432 3437
3433 3438 /*
3434 3439 * If the dma was broken up into PARTIAL transfers cmd_nwin will be
3435 3440 * greater than 0 and we'll need to grab the next dma window
3436 3441 */
3437 3442 /*
3438 3443 * SLM-not doing extra command frame right now; may add later
3439 3444 */
3440 3445
3441 3446 if (cmd->cmd_nwin > 0) {
3442 3447
3443 3448 /*
3444 3449 * Make sure we havn't gone past the the total number
3445 3450 * of windows
3446 3451 */
3447 3452 if (++cmd->cmd_winindex >= cmd->cmd_nwin) {
3448 3453 return (NULL);
3449 3454 }
3450 3455 if (ddi_dma_getwin(cmd->cmd_dmahandle, cmd->cmd_winindex,
3451 3456 &cmd->cmd_dma_offset, &cmd->cmd_dma_len,
3452 3457 &cmd->cmd_cookie, &cmd->cmd_cookiec) == DDI_FAILURE) {
3453 3458 return (NULL);
3454 3459 }
3455 3460 goto get_dma_cookies;
3456 3461 }
3457 3462
3458 3463
3459 3464 if (flags & PKT_XARQ) {
3460 3465 cmd->cmd_flags |= CFLAG_XARQ;
3461 3466 }
3462 3467
3463 3468 /*
3464 3469 * DMA resource allocation. This version assumes your
3465 3470 * HBA has some sort of bus-mastering or onboard DMA capability, with a
3466 3471 * scatter-gather list of length MPTSAS_MAX_DMA_SEGS, as given in the
3467 3472 * ddi_dma_attr_t structure and passed to scsi_impl_dmaget.
3468 3473 */
3469 3474 if (bp && (bp->b_bcount != 0) &&
3470 3475 (cmd->cmd_flags & CFLAG_DMAVALID) == 0) {
3471 3476
3472 3477 int cnt, dma_flags;
3473 3478 mptti_t *dmap; /* ptr to the S/G list */
3474 3479
3475 3480 /*
3476 3481 * Set up DMA memory and position to the next DMA segment.
3477 3482 */
3478 3483 ASSERT(cmd->cmd_dmahandle != NULL);
3479 3484
3480 3485 if (bp->b_flags & B_READ) {
3481 3486 dma_flags = DDI_DMA_READ;
3482 3487 cmd->cmd_flags &= ~CFLAG_DMASEND;
3483 3488 } else {
3484 3489 dma_flags = DDI_DMA_WRITE;
3485 3490 cmd->cmd_flags |= CFLAG_DMASEND;
3486 3491 }
3487 3492 if (flags & PKT_CONSISTENT) {
3488 3493 cmd->cmd_flags |= CFLAG_CMDIOPB;
3489 3494 dma_flags |= DDI_DMA_CONSISTENT;
3490 3495 }
3491 3496
3492 3497 if (flags & PKT_DMA_PARTIAL) {
3493 3498 dma_flags |= DDI_DMA_PARTIAL;
3494 3499 }
3495 3500
3496 3501 /*
3497 3502 * workaround for byte hole issue on psycho and
3498 3503 * schizo pre 2.1
3499 3504 */
3500 3505 if ((bp->b_flags & B_READ) && ((bp->b_flags &
3501 3506 (B_PAGEIO|B_REMAPPED)) != B_PAGEIO) &&
3502 3507 ((uintptr_t)bp->b_un.b_addr & 0x7)) {
3503 3508 dma_flags |= DDI_DMA_CONSISTENT;
3504 3509 }
3505 3510
3506 3511 rval = ddi_dma_buf_bind_handle(cmd->cmd_dmahandle, bp,
3507 3512 dma_flags, callback, arg,
3508 3513 &cmd->cmd_cookie, &cmd->cmd_cookiec);
3509 3514 if (rval == DDI_DMA_PARTIAL_MAP) {
3510 3515 (void) ddi_dma_numwin(cmd->cmd_dmahandle,
3511 3516 &cmd->cmd_nwin);
3512 3517 cmd->cmd_winindex = 0;
3513 3518 (void) ddi_dma_getwin(cmd->cmd_dmahandle,
3514 3519 cmd->cmd_winindex, &cmd->cmd_dma_offset,
3515 3520 &cmd->cmd_dma_len, &cmd->cmd_cookie,
3516 3521 &cmd->cmd_cookiec);
3517 3522 } else if (rval && (rval != DDI_DMA_MAPPED)) {
3518 3523 switch (rval) {
3519 3524 case DDI_DMA_NORESOURCES:
3520 3525 bioerror(bp, 0);
3521 3526 break;
3522 3527 case DDI_DMA_BADATTR:
3523 3528 case DDI_DMA_NOMAPPING:
3524 3529 bioerror(bp, EFAULT);
3525 3530 break;
3526 3531 case DDI_DMA_TOOBIG:
3527 3532 default:
3528 3533 bioerror(bp, EINVAL);
3529 3534 break;
3530 3535 }
3531 3536 cmd->cmd_flags &= ~CFLAG_DMAVALID;
3532 3537 if (new_cmd) {
3533 3538 mptsas_scsi_destroy_pkt(ap, pkt);
3534 3539 }
3535 3540 return ((struct scsi_pkt *)NULL);
3536 3541 }
3537 3542
3538 3543 get_dma_cookies:
3539 3544 cmd->cmd_flags |= CFLAG_DMAVALID;
3540 3545 ASSERT(cmd->cmd_cookiec > 0);
3541 3546
3542 3547 if (cmd->cmd_cookiec > MPTSAS_MAX_CMD_SEGS) {
3543 3548 mptsas_log(mpt, CE_NOTE, "large cookiec received %d\n",
3544 3549 cmd->cmd_cookiec);
3545 3550 bioerror(bp, EINVAL);
3546 3551 if (new_cmd) {
3547 3552 mptsas_scsi_destroy_pkt(ap, pkt);
3548 3553 }
3549 3554 return ((struct scsi_pkt *)NULL);
3550 3555 }
3551 3556
3552 3557 /*
3553 3558 * Allocate extra SGL buffer if needed.
3554 3559 */
3555 3560 if ((cmd->cmd_cookiec > MPTSAS_MAX_FRAME_SGES64(mpt)) &&
3556 3561 (cmd->cmd_extra_frames == NULL)) {
3557 3562 if (mptsas_alloc_extra_sgl_frame(mpt, cmd) ==
3558 3563 DDI_FAILURE) {
3559 3564 mptsas_log(mpt, CE_WARN, "MPT SGL mem alloc "
3560 3565 "failed");
3561 3566 bioerror(bp, ENOMEM);
3562 3567 if (new_cmd) {
3563 3568 mptsas_scsi_destroy_pkt(ap, pkt);
3564 3569 }
3565 3570 return ((struct scsi_pkt *)NULL);
3566 3571 }
3567 3572 }
3568 3573
3569 3574 /*
3570 3575 * Always use scatter-gather transfer
3571 3576 * Use the loop below to store physical addresses of
3572 3577 * DMA segments, from the DMA cookies, into your HBA's
3573 3578 * scatter-gather list.
3574 3579 * We need to ensure we have enough kmem alloc'd
3575 3580 * for the sg entries since we are no longer using an
3576 3581 * array inside mptsas_cmd_t.
3577 3582 *
3578 3583 * We check cmd->cmd_cookiec against oldcookiec so
3579 3584 * the scatter-gather list is correctly allocated
3580 3585 */
3581 3586 #ifndef __sparc
3582 3587 if (oldcookiec != cmd->cmd_cookiec) {
3583 3588 if (cmd->cmd_sg != (mptti_t *)NULL) {
3584 3589 kmem_free(cmd->cmd_sg, sizeof (mptti_t) *
3585 3590 oldcookiec);
3586 3591 cmd->cmd_sg = NULL;
3587 3592 }
3588 3593 }
3589 3594
3590 3595 if (cmd->cmd_sg == (mptti_t *)NULL) {
3591 3596 cmd->cmd_sg = kmem_alloc((size_t)(sizeof (mptti_t)*
3592 3597 cmd->cmd_cookiec), kf);
3593 3598
3594 3599 if (cmd->cmd_sg == (mptti_t *)NULL) {
3595 3600 mptsas_log(mpt, CE_WARN,
3596 3601 "unable to kmem_alloc enough memory "
3597 3602 "for scatter/gather list");
3598 3603 /*
3599 3604 * if we have an ENOMEM condition we need to behave
3600 3605 * the same way as the rest of this routine
3601 3606 */
3602 3607
3603 3608 bioerror(bp, ENOMEM);
3604 3609 if (new_cmd) {
3605 3610 mptsas_scsi_destroy_pkt(ap, pkt);
3606 3611 }
3607 3612 return ((struct scsi_pkt *)NULL);
3608 3613 }
3609 3614 }
3610 3615 #endif /* __sparc */
3611 3616 dmap = cmd->cmd_sg;
3612 3617
3613 3618 ASSERT(cmd->cmd_cookie.dmac_size != 0);
3614 3619
3615 3620 /*
3616 3621 * store the first segment into the S/G list
3617 3622 */
3618 3623 dmap->count = cmd->cmd_cookie.dmac_size;
3619 3624 dmap->addr.address64.Low = (uint32_t)
3620 3625 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull);
3621 3626 dmap->addr.address64.High = (uint32_t)
3622 3627 (cmd->cmd_cookie.dmac_laddress >> 32);
3623 3628
3624 3629 /*
3625 3630 * dmacount counts the size of the dma for this window
3626 3631 * (if partial dma is being used). totaldmacount
3627 3632 * keeps track of the total amount of dma we have
3628 3633 * transferred for all the windows (needed to calculate
3629 3634 * the resid value below).
3630 3635 */
3631 3636 cmd->cmd_dmacount = cmd->cmd_cookie.dmac_size;
3632 3637 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size;
3633 3638
3634 3639 /*
3635 3640 * We already stored the first DMA scatter gather segment,
3636 3641 * start at 1 if we need to store more.
3637 3642 */
3638 3643 for (cnt = 1; cnt < cmd->cmd_cookiec; cnt++) {
3639 3644 /*
3640 3645 * Get next DMA cookie
3641 3646 */
3642 3647 ddi_dma_nextcookie(cmd->cmd_dmahandle,
3643 3648 &cmd->cmd_cookie);
3644 3649 dmap++;
3645 3650
3646 3651 cmd->cmd_dmacount += cmd->cmd_cookie.dmac_size;
3647 3652 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size;
3648 3653
3649 3654 /*
3650 3655 * store the segment parms into the S/G list
3651 3656 */
3652 3657 dmap->count = cmd->cmd_cookie.dmac_size;
3653 3658 dmap->addr.address64.Low = (uint32_t)
3654 3659 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull);
3655 3660 dmap->addr.address64.High = (uint32_t)
3656 3661 (cmd->cmd_cookie.dmac_laddress >> 32);
3657 3662 }
3658 3663
3659 3664 /*
3660 3665 * If this was partially allocated we set the resid
3661 3666 * the amount of data NOT transferred in this window
3662 3667 * If there is only one window, the resid will be 0
3663 3668 */
3664 3669 pkt->pkt_resid = (bp->b_bcount - cmd->cmd_totaldmacount);
3665 3670 NDBG16(("mptsas_dmaget: cmd_dmacount=%d.", cmd->cmd_dmacount));
3666 3671 }
3667 3672 return (pkt);
3668 3673 }
3669 3674
3670 3675 /*
3671 3676 * tran_destroy_pkt(9E) - scsi_pkt(9s) deallocation
3672 3677 *
3673 3678 * Notes:
3674 3679 * - also frees DMA resources if allocated
3675 3680 * - implicit DMA synchonization
3676 3681 */
3677 3682 static void
3678 3683 mptsas_scsi_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
3679 3684 {
3680 3685 mptsas_cmd_t *cmd = PKT2CMD(pkt);
3681 3686 mptsas_t *mpt = ADDR2MPT(ap);
3682 3687
3683 3688 NDBG3(("mptsas_scsi_destroy_pkt: target=%d pkt=0x%p",
3684 3689 ap->a_target, (void *)pkt));
3685 3690
3686 3691 if (cmd->cmd_flags & CFLAG_DMAVALID) {
3687 3692 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle);
3688 3693 cmd->cmd_flags &= ~CFLAG_DMAVALID;
3689 3694 }
3690 3695 #ifndef __sparc
3691 3696 if (cmd->cmd_sg) {
3692 3697 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * cmd->cmd_cookiec);
3693 3698 cmd->cmd_sg = NULL;
3694 3699 }
3695 3700 #endif /* __sparc */
3696 3701 mptsas_free_extra_sgl_frame(mpt, cmd);
3697 3702
3698 3703 if ((cmd->cmd_flags &
3699 3704 (CFLAG_FREE | CFLAG_CDBEXTERN | CFLAG_PRIVEXTERN |
3700 3705 CFLAG_SCBEXTERN)) == 0) {
3701 3706 cmd->cmd_flags = CFLAG_FREE;
3702 3707 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd);
3703 3708 } else {
3704 3709 mptsas_pkt_destroy_extern(mpt, cmd);
3705 3710 }
3706 3711 }
3707 3712
3708 3713 /*
3709 3714 * kmem cache constructor and destructor:
3710 3715 * When constructing, we bzero the cmd and allocate the dma handle
3711 3716 * When destructing, just free the dma handle
3712 3717 */
3713 3718 static int
3714 3719 mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags)
3715 3720 {
3716 3721 mptsas_cmd_t *cmd = buf;
3717 3722 mptsas_t *mpt = cdrarg;
3718 3723 struct scsi_address ap;
3719 3724 uint_t cookiec;
3720 3725 ddi_dma_attr_t arq_dma_attr;
3721 3726 int (*callback)(caddr_t);
3722 3727
3723 3728 callback = (kmflags == KM_SLEEP)? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT;
3724 3729
3725 3730 NDBG4(("mptsas_kmem_cache_constructor"));
3726 3731
3727 3732 ap.a_hba_tran = mpt->m_tran;
3728 3733 ap.a_target = 0;
3729 3734 ap.a_lun = 0;
3730 3735
3731 3736 /*
3732 3737 * allocate a dma handle
3733 3738 */
3734 3739 if ((ddi_dma_alloc_handle(mpt->m_dip, &mpt->m_io_dma_attr, callback,
3735 3740 NULL, &cmd->cmd_dmahandle)) != DDI_SUCCESS) {
3736 3741 cmd->cmd_dmahandle = NULL;
3737 3742 return (-1);
3738 3743 }
3739 3744
3740 3745 cmd->cmd_arq_buf = scsi_alloc_consistent_buf(&ap, (struct buf *)NULL,
3741 3746 SENSE_LENGTH, B_READ, callback, NULL);
3742 3747 if (cmd->cmd_arq_buf == NULL) {
3743 3748 ddi_dma_free_handle(&cmd->cmd_dmahandle);
3744 3749 cmd->cmd_dmahandle = NULL;
3745 3750 return (-1);
3746 3751 }
3747 3752
3748 3753 /*
3749 3754 * allocate a arq handle
3750 3755 */
3751 3756 arq_dma_attr = mpt->m_msg_dma_attr;
3752 3757 arq_dma_attr.dma_attr_sgllen = 1;
3753 3758 if ((ddi_dma_alloc_handle(mpt->m_dip, &arq_dma_attr, callback,
3754 3759 NULL, &cmd->cmd_arqhandle)) != DDI_SUCCESS) {
3755 3760 ddi_dma_free_handle(&cmd->cmd_dmahandle);
3756 3761 scsi_free_consistent_buf(cmd->cmd_arq_buf);
3757 3762 cmd->cmd_dmahandle = NULL;
3758 3763 cmd->cmd_arqhandle = NULL;
3759 3764 return (-1);
3760 3765 }
3761 3766
3762 3767 if (ddi_dma_buf_bind_handle(cmd->cmd_arqhandle,
3763 3768 cmd->cmd_arq_buf, (DDI_DMA_READ | DDI_DMA_CONSISTENT),
3764 3769 callback, NULL, &cmd->cmd_arqcookie, &cookiec) != DDI_SUCCESS) {
3765 3770 ddi_dma_free_handle(&cmd->cmd_dmahandle);
3766 3771 ddi_dma_free_handle(&cmd->cmd_arqhandle);
3767 3772 scsi_free_consistent_buf(cmd->cmd_arq_buf);
3768 3773 cmd->cmd_dmahandle = NULL;
3769 3774 cmd->cmd_arqhandle = NULL;
3770 3775 cmd->cmd_arq_buf = NULL;
3771 3776 return (-1);
3772 3777 }
3773 3778 /*
3774 3779 * In sparc, the sgl length in most of the cases would be 1, so we
3775 3780 * pre-allocate it in cache. On x86, the max number would be 256,
3776 3781 * pre-allocate a maximum would waste a lot of memory especially
3777 3782 * when many cmds are put onto waitq.
3778 3783 */
3779 3784 #ifdef __sparc
3780 3785 cmd->cmd_sg = kmem_alloc((size_t)(sizeof (mptti_t)*
3781 3786 MPTSAS_MAX_CMD_SEGS), KM_SLEEP);
3782 3787 #endif /* __sparc */
3783 3788
3784 3789 return (0);
3785 3790 }
3786 3791
3787 3792 static void
3788 3793 mptsas_kmem_cache_destructor(void *buf, void *cdrarg)
3789 3794 {
3790 3795 #ifndef __lock_lint
3791 3796 _NOTE(ARGUNUSED(cdrarg))
3792 3797 #endif
3793 3798 mptsas_cmd_t *cmd = buf;
3794 3799
3795 3800 NDBG4(("mptsas_kmem_cache_destructor"));
3796 3801
3797 3802 if (cmd->cmd_arqhandle) {
3798 3803 (void) ddi_dma_unbind_handle(cmd->cmd_arqhandle);
3799 3804 ddi_dma_free_handle(&cmd->cmd_arqhandle);
3800 3805 cmd->cmd_arqhandle = NULL;
3801 3806 }
3802 3807 if (cmd->cmd_arq_buf) {
3803 3808 scsi_free_consistent_buf(cmd->cmd_arq_buf);
3804 3809 cmd->cmd_arq_buf = NULL;
3805 3810 }
3806 3811 if (cmd->cmd_dmahandle) {
3807 3812 ddi_dma_free_handle(&cmd->cmd_dmahandle);
3808 3813 cmd->cmd_dmahandle = NULL;
3809 3814 }
3810 3815 #ifdef __sparc
3811 3816 if (cmd->cmd_sg) {
3812 3817 kmem_free(cmd->cmd_sg, sizeof (mptti_t)* MPTSAS_MAX_CMD_SEGS);
3813 3818 cmd->cmd_sg = NULL;
3814 3819 }
3815 3820 #endif /* __sparc */
3816 3821 }
3817 3822
3818 3823 static int
3819 3824 mptsas_cache_frames_constructor(void *buf, void *cdrarg, int kmflags)
3820 3825 {
3821 3826 mptsas_cache_frames_t *p = buf;
3822 3827 mptsas_t *mpt = cdrarg;
3823 3828 ddi_dma_attr_t frame_dma_attr;
3824 3829 size_t mem_size, alloc_len;
3825 3830 ddi_dma_cookie_t cookie;
3826 3831 uint_t ncookie;
3827 3832 int (*callback)(caddr_t) = (kmflags == KM_SLEEP)
3828 3833 ? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT;
3829 3834
3830 3835 frame_dma_attr = mpt->m_msg_dma_attr;
3831 3836 frame_dma_attr.dma_attr_align = 0x10;
3832 3837 frame_dma_attr.dma_attr_sgllen = 1;
3833 3838
3834 3839 if (ddi_dma_alloc_handle(mpt->m_dip, &frame_dma_attr, callback, NULL,
3835 3840 &p->m_dma_hdl) != DDI_SUCCESS) {
3836 3841 mptsas_log(mpt, CE_WARN, "Unable to allocate dma handle for"
3837 3842 " extra SGL.");
3838 3843 return (DDI_FAILURE);
3839 3844 }
3840 3845
3841 3846 mem_size = (mpt->m_max_request_frames - 1) * mpt->m_req_frame_size;
3842 3847
3843 3848 if (ddi_dma_mem_alloc(p->m_dma_hdl, mem_size, &mpt->m_dev_acc_attr,
3844 3849 DDI_DMA_CONSISTENT, callback, NULL, (caddr_t *)&p->m_frames_addr,
3845 3850 &alloc_len, &p->m_acc_hdl) != DDI_SUCCESS) {
3846 3851 ddi_dma_free_handle(&p->m_dma_hdl);
3847 3852 p->m_dma_hdl = NULL;
3848 3853 mptsas_log(mpt, CE_WARN, "Unable to allocate dma memory for"
3849 3854 " extra SGL.");
3850 3855 return (DDI_FAILURE);
3851 3856 }
3852 3857
3853 3858 if (ddi_dma_addr_bind_handle(p->m_dma_hdl, NULL, p->m_frames_addr,
3854 3859 alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, callback, NULL,
3855 3860 &cookie, &ncookie) != DDI_DMA_MAPPED) {
3856 3861 (void) ddi_dma_mem_free(&p->m_acc_hdl);
3857 3862 ddi_dma_free_handle(&p->m_dma_hdl);
3858 3863 p->m_dma_hdl = NULL;
3859 3864 mptsas_log(mpt, CE_WARN, "Unable to bind DMA resources for"
3860 3865 " extra SGL");
3861 3866 return (DDI_FAILURE);
3862 3867 }
3863 3868
3864 3869 /*
3865 3870 * Store the SGL memory address. This chip uses this
3866 3871 * address to dma to and from the driver. The second
3867 3872 * address is the address mpt uses to fill in the SGL.
3868 3873 */
3869 3874 p->m_phys_addr = cookie.dmac_address;
3870 3875
3871 3876 return (DDI_SUCCESS);
3872 3877 }
3873 3878
3874 3879 static void
3875 3880 mptsas_cache_frames_destructor(void *buf, void *cdrarg)
3876 3881 {
3877 3882 #ifndef __lock_lint
3878 3883 _NOTE(ARGUNUSED(cdrarg))
3879 3884 #endif
3880 3885 mptsas_cache_frames_t *p = buf;
3881 3886 if (p->m_dma_hdl != NULL) {
3882 3887 (void) ddi_dma_unbind_handle(p->m_dma_hdl);
3883 3888 (void) ddi_dma_mem_free(&p->m_acc_hdl);
3884 3889 ddi_dma_free_handle(&p->m_dma_hdl);
3885 3890 p->m_phys_addr = NULL;
3886 3891 p->m_frames_addr = NULL;
3887 3892 p->m_dma_hdl = NULL;
3888 3893 p->m_acc_hdl = NULL;
3889 3894 }
3890 3895
3891 3896 }
3892 3897
3893 3898 /*
3894 3899 * allocate and deallocate external pkt space (ie. not part of mptsas_cmd)
3895 3900 * for non-standard length cdb, pkt_private, status areas
3896 3901 * if allocation fails, then deallocate all external space and the pkt
3897 3902 */
3898 3903 /* ARGSUSED */
3899 3904 static int
3900 3905 mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd,
3901 3906 int cmdlen, int tgtlen, int statuslen, int kf)
3902 3907 {
3903 3908 caddr_t cdbp, scbp, tgt;
3904 3909 int (*callback)(caddr_t) = (kf == KM_SLEEP) ?
3905 3910 DDI_DMA_SLEEP : DDI_DMA_DONTWAIT;
3906 3911 struct scsi_address ap;
3907 3912 size_t senselength;
3908 3913 ddi_dma_attr_t ext_arq_dma_attr;
3909 3914 uint_t cookiec;
3910 3915
3911 3916 NDBG3(("mptsas_pkt_alloc_extern: "
3912 3917 "cmd=0x%p cmdlen=%d tgtlen=%d statuslen=%d kf=%x",
3913 3918 (void *)cmd, cmdlen, tgtlen, statuslen, kf));
3914 3919
3915 3920 tgt = cdbp = scbp = NULL;
3916 3921 cmd->cmd_scblen = statuslen;
3917 3922 cmd->cmd_privlen = (uchar_t)tgtlen;
3918 3923
3919 3924 if (cmdlen > sizeof (cmd->cmd_cdb)) {
3920 3925 if ((cdbp = kmem_zalloc((size_t)cmdlen, kf)) == NULL) {
3921 3926 goto fail;
3922 3927 }
3923 3928 cmd->cmd_pkt->pkt_cdbp = (opaque_t)cdbp;
3924 3929 cmd->cmd_flags |= CFLAG_CDBEXTERN;
3925 3930 }
3926 3931 if (tgtlen > PKT_PRIV_LEN) {
3927 3932 if ((tgt = kmem_zalloc((size_t)tgtlen, kf)) == NULL) {
3928 3933 goto fail;
3929 3934 }
3930 3935 cmd->cmd_flags |= CFLAG_PRIVEXTERN;
3931 3936 cmd->cmd_pkt->pkt_private = tgt;
3932 3937 }
3933 3938 if (statuslen > EXTCMDS_STATUS_SIZE) {
3934 3939 if ((scbp = kmem_zalloc((size_t)statuslen, kf)) == NULL) {
3935 3940 goto fail;
3936 3941 }
3937 3942 cmd->cmd_flags |= CFLAG_SCBEXTERN;
3938 3943 cmd->cmd_pkt->pkt_scbp = (opaque_t)scbp;
3939 3944
3940 3945 /* allocate sense data buf for DMA */
3941 3946
3942 3947 senselength = statuslen - MPTSAS_GET_ITEM_OFF(
3943 3948 struct scsi_arq_status, sts_sensedata);
3944 3949 cmd->cmd_rqslen = (uchar_t)senselength;
3945 3950
3946 3951 ap.a_hba_tran = mpt->m_tran;
3947 3952 ap.a_target = 0;
3948 3953 ap.a_lun = 0;
3949 3954
3950 3955 cmd->cmd_ext_arq_buf = scsi_alloc_consistent_buf(&ap,
3951 3956 (struct buf *)NULL, senselength, B_READ,
3952 3957 callback, NULL);
3953 3958
3954 3959 if (cmd->cmd_ext_arq_buf == NULL) {
3955 3960 goto fail;
3956 3961 }
3957 3962 /*
3958 3963 * allocate a extern arq handle and bind the buf
3959 3964 */
3960 3965 ext_arq_dma_attr = mpt->m_msg_dma_attr;
3961 3966 ext_arq_dma_attr.dma_attr_sgllen = 1;
3962 3967 if ((ddi_dma_alloc_handle(mpt->m_dip,
3963 3968 &ext_arq_dma_attr, callback,
3964 3969 NULL, &cmd->cmd_ext_arqhandle)) != DDI_SUCCESS) {
3965 3970 goto fail;
3966 3971 }
3967 3972
3968 3973 if (ddi_dma_buf_bind_handle(cmd->cmd_ext_arqhandle,
3969 3974 cmd->cmd_ext_arq_buf, (DDI_DMA_READ | DDI_DMA_CONSISTENT),
3970 3975 callback, NULL, &cmd->cmd_ext_arqcookie,
3971 3976 &cookiec)
3972 3977 != DDI_SUCCESS) {
3973 3978 goto fail;
3974 3979 }
3975 3980 cmd->cmd_flags |= CFLAG_EXTARQBUFVALID;
3976 3981 }
3977 3982 return (0);
3978 3983 fail:
3979 3984 mptsas_pkt_destroy_extern(mpt, cmd);
3980 3985 return (1);
3981 3986 }
3982 3987
3983 3988 /*
3984 3989 * deallocate external pkt space and deallocate the pkt
3985 3990 */
3986 3991 static void
3987 3992 mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd)
3988 3993 {
3989 3994 NDBG3(("mptsas_pkt_destroy_extern: cmd=0x%p", (void *)cmd));
3990 3995
3991 3996 if (cmd->cmd_flags & CFLAG_FREE) {
3992 3997 mptsas_log(mpt, CE_PANIC,
3993 3998 "mptsas_pkt_destroy_extern: freeing free packet");
3994 3999 _NOTE(NOT_REACHED)
3995 4000 /* NOTREACHED */
3996 4001 }
3997 4002 if (cmd->cmd_flags & CFLAG_CDBEXTERN) {
3998 4003 kmem_free(cmd->cmd_pkt->pkt_cdbp, (size_t)cmd->cmd_cdblen);
3999 4004 }
4000 4005 if (cmd->cmd_flags & CFLAG_SCBEXTERN) {
4001 4006 kmem_free(cmd->cmd_pkt->pkt_scbp, (size_t)cmd->cmd_scblen);
4002 4007 if (cmd->cmd_flags & CFLAG_EXTARQBUFVALID) {
4003 4008 (void) ddi_dma_unbind_handle(cmd->cmd_ext_arqhandle);
4004 4009 }
4005 4010 if (cmd->cmd_ext_arqhandle) {
4006 4011 ddi_dma_free_handle(&cmd->cmd_ext_arqhandle);
4007 4012 cmd->cmd_ext_arqhandle = NULL;
4008 4013 }
4009 4014 if (cmd->cmd_ext_arq_buf)
4010 4015 scsi_free_consistent_buf(cmd->cmd_ext_arq_buf);
4011 4016 }
4012 4017 if (cmd->cmd_flags & CFLAG_PRIVEXTERN) {
4013 4018 kmem_free(cmd->cmd_pkt->pkt_private, (size_t)cmd->cmd_privlen);
4014 4019 }
4015 4020 cmd->cmd_flags = CFLAG_FREE;
4016 4021 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd);
4017 4022 }
4018 4023
4019 4024 /*
4020 4025 * tran_sync_pkt(9E) - explicit DMA synchronization
4021 4026 */
4022 4027 /*ARGSUSED*/
4023 4028 static void
4024 4029 mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
4025 4030 {
4026 4031 mptsas_cmd_t *cmd = PKT2CMD(pkt);
4027 4032
4028 4033 NDBG3(("mptsas_scsi_sync_pkt: target=%d, pkt=0x%p",
4029 4034 ap->a_target, (void *)pkt));
4030 4035
4031 4036 if (cmd->cmd_dmahandle) {
4032 4037 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
4033 4038 (cmd->cmd_flags & CFLAG_DMASEND) ?
4034 4039 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU);
4035 4040 }
4036 4041 }
4037 4042
4038 4043 /*
4039 4044 * tran_dmafree(9E) - deallocate DMA resources allocated for command
4040 4045 */
4041 4046 /*ARGSUSED*/
4042 4047 static void
4043 4048 mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt)
4044 4049 {
4045 4050 mptsas_cmd_t *cmd = PKT2CMD(pkt);
4046 4051 mptsas_t *mpt = ADDR2MPT(ap);
4047 4052
4048 4053 NDBG3(("mptsas_scsi_dmafree: target=%d pkt=0x%p",
4049 4054 ap->a_target, (void *)pkt));
4050 4055
4051 4056 if (cmd->cmd_flags & CFLAG_DMAVALID) {
4052 4057 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle);
4053 4058 cmd->cmd_flags &= ~CFLAG_DMAVALID;
4054 4059 }
4055 4060
4056 4061 if (cmd->cmd_flags & CFLAG_EXTARQBUFVALID) {
4057 4062 (void) ddi_dma_unbind_handle(cmd->cmd_ext_arqhandle);
4058 4063 cmd->cmd_flags &= ~CFLAG_EXTARQBUFVALID;
4059 4064 }
4060 4065
4061 4066 mptsas_free_extra_sgl_frame(mpt, cmd);
4062 4067 }
4063 4068
4064 4069 static void
4065 4070 mptsas_pkt_comp(struct scsi_pkt *pkt, mptsas_cmd_t *cmd)
4066 4071 {
4067 4072 if ((cmd->cmd_flags & CFLAG_CMDIOPB) &&
4068 4073 (!(cmd->cmd_flags & CFLAG_DMASEND))) {
4069 4074 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
4070 4075 DDI_DMA_SYNC_FORCPU);
4071 4076 }
4072 4077 (*pkt->pkt_comp)(pkt);
4073 4078 }
4074 4079
4075 4080 static void
4076 4081 mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, uint32_t *control,
4077 4082 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl)
4078 4083 {
4079 4084 uint_t cookiec;
4080 4085 mptti_t *dmap;
4081 4086 uint32_t flags;
4082 4087 pMpi2SGESimple64_t sge;
4083 4088 pMpi2SGEChain64_t sgechain;
4084 4089 ASSERT(cmd->cmd_flags & CFLAG_DMAVALID);
4085 4090
4086 4091 /*
4087 4092 * Save the number of entries in the DMA
4088 4093 * Scatter/Gather list
4089 4094 */
4090 4095 cookiec = cmd->cmd_cookiec;
4091 4096
4092 4097 NDBG1(("mptsas_sge_setup: cookiec=%d", cookiec));
4093 4098
4094 4099 /*
4095 4100 * Set read/write bit in control.
4096 4101 */
4097 4102 if (cmd->cmd_flags & CFLAG_DMASEND) {
4098 4103 *control |= MPI2_SCSIIO_CONTROL_WRITE;
4099 4104 } else {
4100 4105 *control |= MPI2_SCSIIO_CONTROL_READ;
4101 4106 }
4102 4107
4103 4108 ddi_put32(acc_hdl, &frame->DataLength, cmd->cmd_dmacount);
4104 4109
4105 4110 /*
4106 4111 * We have 2 cases here. First where we can fit all the
4107 4112 * SG elements into the main frame, and the case
4108 4113 * where we can't.
4109 4114 * If we have more cookies than we can attach to a frame
4110 4115 * we will need to use a chain element to point
4111 4116 * a location of memory where the rest of the S/G
4112 4117 * elements reside.
4113 4118 */
4114 4119 if (cookiec <= MPTSAS_MAX_FRAME_SGES64(mpt)) {
4115 4120 dmap = cmd->cmd_sg;
4116 4121 sge = (pMpi2SGESimple64_t)(&frame->SGL);
4117 4122 while (cookiec--) {
4118 4123 ddi_put32(acc_hdl,
4119 4124 &sge->Address.Low, dmap->addr.address64.Low);
4120 4125 ddi_put32(acc_hdl,
4121 4126 &sge->Address.High, dmap->addr.address64.High);
4122 4127 ddi_put32(acc_hdl, &sge->FlagsLength,
4123 4128 dmap->count);
4124 4129 flags = ddi_get32(acc_hdl, &sge->FlagsLength);
4125 4130 flags |= ((uint32_t)
4126 4131 (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4127 4132 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4128 4133 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4129 4134 MPI2_SGE_FLAGS_SHIFT);
4130 4135
4131 4136 /*
4132 4137 * If this is the last cookie, we set the flags
4133 4138 * to indicate so
4134 4139 */
4135 4140 if (cookiec == 0) {
4136 4141 flags |=
4137 4142 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT
4138 4143 | MPI2_SGE_FLAGS_END_OF_BUFFER
4139 4144 | MPI2_SGE_FLAGS_END_OF_LIST) <<
4140 4145 MPI2_SGE_FLAGS_SHIFT);
4141 4146 }
4142 4147 if (cmd->cmd_flags & CFLAG_DMASEND) {
4143 4148 flags |= (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4144 4149 MPI2_SGE_FLAGS_SHIFT);
4145 4150 } else {
4146 4151 flags |= (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4147 4152 MPI2_SGE_FLAGS_SHIFT);
4148 4153 }
4149 4154 ddi_put32(acc_hdl, &sge->FlagsLength, flags);
4150 4155 dmap++;
4151 4156 sge++;
4152 4157 }
4153 4158 } else {
4154 4159 /*
4155 4160 * Hereby we start to deal with multiple frames.
4156 4161 * The process is as follows:
4157 4162 * 1. Determine how many frames are needed for SGL element
4158 4163 * storage; Note that all frames are stored in contiguous
4159 4164 * memory space and in 64-bit DMA mode each element is
4160 4165 * 3 double-words (12 bytes) long.
4161 4166 * 2. Fill up the main frame. We need to do this separately
4162 4167 * since it contains the SCSI IO request header and needs
4163 4168 * dedicated processing. Note that the last 4 double-words
4164 4169 * of the SCSI IO header is for SGL element storage
4165 4170 * (MPI2_SGE_IO_UNION).
4166 4171 * 3. Fill the chain element in the main frame, so the DMA
4167 4172 * engine can use the following frames.
4168 4173 * 4. Enter a loop to fill the remaining frames. Note that the
4169 4174 * last frame contains no chain element. The remaining
4170 4175 * frames go into the mpt SGL buffer allocated on the fly,
4171 4176 * not immediately following the main message frame, as in
4172 4177 * Gen1.
4173 4178 * Some restrictions:
4174 4179 * 1. For 64-bit DMA, the simple element and chain element
4175 4180 * are both of 3 double-words (12 bytes) in size, even
4176 4181 * though all frames are stored in the first 4G of mem
4177 4182 * range and the higher 32-bits of the address are always 0.
4178 4183 * 2. On some controllers (like the 1064/1068), a frame can
4179 4184 * hold SGL elements with the last 1 or 2 double-words
4180 4185 * (4 or 8 bytes) un-used. On these controllers, we should
4181 4186 * recognize that there's not enough room for another SGL
4182 4187 * element and move the sge pointer to the next frame.
4183 4188 */
4184 4189 int i, j, k, l, frames, sgemax;
4185 4190 int temp;
4186 4191 uint8_t chainflags;
4187 4192 uint16_t chainlength;
4188 4193 mptsas_cache_frames_t *p;
4189 4194
4190 4195 /*
4191 4196 * Sgemax is the number of SGE's that will fit
4192 4197 * each extra frame and frames is total
4193 4198 * number of frames we'll need. 1 sge entry per
4194 4199 * frame is reseverd for the chain element thus the -1 below.
4195 4200 */
4196 4201 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_SGE_SIMPLE64))
4197 4202 - 1);
4198 4203 temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax;
4199 4204
4200 4205 /*
4201 4206 * A little check to see if we need to round up the number
4202 4207 * of frames we need
4203 4208 */
4204 4209 if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp *
4205 4210 sgemax) > 1) {
4206 4211 frames = (temp + 1);
4207 4212 } else {
4208 4213 frames = temp;
4209 4214 }
4210 4215 dmap = cmd->cmd_sg;
4211 4216 sge = (pMpi2SGESimple64_t)(&frame->SGL);
4212 4217
4213 4218 /*
4214 4219 * First fill in the main frame
4215 4220 */
4216 4221 for (j = 1; j < MPTSAS_MAX_FRAME_SGES64(mpt); j++) {
4217 4222 ddi_put32(acc_hdl, &sge->Address.Low,
4218 4223 dmap->addr.address64.Low);
4219 4224 ddi_put32(acc_hdl, &sge->Address.High,
4220 4225 dmap->addr.address64.High);
4221 4226 ddi_put32(acc_hdl, &sge->FlagsLength, dmap->count);
4222 4227 flags = ddi_get32(acc_hdl, &sge->FlagsLength);
4223 4228 flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4224 4229 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4225 4230 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4226 4231 MPI2_SGE_FLAGS_SHIFT);
4227 4232
4228 4233 /*
4229 4234 * If this is the last SGE of this frame
4230 4235 * we set the end of list flag
4231 4236 */
4232 4237 if (j == (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) {
4233 4238 flags |= ((uint32_t)
4234 4239 (MPI2_SGE_FLAGS_LAST_ELEMENT) <<
4235 4240 MPI2_SGE_FLAGS_SHIFT);
4236 4241 }
4237 4242 if (cmd->cmd_flags & CFLAG_DMASEND) {
4238 4243 flags |=
4239 4244 (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4240 4245 MPI2_SGE_FLAGS_SHIFT);
4241 4246 } else {
4242 4247 flags |=
4243 4248 (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4244 4249 MPI2_SGE_FLAGS_SHIFT);
4245 4250 }
4246 4251 ddi_put32(acc_hdl, &sge->FlagsLength, flags);
4247 4252 dmap++;
4248 4253 sge++;
4249 4254 }
4250 4255
4251 4256 /*
4252 4257 * Fill in the chain element in the main frame.
4253 4258 * About calculation on ChainOffset:
4254 4259 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes)
4255 4260 * in the end reserved for SGL element storage
4256 4261 * (MPI2_SGE_IO_UNION); we should count it in our
4257 4262 * calculation. See its definition in the header file.
4258 4263 * 2. Constant j is the counter of the current SGL element
4259 4264 * that will be processed, and (j - 1) is the number of
4260 4265 * SGL elements that have been processed (stored in the
4261 4266 * main frame).
4262 4267 * 3. ChainOffset value should be in units of double-words (4
4263 4268 * bytes) so the last value should be divided by 4.
4264 4269 */
4265 4270 ddi_put8(acc_hdl, &frame->ChainOffset,
4266 4271 (sizeof (MPI2_SCSI_IO_REQUEST) -
4267 4272 sizeof (MPI2_SGE_IO_UNION) +
4268 4273 (j - 1) * sizeof (MPI2_SGE_SIMPLE64)) >> 2);
4269 4274 sgechain = (pMpi2SGEChain64_t)sge;
4270 4275 chainflags = (MPI2_SGE_FLAGS_CHAIN_ELEMENT |
4271 4276 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4272 4277 MPI2_SGE_FLAGS_64_BIT_ADDRESSING);
4273 4278 ddi_put8(acc_hdl, &sgechain->Flags, chainflags);
4274 4279
4275 4280 /*
4276 4281 * The size of the next frame is the accurate size of space
4277 4282 * (in bytes) used to store the SGL elements. j is the counter
4278 4283 * of SGL elements. (j - 1) is the number of SGL elements that
4279 4284 * have been processed (stored in frames).
4280 4285 */
4281 4286 if (frames >= 2) {
4282 4287 chainlength = mpt->m_req_frame_size /
4283 4288 sizeof (MPI2_SGE_SIMPLE64) *
4284 4289 sizeof (MPI2_SGE_SIMPLE64);
4285 4290 } else {
4286 4291 chainlength = ((cookiec - (j - 1)) *
4287 4292 sizeof (MPI2_SGE_SIMPLE64));
4288 4293 }
4289 4294
4290 4295 p = cmd->cmd_extra_frames;
4291 4296
4292 4297 ddi_put16(acc_hdl, &sgechain->Length, chainlength);
4293 4298 ddi_put32(acc_hdl, &sgechain->Address.Low,
4294 4299 p->m_phys_addr);
4295 4300 /* SGL is allocated in the first 4G mem range */
4296 4301 ddi_put32(acc_hdl, &sgechain->Address.High, 0);
4297 4302
4298 4303 /*
4299 4304 * If there are more than 2 frames left we have to
4300 4305 * fill in the next chain offset to the location of
4301 4306 * the chain element in the next frame.
4302 4307 * sgemax is the number of simple elements in an extra
4303 4308 * frame. Note that the value NextChainOffset should be
4304 4309 * in double-words (4 bytes).
4305 4310 */
4306 4311 if (frames >= 2) {
4307 4312 ddi_put8(acc_hdl, &sgechain->NextChainOffset,
4308 4313 (sgemax * sizeof (MPI2_SGE_SIMPLE64)) >> 2);
4309 4314 } else {
4310 4315 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 0);
4311 4316 }
4312 4317
4313 4318 /*
4314 4319 * Jump to next frame;
4315 4320 * Starting here, chain buffers go into the per command SGL.
4316 4321 * This buffer is allocated when chain buffers are needed.
4317 4322 */
4318 4323 sge = (pMpi2SGESimple64_t)p->m_frames_addr;
4319 4324 i = cookiec;
4320 4325
4321 4326 /*
4322 4327 * Start filling in frames with SGE's. If we
4323 4328 * reach the end of frame and still have SGE's
4324 4329 * to fill we need to add a chain element and
4325 4330 * use another frame. j will be our counter
4326 4331 * for what cookie we are at and i will be
4327 4332 * the total cookiec. k is the current frame
4328 4333 */
4329 4334 for (k = 1; k <= frames; k++) {
4330 4335 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) {
4331 4336
4332 4337 /*
4333 4338 * If we have reached the end of frame
4334 4339 * and we have more SGE's to fill in
4335 4340 * we have to fill the final entry
4336 4341 * with a chain element and then
4337 4342 * continue to the next frame
4338 4343 */
4339 4344 if ((l == (sgemax + 1)) && (k != frames)) {
4340 4345 sgechain = (pMpi2SGEChain64_t)sge;
4341 4346 j--;
4342 4347 chainflags = (
4343 4348 MPI2_SGE_FLAGS_CHAIN_ELEMENT |
4344 4349 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4345 4350 MPI2_SGE_FLAGS_64_BIT_ADDRESSING);
4346 4351 ddi_put8(p->m_acc_hdl,
4347 4352 &sgechain->Flags, chainflags);
4348 4353 /*
4349 4354 * k is the frame counter and (k + 1)
4350 4355 * is the number of the next frame.
4351 4356 * Note that frames are in contiguous
4352 4357 * memory space.
4353 4358 */
4354 4359 ddi_put32(p->m_acc_hdl,
4355 4360 &sgechain->Address.Low,
4356 4361 (p->m_phys_addr +
4357 4362 (mpt->m_req_frame_size * k)));
4358 4363 ddi_put32(p->m_acc_hdl,
4359 4364 &sgechain->Address.High, 0);
4360 4365
4361 4366 /*
4362 4367 * If there are more than 2 frames left
4363 4368 * we have to next chain offset to
4364 4369 * the location of the chain element
4365 4370 * in the next frame and fill in the
4366 4371 * length of the next chain
4367 4372 */
4368 4373 if ((frames - k) >= 2) {
4369 4374 ddi_put8(p->m_acc_hdl,
4370 4375 &sgechain->NextChainOffset,
4371 4376 (sgemax *
4372 4377 sizeof (MPI2_SGE_SIMPLE64))
4373 4378 >> 2);
4374 4379 ddi_put16(p->m_acc_hdl,
4375 4380 &sgechain->Length,
4376 4381 mpt->m_req_frame_size /
4377 4382 sizeof (MPI2_SGE_SIMPLE64) *
4378 4383 sizeof (MPI2_SGE_SIMPLE64));
4379 4384 } else {
4380 4385 /*
4381 4386 * This is the last frame. Set
4382 4387 * the NextChainOffset to 0 and
4383 4388 * Length is the total size of
4384 4389 * all remaining simple elements
4385 4390 */
4386 4391 ddi_put8(p->m_acc_hdl,
4387 4392 &sgechain->NextChainOffset,
4388 4393 0);
4389 4394 ddi_put16(p->m_acc_hdl,
4390 4395 &sgechain->Length,
4391 4396 (cookiec - j) *
4392 4397 sizeof (MPI2_SGE_SIMPLE64));
4393 4398 }
4394 4399
4395 4400 /* Jump to the next frame */
4396 4401 sge = (pMpi2SGESimple64_t)
4397 4402 ((char *)p->m_frames_addr +
4398 4403 (int)mpt->m_req_frame_size * k);
4399 4404
4400 4405 continue;
4401 4406 }
4402 4407
4403 4408 ddi_put32(p->m_acc_hdl,
4404 4409 &sge->Address.Low,
4405 4410 dmap->addr.address64.Low);
4406 4411 ddi_put32(p->m_acc_hdl,
4407 4412 &sge->Address.High,
4408 4413 dmap->addr.address64.High);
4409 4414 ddi_put32(p->m_acc_hdl,
4410 4415 &sge->FlagsLength, dmap->count);
4411 4416 flags = ddi_get32(p->m_acc_hdl,
4412 4417 &sge->FlagsLength);
4413 4418 flags |= ((uint32_t)(
4414 4419 MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4415 4420 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4416 4421 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4417 4422 MPI2_SGE_FLAGS_SHIFT);
4418 4423
4419 4424 /*
4420 4425 * If we are at the end of the frame and
4421 4426 * there is another frame to fill in
4422 4427 * we set the last simple element as last
4423 4428 * element
4424 4429 */
4425 4430 if ((l == sgemax) && (k != frames)) {
4426 4431 flags |= ((uint32_t)
4427 4432 (MPI2_SGE_FLAGS_LAST_ELEMENT) <<
4428 4433 MPI2_SGE_FLAGS_SHIFT);
4429 4434 }
4430 4435
4431 4436 /*
4432 4437 * If this is the final cookie we
4433 4438 * indicate it by setting the flags
4434 4439 */
4435 4440 if (j == i) {
4436 4441 flags |= ((uint32_t)
4437 4442 (MPI2_SGE_FLAGS_LAST_ELEMENT |
4438 4443 MPI2_SGE_FLAGS_END_OF_BUFFER |
4439 4444 MPI2_SGE_FLAGS_END_OF_LIST) <<
4440 4445 MPI2_SGE_FLAGS_SHIFT);
4441 4446 }
4442 4447 if (cmd->cmd_flags & CFLAG_DMASEND) {
4443 4448 flags |=
4444 4449 (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4445 4450 MPI2_SGE_FLAGS_SHIFT);
4446 4451 } else {
4447 4452 flags |=
4448 4453 (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4449 4454 MPI2_SGE_FLAGS_SHIFT);
4450 4455 }
4451 4456 ddi_put32(p->m_acc_hdl,
4452 4457 &sge->FlagsLength, flags);
4453 4458 dmap++;
4454 4459 sge++;
4455 4460 }
4456 4461 }
4457 4462
4458 4463 /*
4459 4464 * Sync DMA with the chain buffers that were just created
4460 4465 */
4461 4466 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
4462 4467 }
4463 4468 }
4464 4469
4465 4470 /*
4466 4471 * Interrupt handling
4467 4472 * Utility routine. Poll for status of a command sent to HBA
4468 4473 * without interrupts (a FLAG_NOINTR command).
4469 4474 */
4470 4475 int
4471 4476 mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime)
4472 4477 {
4473 4478 int rval = TRUE;
4474 4479
4475 4480 NDBG5(("mptsas_poll: cmd=0x%p", (void *)poll_cmd));
4476 4481
4477 4482 /*
4478 4483 * In order to avoid using m_mutex in ISR(a new separate mutex
4479 4484 * m_intr_mutex is introduced) and keep the same lock logic,
4480 4485 * the m_intr_mutex should be used to protect the getting and
4481 4486 * setting of the ReplyDescriptorIndex.
4482 4487 *
4483 4488 * Since the m_intr_mutex would be released during processing the poll
4484 4489 * cmd, so we should set the poll flag earlier here to make sure the
4485 4490 * polled cmd be handled in this thread/context. A side effect is other
4486 4491 * cmds during the period between the flag set and reset are also
4487 4492 * handled in this thread and not the ISR. Since the poll cmd is not
4488 4493 * so common, so the performance degradation in this case is not a big
4489 4494 * issue.
4490 4495 */
4491 4496 mutex_enter(&mpt->m_intr_mutex);
4492 4497 mpt->m_polled_intr = 1;
4493 4498 mutex_exit(&mpt->m_intr_mutex);
4494 4499
4495 4500 if ((poll_cmd->cmd_flags & CFLAG_TM_CMD) == 0) {
4496 4501 mptsas_restart_hba(mpt);
4497 4502 }
4498 4503
4499 4504 /*
4500 4505 * Wait, using drv_usecwait(), long enough for the command to
4501 4506 * reasonably return from the target if the target isn't
4502 4507 * "dead". A polled command may well be sent from scsi_poll, and
4503 4508 * there are retries built in to scsi_poll if the transport
4504 4509 * accepted the packet (TRAN_ACCEPT). scsi_poll waits 1 second
4505 4510 * and retries the transport up to scsi_poll_busycnt times
4506 4511 * (currently 60) if
4507 4512 * 1. pkt_reason is CMD_INCOMPLETE and pkt_state is 0, or
4508 4513 * 2. pkt_reason is CMD_CMPLT and *pkt_scbp has STATUS_BUSY
4509 4514 *
4510 4515 * limit the waiting to avoid a hang in the event that the
4511 4516 * cmd never gets started but we are still receiving interrupts
4512 4517 */
4513 4518 while (!(poll_cmd->cmd_flags & CFLAG_FINISHED)) {
4514 4519 if (mptsas_wait_intr(mpt, polltime) == FALSE) {
4515 4520 NDBG5(("mptsas_poll: command incomplete"));
4516 4521 rval = FALSE;
4517 4522 break;
4518 4523 }
4519 4524 }
4520 4525
4521 4526 mutex_enter(&mpt->m_intr_mutex);
4522 4527 mpt->m_polled_intr = 0;
4523 4528 mutex_exit(&mpt->m_intr_mutex);
4524 4529
4525 4530 if (rval == FALSE) {
4526 4531
4527 4532 /*
4528 4533 * this isn't supposed to happen, the hba must be wedged
4529 4534 * Mark this cmd as a timeout.
4530 4535 */
4531 4536 mptsas_set_pkt_reason(mpt, poll_cmd, CMD_TIMEOUT,
4532 4537 (STAT_TIMEOUT|STAT_ABORTED));
4533 4538
4534 4539 if (poll_cmd->cmd_queued == FALSE) {
4535 4540
4536 4541 NDBG5(("mptsas_poll: not on waitq"));
4537 4542
4538 4543 poll_cmd->cmd_pkt->pkt_state |=
4539 4544 (STATE_GOT_BUS|STATE_GOT_TARGET|STATE_SENT_CMD);
4540 4545 } else {
4541 4546
4542 4547 /* find and remove it from the waitq */
4543 4548 NDBG5(("mptsas_poll: delete from waitq"));
4544 4549 mptsas_waitq_delete(mpt, poll_cmd);
4545 4550 }
4546 4551
4547 4552 }
4548 4553 mptsas_fma_check(mpt, poll_cmd);
4549 4554 NDBG5(("mptsas_poll: done"));
4550 4555 return (rval);
4551 4556 }
4552 4557
4553 4558 /*
4554 4559 * Used for polling cmds and TM function
4555 4560 */
4556 4561 static int
4557 4562 mptsas_wait_intr(mptsas_t *mpt, int polltime)
4558 4563 {
4559 4564 int cnt;
4560 4565 pMpi2ReplyDescriptorsUnion_t reply_desc_union;
4561 4566 Mpi2ReplyDescriptorsUnion_t reply_desc_union_v;
4562 4567 uint32_t int_mask;
4563 4568 uint8_t reply_type;
4564 4569
4565 4570 NDBG5(("mptsas_wait_intr"));
4566 4571
4567 4572
4568 4573 /*
4569 4574 * Get the current interrupt mask and disable interrupts. When
4570 4575 * re-enabling ints, set mask to saved value.
4571 4576 */
4572 4577 int_mask = ddi_get32(mpt->m_datap, &mpt->m_reg->HostInterruptMask);
4573 4578 MPTSAS_DISABLE_INTR(mpt);
4574 4579
4575 4580 /*
4576 4581 * Keep polling for at least (polltime * 1000) seconds
4577 4582 */
4578 4583 for (cnt = 0; cnt < polltime; cnt++) {
4579 4584 mutex_enter(&mpt->m_intr_mutex);
4580 4585 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
4581 4586 DDI_DMA_SYNC_FORCPU);
4582 4587
4583 4588 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t)
4584 4589 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index);
4585 4590
4586 4591 if (ddi_get32(mpt->m_acc_post_queue_hdl,
4587 4592 &reply_desc_union->Words.Low) == 0xFFFFFFFF ||
4588 4593 ddi_get32(mpt->m_acc_post_queue_hdl,
4589 4594 &reply_desc_union->Words.High) == 0xFFFFFFFF) {
4590 4595 mutex_exit(&mpt->m_intr_mutex);
4591 4596 drv_usecwait(1000);
4592 4597 continue;
4593 4598 }
4594 4599
4595 4600 reply_type = ddi_get8(mpt->m_acc_post_queue_hdl,
4596 4601 &reply_desc_union->Default.ReplyFlags);
4597 4602 reply_type &= MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
4598 4603 reply_desc_union_v.Default.ReplyFlags = reply_type;
4599 4604 if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
4600 4605 reply_desc_union_v.SCSIIOSuccess.SMID =
4601 4606 ddi_get16(mpt->m_acc_post_queue_hdl,
4602 4607 &reply_desc_union->SCSIIOSuccess.SMID);
4603 4608 } else if (reply_type ==
4604 4609 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
4605 4610 reply_desc_union_v.AddressReply.ReplyFrameAddress =
4606 4611 ddi_get32(mpt->m_acc_post_queue_hdl,
4607 4612 &reply_desc_union->AddressReply.ReplyFrameAddress);
4608 4613 reply_desc_union_v.AddressReply.SMID =
4609 4614 ddi_get16(mpt->m_acc_post_queue_hdl,
4610 4615 &reply_desc_union->AddressReply.SMID);
4611 4616 }
4612 4617 /*
4613 4618 * Clear the reply descriptor for re-use and increment
4614 4619 * index.
4615 4620 */
4616 4621 ddi_put64(mpt->m_acc_post_queue_hdl,
4617 4622 &((uint64_t *)(void *)mpt->m_post_queue)[mpt->m_post_index],
4618 4623 0xFFFFFFFFFFFFFFFF);
4619 4624 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
4620 4625 DDI_DMA_SYNC_FORDEV);
4621 4626
4622 4627 if (++mpt->m_post_index == mpt->m_post_queue_depth) {
4623 4628 mpt->m_post_index = 0;
4624 4629 }
4625 4630
4626 4631 /*
4627 4632 * Update the global reply index
4628 4633 */
4629 4634 ddi_put32(mpt->m_datap,
4630 4635 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index);
4631 4636 mutex_exit(&mpt->m_intr_mutex);
4632 4637
4633 4638 /*
4634 4639 * The reply is valid, process it according to its
4635 4640 * type.
4636 4641 */
4637 4642 mptsas_process_intr(mpt, &reply_desc_union_v);
4638 4643
4639 4644
4640 4645 /*
4641 4646 * Re-enable interrupts and quit.
4642 4647 */
4643 4648 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask,
4644 4649 int_mask);
4645 4650 return (TRUE);
4646 4651
4647 4652 }
4648 4653
4649 4654 /*
4650 4655 * Clear polling flag, re-enable interrupts and quit.
4651 4656 */
4652 4657 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, int_mask);
4653 4658 return (FALSE);
4654 4659 }
4655 4660
4656 4661 /*
4657 4662 * For fastpath, the m_intr_mutex should be held from the begining to the end,
4658 4663 * so we only treat those cmds that need not release m_intr_mutex(even just for
4659 4664 * a moment) as candidate for fast processing. otherwise, we don't handle them
4660 4665 * and just return, then in ISR, those cmds would be handled later with m_mutex
4661 4666 * held and m_intr_mutex not held.
4662 4667 */
4663 4668 static int
4664 4669 mptsas_handle_io_fastpath(mptsas_t *mpt,
4665 4670 uint16_t SMID)
4666 4671 {
4667 4672 mptsas_slots_t *slots = mpt->m_active;
4668 4673 mptsas_cmd_t *cmd = NULL;
4669 4674 struct scsi_pkt *pkt;
4670 4675
4671 4676 /*
4672 4677 * This is a success reply so just complete the IO. First, do a sanity
4673 4678 * check on the SMID. The final slot is used for TM requests, which
4674 4679 * would not come into this reply handler.
4675 4680 */
4676 4681 if ((SMID == 0) || (SMID > slots->m_n_slots)) {
4677 4682 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of %d\n",
4678 4683 SMID);
4679 4684 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
4680 4685 return (TRUE);
4681 4686 }
4682 4687
4683 4688 cmd = slots->m_slot[SMID];
4684 4689
4685 4690 /*
4686 4691 * print warning and return if the slot is empty
4687 4692 */
4688 4693 if (cmd == NULL) {
4689 4694 mptsas_log(mpt, CE_WARN, "?NULL command for successful SCSI IO "
4690 4695 "in slot %d", SMID);
4691 4696 return (TRUE);
4692 4697 }
4693 4698
4694 4699 pkt = CMD2PKT(cmd);
4695 4700 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | STATE_SENT_CMD |
4696 4701 STATE_GOT_STATUS);
4697 4702 if (cmd->cmd_flags & CFLAG_DMAVALID) {
4698 4703 pkt->pkt_state |= STATE_XFERRED_DATA;
4699 4704 }
4700 4705 pkt->pkt_resid = 0;
4701 4706
4702 4707 /*
4703 4708 * If the cmd is a IOC, or a passthrough, then we don't process it in
4704 4709 * fastpath, and later it would be handled by mptsas_process_intr()
4705 4710 * with m_mutex protected.
4706 4711 */
4707 4712 if (cmd->cmd_flags & (CFLAG_PASSTHRU | CFLAG_CMDIOC)) {
4708 4713 return (FALSE);
4709 4714 } else {
4710 4715 mptsas_remove_cmd0(mpt, cmd);
4711 4716 }
4712 4717
4713 4718 if (cmd->cmd_flags & CFLAG_RETRY) {
4714 4719 /*
4715 4720 * The target returned QFULL or busy, do not add tihs
4716 4721 * pkt to the doneq since the hba will retry
4717 4722 * this cmd.
4718 4723 *
4719 4724 * The pkt has already been resubmitted in
4720 4725 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error().
4721 4726 * Remove this cmd_flag here.
4722 4727 */
4723 4728 cmd->cmd_flags &= ~CFLAG_RETRY;
4724 4729 } else {
4725 4730 mptsas_doneq_add0(mpt, cmd);
4726 4731 }
4727 4732
4728 4733 /*
4729 4734 * In fastpath, the cmd should only be a context reply, so just check
4730 4735 * the post queue of the reply descriptor and the dmahandle of the cmd
4731 4736 * is enough. No sense data in this case and no need to check the dma
4732 4737 * handle where sense data dma info is saved, the dma handle of the
4733 4738 * reply frame, and the dma handle of the reply free queue.
4734 4739 * For the dma handle of the request queue. Check fma here since we
4735 4740 * are sure the request must have already been sent/DMAed correctly.
4736 4741 * otherwise checking in mptsas_scsi_start() is not correct since
4737 4742 * at that time the dma may not start.
4738 4743 */
4739 4744 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
4740 4745 DDI_SUCCESS) ||
4741 4746 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) !=
4742 4747 DDI_SUCCESS)) {
4743 4748 ddi_fm_service_impact(mpt->m_dip,
4744 4749 DDI_SERVICE_UNAFFECTED);
4745 4750 pkt->pkt_reason = CMD_TRAN_ERR;
4746 4751 pkt->pkt_statistics = 0;
4747 4752 }
4748 4753 if (cmd->cmd_dmahandle &&
4749 4754 (mptsas_check_dma_handle(cmd->cmd_dmahandle) != DDI_SUCCESS)) {
4750 4755 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
4751 4756 pkt->pkt_reason = CMD_TRAN_ERR;
4752 4757 pkt->pkt_statistics = 0;
4753 4758 }
4754 4759 if ((cmd->cmd_extra_frames &&
4755 4760 ((mptsas_check_dma_handle(cmd->cmd_extra_frames->m_dma_hdl) !=
4756 4761 DDI_SUCCESS) ||
4757 4762 (mptsas_check_acc_handle(cmd->cmd_extra_frames->m_acc_hdl) !=
4758 4763 DDI_SUCCESS)))) {
4759 4764 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
4760 4765 pkt->pkt_reason = CMD_TRAN_ERR;
4761 4766 pkt->pkt_statistics = 0;
4762 4767 }
4763 4768
4764 4769 return (TRUE);
4765 4770 }
4766 4771
4767 4772 static void
4768 4773 mptsas_handle_scsi_io_success(mptsas_t *mpt,
4769 4774 pMpi2ReplyDescriptorsUnion_t reply_desc)
4770 4775 {
4771 4776 pMpi2SCSIIOSuccessReplyDescriptor_t scsi_io_success;
4772 4777 uint16_t SMID;
4773 4778 mptsas_slots_t *slots = mpt->m_active;
4774 4779 mptsas_cmd_t *cmd = NULL;
4775 4780 struct scsi_pkt *pkt;
4776 4781
4777 4782 scsi_io_success = (pMpi2SCSIIOSuccessReplyDescriptor_t)reply_desc;
4778 4783 SMID = scsi_io_success->SMID;
4779 4784
4780 4785 /*
4781 4786 * This is a success reply so just complete the IO. First, do a sanity
4782 4787 * check on the SMID. The final slot is used for TM requests, which
4783 4788 * would not come into this reply handler.
4784 4789 */
4785 4790 if ((SMID == 0) || (SMID > slots->m_n_slots)) {
4786 4791 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of %d\n",
4787 4792 SMID);
4788 4793 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
4789 4794 return;
4790 4795 }
4791 4796
4792 4797 cmd = slots->m_slot[SMID];
4793 4798
4794 4799 /*
4795 4800 * print warning and return if the slot is empty
4796 4801 */
4797 4802 if (cmd == NULL) {
4798 4803 mptsas_log(mpt, CE_WARN, "?NULL command for successful SCSI IO "
4799 4804 "in slot %d", SMID);
4800 4805 return;
4801 4806 }
4802 4807
4803 4808 pkt = CMD2PKT(cmd);
4804 4809 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | STATE_SENT_CMD |
4805 4810 STATE_GOT_STATUS);
4806 4811 if (cmd->cmd_flags & CFLAG_DMAVALID) {
4807 4812 pkt->pkt_state |= STATE_XFERRED_DATA;
4808 4813 }
4809 4814 pkt->pkt_resid = 0;
4810 4815
4811 4816 if (cmd->cmd_flags & CFLAG_PASSTHRU) {
4812 4817 cmd->cmd_flags |= CFLAG_FINISHED;
4813 4818 cv_broadcast(&mpt->m_passthru_cv);
4814 4819 return;
4815 4820 } else {
4816 4821 mptsas_remove_cmd(mpt, cmd);
4817 4822 }
4818 4823
4819 4824 if (cmd->cmd_flags & CFLAG_RETRY) {
4820 4825 /*
4821 4826 * The target returned QFULL or busy, do not add tihs
4822 4827 * pkt to the doneq since the hba will retry
4823 4828 * this cmd.
4824 4829 *
4825 4830 * The pkt has already been resubmitted in
4826 4831 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error().
4827 4832 * Remove this cmd_flag here.
4828 4833 */
4829 4834 cmd->cmd_flags &= ~CFLAG_RETRY;
4830 4835 } else {
4831 4836 mptsas_doneq_add(mpt, cmd);
4832 4837 }
4833 4838 }
4834 4839
4835 4840 static void
4836 4841 mptsas_handle_address_reply(mptsas_t *mpt,
4837 4842 pMpi2ReplyDescriptorsUnion_t reply_desc)
4838 4843 {
4839 4844 pMpi2AddressReplyDescriptor_t address_reply;
4840 4845 pMPI2DefaultReply_t reply;
4841 4846 mptsas_fw_diagnostic_buffer_t *pBuffer;
4842 4847 uint32_t reply_addr;
4843 4848 uint16_t SMID, iocstatus;
4844 4849 mptsas_slots_t *slots = mpt->m_active;
4845 4850 mptsas_cmd_t *cmd = NULL;
4846 4851 uint8_t function, buffer_type;
4847 4852 m_replyh_arg_t *args;
4848 4853 int reply_frame_no;
4849 4854
4850 4855 ASSERT(mutex_owned(&mpt->m_mutex));
4851 4856
4852 4857 address_reply = (pMpi2AddressReplyDescriptor_t)reply_desc;
4853 4858
4854 4859 reply_addr = address_reply->ReplyFrameAddress;
4855 4860 SMID = address_reply->SMID;
4856 4861 /*
4857 4862 * If reply frame is not in the proper range we should ignore this
4858 4863 * message and exit the interrupt handler.
4859 4864 */
4860 4865 if ((reply_addr < mpt->m_reply_frame_dma_addr) ||
4861 4866 (reply_addr >= (mpt->m_reply_frame_dma_addr +
4862 4867 (mpt->m_reply_frame_size * mpt->m_max_replies))) ||
4863 4868 ((reply_addr - mpt->m_reply_frame_dma_addr) %
4864 4869 mpt->m_reply_frame_size != 0)) {
4865 4870 mptsas_log(mpt, CE_WARN, "?Received invalid reply frame "
4866 4871 "address 0x%x\n", reply_addr);
4867 4872 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
4868 4873 return;
4869 4874 }
4870 4875
4871 4876 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
4872 4877 DDI_DMA_SYNC_FORCPU);
4873 4878 reply = (pMPI2DefaultReply_t)(mpt->m_reply_frame + (reply_addr -
4874 4879 mpt->m_reply_frame_dma_addr));
4875 4880 function = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->Function);
4876 4881
4877 4882 /*
4878 4883 * don't get slot information and command for events since these values
4879 4884 * don't exist
4880 4885 */
4881 4886 if ((function != MPI2_FUNCTION_EVENT_NOTIFICATION) &&
4882 4887 (function != MPI2_FUNCTION_DIAG_BUFFER_POST)) {
4883 4888 /*
4884 4889 * This could be a TM reply, which use the last allocated SMID,
4885 4890 * so allow for that.
4886 4891 */
4887 4892 if ((SMID == 0) || (SMID > (slots->m_n_slots + 1))) {
4888 4893 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of "
4889 4894 "%d\n", SMID);
4890 4895 ddi_fm_service_impact(mpt->m_dip,
4891 4896 DDI_SERVICE_UNAFFECTED);
4892 4897 return;
4893 4898 }
4894 4899
4895 4900 cmd = slots->m_slot[SMID];
4896 4901
4897 4902 /*
4898 4903 * print warning and return if the slot is empty
4899 4904 */
4900 4905 if (cmd == NULL) {
4901 4906 mptsas_log(mpt, CE_WARN, "?NULL command for address "
4902 4907 "reply in slot %d", SMID);
4903 4908 return;
4904 4909 }
4905 4910 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
4906 4911 (cmd->cmd_flags & CFLAG_CONFIG) ||
4907 4912 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
4908 4913 cmd->cmd_rfm = reply_addr;
4909 4914 cmd->cmd_flags |= CFLAG_FINISHED;
4910 4915 cv_broadcast(&mpt->m_passthru_cv);
4911 4916 cv_broadcast(&mpt->m_config_cv);
4912 4917 cv_broadcast(&mpt->m_fw_diag_cv);
4913 4918 return;
4914 4919 } else if (!(cmd->cmd_flags & CFLAG_FW_CMD)) {
4915 4920 mptsas_remove_cmd(mpt, cmd);
4916 4921 }
4917 4922 NDBG31(("\t\tmptsas_process_intr: slot=%d", SMID));
4918 4923 }
4919 4924 /*
4920 4925 * Depending on the function, we need to handle
4921 4926 * the reply frame (and cmd) differently.
4922 4927 */
4923 4928 switch (function) {
4924 4929 case MPI2_FUNCTION_SCSI_IO_REQUEST:
4925 4930 mptsas_check_scsi_io_error(mpt, (pMpi2SCSIIOReply_t)reply, cmd);
4926 4931 break;
4927 4932 case MPI2_FUNCTION_SCSI_TASK_MGMT:
4928 4933 cmd->cmd_rfm = reply_addr;
4929 4934 mptsas_check_task_mgt(mpt, (pMpi2SCSIManagementReply_t)reply,
4930 4935 cmd);
4931 4936 break;
4932 4937 case MPI2_FUNCTION_FW_DOWNLOAD:
4933 4938 cmd->cmd_flags |= CFLAG_FINISHED;
4934 4939 cv_signal(&mpt->m_fw_cv);
4935 4940 break;
4936 4941 case MPI2_FUNCTION_EVENT_NOTIFICATION:
4937 4942 reply_frame_no = (reply_addr - mpt->m_reply_frame_dma_addr) /
4938 4943 mpt->m_reply_frame_size;
4939 4944 args = &mpt->m_replyh_args[reply_frame_no];
4940 4945 args->mpt = (void *)mpt;
4941 4946 args->rfm = reply_addr;
4942 4947
4943 4948 /*
4944 4949 * Record the event if its type is enabled in
4945 4950 * this mpt instance by ioctl.
4946 4951 */
4947 4952 mptsas_record_event(args);
4948 4953
4949 4954 /*
4950 4955 * Handle time critical events
4951 4956 * NOT_RESPONDING/ADDED only now
4952 4957 */
4953 4958 if (mptsas_handle_event_sync(args) == DDI_SUCCESS) {
4954 4959 /*
4955 4960 * Would not return main process,
4956 4961 * just let taskq resolve ack action
4957 4962 * and ack would be sent in taskq thread
4958 4963 */
4959 4964 NDBG20(("send mptsas_handle_event_sync success"));
4960 4965 }
4961 4966 if ((ddi_taskq_dispatch(mpt->m_event_taskq, mptsas_handle_event,
4962 4967 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) {
4963 4968 mptsas_log(mpt, CE_WARN, "No memory available"
4964 4969 "for dispatch taskq");
4965 4970 /*
4966 4971 * Return the reply frame to the free queue.
4967 4972 */
4968 4973 ddi_put32(mpt->m_acc_free_queue_hdl,
4969 4974 &((uint32_t *)(void *)
4970 4975 mpt->m_free_queue)[mpt->m_free_index], reply_addr);
4971 4976 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
4972 4977 DDI_DMA_SYNC_FORDEV);
4973 4978 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
4974 4979 mpt->m_free_index = 0;
4975 4980 }
4976 4981
4977 4982 ddi_put32(mpt->m_datap,
4978 4983 &mpt->m_reg->ReplyFreeHostIndex, mpt->m_free_index);
4979 4984 }
4980 4985 return;
4981 4986 case MPI2_FUNCTION_DIAG_BUFFER_POST:
4982 4987 /*
4983 4988 * If SMID is 0, this implies that the reply is due to a
4984 4989 * release function with a status that the buffer has been
4985 4990 * released. Set the buffer flags accordingly.
4986 4991 */
4987 4992 if (SMID == 0) {
4988 4993 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
4989 4994 &reply->IOCStatus);
4990 4995 buffer_type = ddi_get8(mpt->m_acc_reply_frame_hdl,
4991 4996 &(((pMpi2DiagBufferPostReply_t)reply)->BufferType));
4992 4997 if (iocstatus == MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED) {
4993 4998 pBuffer =
4994 4999 &mpt->m_fw_diag_buffer_list[buffer_type];
4995 5000 pBuffer->valid_data = TRUE;
4996 5001 pBuffer->owned_by_firmware = FALSE;
4997 5002 pBuffer->immediate = FALSE;
4998 5003 }
4999 5004 } else {
5000 5005 /*
5001 5006 * Normal handling of diag post reply with SMID.
5002 5007 */
5003 5008 cmd = slots->m_slot[SMID];
5004 5009
5005 5010 /*
5006 5011 * print warning and return if the slot is empty
5007 5012 */
5008 5013 if (cmd == NULL) {
5009 5014 mptsas_log(mpt, CE_WARN, "?NULL command for "
5010 5015 "address reply in slot %d", SMID);
5011 5016 return;
5012 5017 }
5013 5018 cmd->cmd_rfm = reply_addr;
5014 5019 cmd->cmd_flags |= CFLAG_FINISHED;
5015 5020 cv_broadcast(&mpt->m_fw_diag_cv);
5016 5021 }
5017 5022 return;
5018 5023 default:
5019 5024 mptsas_log(mpt, CE_WARN, "Unknown function 0x%x ", function);
5020 5025 break;
5021 5026 }
5022 5027
5023 5028 /*
5024 5029 * Return the reply frame to the free queue.
5025 5030 */
5026 5031 ddi_put32(mpt->m_acc_free_queue_hdl,
5027 5032 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
5028 5033 reply_addr);
5029 5034 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
5030 5035 DDI_DMA_SYNC_FORDEV);
5031 5036 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
5032 5037 mpt->m_free_index = 0;
5033 5038 }
5034 5039 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
5035 5040 mpt->m_free_index);
5036 5041
5037 5042 if (cmd->cmd_flags & CFLAG_FW_CMD)
5038 5043 return;
5039 5044
5040 5045 if (cmd->cmd_flags & CFLAG_RETRY) {
5041 5046 /*
5042 5047 * The target returned QFULL or busy, do not add tihs
5043 5048 * pkt to the doneq since the hba will retry
5044 5049 * this cmd.
5045 5050 *
5046 5051 * The pkt has already been resubmitted in
5047 5052 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error().
5048 5053 * Remove this cmd_flag here.
5049 5054 */
5050 5055 cmd->cmd_flags &= ~CFLAG_RETRY;
5051 5056 } else {
5052 5057 mptsas_doneq_add(mpt, cmd);
5053 5058 }
5054 5059 }
5055 5060
5056 5061 static void
5057 5062 mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply,
5058 5063 mptsas_cmd_t *cmd)
5059 5064 {
5060 5065 uint8_t scsi_status, scsi_state;
5061 5066 uint16_t ioc_status;
5062 5067 uint32_t xferred, sensecount, responsedata, loginfo = 0;
5063 5068 struct scsi_pkt *pkt;
5064 5069 struct scsi_arq_status *arqstat;
5065 5070 struct buf *bp;
5066 5071 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
5067 5072 uint8_t *sensedata = NULL;
5068 5073
5069 5074 if ((cmd->cmd_flags & (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) ==
5070 5075 (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) {
5071 5076 bp = cmd->cmd_ext_arq_buf;
5072 5077 } else {
5073 5078 bp = cmd->cmd_arq_buf;
5074 5079 }
5075 5080
5076 5081 scsi_status = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIStatus);
5077 5082 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus);
5078 5083 scsi_state = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIState);
5079 5084 xferred = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->TransferCount);
5080 5085 sensecount = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->SenseCount);
5081 5086 responsedata = ddi_get32(mpt->m_acc_reply_frame_hdl,
5082 5087 &reply->ResponseInfo);
5083 5088
5084 5089 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
5085 5090 loginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
5086 5091 &reply->IOCLogInfo);
5087 5092 mptsas_log(mpt, CE_NOTE,
5088 5093 "?Log info 0x%x received for target %d.\n"
5089 5094 "\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x",
5090 5095 loginfo, Tgt(cmd), scsi_status, ioc_status,
5091 5096 scsi_state);
5092 5097 }
5093 5098
5094 5099 NDBG31(("\t\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x",
5095 5100 scsi_status, ioc_status, scsi_state));
5096 5101
5097 5102 pkt = CMD2PKT(cmd);
5098 5103 *(pkt->pkt_scbp) = scsi_status;
5099 5104
5100 5105 if (loginfo == 0x31170000) {
5101 5106 /*
5102 5107 * if loginfo PL_LOGINFO_CODE_IO_DEVICE_MISSING_DELAY_RETRY
5103 5108 * 0x31170000 comes, that means the device missing delay
5104 5109 * is in progressing, the command need retry later.
5105 5110 */
5106 5111 *(pkt->pkt_scbp) = STATUS_BUSY;
5107 5112 return;
5108 5113 }
5109 5114
5110 5115 if ((scsi_state & MPI2_SCSI_STATE_NO_SCSI_STATUS) &&
5111 5116 ((ioc_status & MPI2_IOCSTATUS_MASK) ==
5112 5117 MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE)) {
5113 5118 pkt->pkt_reason = CMD_INCOMPLETE;
5114 5119 pkt->pkt_state |= STATE_GOT_BUS;
5115 5120 mutex_enter(&ptgt->m_tgt_intr_mutex);
5116 5121 if (ptgt->m_reset_delay == 0) {
5117 5122 mptsas_set_throttle(mpt, ptgt,
5118 5123 DRAIN_THROTTLE);
5119 5124 }
5120 5125 mutex_exit(&ptgt->m_tgt_intr_mutex);
5121 5126 return;
5122 5127 }
5123 5128
5124 5129 if (scsi_state & MPI2_SCSI_STATE_RESPONSE_INFO_VALID) {
5125 5130 responsedata &= 0x000000FF;
5126 5131 if (responsedata & MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF) {
5127 5132 mptsas_log(mpt, CE_NOTE, "Do not support the TLR\n");
5128 5133 pkt->pkt_reason = CMD_TLR_OFF;
5129 5134 return;
5130 5135 }
5131 5136 }
5132 5137
5133 5138
5134 5139 switch (scsi_status) {
5135 5140 case MPI2_SCSI_STATUS_CHECK_CONDITION:
5136 5141 pkt->pkt_resid = (cmd->cmd_dmacount - xferred);
5137 5142 arqstat = (void*)(pkt->pkt_scbp);
5138 5143 arqstat->sts_rqpkt_status = *((struct scsi_status *)
5139 5144 (pkt->pkt_scbp));
5140 5145 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET |
5141 5146 STATE_SENT_CMD | STATE_GOT_STATUS | STATE_ARQ_DONE);
5142 5147 if (cmd->cmd_flags & CFLAG_XARQ) {
5143 5148 pkt->pkt_state |= STATE_XARQ_DONE;
5144 5149 }
5145 5150 if (pkt->pkt_resid != cmd->cmd_dmacount) {
5146 5151 pkt->pkt_state |= STATE_XFERRED_DATA;
5147 5152 }
5148 5153 arqstat->sts_rqpkt_reason = pkt->pkt_reason;
5149 5154 arqstat->sts_rqpkt_state = pkt->pkt_state;
5150 5155 arqstat->sts_rqpkt_state |= STATE_XFERRED_DATA;
5151 5156 arqstat->sts_rqpkt_statistics = pkt->pkt_statistics;
5152 5157 sensedata = (uint8_t *)&arqstat->sts_sensedata;
5153 5158
5154 5159 bcopy((uchar_t *)bp->b_un.b_addr, sensedata,
5155 5160 ((cmd->cmd_rqslen >= sensecount) ? sensecount :
5156 5161 cmd->cmd_rqslen));
5157 5162 arqstat->sts_rqpkt_resid = (cmd->cmd_rqslen - sensecount);
5158 5163 cmd->cmd_flags |= CFLAG_CMDARQ;
5159 5164 /*
5160 5165 * Set proper status for pkt if autosense was valid
5161 5166 */
5162 5167 if (scsi_state & MPI2_SCSI_STATE_AUTOSENSE_VALID) {
5163 5168 struct scsi_status zero_status = { 0 };
5164 5169 arqstat->sts_rqpkt_status = zero_status;
5165 5170 }
5166 5171
5167 5172 /*
5168 5173 * ASC=0x47 is parity error
5169 5174 * ASC=0x48 is initiator detected error received
5170 5175 */
5171 5176 if ((scsi_sense_key(sensedata) == KEY_ABORTED_COMMAND) &&
5172 5177 ((scsi_sense_asc(sensedata) == 0x47) ||
5173 5178 (scsi_sense_asc(sensedata) == 0x48))) {
5174 5179 mptsas_log(mpt, CE_NOTE, "Aborted_command!");
5175 5180 }
5176 5181
5177 5182 /*
5178 5183 * ASC/ASCQ=0x3F/0x0E means report_luns data changed
5179 5184 * ASC/ASCQ=0x25/0x00 means invalid lun
5180 5185 */
5181 5186 if (((scsi_sense_key(sensedata) == KEY_UNIT_ATTENTION) &&
5182 5187 (scsi_sense_asc(sensedata) == 0x3F) &&
5183 5188 (scsi_sense_ascq(sensedata) == 0x0E)) ||
5184 5189 ((scsi_sense_key(sensedata) == KEY_ILLEGAL_REQUEST) &&
5185 5190 (scsi_sense_asc(sensedata) == 0x25) &&
5186 5191 (scsi_sense_ascq(sensedata) == 0x00))) {
5187 5192 mptsas_topo_change_list_t *topo_node = NULL;
5188 5193
5189 5194 topo_node = kmem_zalloc(
5190 5195 sizeof (mptsas_topo_change_list_t),
5191 5196 KM_NOSLEEP);
5192 5197 if (topo_node == NULL) {
5193 5198 mptsas_log(mpt, CE_NOTE, "No memory"
5194 5199 "resource for handle SAS dynamic"
5195 5200 "reconfigure.\n");
5196 5201 break;
5197 5202 }
5198 5203 topo_node->mpt = mpt;
5199 5204 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_TARGET;
5200 5205 topo_node->un.phymask = ptgt->m_phymask;
5201 5206 topo_node->devhdl = ptgt->m_devhdl;
5202 5207 topo_node->object = (void *)ptgt;
5203 5208 topo_node->flags = MPTSAS_TOPO_FLAG_LUN_ASSOCIATED;
5204 5209
5205 5210 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
5206 5211 mptsas_handle_dr,
5207 5212 (void *)topo_node,
5208 5213 DDI_NOSLEEP)) != DDI_SUCCESS) {
5209 5214 mptsas_log(mpt, CE_NOTE, "mptsas start taskq"
5210 5215 "for handle SAS dynamic reconfigure"
5211 5216 "failed. \n");
5212 5217 }
5213 5218 }
5214 5219 break;
5215 5220 case MPI2_SCSI_STATUS_GOOD:
5216 5221 switch (ioc_status & MPI2_IOCSTATUS_MASK) {
5217 5222 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
5218 5223 pkt->pkt_reason = CMD_DEV_GONE;
5219 5224 pkt->pkt_state |= STATE_GOT_BUS;
5220 5225 mutex_enter(&ptgt->m_tgt_intr_mutex);
5221 5226 if (ptgt->m_reset_delay == 0) {
5222 5227 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5223 5228 }
5224 5229 mutex_exit(&ptgt->m_tgt_intr_mutex);
5225 5230 NDBG31(("lost disk for target%d, command:%x",
5226 5231 Tgt(cmd), pkt->pkt_cdbp[0]));
5227 5232 break;
5228 5233 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
5229 5234 NDBG31(("data overrun: xferred=%d", xferred));
5230 5235 NDBG31(("dmacount=%d", cmd->cmd_dmacount));
5231 5236 pkt->pkt_reason = CMD_DATA_OVR;
5232 5237 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET
5233 5238 | STATE_SENT_CMD | STATE_GOT_STATUS
5234 5239 | STATE_XFERRED_DATA);
5235 5240 pkt->pkt_resid = 0;
5236 5241 break;
5237 5242 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
5238 5243 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
5239 5244 NDBG31(("data underrun: xferred=%d", xferred));
5240 5245 NDBG31(("dmacount=%d", cmd->cmd_dmacount));
5241 5246 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET
5242 5247 | STATE_SENT_CMD | STATE_GOT_STATUS);
5243 5248 pkt->pkt_resid = (cmd->cmd_dmacount - xferred);
5244 5249 if (pkt->pkt_resid != cmd->cmd_dmacount) {
5245 5250 pkt->pkt_state |= STATE_XFERRED_DATA;
5246 5251 }
5247 5252 break;
5248 5253 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
5249 5254 mptsas_set_pkt_reason(mpt,
5250 5255 cmd, CMD_RESET, STAT_BUS_RESET);
5251 5256 break;
5252 5257 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
5253 5258 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
5254 5259 mptsas_set_pkt_reason(mpt,
5255 5260 cmd, CMD_RESET, STAT_DEV_RESET);
5256 5261 break;
5257 5262 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
5258 5263 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
5259 5264 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET);
5260 5265 mptsas_set_pkt_reason(mpt,
5261 5266 cmd, CMD_TERMINATED, STAT_TERMINATED);
5262 5267 break;
5263 5268 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
5264 5269 case MPI2_IOCSTATUS_BUSY:
5265 5270 /*
5266 5271 * set throttles to drain
5267 5272 */
5268 5273 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
5269 5274 &mpt->m_active->m_tgttbl, MPTSAS_HASH_FIRST);
5270 5275 while (ptgt != NULL) {
5271 5276 mutex_enter(&ptgt->m_tgt_intr_mutex);
5272 5277 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5273 5278 mutex_exit(&ptgt->m_tgt_intr_mutex);
5274 5279
5275 5280 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
5276 5281 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
5277 5282 }
5278 5283
5279 5284 /*
5280 5285 * retry command
5281 5286 */
5282 5287 cmd->cmd_flags |= CFLAG_RETRY;
5283 5288 cmd->cmd_pkt_flags |= FLAG_HEAD;
5284 5289
5285 5290 mutex_exit(&mpt->m_mutex);
5286 5291 (void) mptsas_accept_pkt(mpt, cmd);
5287 5292 mutex_enter(&mpt->m_mutex);
5288 5293 break;
5289 5294 default:
5290 5295 mptsas_log(mpt, CE_WARN,
5291 5296 "unknown ioc_status = %x\n", ioc_status);
5292 5297 mptsas_log(mpt, CE_CONT, "scsi_state = %x, transfer "
5293 5298 "count = %x, scsi_status = %x", scsi_state,
5294 5299 xferred, scsi_status);
5295 5300 break;
5296 5301 }
5297 5302 break;
5298 5303 case MPI2_SCSI_STATUS_TASK_SET_FULL:
5299 5304 mptsas_handle_qfull(mpt, cmd);
5300 5305 break;
5301 5306 case MPI2_SCSI_STATUS_BUSY:
5302 5307 NDBG31(("scsi_status busy received"));
5303 5308 break;
5304 5309 case MPI2_SCSI_STATUS_RESERVATION_CONFLICT:
5305 5310 NDBG31(("scsi_status reservation conflict received"));
5306 5311 break;
5307 5312 default:
5308 5313 mptsas_log(mpt, CE_WARN, "scsi_status=%x, ioc_status=%x\n",
5309 5314 scsi_status, ioc_status);
5310 5315 mptsas_log(mpt, CE_WARN,
5311 5316 "mptsas_process_intr: invalid scsi status\n");
5312 5317 break;
5313 5318 }
5314 5319 }
5315 5320
5316 5321 static void
5317 5322 mptsas_check_task_mgt(mptsas_t *mpt, pMpi2SCSIManagementReply_t reply,
5318 5323 mptsas_cmd_t *cmd)
5319 5324 {
5320 5325 uint8_t task_type;
5321 5326 uint16_t ioc_status;
5322 5327 uint32_t log_info;
5323 5328 uint16_t dev_handle;
5324 5329 struct scsi_pkt *pkt = CMD2PKT(cmd);
5325 5330
5326 5331 task_type = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->TaskType);
5327 5332 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus);
5328 5333 log_info = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->IOCLogInfo);
5329 5334 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->DevHandle);
5330 5335
5331 5336 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5332 5337 mptsas_log(mpt, CE_WARN, "mptsas_check_task_mgt: Task 0x%x "
5333 5338 "failed. IOCStatus=0x%x IOCLogInfo=0x%x target=%d\n",
5334 5339 task_type, ioc_status, log_info, dev_handle);
5335 5340 pkt->pkt_reason = CMD_INCOMPLETE;
5336 5341 return;
5337 5342 }
5338 5343
5339 5344 switch (task_type) {
5340 5345 case MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK:
5341 5346 case MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET:
5342 5347 case MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK:
5343 5348 case MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA:
5344 5349 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET:
5345 5350 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_UNIT_ATTENTION:
5346 5351 break;
5347 5352 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
5348 5353 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
5349 5354 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
5350 5355 /*
5351 5356 * Check for invalid DevHandle of 0 in case application
5352 5357 * sends bad command. DevHandle of 0 could cause problems.
5353 5358 */
5354 5359 if (dev_handle == 0) {
5355 5360 mptsas_log(mpt, CE_WARN, "!Can't flush target with"
5356 5361 " DevHandle of 0.");
5357 5362 } else {
5358 5363 mptsas_flush_target(mpt, dev_handle, Lun(cmd),
5359 5364 task_type);
5360 5365 }
5361 5366 break;
5362 5367 default:
5363 5368 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.",
5364 5369 task_type);
5365 5370 mptsas_log(mpt, CE_WARN, "ioc status = %x", ioc_status);
5366 5371 break;
5367 5372 }
5368 5373 }
5369 5374
5370 5375 static void
5371 5376 mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg)
5372 5377 {
5373 5378 mptsas_t *mpt = arg->mpt;
5374 5379 uint64_t t = arg->t;
5375 5380 mptsas_cmd_t *cmd;
5376 5381 struct scsi_pkt *pkt;
5377 5382 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
5378 5383
5379 5384 mutex_enter(&item->mutex);
5380 5385 while (item->flag & MPTSAS_DONEQ_THREAD_ACTIVE) {
5381 5386 if (!item->doneq) {
5382 5387 cv_wait(&item->cv, &item->mutex);
5383 5388 }
5384 5389 pkt = NULL;
5385 5390 if ((cmd = mptsas_doneq_thread_rm(mpt, t)) != NULL) {
5386 5391 cmd->cmd_flags |= CFLAG_COMPLETED;
5387 5392 pkt = CMD2PKT(cmd);
5388 5393 }
5389 5394 mutex_exit(&item->mutex);
5390 5395 if (pkt) {
5391 5396 mptsas_pkt_comp(pkt, cmd);
5392 5397 }
5393 5398 mutex_enter(&item->mutex);
5394 5399 }
5395 5400 mutex_exit(&item->mutex);
5396 5401 mutex_enter(&mpt->m_doneq_mutex);
5397 5402 mpt->m_doneq_thread_n--;
5398 5403 cv_broadcast(&mpt->m_doneq_thread_cv);
5399 5404 mutex_exit(&mpt->m_doneq_mutex);
5400 5405 }
5401 5406
5402 5407 /*
5403 5408 * mpt interrupt handler.
5404 5409 */
5405 5410 static uint_t
5406 5411 mptsas_intr(caddr_t arg1, caddr_t arg2)
5407 5412 {
5408 5413 mptsas_t *mpt = (void *)arg1;
5409 5414 pMpi2ReplyDescriptorsUnion_t reply_desc_union;
5410 5415 uchar_t did_reply = FALSE;
5411 5416 int i = 0, j;
5412 5417 uint8_t reply_type;
5413 5418 uint16_t SMID;
5414 5419
5415 5420 NDBG1(("mptsas_intr: arg1 0x%p arg2 0x%p", (void *)arg1, (void *)arg2));
5416 5421
5417 5422 /*
5418 5423 * 1.
5419 5424 * To avoid using m_mutex in the ISR(ISR referes not only mptsas_intr,
5420 5425 * but all of the recursive called functions in it. the same below),
5421 5426 * separate mutexs are introduced to protect the elements shown in ISR.
5422 5427 * 3 type of mutex are involved here:
5423 5428 * a)per instance mutex m_intr_mutex.
5424 5429 * b)per target mutex m_tgt_intr_mutex.
5425 5430 * c)mutex that protect the free slot.
5426 5431 *
5427 5432 * a)per instance mutex m_intr_mutex:
5428 5433 * used to protect m_options, m_power, m_waitq, etc that would be
5429 5434 * checked/modified in ISR; protect the getting and setting the reply
5430 5435 * descriptor index; protect the m_slots[];
5431 5436 *
5432 5437 * b)per target mutex m_tgt_intr_mutex:
5433 5438 * used to protect per target element which has relationship to ISR.
5434 5439 * contention for the new per target mutex is just as high as it in
5435 5440 * sd(7d) driver.
5436 5441 *
5437 5442 * c)mutexs that protect the free slots:
5438 5443 * those mutexs are introduced to minimize the mutex contentions
5439 5444 * between the IO request threads where free slots are allocated
5440 5445 * for sending cmds and ISR where slots holding outstanding cmds
5441 5446 * are returned to the free pool.
5442 5447 * the idea is like this:
5443 5448 * 1) Partition all of the free slot into NCPU groups. For example,
5444 5449 * In system where we have 15 slots, and 4 CPU, then slot s1,s5,s9,s13
5445 5450 * are marked belonging to CPU1, s2,s6,s10,s14 to CPU2, s3,s7,s11,s15
5446 5451 * to CPU3, and s4,s8,s12 to CPU4.
5447 5452 * 2) In each of the group, an alloc/release queue pair is created,
5448 5453 * and both the allocq and the releaseq have a dedicated mutex.
5449 5454 * 3) When init, all of the slots in a CPU group are inserted into the
5450 5455 * allocq of its CPU's pair.
5451 5456 * 4) When doing IO,
5452 5457 * mptsas_scsi_start()
5453 5458 * {
5454 5459 * cpuid = the cpu NO of the cpu where this thread is running on
5455 5460 * retry:
5456 5461 * mutex_enter(&allocq[cpuid]);
5457 5462 * if (get free slot = success) {
5458 5463 * remove the slot from the allocq
5459 5464 * mutex_exit(&allocq[cpuid]);
5460 5465 * return(success);
5461 5466 * } else { // exchange allocq and releaseq and try again
5462 5467 * mutex_enter(&releq[cpuid]);
5463 5468 * exchange the allocq and releaseq of this pair;
5464 5469 * mutex_exit(&releq[cpuid]);
5465 5470 * if (try to get free slot again = success) {
5466 5471 * remove the slot from the allocq
5467 5472 * mutex_exit(&allocq[cpuid]);
5468 5473 * return(success);
5469 5474 * } else {
5470 5475 * MOD(cpuid)++;
5471 5476 * goto retry;
5472 5477 * if (all CPU groups tried)
5473 5478 * mutex_exit(&allocq[cpuid]);
5474 5479 * return(failure);
5475 5480 * }
5476 5481 * }
5477 5482 * }
5478 5483 * ISR()
5479 5484 * {
5480 5485 * cpuid = the CPU group id where the slot sending the
5481 5486 * cmd belongs;
5482 5487 * mutex_enter(&releq[cpuid]);
5483 5488 * remove the slot from the releaseq
5484 5489 * mutex_exit(&releq[cpuid]);
5485 5490 * }
5486 5491 * This way, only when the queue pair doing exchange have mutex
5487 5492 * contentions.
5488 5493 *
5489 5494 * For mutex m_intr_mutex and m_tgt_intr_mutex, there are 2 scenarios:
5490 5495 *
5491 5496 * a)If the elements are only checked but not modified in the ISR, then
5492 5497 * only the places where those elements are modifed(outside of ISR)
5493 5498 * need to be protected by the new introduced mutex.
5494 5499 * For example, data A is only read/checked in ISR, then we need do
5495 5500 * like this:
5496 5501 * In ISR:
5497 5502 * {
5498 5503 * mutex_enter(&new_mutex);
5499 5504 * read(A);
5500 5505 * mutex_exit(&new_mutex);
5501 5506 * //the new_mutex here is either the m_tgt_intr_mutex or
5502 5507 * //the m_intr_mutex.
5503 5508 * }
5504 5509 * In non-ISR
5505 5510 * {
5506 5511 * mutex_enter(&m_mutex); //the stock driver already did this
5507 5512 * mutex_enter(&new_mutex);
5508 5513 * write(A);
5509 5514 * mutex_exit(&new_mutex);
5510 5515 * mutex_exit(&m_mutex); //the stock driver already did this
5511 5516 *
5512 5517 * read(A);
5513 5518 * // read(A) in non-ISR is not required to be protected by new
5514 5519 * // mutex since 'A' has already been protected by m_mutex
5515 5520 * // outside of the ISR
5516 5521 * }
5517 5522 *
5518 5523 * Those fields in mptsas_target_t/ptgt which are only read in ISR
5519 5524 * fall into this catergory. So they, together with the fields which
5520 5525 * are never read in ISR, are not necessary to be protected by
5521 5526 * m_tgt_intr_mutex, don't bother.
5522 5527 * checking of m_waitq also falls into this catergory. so all of the
5523 5528 * place outside of ISR where the m_waitq is modified, such as in
5524 5529 * mptsas_waitq_add(), mptsas_waitq_delete(), mptsas_waitq_rm(),
5525 5530 * m_intr_mutex should be used.
5526 5531 *
5527 5532 * b)If the elements are modified in the ISR, then each place where
5528 5533 * those elements are referred(outside of ISR) need to be protected
5529 5534 * by the new introduced mutex. Of course, if those elements only
5530 5535 * appear in the non-key code path, that is, they don't affect
5531 5536 * performance, then the m_mutex can still be used as before.
5532 5537 * For example, data B is modified in key code path in ISR, and data C
5533 5538 * is modified in non-key code path in ISR, then we can do like this:
5534 5539 * In ISR:
5535 5540 * {
5536 5541 * mutex_enter(&new_mutex);
5537 5542 * wirte(B);
5538 5543 * mutex_exit(&new_mutex);
5539 5544 * if (seldom happen) {
5540 5545 * mutex_enter(&m_mutex);
5541 5546 * write(C);
5542 5547 * mutex_exit(&m_mutex);
5543 5548 * }
5544 5549 * //the new_mutex here is either the m_tgt_intr_mutex or
5545 5550 * //the m_intr_mutex.
5546 5551 * }
5547 5552 * In non-ISR
5548 5553 * {
5549 5554 * mutex_enter(&new_mutex);
5550 5555 * write(B);
5551 5556 * mutex_exit(&new_mutex);
5552 5557 *
5553 5558 * mutex_enter(&new_mutex);
5554 5559 * read(B);
5555 5560 * mutex_exit(&new_mutex);
5556 5561 * // both write(B) and read(B) in non-ISR is required to be
5557 5562 * // protected by new mutex outside of the ISR
5558 5563 *
5559 5564 * mutex_enter(&m_mutex); //the stock driver already did this
5560 5565 * read(C);
5561 5566 * write(C);
5562 5567 * mutex_exit(&m_mutex); //the stock driver already did this
5563 5568 * // both write(C) and read(C) in non-ISR have been already
5564 5569 * // been protected by m_mutex outside of the ISR
5565 5570 * }
5566 5571 *
5567 5572 * For example, ptgt->m_t_ncmds fall into 'B' of this catergory, and
5568 5573 * elements shown in address reply, restart_hba, passthrough, IOC
5569 5574 * fall into 'C' of this catergory.
5570 5575 *
5571 5576 * In any case where mutexs are nested, make sure in the following
5572 5577 * order:
5573 5578 * m_mutex -> m_intr_mutex -> m_tgt_intr_mutex
5574 5579 * m_intr_mutex -> m_tgt_intr_mutex
5575 5580 * m_mutex -> m_intr_mutex
5576 5581 * m_mutex -> m_tgt_intr_mutex
5577 5582 *
5578 5583 * 2.
5579 5584 * Make sure at any time, getting the ReplyDescriptor by m_post_index
5580 5585 * and setting m_post_index to the ReplyDescriptorIndex register are
5581 5586 * atomic. Since m_mutex is not used for this purpose in ISR, the new
5582 5587 * mutex m_intr_mutex must play this role. So mptsas_poll(), where this
5583 5588 * kind of getting/setting is also performed, must use m_intr_mutex.
5584 5589 * Note, since context reply in ISR/process_intr is the only code path
5585 5590 * which affect performance, a fast path is introduced to only handle
5586 5591 * the read/write IO having context reply. For other IOs such as
5587 5592 * passthrough and IOC with context reply and all address reply, we
5588 5593 * use the as-is process_intr() to handle them. In order to keep the
5589 5594 * same semantics in process_intr(), make sure any new mutex is not held
5590 5595 * before enterring it.
5591 5596 */
5592 5597
5593 5598 mutex_enter(&mpt->m_intr_mutex);
5594 5599
5595 5600 /*
5596 5601 * If interrupts are shared by two channels then check whether this
5597 5602 * interrupt is genuinely for this channel by making sure first the
5598 5603 * chip is in high power state.
5599 5604 */
5600 5605 if ((mpt->m_options & MPTSAS_OPT_PM) &&
5601 5606 (mpt->m_power_level != PM_LEVEL_D0)) {
5602 5607 mutex_exit(&mpt->m_intr_mutex);
5603 5608 return (DDI_INTR_UNCLAIMED);
5604 5609 }
5605 5610
5606 5611 /*
5607 5612 * If polling, interrupt was triggered by some shared interrupt because
5608 5613 * IOC interrupts are disabled during polling, so polling routine will
5609 5614 * handle any replies. Considering this, if polling is happening,
5610 5615 * return with interrupt unclaimed.
5611 5616 */
5612 5617 if (mpt->m_polled_intr) {
5613 5618 mutex_exit(&mpt->m_intr_mutex);
5614 5619 mptsas_log(mpt, CE_WARN, "mpt_sas: Unclaimed interrupt");
5615 5620 return (DDI_INTR_UNCLAIMED);
5616 5621 }
5617 5622
5618 5623 /*
5619 5624 * Read the istat register.
5620 5625 */
5621 5626 if ((INTPENDING(mpt)) != 0) {
5622 5627 /*
5623 5628 * read fifo until empty.
5624 5629 */
5625 5630 #ifndef __lock_lint
5626 5631 _NOTE(CONSTCOND)
5627 5632 #endif
5628 5633 while (TRUE) {
5629 5634 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
5630 5635 DDI_DMA_SYNC_FORCPU);
5631 5636 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t)
5632 5637 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index);
5633 5638
5634 5639 if (ddi_get32(mpt->m_acc_post_queue_hdl,
5635 5640 &reply_desc_union->Words.Low) == 0xFFFFFFFF ||
5636 5641 ddi_get32(mpt->m_acc_post_queue_hdl,
5637 5642 &reply_desc_union->Words.High) == 0xFFFFFFFF) {
5638 5643 break;
5639 5644 }
5640 5645
5641 5646 /*
5642 5647 * The reply is valid, process it according to its
5643 5648 * type. Also, set a flag for updating the reply index
5644 5649 * after they've all been processed.
5645 5650 */
5646 5651 did_reply = TRUE;
5647 5652
5648 5653 reply_type = ddi_get8(mpt->m_acc_post_queue_hdl,
5649 5654 &reply_desc_union->Default.ReplyFlags);
5650 5655 reply_type &= MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
5651 5656 mpt->m_reply[i].Default.ReplyFlags = reply_type;
5652 5657 if (reply_type ==
5653 5658 MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
5654 5659 SMID = ddi_get16(mpt->m_acc_post_queue_hdl,
5655 5660 &reply_desc_union->SCSIIOSuccess.SMID);
5656 5661 if (mptsas_handle_io_fastpath(mpt, SMID) !=
5657 5662 TRUE) {
5658 5663 mpt->m_reply[i].SCSIIOSuccess.SMID =
5659 5664 SMID;
5660 5665 i++;
5661 5666 }
5662 5667 } else if (reply_type ==
5663 5668 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
5664 5669 mpt->m_reply[i].AddressReply.ReplyFrameAddress =
5665 5670 ddi_get32(mpt->m_acc_post_queue_hdl,
5666 5671 &reply_desc_union->AddressReply.
5667 5672 ReplyFrameAddress);
5668 5673 mpt->m_reply[i].AddressReply.SMID =
5669 5674 ddi_get16(mpt->m_acc_post_queue_hdl,
5670 5675 &reply_desc_union->AddressReply.SMID);
5671 5676 i++;
5672 5677 }
5673 5678 /*
5674 5679 * Clear the reply descriptor for re-use and increment
5675 5680 * index.
5676 5681 */
5677 5682 ddi_put64(mpt->m_acc_post_queue_hdl,
5678 5683 &((uint64_t *)(void *)mpt->m_post_queue)
5679 5684 [mpt->m_post_index], 0xFFFFFFFFFFFFFFFF);
5680 5685 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
5681 5686 DDI_DMA_SYNC_FORDEV);
5682 5687
5683 5688 /*
5684 5689 * Increment post index and roll over if needed.
5685 5690 */
5686 5691 if (++mpt->m_post_index == mpt->m_post_queue_depth) {
5687 5692 mpt->m_post_index = 0;
5688 5693 }
5689 5694 if (i >= MPI_ADDRESS_COALSCE_MAX)
5690 5695 break;
5691 5696 }
5692 5697
5693 5698 /*
5694 5699 * Update the global reply index if at least one reply was
5695 5700 * processed.
5696 5701 */
5697 5702 if (did_reply) {
5698 5703 ddi_put32(mpt->m_datap,
5699 5704 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index);
5700 5705
5701 5706 /*
5702 5707 * For fma, only check the PIO is required and enough
5703 5708 * here. Those cases where fastpath is not hit, the
5704 5709 * mptsas_fma_check() check all of the types of
5705 5710 * fma. That is not necessary and sometimes not
5706 5711 * correct. fma check should only be done after
5707 5712 * the PIO and/or dma is performed.
5708 5713 */
5709 5714 if ((mptsas_check_acc_handle(mpt->m_datap) !=
5710 5715 DDI_SUCCESS)) {
5711 5716 ddi_fm_service_impact(mpt->m_dip,
5712 5717 DDI_SERVICE_UNAFFECTED);
5713 5718 }
5714 5719
5715 5720 }
5716 5721 } else {
5717 5722 mutex_exit(&mpt->m_intr_mutex);
5718 5723 return (DDI_INTR_UNCLAIMED);
5719 5724 }
5720 5725 NDBG1(("mptsas_intr complete"));
5721 5726 mutex_exit(&mpt->m_intr_mutex);
5722 5727
5723 5728 /*
5724 5729 * Since most of the cmds(read and write IO with success return.)
5725 5730 * have already been processed in fast path in which the m_mutex
5726 5731 * is not held, handling here the address reply and other context reply
5727 5732 * such as passthrough and IOC cmd with m_mutex held should be a big
5728 5733 * issue for performance.
5729 5734 * If holding m_mutex to process these cmds was still an obvious issue,
5730 5735 * we can process them in a taskq.
5731 5736 */
5732 5737 for (j = 0; j < i; j++) {
5733 5738 mutex_enter(&mpt->m_mutex);
5734 5739 mptsas_process_intr(mpt, &mpt->m_reply[j]);
5735 5740 mutex_exit(&mpt->m_mutex);
5736 5741 }
5737 5742
5738 5743 /*
5739 5744 * If no helper threads are created, process the doneq in ISR. If
5740 5745 * helpers are created, use the doneq length as a metric to measure the
5741 5746 * load on the interrupt CPU. If it is long enough, which indicates the
5742 5747 * load is heavy, then we deliver the IO completions to the helpers.
5743 5748 * This measurement has some limitations, although it is simple and
5744 5749 * straightforward and works well for most of the cases at present.
5745 5750 */
5746 5751 if (!mpt->m_doneq_thread_n) {
5747 5752 mptsas_doneq_empty(mpt);
5748 5753 } else {
5749 5754 int helper = 1;
5750 5755 mutex_enter(&mpt->m_intr_mutex);
5751 5756 if (mpt->m_doneq_len <= mpt->m_doneq_length_threshold)
5752 5757 helper = 0;
5753 5758 mutex_exit(&mpt->m_intr_mutex);
5754 5759 if (helper) {
5755 5760 mptsas_deliver_doneq_thread(mpt);
5756 5761 } else {
5757 5762 mptsas_doneq_empty(mpt);
5758 5763 }
5759 5764 }
5760 5765
5761 5766 /*
5762 5767 * If there are queued cmd, start them now.
5763 5768 */
5764 5769 mutex_enter(&mpt->m_intr_mutex);
5765 5770 if (mpt->m_waitq != NULL) {
5766 5771 mutex_exit(&mpt->m_intr_mutex);
5767 5772 mutex_enter(&mpt->m_mutex);
5768 5773 mptsas_restart_hba(mpt);
5769 5774 mutex_exit(&mpt->m_mutex);
5770 5775 return (DDI_INTR_CLAIMED);
5771 5776 }
5772 5777 mutex_exit(&mpt->m_intr_mutex);
5773 5778 return (DDI_INTR_CLAIMED);
5774 5779 }
5775 5780
5776 5781 /*
5777 5782 * In ISR, the successfully completed read and write IO are processed in a
5778 5783 * fast path. This function is only used to handle non-fastpath IO, including
5779 5784 * all of the address reply, and the context reply for IOC cmd, passthrough,
5780 5785 * etc.
5781 5786 * This function is also used to process polled cmd.
5782 5787 */
5783 5788 static void
5784 5789 mptsas_process_intr(mptsas_t *mpt,
5785 5790 pMpi2ReplyDescriptorsUnion_t reply_desc_union)
5786 5791 {
5787 5792 uint8_t reply_type;
5788 5793
5789 5794 /*
5790 5795 * The reply is valid, process it according to its
5791 5796 * type. Also, set a flag for updated the reply index
5792 5797 * after they've all been processed.
5793 5798 */
5794 5799 reply_type = reply_desc_union->Default.ReplyFlags;
5795 5800 if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
5796 5801 mptsas_handle_scsi_io_success(mpt, reply_desc_union);
5797 5802 } else if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
5798 5803 mptsas_handle_address_reply(mpt, reply_desc_union);
5799 5804 } else {
5800 5805 mptsas_log(mpt, CE_WARN, "?Bad reply type %x", reply_type);
5801 5806 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
5802 5807 }
5803 5808 }
5804 5809
5805 5810 /*
5806 5811 * handle qfull condition
5807 5812 */
5808 5813 static void
5809 5814 mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd)
5810 5815 {
5811 5816 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
5812 5817
5813 5818 if ((++cmd->cmd_qfull_retries > ptgt->m_qfull_retries) ||
5814 5819 (ptgt->m_qfull_retries == 0)) {
5815 5820 /*
5816 5821 * We have exhausted the retries on QFULL, or,
5817 5822 * the target driver has indicated that it
5818 5823 * wants to handle QFULL itself by setting
5819 5824 * qfull-retries capability to 0. In either case
5820 5825 * we want the target driver's QFULL handling
5821 5826 * to kick in. We do this by having pkt_reason
5822 5827 * as CMD_CMPLT and pkt_scbp as STATUS_QFULL.
5823 5828 */
5824 5829 mutex_enter(&ptgt->m_tgt_intr_mutex);
5825 5830 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5826 5831 mutex_exit(&ptgt->m_tgt_intr_mutex);
5827 5832 } else {
5828 5833 mutex_enter(&ptgt->m_tgt_intr_mutex);
5829 5834 if (ptgt->m_reset_delay == 0) {
5830 5835 ptgt->m_t_throttle =
5831 5836 max((ptgt->m_t_ncmds - 2), 0);
5832 5837 }
5833 5838 mutex_exit(&ptgt->m_tgt_intr_mutex);
5834 5839
5835 5840 cmd->cmd_pkt_flags |= FLAG_HEAD;
5836 5841 cmd->cmd_flags &= ~(CFLAG_TRANFLAG);
5837 5842 cmd->cmd_flags |= CFLAG_RETRY;
5838 5843
5839 5844 mutex_exit(&mpt->m_mutex);
5840 5845 (void) mptsas_accept_pkt(mpt, cmd);
5841 5846 mutex_enter(&mpt->m_mutex);
5842 5847
5843 5848 /*
5844 5849 * when target gives queue full status with no commands
5845 5850 * outstanding (m_t_ncmds == 0), throttle is set to 0
5846 5851 * (HOLD_THROTTLE), and the queue full handling start
5847 5852 * (see psarc/1994/313); if there are commands outstanding,
5848 5853 * throttle is set to (m_t_ncmds - 2)
5849 5854 */
5850 5855 mutex_enter(&ptgt->m_tgt_intr_mutex);
5851 5856 if (ptgt->m_t_throttle == HOLD_THROTTLE) {
5852 5857 /*
5853 5858 * By setting throttle to QFULL_THROTTLE, we
5854 5859 * avoid submitting new commands and in
5855 5860 * mptsas_restart_cmd find out slots which need
5856 5861 * their throttles to be cleared.
5857 5862 */
5858 5863 mptsas_set_throttle(mpt, ptgt, QFULL_THROTTLE);
5859 5864 if (mpt->m_restart_cmd_timeid == 0) {
5860 5865 mpt->m_restart_cmd_timeid =
5861 5866 timeout(mptsas_restart_cmd, mpt,
5862 5867 ptgt->m_qfull_retry_interval);
5863 5868 }
5864 5869 }
5865 5870 mutex_exit(&ptgt->m_tgt_intr_mutex);
5866 5871 }
5867 5872 }
5868 5873
5869 5874 mptsas_phymask_t
5870 5875 mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport)
5871 5876 {
5872 5877 mptsas_phymask_t phy_mask = 0;
5873 5878 uint8_t i = 0;
5874 5879
5875 5880 NDBG20(("mptsas%d physport_to_phymask enter", mpt->m_instance));
5876 5881
5877 5882 ASSERT(mutex_owned(&mpt->m_mutex));
5878 5883
5879 5884 /*
5880 5885 * If physport is 0xFF, this is a RAID volume. Use phymask of 0.
5881 5886 */
5882 5887 if (physport == 0xFF) {
5883 5888 return (0);
5884 5889 }
5885 5890
5886 5891 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
5887 5892 if (mpt->m_phy_info[i].attached_devhdl &&
5888 5893 (mpt->m_phy_info[i].phy_mask != 0) &&
5889 5894 (mpt->m_phy_info[i].port_num == physport)) {
5890 5895 phy_mask = mpt->m_phy_info[i].phy_mask;
5891 5896 break;
5892 5897 }
5893 5898 }
5894 5899 NDBG20(("mptsas%d physport_to_phymask:physport :%x phymask :%x, ",
5895 5900 mpt->m_instance, physport, phy_mask));
5896 5901 return (phy_mask);
5897 5902 }
5898 5903
5899 5904 /*
5900 5905 * mpt free device handle after device gone, by use of passthrough
5901 5906 */
5902 5907 static int
5903 5908 mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl)
5904 5909 {
5905 5910 Mpi2SasIoUnitControlRequest_t req;
5906 5911 Mpi2SasIoUnitControlReply_t rep;
5907 5912 int ret;
5908 5913
5909 5914 ASSERT(mutex_owned(&mpt->m_mutex));
5910 5915
5911 5916 /*
5912 5917 * Need to compose a SAS IO Unit Control request message
5913 5918 * and call mptsas_do_passthru() function
5914 5919 */
5915 5920 bzero(&req, sizeof (req));
5916 5921 bzero(&rep, sizeof (rep));
5917 5922
5918 5923 req.Function = MPI2_FUNCTION_SAS_IO_UNIT_CONTROL;
5919 5924 req.Operation = MPI2_SAS_OP_REMOVE_DEVICE;
5920 5925 req.DevHandle = LE_16(devhdl);
5921 5926
5922 5927 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL,
5923 5928 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL);
5924 5929 if (ret != 0) {
5925 5930 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit "
5926 5931 "Control error %d", ret);
5927 5932 return (DDI_FAILURE);
5928 5933 }
5929 5934
5930 5935 /* do passthrough success, check the ioc status */
5931 5936 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
5932 5937 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit "
5933 5938 "Control IOCStatus %d", LE_16(rep.IOCStatus));
5934 5939 return (DDI_FAILURE);
5935 5940 }
5936 5941
5937 5942 return (DDI_SUCCESS);
5938 5943 }
5939 5944
5940 5945 static void
5941 5946 mptsas_update_phymask(mptsas_t *mpt)
5942 5947 {
5943 5948 mptsas_phymask_t mask = 0, phy_mask;
5944 5949 char *phy_mask_name;
5945 5950 uint8_t current_port;
5946 5951 int i, j;
5947 5952
5948 5953 NDBG20(("mptsas%d update phymask ", mpt->m_instance));
5949 5954
5950 5955 ASSERT(mutex_owned(&mpt->m_mutex));
5951 5956
5952 5957 (void) mptsas_get_sas_io_unit_page(mpt);
5953 5958
5954 5959 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
5955 5960
5956 5961 for (i = 0; i < mpt->m_num_phys; i++) {
5957 5962 phy_mask = 0x00;
5958 5963
5959 5964 if (mpt->m_phy_info[i].attached_devhdl == 0)
5960 5965 continue;
5961 5966
5962 5967 bzero(phy_mask_name, sizeof (phy_mask_name));
5963 5968
5964 5969 current_port = mpt->m_phy_info[i].port_num;
5965 5970
5966 5971 if ((mask & (1 << i)) != 0)
5967 5972 continue;
5968 5973
5969 5974 for (j = 0; j < mpt->m_num_phys; j++) {
5970 5975 if (mpt->m_phy_info[j].attached_devhdl &&
5971 5976 (mpt->m_phy_info[j].port_num == current_port)) {
5972 5977 phy_mask |= (1 << j);
5973 5978 }
5974 5979 }
5975 5980 mask = mask | phy_mask;
5976 5981
5977 5982 for (j = 0; j < mpt->m_num_phys; j++) {
5978 5983 if ((phy_mask >> j) & 0x01) {
5979 5984 mpt->m_phy_info[j].phy_mask = phy_mask;
5980 5985 }
5981 5986 }
5982 5987
5983 5988 (void) sprintf(phy_mask_name, "%x", phy_mask);
5984 5989
5985 5990 mutex_exit(&mpt->m_mutex);
5986 5991 /*
5987 5992 * register a iport, if the port has already been existed
5988 5993 * SCSA will do nothing and just return.
5989 5994 */
5990 5995 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name);
5991 5996 mutex_enter(&mpt->m_mutex);
5992 5997 }
5993 5998 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
5994 5999 NDBG20(("mptsas%d update phymask return", mpt->m_instance));
5995 6000 }
5996 6001
5997 6002 /*
5998 6003 * mptsas_handle_dr is a task handler for DR, the DR action includes:
5999 6004 * 1. Directly attched Device Added/Removed.
6000 6005 * 2. Expander Device Added/Removed.
6001 6006 * 3. Indirectly Attached Device Added/Expander.
6002 6007 * 4. LUNs of a existing device status change.
6003 6008 * 5. RAID volume created/deleted.
6004 6009 * 6. Member of RAID volume is released because of RAID deletion.
6005 6010 * 7. Physical disks are removed because of RAID creation.
6006 6011 */
6007 6012 static void
6008 6013 mptsas_handle_dr(void *args) {
6009 6014 mptsas_topo_change_list_t *topo_node = NULL;
6010 6015 mptsas_topo_change_list_t *save_node = NULL;
6011 6016 mptsas_t *mpt;
6012 6017 dev_info_t *parent = NULL;
6013 6018 mptsas_phymask_t phymask = 0;
6014 6019 char *phy_mask_name;
6015 6020 uint8_t flags = 0, physport = 0xff;
6016 6021 uint8_t port_update = 0;
6017 6022 uint_t event;
6018 6023
6019 6024 topo_node = (mptsas_topo_change_list_t *)args;
6020 6025
6021 6026 mpt = topo_node->mpt;
6022 6027 event = topo_node->event;
6023 6028 flags = topo_node->flags;
6024 6029
6025 6030 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
6026 6031
6027 6032 NDBG20(("mptsas%d handle_dr enter", mpt->m_instance));
6028 6033
6029 6034 switch (event) {
6030 6035 case MPTSAS_DR_EVENT_RECONFIG_TARGET:
6031 6036 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6032 6037 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE) ||
6033 6038 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) {
6034 6039 /*
6035 6040 * Direct attached or expander attached device added
6036 6041 * into system or a Phys Disk that is being unhidden.
6037 6042 */
6038 6043 port_update = 1;
6039 6044 }
6040 6045 break;
6041 6046 case MPTSAS_DR_EVENT_RECONFIG_SMP:
6042 6047 /*
6043 6048 * New expander added into system, it must be the head
6044 6049 * of topo_change_list_t
6045 6050 */
6046 6051 port_update = 1;
6047 6052 break;
6048 6053 default:
6049 6054 port_update = 0;
6050 6055 break;
6051 6056 }
6052 6057 /*
6053 6058 * All cases port_update == 1 may cause initiator port form change
6054 6059 */
6055 6060 mutex_enter(&mpt->m_mutex);
6056 6061 if (mpt->m_port_chng && port_update) {
6057 6062 /*
6058 6063 * mpt->m_port_chng flag indicates some PHYs of initiator
6059 6064 * port have changed to online. So when expander added or
6060 6065 * directly attached device online event come, we force to
6061 6066 * update port information by issueing SAS IO Unit Page and
6062 6067 * update PHYMASKs.
6063 6068 */
6064 6069 (void) mptsas_update_phymask(mpt);
6065 6070 mpt->m_port_chng = 0;
6066 6071
6067 6072 }
6068 6073 mutex_exit(&mpt->m_mutex);
6069 6074 while (topo_node) {
6070 6075 phymask = 0;
6071 6076 if (parent == NULL) {
6072 6077 physport = topo_node->un.physport;
6073 6078 event = topo_node->event;
6074 6079 flags = topo_node->flags;
6075 6080 if (event & (MPTSAS_DR_EVENT_OFFLINE_TARGET |
6076 6081 MPTSAS_DR_EVENT_OFFLINE_SMP)) {
6077 6082 /*
6078 6083 * For all offline events, phymask is known
6079 6084 */
6080 6085 phymask = topo_node->un.phymask;
6081 6086 goto find_parent;
6082 6087 }
6083 6088 if (event & MPTSAS_TOPO_FLAG_REMOVE_HANDLE) {
6084 6089 goto handle_topo_change;
6085 6090 }
6086 6091 if (flags & MPTSAS_TOPO_FLAG_LUN_ASSOCIATED) {
6087 6092 phymask = topo_node->un.phymask;
6088 6093 goto find_parent;
6089 6094 }
6090 6095
6091 6096 if ((flags ==
6092 6097 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) &&
6093 6098 (event == MPTSAS_DR_EVENT_RECONFIG_TARGET)) {
6094 6099 /*
6095 6100 * There is no any field in IR_CONFIG_CHANGE
6096 6101 * event indicate physport/phynum, let's get
6097 6102 * parent after SAS Device Page0 request.
6098 6103 */
6099 6104 goto handle_topo_change;
6100 6105 }
6101 6106
6102 6107 mutex_enter(&mpt->m_mutex);
6103 6108 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6104 6109 /*
6105 6110 * If the direct attached device added or a
6106 6111 * phys disk is being unhidden, argument
6107 6112 * physport actually is PHY#, so we have to get
6108 6113 * phymask according PHY#.
6109 6114 */
6110 6115 physport = mpt->m_phy_info[physport].port_num;
6111 6116 }
6112 6117
6113 6118 /*
6114 6119 * Translate physport to phymask so that we can search
6115 6120 * parent dip.
6116 6121 */
6117 6122 phymask = mptsas_physport_to_phymask(mpt,
6118 6123 physport);
6119 6124 mutex_exit(&mpt->m_mutex);
6120 6125
6121 6126 find_parent:
6122 6127 bzero(phy_mask_name, MPTSAS_MAX_PHYS);
6123 6128 /*
6124 6129 * For RAID topology change node, write the iport name
6125 6130 * as v0.
6126 6131 */
6127 6132 if (flags & MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
6128 6133 (void) sprintf(phy_mask_name, "v0");
6129 6134 } else {
6130 6135 /*
6131 6136 * phymask can bo 0 if the drive has been
6132 6137 * pulled by the time an add event is
6133 6138 * processed. If phymask is 0, just skip this
6134 6139 * event and continue.
6135 6140 */
6136 6141 if (phymask == 0) {
6137 6142 mutex_enter(&mpt->m_mutex);
6138 6143 save_node = topo_node;
6139 6144 topo_node = topo_node->next;
6140 6145 ASSERT(save_node);
6141 6146 kmem_free(save_node,
6142 6147 sizeof (mptsas_topo_change_list_t));
6143 6148 mutex_exit(&mpt->m_mutex);
6144 6149
6145 6150 parent = NULL;
6146 6151 continue;
6147 6152 }
6148 6153 (void) sprintf(phy_mask_name, "%x", phymask);
6149 6154 }
6150 6155 parent = scsi_hba_iport_find(mpt->m_dip,
6151 6156 phy_mask_name);
6152 6157 if (parent == NULL) {
6153 6158 mptsas_log(mpt, CE_WARN, "Failed to find an "
6154 6159 "iport, should not happen!");
6155 6160 goto out;
6156 6161 }
6157 6162
6158 6163 }
6159 6164 ASSERT(parent);
6160 6165 handle_topo_change:
6161 6166
6162 6167 mutex_enter(&mpt->m_mutex);
6163 6168
6164 6169 mptsas_handle_topo_change(topo_node, parent);
6165 6170 save_node = topo_node;
6166 6171 topo_node = topo_node->next;
6167 6172 ASSERT(save_node);
6168 6173 kmem_free(save_node, sizeof (mptsas_topo_change_list_t));
6169 6174 mutex_exit(&mpt->m_mutex);
6170 6175
6171 6176 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6172 6177 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) ||
6173 6178 (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED)) {
6174 6179 /*
6175 6180 * If direct attached device associated, make sure
6176 6181 * reset the parent before start the next one. But
6177 6182 * all devices associated with expander shares the
6178 6183 * parent. Also, reset parent if this is for RAID.
6179 6184 */
6180 6185 parent = NULL;
6181 6186 }
6182 6187 }
6183 6188 out:
6184 6189 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
6185 6190 }
6186 6191
6187 6192 static void
6188 6193 mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node,
6189 6194 dev_info_t *parent)
6190 6195 {
6191 6196 mptsas_target_t *ptgt = NULL;
6192 6197 mptsas_smp_t *psmp = NULL;
6193 6198 mptsas_t *mpt = (void *)topo_node->mpt;
6194 6199 uint16_t devhdl;
6195 6200 uint16_t attached_devhdl;
6196 6201 uint64_t sas_wwn = 0;
6197 6202 int rval = 0;
6198 6203 uint32_t page_address;
6199 6204 uint8_t phy, flags;
6200 6205 char *addr = NULL;
6201 6206 dev_info_t *lundip;
6202 6207 int circ = 0, circ1 = 0;
6203 6208 char attached_wwnstr[MPTSAS_WWN_STRLEN];
6204 6209
6205 6210 NDBG20(("mptsas%d handle_topo_change enter", mpt->m_instance));
6206 6211
6207 6212 ASSERT(mutex_owned(&mpt->m_mutex));
6208 6213
6209 6214 switch (topo_node->event) {
6210 6215 case MPTSAS_DR_EVENT_RECONFIG_TARGET:
6211 6216 {
6212 6217 char *phy_mask_name;
6213 6218 mptsas_phymask_t phymask = 0;
6214 6219
6215 6220 if (topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
6216 6221 /*
6217 6222 * Get latest RAID info.
6218 6223 */
6219 6224 (void) mptsas_get_raid_info(mpt);
6220 6225 ptgt = mptsas_search_by_devhdl(
6221 6226 &mpt->m_active->m_tgttbl, topo_node->devhdl);
6222 6227 if (ptgt == NULL)
6223 6228 break;
6224 6229 } else {
6225 6230 ptgt = (void *)topo_node->object;
6226 6231 }
6227 6232
6228 6233 if (ptgt == NULL) {
6229 6234 /*
6230 6235 * If a Phys Disk was deleted, RAID info needs to be
6231 6236 * updated to reflect the new topology.
6232 6237 */
6233 6238 (void) mptsas_get_raid_info(mpt);
6234 6239
6235 6240 /*
6236 6241 * Get sas device page 0 by DevHandle to make sure if
6237 6242 * SSP/SATA end device exist.
6238 6243 */
6239 6244 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
6240 6245 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
6241 6246 topo_node->devhdl;
6242 6247
6243 6248 rval = mptsas_get_target_device_info(mpt, page_address,
6244 6249 &devhdl, &ptgt);
6245 6250 if (rval == DEV_INFO_WRONG_DEVICE_TYPE) {
6246 6251 mptsas_log(mpt, CE_NOTE,
6247 6252 "mptsas_handle_topo_change: target %d is "
6248 6253 "not a SAS/SATA device. \n",
6249 6254 topo_node->devhdl);
6250 6255 } else if (rval == DEV_INFO_FAIL_ALLOC) {
6251 6256 mptsas_log(mpt, CE_NOTE,
6252 6257 "mptsas_handle_topo_change: could not "
6253 6258 "allocate memory. \n");
6254 6259 }
6255 6260 /*
6256 6261 * If rval is DEV_INFO_PHYS_DISK than there is nothing
6257 6262 * else to do, just leave.
6258 6263 */
6259 6264 if (rval != DEV_INFO_SUCCESS) {
6260 6265 return;
6261 6266 }
6262 6267 }
6263 6268
6264 6269 ASSERT(ptgt->m_devhdl == topo_node->devhdl);
6265 6270
6266 6271 mutex_exit(&mpt->m_mutex);
6267 6272 flags = topo_node->flags;
6268 6273
6269 6274 if (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) {
6270 6275 phymask = ptgt->m_phymask;
6271 6276 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
6272 6277 (void) sprintf(phy_mask_name, "%x", phymask);
6273 6278 parent = scsi_hba_iport_find(mpt->m_dip,
6274 6279 phy_mask_name);
6275 6280 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
6276 6281 if (parent == NULL) {
6277 6282 mptsas_log(mpt, CE_WARN, "Failed to find a "
6278 6283 "iport for PD, should not happen!");
6279 6284 mutex_enter(&mpt->m_mutex);
6280 6285 break;
6281 6286 }
6282 6287 }
6283 6288
6284 6289 if (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
6285 6290 ndi_devi_enter(parent, &circ1);
6286 6291 (void) mptsas_config_raid(parent, topo_node->devhdl,
6287 6292 &lundip);
6288 6293 ndi_devi_exit(parent, circ1);
6289 6294 } else {
6290 6295 /*
6291 6296 * hold nexus for bus configure
6292 6297 */
6293 6298 ndi_devi_enter(scsi_vhci_dip, &circ);
6294 6299 ndi_devi_enter(parent, &circ1);
6295 6300 rval = mptsas_config_target(parent, ptgt);
6296 6301 /*
6297 6302 * release nexus for bus configure
6298 6303 */
6299 6304 ndi_devi_exit(parent, circ1);
6300 6305 ndi_devi_exit(scsi_vhci_dip, circ);
6301 6306
6302 6307 /*
6303 6308 * Add parent's props for SMHBA support
6304 6309 */
6305 6310 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6306 6311 bzero(attached_wwnstr,
6307 6312 sizeof (attached_wwnstr));
6308 6313 (void) sprintf(attached_wwnstr, "w%016"PRIx64,
6309 6314 ptgt->m_sas_wwn);
6310 6315 if (ddi_prop_update_string(DDI_DEV_T_NONE,
6311 6316 parent,
6312 6317 SCSI_ADDR_PROP_ATTACHED_PORT,
6313 6318 attached_wwnstr)
6314 6319 != DDI_PROP_SUCCESS) {
6315 6320 (void) ddi_prop_remove(DDI_DEV_T_NONE,
6316 6321 parent,
6317 6322 SCSI_ADDR_PROP_ATTACHED_PORT);
6318 6323 mptsas_log(mpt, CE_WARN, "Failed to"
6319 6324 "attached-port props");
6320 6325 return;
6321 6326 }
6322 6327 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6323 6328 MPTSAS_NUM_PHYS, 1) !=
6324 6329 DDI_PROP_SUCCESS) {
6325 6330 (void) ddi_prop_remove(DDI_DEV_T_NONE,
6326 6331 parent, MPTSAS_NUM_PHYS);
6327 6332 mptsas_log(mpt, CE_WARN, "Failed to"
6328 6333 " create num-phys props");
6329 6334 return;
6330 6335 }
6331 6336
6332 6337 /*
6333 6338 * Update PHY info for smhba
6334 6339 */
6335 6340 mutex_enter(&mpt->m_mutex);
6336 6341 if (mptsas_smhba_phy_init(mpt)) {
6337 6342 mutex_exit(&mpt->m_mutex);
6338 6343 mptsas_log(mpt, CE_WARN, "mptsas phy"
6339 6344 " update failed");
6340 6345 return;
6341 6346 }
6342 6347 mutex_exit(&mpt->m_mutex);
6343 6348 mptsas_smhba_set_phy_props(mpt,
6344 6349 ddi_get_name_addr(parent), parent,
6345 6350 1, &attached_devhdl);
6346 6351 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6347 6352 MPTSAS_VIRTUAL_PORT, 0) !=
6348 6353 DDI_PROP_SUCCESS) {
6349 6354 (void) ddi_prop_remove(DDI_DEV_T_NONE,
6350 6355 parent, MPTSAS_VIRTUAL_PORT);
6351 6356 mptsas_log(mpt, CE_WARN,
6352 6357 "mptsas virtual-port"
6353 6358 "port prop update failed");
6354 6359 return;
6355 6360 }
6356 6361 }
6357 6362 }
6358 6363 mutex_enter(&mpt->m_mutex);
6359 6364
6360 6365 NDBG20(("mptsas%d handle_topo_change to online devhdl:%x, "
6361 6366 "phymask:%x.", mpt->m_instance, ptgt->m_devhdl,
6362 6367 ptgt->m_phymask));
6363 6368 break;
6364 6369 }
6365 6370 case MPTSAS_DR_EVENT_OFFLINE_TARGET:
6366 6371 {
6367 6372 mptsas_hash_table_t *tgttbl = &mpt->m_active->m_tgttbl;
6368 6373 devhdl = topo_node->devhdl;
6369 6374 ptgt = mptsas_search_by_devhdl(tgttbl, devhdl);
6370 6375 if (ptgt == NULL)
6371 6376 break;
6372 6377
6373 6378 sas_wwn = ptgt->m_sas_wwn;
6374 6379 phy = ptgt->m_phynum;
6375 6380
6376 6381 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
6377 6382
6378 6383 if (sas_wwn) {
6379 6384 (void) sprintf(addr, "w%016"PRIx64, sas_wwn);
6380 6385 } else {
6381 6386 (void) sprintf(addr, "p%x", phy);
6382 6387 }
6383 6388 ASSERT(ptgt->m_devhdl == devhdl);
6384 6389
6385 6390 if ((topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) ||
6386 6391 (topo_node->flags ==
6387 6392 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) {
6388 6393 /*
6389 6394 * Get latest RAID info if RAID volume status changes
6390 6395 * or Phys Disk status changes
6391 6396 */
6392 6397 (void) mptsas_get_raid_info(mpt);
6393 6398 }
6394 6399 /*
6395 6400 * Abort all outstanding command on the device
6396 6401 */
6397 6402 rval = mptsas_do_scsi_reset(mpt, devhdl);
6398 6403 if (rval) {
6399 6404 NDBG20(("mptsas%d handle_topo_change to reset target "
6400 6405 "before offline devhdl:%x, phymask:%x, rval:%x",
6401 6406 mpt->m_instance, ptgt->m_devhdl, ptgt->m_phymask,
6402 6407 rval));
6403 6408 }
6404 6409
6405 6410 mutex_exit(&mpt->m_mutex);
6406 6411
6407 6412 ndi_devi_enter(scsi_vhci_dip, &circ);
6408 6413 ndi_devi_enter(parent, &circ1);
6409 6414 rval = mptsas_offline_target(parent, addr);
6410 6415 ndi_devi_exit(parent, circ1);
6411 6416 ndi_devi_exit(scsi_vhci_dip, circ);
6412 6417 NDBG20(("mptsas%d handle_topo_change to offline devhdl:%x, "
6413 6418 "phymask:%x, rval:%x", mpt->m_instance,
6414 6419 ptgt->m_devhdl, ptgt->m_phymask, rval));
6415 6420
6416 6421 kmem_free(addr, SCSI_MAXNAMELEN);
6417 6422
6418 6423 /*
6419 6424 * Clear parent's props for SMHBA support
6420 6425 */
6421 6426 flags = topo_node->flags;
6422 6427 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6423 6428 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6424 6429 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent,
6425 6430 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
6426 6431 DDI_PROP_SUCCESS) {
6427 6432 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6428 6433 SCSI_ADDR_PROP_ATTACHED_PORT);
6429 6434 mptsas_log(mpt, CE_WARN, "mptsas attached port "
6430 6435 "prop update failed");
6431 6436 break;
6432 6437 }
6433 6438 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6434 6439 MPTSAS_NUM_PHYS, 0) !=
6435 6440 DDI_PROP_SUCCESS) {
6436 6441 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6437 6442 MPTSAS_NUM_PHYS);
6438 6443 mptsas_log(mpt, CE_WARN, "mptsas num phys "
6439 6444 "prop update failed");
6440 6445 break;
6441 6446 }
6442 6447 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6443 6448 MPTSAS_VIRTUAL_PORT, 1) !=
↓ open down ↓ |
5342 lines elided |
↑ open up ↑ |
6444 6449 DDI_PROP_SUCCESS) {
6445 6450 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6446 6451 MPTSAS_VIRTUAL_PORT);
6447 6452 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
6448 6453 "prop update failed");
6449 6454 break;
6450 6455 }
6451 6456 }
6452 6457
6453 6458 mutex_enter(&mpt->m_mutex);
6454 - if (mptsas_set_led_status(mpt, ptgt, 0) != DDI_SUCCESS) {
6459 + ptgt->m_led_status = 0;
6460 + if (mptsas_flush_led_status(mpt, ptgt) != DDI_SUCCESS) {
6455 6461 NDBG14(("mptsas: clear LED for tgt %x failed",
6456 6462 ptgt->m_slot_num));
6457 6463 }
6458 6464 if (rval == DDI_SUCCESS) {
6459 6465 mptsas_tgt_free(&mpt->m_active->m_tgttbl,
6460 6466 ptgt->m_sas_wwn, ptgt->m_phymask);
6461 6467 ptgt = NULL;
6462 6468 } else {
6463 6469 /*
6464 6470 * clean DR_INTRANSITION flag to allow I/O down to
6465 6471 * PHCI driver since failover finished.
6466 6472 * Invalidate the devhdl
6467 6473 */
6468 6474 mutex_enter(&ptgt->m_tgt_intr_mutex);
6469 6475 ptgt->m_devhdl = MPTSAS_INVALID_DEVHDL;
6470 6476 ptgt->m_tgt_unconfigured = 0;
6471 6477 ptgt->m_dr_flag = MPTSAS_DR_INACTIVE;
6472 6478 mutex_exit(&ptgt->m_tgt_intr_mutex);
6473 6479 }
6474 6480
6475 6481 /*
6476 6482 * Send SAS IO Unit Control to free the dev handle
6477 6483 */
6478 6484 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6479 6485 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE)) {
6480 6486 rval = mptsas_free_devhdl(mpt, devhdl);
6481 6487
6482 6488 NDBG20(("mptsas%d handle_topo_change to remove "
6483 6489 "devhdl:%x, rval:%x", mpt->m_instance, devhdl,
6484 6490 rval));
6485 6491 }
6486 6492
6487 6493 break;
6488 6494 }
6489 6495 case MPTSAS_TOPO_FLAG_REMOVE_HANDLE:
6490 6496 {
6491 6497 devhdl = topo_node->devhdl;
6492 6498 /*
6493 6499 * If this is the remove handle event, do a reset first.
6494 6500 */
6495 6501 if (topo_node->event == MPTSAS_TOPO_FLAG_REMOVE_HANDLE) {
6496 6502 rval = mptsas_do_scsi_reset(mpt, devhdl);
6497 6503 if (rval) {
6498 6504 NDBG20(("mpt%d reset target before remove "
6499 6505 "devhdl:%x, rval:%x", mpt->m_instance,
6500 6506 devhdl, rval));
6501 6507 }
6502 6508 }
6503 6509
6504 6510 /*
6505 6511 * Send SAS IO Unit Control to free the dev handle
6506 6512 */
6507 6513 rval = mptsas_free_devhdl(mpt, devhdl);
6508 6514 NDBG20(("mptsas%d handle_topo_change to remove "
6509 6515 "devhdl:%x, rval:%x", mpt->m_instance, devhdl,
6510 6516 rval));
6511 6517 break;
6512 6518 }
6513 6519 case MPTSAS_DR_EVENT_RECONFIG_SMP:
6514 6520 {
6515 6521 mptsas_smp_t smp;
6516 6522 dev_info_t *smpdip;
6517 6523 mptsas_hash_table_t *smptbl = &mpt->m_active->m_smptbl;
6518 6524
6519 6525 devhdl = topo_node->devhdl;
6520 6526
6521 6527 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL &
6522 6528 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)devhdl;
6523 6529 rval = mptsas_get_sas_expander_page0(mpt, page_address, &smp);
6524 6530 if (rval != DDI_SUCCESS) {
6525 6531 mptsas_log(mpt, CE_WARN, "failed to online smp, "
6526 6532 "handle %x", devhdl);
6527 6533 return;
6528 6534 }
6529 6535
6530 6536 psmp = mptsas_smp_alloc(smptbl, &smp);
6531 6537 if (psmp == NULL) {
6532 6538 return;
6533 6539 }
6534 6540
6535 6541 mutex_exit(&mpt->m_mutex);
6536 6542 ndi_devi_enter(parent, &circ1);
6537 6543 (void) mptsas_online_smp(parent, psmp, &smpdip);
6538 6544 ndi_devi_exit(parent, circ1);
6539 6545
6540 6546 mutex_enter(&mpt->m_mutex);
6541 6547 break;
6542 6548 }
6543 6549 case MPTSAS_DR_EVENT_OFFLINE_SMP:
6544 6550 {
6545 6551 mptsas_hash_table_t *smptbl = &mpt->m_active->m_smptbl;
6546 6552 devhdl = topo_node->devhdl;
6547 6553 uint32_t dev_info;
6548 6554
6549 6555 psmp = mptsas_search_by_devhdl(smptbl, devhdl);
6550 6556 if (psmp == NULL)
6551 6557 break;
6552 6558 /*
6553 6559 * The mptsas_smp_t data is released only if the dip is offlined
6554 6560 * successfully.
6555 6561 */
6556 6562 mutex_exit(&mpt->m_mutex);
6557 6563
6558 6564 ndi_devi_enter(parent, &circ1);
6559 6565 rval = mptsas_offline_smp(parent, psmp, NDI_DEVI_REMOVE);
6560 6566 ndi_devi_exit(parent, circ1);
6561 6567
6562 6568 dev_info = psmp->m_deviceinfo;
6563 6569 if ((dev_info & DEVINFO_DIRECT_ATTACHED) ==
6564 6570 DEVINFO_DIRECT_ATTACHED) {
6565 6571 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6566 6572 MPTSAS_VIRTUAL_PORT, 1) !=
6567 6573 DDI_PROP_SUCCESS) {
6568 6574 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6569 6575 MPTSAS_VIRTUAL_PORT);
6570 6576 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
6571 6577 "prop update failed");
6572 6578 return;
6573 6579 }
6574 6580 /*
6575 6581 * Check whether the smp connected to the iport,
6576 6582 */
6577 6583 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6578 6584 MPTSAS_NUM_PHYS, 0) !=
6579 6585 DDI_PROP_SUCCESS) {
6580 6586 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6581 6587 MPTSAS_NUM_PHYS);
6582 6588 mptsas_log(mpt, CE_WARN, "mptsas num phys"
6583 6589 "prop update failed");
6584 6590 return;
6585 6591 }
6586 6592 /*
6587 6593 * Clear parent's attached-port props
6588 6594 */
6589 6595 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6590 6596 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent,
6591 6597 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
6592 6598 DDI_PROP_SUCCESS) {
6593 6599 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6594 6600 SCSI_ADDR_PROP_ATTACHED_PORT);
6595 6601 mptsas_log(mpt, CE_WARN, "mptsas attached port "
6596 6602 "prop update failed");
6597 6603 return;
6598 6604 }
6599 6605 }
6600 6606
6601 6607 mutex_enter(&mpt->m_mutex);
6602 6608 NDBG20(("mptsas%d handle_topo_change to remove devhdl:%x, "
6603 6609 "rval:%x", mpt->m_instance, psmp->m_devhdl, rval));
6604 6610 if (rval == DDI_SUCCESS) {
6605 6611 mptsas_smp_free(smptbl, psmp->m_sasaddr,
6606 6612 psmp->m_phymask);
6607 6613 } else {
6608 6614 psmp->m_devhdl = MPTSAS_INVALID_DEVHDL;
6609 6615 }
6610 6616
6611 6617 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6612 6618
6613 6619 break;
6614 6620 }
6615 6621 default:
6616 6622 return;
6617 6623 }
6618 6624 }
6619 6625
6620 6626 /*
6621 6627 * Record the event if its type is enabled in mpt instance by ioctl.
6622 6628 */
6623 6629 static void
6624 6630 mptsas_record_event(void *args)
6625 6631 {
6626 6632 m_replyh_arg_t *replyh_arg;
6627 6633 pMpi2EventNotificationReply_t eventreply;
6628 6634 uint32_t event, rfm;
6629 6635 mptsas_t *mpt;
6630 6636 int i, j;
6631 6637 uint16_t event_data_len;
6632 6638 boolean_t sendAEN = FALSE;
6633 6639
6634 6640 replyh_arg = (m_replyh_arg_t *)args;
6635 6641 rfm = replyh_arg->rfm;
6636 6642 mpt = replyh_arg->mpt;
6637 6643
6638 6644 eventreply = (pMpi2EventNotificationReply_t)
6639 6645 (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr));
6640 6646 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
6641 6647
6642 6648
6643 6649 /*
6644 6650 * Generate a system event to let anyone who cares know that a
6645 6651 * LOG_ENTRY_ADDED event has occurred. This is sent no matter what the
6646 6652 * event mask is set to.
6647 6653 */
6648 6654 if (event == MPI2_EVENT_LOG_ENTRY_ADDED) {
6649 6655 sendAEN = TRUE;
6650 6656 }
6651 6657
6652 6658 /*
6653 6659 * Record the event only if it is not masked. Determine which dword
6654 6660 * and bit of event mask to test.
6655 6661 */
6656 6662 i = (uint8_t)(event / 32);
6657 6663 j = (uint8_t)(event % 32);
6658 6664 if ((i < 4) && ((1 << j) & mpt->m_event_mask[i])) {
6659 6665 i = mpt->m_event_index;
6660 6666 mpt->m_events[i].Type = event;
6661 6667 mpt->m_events[i].Number = ++mpt->m_event_number;
6662 6668 bzero(mpt->m_events[i].Data, MPTSAS_MAX_EVENT_DATA_LENGTH * 4);
6663 6669 event_data_len = ddi_get16(mpt->m_acc_reply_frame_hdl,
6664 6670 &eventreply->EventDataLength);
6665 6671
6666 6672 if (event_data_len > 0) {
6667 6673 /*
6668 6674 * Limit data to size in m_event entry
6669 6675 */
6670 6676 if (event_data_len > MPTSAS_MAX_EVENT_DATA_LENGTH) {
6671 6677 event_data_len = MPTSAS_MAX_EVENT_DATA_LENGTH;
6672 6678 }
6673 6679 for (j = 0; j < event_data_len; j++) {
6674 6680 mpt->m_events[i].Data[j] =
6675 6681 ddi_get32(mpt->m_acc_reply_frame_hdl,
6676 6682 &(eventreply->EventData[j]));
6677 6683 }
6678 6684
6679 6685 /*
6680 6686 * check for index wrap-around
6681 6687 */
6682 6688 if (++i == MPTSAS_EVENT_QUEUE_SIZE) {
6683 6689 i = 0;
6684 6690 }
6685 6691 mpt->m_event_index = (uint8_t)i;
6686 6692
6687 6693 /*
6688 6694 * Set flag to send the event.
6689 6695 */
6690 6696 sendAEN = TRUE;
6691 6697 }
6692 6698 }
6693 6699
6694 6700 /*
6695 6701 * Generate a system event if flag is set to let anyone who cares know
6696 6702 * that an event has occurred.
6697 6703 */
6698 6704 if (sendAEN) {
6699 6705 (void) ddi_log_sysevent(mpt->m_dip, DDI_VENDOR_LSI, "MPT_SAS",
6700 6706 "SAS", NULL, NULL, DDI_NOSLEEP);
6701 6707 }
6702 6708 }
6703 6709
6704 6710 #define SMP_RESET_IN_PROGRESS MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS
6705 6711 /*
6706 6712 * handle sync events from ioc in interrupt
6707 6713 * return value:
6708 6714 * DDI_SUCCESS: The event is handled by this func
6709 6715 * DDI_FAILURE: Event is not handled
6710 6716 */
6711 6717 static int
6712 6718 mptsas_handle_event_sync(void *args)
6713 6719 {
6714 6720 m_replyh_arg_t *replyh_arg;
6715 6721 pMpi2EventNotificationReply_t eventreply;
6716 6722 uint32_t event, rfm;
6717 6723 mptsas_t *mpt;
6718 6724 uint_t iocstatus;
6719 6725
6720 6726 replyh_arg = (m_replyh_arg_t *)args;
6721 6727 rfm = replyh_arg->rfm;
6722 6728 mpt = replyh_arg->mpt;
6723 6729
6724 6730 ASSERT(mutex_owned(&mpt->m_mutex));
6725 6731
6726 6732 eventreply = (pMpi2EventNotificationReply_t)
6727 6733 (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr));
6728 6734 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
6729 6735
6730 6736 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
6731 6737 &eventreply->IOCStatus)) {
6732 6738 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
6733 6739 mptsas_log(mpt, CE_WARN,
6734 6740 "!mptsas_handle_event_sync: IOCStatus=0x%x, "
6735 6741 "IOCLogInfo=0x%x", iocstatus,
6736 6742 ddi_get32(mpt->m_acc_reply_frame_hdl,
6737 6743 &eventreply->IOCLogInfo));
6738 6744 } else {
6739 6745 mptsas_log(mpt, CE_WARN,
6740 6746 "mptsas_handle_event_sync: IOCStatus=0x%x, "
6741 6747 "IOCLogInfo=0x%x", iocstatus,
6742 6748 ddi_get32(mpt->m_acc_reply_frame_hdl,
6743 6749 &eventreply->IOCLogInfo));
6744 6750 }
6745 6751 }
6746 6752
6747 6753 /*
6748 6754 * figure out what kind of event we got and handle accordingly
6749 6755 */
6750 6756 switch (event) {
6751 6757 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
6752 6758 {
6753 6759 pMpi2EventDataSasTopologyChangeList_t sas_topo_change_list;
6754 6760 uint8_t num_entries, expstatus, phy;
6755 6761 uint8_t phystatus, physport, state, i;
6756 6762 uint8_t start_phy_num, link_rate;
6757 6763 uint16_t dev_handle, reason_code;
6758 6764 uint16_t enc_handle, expd_handle;
6759 6765 char string[80], curr[80], prev[80];
6760 6766 mptsas_topo_change_list_t *topo_head = NULL;
6761 6767 mptsas_topo_change_list_t *topo_tail = NULL;
6762 6768 mptsas_topo_change_list_t *topo_node = NULL;
6763 6769 mptsas_target_t *ptgt;
6764 6770 mptsas_smp_t *psmp;
6765 6771 mptsas_hash_table_t *tgttbl, *smptbl;
6766 6772 uint8_t flags = 0, exp_flag;
6767 6773 smhba_info_t *pSmhba = NULL;
6768 6774
6769 6775 NDBG20(("mptsas_handle_event_sync: SAS topology change"));
6770 6776
6771 6777 tgttbl = &mpt->m_active->m_tgttbl;
6772 6778 smptbl = &mpt->m_active->m_smptbl;
6773 6779
6774 6780 sas_topo_change_list = (pMpi2EventDataSasTopologyChangeList_t)
6775 6781 eventreply->EventData;
6776 6782
6777 6783 enc_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6778 6784 &sas_topo_change_list->EnclosureHandle);
6779 6785 expd_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6780 6786 &sas_topo_change_list->ExpanderDevHandle);
6781 6787 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl,
6782 6788 &sas_topo_change_list->NumEntries);
6783 6789 start_phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl,
6784 6790 &sas_topo_change_list->StartPhyNum);
6785 6791 expstatus = ddi_get8(mpt->m_acc_reply_frame_hdl,
6786 6792 &sas_topo_change_list->ExpStatus);
6787 6793 physport = ddi_get8(mpt->m_acc_reply_frame_hdl,
6788 6794 &sas_topo_change_list->PhysicalPort);
6789 6795
6790 6796 string[0] = 0;
6791 6797 if (expd_handle) {
6792 6798 flags = MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED;
6793 6799 switch (expstatus) {
6794 6800 case MPI2_EVENT_SAS_TOPO_ES_ADDED:
6795 6801 (void) sprintf(string, " added");
6796 6802 /*
6797 6803 * New expander device added
6798 6804 */
6799 6805 mpt->m_port_chng = 1;
6800 6806 topo_node = kmem_zalloc(
6801 6807 sizeof (mptsas_topo_change_list_t),
6802 6808 KM_SLEEP);
6803 6809 topo_node->mpt = mpt;
6804 6810 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_SMP;
6805 6811 topo_node->un.physport = physport;
6806 6812 topo_node->devhdl = expd_handle;
6807 6813 topo_node->flags = flags;
6808 6814 topo_node->object = NULL;
6809 6815 if (topo_head == NULL) {
6810 6816 topo_head = topo_tail = topo_node;
6811 6817 } else {
6812 6818 topo_tail->next = topo_node;
6813 6819 topo_tail = topo_node;
6814 6820 }
6815 6821 break;
6816 6822 case MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING:
6817 6823 (void) sprintf(string, " not responding, "
6818 6824 "removed");
6819 6825 psmp = mptsas_search_by_devhdl(smptbl,
6820 6826 expd_handle);
6821 6827 if (psmp == NULL)
6822 6828 break;
6823 6829
6824 6830 topo_node = kmem_zalloc(
6825 6831 sizeof (mptsas_topo_change_list_t),
6826 6832 KM_SLEEP);
6827 6833 topo_node->mpt = mpt;
6828 6834 topo_node->un.phymask = psmp->m_phymask;
6829 6835 topo_node->event = MPTSAS_DR_EVENT_OFFLINE_SMP;
6830 6836 topo_node->devhdl = expd_handle;
6831 6837 topo_node->flags = flags;
6832 6838 topo_node->object = NULL;
6833 6839 if (topo_head == NULL) {
6834 6840 topo_head = topo_tail = topo_node;
6835 6841 } else {
6836 6842 topo_tail->next = topo_node;
6837 6843 topo_tail = topo_node;
6838 6844 }
6839 6845 break;
6840 6846 case MPI2_EVENT_SAS_TOPO_ES_RESPONDING:
6841 6847 break;
6842 6848 case MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING:
6843 6849 (void) sprintf(string, " not responding, "
6844 6850 "delaying removal");
6845 6851 break;
6846 6852 default:
6847 6853 break;
6848 6854 }
6849 6855 } else {
6850 6856 flags = MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE;
6851 6857 }
6852 6858
6853 6859 NDBG20(("SAS TOPOLOGY CHANGE for enclosure %x expander %x%s\n",
6854 6860 enc_handle, expd_handle, string));
6855 6861 for (i = 0; i < num_entries; i++) {
6856 6862 phy = i + start_phy_num;
6857 6863 phystatus = ddi_get8(mpt->m_acc_reply_frame_hdl,
6858 6864 &sas_topo_change_list->PHY[i].PhyStatus);
6859 6865 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6860 6866 &sas_topo_change_list->PHY[i].AttachedDevHandle);
6861 6867 reason_code = phystatus & MPI2_EVENT_SAS_TOPO_RC_MASK;
6862 6868 /*
6863 6869 * Filter out processing of Phy Vacant Status unless
6864 6870 * the reason code is "Not Responding". Process all
6865 6871 * other combinations of Phy Status and Reason Codes.
6866 6872 */
6867 6873 if ((phystatus &
6868 6874 MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT) &&
6869 6875 (reason_code !=
6870 6876 MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING)) {
6871 6877 continue;
6872 6878 }
6873 6879 curr[0] = 0;
6874 6880 prev[0] = 0;
6875 6881 string[0] = 0;
6876 6882 switch (reason_code) {
6877 6883 case MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED:
6878 6884 {
6879 6885 NDBG20(("mptsas%d phy %d physical_port %d "
6880 6886 "dev_handle %d added", mpt->m_instance, phy,
6881 6887 physport, dev_handle));
6882 6888 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl,
6883 6889 &sas_topo_change_list->PHY[i].LinkRate);
6884 6890 state = (link_rate &
6885 6891 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >>
6886 6892 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT;
6887 6893 switch (state) {
6888 6894 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
6889 6895 (void) sprintf(curr, "is disabled");
6890 6896 break;
6891 6897 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
6892 6898 (void) sprintf(curr, "is offline, "
6893 6899 "failed speed negotiation");
6894 6900 break;
6895 6901 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
6896 6902 (void) sprintf(curr, "SATA OOB "
6897 6903 "complete");
6898 6904 break;
6899 6905 case SMP_RESET_IN_PROGRESS:
6900 6906 (void) sprintf(curr, "SMP reset in "
6901 6907 "progress");
6902 6908 break;
6903 6909 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
6904 6910 (void) sprintf(curr, "is online at "
6905 6911 "1.5 Gbps");
6906 6912 break;
6907 6913 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
6908 6914 (void) sprintf(curr, "is online at 3.0 "
6909 6915 "Gbps");
6910 6916 break;
6911 6917 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
6912 6918 (void) sprintf(curr, "is online at 6.0 "
6913 6919 "Gbps");
6914 6920 break;
6915 6921 default:
6916 6922 (void) sprintf(curr, "state is "
6917 6923 "unknown");
6918 6924 break;
6919 6925 }
6920 6926 /*
6921 6927 * New target device added into the system.
6922 6928 * Set association flag according to if an
6923 6929 * expander is used or not.
6924 6930 */
6925 6931 exp_flag =
6926 6932 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE;
6927 6933 if (flags ==
6928 6934 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) {
6929 6935 flags = exp_flag;
6930 6936 }
6931 6937 topo_node = kmem_zalloc(
6932 6938 sizeof (mptsas_topo_change_list_t),
6933 6939 KM_SLEEP);
6934 6940 topo_node->mpt = mpt;
6935 6941 topo_node->event =
6936 6942 MPTSAS_DR_EVENT_RECONFIG_TARGET;
6937 6943 if (expd_handle == 0) {
6938 6944 /*
6939 6945 * Per MPI 2, if expander dev handle
6940 6946 * is 0, it's a directly attached
6941 6947 * device. So driver use PHY to decide
6942 6948 * which iport is associated
6943 6949 */
6944 6950 physport = phy;
6945 6951 mpt->m_port_chng = 1;
6946 6952 }
6947 6953 topo_node->un.physport = physport;
6948 6954 topo_node->devhdl = dev_handle;
6949 6955 topo_node->flags = flags;
6950 6956 topo_node->object = NULL;
6951 6957 if (topo_head == NULL) {
6952 6958 topo_head = topo_tail = topo_node;
6953 6959 } else {
6954 6960 topo_tail->next = topo_node;
6955 6961 topo_tail = topo_node;
6956 6962 }
6957 6963 break;
6958 6964 }
6959 6965 case MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING:
6960 6966 {
6961 6967 NDBG20(("mptsas%d phy %d physical_port %d "
6962 6968 "dev_handle %d removed", mpt->m_instance,
6963 6969 phy, physport, dev_handle));
6964 6970 /*
6965 6971 * Set association flag according to if an
6966 6972 * expander is used or not.
6967 6973 */
6968 6974 exp_flag =
6969 6975 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE;
6970 6976 if (flags ==
6971 6977 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) {
6972 6978 flags = exp_flag;
6973 6979 }
6974 6980 /*
6975 6981 * Target device is removed from the system
6976 6982 * Before the device is really offline from
6977 6983 * from system.
6978 6984 */
6979 6985 ptgt = mptsas_search_by_devhdl(tgttbl,
6980 6986 dev_handle);
6981 6987 /*
6982 6988 * If ptgt is NULL here, it means that the
6983 6989 * DevHandle is not in the hash table. This is
6984 6990 * reasonable sometimes. For example, if a
6985 6991 * disk was pulled, then added, then pulled
6986 6992 * again, the disk will not have been put into
6987 6993 * the hash table because the add event will
6988 6994 * have an invalid phymask. BUT, this does not
6989 6995 * mean that the DevHandle is invalid. The
6990 6996 * controller will still have a valid DevHandle
6991 6997 * that must be removed. To do this, use the
6992 6998 * MPTSAS_TOPO_FLAG_REMOVE_HANDLE event.
6993 6999 */
6994 7000 if (ptgt == NULL) {
6995 7001 topo_node = kmem_zalloc(
6996 7002 sizeof (mptsas_topo_change_list_t),
6997 7003 KM_SLEEP);
6998 7004 topo_node->mpt = mpt;
6999 7005 topo_node->un.phymask = 0;
7000 7006 topo_node->event =
7001 7007 MPTSAS_TOPO_FLAG_REMOVE_HANDLE;
7002 7008 topo_node->devhdl = dev_handle;
7003 7009 topo_node->flags = flags;
7004 7010 topo_node->object = NULL;
7005 7011 if (topo_head == NULL) {
7006 7012 topo_head = topo_tail =
7007 7013 topo_node;
7008 7014 } else {
7009 7015 topo_tail->next = topo_node;
7010 7016 topo_tail = topo_node;
7011 7017 }
7012 7018 break;
7013 7019 }
7014 7020
7015 7021 /*
7016 7022 * Update DR flag immediately avoid I/O failure
7017 7023 * before failover finish. Pay attention to the
7018 7024 * mutex protect, we need grab the per target
7019 7025 * mutex during set m_dr_flag because the
7020 7026 * m_mutex would not be held all the time in
7021 7027 * mptsas_scsi_start().
7022 7028 */
7023 7029 mutex_enter(&ptgt->m_tgt_intr_mutex);
7024 7030 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
7025 7031 mutex_exit(&ptgt->m_tgt_intr_mutex);
7026 7032
7027 7033 topo_node = kmem_zalloc(
7028 7034 sizeof (mptsas_topo_change_list_t),
7029 7035 KM_SLEEP);
7030 7036 topo_node->mpt = mpt;
7031 7037 topo_node->un.phymask = ptgt->m_phymask;
7032 7038 topo_node->event =
7033 7039 MPTSAS_DR_EVENT_OFFLINE_TARGET;
7034 7040 topo_node->devhdl = dev_handle;
7035 7041 topo_node->flags = flags;
7036 7042 topo_node->object = NULL;
7037 7043 if (topo_head == NULL) {
7038 7044 topo_head = topo_tail = topo_node;
7039 7045 } else {
7040 7046 topo_tail->next = topo_node;
7041 7047 topo_tail = topo_node;
7042 7048 }
7043 7049 break;
7044 7050 }
7045 7051 case MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED:
7046 7052 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl,
7047 7053 &sas_topo_change_list->PHY[i].LinkRate);
7048 7054 state = (link_rate &
7049 7055 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >>
7050 7056 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT;
7051 7057 pSmhba = &mpt->m_phy_info[i].smhba_info;
7052 7058 pSmhba->negotiated_link_rate = state;
7053 7059 switch (state) {
7054 7060 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
7055 7061 (void) sprintf(curr, "is disabled");
7056 7062 mptsas_smhba_log_sysevent(mpt,
7057 7063 ESC_SAS_PHY_EVENT,
7058 7064 SAS_PHY_REMOVE,
7059 7065 &mpt->m_phy_info[i].smhba_info);
7060 7066 mpt->m_phy_info[i].smhba_info.
7061 7067 negotiated_link_rate
7062 7068 = 0x1;
7063 7069 break;
7064 7070 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
7065 7071 (void) sprintf(curr, "is offline, "
7066 7072 "failed speed negotiation");
7067 7073 mptsas_smhba_log_sysevent(mpt,
7068 7074 ESC_SAS_PHY_EVENT,
7069 7075 SAS_PHY_OFFLINE,
7070 7076 &mpt->m_phy_info[i].smhba_info);
7071 7077 break;
7072 7078 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
7073 7079 (void) sprintf(curr, "SATA OOB "
7074 7080 "complete");
7075 7081 break;
7076 7082 case SMP_RESET_IN_PROGRESS:
7077 7083 (void) sprintf(curr, "SMP reset in "
7078 7084 "progress");
7079 7085 break;
7080 7086 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
7081 7087 (void) sprintf(curr, "is online at "
7082 7088 "1.5 Gbps");
7083 7089 if ((expd_handle == 0) &&
7084 7090 (enc_handle == 1)) {
7085 7091 mpt->m_port_chng = 1;
7086 7092 }
7087 7093 mptsas_smhba_log_sysevent(mpt,
7088 7094 ESC_SAS_PHY_EVENT,
7089 7095 SAS_PHY_ONLINE,
7090 7096 &mpt->m_phy_info[i].smhba_info);
7091 7097 break;
7092 7098 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
7093 7099 (void) sprintf(curr, "is online at 3.0 "
7094 7100 "Gbps");
7095 7101 if ((expd_handle == 0) &&
7096 7102 (enc_handle == 1)) {
7097 7103 mpt->m_port_chng = 1;
7098 7104 }
7099 7105 mptsas_smhba_log_sysevent(mpt,
7100 7106 ESC_SAS_PHY_EVENT,
7101 7107 SAS_PHY_ONLINE,
7102 7108 &mpt->m_phy_info[i].smhba_info);
7103 7109 break;
7104 7110 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
7105 7111 (void) sprintf(curr, "is online at "
7106 7112 "6.0 Gbps");
7107 7113 if ((expd_handle == 0) &&
7108 7114 (enc_handle == 1)) {
7109 7115 mpt->m_port_chng = 1;
7110 7116 }
7111 7117 mptsas_smhba_log_sysevent(mpt,
7112 7118 ESC_SAS_PHY_EVENT,
7113 7119 SAS_PHY_ONLINE,
7114 7120 &mpt->m_phy_info[i].smhba_info);
7115 7121 break;
7116 7122 default:
7117 7123 (void) sprintf(curr, "state is "
7118 7124 "unknown");
7119 7125 break;
7120 7126 }
7121 7127
7122 7128 state = (link_rate &
7123 7129 MPI2_EVENT_SAS_TOPO_LR_PREV_MASK) >>
7124 7130 MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT;
7125 7131 switch (state) {
7126 7132 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
7127 7133 (void) sprintf(prev, ", was disabled");
7128 7134 break;
7129 7135 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
7130 7136 (void) sprintf(prev, ", was offline, "
7131 7137 "failed speed negotiation");
7132 7138 break;
7133 7139 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
7134 7140 (void) sprintf(prev, ", was SATA OOB "
7135 7141 "complete");
7136 7142 break;
7137 7143 case SMP_RESET_IN_PROGRESS:
7138 7144 (void) sprintf(prev, ", was SMP reset "
7139 7145 "in progress");
7140 7146 break;
7141 7147 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
7142 7148 (void) sprintf(prev, ", was online at "
7143 7149 "1.5 Gbps");
7144 7150 break;
7145 7151 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
7146 7152 (void) sprintf(prev, ", was online at "
7147 7153 "3.0 Gbps");
7148 7154 break;
7149 7155 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
7150 7156 (void) sprintf(prev, ", was online at "
7151 7157 "6.0 Gbps");
7152 7158 break;
7153 7159 default:
7154 7160 break;
7155 7161 }
7156 7162 (void) sprintf(&string[strlen(string)], "link "
7157 7163 "changed, ");
7158 7164 break;
7159 7165 case MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE:
7160 7166 continue;
7161 7167 case MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING:
7162 7168 (void) sprintf(&string[strlen(string)],
7163 7169 "target not responding, delaying "
7164 7170 "removal");
7165 7171 break;
7166 7172 }
7167 7173 NDBG20(("mptsas%d phy %d DevHandle %x, %s%s%s\n",
7168 7174 mpt->m_instance, phy, dev_handle, string, curr,
7169 7175 prev));
7170 7176 }
7171 7177 if (topo_head != NULL) {
7172 7178 /*
7173 7179 * Launch DR taskq to handle topology change
7174 7180 */
7175 7181 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
7176 7182 mptsas_handle_dr, (void *)topo_head,
7177 7183 DDI_NOSLEEP)) != DDI_SUCCESS) {
7178 7184 mptsas_log(mpt, CE_NOTE, "mptsas start taskq "
7179 7185 "for handle SAS DR event failed. \n");
7180 7186 }
7181 7187 }
7182 7188 break;
7183 7189 }
7184 7190 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
7185 7191 {
7186 7192 Mpi2EventDataIrConfigChangeList_t *irChangeList;
7187 7193 mptsas_topo_change_list_t *topo_head = NULL;
7188 7194 mptsas_topo_change_list_t *topo_tail = NULL;
7189 7195 mptsas_topo_change_list_t *topo_node = NULL;
7190 7196 mptsas_target_t *ptgt;
7191 7197 mptsas_hash_table_t *tgttbl;
7192 7198 uint8_t num_entries, i, reason;
7193 7199 uint16_t volhandle, diskhandle;
7194 7200
7195 7201 irChangeList = (pMpi2EventDataIrConfigChangeList_t)
7196 7202 eventreply->EventData;
7197 7203 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl,
7198 7204 &irChangeList->NumElements);
7199 7205
7200 7206 tgttbl = &mpt->m_active->m_tgttbl;
7201 7207
7202 7208 NDBG20(("mptsas%d IR_CONFIGURATION_CHANGE_LIST event received",
7203 7209 mpt->m_instance));
7204 7210
7205 7211 for (i = 0; i < num_entries; i++) {
7206 7212 reason = ddi_get8(mpt->m_acc_reply_frame_hdl,
7207 7213 &irChangeList->ConfigElement[i].ReasonCode);
7208 7214 volhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7209 7215 &irChangeList->ConfigElement[i].VolDevHandle);
7210 7216 diskhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7211 7217 &irChangeList->ConfigElement[i].PhysDiskDevHandle);
7212 7218
7213 7219 switch (reason) {
7214 7220 case MPI2_EVENT_IR_CHANGE_RC_ADDED:
7215 7221 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED:
7216 7222 {
7217 7223 NDBG20(("mptsas %d volume added\n",
7218 7224 mpt->m_instance));
7219 7225
7220 7226 topo_node = kmem_zalloc(
7221 7227 sizeof (mptsas_topo_change_list_t),
7222 7228 KM_SLEEP);
7223 7229
7224 7230 topo_node->mpt = mpt;
7225 7231 topo_node->event =
7226 7232 MPTSAS_DR_EVENT_RECONFIG_TARGET;
7227 7233 topo_node->un.physport = 0xff;
7228 7234 topo_node->devhdl = volhandle;
7229 7235 topo_node->flags =
7230 7236 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED;
7231 7237 topo_node->object = NULL;
7232 7238 if (topo_head == NULL) {
7233 7239 topo_head = topo_tail = topo_node;
7234 7240 } else {
7235 7241 topo_tail->next = topo_node;
7236 7242 topo_tail = topo_node;
7237 7243 }
7238 7244 break;
7239 7245 }
7240 7246 case MPI2_EVENT_IR_CHANGE_RC_REMOVED:
7241 7247 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED:
7242 7248 {
7243 7249 NDBG20(("mptsas %d volume deleted\n",
7244 7250 mpt->m_instance));
7245 7251 ptgt = mptsas_search_by_devhdl(tgttbl,
7246 7252 volhandle);
7247 7253 if (ptgt == NULL)
7248 7254 break;
7249 7255
7250 7256 /*
7251 7257 * Clear any flags related to volume
7252 7258 */
7253 7259 (void) mptsas_delete_volume(mpt, volhandle);
7254 7260
7255 7261 /*
7256 7262 * Update DR flag immediately avoid I/O failure
7257 7263 */
7258 7264 mutex_enter(&ptgt->m_tgt_intr_mutex);
7259 7265 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
7260 7266 mutex_exit(&ptgt->m_tgt_intr_mutex);
7261 7267
7262 7268 topo_node = kmem_zalloc(
7263 7269 sizeof (mptsas_topo_change_list_t),
7264 7270 KM_SLEEP);
7265 7271 topo_node->mpt = mpt;
7266 7272 topo_node->un.phymask = ptgt->m_phymask;
7267 7273 topo_node->event =
7268 7274 MPTSAS_DR_EVENT_OFFLINE_TARGET;
7269 7275 topo_node->devhdl = volhandle;
7270 7276 topo_node->flags =
7271 7277 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED;
7272 7278 topo_node->object = (void *)ptgt;
7273 7279 if (topo_head == NULL) {
7274 7280 topo_head = topo_tail = topo_node;
7275 7281 } else {
7276 7282 topo_tail->next = topo_node;
7277 7283 topo_tail = topo_node;
7278 7284 }
7279 7285 break;
7280 7286 }
7281 7287 case MPI2_EVENT_IR_CHANGE_RC_PD_CREATED:
7282 7288 case MPI2_EVENT_IR_CHANGE_RC_HIDE:
7283 7289 {
7284 7290 ptgt = mptsas_search_by_devhdl(tgttbl,
7285 7291 diskhandle);
7286 7292 if (ptgt == NULL)
7287 7293 break;
7288 7294
7289 7295 /*
7290 7296 * Update DR flag immediately avoid I/O failure
7291 7297 */
7292 7298 mutex_enter(&ptgt->m_tgt_intr_mutex);
7293 7299 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
7294 7300 mutex_exit(&ptgt->m_tgt_intr_mutex);
7295 7301
7296 7302 topo_node = kmem_zalloc(
7297 7303 sizeof (mptsas_topo_change_list_t),
7298 7304 KM_SLEEP);
7299 7305 topo_node->mpt = mpt;
7300 7306 topo_node->un.phymask = ptgt->m_phymask;
7301 7307 topo_node->event =
7302 7308 MPTSAS_DR_EVENT_OFFLINE_TARGET;
7303 7309 topo_node->devhdl = diskhandle;
7304 7310 topo_node->flags =
7305 7311 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED;
7306 7312 topo_node->object = (void *)ptgt;
7307 7313 if (topo_head == NULL) {
7308 7314 topo_head = topo_tail = topo_node;
7309 7315 } else {
7310 7316 topo_tail->next = topo_node;
7311 7317 topo_tail = topo_node;
7312 7318 }
7313 7319 break;
7314 7320 }
7315 7321 case MPI2_EVENT_IR_CHANGE_RC_UNHIDE:
7316 7322 case MPI2_EVENT_IR_CHANGE_RC_PD_DELETED:
7317 7323 {
7318 7324 /*
7319 7325 * The physical drive is released by a IR
7320 7326 * volume. But we cannot get the the physport
7321 7327 * or phynum from the event data, so we only
7322 7328 * can get the physport/phynum after SAS
7323 7329 * Device Page0 request for the devhdl.
7324 7330 */
7325 7331 topo_node = kmem_zalloc(
7326 7332 sizeof (mptsas_topo_change_list_t),
7327 7333 KM_SLEEP);
7328 7334 topo_node->mpt = mpt;
7329 7335 topo_node->un.phymask = 0;
7330 7336 topo_node->event =
7331 7337 MPTSAS_DR_EVENT_RECONFIG_TARGET;
7332 7338 topo_node->devhdl = diskhandle;
7333 7339 topo_node->flags =
7334 7340 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED;
7335 7341 topo_node->object = NULL;
7336 7342 mpt->m_port_chng = 1;
7337 7343 if (topo_head == NULL) {
7338 7344 topo_head = topo_tail = topo_node;
7339 7345 } else {
7340 7346 topo_tail->next = topo_node;
7341 7347 topo_tail = topo_node;
7342 7348 }
7343 7349 break;
7344 7350 }
7345 7351 default:
7346 7352 break;
7347 7353 }
7348 7354 }
7349 7355
7350 7356 if (topo_head != NULL) {
7351 7357 /*
7352 7358 * Launch DR taskq to handle topology change
7353 7359 */
7354 7360 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
7355 7361 mptsas_handle_dr, (void *)topo_head,
7356 7362 DDI_NOSLEEP)) != DDI_SUCCESS) {
7357 7363 mptsas_log(mpt, CE_NOTE, "mptsas start taskq "
7358 7364 "for handle SAS DR event failed. \n");
7359 7365 }
7360 7366 }
7361 7367 break;
7362 7368 }
7363 7369 default:
7364 7370 return (DDI_FAILURE);
7365 7371 }
7366 7372
7367 7373 return (DDI_SUCCESS);
7368 7374 }
7369 7375
7370 7376 /*
7371 7377 * handle events from ioc
7372 7378 */
7373 7379 static void
7374 7380 mptsas_handle_event(void *args)
7375 7381 {
7376 7382 m_replyh_arg_t *replyh_arg;
7377 7383 pMpi2EventNotificationReply_t eventreply;
7378 7384 uint32_t event, iocloginfo, rfm;
7379 7385 uint32_t status;
7380 7386 uint8_t port;
7381 7387 mptsas_t *mpt;
7382 7388 uint_t iocstatus;
7383 7389
7384 7390 replyh_arg = (m_replyh_arg_t *)args;
7385 7391 rfm = replyh_arg->rfm;
7386 7392 mpt = replyh_arg->mpt;
7387 7393
7388 7394 mutex_enter(&mpt->m_mutex);
7389 7395
7390 7396 eventreply = (pMpi2EventNotificationReply_t)
7391 7397 (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr));
7392 7398 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
7393 7399
7394 7400 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
7395 7401 &eventreply->IOCStatus)) {
7396 7402 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
7397 7403 mptsas_log(mpt, CE_WARN,
7398 7404 "!mptsas_handle_event: IOCStatus=0x%x, "
7399 7405 "IOCLogInfo=0x%x", iocstatus,
7400 7406 ddi_get32(mpt->m_acc_reply_frame_hdl,
7401 7407 &eventreply->IOCLogInfo));
7402 7408 } else {
7403 7409 mptsas_log(mpt, CE_WARN,
7404 7410 "mptsas_handle_event: IOCStatus=0x%x, "
7405 7411 "IOCLogInfo=0x%x", iocstatus,
7406 7412 ddi_get32(mpt->m_acc_reply_frame_hdl,
7407 7413 &eventreply->IOCLogInfo));
7408 7414 }
7409 7415 }
7410 7416
7411 7417 /*
7412 7418 * figure out what kind of event we got and handle accordingly
7413 7419 */
7414 7420 switch (event) {
7415 7421 case MPI2_EVENT_LOG_ENTRY_ADDED:
7416 7422 break;
7417 7423 case MPI2_EVENT_LOG_DATA:
7418 7424 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
7419 7425 &eventreply->IOCLogInfo);
7420 7426 NDBG20(("mptsas %d log info %x received.\n", mpt->m_instance,
7421 7427 iocloginfo));
7422 7428 break;
7423 7429 case MPI2_EVENT_STATE_CHANGE:
7424 7430 NDBG20(("mptsas%d state change.", mpt->m_instance));
7425 7431 break;
7426 7432 case MPI2_EVENT_HARD_RESET_RECEIVED:
7427 7433 NDBG20(("mptsas%d event change.", mpt->m_instance));
7428 7434 break;
7429 7435 case MPI2_EVENT_SAS_DISCOVERY:
7430 7436 {
7431 7437 MPI2_EVENT_DATA_SAS_DISCOVERY *sasdiscovery;
7432 7438 char string[80];
7433 7439 uint8_t rc;
7434 7440
7435 7441 sasdiscovery =
7436 7442 (pMpi2EventDataSasDiscovery_t)eventreply->EventData;
7437 7443
7438 7444 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7439 7445 &sasdiscovery->ReasonCode);
7440 7446 port = ddi_get8(mpt->m_acc_reply_frame_hdl,
7441 7447 &sasdiscovery->PhysicalPort);
7442 7448 status = ddi_get32(mpt->m_acc_reply_frame_hdl,
7443 7449 &sasdiscovery->DiscoveryStatus);
7444 7450
7445 7451 string[0] = 0;
7446 7452 switch (rc) {
7447 7453 case MPI2_EVENT_SAS_DISC_RC_STARTED:
7448 7454 (void) sprintf(string, "STARTING");
7449 7455 break;
7450 7456 case MPI2_EVENT_SAS_DISC_RC_COMPLETED:
7451 7457 (void) sprintf(string, "COMPLETED");
7452 7458 break;
7453 7459 default:
7454 7460 (void) sprintf(string, "UNKNOWN");
7455 7461 break;
7456 7462 }
7457 7463
7458 7464 NDBG20(("SAS DISCOVERY is %s for port %d, status %x", string,
7459 7465 port, status));
7460 7466
7461 7467 break;
7462 7468 }
7463 7469 case MPI2_EVENT_EVENT_CHANGE:
7464 7470 NDBG20(("mptsas%d event change.", mpt->m_instance));
7465 7471 break;
7466 7472 case MPI2_EVENT_TASK_SET_FULL:
7467 7473 {
7468 7474 pMpi2EventDataTaskSetFull_t taskfull;
7469 7475
7470 7476 taskfull = (pMpi2EventDataTaskSetFull_t)eventreply->EventData;
7471 7477
7472 7478 NDBG20(("TASK_SET_FULL received for mptsas%d, depth %d\n",
7473 7479 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl,
7474 7480 &taskfull->CurrentDepth)));
7475 7481 break;
7476 7482 }
7477 7483 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
7478 7484 {
7479 7485 /*
7480 7486 * SAS TOPOLOGY CHANGE LIST Event has already been handled
7481 7487 * in mptsas_handle_event_sync() of interrupt context
7482 7488 */
7483 7489 break;
7484 7490 }
7485 7491 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
7486 7492 {
7487 7493 pMpi2EventDataSasEnclDevStatusChange_t encstatus;
7488 7494 uint8_t rc;
7489 7495 char string[80];
7490 7496
7491 7497 encstatus = (pMpi2EventDataSasEnclDevStatusChange_t)
7492 7498 eventreply->EventData;
7493 7499
7494 7500 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7495 7501 &encstatus->ReasonCode);
7496 7502 switch (rc) {
7497 7503 case MPI2_EVENT_SAS_ENCL_RC_ADDED:
7498 7504 (void) sprintf(string, "added");
7499 7505 break;
7500 7506 case MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING:
7501 7507 (void) sprintf(string, ", not responding");
7502 7508 break;
7503 7509 default:
7504 7510 break;
7505 7511 }
7506 7512 NDBG20(("mptsas%d ENCLOSURE STATUS CHANGE for enclosure %x%s\n",
7507 7513 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl,
7508 7514 &encstatus->EnclosureHandle), string));
7509 7515 break;
7510 7516 }
7511 7517
7512 7518 /*
7513 7519 * MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE is handled by
7514 7520 * mptsas_handle_event_sync,in here just send ack message.
7515 7521 */
7516 7522 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
7517 7523 {
7518 7524 pMpi2EventDataSasDeviceStatusChange_t statuschange;
7519 7525 uint8_t rc;
7520 7526 uint16_t devhdl;
7521 7527 uint64_t wwn = 0;
7522 7528 uint32_t wwn_lo, wwn_hi;
7523 7529
7524 7530 statuschange = (pMpi2EventDataSasDeviceStatusChange_t)
7525 7531 eventreply->EventData;
7526 7532 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7527 7533 &statuschange->ReasonCode);
7528 7534 wwn_lo = ddi_get32(mpt->m_acc_reply_frame_hdl,
7529 7535 (uint32_t *)(void *)&statuschange->SASAddress);
7530 7536 wwn_hi = ddi_get32(mpt->m_acc_reply_frame_hdl,
7531 7537 (uint32_t *)(void *)&statuschange->SASAddress + 1);
7532 7538 wwn = ((uint64_t)wwn_hi << 32) | wwn_lo;
7533 7539 devhdl = ddi_get16(mpt->m_acc_reply_frame_hdl,
7534 7540 &statuschange->DevHandle);
7535 7541
7536 7542 NDBG13(("MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE wwn is %"PRIx64,
7537 7543 wwn));
7538 7544
7539 7545 switch (rc) {
7540 7546 case MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA:
7541 7547 NDBG20(("SMART data received, ASC/ASCQ = %02x/%02x",
7542 7548 ddi_get8(mpt->m_acc_reply_frame_hdl,
7543 7549 &statuschange->ASC),
7544 7550 ddi_get8(mpt->m_acc_reply_frame_hdl,
7545 7551 &statuschange->ASCQ)));
7546 7552 break;
7547 7553
7548 7554 case MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED:
7549 7555 NDBG20(("Device not supported"));
7550 7556 break;
7551 7557
7552 7558 case MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET:
7553 7559 NDBG20(("IOC internally generated the Target Reset "
7554 7560 "for devhdl:%x", devhdl));
7555 7561 break;
7556 7562
7557 7563 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET:
7558 7564 NDBG20(("IOC's internally generated Target Reset "
7559 7565 "completed for devhdl:%x", devhdl));
7560 7566 break;
7561 7567
7562 7568 case MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL:
7563 7569 NDBG20(("IOC internally generated Abort Task"));
7564 7570 break;
7565 7571
7566 7572 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL:
7567 7573 NDBG20(("IOC's internally generated Abort Task "
7568 7574 "completed"));
7569 7575 break;
7570 7576
7571 7577 case MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL:
7572 7578 NDBG20(("IOC internally generated Abort Task Set"));
7573 7579 break;
7574 7580
7575 7581 case MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL:
7576 7582 NDBG20(("IOC internally generated Clear Task Set"));
7577 7583 break;
7578 7584
7579 7585 case MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL:
7580 7586 NDBG20(("IOC internally generated Query Task"));
7581 7587 break;
7582 7588
7583 7589 case MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION:
7584 7590 NDBG20(("Device sent an Asynchronous Notification"));
7585 7591 break;
7586 7592
7587 7593 default:
7588 7594 break;
7589 7595 }
7590 7596 break;
7591 7597 }
7592 7598 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
7593 7599 {
7594 7600 /*
7595 7601 * IR TOPOLOGY CHANGE LIST Event has already been handled
7596 7602 * in mpt_handle_event_sync() of interrupt context
7597 7603 */
7598 7604 break;
7599 7605 }
7600 7606 case MPI2_EVENT_IR_OPERATION_STATUS:
7601 7607 {
7602 7608 Mpi2EventDataIrOperationStatus_t *irOpStatus;
7603 7609 char reason_str[80];
7604 7610 uint8_t rc, percent;
7605 7611 uint16_t handle;
7606 7612
7607 7613 irOpStatus = (pMpi2EventDataIrOperationStatus_t)
7608 7614 eventreply->EventData;
7609 7615 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7610 7616 &irOpStatus->RAIDOperation);
7611 7617 percent = ddi_get8(mpt->m_acc_reply_frame_hdl,
7612 7618 &irOpStatus->PercentComplete);
7613 7619 handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7614 7620 &irOpStatus->VolDevHandle);
7615 7621
7616 7622 switch (rc) {
7617 7623 case MPI2_EVENT_IR_RAIDOP_RESYNC:
7618 7624 (void) sprintf(reason_str, "resync");
7619 7625 break;
7620 7626 case MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION:
7621 7627 (void) sprintf(reason_str, "online capacity "
7622 7628 "expansion");
7623 7629 break;
7624 7630 case MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK:
7625 7631 (void) sprintf(reason_str, "consistency check");
7626 7632 break;
7627 7633 default:
7628 7634 (void) sprintf(reason_str, "unknown reason %x",
7629 7635 rc);
7630 7636 }
7631 7637
7632 7638 NDBG20(("mptsas%d raid operational status: (%s)"
7633 7639 "\thandle(0x%04x), percent complete(%d)\n",
7634 7640 mpt->m_instance, reason_str, handle, percent));
7635 7641 break;
7636 7642 }
7637 7643 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
7638 7644 {
7639 7645 pMpi2EventDataSasBroadcastPrimitive_t sas_broadcast;
7640 7646 uint8_t phy_num;
7641 7647 uint8_t primitive;
7642 7648
7643 7649 sas_broadcast = (pMpi2EventDataSasBroadcastPrimitive_t)
7644 7650 eventreply->EventData;
7645 7651
7646 7652 phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl,
7647 7653 &sas_broadcast->PhyNum);
7648 7654 primitive = ddi_get8(mpt->m_acc_reply_frame_hdl,
7649 7655 &sas_broadcast->Primitive);
7650 7656
7651 7657 switch (primitive) {
7652 7658 case MPI2_EVENT_PRIMITIVE_CHANGE:
7653 7659 mptsas_smhba_log_sysevent(mpt,
7654 7660 ESC_SAS_HBA_PORT_BROADCAST,
7655 7661 SAS_PORT_BROADCAST_CHANGE,
7656 7662 &mpt->m_phy_info[phy_num].smhba_info);
7657 7663 break;
7658 7664 case MPI2_EVENT_PRIMITIVE_SES:
7659 7665 mptsas_smhba_log_sysevent(mpt,
7660 7666 ESC_SAS_HBA_PORT_BROADCAST,
7661 7667 SAS_PORT_BROADCAST_SES,
7662 7668 &mpt->m_phy_info[phy_num].smhba_info);
7663 7669 break;
7664 7670 case MPI2_EVENT_PRIMITIVE_EXPANDER:
7665 7671 mptsas_smhba_log_sysevent(mpt,
7666 7672 ESC_SAS_HBA_PORT_BROADCAST,
7667 7673 SAS_PORT_BROADCAST_D01_4,
7668 7674 &mpt->m_phy_info[phy_num].smhba_info);
7669 7675 break;
7670 7676 case MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT:
7671 7677 mptsas_smhba_log_sysevent(mpt,
7672 7678 ESC_SAS_HBA_PORT_BROADCAST,
7673 7679 SAS_PORT_BROADCAST_D04_7,
7674 7680 &mpt->m_phy_info[phy_num].smhba_info);
7675 7681 break;
7676 7682 case MPI2_EVENT_PRIMITIVE_RESERVED3:
7677 7683 mptsas_smhba_log_sysevent(mpt,
7678 7684 ESC_SAS_HBA_PORT_BROADCAST,
7679 7685 SAS_PORT_BROADCAST_D16_7,
7680 7686 &mpt->m_phy_info[phy_num].smhba_info);
7681 7687 break;
7682 7688 case MPI2_EVENT_PRIMITIVE_RESERVED4:
7683 7689 mptsas_smhba_log_sysevent(mpt,
7684 7690 ESC_SAS_HBA_PORT_BROADCAST,
7685 7691 SAS_PORT_BROADCAST_D29_7,
7686 7692 &mpt->m_phy_info[phy_num].smhba_info);
7687 7693 break;
7688 7694 case MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED:
7689 7695 mptsas_smhba_log_sysevent(mpt,
7690 7696 ESC_SAS_HBA_PORT_BROADCAST,
7691 7697 SAS_PORT_BROADCAST_D24_0,
7692 7698 &mpt->m_phy_info[phy_num].smhba_info);
7693 7699 break;
7694 7700 case MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED:
7695 7701 mptsas_smhba_log_sysevent(mpt,
7696 7702 ESC_SAS_HBA_PORT_BROADCAST,
7697 7703 SAS_PORT_BROADCAST_D27_4,
7698 7704 &mpt->m_phy_info[phy_num].smhba_info);
7699 7705 break;
7700 7706 default:
7701 7707 NDBG20(("mptsas%d: unknown BROADCAST PRIMITIVE"
7702 7708 " %x received",
7703 7709 mpt->m_instance, primitive));
7704 7710 break;
7705 7711 }
7706 7712 NDBG20(("mptsas%d sas broadcast primitive: "
7707 7713 "\tprimitive(0x%04x), phy(%d) complete\n",
7708 7714 mpt->m_instance, primitive, phy_num));
7709 7715 break;
7710 7716 }
7711 7717 case MPI2_EVENT_IR_VOLUME:
7712 7718 {
7713 7719 Mpi2EventDataIrVolume_t *irVolume;
7714 7720 uint16_t devhandle;
7715 7721 uint32_t state;
7716 7722 int config, vol;
7717 7723 mptsas_slots_t *slots = mpt->m_active;
7718 7724 uint8_t found = FALSE;
7719 7725
7720 7726 irVolume = (pMpi2EventDataIrVolume_t)eventreply->EventData;
7721 7727 state = ddi_get32(mpt->m_acc_reply_frame_hdl,
7722 7728 &irVolume->NewValue);
7723 7729 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7724 7730 &irVolume->VolDevHandle);
7725 7731
7726 7732 NDBG20(("EVENT_IR_VOLUME event is received"));
7727 7733
7728 7734 /*
7729 7735 * Get latest RAID info and then find the DevHandle for this
7730 7736 * event in the configuration. If the DevHandle is not found
7731 7737 * just exit the event.
7732 7738 */
7733 7739 (void) mptsas_get_raid_info(mpt);
7734 7740 for (config = 0; (config < slots->m_num_raid_configs) &&
7735 7741 (!found); config++) {
7736 7742 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) {
7737 7743 if (slots->m_raidconfig[config].m_raidvol[vol].
7738 7744 m_raidhandle == devhandle) {
7739 7745 found = TRUE;
7740 7746 break;
7741 7747 }
7742 7748 }
7743 7749 }
7744 7750 if (!found) {
7745 7751 break;
7746 7752 }
7747 7753
7748 7754 switch (irVolume->ReasonCode) {
7749 7755 case MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED:
7750 7756 {
7751 7757 uint32_t i;
7752 7758 slots->m_raidconfig[config].m_raidvol[vol].m_settings =
7753 7759 state;
7754 7760
7755 7761 i = state & MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING;
7756 7762 mptsas_log(mpt, CE_NOTE, " Volume %d settings changed"
7757 7763 ", auto-config of hot-swap drives is %s"
7758 7764 ", write caching is %s"
7759 7765 ", hot-spare pool mask is %02x\n",
7760 7766 vol, state &
7761 7767 MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE
7762 7768 ? "disabled" : "enabled",
7763 7769 i == MPI2_RAIDVOL0_SETTING_UNCHANGED
7764 7770 ? "controlled by member disks" :
7765 7771 i == MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING
7766 7772 ? "disabled" :
7767 7773 i == MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING
7768 7774 ? "enabled" :
7769 7775 "incorrectly set",
7770 7776 (state >> 16) & 0xff);
7771 7777 break;
7772 7778 }
7773 7779 case MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED:
7774 7780 {
7775 7781 slots->m_raidconfig[config].m_raidvol[vol].m_state =
7776 7782 (uint8_t)state;
7777 7783
7778 7784 mptsas_log(mpt, CE_NOTE,
7779 7785 "Volume %d is now %s\n", vol,
7780 7786 state == MPI2_RAID_VOL_STATE_OPTIMAL
7781 7787 ? "optimal" :
7782 7788 state == MPI2_RAID_VOL_STATE_DEGRADED
7783 7789 ? "degraded" :
7784 7790 state == MPI2_RAID_VOL_STATE_ONLINE
7785 7791 ? "online" :
7786 7792 state == MPI2_RAID_VOL_STATE_INITIALIZING
7787 7793 ? "initializing" :
7788 7794 state == MPI2_RAID_VOL_STATE_FAILED
7789 7795 ? "failed" :
7790 7796 state == MPI2_RAID_VOL_STATE_MISSING
7791 7797 ? "missing" :
7792 7798 "state unknown");
7793 7799 break;
7794 7800 }
7795 7801 case MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED:
7796 7802 {
7797 7803 slots->m_raidconfig[config].m_raidvol[vol].
7798 7804 m_statusflags = state;
7799 7805
7800 7806 mptsas_log(mpt, CE_NOTE,
7801 7807 " Volume %d is now %s%s%s%s%s%s%s%s%s\n",
7802 7808 vol,
7803 7809 state & MPI2_RAIDVOL0_STATUS_FLAG_ENABLED
7804 7810 ? ", enabled" : ", disabled",
7805 7811 state & MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED
7806 7812 ? ", quiesced" : "",
7807 7813 state & MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE
7808 7814 ? ", inactive" : ", active",
7809 7815 state &
7810 7816 MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL
7811 7817 ? ", bad block table is full" : "",
7812 7818 state &
7813 7819 MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS
7814 7820 ? ", resync in progress" : "",
7815 7821 state & MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT
7816 7822 ? ", background initialization in progress" : "",
7817 7823 state &
7818 7824 MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION
7819 7825 ? ", capacity expansion in progress" : "",
7820 7826 state &
7821 7827 MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK
7822 7828 ? ", consistency check in progress" : "",
7823 7829 state & MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB
7824 7830 ? ", data scrub in progress" : "");
7825 7831 break;
7826 7832 }
7827 7833 default:
7828 7834 break;
7829 7835 }
7830 7836 break;
7831 7837 }
7832 7838 case MPI2_EVENT_IR_PHYSICAL_DISK:
7833 7839 {
7834 7840 Mpi2EventDataIrPhysicalDisk_t *irPhysDisk;
7835 7841 uint16_t devhandle, enchandle, slot;
7836 7842 uint32_t status, state;
7837 7843 uint8_t physdisknum, reason;
7838 7844
7839 7845 irPhysDisk = (Mpi2EventDataIrPhysicalDisk_t *)
7840 7846 eventreply->EventData;
7841 7847 physdisknum = ddi_get8(mpt->m_acc_reply_frame_hdl,
7842 7848 &irPhysDisk->PhysDiskNum);
7843 7849 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7844 7850 &irPhysDisk->PhysDiskDevHandle);
7845 7851 enchandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7846 7852 &irPhysDisk->EnclosureHandle);
7847 7853 slot = ddi_get16(mpt->m_acc_reply_frame_hdl,
7848 7854 &irPhysDisk->Slot);
7849 7855 state = ddi_get32(mpt->m_acc_reply_frame_hdl,
7850 7856 &irPhysDisk->NewValue);
7851 7857 reason = ddi_get8(mpt->m_acc_reply_frame_hdl,
7852 7858 &irPhysDisk->ReasonCode);
7853 7859
7854 7860 NDBG20(("EVENT_IR_PHYSICAL_DISK event is received"));
7855 7861
7856 7862 switch (reason) {
7857 7863 case MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED:
7858 7864 mptsas_log(mpt, CE_NOTE,
7859 7865 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
7860 7866 "for enclosure with handle 0x%x is now in hot "
7861 7867 "spare pool %d",
7862 7868 physdisknum, devhandle, slot, enchandle,
7863 7869 (state >> 16) & 0xff);
7864 7870 break;
7865 7871
7866 7872 case MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED:
7867 7873 status = state;
7868 7874 mptsas_log(mpt, CE_NOTE,
7869 7875 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
7870 7876 "for enclosure with handle 0x%x is now "
7871 7877 "%s%s%s%s%s\n", physdisknum, devhandle, slot,
7872 7878 enchandle,
7873 7879 status & MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME
7874 7880 ? ", inactive" : ", active",
7875 7881 status & MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC
7876 7882 ? ", out of sync" : "",
7877 7883 status & MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED
7878 7884 ? ", quiesced" : "",
7879 7885 status &
7880 7886 MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED
7881 7887 ? ", write cache enabled" : "",
7882 7888 status & MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET
7883 7889 ? ", capacity expansion target" : "");
7884 7890 break;
7885 7891
7886 7892 case MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED:
7887 7893 mptsas_log(mpt, CE_NOTE,
7888 7894 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
7889 7895 "for enclosure with handle 0x%x is now %s\n",
7890 7896 physdisknum, devhandle, slot, enchandle,
7891 7897 state == MPI2_RAID_PD_STATE_OPTIMAL
7892 7898 ? "optimal" :
7893 7899 state == MPI2_RAID_PD_STATE_REBUILDING
7894 7900 ? "rebuilding" :
7895 7901 state == MPI2_RAID_PD_STATE_DEGRADED
7896 7902 ? "degraded" :
7897 7903 state == MPI2_RAID_PD_STATE_HOT_SPARE
7898 7904 ? "a hot spare" :
7899 7905 state == MPI2_RAID_PD_STATE_ONLINE
7900 7906 ? "online" :
7901 7907 state == MPI2_RAID_PD_STATE_OFFLINE
7902 7908 ? "offline" :
7903 7909 state == MPI2_RAID_PD_STATE_NOT_COMPATIBLE
7904 7910 ? "not compatible" :
7905 7911 state == MPI2_RAID_PD_STATE_NOT_CONFIGURED
7906 7912 ? "not configured" :
7907 7913 "state unknown");
7908 7914 break;
7909 7915 }
7910 7916 break;
7911 7917 }
7912 7918 default:
7913 7919 NDBG20(("mptsas%d: unknown event %x received",
7914 7920 mpt->m_instance, event));
7915 7921 break;
7916 7922 }
7917 7923
7918 7924 /*
7919 7925 * Return the reply frame to the free queue.
7920 7926 */
7921 7927 ddi_put32(mpt->m_acc_free_queue_hdl,
7922 7928 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], rfm);
7923 7929 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
7924 7930 DDI_DMA_SYNC_FORDEV);
7925 7931 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
7926 7932 mpt->m_free_index = 0;
7927 7933 }
7928 7934 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
7929 7935 mpt->m_free_index);
7930 7936 mutex_exit(&mpt->m_mutex);
7931 7937 }
7932 7938
7933 7939 /*
7934 7940 * invoked from timeout() to restart qfull cmds with throttle == 0
7935 7941 */
7936 7942 static void
7937 7943 mptsas_restart_cmd(void *arg)
7938 7944 {
7939 7945 mptsas_t *mpt = arg;
7940 7946 mptsas_target_t *ptgt = NULL;
7941 7947
7942 7948 mutex_enter(&mpt->m_mutex);
7943 7949
7944 7950 mpt->m_restart_cmd_timeid = 0;
7945 7951
7946 7952 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
7947 7953 MPTSAS_HASH_FIRST);
7948 7954 while (ptgt != NULL) {
7949 7955 mutex_enter(&ptgt->m_tgt_intr_mutex);
7950 7956 if (ptgt->m_reset_delay == 0) {
7951 7957 if (ptgt->m_t_throttle == QFULL_THROTTLE) {
7952 7958 mptsas_set_throttle(mpt, ptgt,
7953 7959 MAX_THROTTLE);
7954 7960 }
7955 7961 }
7956 7962 mutex_exit(&ptgt->m_tgt_intr_mutex);
7957 7963
7958 7964 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
7959 7965 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
7960 7966 }
7961 7967 mptsas_restart_hba(mpt);
7962 7968 mutex_exit(&mpt->m_mutex);
7963 7969 }
7964 7970
7965 7971 /*
7966 7972 * mptsas_remove_cmd0 is similar to mptsas_remove_cmd except that it is called
7967 7973 * where m_intr_mutex has already been held.
7968 7974 */
7969 7975 void
7970 7976 mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
7971 7977 {
7972 7978 ASSERT(mutex_owned(&mpt->m_mutex));
7973 7979
7974 7980 /*
7975 7981 * With new fine-grained lock mechanism, the outstanding cmd is only
7976 7982 * linked to m_active before the dma is triggerred(MPTSAS_START_CMD)
7977 7983 * to send it. that is, mptsas_save_cmd() doesn't link the outstanding
7978 7984 * cmd now. So when mptsas_remove_cmd is called, a mptsas_save_cmd must
7979 7985 * have been called, but the cmd may have not been linked.
7980 7986 * For mptsas_remove_cmd0, the cmd must have been linked.
7981 7987 * In order to keep the same semantic, we link the cmd to the
7982 7988 * outstanding cmd list.
7983 7989 */
7984 7990 mpt->m_active->m_slot[cmd->cmd_slot] = cmd;
7985 7991
7986 7992 mutex_enter(&mpt->m_intr_mutex);
7987 7993 mptsas_remove_cmd0(mpt, cmd);
7988 7994 mutex_exit(&mpt->m_intr_mutex);
7989 7995 }
7990 7996
7991 7997 static inline void
7992 7998 mptsas_remove_cmd0(mptsas_t *mpt, mptsas_cmd_t *cmd)
7993 7999 {
7994 8000 int slot;
7995 8001 mptsas_slots_t *slots = mpt->m_active;
7996 8002 int t;
7997 8003 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
7998 8004 mptsas_slot_free_e_t *pe;
7999 8005
8000 8006 ASSERT(cmd != NULL);
8001 8007 ASSERT(cmd->cmd_queued == FALSE);
8002 8008
8003 8009 /*
8004 8010 * Task Management cmds are removed in their own routines. Also,
8005 8011 * we don't want to modify timeout based on TM cmds.
8006 8012 */
8007 8013 if (cmd->cmd_flags & CFLAG_TM_CMD) {
8008 8014 return;
8009 8015 }
8010 8016
8011 8017 t = Tgt(cmd);
8012 8018 slot = cmd->cmd_slot;
8013 8019 pe = mpt->m_slot_free_ae + slot - 1;
8014 8020 ASSERT(cmd == slots->m_slot[slot]);
8015 8021 ASSERT((slot > 0) && slot < (mpt->m_max_requests - 1));
8016 8022
8017 8023 /*
8018 8024 * remove the cmd.
8019 8025 */
8020 8026 mutex_enter(&mpt->m_slot_freeq_pairp[pe->cpuid].
8021 8027 m_slot_releq.s.m_fq_mutex);
8022 8028 NDBG31(("mptsas_remove_cmd0: removing cmd=0x%p", (void *)cmd));
8023 8029 slots->m_slot[slot] = NULL;
8024 8030 ASSERT(pe->slot == slot);
8025 8031 list_insert_tail(&mpt->m_slot_freeq_pairp[pe->cpuid].
8026 8032 m_slot_releq.s.m_fq_list, pe);
8027 8033 mpt->m_slot_freeq_pairp[pe->cpuid].m_slot_releq.s.m_fq_n++;
8028 8034 ASSERT(mpt->m_slot_freeq_pairp[pe->cpuid].
8029 8035 m_slot_releq.s.m_fq_n <= mpt->m_max_requests - 2);
8030 8036 mutex_exit(&mpt->m_slot_freeq_pairp[pe->cpuid].
8031 8037 m_slot_releq.s.m_fq_mutex);
8032 8038
8033 8039 /*
8034 8040 * only decrement per target ncmds if command
8035 8041 * has a target associated with it.
8036 8042 */
8037 8043 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
8038 8044 mutex_enter(&ptgt->m_tgt_intr_mutex);
8039 8045 ptgt->m_t_ncmds--;
8040 8046 /*
8041 8047 * reset throttle if we just ran an untagged command
8042 8048 * to a tagged target
8043 8049 */
8044 8050 if ((ptgt->m_t_ncmds == 0) &&
8045 8051 ((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0)) {
8046 8052 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
8047 8053 }
8048 8054 mutex_exit(&ptgt->m_tgt_intr_mutex);
8049 8055 }
8050 8056
8051 8057 /*
8052 8058 * This is all we need to do for ioc commands.
8053 8059 * The ioc cmds would never be handled in fastpath in ISR, so we make
8054 8060 * sure the mptsas_return_to_pool() would always be called with
8055 8061 * m_mutex protected.
8056 8062 */
8057 8063 if (cmd->cmd_flags & CFLAG_CMDIOC) {
8058 8064 ASSERT(mutex_owned(&mpt->m_mutex));
8059 8065 mptsas_return_to_pool(mpt, cmd);
8060 8066 return;
8061 8067 }
8062 8068
8063 8069 /*
8064 8070 * Figure out what to set tag Q timeout for...
8065 8071 *
8066 8072 * Optimize: If we have duplicate's of same timeout
8067 8073 * we're using, then we'll use it again until we run
8068 8074 * out of duplicates. This should be the normal case
8069 8075 * for block and raw I/O.
8070 8076 * If no duplicates, we have to scan through tag que and
8071 8077 * find the longest timeout value and use it. This is
8072 8078 * going to take a while...
8073 8079 * Add 1 to m_n_slots to account for TM request.
8074 8080 */
8075 8081 mutex_enter(&ptgt->m_tgt_intr_mutex);
8076 8082 if (cmd->cmd_pkt->pkt_time == ptgt->m_timebase) {
8077 8083 if (--(ptgt->m_dups) == 0) {
8078 8084 if (ptgt->m_t_ncmds) {
8079 8085 mptsas_cmd_t *ssp;
8080 8086 uint_t n = 0;
8081 8087 ushort_t nslots = (slots->m_n_slots + 1);
8082 8088 ushort_t i;
8083 8089 /*
8084 8090 * This crude check assumes we don't do
8085 8091 * this too often which seems reasonable
8086 8092 * for block and raw I/O.
8087 8093 */
8088 8094 for (i = 0; i < nslots; i++) {
8089 8095 ssp = slots->m_slot[i];
8090 8096 if (ssp && (Tgt(ssp) == t) &&
8091 8097 (ssp->cmd_pkt->pkt_time > n)) {
8092 8098 n = ssp->cmd_pkt->pkt_time;
8093 8099 ptgt->m_dups = 1;
8094 8100 } else if (ssp && (Tgt(ssp) == t) &&
8095 8101 (ssp->cmd_pkt->pkt_time == n)) {
8096 8102 ptgt->m_dups++;
8097 8103 }
8098 8104 }
8099 8105 ptgt->m_timebase = n;
8100 8106 } else {
8101 8107 ptgt->m_dups = 0;
8102 8108 ptgt->m_timebase = 0;
8103 8109 }
8104 8110 }
8105 8111 }
8106 8112 ptgt->m_timeout = ptgt->m_timebase;
8107 8113
8108 8114 ASSERT(cmd != slots->m_slot[cmd->cmd_slot]);
8109 8115 mutex_exit(&ptgt->m_tgt_intr_mutex);
8110 8116 }
8111 8117
8112 8118 /*
8113 8119 * start a fresh request from the top of the device queue.
8114 8120 */
8115 8121 static void
8116 8122 mptsas_restart_hba(mptsas_t *mpt)
8117 8123 {
8118 8124 mptsas_cmd_t *cmd, *next_cmd;
8119 8125 mptsas_target_t *ptgt = NULL;
8120 8126
8121 8127 NDBG1(("mptsas_restart_hba: mpt=0x%p", (void *)mpt));
8122 8128
8123 8129 ASSERT(mutex_owned(&mpt->m_mutex));
8124 8130
8125 8131 /*
8126 8132 * If there is a reset delay, don't start any cmds. Otherwise, start
8127 8133 * as many cmds as possible.
8128 8134 * Since SMID 0 is reserved and the TM slot is reserved, the actual max
8129 8135 * commands is m_max_requests - 2.
8130 8136 */
8131 8137 cmd = mpt->m_waitq;
8132 8138
8133 8139 while (cmd != NULL) {
8134 8140 next_cmd = cmd->cmd_linkp;
8135 8141 if (cmd->cmd_flags & CFLAG_PASSTHRU) {
8136 8142 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8137 8143 /*
8138 8144 * passthru command get slot need
8139 8145 * set CFLAG_PREPARED.
8140 8146 */
8141 8147 cmd->cmd_flags |= CFLAG_PREPARED;
8142 8148 mptsas_waitq_delete(mpt, cmd);
8143 8149 mptsas_start_passthru(mpt, cmd);
8144 8150 }
8145 8151 cmd = next_cmd;
8146 8152 continue;
8147 8153 }
8148 8154 if (cmd->cmd_flags & CFLAG_CONFIG) {
8149 8155 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8150 8156 /*
8151 8157 * Send the config page request and delete it
8152 8158 * from the waitq.
8153 8159 */
8154 8160 cmd->cmd_flags |= CFLAG_PREPARED;
8155 8161 mptsas_waitq_delete(mpt, cmd);
8156 8162 mptsas_start_config_page_access(mpt, cmd);
8157 8163 }
8158 8164 cmd = next_cmd;
8159 8165 continue;
8160 8166 }
8161 8167 if (cmd->cmd_flags & CFLAG_FW_DIAG) {
8162 8168 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8163 8169 /*
8164 8170 * Send the FW Diag request and delete if from
8165 8171 * the waitq.
8166 8172 */
8167 8173 cmd->cmd_flags |= CFLAG_PREPARED;
8168 8174 mptsas_waitq_delete(mpt, cmd);
8169 8175 mptsas_start_diag(mpt, cmd);
8170 8176 }
8171 8177 cmd = next_cmd;
8172 8178 continue;
8173 8179 }
8174 8180
8175 8181 ptgt = cmd->cmd_tgt_addr;
8176 8182 if (ptgt) {
8177 8183 mutex_enter(&mpt->m_intr_mutex);
8178 8184 mutex_enter(&ptgt->m_tgt_intr_mutex);
8179 8185 if ((ptgt->m_t_throttle == DRAIN_THROTTLE) &&
8180 8186 (ptgt->m_t_ncmds == 0)) {
8181 8187 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
8182 8188 }
8183 8189 if ((ptgt->m_reset_delay == 0) &&
8184 8190 (ptgt->m_t_ncmds < ptgt->m_t_throttle)) {
8185 8191 mutex_exit(&ptgt->m_tgt_intr_mutex);
8186 8192 mutex_exit(&mpt->m_intr_mutex);
8187 8193 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8188 8194 mptsas_waitq_delete(mpt, cmd);
8189 8195 (void) mptsas_start_cmd(mpt, cmd);
8190 8196 }
8191 8197 goto out;
8192 8198 }
8193 8199 mutex_exit(&ptgt->m_tgt_intr_mutex);
8194 8200 mutex_exit(&mpt->m_intr_mutex);
8195 8201 }
8196 8202 out:
8197 8203 cmd = next_cmd;
8198 8204 }
8199 8205 }
8200 8206
8201 8207 /*
8202 8208 * mpt tag type lookup
8203 8209 */
8204 8210 static char mptsas_tag_lookup[] =
8205 8211 {0, MSG_HEAD_QTAG, MSG_ORDERED_QTAG, 0, MSG_SIMPLE_QTAG};
8206 8212
8207 8213 /*
8208 8214 * mptsas_start_cmd0 is similar to mptsas_start_cmd, except that, it is called
8209 8215 * without ANY mutex protected, while, mptsas_start_cmd is called with m_mutex
8210 8216 * protected.
8211 8217 *
8212 8218 * the relevant field in ptgt should be protected by m_tgt_intr_mutex in both
8213 8219 * functions.
8214 8220 *
8215 8221 * before the cmds are linked on the slot for monitor as outstanding cmds, they
8216 8222 * are accessed as slab objects, so slab framework ensures the exclusive access,
8217 8223 * and no other mutex is requireed. Linking for monitor and the trigger of dma
8218 8224 * must be done exclusively.
8219 8225 */
8220 8226 static int
8221 8227 mptsas_start_cmd0(mptsas_t *mpt, mptsas_cmd_t *cmd)
8222 8228 {
8223 8229 struct scsi_pkt *pkt = CMD2PKT(cmd);
8224 8230 uint32_t control = 0;
8225 8231 int n;
8226 8232 caddr_t mem;
8227 8233 pMpi2SCSIIORequest_t io_request;
8228 8234 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl;
8229 8235 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl;
8230 8236 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8231 8237 uint16_t SMID, io_flags = 0;
8232 8238 uint32_t request_desc_low, request_desc_high;
8233 8239
8234 8240 NDBG1(("mptsas_start_cmd0: cmd=0x%p", (void *)cmd));
8235 8241
8236 8242 /*
8237 8243 * Set SMID and increment index. Rollover to 1 instead of 0 if index
8238 8244 * is at the max. 0 is an invalid SMID, so we call the first index 1.
8239 8245 */
8240 8246 SMID = cmd->cmd_slot;
8241 8247
8242 8248 /*
8243 8249 * It is possible for back to back device reset to
8244 8250 * happen before the reset delay has expired. That's
8245 8251 * ok, just let the device reset go out on the bus.
8246 8252 */
8247 8253 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
8248 8254 ASSERT(ptgt->m_reset_delay == 0);
8249 8255 }
8250 8256
8251 8257 /*
8252 8258 * if a non-tagged cmd is submitted to an active tagged target
8253 8259 * then drain before submitting this cmd; SCSI-2 allows RQSENSE
8254 8260 * to be untagged
8255 8261 */
8256 8262 mutex_enter(&ptgt->m_tgt_intr_mutex);
8257 8263 if (((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0) &&
8258 8264 (ptgt->m_t_ncmds > 1) &&
8259 8265 ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) &&
8260 8266 (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE)) {
8261 8267 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
8262 8268 NDBG23(("target=%d, untagged cmd, start draining\n",
8263 8269 ptgt->m_devhdl));
8264 8270
8265 8271 if (ptgt->m_reset_delay == 0) {
8266 8272 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
8267 8273 }
8268 8274 mutex_exit(&ptgt->m_tgt_intr_mutex);
8269 8275
8270 8276 mutex_enter(&mpt->m_mutex);
8271 8277 mptsas_remove_cmd(mpt, cmd);
8272 8278 cmd->cmd_pkt_flags |= FLAG_HEAD;
8273 8279 mptsas_waitq_add(mpt, cmd);
8274 8280 mutex_exit(&mpt->m_mutex);
8275 8281 return (DDI_FAILURE);
8276 8282 }
8277 8283 mutex_exit(&ptgt->m_tgt_intr_mutex);
8278 8284 return (DDI_FAILURE);
8279 8285 }
8280 8286 mutex_exit(&ptgt->m_tgt_intr_mutex);
8281 8287
8282 8288 /*
8283 8289 * Set correct tag bits.
8284 8290 */
8285 8291 if (cmd->cmd_pkt_flags & FLAG_TAGMASK) {
8286 8292 switch (mptsas_tag_lookup[((cmd->cmd_pkt_flags &
8287 8293 FLAG_TAGMASK) >> 12)]) {
8288 8294 case MSG_SIMPLE_QTAG:
8289 8295 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
8290 8296 break;
8291 8297 case MSG_HEAD_QTAG:
8292 8298 control |= MPI2_SCSIIO_CONTROL_HEADOFQ;
8293 8299 break;
8294 8300 case MSG_ORDERED_QTAG:
8295 8301 control |= MPI2_SCSIIO_CONTROL_ORDEREDQ;
8296 8302 break;
8297 8303 default:
8298 8304 mptsas_log(mpt, CE_WARN, "mpt: Invalid tag type\n");
8299 8305 break;
8300 8306 }
8301 8307 } else {
8302 8308 if (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE) {
8303 8309 ptgt->m_t_throttle = 1;
8304 8310 }
8305 8311 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
8306 8312 }
8307 8313
8308 8314 if (cmd->cmd_pkt_flags & FLAG_TLR) {
8309 8315 control |= MPI2_SCSIIO_CONTROL_TLR_ON;
8310 8316 }
8311 8317
8312 8318 mem = mpt->m_req_frame + (mpt->m_req_frame_size * SMID);
8313 8319 io_request = (pMpi2SCSIIORequest_t)mem;
8314 8320
8315 8321 bzero(io_request, sizeof (Mpi2SCSIIORequest_t));
8316 8322 ddi_put8(acc_hdl, &io_request->SGLOffset0, offsetof
8317 8323 (MPI2_SCSI_IO_REQUEST, SGL) / 4);
8318 8324 mptsas_init_std_hdr(acc_hdl, io_request, ptgt->m_devhdl, Lun(cmd), 0,
8319 8325 MPI2_FUNCTION_SCSI_IO_REQUEST);
8320 8326
8321 8327 (void) ddi_rep_put8(acc_hdl, (uint8_t *)pkt->pkt_cdbp,
8322 8328 io_request->CDB.CDB32, cmd->cmd_cdblen, DDI_DEV_AUTOINCR);
8323 8329
8324 8330 io_flags = cmd->cmd_cdblen;
8325 8331 ddi_put16(acc_hdl, &io_request->IoFlags, io_flags);
8326 8332 /*
8327 8333 * setup the Scatter/Gather DMA list for this request
8328 8334 */
8329 8335 if (cmd->cmd_cookiec > 0) {
8330 8336 mptsas_sge_setup(mpt, cmd, &control, io_request, acc_hdl);
8331 8337 } else {
8332 8338 ddi_put32(acc_hdl, &io_request->SGL.MpiSimple.FlagsLength,
8333 8339 ((uint32_t)MPI2_SGE_FLAGS_LAST_ELEMENT |
8334 8340 MPI2_SGE_FLAGS_END_OF_BUFFER |
8335 8341 MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
8336 8342 MPI2_SGE_FLAGS_END_OF_LIST) << MPI2_SGE_FLAGS_SHIFT);
8337 8343 }
8338 8344
8339 8345 /*
8340 8346 * save ARQ information
8341 8347 */
8342 8348 ddi_put8(acc_hdl, &io_request->SenseBufferLength, cmd->cmd_rqslen);
8343 8349 if ((cmd->cmd_flags & (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) ==
8344 8350 (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) {
8345 8351 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress,
8346 8352 cmd->cmd_ext_arqcookie.dmac_address);
8347 8353 } else {
8348 8354 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress,
8349 8355 cmd->cmd_arqcookie.dmac_address);
8350 8356 }
8351 8357
8352 8358 ddi_put32(acc_hdl, &io_request->Control, control);
8353 8359
8354 8360 NDBG31(("starting message=0x%p, with cmd=0x%p",
8355 8361 (void *)(uintptr_t)mpt->m_req_frame_dma_addr, (void *)cmd));
8356 8362
8357 8363 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
8358 8364
8359 8365 /*
8360 8366 * Build request descriptor and write it to the request desc post reg.
8361 8367 */
8362 8368 request_desc_low = (SMID << 16) + MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
8363 8369 request_desc_high = ptgt->m_devhdl << 16;
8364 8370
8365 8371 mutex_enter(&mpt->m_mutex);
8366 8372 mpt->m_active->m_slot[cmd->cmd_slot] = cmd;
8367 8373 MPTSAS_START_CMD(mpt, request_desc_low, request_desc_high);
8368 8374 mutex_exit(&mpt->m_mutex);
8369 8375
8370 8376 /*
8371 8377 * Start timeout.
8372 8378 */
8373 8379 mutex_enter(&ptgt->m_tgt_intr_mutex);
8374 8380 #ifdef MPTSAS_TEST
8375 8381 /*
8376 8382 * Temporarily set timebase = 0; needed for
8377 8383 * timeout torture test.
8378 8384 */
8379 8385 if (mptsas_test_timeouts) {
8380 8386 ptgt->m_timebase = 0;
8381 8387 }
8382 8388 #endif
8383 8389 n = pkt->pkt_time - ptgt->m_timebase;
8384 8390
8385 8391 if (n == 0) {
8386 8392 (ptgt->m_dups)++;
8387 8393 ptgt->m_timeout = ptgt->m_timebase;
8388 8394 } else if (n > 0) {
8389 8395 ptgt->m_timeout =
8390 8396 ptgt->m_timebase = pkt->pkt_time;
8391 8397 ptgt->m_dups = 1;
8392 8398 } else if (n < 0) {
8393 8399 ptgt->m_timeout = ptgt->m_timebase;
8394 8400 }
8395 8401 #ifdef MPTSAS_TEST
8396 8402 /*
8397 8403 * Set back to a number higher than
8398 8404 * mptsas_scsi_watchdog_tick
8399 8405 * so timeouts will happen in mptsas_watchsubr
8400 8406 */
8401 8407 if (mptsas_test_timeouts) {
8402 8408 ptgt->m_timebase = 60;
8403 8409 }
8404 8410 #endif
8405 8411 mutex_exit(&ptgt->m_tgt_intr_mutex);
8406 8412
8407 8413 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) ||
8408 8414 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) {
8409 8415 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8410 8416 return (DDI_FAILURE);
8411 8417 }
8412 8418 return (DDI_SUCCESS);
8413 8419 }
8414 8420
8415 8421 static int
8416 8422 mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
8417 8423 {
8418 8424 struct scsi_pkt *pkt = CMD2PKT(cmd);
8419 8425 uint32_t control = 0;
8420 8426 int n;
8421 8427 caddr_t mem;
8422 8428 pMpi2SCSIIORequest_t io_request;
8423 8429 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl;
8424 8430 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl;
8425 8431 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8426 8432 uint16_t SMID, io_flags = 0;
8427 8433 uint32_t request_desc_low, request_desc_high;
8428 8434
8429 8435 NDBG1(("mptsas_start_cmd: cmd=0x%p", (void *)cmd));
8430 8436
8431 8437 /*
8432 8438 * Set SMID and increment index. Rollover to 1 instead of 0 if index
8433 8439 * is at the max. 0 is an invalid SMID, so we call the first index 1.
8434 8440 */
8435 8441 SMID = cmd->cmd_slot;
8436 8442
8437 8443 /*
8438 8444 * It is possible for back to back device reset to
8439 8445 * happen before the reset delay has expired. That's
8440 8446 * ok, just let the device reset go out on the bus.
8441 8447 */
8442 8448 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
8443 8449 ASSERT(ptgt->m_reset_delay == 0);
8444 8450 }
8445 8451
8446 8452 /*
8447 8453 * if a non-tagged cmd is submitted to an active tagged target
8448 8454 * then drain before submitting this cmd; SCSI-2 allows RQSENSE
8449 8455 * to be untagged
8450 8456 */
8451 8457 mutex_enter(&ptgt->m_tgt_intr_mutex);
8452 8458 if (((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0) &&
8453 8459 (ptgt->m_t_ncmds > 1) &&
8454 8460 ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) &&
8455 8461 (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE)) {
8456 8462 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
8457 8463 NDBG23(("target=%d, untagged cmd, start draining\n",
8458 8464 ptgt->m_devhdl));
8459 8465
8460 8466 if (ptgt->m_reset_delay == 0) {
8461 8467 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
8462 8468 }
8463 8469 mutex_exit(&ptgt->m_tgt_intr_mutex);
8464 8470
8465 8471 mptsas_remove_cmd(mpt, cmd);
8466 8472 cmd->cmd_pkt_flags |= FLAG_HEAD;
8467 8473 mptsas_waitq_add(mpt, cmd);
8468 8474 return (DDI_FAILURE);
8469 8475 }
8470 8476 mutex_exit(&ptgt->m_tgt_intr_mutex);
8471 8477 return (DDI_FAILURE);
8472 8478 }
8473 8479 mutex_exit(&ptgt->m_tgt_intr_mutex);
8474 8480
8475 8481 /*
8476 8482 * Set correct tag bits.
8477 8483 */
8478 8484 if (cmd->cmd_pkt_flags & FLAG_TAGMASK) {
8479 8485 switch (mptsas_tag_lookup[((cmd->cmd_pkt_flags &
8480 8486 FLAG_TAGMASK) >> 12)]) {
8481 8487 case MSG_SIMPLE_QTAG:
8482 8488 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
8483 8489 break;
8484 8490 case MSG_HEAD_QTAG:
8485 8491 control |= MPI2_SCSIIO_CONTROL_HEADOFQ;
8486 8492 break;
8487 8493 case MSG_ORDERED_QTAG:
8488 8494 control |= MPI2_SCSIIO_CONTROL_ORDEREDQ;
8489 8495 break;
8490 8496 default:
8491 8497 mptsas_log(mpt, CE_WARN, "mpt: Invalid tag type\n");
8492 8498 break;
8493 8499 }
8494 8500 } else {
8495 8501 if (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE) {
8496 8502 ptgt->m_t_throttle = 1;
8497 8503 }
8498 8504 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
8499 8505 }
8500 8506
8501 8507 if (cmd->cmd_pkt_flags & FLAG_TLR) {
8502 8508 control |= MPI2_SCSIIO_CONTROL_TLR_ON;
8503 8509 }
8504 8510
8505 8511 mem = mpt->m_req_frame + (mpt->m_req_frame_size * SMID);
8506 8512 io_request = (pMpi2SCSIIORequest_t)mem;
8507 8513
8508 8514 bzero(io_request, sizeof (Mpi2SCSIIORequest_t));
8509 8515 ddi_put8(acc_hdl, &io_request->SGLOffset0, offsetof
8510 8516 (MPI2_SCSI_IO_REQUEST, SGL) / 4);
8511 8517 mptsas_init_std_hdr(acc_hdl, io_request, ptgt->m_devhdl, Lun(cmd), 0,
8512 8518 MPI2_FUNCTION_SCSI_IO_REQUEST);
8513 8519
8514 8520 (void) ddi_rep_put8(acc_hdl, (uint8_t *)pkt->pkt_cdbp,
8515 8521 io_request->CDB.CDB32, cmd->cmd_cdblen, DDI_DEV_AUTOINCR);
8516 8522
8517 8523 io_flags = cmd->cmd_cdblen;
8518 8524 ddi_put16(acc_hdl, &io_request->IoFlags, io_flags);
8519 8525 /*
8520 8526 * setup the Scatter/Gather DMA list for this request
8521 8527 */
8522 8528 if (cmd->cmd_cookiec > 0) {
8523 8529 mptsas_sge_setup(mpt, cmd, &control, io_request, acc_hdl);
8524 8530 } else {
8525 8531 ddi_put32(acc_hdl, &io_request->SGL.MpiSimple.FlagsLength,
8526 8532 ((uint32_t)MPI2_SGE_FLAGS_LAST_ELEMENT |
8527 8533 MPI2_SGE_FLAGS_END_OF_BUFFER |
8528 8534 MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
8529 8535 MPI2_SGE_FLAGS_END_OF_LIST) << MPI2_SGE_FLAGS_SHIFT);
8530 8536 }
8531 8537
8532 8538 /*
8533 8539 * save ARQ information
8534 8540 */
8535 8541 ddi_put8(acc_hdl, &io_request->SenseBufferLength, cmd->cmd_rqslen);
8536 8542 if ((cmd->cmd_flags & (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) ==
8537 8543 (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) {
8538 8544 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress,
8539 8545 cmd->cmd_ext_arqcookie.dmac_address);
8540 8546 } else {
8541 8547 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress,
8542 8548 cmd->cmd_arqcookie.dmac_address);
8543 8549 }
8544 8550
8545 8551 ddi_put32(acc_hdl, &io_request->Control, control);
8546 8552
8547 8553 NDBG31(("starting message=0x%p, with cmd=0x%p",
8548 8554 (void *)(uintptr_t)mpt->m_req_frame_dma_addr, (void *)cmd));
8549 8555
8550 8556 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
8551 8557
8552 8558 /*
8553 8559 * Build request descriptor and write it to the request desc post reg.
8554 8560 */
8555 8561 request_desc_low = (SMID << 16) + MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
8556 8562 request_desc_high = ptgt->m_devhdl << 16;
8557 8563
8558 8564 mpt->m_active->m_slot[cmd->cmd_slot] = cmd;
8559 8565 MPTSAS_START_CMD(mpt, request_desc_low, request_desc_high);
8560 8566
8561 8567 /*
8562 8568 * Start timeout.
8563 8569 */
8564 8570 mutex_enter(&ptgt->m_tgt_intr_mutex);
8565 8571 #ifdef MPTSAS_TEST
8566 8572 /*
8567 8573 * Temporarily set timebase = 0; needed for
8568 8574 * timeout torture test.
8569 8575 */
8570 8576 if (mptsas_test_timeouts) {
8571 8577 ptgt->m_timebase = 0;
8572 8578 }
8573 8579 #endif
8574 8580 n = pkt->pkt_time - ptgt->m_timebase;
8575 8581
8576 8582 if (n == 0) {
8577 8583 (ptgt->m_dups)++;
8578 8584 ptgt->m_timeout = ptgt->m_timebase;
8579 8585 } else if (n > 0) {
8580 8586 ptgt->m_timeout =
8581 8587 ptgt->m_timebase = pkt->pkt_time;
8582 8588 ptgt->m_dups = 1;
8583 8589 } else if (n < 0) {
8584 8590 ptgt->m_timeout = ptgt->m_timebase;
8585 8591 }
8586 8592 #ifdef MPTSAS_TEST
8587 8593 /*
8588 8594 * Set back to a number higher than
8589 8595 * mptsas_scsi_watchdog_tick
8590 8596 * so timeouts will happen in mptsas_watchsubr
8591 8597 */
8592 8598 if (mptsas_test_timeouts) {
8593 8599 ptgt->m_timebase = 60;
8594 8600 }
8595 8601 #endif
8596 8602 mutex_exit(&ptgt->m_tgt_intr_mutex);
8597 8603
8598 8604 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) ||
8599 8605 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) {
8600 8606 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8601 8607 return (DDI_FAILURE);
8602 8608 }
8603 8609 return (DDI_SUCCESS);
8604 8610 }
8605 8611
8606 8612 /*
8607 8613 * Select a helper thread to handle current doneq
8608 8614 */
8609 8615 static void
8610 8616 mptsas_deliver_doneq_thread(mptsas_t *mpt)
8611 8617 {
8612 8618 uint64_t t, i;
8613 8619 uint32_t min = 0xffffffff;
8614 8620 mptsas_doneq_thread_list_t *item;
8615 8621
8616 8622 for (i = 0; i < mpt->m_doneq_thread_n; i++) {
8617 8623 item = &mpt->m_doneq_thread_id[i];
8618 8624 /*
8619 8625 * If the completed command on help thread[i] less than
8620 8626 * doneq_thread_threshold, then pick the thread[i]. Otherwise
8621 8627 * pick a thread which has least completed command.
8622 8628 */
8623 8629
8624 8630 mutex_enter(&item->mutex);
8625 8631 if (item->len < mpt->m_doneq_thread_threshold) {
8626 8632 t = i;
8627 8633 mutex_exit(&item->mutex);
8628 8634 break;
8629 8635 }
8630 8636 if (item->len < min) {
8631 8637 min = item->len;
8632 8638 t = i;
8633 8639 }
8634 8640 mutex_exit(&item->mutex);
8635 8641 }
8636 8642 mutex_enter(&mpt->m_doneq_thread_id[t].mutex);
8637 8643 mptsas_doneq_mv(mpt, t);
8638 8644 cv_signal(&mpt->m_doneq_thread_id[t].cv);
8639 8645 mutex_exit(&mpt->m_doneq_thread_id[t].mutex);
8640 8646 }
8641 8647
8642 8648 /*
8643 8649 * move the current global doneq to the doneq of thread[t]
8644 8650 */
8645 8651 static void
8646 8652 mptsas_doneq_mv(mptsas_t *mpt, uint64_t t)
8647 8653 {
8648 8654 mptsas_cmd_t *cmd;
8649 8655 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
8650 8656
8651 8657 ASSERT(mutex_owned(&item->mutex));
8652 8658 mutex_enter(&mpt->m_intr_mutex);
8653 8659 while ((cmd = mpt->m_doneq) != NULL) {
8654 8660 if ((mpt->m_doneq = cmd->cmd_linkp) == NULL) {
8655 8661 mpt->m_donetail = &mpt->m_doneq;
8656 8662 }
8657 8663 cmd->cmd_linkp = NULL;
8658 8664 *item->donetail = cmd;
8659 8665 item->donetail = &cmd->cmd_linkp;
8660 8666 mpt->m_doneq_len--;
8661 8667 item->len++;
8662 8668 }
8663 8669 mutex_exit(&mpt->m_intr_mutex);
8664 8670 }
8665 8671
8666 8672 void
8667 8673 mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd)
8668 8674 {
8669 8675 struct scsi_pkt *pkt = CMD2PKT(cmd);
8670 8676
8671 8677 /* Check all acc and dma handles */
8672 8678 if ((mptsas_check_acc_handle(mpt->m_datap) !=
8673 8679 DDI_SUCCESS) ||
8674 8680 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
8675 8681 DDI_SUCCESS) ||
8676 8682 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) !=
8677 8683 DDI_SUCCESS) ||
8678 8684 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) !=
8679 8685 DDI_SUCCESS) ||
8680 8686 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) !=
8681 8687 DDI_SUCCESS) ||
8682 8688 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) !=
8683 8689 DDI_SUCCESS) ||
8684 8690 (mptsas_check_acc_handle(mpt->m_config_handle) !=
8685 8691 DDI_SUCCESS)) {
8686 8692 ddi_fm_service_impact(mpt->m_dip,
8687 8693 DDI_SERVICE_UNAFFECTED);
8688 8694 ddi_fm_acc_err_clear(mpt->m_config_handle,
8689 8695 DDI_FME_VER0);
8690 8696 pkt->pkt_reason = CMD_TRAN_ERR;
8691 8697 pkt->pkt_statistics = 0;
8692 8698 }
8693 8699 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
8694 8700 DDI_SUCCESS) ||
8695 8701 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) !=
8696 8702 DDI_SUCCESS) ||
8697 8703 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) !=
8698 8704 DDI_SUCCESS) ||
8699 8705 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) !=
8700 8706 DDI_SUCCESS) ||
8701 8707 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) !=
8702 8708 DDI_SUCCESS)) {
8703 8709 ddi_fm_service_impact(mpt->m_dip,
8704 8710 DDI_SERVICE_UNAFFECTED);
8705 8711 pkt->pkt_reason = CMD_TRAN_ERR;
8706 8712 pkt->pkt_statistics = 0;
8707 8713 }
8708 8714 if (cmd->cmd_dmahandle &&
8709 8715 (mptsas_check_dma_handle(cmd->cmd_dmahandle) != DDI_SUCCESS)) {
8710 8716 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8711 8717 pkt->pkt_reason = CMD_TRAN_ERR;
8712 8718 pkt->pkt_statistics = 0;
8713 8719 }
8714 8720 if ((cmd->cmd_extra_frames &&
8715 8721 ((mptsas_check_dma_handle(cmd->cmd_extra_frames->m_dma_hdl) !=
8716 8722 DDI_SUCCESS) ||
8717 8723 (mptsas_check_acc_handle(cmd->cmd_extra_frames->m_acc_hdl) !=
8718 8724 DDI_SUCCESS)))) {
8719 8725 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8720 8726 pkt->pkt_reason = CMD_TRAN_ERR;
8721 8727 pkt->pkt_statistics = 0;
8722 8728 }
8723 8729 if (cmd->cmd_arqhandle &&
8724 8730 (mptsas_check_dma_handle(cmd->cmd_arqhandle) != DDI_SUCCESS)) {
8725 8731 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8726 8732 pkt->pkt_reason = CMD_TRAN_ERR;
8727 8733 pkt->pkt_statistics = 0;
8728 8734 }
8729 8735 if (cmd->cmd_ext_arqhandle &&
8730 8736 (mptsas_check_dma_handle(cmd->cmd_ext_arqhandle) != DDI_SUCCESS)) {
8731 8737 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8732 8738 pkt->pkt_reason = CMD_TRAN_ERR;
8733 8739 pkt->pkt_statistics = 0;
8734 8740 }
8735 8741 }
8736 8742
8737 8743 /*
8738 8744 * mptsas_doneq_add0 is similar to mptsas_doneq_add except that it is called
8739 8745 * where m_intr_mutex has already been held.
8740 8746 */
8741 8747 static inline void
8742 8748 mptsas_doneq_add0(mptsas_t *mpt, mptsas_cmd_t *cmd)
8743 8749 {
8744 8750 struct scsi_pkt *pkt = CMD2PKT(cmd);
8745 8751
8746 8752 NDBG31(("mptsas_doneq_add0: cmd=0x%p", (void *)cmd));
8747 8753
8748 8754 ASSERT((cmd->cmd_flags & CFLAG_COMPLETED) == 0);
8749 8755 cmd->cmd_linkp = NULL;
8750 8756 cmd->cmd_flags |= CFLAG_FINISHED;
8751 8757 cmd->cmd_flags &= ~CFLAG_IN_TRANSPORT;
8752 8758
8753 8759 /*
8754 8760 * only add scsi pkts that have completion routines to
8755 8761 * the doneq. no intr cmds do not have callbacks.
8756 8762 */
8757 8763 if (pkt && (pkt->pkt_comp)) {
8758 8764 *mpt->m_donetail = cmd;
8759 8765 mpt->m_donetail = &cmd->cmd_linkp;
8760 8766 mpt->m_doneq_len++;
8761 8767 }
8762 8768 }
8763 8769
8764 8770 /*
8765 8771 * These routines manipulate the queue of commands that
8766 8772 * are waiting for their completion routines to be called.
8767 8773 * The queue is usually in FIFO order but on an MP system
8768 8774 * it's possible for the completion routines to get out
8769 8775 * of order. If that's a problem you need to add a global
8770 8776 * mutex around the code that calls the completion routine
8771 8777 * in the interrupt handler.
8772 8778 */
8773 8779 static void
8774 8780 mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd)
8775 8781 {
8776 8782 ASSERT(mutex_owned(&mpt->m_mutex));
8777 8783
8778 8784 mptsas_fma_check(mpt, cmd);
8779 8785
8780 8786 mutex_enter(&mpt->m_intr_mutex);
8781 8787 mptsas_doneq_add0(mpt, cmd);
8782 8788 mutex_exit(&mpt->m_intr_mutex);
8783 8789 }
8784 8790
8785 8791 static mptsas_cmd_t *
8786 8792 mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t)
8787 8793 {
8788 8794 mptsas_cmd_t *cmd;
8789 8795 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
8790 8796
8791 8797 /* pop one off the done queue */
8792 8798 if ((cmd = item->doneq) != NULL) {
8793 8799 /* if the queue is now empty fix the tail pointer */
8794 8800 NDBG31(("mptsas_doneq_thread_rm: cmd=0x%p", (void *)cmd));
8795 8801 if ((item->doneq = cmd->cmd_linkp) == NULL) {
8796 8802 item->donetail = &item->doneq;
8797 8803 }
8798 8804 cmd->cmd_linkp = NULL;
8799 8805 item->len--;
8800 8806 }
8801 8807 return (cmd);
8802 8808 }
8803 8809
8804 8810 static void
8805 8811 mptsas_doneq_empty(mptsas_t *mpt)
8806 8812 {
8807 8813 mutex_enter(&mpt->m_intr_mutex);
8808 8814 if (mpt->m_doneq && !mpt->m_in_callback) {
8809 8815 mptsas_cmd_t *cmd, *next;
8810 8816 struct scsi_pkt *pkt;
8811 8817
8812 8818 mpt->m_in_callback = 1;
8813 8819 cmd = mpt->m_doneq;
8814 8820 mpt->m_doneq = NULL;
8815 8821 mpt->m_donetail = &mpt->m_doneq;
8816 8822 mpt->m_doneq_len = 0;
8817 8823
8818 8824 mutex_exit(&mpt->m_intr_mutex);
8819 8825
8820 8826 /*
8821 8827 * ONLY in ISR, is it called without m_mutex held, otherwise,
8822 8828 * it is always called with m_mutex held.
8823 8829 */
8824 8830 if ((curthread->t_flag & T_INTR_THREAD) == 0)
8825 8831 mutex_exit(&mpt->m_mutex);
8826 8832 /*
8827 8833 * run the completion routines of all the
8828 8834 * completed commands
8829 8835 */
8830 8836 while (cmd != NULL) {
8831 8837 next = cmd->cmd_linkp;
8832 8838 cmd->cmd_linkp = NULL;
8833 8839 /* run this command's completion routine */
8834 8840 cmd->cmd_flags |= CFLAG_COMPLETED;
8835 8841 pkt = CMD2PKT(cmd);
8836 8842 mptsas_pkt_comp(pkt, cmd);
8837 8843 cmd = next;
8838 8844 }
8839 8845 if ((curthread->t_flag & T_INTR_THREAD) == 0)
8840 8846 mutex_enter(&mpt->m_mutex);
8841 8847 mpt->m_in_callback = 0;
8842 8848 return;
8843 8849 }
8844 8850 mutex_exit(&mpt->m_intr_mutex);
8845 8851 }
8846 8852
8847 8853 /*
8848 8854 * These routines manipulate the target's queue of pending requests
8849 8855 */
8850 8856 void
8851 8857 mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd)
8852 8858 {
8853 8859 NDBG7(("mptsas_waitq_add: cmd=0x%p", (void *)cmd));
8854 8860 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8855 8861 cmd->cmd_queued = TRUE;
8856 8862 if (ptgt)
8857 8863 ptgt->m_t_nwait++;
8858 8864 if (cmd->cmd_pkt_flags & FLAG_HEAD) {
8859 8865 mutex_enter(&mpt->m_intr_mutex);
8860 8866 if ((cmd->cmd_linkp = mpt->m_waitq) == NULL) {
8861 8867 mpt->m_waitqtail = &cmd->cmd_linkp;
8862 8868 }
8863 8869 mpt->m_waitq = cmd;
8864 8870 mutex_exit(&mpt->m_intr_mutex);
8865 8871 } else {
8866 8872 cmd->cmd_linkp = NULL;
8867 8873 *(mpt->m_waitqtail) = cmd;
8868 8874 mpt->m_waitqtail = &cmd->cmd_linkp;
8869 8875 }
8870 8876 }
8871 8877
8872 8878 static mptsas_cmd_t *
8873 8879 mptsas_waitq_rm(mptsas_t *mpt)
8874 8880 {
8875 8881 mptsas_cmd_t *cmd;
8876 8882 mptsas_target_t *ptgt;
8877 8883 NDBG7(("mptsas_waitq_rm"));
8878 8884
8879 8885 mutex_enter(&mpt->m_intr_mutex);
8880 8886 MPTSAS_WAITQ_RM(mpt, cmd);
8881 8887 mutex_exit(&mpt->m_intr_mutex);
8882 8888
8883 8889 NDBG7(("mptsas_waitq_rm: cmd=0x%p", (void *)cmd));
8884 8890 if (cmd) {
8885 8891 ptgt = cmd->cmd_tgt_addr;
8886 8892 if (ptgt) {
8887 8893 ptgt->m_t_nwait--;
8888 8894 ASSERT(ptgt->m_t_nwait >= 0);
8889 8895 }
8890 8896 }
8891 8897 return (cmd);
8892 8898 }
8893 8899
8894 8900 /*
8895 8901 * remove specified cmd from the middle of the wait queue.
8896 8902 */
8897 8903 static void
8898 8904 mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd)
8899 8905 {
8900 8906 mptsas_cmd_t *prevp = mpt->m_waitq;
8901 8907 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8902 8908
8903 8909 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
8904 8910 (void *)mpt, (void *)cmd));
8905 8911 if (ptgt) {
8906 8912 ptgt->m_t_nwait--;
8907 8913 ASSERT(ptgt->m_t_nwait >= 0);
8908 8914 }
8909 8915
8910 8916 if (prevp == cmd) {
8911 8917 mutex_enter(&mpt->m_intr_mutex);
8912 8918 if ((mpt->m_waitq = cmd->cmd_linkp) == NULL)
8913 8919 mpt->m_waitqtail = &mpt->m_waitq;
8914 8920 mutex_exit(&mpt->m_intr_mutex);
8915 8921
8916 8922 cmd->cmd_linkp = NULL;
8917 8923 cmd->cmd_queued = FALSE;
8918 8924 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
8919 8925 (void *)mpt, (void *)cmd));
8920 8926 return;
8921 8927 }
8922 8928
8923 8929 while (prevp != NULL) {
8924 8930 if (prevp->cmd_linkp == cmd) {
8925 8931 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL)
8926 8932 mpt->m_waitqtail = &prevp->cmd_linkp;
8927 8933
8928 8934 cmd->cmd_linkp = NULL;
8929 8935 cmd->cmd_queued = FALSE;
8930 8936 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
8931 8937 (void *)mpt, (void *)cmd));
8932 8938 return;
8933 8939 }
8934 8940 prevp = prevp->cmd_linkp;
8935 8941 }
8936 8942 cmn_err(CE_PANIC, "mpt: mptsas_waitq_delete: queue botch");
8937 8943 }
8938 8944
8939 8945 /*
8940 8946 * device and bus reset handling
8941 8947 *
8942 8948 * Notes:
8943 8949 * - RESET_ALL: reset the controller
8944 8950 * - RESET_TARGET: reset the target specified in scsi_address
8945 8951 */
8946 8952 static int
8947 8953 mptsas_scsi_reset(struct scsi_address *ap, int level)
8948 8954 {
8949 8955 mptsas_t *mpt = ADDR2MPT(ap);
8950 8956 int rval;
8951 8957 mptsas_tgt_private_t *tgt_private;
8952 8958 mptsas_target_t *ptgt = NULL;
8953 8959
8954 8960 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->tran_tgt_private;
8955 8961 ptgt = tgt_private->t_private;
8956 8962 if (ptgt == NULL) {
8957 8963 return (FALSE);
8958 8964 }
8959 8965 NDBG22(("mptsas_scsi_reset: target=%d level=%d", ptgt->m_devhdl,
8960 8966 level));
8961 8967
8962 8968 mutex_enter(&mpt->m_mutex);
8963 8969 /*
8964 8970 * if we are not in panic set up a reset delay for this target
8965 8971 */
8966 8972 if (!ddi_in_panic()) {
8967 8973 mptsas_setup_bus_reset_delay(mpt);
8968 8974 } else {
8969 8975 drv_usecwait(mpt->m_scsi_reset_delay * 1000);
8970 8976 }
8971 8977 rval = mptsas_do_scsi_reset(mpt, ptgt->m_devhdl);
8972 8978 mutex_exit(&mpt->m_mutex);
8973 8979
8974 8980 /*
8975 8981 * The transport layer expect to only see TRUE and
8976 8982 * FALSE. Therefore, we will adjust the return value
8977 8983 * if mptsas_do_scsi_reset returns FAILED.
8978 8984 */
8979 8985 if (rval == FAILED)
8980 8986 rval = FALSE;
8981 8987 return (rval);
8982 8988 }
8983 8989
8984 8990 static int
8985 8991 mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl)
8986 8992 {
8987 8993 int rval = FALSE;
8988 8994 uint8_t config, disk;
8989 8995 mptsas_slots_t *slots = mpt->m_active;
8990 8996
8991 8997 ASSERT(mutex_owned(&mpt->m_mutex));
8992 8998
8993 8999 if (mptsas_debug_resets) {
8994 9000 mptsas_log(mpt, CE_WARN, "mptsas_do_scsi_reset: target=%d",
8995 9001 devhdl);
8996 9002 }
8997 9003
8998 9004 /*
8999 9005 * Issue a Target Reset message to the target specified but not to a
9000 9006 * disk making up a raid volume. Just look through the RAID config
9001 9007 * Phys Disk list of DevHandles. If the target's DevHandle is in this
9002 9008 * list, then don't reset this target.
9003 9009 */
9004 9010 for (config = 0; config < slots->m_num_raid_configs; config++) {
9005 9011 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) {
9006 9012 if (devhdl == slots->m_raidconfig[config].
9007 9013 m_physdisk_devhdl[disk]) {
9008 9014 return (TRUE);
9009 9015 }
9010 9016 }
9011 9017 }
9012 9018
9013 9019 rval = mptsas_ioc_task_management(mpt,
9014 9020 MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, devhdl, 0, NULL, 0, 0);
9015 9021
9016 9022 mptsas_doneq_empty(mpt);
9017 9023 return (rval);
9018 9024 }
9019 9025
9020 9026 static int
9021 9027 mptsas_scsi_reset_notify(struct scsi_address *ap, int flag,
9022 9028 void (*callback)(caddr_t), caddr_t arg)
9023 9029 {
9024 9030 mptsas_t *mpt = ADDR2MPT(ap);
9025 9031
9026 9032 NDBG22(("mptsas_scsi_reset_notify: tgt=%d", ap->a_target));
9027 9033
9028 9034 return (scsi_hba_reset_notify_setup(ap, flag, callback, arg,
9029 9035 &mpt->m_mutex, &mpt->m_reset_notify_listf));
9030 9036 }
9031 9037
9032 9038 static int
9033 9039 mptsas_get_name(struct scsi_device *sd, char *name, int len)
9034 9040 {
9035 9041 dev_info_t *lun_dip = NULL;
9036 9042
9037 9043 ASSERT(sd != NULL);
9038 9044 ASSERT(name != NULL);
9039 9045 lun_dip = sd->sd_dev;
9040 9046 ASSERT(lun_dip != NULL);
9041 9047
9042 9048 if (mptsas_name_child(lun_dip, name, len) == DDI_SUCCESS) {
9043 9049 return (1);
9044 9050 } else {
9045 9051 return (0);
9046 9052 }
9047 9053 }
9048 9054
9049 9055 static int
9050 9056 mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len)
9051 9057 {
9052 9058 return (mptsas_get_name(sd, name, len));
9053 9059 }
9054 9060
9055 9061 void
9056 9062 mptsas_set_throttle(mptsas_t *mpt, mptsas_target_t *ptgt, int what)
9057 9063 {
9058 9064
9059 9065 NDBG25(("mptsas_set_throttle: throttle=%x", what));
9060 9066
9061 9067 /*
9062 9068 * if the bus is draining/quiesced, no changes to the throttles
9063 9069 * are allowed. Not allowing change of throttles during draining
9064 9070 * limits error recovery but will reduce draining time
9065 9071 *
9066 9072 * all throttles should have been set to HOLD_THROTTLE
9067 9073 */
9068 9074 if (mpt->m_softstate & (MPTSAS_SS_QUIESCED | MPTSAS_SS_DRAINING)) {
9069 9075 return;
9070 9076 }
9071 9077
9072 9078 if (what == HOLD_THROTTLE) {
9073 9079 ptgt->m_t_throttle = HOLD_THROTTLE;
9074 9080 } else if (ptgt->m_reset_delay == 0) {
9075 9081 ptgt->m_t_throttle = what;
9076 9082 }
9077 9083 }
9078 9084
9079 9085 /*
9080 9086 * Clean up from a device reset.
9081 9087 * For the case of target reset, this function clears the waitq of all
9082 9088 * commands for a particular target. For the case of abort task set, this
9083 9089 * function clears the waitq of all commonds for a particular target/lun.
9084 9090 */
9085 9091 static void
9086 9092 mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, uint8_t tasktype)
9087 9093 {
9088 9094 mptsas_slots_t *slots = mpt->m_active;
9089 9095 mptsas_cmd_t *cmd, *next_cmd;
9090 9096 int slot;
9091 9097 uchar_t reason;
9092 9098 uint_t stat;
9093 9099
9094 9100 NDBG25(("mptsas_flush_target: target=%d lun=%d", target, lun));
9095 9101
9096 9102 /*
9097 9103 * Make sure the I/O Controller has flushed all cmds
9098 9104 * that are associated with this target for a target reset
9099 9105 * and target/lun for abort task set.
9100 9106 * Account for TM requests, which use the last SMID.
9101 9107 */
9102 9108 mutex_enter(&mpt->m_intr_mutex);
9103 9109 for (slot = 0; slot <= mpt->m_active->m_n_slots; slot++) {
9104 9110 if ((cmd = slots->m_slot[slot]) == NULL) {
9105 9111 continue;
9106 9112 }
9107 9113 reason = CMD_RESET;
9108 9114 stat = STAT_DEV_RESET;
9109 9115 switch (tasktype) {
9110 9116 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
9111 9117 if (Tgt(cmd) == target) {
9112 9118 NDBG25(("mptsas_flush_target discovered non-"
9113 9119 "NULL cmd in slot %d, tasktype 0x%x", slot,
9114 9120 tasktype));
9115 9121 mptsas_dump_cmd(mpt, cmd);
9116 9122 mptsas_remove_cmd0(mpt, cmd);
9117 9123 mptsas_set_pkt_reason(mpt, cmd, reason, stat);
9118 9124 mptsas_doneq_add0(mpt, cmd);
9119 9125 }
9120 9126 break;
9121 9127 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
9122 9128 reason = CMD_ABORTED;
9123 9129 stat = STAT_ABORTED;
9124 9130 /*FALLTHROUGH*/
9125 9131 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
9126 9132 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
9127 9133
9128 9134 NDBG25(("mptsas_flush_target discovered non-"
9129 9135 "NULL cmd in slot %d, tasktype 0x%x", slot,
9130 9136 tasktype));
9131 9137 mptsas_dump_cmd(mpt, cmd);
9132 9138 mptsas_remove_cmd0(mpt, cmd);
9133 9139 mptsas_set_pkt_reason(mpt, cmd, reason,
9134 9140 stat);
9135 9141 mptsas_doneq_add0(mpt, cmd);
9136 9142 }
9137 9143 break;
9138 9144 default:
9139 9145 break;
9140 9146 }
9141 9147 }
9142 9148 mutex_exit(&mpt->m_intr_mutex);
9143 9149
9144 9150 /*
9145 9151 * Flush the waitq of this target's cmds
9146 9152 */
9147 9153 cmd = mpt->m_waitq;
9148 9154
9149 9155 reason = CMD_RESET;
9150 9156 stat = STAT_DEV_RESET;
9151 9157
9152 9158 switch (tasktype) {
9153 9159 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
9154 9160 while (cmd != NULL) {
9155 9161 next_cmd = cmd->cmd_linkp;
9156 9162 if (Tgt(cmd) == target) {
9157 9163 mptsas_waitq_delete(mpt, cmd);
9158 9164 mptsas_set_pkt_reason(mpt, cmd,
9159 9165 reason, stat);
9160 9166 mptsas_doneq_add(mpt, cmd);
9161 9167 }
9162 9168 cmd = next_cmd;
9163 9169 }
9164 9170 break;
9165 9171 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
9166 9172 reason = CMD_ABORTED;
9167 9173 stat = STAT_ABORTED;
9168 9174 /*FALLTHROUGH*/
9169 9175 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
9170 9176 while (cmd != NULL) {
9171 9177 next_cmd = cmd->cmd_linkp;
9172 9178 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
9173 9179 mptsas_waitq_delete(mpt, cmd);
9174 9180 mptsas_set_pkt_reason(mpt, cmd,
9175 9181 reason, stat);
9176 9182 mptsas_doneq_add(mpt, cmd);
9177 9183 }
9178 9184 cmd = next_cmd;
9179 9185 }
9180 9186 break;
9181 9187 default:
9182 9188 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.",
9183 9189 tasktype);
9184 9190 break;
9185 9191 }
9186 9192 }
9187 9193
9188 9194 /*
9189 9195 * Clean up hba state, abort all outstanding command and commands in waitq
9190 9196 * reset timeout of all targets.
9191 9197 */
9192 9198 static void
9193 9199 mptsas_flush_hba(mptsas_t *mpt)
9194 9200 {
9195 9201 mptsas_slots_t *slots = mpt->m_active;
9196 9202 mptsas_cmd_t *cmd;
9197 9203 int slot;
9198 9204
9199 9205 NDBG25(("mptsas_flush_hba"));
9200 9206
9201 9207 /*
9202 9208 * The I/O Controller should have already sent back
9203 9209 * all commands via the scsi I/O reply frame. Make
9204 9210 * sure all commands have been flushed.
9205 9211 * Account for TM request, which use the last SMID.
9206 9212 */
9207 9213 mutex_enter(&mpt->m_intr_mutex);
9208 9214 for (slot = 0; slot <= mpt->m_active->m_n_slots; slot++) {
9209 9215 if ((cmd = slots->m_slot[slot]) == NULL) {
9210 9216 continue;
9211 9217 }
9212 9218
9213 9219 if (cmd->cmd_flags & CFLAG_CMDIOC) {
9214 9220 /*
9215 9221 * Need to make sure to tell everyone that might be
9216 9222 * waiting on this command that it's going to fail. If
9217 9223 * we get here, this command will never timeout because
9218 9224 * the active command table is going to be re-allocated,
9219 9225 * so there will be nothing to check against a time out.
9220 9226 * Instead, mark the command as failed due to reset.
9221 9227 */
9222 9228 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET,
9223 9229 STAT_BUS_RESET);
9224 9230 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
9225 9231 (cmd->cmd_flags & CFLAG_CONFIG) ||
9226 9232 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
9227 9233 cmd->cmd_flags |= CFLAG_FINISHED;
9228 9234 cv_broadcast(&mpt->m_passthru_cv);
9229 9235 cv_broadcast(&mpt->m_config_cv);
9230 9236 cv_broadcast(&mpt->m_fw_diag_cv);
9231 9237 }
9232 9238 continue;
9233 9239 }
9234 9240
9235 9241 NDBG25(("mptsas_flush_hba discovered non-NULL cmd in slot %d",
9236 9242 slot));
9237 9243 mptsas_dump_cmd(mpt, cmd);
9238 9244
9239 9245 mptsas_remove_cmd0(mpt, cmd);
9240 9246 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
9241 9247 mptsas_doneq_add0(mpt, cmd);
9242 9248 }
9243 9249 mutex_exit(&mpt->m_intr_mutex);
9244 9250
9245 9251 /*
9246 9252 * Flush the waitq.
9247 9253 */
9248 9254 while ((cmd = mptsas_waitq_rm(mpt)) != NULL) {
9249 9255 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
9250 9256 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
9251 9257 (cmd->cmd_flags & CFLAG_CONFIG) ||
9252 9258 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
9253 9259 cmd->cmd_flags |= CFLAG_FINISHED;
9254 9260 cv_broadcast(&mpt->m_passthru_cv);
9255 9261 cv_broadcast(&mpt->m_config_cv);
9256 9262 cv_broadcast(&mpt->m_fw_diag_cv);
9257 9263 } else {
9258 9264 mptsas_doneq_add(mpt, cmd);
9259 9265 }
9260 9266 }
9261 9267 }
9262 9268
9263 9269 /*
9264 9270 * set pkt_reason and OR in pkt_statistics flag
9265 9271 */
9266 9272 static void
9267 9273 mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, uchar_t reason,
9268 9274 uint_t stat)
9269 9275 {
9270 9276 #ifndef __lock_lint
9271 9277 _NOTE(ARGUNUSED(mpt))
9272 9278 #endif
9273 9279
9274 9280 NDBG25(("mptsas_set_pkt_reason: cmd=0x%p reason=%x stat=%x",
9275 9281 (void *)cmd, reason, stat));
9276 9282
9277 9283 if (cmd) {
9278 9284 if (cmd->cmd_pkt->pkt_reason == CMD_CMPLT) {
9279 9285 cmd->cmd_pkt->pkt_reason = reason;
9280 9286 }
9281 9287 cmd->cmd_pkt->pkt_statistics |= stat;
9282 9288 }
9283 9289 }
9284 9290
9285 9291 static void
9286 9292 mptsas_start_watch_reset_delay()
9287 9293 {
9288 9294 NDBG22(("mptsas_start_watch_reset_delay"));
9289 9295
9290 9296 mutex_enter(&mptsas_global_mutex);
9291 9297 if (mptsas_reset_watch == NULL && mptsas_timeouts_enabled) {
9292 9298 mptsas_reset_watch = timeout(mptsas_watch_reset_delay, NULL,
9293 9299 drv_usectohz((clock_t)
9294 9300 MPTSAS_WATCH_RESET_DELAY_TICK * 1000));
9295 9301 ASSERT(mptsas_reset_watch != NULL);
9296 9302 }
9297 9303 mutex_exit(&mptsas_global_mutex);
9298 9304 }
9299 9305
9300 9306 static void
9301 9307 mptsas_setup_bus_reset_delay(mptsas_t *mpt)
9302 9308 {
9303 9309 mptsas_target_t *ptgt = NULL;
9304 9310
9305 9311 NDBG22(("mptsas_setup_bus_reset_delay"));
9306 9312 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
9307 9313 MPTSAS_HASH_FIRST);
9308 9314 while (ptgt != NULL) {
9309 9315 mutex_enter(&ptgt->m_tgt_intr_mutex);
9310 9316 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
9311 9317 ptgt->m_reset_delay = mpt->m_scsi_reset_delay;
9312 9318 mutex_exit(&ptgt->m_tgt_intr_mutex);
9313 9319
9314 9320 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9315 9321 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9316 9322 }
9317 9323
9318 9324 mptsas_start_watch_reset_delay();
9319 9325 }
9320 9326
9321 9327 /*
9322 9328 * mptsas_watch_reset_delay(_subr) is invoked by timeout() and checks every
9323 9329 * mpt instance for active reset delays
9324 9330 */
9325 9331 static void
9326 9332 mptsas_watch_reset_delay(void *arg)
9327 9333 {
9328 9334 #ifndef __lock_lint
9329 9335 _NOTE(ARGUNUSED(arg))
9330 9336 #endif
9331 9337
9332 9338 mptsas_t *mpt;
9333 9339 int not_done = 0;
9334 9340
9335 9341 NDBG22(("mptsas_watch_reset_delay"));
9336 9342
9337 9343 mutex_enter(&mptsas_global_mutex);
9338 9344 mptsas_reset_watch = 0;
9339 9345 mutex_exit(&mptsas_global_mutex);
9340 9346 rw_enter(&mptsas_global_rwlock, RW_READER);
9341 9347 for (mpt = mptsas_head; mpt != NULL; mpt = mpt->m_next) {
9342 9348 if (mpt->m_tran == 0) {
9343 9349 continue;
9344 9350 }
9345 9351 mutex_enter(&mpt->m_mutex);
9346 9352 not_done += mptsas_watch_reset_delay_subr(mpt);
9347 9353 mutex_exit(&mpt->m_mutex);
9348 9354 }
9349 9355 rw_exit(&mptsas_global_rwlock);
9350 9356
9351 9357 if (not_done) {
9352 9358 mptsas_start_watch_reset_delay();
9353 9359 }
9354 9360 }
9355 9361
9356 9362 static int
9357 9363 mptsas_watch_reset_delay_subr(mptsas_t *mpt)
9358 9364 {
9359 9365 int done = 0;
9360 9366 int restart = 0;
9361 9367 mptsas_target_t *ptgt = NULL;
9362 9368
9363 9369 NDBG22(("mptsas_watch_reset_delay_subr: mpt=0x%p", (void *)mpt));
9364 9370
9365 9371 ASSERT(mutex_owned(&mpt->m_mutex));
9366 9372
9367 9373 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
9368 9374 MPTSAS_HASH_FIRST);
9369 9375 while (ptgt != NULL) {
9370 9376 mutex_enter(&ptgt->m_tgt_intr_mutex);
9371 9377 if (ptgt->m_reset_delay != 0) {
9372 9378 ptgt->m_reset_delay -=
9373 9379 MPTSAS_WATCH_RESET_DELAY_TICK;
9374 9380 if (ptgt->m_reset_delay <= 0) {
9375 9381 ptgt->m_reset_delay = 0;
9376 9382 mptsas_set_throttle(mpt, ptgt,
9377 9383 MAX_THROTTLE);
9378 9384 restart++;
9379 9385 } else {
9380 9386 done = -1;
9381 9387 }
9382 9388 }
9383 9389 mutex_exit(&ptgt->m_tgt_intr_mutex);
9384 9390
9385 9391 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9386 9392 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9387 9393 }
9388 9394
9389 9395 if (restart > 0) {
9390 9396 mptsas_restart_hba(mpt);
9391 9397 }
9392 9398 return (done);
9393 9399 }
9394 9400
9395 9401 #ifdef MPTSAS_TEST
9396 9402 static void
9397 9403 mptsas_test_reset(mptsas_t *mpt, int target)
9398 9404 {
9399 9405 mptsas_target_t *ptgt = NULL;
9400 9406
9401 9407 if (mptsas_rtest == target) {
9402 9408 if (mptsas_do_scsi_reset(mpt, target) == TRUE) {
9403 9409 mptsas_rtest = -1;
9404 9410 }
9405 9411 if (mptsas_rtest == -1) {
9406 9412 NDBG22(("mptsas_test_reset success"));
9407 9413 }
9408 9414 }
9409 9415 }
9410 9416 #endif
9411 9417
9412 9418 /*
9413 9419 * abort handling:
9414 9420 *
9415 9421 * Notes:
9416 9422 * - if pkt is not NULL, abort just that command
9417 9423 * - if pkt is NULL, abort all outstanding commands for target
9418 9424 */
9419 9425 static int
9420 9426 mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt)
9421 9427 {
9422 9428 mptsas_t *mpt = ADDR2MPT(ap);
9423 9429 int rval;
9424 9430 mptsas_tgt_private_t *tgt_private;
9425 9431 int target, lun;
9426 9432
9427 9433 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->
9428 9434 tran_tgt_private;
9429 9435 ASSERT(tgt_private != NULL);
9430 9436 target = tgt_private->t_private->m_devhdl;
9431 9437 lun = tgt_private->t_lun;
9432 9438
9433 9439 NDBG23(("mptsas_scsi_abort: target=%d.%d", target, lun));
9434 9440
9435 9441 mutex_enter(&mpt->m_mutex);
9436 9442 rval = mptsas_do_scsi_abort(mpt, target, lun, pkt);
9437 9443 mutex_exit(&mpt->m_mutex);
9438 9444 return (rval);
9439 9445 }
9440 9446
9441 9447 static int
9442 9448 mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, struct scsi_pkt *pkt)
9443 9449 {
9444 9450 mptsas_cmd_t *sp = NULL;
9445 9451 mptsas_slots_t *slots = mpt->m_active;
9446 9452 int rval = FALSE;
9447 9453
9448 9454 ASSERT(mutex_owned(&mpt->m_mutex));
9449 9455
9450 9456 /*
9451 9457 * Abort the command pkt on the target/lun in ap. If pkt is
9452 9458 * NULL, abort all outstanding commands on that target/lun.
9453 9459 * If you can abort them, return 1, else return 0.
9454 9460 * Each packet that's aborted should be sent back to the target
9455 9461 * driver through the callback routine, with pkt_reason set to
9456 9462 * CMD_ABORTED.
9457 9463 *
9458 9464 * abort cmd pkt on HBA hardware; clean out of outstanding
9459 9465 * command lists, etc.
9460 9466 */
9461 9467 if (pkt != NULL) {
9462 9468 /* abort the specified packet */
9463 9469 sp = PKT2CMD(pkt);
9464 9470
9465 9471 if (sp->cmd_queued) {
9466 9472 NDBG23(("mptsas_do_scsi_abort: queued sp=0x%p aborted",
9467 9473 (void *)sp));
9468 9474 mptsas_waitq_delete(mpt, sp);
9469 9475 mptsas_set_pkt_reason(mpt, sp, CMD_ABORTED,
9470 9476 STAT_ABORTED);
9471 9477 mptsas_doneq_add(mpt, sp);
9472 9478 rval = TRUE;
9473 9479 goto done;
9474 9480 }
9475 9481
9476 9482 /*
9477 9483 * Have mpt firmware abort this command
9478 9484 */
9479 9485 mutex_enter(&mpt->m_intr_mutex);
9480 9486 if (slots->m_slot[sp->cmd_slot] != NULL) {
9481 9487 mutex_exit(&mpt->m_intr_mutex);
9482 9488 rval = mptsas_ioc_task_management(mpt,
9483 9489 MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK, target,
9484 9490 lun, NULL, 0, 0);
9485 9491
9486 9492 /*
9487 9493 * The transport layer expects only TRUE and FALSE.
9488 9494 * Therefore, if mptsas_ioc_task_management returns
9489 9495 * FAILED we will return FALSE.
9490 9496 */
9491 9497 if (rval == FAILED)
9492 9498 rval = FALSE;
9493 9499 goto done;
9494 9500 }
9495 9501 mutex_exit(&mpt->m_intr_mutex);
9496 9502 }
9497 9503
9498 9504 /*
9499 9505 * If pkt is NULL then abort task set
9500 9506 */
9501 9507 rval = mptsas_ioc_task_management(mpt,
9502 9508 MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET, target, lun, NULL, 0, 0);
9503 9509
9504 9510 /*
9505 9511 * The transport layer expects only TRUE and FALSE.
9506 9512 * Therefore, if mptsas_ioc_task_management returns
9507 9513 * FAILED we will return FALSE.
9508 9514 */
9509 9515 if (rval == FAILED)
9510 9516 rval = FALSE;
9511 9517
9512 9518 #ifdef MPTSAS_TEST
9513 9519 if (rval && mptsas_test_stop) {
9514 9520 debug_enter("mptsas_do_scsi_abort");
9515 9521 }
9516 9522 #endif
9517 9523
9518 9524 done:
9519 9525 mptsas_doneq_empty(mpt);
9520 9526 return (rval);
9521 9527 }
9522 9528
9523 9529 /*
9524 9530 * capability handling:
9525 9531 * (*tran_getcap). Get the capability named, and return its value.
9526 9532 */
9527 9533 static int
9528 9534 mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly)
9529 9535 {
9530 9536 mptsas_t *mpt = ADDR2MPT(ap);
9531 9537 int ckey;
9532 9538 int rval = FALSE;
9533 9539
9534 9540 NDBG24(("mptsas_scsi_getcap: target=%d, cap=%s tgtonly=%x",
9535 9541 ap->a_target, cap, tgtonly));
9536 9542
9537 9543 mutex_enter(&mpt->m_mutex);
9538 9544
9539 9545 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) {
9540 9546 mutex_exit(&mpt->m_mutex);
9541 9547 return (UNDEFINED);
9542 9548 }
9543 9549
9544 9550 switch (ckey) {
9545 9551 case SCSI_CAP_DMA_MAX:
9546 9552 rval = (int)mpt->m_msg_dma_attr.dma_attr_maxxfer;
9547 9553 break;
9548 9554 case SCSI_CAP_ARQ:
9549 9555 rval = TRUE;
9550 9556 break;
9551 9557 case SCSI_CAP_MSG_OUT:
9552 9558 case SCSI_CAP_PARITY:
9553 9559 case SCSI_CAP_UNTAGGED_QING:
9554 9560 rval = TRUE;
9555 9561 break;
9556 9562 case SCSI_CAP_TAGGED_QING:
9557 9563 rval = TRUE;
9558 9564 break;
9559 9565 case SCSI_CAP_RESET_NOTIFICATION:
9560 9566 rval = TRUE;
9561 9567 break;
9562 9568 case SCSI_CAP_LINKED_CMDS:
9563 9569 rval = FALSE;
9564 9570 break;
9565 9571 case SCSI_CAP_QFULL_RETRIES:
9566 9572 rval = ((mptsas_tgt_private_t *)(ap->a_hba_tran->
9567 9573 tran_tgt_private))->t_private->m_qfull_retries;
9568 9574 break;
9569 9575 case SCSI_CAP_QFULL_RETRY_INTERVAL:
9570 9576 rval = drv_hztousec(((mptsas_tgt_private_t *)
9571 9577 (ap->a_hba_tran->tran_tgt_private))->
9572 9578 t_private->m_qfull_retry_interval) / 1000;
9573 9579 break;
9574 9580 case SCSI_CAP_CDB_LEN:
9575 9581 rval = CDB_GROUP4;
9576 9582 break;
9577 9583 case SCSI_CAP_INTERCONNECT_TYPE:
9578 9584 rval = INTERCONNECT_SAS;
9579 9585 break;
9580 9586 case SCSI_CAP_TRAN_LAYER_RETRIES:
9581 9587 if (mpt->m_ioc_capabilities &
9582 9588 MPI2_IOCFACTS_CAPABILITY_TLR)
9583 9589 rval = TRUE;
9584 9590 else
9585 9591 rval = FALSE;
9586 9592 break;
9587 9593 default:
9588 9594 rval = UNDEFINED;
9589 9595 break;
9590 9596 }
9591 9597
9592 9598 NDBG24(("mptsas_scsi_getcap: %s, rval=%x", cap, rval));
9593 9599
9594 9600 mutex_exit(&mpt->m_mutex);
9595 9601 return (rval);
9596 9602 }
9597 9603
9598 9604 /*
9599 9605 * (*tran_setcap). Set the capability named to the value given.
9600 9606 */
9601 9607 static int
9602 9608 mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, int tgtonly)
9603 9609 {
9604 9610 mptsas_t *mpt = ADDR2MPT(ap);
9605 9611 int ckey;
9606 9612 int rval = FALSE;
9607 9613 mptsas_target_t *ptgt;
9608 9614
9609 9615 NDBG24(("mptsas_scsi_setcap: target=%d, cap=%s value=%x tgtonly=%x",
9610 9616 ap->a_target, cap, value, tgtonly));
9611 9617
9612 9618 if (!tgtonly) {
9613 9619 return (rval);
9614 9620 }
9615 9621
9616 9622 mutex_enter(&mpt->m_mutex);
9617 9623
9618 9624 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) {
9619 9625 mutex_exit(&mpt->m_mutex);
9620 9626 return (UNDEFINED);
9621 9627 }
9622 9628
9623 9629 switch (ckey) {
9624 9630 case SCSI_CAP_DMA_MAX:
9625 9631 case SCSI_CAP_MSG_OUT:
9626 9632 case SCSI_CAP_PARITY:
9627 9633 case SCSI_CAP_INITIATOR_ID:
9628 9634 case SCSI_CAP_LINKED_CMDS:
9629 9635 case SCSI_CAP_UNTAGGED_QING:
9630 9636 case SCSI_CAP_RESET_NOTIFICATION:
9631 9637 /*
9632 9638 * None of these are settable via
9633 9639 * the capability interface.
9634 9640 */
9635 9641 break;
9636 9642 case SCSI_CAP_ARQ:
9637 9643 /*
9638 9644 * We cannot turn off arq so return false if asked to
9639 9645 */
9640 9646 if (value) {
9641 9647 rval = TRUE;
9642 9648 } else {
9643 9649 rval = FALSE;
9644 9650 }
9645 9651 break;
9646 9652 case SCSI_CAP_TAGGED_QING:
9647 9653 ptgt = ((mptsas_tgt_private_t *)
9648 9654 (ap->a_hba_tran->tran_tgt_private))->t_private;
9649 9655 mutex_enter(&ptgt->m_tgt_intr_mutex);
9650 9656 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
9651 9657 mutex_exit(&ptgt->m_tgt_intr_mutex);
9652 9658 rval = TRUE;
9653 9659 break;
9654 9660 case SCSI_CAP_QFULL_RETRIES:
9655 9661 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))->
9656 9662 t_private->m_qfull_retries = (uchar_t)value;
9657 9663 rval = TRUE;
9658 9664 break;
9659 9665 case SCSI_CAP_QFULL_RETRY_INTERVAL:
9660 9666 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))->
9661 9667 t_private->m_qfull_retry_interval =
9662 9668 drv_usectohz(value * 1000);
9663 9669 rval = TRUE;
9664 9670 break;
9665 9671 default:
9666 9672 rval = UNDEFINED;
9667 9673 break;
9668 9674 }
9669 9675 mutex_exit(&mpt->m_mutex);
9670 9676 return (rval);
9671 9677 }
9672 9678
9673 9679 /*
9674 9680 * Utility routine for mptsas_ifsetcap/ifgetcap
9675 9681 */
9676 9682 /*ARGSUSED*/
9677 9683 static int
9678 9684 mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp)
9679 9685 {
9680 9686 NDBG24(("mptsas_scsi_capchk: cap=%s", cap));
9681 9687
9682 9688 if (!cap)
9683 9689 return (FALSE);
9684 9690
9685 9691 *cidxp = scsi_hba_lookup_capstr(cap);
9686 9692 return (TRUE);
9687 9693 }
9688 9694
9689 9695 static int
9690 9696 mptsas_alloc_active_slots(mptsas_t *mpt, int flag)
9691 9697 {
9692 9698 mptsas_slots_t *old_active = mpt->m_active;
9693 9699 mptsas_slots_t *new_active;
9694 9700 size_t size;
9695 9701 int rval = -1, nslot, i;
9696 9702 mptsas_slot_free_e_t *pe;
9697 9703
9698 9704 if (mptsas_outstanding_cmds_n(mpt)) {
9699 9705 NDBG9(("cannot change size of active slots array"));
9700 9706 return (rval);
9701 9707 }
9702 9708
9703 9709 size = MPTSAS_SLOTS_SIZE(mpt);
9704 9710 new_active = kmem_zalloc(size, flag);
9705 9711 if (new_active == NULL) {
9706 9712 NDBG1(("new active alloc failed"));
9707 9713 return (rval);
9708 9714 }
9709 9715 /*
9710 9716 * Since SMID 0 is reserved and the TM slot is reserved, the
9711 9717 * number of slots that can be used at any one time is
9712 9718 * m_max_requests - 2.
9713 9719 */
9714 9720 new_active->m_n_slots = nslot = (mpt->m_max_requests - 2);
9715 9721 new_active->m_size = size;
9716 9722 new_active->m_tags = 1;
9717 9723
9718 9724 if (old_active) {
9719 9725 new_active->m_tgttbl = old_active->m_tgttbl;
9720 9726 new_active->m_smptbl = old_active->m_smptbl;
9721 9727 new_active->m_num_raid_configs =
9722 9728 old_active->m_num_raid_configs;
9723 9729 for (i = 0; i < new_active->m_num_raid_configs; i++) {
9724 9730 new_active->m_raidconfig[i] =
9725 9731 old_active->m_raidconfig[i];
9726 9732 }
9727 9733 mptsas_free_active_slots(mpt);
9728 9734 }
9729 9735
9730 9736 if (max_ncpus & (max_ncpus - 1)) {
9731 9737 mpt->m_slot_freeq_pair_n = (1 << highbit(max_ncpus));
9732 9738 } else {
9733 9739 mpt->m_slot_freeq_pair_n = max_ncpus;
9734 9740 }
9735 9741 mpt->m_slot_freeq_pairp = kmem_zalloc(
9736 9742 mpt->m_slot_freeq_pair_n *
9737 9743 sizeof (mptsas_slot_freeq_pair_t), KM_SLEEP);
9738 9744 for (i = 0; i < mpt->m_slot_freeq_pair_n; i++) {
9739 9745 list_create(&mpt->m_slot_freeq_pairp[i].
9740 9746 m_slot_allocq.s.m_fq_list,
9741 9747 sizeof (mptsas_slot_free_e_t),
9742 9748 offsetof(mptsas_slot_free_e_t, node));
9743 9749 list_create(&mpt->m_slot_freeq_pairp[i].
9744 9750 m_slot_releq.s.m_fq_list,
9745 9751 sizeof (mptsas_slot_free_e_t),
9746 9752 offsetof(mptsas_slot_free_e_t, node));
9747 9753 mpt->m_slot_freeq_pairp[i].m_slot_allocq.s.m_fq_n = 0;
9748 9754 mpt->m_slot_freeq_pairp[i].m_slot_releq.s.m_fq_n = 0;
9749 9755 mutex_init(&mpt->m_slot_freeq_pairp[i].
9750 9756 m_slot_allocq.s.m_fq_mutex, NULL, MUTEX_DRIVER,
9751 9757 DDI_INTR_PRI(mpt->m_intr_pri));
9752 9758 mutex_init(&mpt->m_slot_freeq_pairp[i].
9753 9759 m_slot_releq.s.m_fq_mutex, NULL, MUTEX_DRIVER,
9754 9760 DDI_INTR_PRI(mpt->m_intr_pri));
9755 9761 }
9756 9762 pe = mpt->m_slot_free_ae = kmem_zalloc(nslot *
9757 9763 sizeof (mptsas_slot_free_e_t), KM_SLEEP);
9758 9764 /*
9759 9765 * An array of Mpi2ReplyDescriptorsUnion_t is defined here.
9760 9766 * We are trying to eliminate the m_mutex in the context
9761 9767 * reply code path in the ISR. Since the read of the
9762 9768 * ReplyDescriptor and update/write of the ReplyIndex must
9763 9769 * be atomic (since the poll thread may also update them at
9764 9770 * the same time) so we first read out of the ReplyDescriptor
9765 9771 * into this array and update the ReplyIndex register with a
9766 9772 * separate mutex m_intr_mutex protected, and then release the
9767 9773 * mutex and process all of them. the length of the array is
9768 9774 * defined as max as 128(128*64=8k), which is
9769 9775 * assumed as the maxmium depth of the interrupt coalese.
9770 9776 */
9771 9777 mpt->m_reply = kmem_zalloc(MPI_ADDRESS_COALSCE_MAX *
9772 9778 sizeof (Mpi2ReplyDescriptorsUnion_t), KM_SLEEP);
9773 9779 for (i = 0; i < nslot; i++, pe++) {
9774 9780 pe->slot = i + 1; /* SMID 0 is reserved */
9775 9781 pe->cpuid = i % mpt->m_slot_freeq_pair_n;
9776 9782 list_insert_tail(&mpt->m_slot_freeq_pairp
9777 9783 [i % mpt->m_slot_freeq_pair_n]
9778 9784 .m_slot_allocq.s.m_fq_list, pe);
9779 9785 mpt->m_slot_freeq_pairp[i % mpt->m_slot_freeq_pair_n]
9780 9786 .m_slot_allocq.s.m_fq_n++;
9781 9787 mpt->m_slot_freeq_pairp[i % mpt->m_slot_freeq_pair_n]
9782 9788 .m_slot_allocq.s.m_fq_n_init++;
9783 9789 }
9784 9790
9785 9791 mpt->m_active = new_active;
9786 9792 rval = 0;
9787 9793
9788 9794 return (rval);
9789 9795 }
9790 9796
9791 9797 static void
9792 9798 mptsas_free_active_slots(mptsas_t *mpt)
9793 9799 {
9794 9800 mptsas_slots_t *active = mpt->m_active;
9795 9801 size_t size;
9796 9802 mptsas_slot_free_e_t *pe;
9797 9803 int i;
9798 9804
9799 9805 if (active == NULL)
9800 9806 return;
9801 9807
9802 9808 if (mpt->m_slot_freeq_pairp) {
9803 9809 for (i = 0; i < mpt->m_slot_freeq_pair_n; i++) {
9804 9810 while ((pe = list_head(&mpt->m_slot_freeq_pairp
9805 9811 [i].m_slot_allocq.s.m_fq_list)) != NULL) {
9806 9812 list_remove(&mpt->m_slot_freeq_pairp[i]
9807 9813 .m_slot_allocq.s.m_fq_list, pe);
9808 9814 }
9809 9815 list_destroy(&mpt->m_slot_freeq_pairp
9810 9816 [i].m_slot_allocq.s.m_fq_list);
9811 9817 while ((pe = list_head(&mpt->m_slot_freeq_pairp
9812 9818 [i].m_slot_releq.s.m_fq_list)) != NULL) {
9813 9819 list_remove(&mpt->m_slot_freeq_pairp[i]
9814 9820 .m_slot_releq.s.m_fq_list, pe);
9815 9821 }
9816 9822 list_destroy(&mpt->m_slot_freeq_pairp
9817 9823 [i].m_slot_releq.s.m_fq_list);
9818 9824 mutex_destroy(&mpt->m_slot_freeq_pairp
9819 9825 [i].m_slot_allocq.s.m_fq_mutex);
9820 9826 mutex_destroy(&mpt->m_slot_freeq_pairp
9821 9827 [i].m_slot_releq.s.m_fq_mutex);
9822 9828 }
9823 9829 kmem_free(mpt->m_slot_freeq_pairp, mpt->m_slot_freeq_pair_n *
9824 9830 sizeof (mptsas_slot_freeq_pair_t));
9825 9831 }
9826 9832 if (mpt->m_slot_free_ae)
9827 9833 kmem_free(mpt->m_slot_free_ae, mpt->m_active->m_n_slots *
9828 9834 sizeof (mptsas_slot_free_e_t));
9829 9835
9830 9836 if (mpt->m_reply)
9831 9837 kmem_free(mpt->m_reply, MPI_ADDRESS_COALSCE_MAX *
9832 9838 sizeof (Mpi2ReplyDescriptorsUnion_t));
9833 9839
9834 9840 size = active->m_size;
9835 9841 kmem_free(active, size);
9836 9842 mpt->m_active = NULL;
9837 9843 }
9838 9844
9839 9845 /*
9840 9846 * Error logging, printing, and debug print routines.
9841 9847 */
9842 9848 static char *mptsas_label = "mpt_sas";
9843 9849
9844 9850 /*PRINTFLIKE3*/
9845 9851 void
9846 9852 mptsas_log(mptsas_t *mpt, int level, char *fmt, ...)
9847 9853 {
9848 9854 dev_info_t *dev;
9849 9855 va_list ap;
9850 9856
9851 9857 if (mpt) {
9852 9858 dev = mpt->m_dip;
9853 9859 } else {
9854 9860 dev = 0;
9855 9861 }
9856 9862
9857 9863 mutex_enter(&mptsas_log_mutex);
9858 9864
9859 9865 va_start(ap, fmt);
9860 9866 (void) vsprintf(mptsas_log_buf, fmt, ap);
9861 9867 va_end(ap);
9862 9868
9863 9869 if (level == CE_CONT) {
9864 9870 scsi_log(dev, mptsas_label, level, "%s\n", mptsas_log_buf);
9865 9871 } else {
9866 9872 scsi_log(dev, mptsas_label, level, "%s", mptsas_log_buf);
9867 9873 }
9868 9874
9869 9875 mutex_exit(&mptsas_log_mutex);
9870 9876 }
9871 9877
9872 9878 #ifdef MPTSAS_DEBUG
9873 9879 /*PRINTFLIKE1*/
9874 9880 void
9875 9881 mptsas_printf(char *fmt, ...)
9876 9882 {
9877 9883 dev_info_t *dev = 0;
9878 9884 va_list ap;
9879 9885
9880 9886 mutex_enter(&mptsas_log_mutex);
9881 9887
9882 9888 va_start(ap, fmt);
9883 9889 (void) vsprintf(mptsas_log_buf, fmt, ap);
9884 9890 va_end(ap);
9885 9891
9886 9892 #ifdef PROM_PRINTF
9887 9893 prom_printf("%s:\t%s\n", mptsas_label, mptsas_log_buf);
9888 9894 #else
9889 9895 scsi_log(dev, mptsas_label, SCSI_DEBUG, "%s\n", mptsas_log_buf);
9890 9896 #endif
9891 9897 mutex_exit(&mptsas_log_mutex);
9892 9898 }
9893 9899 #endif
9894 9900
9895 9901 /*
9896 9902 * timeout handling
9897 9903 */
9898 9904 static void
9899 9905 mptsas_watch(void *arg)
9900 9906 {
9901 9907 #ifndef __lock_lint
9902 9908 _NOTE(ARGUNUSED(arg))
9903 9909 #endif
9904 9910
9905 9911 mptsas_t *mpt;
9906 9912 uint32_t doorbell;
9907 9913
9908 9914 NDBG30(("mptsas_watch"));
9909 9915
9910 9916 rw_enter(&mptsas_global_rwlock, RW_READER);
9911 9917 for (mpt = mptsas_head; mpt != (mptsas_t *)NULL; mpt = mpt->m_next) {
9912 9918
9913 9919 mutex_enter(&mpt->m_mutex);
9914 9920
9915 9921 /* Skip device if not powered on */
9916 9922 if (mpt->m_options & MPTSAS_OPT_PM) {
9917 9923 if (mpt->m_power_level == PM_LEVEL_D0) {
9918 9924 (void) pm_busy_component(mpt->m_dip, 0);
9919 9925 mpt->m_busy = 1;
9920 9926 } else {
9921 9927 mutex_exit(&mpt->m_mutex);
9922 9928 continue;
9923 9929 }
9924 9930 }
9925 9931
9926 9932 /*
9927 9933 * Check if controller is in a FAULT state. If so, reset it.
9928 9934 */
9929 9935 doorbell = ddi_get32(mpt->m_datap, &mpt->m_reg->Doorbell);
9930 9936 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
9931 9937 doorbell &= MPI2_DOORBELL_DATA_MASK;
9932 9938 mptsas_log(mpt, CE_WARN, "MPT Firmware Fault, "
9933 9939 "code: %04x", doorbell);
9934 9940 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
9935 9941 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
9936 9942 mptsas_log(mpt, CE_WARN, "Reset failed"
9937 9943 "after fault was detected");
9938 9944 }
9939 9945 }
9940 9946
9941 9947 /*
9942 9948 * For now, always call mptsas_watchsubr.
9943 9949 */
9944 9950 mptsas_watchsubr(mpt);
9945 9951
9946 9952 if (mpt->m_options & MPTSAS_OPT_PM) {
9947 9953 mpt->m_busy = 0;
9948 9954 (void) pm_idle_component(mpt->m_dip, 0);
9949 9955 }
9950 9956
9951 9957 mutex_exit(&mpt->m_mutex);
9952 9958 }
9953 9959 rw_exit(&mptsas_global_rwlock);
9954 9960
9955 9961 mutex_enter(&mptsas_global_mutex);
9956 9962 if (mptsas_timeouts_enabled)
9957 9963 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick);
9958 9964 mutex_exit(&mptsas_global_mutex);
9959 9965 }
9960 9966
9961 9967 static void
9962 9968 mptsas_watchsubr(mptsas_t *mpt)
9963 9969 {
9964 9970 int i;
9965 9971 mptsas_cmd_t *cmd;
9966 9972 mptsas_target_t *ptgt = NULL;
9967 9973
9968 9974 NDBG30(("mptsas_watchsubr: mpt=0x%p", (void *)mpt));
9969 9975
9970 9976 #ifdef MPTSAS_TEST
9971 9977 if (mptsas_enable_untagged) {
9972 9978 mptsas_test_untagged++;
9973 9979 }
9974 9980 #endif
9975 9981
9976 9982 /*
9977 9983 * Check for commands stuck in active slot
9978 9984 * Account for TM requests, which use the last SMID.
9979 9985 */
9980 9986 mutex_enter(&mpt->m_intr_mutex);
9981 9987 for (i = 0; i <= mpt->m_active->m_n_slots; i++) {
9982 9988 if ((cmd = mpt->m_active->m_slot[i]) != NULL) {
9983 9989 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
9984 9990 cmd->cmd_active_timeout -=
9985 9991 mptsas_scsi_watchdog_tick;
9986 9992 if (cmd->cmd_active_timeout <= 0) {
9987 9993 /*
9988 9994 * There seems to be a command stuck
9989 9995 * in the active slot. Drain throttle.
9990 9996 */
9991 9997 ptgt = cmd->cmd_tgt_addr;
9992 9998 mutex_enter(&ptgt->m_tgt_intr_mutex);
9993 9999 mptsas_set_throttle(mpt, ptgt,
9994 10000 DRAIN_THROTTLE);
9995 10001 mutex_exit(&ptgt->m_tgt_intr_mutex);
9996 10002 }
9997 10003 }
9998 10004 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
9999 10005 (cmd->cmd_flags & CFLAG_CONFIG) ||
10000 10006 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
10001 10007 cmd->cmd_active_timeout -=
10002 10008 mptsas_scsi_watchdog_tick;
10003 10009 if (cmd->cmd_active_timeout <= 0) {
10004 10010 /*
10005 10011 * passthrough command timeout
10006 10012 */
10007 10013 cmd->cmd_flags |= (CFLAG_FINISHED |
10008 10014 CFLAG_TIMEOUT);
10009 10015 cv_broadcast(&mpt->m_passthru_cv);
10010 10016 cv_broadcast(&mpt->m_config_cv);
10011 10017 cv_broadcast(&mpt->m_fw_diag_cv);
10012 10018 }
10013 10019 }
10014 10020 }
10015 10021 }
10016 10022 mutex_exit(&mpt->m_intr_mutex);
10017 10023
10018 10024 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
10019 10025 MPTSAS_HASH_FIRST);
10020 10026 while (ptgt != NULL) {
10021 10027 /*
10022 10028 * In order to avoid using m_mutex in the key code path in ISR,
10023 10029 * separate mutexs are introduced to protect those elements
10024 10030 * shown in ISR.
10025 10031 */
10026 10032 mutex_enter(&ptgt->m_tgt_intr_mutex);
10027 10033
10028 10034 /*
10029 10035 * If we were draining due to a qfull condition,
10030 10036 * go back to full throttle.
10031 10037 */
10032 10038 if ((ptgt->m_t_throttle < MAX_THROTTLE) &&
10033 10039 (ptgt->m_t_throttle > HOLD_THROTTLE) &&
10034 10040 (ptgt->m_t_ncmds < ptgt->m_t_throttle)) {
10035 10041 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
10036 10042 mptsas_restart_hba(mpt);
10037 10043 }
10038 10044
10039 10045 if ((ptgt->m_t_ncmds > 0) &&
10040 10046 (ptgt->m_timebase)) {
10041 10047
10042 10048 if (ptgt->m_timebase <=
10043 10049 mptsas_scsi_watchdog_tick) {
10044 10050 ptgt->m_timebase +=
10045 10051 mptsas_scsi_watchdog_tick;
10046 10052 mutex_exit(&ptgt->m_tgt_intr_mutex);
10047 10053 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
10048 10054 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
10049 10055 continue;
10050 10056 }
10051 10057
10052 10058 ptgt->m_timeout -= mptsas_scsi_watchdog_tick;
10053 10059
10054 10060 if (ptgt->m_timeout < 0) {
10055 10061 mutex_exit(&ptgt->m_tgt_intr_mutex);
10056 10062 mptsas_cmd_timeout(mpt, ptgt->m_devhdl);
10057 10063 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
10058 10064 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
10059 10065 continue;
10060 10066 }
10061 10067
10062 10068 if ((ptgt->m_timeout) <=
10063 10069 mptsas_scsi_watchdog_tick) {
10064 10070 NDBG23(("pending timeout"));
10065 10071 mptsas_set_throttle(mpt, ptgt,
10066 10072 DRAIN_THROTTLE);
10067 10073 }
10068 10074 }
10069 10075 mutex_exit(&ptgt->m_tgt_intr_mutex);
10070 10076 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
10071 10077 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
10072 10078 }
10073 10079 }
10074 10080
10075 10081 /*
10076 10082 * timeout recovery
10077 10083 */
10078 10084 static void
10079 10085 mptsas_cmd_timeout(mptsas_t *mpt, uint16_t devhdl)
10080 10086 {
10081 10087
10082 10088 NDBG29(("mptsas_cmd_timeout: target=%d", devhdl));
10083 10089 mptsas_log(mpt, CE_WARN, "Disconnected command timeout for "
10084 10090 "Target %d", devhdl);
10085 10091
10086 10092 /*
10087 10093 * If the current target is not the target passed in,
10088 10094 * try to reset that target.
10089 10095 */
10090 10096 NDBG29(("mptsas_cmd_timeout: device reset"));
10091 10097 if (mptsas_do_scsi_reset(mpt, devhdl) != TRUE) {
10092 10098 mptsas_log(mpt, CE_WARN, "Target %d reset for command timeout "
10093 10099 "recovery failed!", devhdl);
10094 10100 }
10095 10101 }
10096 10102
10097 10103 /*
10098 10104 * Device / Hotplug control
10099 10105 */
10100 10106 static int
10101 10107 mptsas_scsi_quiesce(dev_info_t *dip)
10102 10108 {
10103 10109 mptsas_t *mpt;
10104 10110 scsi_hba_tran_t *tran;
10105 10111
10106 10112 tran = ddi_get_driver_private(dip);
10107 10113 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL)
10108 10114 return (-1);
10109 10115
10110 10116 return (mptsas_quiesce_bus(mpt));
10111 10117 }
10112 10118
10113 10119 static int
10114 10120 mptsas_scsi_unquiesce(dev_info_t *dip)
10115 10121 {
10116 10122 mptsas_t *mpt;
10117 10123 scsi_hba_tran_t *tran;
10118 10124
10119 10125 tran = ddi_get_driver_private(dip);
10120 10126 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL)
10121 10127 return (-1);
10122 10128
10123 10129 return (mptsas_unquiesce_bus(mpt));
10124 10130 }
10125 10131
10126 10132 static int
10127 10133 mptsas_quiesce_bus(mptsas_t *mpt)
10128 10134 {
10129 10135 mptsas_target_t *ptgt = NULL;
10130 10136
10131 10137 NDBG28(("mptsas_quiesce_bus"));
10132 10138 mutex_enter(&mpt->m_mutex);
10133 10139
10134 10140 /* Set all the throttles to zero */
10135 10141 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
10136 10142 MPTSAS_HASH_FIRST);
10137 10143 while (ptgt != NULL) {
10138 10144 mutex_enter(&ptgt->m_tgt_intr_mutex);
10139 10145 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
10140 10146 mutex_exit(&ptgt->m_tgt_intr_mutex);
10141 10147
10142 10148 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
10143 10149 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
10144 10150 }
10145 10151
10146 10152 /* If there are any outstanding commands in the queue */
10147 10153 mutex_enter(&mpt->m_intr_mutex);
10148 10154 if (mptsas_outstanding_cmds_n(mpt)) {
10149 10155 mutex_exit(&mpt->m_intr_mutex);
10150 10156 mpt->m_softstate |= MPTSAS_SS_DRAINING;
10151 10157 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain,
10152 10158 mpt, (MPTSAS_QUIESCE_TIMEOUT * drv_usectohz(1000000)));
10153 10159 if (cv_wait_sig(&mpt->m_cv, &mpt->m_mutex) == 0) {
10154 10160 /*
10155 10161 * Quiesce has been interrupted
10156 10162 */
10157 10163 mpt->m_softstate &= ~MPTSAS_SS_DRAINING;
10158 10164 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
10159 10165 &mpt->m_active->m_tgttbl, MPTSAS_HASH_FIRST);
10160 10166 while (ptgt != NULL) {
10161 10167 mutex_enter(&ptgt->m_tgt_intr_mutex);
10162 10168 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
10163 10169 mutex_exit(&ptgt->m_tgt_intr_mutex);
10164 10170
10165 10171 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
10166 10172 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
10167 10173 }
10168 10174 mptsas_restart_hba(mpt);
10169 10175 if (mpt->m_quiesce_timeid != 0) {
10170 10176 timeout_id_t tid = mpt->m_quiesce_timeid;
10171 10177 mpt->m_quiesce_timeid = 0;
10172 10178 mutex_exit(&mpt->m_mutex);
10173 10179 (void) untimeout(tid);
10174 10180 return (-1);
10175 10181 }
10176 10182 mutex_exit(&mpt->m_mutex);
10177 10183 return (-1);
10178 10184 } else {
10179 10185 /* Bus has been quiesced */
10180 10186 ASSERT(mpt->m_quiesce_timeid == 0);
10181 10187 mpt->m_softstate &= ~MPTSAS_SS_DRAINING;
10182 10188 mpt->m_softstate |= MPTSAS_SS_QUIESCED;
10183 10189 mutex_exit(&mpt->m_mutex);
10184 10190 return (0);
10185 10191 }
10186 10192 }
10187 10193 mutex_exit(&mpt->m_intr_mutex);
10188 10194 /* Bus was not busy - QUIESCED */
10189 10195 mutex_exit(&mpt->m_mutex);
10190 10196
10191 10197 return (0);
10192 10198 }
10193 10199
10194 10200 static int
10195 10201 mptsas_unquiesce_bus(mptsas_t *mpt)
10196 10202 {
10197 10203 mptsas_target_t *ptgt = NULL;
10198 10204
10199 10205 NDBG28(("mptsas_unquiesce_bus"));
10200 10206 mutex_enter(&mpt->m_mutex);
10201 10207 mpt->m_softstate &= ~MPTSAS_SS_QUIESCED;
10202 10208 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
10203 10209 MPTSAS_HASH_FIRST);
10204 10210 while (ptgt != NULL) {
10205 10211 mutex_enter(&ptgt->m_tgt_intr_mutex);
10206 10212 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
10207 10213 mutex_exit(&ptgt->m_tgt_intr_mutex);
10208 10214
10209 10215 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
10210 10216 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
10211 10217 }
10212 10218 mptsas_restart_hba(mpt);
10213 10219 mutex_exit(&mpt->m_mutex);
10214 10220 return (0);
10215 10221 }
10216 10222
10217 10223 static void
10218 10224 mptsas_ncmds_checkdrain(void *arg)
10219 10225 {
10220 10226 mptsas_t *mpt = arg;
10221 10227 mptsas_target_t *ptgt = NULL;
10222 10228
10223 10229 mutex_enter(&mpt->m_mutex);
10224 10230 if (mpt->m_softstate & MPTSAS_SS_DRAINING) {
10225 10231 mpt->m_quiesce_timeid = 0;
10226 10232 mutex_enter(&mpt->m_intr_mutex);
10227 10233 if (mptsas_outstanding_cmds_n(mpt)) {
10228 10234 mutex_exit(&mpt->m_intr_mutex);
10229 10235 /*
10230 10236 * The throttle may have been reset because
10231 10237 * of a SCSI bus reset
10232 10238 */
10233 10239 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
10234 10240 &mpt->m_active->m_tgttbl, MPTSAS_HASH_FIRST);
10235 10241 while (ptgt != NULL) {
10236 10242 mutex_enter(&ptgt->m_tgt_intr_mutex);
10237 10243 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
10238 10244 mutex_exit(&ptgt->m_tgt_intr_mutex);
10239 10245
10240 10246 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
10241 10247 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
10242 10248 }
10243 10249
10244 10250 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain,
10245 10251 mpt, (MPTSAS_QUIESCE_TIMEOUT *
10246 10252 drv_usectohz(1000000)));
10247 10253 } else {
10248 10254 mutex_exit(&mpt->m_intr_mutex);
10249 10255 /* Command queue has been drained */
10250 10256 cv_signal(&mpt->m_cv);
10251 10257 }
10252 10258 }
10253 10259 mutex_exit(&mpt->m_mutex);
10254 10260 }
10255 10261
10256 10262 /*ARGSUSED*/
10257 10263 static void
10258 10264 mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
10259 10265 {
10260 10266 int i;
10261 10267 uint8_t *cp = (uchar_t *)cmd->cmd_pkt->pkt_cdbp;
10262 10268 char buf[128];
10263 10269
10264 10270 buf[0] = '\0';
10265 10271 NDBG25(("?Cmd (0x%p) dump for Target %d Lun %d:\n", (void *)cmd,
10266 10272 Tgt(cmd), Lun(cmd)));
10267 10273 (void) sprintf(&buf[0], "\tcdb=[");
10268 10274 for (i = 0; i < (int)cmd->cmd_cdblen; i++) {
10269 10275 (void) sprintf(&buf[strlen(buf)], " 0x%x", *cp++);
10270 10276 }
10271 10277 (void) sprintf(&buf[strlen(buf)], " ]");
10272 10278 NDBG25(("?%s\n", buf));
10273 10279 NDBG25(("?pkt_flags=0x%x pkt_statistics=0x%x pkt_state=0x%x\n",
10274 10280 cmd->cmd_pkt->pkt_flags, cmd->cmd_pkt->pkt_statistics,
10275 10281 cmd->cmd_pkt->pkt_state));
10276 10282 NDBG25(("?pkt_scbp=0x%x cmd_flags=0x%x\n", cmd->cmd_pkt->pkt_scbp ?
10277 10283 *(cmd->cmd_pkt->pkt_scbp) : 0, cmd->cmd_flags));
10278 10284 }
10279 10285
10280 10286 static void
10281 10287 mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd)
10282 10288 {
10283 10289 caddr_t memp;
10284 10290 pMPI2RequestHeader_t request_hdrp;
10285 10291 struct scsi_pkt *pkt = cmd->cmd_pkt;
10286 10292 mptsas_pt_request_t *pt = pkt->pkt_ha_private;
10287 10293 uint32_t request_size, data_size, dataout_size;
10288 10294 uint32_t direction;
10289 10295 ddi_dma_cookie_t data_cookie;
10290 10296 ddi_dma_cookie_t dataout_cookie;
10291 10297 uint32_t request_desc_low, request_desc_high = 0;
10292 10298 uint32_t i, sense_bufp;
10293 10299 uint8_t desc_type;
10294 10300 uint8_t *request, function;
10295 10301 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl;
10296 10302 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl;
10297 10303
10298 10304 desc_type = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
10299 10305
10300 10306 request = pt->request;
10301 10307 direction = pt->direction;
10302 10308 request_size = pt->request_size;
10303 10309 data_size = pt->data_size;
10304 10310 dataout_size = pt->dataout_size;
10305 10311 data_cookie = pt->data_cookie;
10306 10312 dataout_cookie = pt->dataout_cookie;
10307 10313
10308 10314 /*
10309 10315 * Store the passthrough message in memory location
10310 10316 * corresponding to our slot number
10311 10317 */
10312 10318 memp = mpt->m_req_frame + (mpt->m_req_frame_size * cmd->cmd_slot);
10313 10319 request_hdrp = (pMPI2RequestHeader_t)memp;
10314 10320 bzero(memp, mpt->m_req_frame_size);
10315 10321
10316 10322 for (i = 0; i < request_size; i++) {
10317 10323 bcopy(request + i, memp + i, 1);
10318 10324 }
10319 10325
10320 10326 if (data_size || dataout_size) {
10321 10327 pMpi2SGESimple64_t sgep;
10322 10328 uint32_t sge_flags;
10323 10329
10324 10330 sgep = (pMpi2SGESimple64_t)((uint8_t *)request_hdrp +
10325 10331 request_size);
10326 10332 if (dataout_size) {
10327 10333
10328 10334 sge_flags = dataout_size |
10329 10335 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
10330 10336 MPI2_SGE_FLAGS_END_OF_BUFFER |
10331 10337 MPI2_SGE_FLAGS_HOST_TO_IOC |
10332 10338 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
10333 10339 MPI2_SGE_FLAGS_SHIFT);
10334 10340 ddi_put32(acc_hdl, &sgep->FlagsLength, sge_flags);
10335 10341 ddi_put32(acc_hdl, &sgep->Address.Low,
10336 10342 (uint32_t)(dataout_cookie.dmac_laddress &
10337 10343 0xffffffffull));
10338 10344 ddi_put32(acc_hdl, &sgep->Address.High,
10339 10345 (uint32_t)(dataout_cookie.dmac_laddress
10340 10346 >> 32));
10341 10347 sgep++;
10342 10348 }
10343 10349 sge_flags = data_size;
10344 10350 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
10345 10351 MPI2_SGE_FLAGS_LAST_ELEMENT |
10346 10352 MPI2_SGE_FLAGS_END_OF_BUFFER |
10347 10353 MPI2_SGE_FLAGS_END_OF_LIST |
10348 10354 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
10349 10355 MPI2_SGE_FLAGS_SHIFT);
10350 10356 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) {
10351 10357 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) <<
10352 10358 MPI2_SGE_FLAGS_SHIFT);
10353 10359 } else {
10354 10360 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) <<
10355 10361 MPI2_SGE_FLAGS_SHIFT);
10356 10362 }
10357 10363 ddi_put32(acc_hdl, &sgep->FlagsLength,
10358 10364 sge_flags);
10359 10365 ddi_put32(acc_hdl, &sgep->Address.Low,
10360 10366 (uint32_t)(data_cookie.dmac_laddress &
10361 10367 0xffffffffull));
10362 10368 ddi_put32(acc_hdl, &sgep->Address.High,
10363 10369 (uint32_t)(data_cookie.dmac_laddress >> 32));
10364 10370 }
10365 10371
10366 10372 function = request_hdrp->Function;
10367 10373 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
10368 10374 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
10369 10375 pMpi2SCSIIORequest_t scsi_io_req;
10370 10376
10371 10377 scsi_io_req = (pMpi2SCSIIORequest_t)request_hdrp;
10372 10378 /*
10373 10379 * Put SGE for data and data_out buffer at the end of
10374 10380 * scsi_io_request message header.(64 bytes in total)
10375 10381 * Following above SGEs, the residual space will be
10376 10382 * used by sense data.
10377 10383 */
10378 10384 ddi_put8(acc_hdl,
10379 10385 &scsi_io_req->SenseBufferLength,
10380 10386 (uint8_t)(request_size - 64));
10381 10387
10382 10388 sense_bufp = mpt->m_req_frame_dma_addr +
10383 10389 (mpt->m_req_frame_size * cmd->cmd_slot);
10384 10390 sense_bufp += 64;
10385 10391 ddi_put32(acc_hdl,
10386 10392 &scsi_io_req->SenseBufferLowAddress, sense_bufp);
10387 10393
10388 10394 /*
10389 10395 * Set SGLOffset0 value
10390 10396 */
10391 10397 ddi_put8(acc_hdl, &scsi_io_req->SGLOffset0,
10392 10398 offsetof(MPI2_SCSI_IO_REQUEST, SGL) / 4);
10393 10399
10394 10400 /*
10395 10401 * Setup descriptor info. RAID passthrough must use the
10396 10402 * default request descriptor which is already set, so if this
10397 10403 * is a SCSI IO request, change the descriptor to SCSI IO.
10398 10404 */
10399 10405 if (function == MPI2_FUNCTION_SCSI_IO_REQUEST) {
10400 10406 desc_type = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
10401 10407 request_desc_high = (ddi_get16(acc_hdl,
10402 10408 &scsi_io_req->DevHandle) << 16);
10403 10409 }
10404 10410 }
10405 10411
10406 10412 /*
10407 10413 * We must wait till the message has been completed before
10408 10414 * beginning the next message so we wait for this one to
10409 10415 * finish.
10410 10416 */
10411 10417 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
10412 10418 request_desc_low = (cmd->cmd_slot << 16) + desc_type;
10413 10419 cmd->cmd_rfm = NULL;
10414 10420 mpt->m_active->m_slot[cmd->cmd_slot] = cmd;
10415 10421 MPTSAS_START_CMD(mpt, request_desc_low, request_desc_high);
10416 10422 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) ||
10417 10423 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) {
10418 10424 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
10419 10425 }
10420 10426 }
10421 10427
10422 10428
10423 10429
10424 10430 static int
10425 10431 mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply,
10426 10432 uint8_t *data, uint32_t request_size, uint32_t reply_size,
10427 10433 uint32_t data_size, uint32_t direction, uint8_t *dataout,
10428 10434 uint32_t dataout_size, short timeout, int mode)
10429 10435 {
10430 10436 mptsas_pt_request_t pt;
10431 10437 mptsas_dma_alloc_state_t data_dma_state;
10432 10438 mptsas_dma_alloc_state_t dataout_dma_state;
10433 10439 caddr_t memp;
10434 10440 mptsas_cmd_t *cmd = NULL;
10435 10441 struct scsi_pkt *pkt;
10436 10442 uint32_t reply_len = 0, sense_len = 0;
10437 10443 pMPI2RequestHeader_t request_hdrp;
10438 10444 pMPI2RequestHeader_t request_msg;
10439 10445 pMPI2DefaultReply_t reply_msg;
10440 10446 Mpi2SCSIIOReply_t rep_msg;
10441 10447 int i, status = 0, pt_flags = 0, rv = 0;
10442 10448 int rvalue;
10443 10449 uint8_t function;
10444 10450
10445 10451 ASSERT(mutex_owned(&mpt->m_mutex));
10446 10452
10447 10453 reply_msg = (pMPI2DefaultReply_t)(&rep_msg);
10448 10454 bzero(reply_msg, sizeof (MPI2_DEFAULT_REPLY));
10449 10455 request_msg = kmem_zalloc(request_size, KM_SLEEP);
10450 10456
10451 10457 mutex_exit(&mpt->m_mutex);
10452 10458 /*
10453 10459 * copy in the request buffer since it could be used by
10454 10460 * another thread when the pt request into waitq
10455 10461 */
10456 10462 if (ddi_copyin(request, request_msg, request_size, mode)) {
10457 10463 mutex_enter(&mpt->m_mutex);
10458 10464 status = EFAULT;
10459 10465 mptsas_log(mpt, CE_WARN, "failed to copy request data");
10460 10466 goto out;
10461 10467 }
10462 10468 mutex_enter(&mpt->m_mutex);
10463 10469
10464 10470 function = request_msg->Function;
10465 10471 if (function == MPI2_FUNCTION_SCSI_TASK_MGMT) {
10466 10472 pMpi2SCSITaskManagementRequest_t task;
10467 10473 task = (pMpi2SCSITaskManagementRequest_t)request_msg;
10468 10474 mptsas_setup_bus_reset_delay(mpt);
10469 10475 rv = mptsas_ioc_task_management(mpt, task->TaskType,
10470 10476 task->DevHandle, (int)task->LUN[1], reply, reply_size,
10471 10477 mode);
10472 10478
10473 10479 if (rv != TRUE) {
10474 10480 status = EIO;
10475 10481 mptsas_log(mpt, CE_WARN, "task management failed");
10476 10482 }
10477 10483 goto out;
10478 10484 }
10479 10485
10480 10486 if (data_size != 0) {
10481 10487 data_dma_state.size = data_size;
10482 10488 if (mptsas_dma_alloc(mpt, &data_dma_state) != DDI_SUCCESS) {
10483 10489 status = ENOMEM;
10484 10490 mptsas_log(mpt, CE_WARN, "failed to alloc DMA "
10485 10491 "resource");
10486 10492 goto out;
10487 10493 }
10488 10494 pt_flags |= MPTSAS_DATA_ALLOCATED;
10489 10495 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) {
10490 10496 mutex_exit(&mpt->m_mutex);
10491 10497 for (i = 0; i < data_size; i++) {
10492 10498 if (ddi_copyin(data + i, (uint8_t *)
10493 10499 data_dma_state.memp + i, 1, mode)) {
10494 10500 mutex_enter(&mpt->m_mutex);
10495 10501 status = EFAULT;
10496 10502 mptsas_log(mpt, CE_WARN, "failed to "
10497 10503 "copy read data");
10498 10504 goto out;
10499 10505 }
10500 10506 }
10501 10507 mutex_enter(&mpt->m_mutex);
10502 10508 }
10503 10509 }
10504 10510
10505 10511 if (dataout_size != 0) {
10506 10512 dataout_dma_state.size = dataout_size;
10507 10513 if (mptsas_dma_alloc(mpt, &dataout_dma_state) != DDI_SUCCESS) {
10508 10514 status = ENOMEM;
10509 10515 mptsas_log(mpt, CE_WARN, "failed to alloc DMA "
10510 10516 "resource");
10511 10517 goto out;
10512 10518 }
10513 10519 pt_flags |= MPTSAS_DATAOUT_ALLOCATED;
10514 10520 mutex_exit(&mpt->m_mutex);
10515 10521 for (i = 0; i < dataout_size; i++) {
10516 10522 if (ddi_copyin(dataout + i, (uint8_t *)
10517 10523 dataout_dma_state.memp + i, 1, mode)) {
10518 10524 mutex_enter(&mpt->m_mutex);
10519 10525 mptsas_log(mpt, CE_WARN, "failed to copy out"
10520 10526 " data");
10521 10527 status = EFAULT;
10522 10528 goto out;
10523 10529 }
10524 10530 }
10525 10531 mutex_enter(&mpt->m_mutex);
10526 10532 }
10527 10533
10528 10534 if ((rvalue = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
10529 10535 status = EAGAIN;
10530 10536 mptsas_log(mpt, CE_NOTE, "event ack command pool is full");
10531 10537 goto out;
10532 10538 }
10533 10539 pt_flags |= MPTSAS_REQUEST_POOL_CMD;
10534 10540
10535 10541 bzero((caddr_t)cmd, sizeof (*cmd));
10536 10542 bzero((caddr_t)pkt, scsi_pkt_size());
10537 10543 bzero((caddr_t)&pt, sizeof (pt));
10538 10544
10539 10545 cmd->ioc_cmd_slot = (uint32_t)(rvalue);
10540 10546
10541 10547 pt.request = (uint8_t *)request_msg;
10542 10548 pt.direction = direction;
10543 10549 pt.request_size = request_size;
10544 10550 pt.data_size = data_size;
10545 10551 pt.dataout_size = dataout_size;
10546 10552 pt.data_cookie = data_dma_state.cookie;
10547 10553 pt.dataout_cookie = dataout_dma_state.cookie;
10548 10554
10549 10555 /*
10550 10556 * Form a blank cmd/pkt to store the acknowledgement message
10551 10557 */
10552 10558 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb[0];
10553 10559 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb;
10554 10560 pkt->pkt_ha_private = (opaque_t)&pt;
10555 10561 pkt->pkt_flags = FLAG_HEAD;
10556 10562 pkt->pkt_time = timeout;
10557 10563 cmd->cmd_pkt = pkt;
10558 10564 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_PASSTHRU;
10559 10565
10560 10566 /*
10561 10567 * Save the command in a slot
10562 10568 */
10563 10569 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
10564 10570 /*
10565 10571 * Once passthru command get slot, set cmd_flags
10566 10572 * CFLAG_PREPARED.
10567 10573 */
10568 10574 cmd->cmd_flags |= CFLAG_PREPARED;
10569 10575 mptsas_start_passthru(mpt, cmd);
10570 10576 } else {
10571 10577 mptsas_waitq_add(mpt, cmd);
10572 10578 }
10573 10579
10574 10580 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
10575 10581 cv_wait(&mpt->m_passthru_cv, &mpt->m_mutex);
10576 10582 }
10577 10583
10578 10584 if (cmd->cmd_flags & CFLAG_PREPARED) {
10579 10585 memp = mpt->m_req_frame + (mpt->m_req_frame_size *
10580 10586 cmd->cmd_slot);
10581 10587 request_hdrp = (pMPI2RequestHeader_t)memp;
10582 10588 }
10583 10589
10584 10590 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
10585 10591 status = ETIMEDOUT;
10586 10592 mptsas_log(mpt, CE_WARN, "passthrough command timeout");
10587 10593 pt_flags |= MPTSAS_CMD_TIMEOUT;
10588 10594 goto out;
10589 10595 }
10590 10596
10591 10597 if (cmd->cmd_rfm) {
10592 10598 /*
10593 10599 * cmd_rfm is zero means the command reply is a CONTEXT
10594 10600 * reply and no PCI Write to post the free reply SMFA
10595 10601 * because no reply message frame is used.
10596 10602 * cmd_rfm is non-zero means the reply is a ADDRESS
10597 10603 * reply and reply message frame is used.
10598 10604 */
10599 10605 pt_flags |= MPTSAS_ADDRESS_REPLY;
10600 10606 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
10601 10607 DDI_DMA_SYNC_FORCPU);
10602 10608 reply_msg = (pMPI2DefaultReply_t)
10603 10609 (mpt->m_reply_frame + (cmd->cmd_rfm -
10604 10610 mpt->m_reply_frame_dma_addr));
10605 10611 }
10606 10612
10607 10613 mptsas_fma_check(mpt, cmd);
10608 10614 if (pkt->pkt_reason == CMD_TRAN_ERR) {
10609 10615 status = EAGAIN;
10610 10616 mptsas_log(mpt, CE_WARN, "passthru fma error");
10611 10617 goto out;
10612 10618 }
10613 10619 if (pkt->pkt_reason == CMD_RESET) {
10614 10620 status = EAGAIN;
10615 10621 mptsas_log(mpt, CE_WARN, "ioc reset abort passthru");
10616 10622 goto out;
10617 10623 }
10618 10624
10619 10625 if (pkt->pkt_reason == CMD_INCOMPLETE) {
10620 10626 status = EIO;
10621 10627 mptsas_log(mpt, CE_WARN, "passthrough command incomplete");
10622 10628 goto out;
10623 10629 }
10624 10630
10625 10631 mutex_exit(&mpt->m_mutex);
10626 10632 if (cmd->cmd_flags & CFLAG_PREPARED) {
10627 10633 function = request_hdrp->Function;
10628 10634 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
10629 10635 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
10630 10636 reply_len = sizeof (MPI2_SCSI_IO_REPLY);
10631 10637 sense_len = reply_size - reply_len;
10632 10638 } else {
10633 10639 reply_len = reply_size;
10634 10640 sense_len = 0;
10635 10641 }
10636 10642
10637 10643 for (i = 0; i < reply_len; i++) {
10638 10644 if (ddi_copyout((uint8_t *)reply_msg + i, reply + i, 1,
10639 10645 mode)) {
10640 10646 mutex_enter(&mpt->m_mutex);
10641 10647 status = EFAULT;
10642 10648 mptsas_log(mpt, CE_WARN, "failed to copy out "
10643 10649 "reply data");
10644 10650 goto out;
10645 10651 }
10646 10652 }
10647 10653 for (i = 0; i < sense_len; i++) {
10648 10654 if (ddi_copyout((uint8_t *)request_hdrp + 64 + i,
10649 10655 reply + reply_len + i, 1, mode)) {
10650 10656 mutex_enter(&mpt->m_mutex);
10651 10657 status = EFAULT;
10652 10658 mptsas_log(mpt, CE_WARN, "failed to copy out "
10653 10659 "sense data");
10654 10660 goto out;
10655 10661 }
10656 10662 }
10657 10663 }
10658 10664
10659 10665 if (data_size) {
10660 10666 if (direction != MPTSAS_PASS_THRU_DIRECTION_WRITE) {
10661 10667 (void) ddi_dma_sync(data_dma_state.handle, 0, 0,
10662 10668 DDI_DMA_SYNC_FORCPU);
10663 10669 for (i = 0; i < data_size; i++) {
10664 10670 if (ddi_copyout((uint8_t *)(
10665 10671 data_dma_state.memp + i), data + i, 1,
10666 10672 mode)) {
10667 10673 mutex_enter(&mpt->m_mutex);
10668 10674 status = EFAULT;
10669 10675 mptsas_log(mpt, CE_WARN, "failed to "
10670 10676 "copy out the reply data");
10671 10677 goto out;
10672 10678 }
10673 10679 }
10674 10680 }
10675 10681 }
10676 10682 mutex_enter(&mpt->m_mutex);
10677 10683 out:
10678 10684 /*
10679 10685 * Put the reply frame back on the free queue, increment the free
10680 10686 * index, and write the new index to the free index register. But only
10681 10687 * if this reply is an ADDRESS reply.
10682 10688 */
10683 10689 if (pt_flags & MPTSAS_ADDRESS_REPLY) {
10684 10690 ddi_put32(mpt->m_acc_free_queue_hdl,
10685 10691 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
10686 10692 cmd->cmd_rfm);
10687 10693 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
10688 10694 DDI_DMA_SYNC_FORDEV);
10689 10695 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
10690 10696 mpt->m_free_index = 0;
10691 10697 }
10692 10698 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
10693 10699 mpt->m_free_index);
10694 10700 }
10695 10701 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
10696 10702 mptsas_remove_cmd(mpt, cmd);
10697 10703 pt_flags &= (~MPTSAS_REQUEST_POOL_CMD);
10698 10704 }
10699 10705 if (pt_flags & MPTSAS_REQUEST_POOL_CMD)
10700 10706 mptsas_return_to_pool(mpt, cmd);
10701 10707 if (pt_flags & MPTSAS_DATA_ALLOCATED) {
10702 10708 if (mptsas_check_dma_handle(data_dma_state.handle) !=
10703 10709 DDI_SUCCESS) {
10704 10710 ddi_fm_service_impact(mpt->m_dip,
10705 10711 DDI_SERVICE_UNAFFECTED);
10706 10712 status = EFAULT;
10707 10713 }
10708 10714 mptsas_dma_free(&data_dma_state);
10709 10715 }
10710 10716 if (pt_flags & MPTSAS_DATAOUT_ALLOCATED) {
10711 10717 if (mptsas_check_dma_handle(dataout_dma_state.handle) !=
10712 10718 DDI_SUCCESS) {
10713 10719 ddi_fm_service_impact(mpt->m_dip,
10714 10720 DDI_SERVICE_UNAFFECTED);
10715 10721 status = EFAULT;
10716 10722 }
10717 10723 mptsas_dma_free(&dataout_dma_state);
10718 10724 }
10719 10725 if (pt_flags & MPTSAS_CMD_TIMEOUT) {
10720 10726 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
10721 10727 mptsas_log(mpt, CE_WARN, "mptsas_restart_ioc failed");
10722 10728 }
10723 10729 }
10724 10730 if (request_msg)
10725 10731 kmem_free(request_msg, request_size);
10726 10732
10727 10733 return (status);
10728 10734 }
10729 10735
10730 10736 static int
10731 10737 mptsas_pass_thru(mptsas_t *mpt, mptsas_pass_thru_t *data, int mode)
10732 10738 {
10733 10739 /*
10734 10740 * If timeout is 0, set timeout to default of 60 seconds.
10735 10741 */
10736 10742 if (data->Timeout == 0) {
10737 10743 data->Timeout = MPTSAS_PASS_THRU_TIME_DEFAULT;
10738 10744 }
10739 10745
10740 10746 if (((data->DataSize == 0) &&
10741 10747 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_NONE)) ||
10742 10748 ((data->DataSize != 0) &&
10743 10749 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_READ) ||
10744 10750 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_WRITE) ||
10745 10751 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) &&
10746 10752 (data->DataOutSize != 0))))) {
10747 10753 if (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) {
10748 10754 data->DataDirection = MPTSAS_PASS_THRU_DIRECTION_READ;
10749 10755 } else {
10750 10756 data->DataOutSize = 0;
10751 10757 }
10752 10758 /*
10753 10759 * Send passthru request messages
10754 10760 */
10755 10761 return (mptsas_do_passthru(mpt,
10756 10762 (uint8_t *)((uintptr_t)data->PtrRequest),
10757 10763 (uint8_t *)((uintptr_t)data->PtrReply),
10758 10764 (uint8_t *)((uintptr_t)data->PtrData),
10759 10765 data->RequestSize, data->ReplySize,
10760 10766 data->DataSize, data->DataDirection,
10761 10767 (uint8_t *)((uintptr_t)data->PtrDataOut),
10762 10768 data->DataOutSize, data->Timeout, mode));
10763 10769 } else {
10764 10770 return (EINVAL);
10765 10771 }
10766 10772 }
10767 10773
10768 10774 static uint8_t
10769 10775 mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, uint32_t unique_id)
10770 10776 {
10771 10777 uint8_t index;
10772 10778
10773 10779 for (index = 0; index < MPI2_DIAG_BUF_TYPE_COUNT; index++) {
10774 10780 if (mpt->m_fw_diag_buffer_list[index].unique_id == unique_id) {
10775 10781 return (index);
10776 10782 }
10777 10783 }
10778 10784
10779 10785 return (MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND);
10780 10786 }
10781 10787
10782 10788 static void
10783 10789 mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd)
10784 10790 {
10785 10791 pMpi2DiagBufferPostRequest_t pDiag_post_msg;
10786 10792 pMpi2DiagReleaseRequest_t pDiag_release_msg;
10787 10793 struct scsi_pkt *pkt = cmd->cmd_pkt;
10788 10794 mptsas_diag_request_t *diag = pkt->pkt_ha_private;
10789 10795 uint32_t request_desc_low, i;
10790 10796
10791 10797 ASSERT(mutex_owned(&mpt->m_mutex));
10792 10798
10793 10799 /*
10794 10800 * Form the diag message depending on the post or release function.
10795 10801 */
10796 10802 if (diag->function == MPI2_FUNCTION_DIAG_BUFFER_POST) {
10797 10803 pDiag_post_msg = (pMpi2DiagBufferPostRequest_t)
10798 10804 (mpt->m_req_frame + (mpt->m_req_frame_size *
10799 10805 cmd->cmd_slot));
10800 10806 bzero(pDiag_post_msg, mpt->m_req_frame_size);
10801 10807 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->Function,
10802 10808 diag->function);
10803 10809 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->BufferType,
10804 10810 diag->pBuffer->buffer_type);
10805 10811 ddi_put8(mpt->m_acc_req_frame_hdl,
10806 10812 &pDiag_post_msg->ExtendedType,
10807 10813 diag->pBuffer->extended_type);
10808 10814 ddi_put32(mpt->m_acc_req_frame_hdl,
10809 10815 &pDiag_post_msg->BufferLength,
10810 10816 diag->pBuffer->buffer_data.size);
10811 10817 for (i = 0; i < (sizeof (pDiag_post_msg->ProductSpecific) / 4);
10812 10818 i++) {
10813 10819 ddi_put32(mpt->m_acc_req_frame_hdl,
10814 10820 &pDiag_post_msg->ProductSpecific[i],
10815 10821 diag->pBuffer->product_specific[i]);
10816 10822 }
10817 10823 ddi_put32(mpt->m_acc_req_frame_hdl,
10818 10824 &pDiag_post_msg->BufferAddress.Low,
10819 10825 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress
10820 10826 & 0xffffffffull));
10821 10827 ddi_put32(mpt->m_acc_req_frame_hdl,
10822 10828 &pDiag_post_msg->BufferAddress.High,
10823 10829 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress
10824 10830 >> 32));
10825 10831 } else {
10826 10832 pDiag_release_msg = (pMpi2DiagReleaseRequest_t)
10827 10833 (mpt->m_req_frame + (mpt->m_req_frame_size *
10828 10834 cmd->cmd_slot));
10829 10835 bzero(pDiag_release_msg, mpt->m_req_frame_size);
10830 10836 ddi_put8(mpt->m_acc_req_frame_hdl,
10831 10837 &pDiag_release_msg->Function, diag->function);
10832 10838 ddi_put8(mpt->m_acc_req_frame_hdl,
10833 10839 &pDiag_release_msg->BufferType,
10834 10840 diag->pBuffer->buffer_type);
10835 10841 }
10836 10842
10837 10843 /*
10838 10844 * Send the message
10839 10845 */
10840 10846 (void) ddi_dma_sync(mpt->m_dma_req_frame_hdl, 0, 0,
10841 10847 DDI_DMA_SYNC_FORDEV);
10842 10848 request_desc_low = (cmd->cmd_slot << 16) +
10843 10849 MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
10844 10850 cmd->cmd_rfm = NULL;
10845 10851 mpt->m_active->m_slot[cmd->cmd_slot] = cmd;
10846 10852 MPTSAS_START_CMD(mpt, request_desc_low, 0);
10847 10853 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
10848 10854 DDI_SUCCESS) ||
10849 10855 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
10850 10856 DDI_SUCCESS)) {
10851 10857 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
10852 10858 }
10853 10859 }
10854 10860
10855 10861 static int
10856 10862 mptsas_post_fw_diag_buffer(mptsas_t *mpt,
10857 10863 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code)
10858 10864 {
10859 10865 mptsas_diag_request_t diag;
10860 10866 int status, slot_num, post_flags = 0;
10861 10867 mptsas_cmd_t *cmd = NULL;
10862 10868 struct scsi_pkt *pkt;
10863 10869 pMpi2DiagBufferPostReply_t reply;
10864 10870 uint16_t iocstatus;
10865 10871 uint32_t iocloginfo, transfer_length;
10866 10872
10867 10873 /*
10868 10874 * If buffer is not enabled, just leave.
10869 10875 */
10870 10876 *return_code = MPTSAS_FW_DIAG_ERROR_POST_FAILED;
10871 10877 if (!pBuffer->enabled) {
10872 10878 status = DDI_FAILURE;
10873 10879 goto out;
10874 10880 }
10875 10881
10876 10882 /*
10877 10883 * Clear some flags initially.
10878 10884 */
10879 10885 pBuffer->force_release = FALSE;
10880 10886 pBuffer->valid_data = FALSE;
10881 10887 pBuffer->owned_by_firmware = FALSE;
10882 10888
10883 10889 /*
10884 10890 * Get a cmd buffer from the cmd buffer pool
10885 10891 */
10886 10892 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
10887 10893 status = DDI_FAILURE;
10888 10894 mptsas_log(mpt, CE_NOTE, "command pool is full: Post FW Diag");
10889 10895 goto out;
10890 10896 }
10891 10897 post_flags |= MPTSAS_REQUEST_POOL_CMD;
10892 10898
10893 10899 bzero((caddr_t)cmd, sizeof (*cmd));
10894 10900 bzero((caddr_t)pkt, scsi_pkt_size());
10895 10901
10896 10902 cmd->ioc_cmd_slot = (uint32_t)(slot_num);
10897 10903
10898 10904 diag.pBuffer = pBuffer;
10899 10905 diag.function = MPI2_FUNCTION_DIAG_BUFFER_POST;
10900 10906
10901 10907 /*
10902 10908 * Form a blank cmd/pkt to store the acknowledgement message
10903 10909 */
10904 10910 pkt->pkt_ha_private = (opaque_t)&diag;
10905 10911 pkt->pkt_flags = FLAG_HEAD;
10906 10912 pkt->pkt_time = 60;
10907 10913 cmd->cmd_pkt = pkt;
10908 10914 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG;
10909 10915
10910 10916 /*
10911 10917 * Save the command in a slot
10912 10918 */
10913 10919 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
10914 10920 /*
10915 10921 * Once passthru command get slot, set cmd_flags
10916 10922 * CFLAG_PREPARED.
10917 10923 */
10918 10924 cmd->cmd_flags |= CFLAG_PREPARED;
10919 10925 mptsas_start_diag(mpt, cmd);
10920 10926 } else {
10921 10927 mptsas_waitq_add(mpt, cmd);
10922 10928 }
10923 10929
10924 10930 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
10925 10931 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex);
10926 10932 }
10927 10933
10928 10934 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
10929 10935 status = DDI_FAILURE;
10930 10936 mptsas_log(mpt, CE_WARN, "Post FW Diag command timeout");
10931 10937 goto out;
10932 10938 }
10933 10939
10934 10940 /*
10935 10941 * cmd_rfm points to the reply message if a reply was given. Check the
10936 10942 * IOCStatus to make sure everything went OK with the FW diag request
10937 10943 * and set buffer flags.
10938 10944 */
10939 10945 if (cmd->cmd_rfm) {
10940 10946 post_flags |= MPTSAS_ADDRESS_REPLY;
10941 10947 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
10942 10948 DDI_DMA_SYNC_FORCPU);
10943 10949 reply = (pMpi2DiagBufferPostReply_t)(mpt->m_reply_frame +
10944 10950 (cmd->cmd_rfm - mpt->m_reply_frame_dma_addr));
10945 10951
10946 10952 /*
10947 10953 * Get the reply message data
10948 10954 */
10949 10955 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
10950 10956 &reply->IOCStatus);
10951 10957 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
10952 10958 &reply->IOCLogInfo);
10953 10959 transfer_length = ddi_get32(mpt->m_acc_reply_frame_hdl,
10954 10960 &reply->TransferLength);
10955 10961
10956 10962 /*
10957 10963 * If post failed quit.
10958 10964 */
10959 10965 if (iocstatus != MPI2_IOCSTATUS_SUCCESS) {
10960 10966 status = DDI_FAILURE;
10961 10967 NDBG13(("post FW Diag Buffer failed: IOCStatus=0x%x, "
10962 10968 "IOCLogInfo=0x%x, TransferLength=0x%x", iocstatus,
10963 10969 iocloginfo, transfer_length));
10964 10970 goto out;
10965 10971 }
10966 10972
10967 10973 /*
10968 10974 * Post was successful.
10969 10975 */
10970 10976 pBuffer->valid_data = TRUE;
10971 10977 pBuffer->owned_by_firmware = TRUE;
10972 10978 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
10973 10979 status = DDI_SUCCESS;
10974 10980 }
10975 10981
10976 10982 out:
10977 10983 /*
10978 10984 * Put the reply frame back on the free queue, increment the free
10979 10985 * index, and write the new index to the free index register. But only
10980 10986 * if this reply is an ADDRESS reply.
10981 10987 */
10982 10988 if (post_flags & MPTSAS_ADDRESS_REPLY) {
10983 10989 ddi_put32(mpt->m_acc_free_queue_hdl,
10984 10990 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
10985 10991 cmd->cmd_rfm);
10986 10992 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
10987 10993 DDI_DMA_SYNC_FORDEV);
10988 10994 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
10989 10995 mpt->m_free_index = 0;
10990 10996 }
10991 10997 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
10992 10998 mpt->m_free_index);
10993 10999 }
10994 11000 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
10995 11001 mptsas_remove_cmd(mpt, cmd);
10996 11002 post_flags &= (~MPTSAS_REQUEST_POOL_CMD);
10997 11003 }
10998 11004 if (post_flags & MPTSAS_REQUEST_POOL_CMD) {
10999 11005 mptsas_return_to_pool(mpt, cmd);
11000 11006 }
11001 11007
11002 11008 return (status);
11003 11009 }
11004 11010
11005 11011 static int
11006 11012 mptsas_release_fw_diag_buffer(mptsas_t *mpt,
11007 11013 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code,
11008 11014 uint32_t diag_type)
11009 11015 {
11010 11016 mptsas_diag_request_t diag;
11011 11017 int status, slot_num, rel_flags = 0;
11012 11018 mptsas_cmd_t *cmd = NULL;
11013 11019 struct scsi_pkt *pkt;
11014 11020 pMpi2DiagReleaseReply_t reply;
11015 11021 uint16_t iocstatus;
11016 11022 uint32_t iocloginfo;
11017 11023
11018 11024 /*
11019 11025 * If buffer is not enabled, just leave.
11020 11026 */
11021 11027 *return_code = MPTSAS_FW_DIAG_ERROR_RELEASE_FAILED;
11022 11028 if (!pBuffer->enabled) {
11023 11029 mptsas_log(mpt, CE_NOTE, "This buffer type is not supported "
11024 11030 "by the IOC");
11025 11031 status = DDI_FAILURE;
11026 11032 goto out;
11027 11033 }
11028 11034
11029 11035 /*
11030 11036 * Clear some flags initially.
11031 11037 */
11032 11038 pBuffer->force_release = FALSE;
11033 11039 pBuffer->valid_data = FALSE;
11034 11040 pBuffer->owned_by_firmware = FALSE;
11035 11041
11036 11042 /*
11037 11043 * Get a cmd buffer from the cmd buffer pool
11038 11044 */
11039 11045 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
11040 11046 status = DDI_FAILURE;
11041 11047 mptsas_log(mpt, CE_NOTE, "command pool is full: Release FW "
11042 11048 "Diag");
11043 11049 goto out;
11044 11050 }
11045 11051 rel_flags |= MPTSAS_REQUEST_POOL_CMD;
11046 11052
11047 11053 bzero((caddr_t)cmd, sizeof (*cmd));
11048 11054 bzero((caddr_t)pkt, scsi_pkt_size());
11049 11055
11050 11056 cmd->ioc_cmd_slot = (uint32_t)(slot_num);
11051 11057
11052 11058 diag.pBuffer = pBuffer;
11053 11059 diag.function = MPI2_FUNCTION_DIAG_RELEASE;
11054 11060
11055 11061 /*
11056 11062 * Form a blank cmd/pkt to store the acknowledgement message
11057 11063 */
11058 11064 pkt->pkt_ha_private = (opaque_t)&diag;
11059 11065 pkt->pkt_flags = FLAG_HEAD;
11060 11066 pkt->pkt_time = 60;
11061 11067 cmd->cmd_pkt = pkt;
11062 11068 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG;
11063 11069
11064 11070 /*
11065 11071 * Save the command in a slot
11066 11072 */
11067 11073 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
11068 11074 /*
11069 11075 * Once passthru command get slot, set cmd_flags
11070 11076 * CFLAG_PREPARED.
11071 11077 */
11072 11078 cmd->cmd_flags |= CFLAG_PREPARED;
11073 11079 mptsas_start_diag(mpt, cmd);
11074 11080 } else {
11075 11081 mptsas_waitq_add(mpt, cmd);
11076 11082 }
11077 11083
11078 11084 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
11079 11085 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex);
11080 11086 }
11081 11087
11082 11088 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
11083 11089 status = DDI_FAILURE;
11084 11090 mptsas_log(mpt, CE_WARN, "Release FW Diag command timeout");
11085 11091 goto out;
11086 11092 }
11087 11093
11088 11094 /*
11089 11095 * cmd_rfm points to the reply message if a reply was given. Check the
11090 11096 * IOCStatus to make sure everything went OK with the FW diag request
11091 11097 * and set buffer flags.
11092 11098 */
11093 11099 if (cmd->cmd_rfm) {
11094 11100 rel_flags |= MPTSAS_ADDRESS_REPLY;
11095 11101 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
11096 11102 DDI_DMA_SYNC_FORCPU);
11097 11103 reply = (pMpi2DiagReleaseReply_t)(mpt->m_reply_frame +
11098 11104 (cmd->cmd_rfm - mpt->m_reply_frame_dma_addr));
11099 11105
11100 11106 /*
11101 11107 * Get the reply message data
11102 11108 */
11103 11109 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
11104 11110 &reply->IOCStatus);
11105 11111 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
11106 11112 &reply->IOCLogInfo);
11107 11113
11108 11114 /*
11109 11115 * If release failed quit.
11110 11116 */
11111 11117 if ((iocstatus != MPI2_IOCSTATUS_SUCCESS) ||
11112 11118 pBuffer->owned_by_firmware) {
11113 11119 status = DDI_FAILURE;
11114 11120 NDBG13(("release FW Diag Buffer failed: "
11115 11121 "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus,
11116 11122 iocloginfo));
11117 11123 goto out;
11118 11124 }
11119 11125
11120 11126 /*
11121 11127 * Release was successful.
11122 11128 */
11123 11129 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
11124 11130 status = DDI_SUCCESS;
11125 11131
11126 11132 /*
11127 11133 * If this was for an UNREGISTER diag type command, clear the
11128 11134 * unique ID.
11129 11135 */
11130 11136 if (diag_type == MPTSAS_FW_DIAG_TYPE_UNREGISTER) {
11131 11137 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID;
11132 11138 }
11133 11139 }
11134 11140
11135 11141 out:
11136 11142 /*
11137 11143 * Put the reply frame back on the free queue, increment the free
11138 11144 * index, and write the new index to the free index register. But only
11139 11145 * if this reply is an ADDRESS reply.
11140 11146 */
11141 11147 if (rel_flags & MPTSAS_ADDRESS_REPLY) {
11142 11148 ddi_put32(mpt->m_acc_free_queue_hdl,
11143 11149 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
11144 11150 cmd->cmd_rfm);
11145 11151 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
11146 11152 DDI_DMA_SYNC_FORDEV);
11147 11153 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
11148 11154 mpt->m_free_index = 0;
11149 11155 }
11150 11156 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
11151 11157 mpt->m_free_index);
11152 11158 }
11153 11159 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
11154 11160 mptsas_remove_cmd(mpt, cmd);
11155 11161 rel_flags &= (~MPTSAS_REQUEST_POOL_CMD);
11156 11162 }
11157 11163 if (rel_flags & MPTSAS_REQUEST_POOL_CMD) {
11158 11164 mptsas_return_to_pool(mpt, cmd);
11159 11165 }
11160 11166
11161 11167 return (status);
11162 11168 }
11163 11169
11164 11170 static int
11165 11171 mptsas_diag_register(mptsas_t *mpt, mptsas_fw_diag_register_t *diag_register,
11166 11172 uint32_t *return_code)
11167 11173 {
11168 11174 mptsas_fw_diagnostic_buffer_t *pBuffer;
11169 11175 uint8_t extended_type, buffer_type, i;
11170 11176 uint32_t buffer_size;
11171 11177 uint32_t unique_id;
11172 11178 int status;
11173 11179
11174 11180 ASSERT(mutex_owned(&mpt->m_mutex));
11175 11181
11176 11182 extended_type = diag_register->ExtendedType;
11177 11183 buffer_type = diag_register->BufferType;
11178 11184 buffer_size = diag_register->RequestedBufferSize;
11179 11185 unique_id = diag_register->UniqueId;
11180 11186
11181 11187 /*
11182 11188 * Check for valid buffer type
11183 11189 */
11184 11190 if (buffer_type >= MPI2_DIAG_BUF_TYPE_COUNT) {
11185 11191 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
11186 11192 return (DDI_FAILURE);
11187 11193 }
11188 11194
11189 11195 /*
11190 11196 * Get the current buffer and look up the unique ID. The unique ID
11191 11197 * should not be found. If it is, the ID is already in use.
11192 11198 */
11193 11199 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
11194 11200 pBuffer = &mpt->m_fw_diag_buffer_list[buffer_type];
11195 11201 if (i != MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
11196 11202 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11197 11203 return (DDI_FAILURE);
11198 11204 }
11199 11205
11200 11206 /*
11201 11207 * The buffer's unique ID should not be registered yet, and the given
11202 11208 * unique ID cannot be 0.
11203 11209 */
11204 11210 if ((pBuffer->unique_id != MPTSAS_FW_DIAG_INVALID_UID) ||
11205 11211 (unique_id == MPTSAS_FW_DIAG_INVALID_UID)) {
11206 11212 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11207 11213 return (DDI_FAILURE);
11208 11214 }
11209 11215
11210 11216 /*
11211 11217 * If this buffer is already posted as immediate, just change owner.
11212 11218 */
11213 11219 if (pBuffer->immediate && pBuffer->owned_by_firmware &&
11214 11220 (pBuffer->unique_id == MPTSAS_FW_DIAG_INVALID_UID)) {
11215 11221 pBuffer->immediate = FALSE;
11216 11222 pBuffer->unique_id = unique_id;
11217 11223 return (DDI_SUCCESS);
11218 11224 }
11219 11225
11220 11226 /*
11221 11227 * Post a new buffer after checking if it's enabled. The DMA buffer
11222 11228 * that is allocated will be contiguous (sgl_len = 1).
11223 11229 */
11224 11230 if (!pBuffer->enabled) {
11225 11231 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER;
11226 11232 return (DDI_FAILURE);
11227 11233 }
11228 11234 bzero(&pBuffer->buffer_data, sizeof (mptsas_dma_alloc_state_t));
11229 11235 pBuffer->buffer_data.size = buffer_size;
11230 11236 if (mptsas_dma_alloc(mpt, &pBuffer->buffer_data) != DDI_SUCCESS) {
11231 11237 mptsas_log(mpt, CE_WARN, "failed to alloc DMA resource for "
11232 11238 "diag buffer: size = %d bytes", buffer_size);
11233 11239 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER;
11234 11240 return (DDI_FAILURE);
11235 11241 }
11236 11242
11237 11243 /*
11238 11244 * Copy the given info to the diag buffer and post the buffer.
11239 11245 */
11240 11246 pBuffer->buffer_type = buffer_type;
11241 11247 pBuffer->immediate = FALSE;
11242 11248 if (buffer_type == MPI2_DIAG_BUF_TYPE_TRACE) {
11243 11249 for (i = 0; i < (sizeof (pBuffer->product_specific) / 4);
11244 11250 i++) {
11245 11251 pBuffer->product_specific[i] =
11246 11252 diag_register->ProductSpecific[i];
11247 11253 }
11248 11254 }
11249 11255 pBuffer->extended_type = extended_type;
11250 11256 pBuffer->unique_id = unique_id;
11251 11257 status = mptsas_post_fw_diag_buffer(mpt, pBuffer, return_code);
11252 11258
11253 11259 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) !=
11254 11260 DDI_SUCCESS) {
11255 11261 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed in "
11256 11262 "mptsas_diag_register.");
11257 11263 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
11258 11264 status = DDI_FAILURE;
11259 11265 }
11260 11266
11261 11267 /*
11262 11268 * In case there was a failure, free the DMA buffer.
11263 11269 */
11264 11270 if (status == DDI_FAILURE) {
11265 11271 mptsas_dma_free(&pBuffer->buffer_data);
11266 11272 }
11267 11273
11268 11274 return (status);
11269 11275 }
11270 11276
11271 11277 static int
11272 11278 mptsas_diag_unregister(mptsas_t *mpt,
11273 11279 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code)
11274 11280 {
11275 11281 mptsas_fw_diagnostic_buffer_t *pBuffer;
11276 11282 uint8_t i;
11277 11283 uint32_t unique_id;
11278 11284 int status;
11279 11285
11280 11286 ASSERT(mutex_owned(&mpt->m_mutex));
11281 11287
11282 11288 unique_id = diag_unregister->UniqueId;
11283 11289
11284 11290 /*
11285 11291 * Get the current buffer and look up the unique ID. The unique ID
11286 11292 * should be there.
11287 11293 */
11288 11294 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
11289 11295 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
11290 11296 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11291 11297 return (DDI_FAILURE);
11292 11298 }
11293 11299
11294 11300 pBuffer = &mpt->m_fw_diag_buffer_list[i];
11295 11301
11296 11302 /*
11297 11303 * Try to release the buffer from FW before freeing it. If release
11298 11304 * fails, don't free the DMA buffer in case FW tries to access it
11299 11305 * later. If buffer is not owned by firmware, can't release it.
11300 11306 */
11301 11307 if (!pBuffer->owned_by_firmware) {
11302 11308 status = DDI_SUCCESS;
11303 11309 } else {
11304 11310 status = mptsas_release_fw_diag_buffer(mpt, pBuffer,
11305 11311 return_code, MPTSAS_FW_DIAG_TYPE_UNREGISTER);
11306 11312 }
11307 11313
11308 11314 /*
11309 11315 * At this point, return the current status no matter what happens with
11310 11316 * the DMA buffer.
11311 11317 */
11312 11318 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID;
11313 11319 if (status == DDI_SUCCESS) {
11314 11320 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) !=
11315 11321 DDI_SUCCESS) {
11316 11322 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed "
11317 11323 "in mptsas_diag_unregister.");
11318 11324 ddi_fm_service_impact(mpt->m_dip,
11319 11325 DDI_SERVICE_UNAFFECTED);
11320 11326 }
11321 11327 mptsas_dma_free(&pBuffer->buffer_data);
11322 11328 }
11323 11329
11324 11330 return (status);
11325 11331 }
11326 11332
11327 11333 static int
11328 11334 mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query,
11329 11335 uint32_t *return_code)
11330 11336 {
11331 11337 mptsas_fw_diagnostic_buffer_t *pBuffer;
11332 11338 uint8_t i;
11333 11339 uint32_t unique_id;
11334 11340
11335 11341 ASSERT(mutex_owned(&mpt->m_mutex));
11336 11342
11337 11343 unique_id = diag_query->UniqueId;
11338 11344
11339 11345 /*
11340 11346 * If ID is valid, query on ID.
11341 11347 * If ID is invalid, query on buffer type.
11342 11348 */
11343 11349 if (unique_id == MPTSAS_FW_DIAG_INVALID_UID) {
11344 11350 i = diag_query->BufferType;
11345 11351 if (i >= MPI2_DIAG_BUF_TYPE_COUNT) {
11346 11352 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11347 11353 return (DDI_FAILURE);
11348 11354 }
11349 11355 } else {
11350 11356 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
11351 11357 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
11352 11358 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11353 11359 return (DDI_FAILURE);
11354 11360 }
11355 11361 }
11356 11362
11357 11363 /*
11358 11364 * Fill query structure with the diag buffer info.
11359 11365 */
11360 11366 pBuffer = &mpt->m_fw_diag_buffer_list[i];
11361 11367 diag_query->BufferType = pBuffer->buffer_type;
11362 11368 diag_query->ExtendedType = pBuffer->extended_type;
11363 11369 if (diag_query->BufferType == MPI2_DIAG_BUF_TYPE_TRACE) {
11364 11370 for (i = 0; i < (sizeof (diag_query->ProductSpecific) / 4);
11365 11371 i++) {
11366 11372 diag_query->ProductSpecific[i] =
11367 11373 pBuffer->product_specific[i];
11368 11374 }
11369 11375 }
11370 11376 diag_query->TotalBufferSize = pBuffer->buffer_data.size;
11371 11377 diag_query->DriverAddedBufferSize = 0;
11372 11378 diag_query->UniqueId = pBuffer->unique_id;
11373 11379 diag_query->ApplicationFlags = 0;
11374 11380 diag_query->DiagnosticFlags = 0;
11375 11381
11376 11382 /*
11377 11383 * Set/Clear application flags
11378 11384 */
11379 11385 if (pBuffer->immediate) {
11380 11386 diag_query->ApplicationFlags &= ~MPTSAS_FW_DIAG_FLAG_APP_OWNED;
11381 11387 } else {
11382 11388 diag_query->ApplicationFlags |= MPTSAS_FW_DIAG_FLAG_APP_OWNED;
11383 11389 }
11384 11390 if (pBuffer->valid_data || pBuffer->owned_by_firmware) {
11385 11391 diag_query->ApplicationFlags |=
11386 11392 MPTSAS_FW_DIAG_FLAG_BUFFER_VALID;
11387 11393 } else {
11388 11394 diag_query->ApplicationFlags &=
11389 11395 ~MPTSAS_FW_DIAG_FLAG_BUFFER_VALID;
11390 11396 }
11391 11397 if (pBuffer->owned_by_firmware) {
11392 11398 diag_query->ApplicationFlags |=
11393 11399 MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS;
11394 11400 } else {
11395 11401 diag_query->ApplicationFlags &=
11396 11402 ~MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS;
11397 11403 }
11398 11404
11399 11405 return (DDI_SUCCESS);
11400 11406 }
11401 11407
11402 11408 static int
11403 11409 mptsas_diag_read_buffer(mptsas_t *mpt,
11404 11410 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf,
11405 11411 uint32_t *return_code, int ioctl_mode)
11406 11412 {
11407 11413 mptsas_fw_diagnostic_buffer_t *pBuffer;
11408 11414 uint8_t i, *pData;
11409 11415 uint32_t unique_id, byte;
11410 11416 int status;
11411 11417
11412 11418 ASSERT(mutex_owned(&mpt->m_mutex));
11413 11419
11414 11420 unique_id = diag_read_buffer->UniqueId;
11415 11421
11416 11422 /*
11417 11423 * Get the current buffer and look up the unique ID. The unique ID
11418 11424 * should be there.
11419 11425 */
11420 11426 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
11421 11427 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
11422 11428 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11423 11429 return (DDI_FAILURE);
11424 11430 }
11425 11431
11426 11432 pBuffer = &mpt->m_fw_diag_buffer_list[i];
11427 11433
11428 11434 /*
11429 11435 * Make sure requested read is within limits
11430 11436 */
11431 11437 if (diag_read_buffer->StartingOffset + diag_read_buffer->BytesToRead >
11432 11438 pBuffer->buffer_data.size) {
11433 11439 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
11434 11440 return (DDI_FAILURE);
11435 11441 }
11436 11442
11437 11443 /*
11438 11444 * Copy the requested data from DMA to the diag_read_buffer. The DMA
11439 11445 * buffer that was allocated is one contiguous buffer.
11440 11446 */
11441 11447 pData = (uint8_t *)(pBuffer->buffer_data.memp +
11442 11448 diag_read_buffer->StartingOffset);
11443 11449 (void) ddi_dma_sync(pBuffer->buffer_data.handle, 0, 0,
11444 11450 DDI_DMA_SYNC_FORCPU);
11445 11451 for (byte = 0; byte < diag_read_buffer->BytesToRead; byte++) {
11446 11452 if (ddi_copyout(pData + byte, ioctl_buf + byte, 1, ioctl_mode)
11447 11453 != 0) {
11448 11454 return (DDI_FAILURE);
11449 11455 }
11450 11456 }
11451 11457 diag_read_buffer->Status = 0;
11452 11458
11453 11459 /*
11454 11460 * Set or clear the Force Release flag.
11455 11461 */
11456 11462 if (pBuffer->force_release) {
11457 11463 diag_read_buffer->Flags |= MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE;
11458 11464 } else {
11459 11465 diag_read_buffer->Flags &= ~MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE;
11460 11466 }
11461 11467
11462 11468 /*
11463 11469 * If buffer is to be reregistered, make sure it's not already owned by
11464 11470 * firmware first.
11465 11471 */
11466 11472 status = DDI_SUCCESS;
11467 11473 if (!pBuffer->owned_by_firmware) {
11468 11474 if (diag_read_buffer->Flags & MPTSAS_FW_DIAG_FLAG_REREGISTER) {
11469 11475 status = mptsas_post_fw_diag_buffer(mpt, pBuffer,
11470 11476 return_code);
11471 11477 }
11472 11478 }
11473 11479
11474 11480 return (status);
11475 11481 }
11476 11482
11477 11483 static int
11478 11484 mptsas_diag_release(mptsas_t *mpt, mptsas_fw_diag_release_t *diag_release,
11479 11485 uint32_t *return_code)
11480 11486 {
11481 11487 mptsas_fw_diagnostic_buffer_t *pBuffer;
11482 11488 uint8_t i;
11483 11489 uint32_t unique_id;
11484 11490 int status;
11485 11491
11486 11492 ASSERT(mutex_owned(&mpt->m_mutex));
11487 11493
11488 11494 unique_id = diag_release->UniqueId;
11489 11495
11490 11496 /*
11491 11497 * Get the current buffer and look up the unique ID. The unique ID
11492 11498 * should be there.
11493 11499 */
11494 11500 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
11495 11501 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
11496 11502 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11497 11503 return (DDI_FAILURE);
11498 11504 }
11499 11505
11500 11506 pBuffer = &mpt->m_fw_diag_buffer_list[i];
11501 11507
11502 11508 /*
11503 11509 * If buffer is not owned by firmware, it's already been released.
11504 11510 */
11505 11511 if (!pBuffer->owned_by_firmware) {
11506 11512 *return_code = MPTSAS_FW_DIAG_ERROR_ALREADY_RELEASED;
11507 11513 return (DDI_FAILURE);
11508 11514 }
11509 11515
11510 11516 /*
11511 11517 * Release the buffer.
11512 11518 */
11513 11519 status = mptsas_release_fw_diag_buffer(mpt, pBuffer, return_code,
11514 11520 MPTSAS_FW_DIAG_TYPE_RELEASE);
11515 11521 return (status);
11516 11522 }
11517 11523
11518 11524 static int
11519 11525 mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, uint8_t *diag_action,
11520 11526 uint32_t length, uint32_t *return_code, int ioctl_mode)
11521 11527 {
11522 11528 mptsas_fw_diag_register_t diag_register;
11523 11529 mptsas_fw_diag_unregister_t diag_unregister;
11524 11530 mptsas_fw_diag_query_t diag_query;
11525 11531 mptsas_diag_read_buffer_t diag_read_buffer;
11526 11532 mptsas_fw_diag_release_t diag_release;
11527 11533 int status = DDI_SUCCESS;
11528 11534 uint32_t original_return_code, read_buf_len;
11529 11535
11530 11536 ASSERT(mutex_owned(&mpt->m_mutex));
11531 11537
11532 11538 original_return_code = *return_code;
11533 11539 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
11534 11540
11535 11541 switch (action) {
11536 11542 case MPTSAS_FW_DIAG_TYPE_REGISTER:
11537 11543 if (!length) {
11538 11544 *return_code =
11539 11545 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
11540 11546 status = DDI_FAILURE;
11541 11547 break;
11542 11548 }
11543 11549 if (ddi_copyin(diag_action, &diag_register,
11544 11550 sizeof (diag_register), ioctl_mode) != 0) {
11545 11551 return (DDI_FAILURE);
11546 11552 }
11547 11553 status = mptsas_diag_register(mpt, &diag_register,
11548 11554 return_code);
11549 11555 break;
11550 11556
11551 11557 case MPTSAS_FW_DIAG_TYPE_UNREGISTER:
11552 11558 if (length < sizeof (diag_unregister)) {
11553 11559 *return_code =
11554 11560 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
11555 11561 status = DDI_FAILURE;
11556 11562 break;
11557 11563 }
11558 11564 if (ddi_copyin(diag_action, &diag_unregister,
11559 11565 sizeof (diag_unregister), ioctl_mode) != 0) {
11560 11566 return (DDI_FAILURE);
11561 11567 }
11562 11568 status = mptsas_diag_unregister(mpt, &diag_unregister,
11563 11569 return_code);
11564 11570 break;
11565 11571
11566 11572 case MPTSAS_FW_DIAG_TYPE_QUERY:
11567 11573 if (length < sizeof (diag_query)) {
11568 11574 *return_code =
11569 11575 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
11570 11576 status = DDI_FAILURE;
11571 11577 break;
11572 11578 }
11573 11579 if (ddi_copyin(diag_action, &diag_query,
11574 11580 sizeof (diag_query), ioctl_mode) != 0) {
11575 11581 return (DDI_FAILURE);
11576 11582 }
11577 11583 status = mptsas_diag_query(mpt, &diag_query,
11578 11584 return_code);
11579 11585 if (status == DDI_SUCCESS) {
11580 11586 if (ddi_copyout(&diag_query, diag_action,
11581 11587 sizeof (diag_query), ioctl_mode) != 0) {
11582 11588 return (DDI_FAILURE);
11583 11589 }
11584 11590 }
11585 11591 break;
11586 11592
11587 11593 case MPTSAS_FW_DIAG_TYPE_READ_BUFFER:
11588 11594 if (ddi_copyin(diag_action, &diag_read_buffer,
11589 11595 sizeof (diag_read_buffer) - 4, ioctl_mode) != 0) {
11590 11596 return (DDI_FAILURE);
11591 11597 }
11592 11598 read_buf_len = sizeof (diag_read_buffer) -
11593 11599 sizeof (diag_read_buffer.DataBuffer) +
11594 11600 diag_read_buffer.BytesToRead;
11595 11601 if (length < read_buf_len) {
11596 11602 *return_code =
11597 11603 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
11598 11604 status = DDI_FAILURE;
11599 11605 break;
11600 11606 }
11601 11607 status = mptsas_diag_read_buffer(mpt,
11602 11608 &diag_read_buffer, diag_action +
11603 11609 sizeof (diag_read_buffer) - 4, return_code,
11604 11610 ioctl_mode);
11605 11611 if (status == DDI_SUCCESS) {
11606 11612 if (ddi_copyout(&diag_read_buffer, diag_action,
11607 11613 sizeof (diag_read_buffer) - 4, ioctl_mode)
11608 11614 != 0) {
11609 11615 return (DDI_FAILURE);
11610 11616 }
11611 11617 }
11612 11618 break;
11613 11619
11614 11620 case MPTSAS_FW_DIAG_TYPE_RELEASE:
11615 11621 if (length < sizeof (diag_release)) {
11616 11622 *return_code =
11617 11623 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
11618 11624 status = DDI_FAILURE;
11619 11625 break;
11620 11626 }
11621 11627 if (ddi_copyin(diag_action, &diag_release,
11622 11628 sizeof (diag_release), ioctl_mode) != 0) {
11623 11629 return (DDI_FAILURE);
11624 11630 }
11625 11631 status = mptsas_diag_release(mpt, &diag_release,
11626 11632 return_code);
11627 11633 break;
11628 11634
11629 11635 default:
11630 11636 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
11631 11637 status = DDI_FAILURE;
11632 11638 break;
11633 11639 }
11634 11640
11635 11641 if ((status == DDI_FAILURE) &&
11636 11642 (original_return_code == MPTSAS_FW_DIAG_NEW) &&
11637 11643 (*return_code != MPTSAS_FW_DIAG_ERROR_SUCCESS)) {
11638 11644 status = DDI_SUCCESS;
11639 11645 }
11640 11646
11641 11647 return (status);
11642 11648 }
11643 11649
11644 11650 static int
11645 11651 mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *user_data, int mode)
11646 11652 {
11647 11653 int status;
11648 11654 mptsas_diag_action_t driver_data;
11649 11655
11650 11656 ASSERT(mutex_owned(&mpt->m_mutex));
11651 11657
11652 11658 /*
11653 11659 * Copy the user data to a driver data buffer.
11654 11660 */
11655 11661 if (ddi_copyin(user_data, &driver_data, sizeof (mptsas_diag_action_t),
11656 11662 mode) == 0) {
11657 11663 /*
11658 11664 * Send diag action request if Action is valid
11659 11665 */
11660 11666 if (driver_data.Action == MPTSAS_FW_DIAG_TYPE_REGISTER ||
11661 11667 driver_data.Action == MPTSAS_FW_DIAG_TYPE_UNREGISTER ||
11662 11668 driver_data.Action == MPTSAS_FW_DIAG_TYPE_QUERY ||
11663 11669 driver_data.Action == MPTSAS_FW_DIAG_TYPE_READ_BUFFER ||
11664 11670 driver_data.Action == MPTSAS_FW_DIAG_TYPE_RELEASE) {
11665 11671 status = mptsas_do_diag_action(mpt, driver_data.Action,
11666 11672 (void *)(uintptr_t)driver_data.PtrDiagAction,
11667 11673 driver_data.Length, &driver_data.ReturnCode,
11668 11674 mode);
11669 11675 if (status == DDI_SUCCESS) {
11670 11676 if (ddi_copyout(&driver_data.ReturnCode,
11671 11677 &user_data->ReturnCode,
11672 11678 sizeof (user_data->ReturnCode), mode)
11673 11679 != 0) {
11674 11680 status = EFAULT;
11675 11681 } else {
11676 11682 status = 0;
11677 11683 }
11678 11684 } else {
11679 11685 status = EIO;
11680 11686 }
11681 11687 } else {
11682 11688 status = EINVAL;
11683 11689 }
11684 11690 } else {
11685 11691 status = EFAULT;
11686 11692 }
11687 11693
11688 11694 return (status);
11689 11695 }
11690 11696
11691 11697 /*
11692 11698 * This routine handles the "event query" ioctl.
11693 11699 */
11694 11700 static int
11695 11701 mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, int mode,
11696 11702 int *rval)
11697 11703 {
11698 11704 int status;
11699 11705 mptsas_event_query_t driverdata;
11700 11706 uint8_t i;
11701 11707
11702 11708 driverdata.Entries = MPTSAS_EVENT_QUEUE_SIZE;
11703 11709
11704 11710 mutex_enter(&mpt->m_mutex);
11705 11711 for (i = 0; i < 4; i++) {
11706 11712 driverdata.Types[i] = mpt->m_event_mask[i];
11707 11713 }
11708 11714 mutex_exit(&mpt->m_mutex);
11709 11715
11710 11716 if (ddi_copyout(&driverdata, data, sizeof (driverdata), mode) != 0) {
11711 11717 status = EFAULT;
11712 11718 } else {
11713 11719 *rval = MPTIOCTL_STATUS_GOOD;
11714 11720 status = 0;
11715 11721 }
11716 11722
11717 11723 return (status);
11718 11724 }
11719 11725
11720 11726 /*
11721 11727 * This routine handles the "event enable" ioctl.
11722 11728 */
11723 11729 static int
11724 11730 mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, int mode,
11725 11731 int *rval)
11726 11732 {
11727 11733 int status;
11728 11734 mptsas_event_enable_t driverdata;
11729 11735 uint8_t i;
11730 11736
11731 11737 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) {
11732 11738 mutex_enter(&mpt->m_mutex);
11733 11739 for (i = 0; i < 4; i++) {
11734 11740 mpt->m_event_mask[i] = driverdata.Types[i];
11735 11741 }
11736 11742 mutex_exit(&mpt->m_mutex);
11737 11743
11738 11744 *rval = MPTIOCTL_STATUS_GOOD;
11739 11745 status = 0;
11740 11746 } else {
11741 11747 status = EFAULT;
11742 11748 }
11743 11749 return (status);
11744 11750 }
11745 11751
11746 11752 /*
11747 11753 * This routine handles the "event report" ioctl.
11748 11754 */
11749 11755 static int
11750 11756 mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, int mode,
11751 11757 int *rval)
11752 11758 {
11753 11759 int status;
11754 11760 mptsas_event_report_t driverdata;
11755 11761
11756 11762 mutex_enter(&mpt->m_mutex);
11757 11763
11758 11764 if (ddi_copyin(&data->Size, &driverdata.Size, sizeof (driverdata.Size),
11759 11765 mode) == 0) {
11760 11766 if (driverdata.Size >= sizeof (mpt->m_events)) {
11761 11767 if (ddi_copyout(mpt->m_events, data->Events,
11762 11768 sizeof (mpt->m_events), mode) != 0) {
11763 11769 status = EFAULT;
11764 11770 } else {
11765 11771 if (driverdata.Size > sizeof (mpt->m_events)) {
11766 11772 driverdata.Size =
11767 11773 sizeof (mpt->m_events);
11768 11774 if (ddi_copyout(&driverdata.Size,
11769 11775 &data->Size,
11770 11776 sizeof (driverdata.Size),
11771 11777 mode) != 0) {
11772 11778 status = EFAULT;
11773 11779 } else {
11774 11780 *rval = MPTIOCTL_STATUS_GOOD;
11775 11781 status = 0;
11776 11782 }
11777 11783 } else {
11778 11784 *rval = MPTIOCTL_STATUS_GOOD;
11779 11785 status = 0;
11780 11786 }
11781 11787 }
11782 11788 } else {
11783 11789 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT;
11784 11790 status = 0;
11785 11791 }
11786 11792 } else {
11787 11793 status = EFAULT;
11788 11794 }
11789 11795
11790 11796 mutex_exit(&mpt->m_mutex);
11791 11797 return (status);
11792 11798 }
11793 11799
11794 11800 static void
11795 11801 mptsas_lookup_pci_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data)
11796 11802 {
11797 11803 int *reg_data;
11798 11804 uint_t reglen;
11799 11805
11800 11806 /*
11801 11807 * Lookup the 'reg' property and extract the other data
11802 11808 */
11803 11809 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip,
11804 11810 DDI_PROP_DONTPASS, "reg", ®_data, ®len) ==
11805 11811 DDI_PROP_SUCCESS) {
11806 11812 /*
11807 11813 * Extract the PCI data from the 'reg' property first DWORD.
11808 11814 * The entry looks like the following:
11809 11815 * First DWORD:
11810 11816 * Bits 0 - 7 8-bit Register number
11811 11817 * Bits 8 - 10 3-bit Function number
11812 11818 * Bits 11 - 15 5-bit Device number
11813 11819 * Bits 16 - 23 8-bit Bus number
11814 11820 * Bits 24 - 25 2-bit Address Space type identifier
11815 11821 *
11816 11822 */
11817 11823 adapter_data->PciInformation.u.bits.BusNumber =
11818 11824 (reg_data[0] & 0x00FF0000) >> 16;
11819 11825 adapter_data->PciInformation.u.bits.DeviceNumber =
11820 11826 (reg_data[0] & 0x0000F800) >> 11;
11821 11827 adapter_data->PciInformation.u.bits.FunctionNumber =
11822 11828 (reg_data[0] & 0x00000700) >> 8;
11823 11829 ddi_prop_free((void *)reg_data);
11824 11830 } else {
11825 11831 /*
11826 11832 * If we can't determine the PCI data then we fill in FF's for
11827 11833 * the data to indicate this.
11828 11834 */
11829 11835 adapter_data->PCIDeviceHwId = 0xFFFFFFFF;
11830 11836 adapter_data->MpiPortNumber = 0xFFFFFFFF;
11831 11837 adapter_data->PciInformation.u.AsDWORD = 0xFFFFFFFF;
11832 11838 }
11833 11839
11834 11840 /*
11835 11841 * Saved in the mpt->m_fwversion
11836 11842 */
11837 11843 adapter_data->MpiFirmwareVersion = mpt->m_fwversion;
11838 11844 }
11839 11845
11840 11846 static void
11841 11847 mptsas_read_adapter_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data)
11842 11848 {
11843 11849 char *driver_verstr = MPTSAS_MOD_STRING;
11844 11850
11845 11851 mptsas_lookup_pci_data(mpt, adapter_data);
11846 11852 adapter_data->AdapterType = MPTIOCTL_ADAPTER_TYPE_SAS2;
11847 11853 adapter_data->PCIDeviceHwId = (uint32_t)mpt->m_devid;
11848 11854 adapter_data->PCIDeviceHwRev = (uint32_t)mpt->m_revid;
11849 11855 adapter_data->SubSystemId = (uint32_t)mpt->m_ssid;
11850 11856 adapter_data->SubsystemVendorId = (uint32_t)mpt->m_svid;
11851 11857 (void) strcpy((char *)&adapter_data->DriverVersion[0], driver_verstr);
11852 11858 adapter_data->BiosVersion = 0;
11853 11859 (void) mptsas_get_bios_page3(mpt, &adapter_data->BiosVersion);
11854 11860 }
11855 11861
11856 11862 static void
11857 11863 mptsas_read_pci_info(mptsas_t *mpt, mptsas_pci_info_t *pci_info)
11858 11864 {
11859 11865 int *reg_data, i;
11860 11866 uint_t reglen;
11861 11867
11862 11868 /*
11863 11869 * Lookup the 'reg' property and extract the other data
11864 11870 */
11865 11871 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip,
11866 11872 DDI_PROP_DONTPASS, "reg", ®_data, ®len) ==
11867 11873 DDI_PROP_SUCCESS) {
11868 11874 /*
11869 11875 * Extract the PCI data from the 'reg' property first DWORD.
11870 11876 * The entry looks like the following:
11871 11877 * First DWORD:
11872 11878 * Bits 8 - 10 3-bit Function number
11873 11879 * Bits 11 - 15 5-bit Device number
11874 11880 * Bits 16 - 23 8-bit Bus number
11875 11881 */
11876 11882 pci_info->BusNumber = (reg_data[0] & 0x00FF0000) >> 16;
11877 11883 pci_info->DeviceNumber = (reg_data[0] & 0x0000F800) >> 11;
11878 11884 pci_info->FunctionNumber = (reg_data[0] & 0x00000700) >> 8;
11879 11885 ddi_prop_free((void *)reg_data);
11880 11886 } else {
11881 11887 /*
11882 11888 * If we can't determine the PCI info then we fill in FF's for
11883 11889 * the data to indicate this.
11884 11890 */
11885 11891 pci_info->BusNumber = 0xFFFFFFFF;
11886 11892 pci_info->DeviceNumber = 0xFF;
11887 11893 pci_info->FunctionNumber = 0xFF;
11888 11894 }
11889 11895
11890 11896 /*
11891 11897 * Now get the interrupt vector and the pci header. The vector can
11892 11898 * only be 0 right now. The header is the first 256 bytes of config
11893 11899 * space.
11894 11900 */
11895 11901 pci_info->InterruptVector = 0;
11896 11902 for (i = 0; i < sizeof (pci_info->PciHeader); i++) {
11897 11903 pci_info->PciHeader[i] = pci_config_get8(mpt->m_config_handle,
11898 11904 i);
11899 11905 }
11900 11906 }
11901 11907
11902 11908 static int
11903 11909 mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, int mode)
11904 11910 {
11905 11911 int status = 0;
11906 11912 mptsas_reg_access_t driverdata;
11907 11913
11908 11914 mutex_enter(&mpt->m_mutex);
11909 11915 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) {
11910 11916 switch (driverdata.Command) {
11911 11917 /*
11912 11918 * IO access is not supported.
11913 11919 */
11914 11920 case REG_IO_READ:
11915 11921 case REG_IO_WRITE:
11916 11922 mptsas_log(mpt, CE_WARN, "IO access is not "
11917 11923 "supported. Use memory access.");
11918 11924 status = EINVAL;
11919 11925 break;
11920 11926
11921 11927 case REG_MEM_READ:
11922 11928 driverdata.RegData = ddi_get32(mpt->m_datap,
11923 11929 (uint32_t *)(void *)mpt->m_reg +
11924 11930 driverdata.RegOffset);
11925 11931 if (ddi_copyout(&driverdata.RegData,
11926 11932 &data->RegData,
11927 11933 sizeof (driverdata.RegData), mode) != 0) {
11928 11934 mptsas_log(mpt, CE_WARN, "Register "
11929 11935 "Read Failed");
11930 11936 status = EFAULT;
11931 11937 }
11932 11938 break;
11933 11939
11934 11940 case REG_MEM_WRITE:
11935 11941 ddi_put32(mpt->m_datap,
11936 11942 (uint32_t *)(void *)mpt->m_reg +
11937 11943 driverdata.RegOffset,
11938 11944 driverdata.RegData);
11939 11945 break;
11940 11946
11941 11947 default:
11942 11948 status = EINVAL;
11943 11949 break;
↓ open down ↓ |
5479 lines elided |
↑ open up ↑ |
11944 11950 }
11945 11951 } else {
11946 11952 status = EFAULT;
11947 11953 }
11948 11954
11949 11955 mutex_exit(&mpt->m_mutex);
11950 11956 return (status);
11951 11957 }
11952 11958
11953 11959 static int
11960 +led_control(mptsas_t *mpt, intptr_t data, int mode)
11961 +{
11962 + int ret = 0;
11963 + mptsas_led_control_t lc;
11964 + mptsas_target_t *ptgt;
11965 +
11966 + if (ddi_copyin((void *)data, &lc, sizeof (lc), mode) != 0) {
11967 + return (EFAULT);
11968 + }
11969 +
11970 + if ((lc.Command != MPTSAS_LEDCTL_FLAG_SET &&
11971 + lc.Command != MPTSAS_LEDCTL_FLAG_GET) ||
11972 + lc.Led < MPTSAS_LEDCTL_LED_IDENT ||
11973 + lc.Led > MPTSAS_LEDCTL_LED_OK2RM) {
11974 + return (EINVAL);
11975 + }
11976 +
11977 + /* Locate the target we're interrogating... */
11978 + mutex_enter(&mpt->m_mutex);
11979 + ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
11980 + MPTSAS_HASH_FIRST);
11981 + while (ptgt != NULL) {
11982 + if (ptgt->m_enclosure == lc.Enclosure &&
11983 + ptgt->m_slot_num == lc.Slot) {
11984 + break;
11985 + }
11986 + ptgt = (mptsas_target_t *)mptsas_hash_traverse(
11987 + &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
11988 + }
11989 + if (ptgt == NULL) {
11990 + /* We could not find a target for that enclosure/slot. */
11991 + mutex_exit(&mpt->m_mutex);
11992 + return (ENOENT);
11993 + }
11994 +
11995 + if (lc.Command == MPTSAS_LEDCTL_FLAG_SET) {
11996 + /* Update our internal LED state. */
11997 + ptgt->m_led_status &= ~(1 << (lc.Led - 1));
11998 + ptgt->m_led_status |= (!!lc.LedStatus) << (lc.Led - 1);
11999 +
12000 + /* Flush it to the controller. */
12001 + ret = mptsas_flush_led_status(mpt, ptgt);
12002 + mutex_exit(&mpt->m_mutex);
12003 + return (ret);
12004 + }
12005 +
12006 + /* Return our internal LED state. */
12007 + lc.LedStatus = !!(ptgt->m_led_status & (1 << (lc.Led - 1)));
12008 + mutex_exit(&mpt->m_mutex);
12009 +
12010 + if (ddi_copyout(&lc, (void *)data, sizeof (lc), mode) != 0) {
12011 + return (EFAULT);
12012 + }
12013 +
12014 + return (0);
12015 +}
12016 +
12017 +static int
12018 +get_disk_info(mptsas_t *mpt, intptr_t data, int mode)
12019 +{
12020 + int i;
12021 + int count = 0;
12022 + int ret = 0;
12023 + mptsas_target_t *ptgt;
12024 + mptsas_disk_info_t *di;
12025 + STRUCT_DECL(mptsas_get_disk_info, gdi);
12026 +
12027 + STRUCT_INIT(gdi, get_udatamodel());
12028 +
12029 + if (ddi_copyin((void *)data, STRUCT_BUF(gdi), STRUCT_SIZE(gdi),
12030 + mode) != 0) {
12031 + return (EFAULT);
12032 + }
12033 +
12034 +restart:
12035 + /* Find out how many targets there are. */
12036 + mutex_enter(&mpt->m_mutex);
12037 + ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
12038 + MPTSAS_HASH_FIRST);
12039 + while (ptgt != NULL) {
12040 + count++;
12041 + ptgt = (mptsas_target_t *)mptsas_hash_traverse(
12042 + &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
12043 + }
12044 + mutex_exit(&mpt->m_mutex);
12045 +
12046 + /*
12047 + * If we haven't been asked to copy out information on each target,
12048 + * then just return the count.
12049 + */
12050 + STRUCT_FSET(gdi, DiskCount, count);
12051 + if (STRUCT_FGETP(gdi, PtrDiskInfoArray) == NULL)
12052 + goto copy_out;
12053 +
12054 + /*
12055 + * If we haven't been given a large enough buffer to copy out into,
12056 + * let the caller know.
12057 + */
12058 + if (STRUCT_FGET(gdi, DiskInfoArraySize) <
12059 + count * sizeof (mptsas_disk_info_t)) {
12060 + ret = ENOSPC;
12061 + goto copy_out;
12062 + }
12063 +
12064 + di = kmem_zalloc(count * sizeof (mptsas_disk_info_t), KM_SLEEP);
12065 +
12066 + mutex_enter(&mpt->m_mutex);
12067 + i = 0;
12068 + ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
12069 + MPTSAS_HASH_FIRST);
12070 + while (ptgt != NULL) {
12071 + if (i >= count) {
12072 + /*
12073 + * The number of targets changed while we weren't
12074 + * looking. Go again.
12075 + */
12076 + mutex_exit(&mpt->m_mutex);
12077 + kmem_free(di, count * sizeof (mptsas_disk_info_t));
12078 + goto restart;
12079 + }
12080 + di[i].Instance = mpt->m_instance;
12081 + di[i].Enclosure = ptgt->m_enclosure;
12082 + di[i].Slot = ptgt->m_slot_num;
12083 + di[i].SasAddress = ptgt->m_sas_wwn;
12084 +
12085 + ptgt = (mptsas_target_t *)mptsas_hash_traverse(
12086 + &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
12087 + i++;
12088 + }
12089 + mutex_exit(&mpt->m_mutex);
12090 + STRUCT_FSET(gdi, DiskCount, i);
12091 +
12092 + /* Copy out the disk information to the caller. */
12093 + if (ddi_copyout((void *)di, STRUCT_FGETP(gdi, PtrDiskInfoArray),
12094 + i * sizeof (mptsas_disk_info_t), mode) != 0) {
12095 + ret = EFAULT;
12096 + }
12097 +
12098 + kmem_free(di, count * sizeof (mptsas_disk_info_t));
12099 +
12100 +copy_out:
12101 + if (ddi_copyout(STRUCT_BUF(gdi), (void *)data, STRUCT_SIZE(gdi),
12102 + mode) != 0) {
12103 + ret = EFAULT;
12104 + }
12105 +
12106 + return (ret);
12107 +}
12108 +
12109 +static int
11954 12110 mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, cred_t *credp,
11955 12111 int *rval)
11956 12112 {
11957 12113 int status = 0;
11958 12114 mptsas_t *mpt;
11959 12115 mptsas_update_flash_t flashdata;
11960 12116 mptsas_pass_thru_t passthru_data;
11961 12117 mptsas_adapter_data_t adapter_data;
11962 12118 mptsas_pci_info_t pci_info;
11963 12119 int copylen;
11964 12120
11965 12121 int iport_flag = 0;
11966 12122 dev_info_t *dip = NULL;
11967 12123 mptsas_phymask_t phymask = 0;
11968 12124 struct devctl_iocdata *dcp = NULL;
11969 12125 uint32_t slotstatus = 0;
11970 12126 char *addr = NULL;
11971 12127 mptsas_target_t *ptgt = NULL;
11972 12128
11973 12129 *rval = MPTIOCTL_STATUS_GOOD;
11974 12130 if (secpolicy_sys_config(credp, B_FALSE) != 0) {
11975 12131 return (EPERM);
11976 12132 }
11977 12133
11978 12134 mpt = ddi_get_soft_state(mptsas_state, MINOR2INST(getminor(dev)));
11979 12135 if (mpt == NULL) {
11980 12136 /*
11981 12137 * Called from iport node, get the states
11982 12138 */
11983 12139 iport_flag = 1;
11984 12140 dip = mptsas_get_dip_from_dev(dev, &phymask);
11985 12141 if (dip == NULL) {
11986 12142 return (ENXIO);
11987 12143 }
11988 12144 mpt = DIP2MPT(dip);
11989 12145 }
11990 12146 /* Make sure power level is D0 before accessing registers */
11991 12147 mutex_enter(&mpt->m_mutex);
11992 12148 if (mpt->m_options & MPTSAS_OPT_PM) {
11993 12149 (void) pm_busy_component(mpt->m_dip, 0);
11994 12150 if (mpt->m_power_level != PM_LEVEL_D0) {
11995 12151 mutex_exit(&mpt->m_mutex);
11996 12152 if (pm_raise_power(mpt->m_dip, 0, PM_LEVEL_D0) !=
11997 12153 DDI_SUCCESS) {
11998 12154 mptsas_log(mpt, CE_WARN,
11999 12155 "mptsas%d: mptsas_ioctl: Raise power "
12000 12156 "request failed.", mpt->m_instance);
12001 12157 (void) pm_idle_component(mpt->m_dip, 0);
12002 12158 return (ENXIO);
12003 12159 }
12004 12160 } else {
12005 12161 mutex_exit(&mpt->m_mutex);
12006 12162 }
12007 12163 } else {
12008 12164 mutex_exit(&mpt->m_mutex);
12009 12165 }
12010 12166
12011 12167 if (iport_flag) {
12012 12168 status = scsi_hba_ioctl(dev, cmd, data, mode, credp, rval);
12013 12169 if (status != 0) {
12014 12170 goto out;
12015 12171 }
12016 12172 /*
12017 12173 * The following code control the OK2RM LED, it doesn't affect
12018 12174 * the ioctl return status.
12019 12175 */
12020 12176 if ((cmd == DEVCTL_DEVICE_ONLINE) ||
12021 12177 (cmd == DEVCTL_DEVICE_OFFLINE)) {
12022 12178 if (ndi_dc_allochdl((void *)data, &dcp) !=
12023 12179 NDI_SUCCESS) {
12024 12180 goto out;
12025 12181 }
12026 12182 addr = ndi_dc_getaddr(dcp);
12027 12183 ptgt = mptsas_addr_to_ptgt(mpt, addr, phymask);
12028 12184 if (ptgt == NULL) {
12029 12185 NDBG14(("mptsas_ioctl led control: tgt %s not "
↓ open down ↓ |
66 lines elided |
↑ open up ↑ |
12030 12186 "found", addr));
12031 12187 ndi_dc_freehdl(dcp);
12032 12188 goto out;
12033 12189 }
12034 12190 mutex_enter(&mpt->m_mutex);
12035 12191 if (cmd == DEVCTL_DEVICE_ONLINE) {
12036 12192 ptgt->m_tgt_unconfigured = 0;
12037 12193 } else if (cmd == DEVCTL_DEVICE_OFFLINE) {
12038 12194 ptgt->m_tgt_unconfigured = 1;
12039 12195 }
12040 - slotstatus = 0;
12041 -#ifdef MPTSAS_GET_LED
12042 - /*
12043 - * The get led status can't get a valid/reasonable
12044 - * state, so ignore the get led status, and write the
12045 - * required value directly
12046 - */
12047 - if (mptsas_get_led_status(mpt, ptgt, &slotstatus) !=
12048 - DDI_SUCCESS) {
12049 - NDBG14(("mptsas_ioctl: get LED for tgt %s "
12050 - "failed %x", addr, slotstatus));
12051 - slotstatus = 0;
12052 - }
12053 - NDBG14(("mptsas_ioctl: LED status %x for %s",
12054 - slotstatus, addr));
12055 -#endif
12056 12196 if (cmd == DEVCTL_DEVICE_OFFLINE) {
12057 - slotstatus |=
12058 - MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE;
12197 + ptgt->m_led_status |=
12198 + (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1));
12059 12199 } else {
12060 - slotstatus &=
12061 - ~MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE;
12200 + ptgt->m_led_status &=
12201 + ~(1 << (MPTSAS_LEDCTL_LED_OK2RM - 1));
12062 12202 }
12063 - if (mptsas_set_led_status(mpt, ptgt, slotstatus) !=
12064 - DDI_SUCCESS) {
12203 + if (mptsas_flush_led_status(mpt, ptgt) != DDI_SUCCESS) {
12065 12204 NDBG14(("mptsas_ioctl: set LED for tgt %s "
12066 12205 "failed %x", addr, slotstatus));
12067 12206 }
12068 12207 mutex_exit(&mpt->m_mutex);
12069 12208 ndi_dc_freehdl(dcp);
12070 12209 }
12071 12210 goto out;
12072 12211 }
12073 12212 switch (cmd) {
12213 + case MPTIOCTL_GET_DISK_INFO:
12214 + status = get_disk_info(mpt, data, mode);
12215 + break;
12216 + case MPTIOCTL_LED_CONTROL:
12217 + status = led_control(mpt, data, mode);
12218 + break;
12074 12219 case MPTIOCTL_UPDATE_FLASH:
12075 12220 if (ddi_copyin((void *)data, &flashdata,
12076 12221 sizeof (struct mptsas_update_flash), mode)) {
12077 12222 status = EFAULT;
12078 12223 break;
12079 12224 }
12080 12225
12081 12226 mutex_enter(&mpt->m_mutex);
12082 12227 if (mptsas_update_flash(mpt,
12083 12228 (caddr_t)(long)flashdata.PtrBuffer,
12084 12229 flashdata.ImageSize, flashdata.ImageType, mode)) {
12085 12230 status = EFAULT;
12086 12231 }
12087 12232
12088 12233 /*
12089 12234 * Reset the chip to start using the new
12090 12235 * firmware. Reset if failed also.
12091 12236 */
12092 12237 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
12093 12238 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) {
12094 12239 status = EFAULT;
12095 12240 }
12096 12241 mutex_exit(&mpt->m_mutex);
12097 12242 break;
12098 12243 case MPTIOCTL_PASS_THRU:
12099 12244 /*
12100 12245 * The user has requested to pass through a command to
12101 12246 * be executed by the MPT firmware. Call our routine
12102 12247 * which does this. Only allow one passthru IOCTL at
12103 12248 * one time. Other threads will block on
12104 12249 * m_passthru_mutex, which is of adaptive variant.
12105 12250 */
12106 12251 if (ddi_copyin((void *)data, &passthru_data,
12107 12252 sizeof (mptsas_pass_thru_t), mode)) {
12108 12253 status = EFAULT;
12109 12254 break;
12110 12255 }
12111 12256 mutex_enter(&mpt->m_passthru_mutex);
12112 12257 mutex_enter(&mpt->m_mutex);
12113 12258 status = mptsas_pass_thru(mpt, &passthru_data, mode);
12114 12259 mutex_exit(&mpt->m_mutex);
12115 12260 mutex_exit(&mpt->m_passthru_mutex);
12116 12261
12117 12262 break;
12118 12263 case MPTIOCTL_GET_ADAPTER_DATA:
12119 12264 /*
12120 12265 * The user has requested to read adapter data. Call
12121 12266 * our routine which does this.
12122 12267 */
12123 12268 bzero(&adapter_data, sizeof (mptsas_adapter_data_t));
12124 12269 if (ddi_copyin((void *)data, (void *)&adapter_data,
12125 12270 sizeof (mptsas_adapter_data_t), mode)) {
12126 12271 status = EFAULT;
12127 12272 break;
12128 12273 }
12129 12274 if (adapter_data.StructureLength >=
12130 12275 sizeof (mptsas_adapter_data_t)) {
12131 12276 adapter_data.StructureLength = (uint32_t)
12132 12277 sizeof (mptsas_adapter_data_t);
12133 12278 copylen = sizeof (mptsas_adapter_data_t);
12134 12279 mutex_enter(&mpt->m_mutex);
12135 12280 mptsas_read_adapter_data(mpt, &adapter_data);
12136 12281 mutex_exit(&mpt->m_mutex);
12137 12282 } else {
12138 12283 adapter_data.StructureLength = (uint32_t)
12139 12284 sizeof (mptsas_adapter_data_t);
12140 12285 copylen = sizeof (adapter_data.StructureLength);
12141 12286 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT;
12142 12287 }
12143 12288 if (ddi_copyout((void *)(&adapter_data), (void *)data,
12144 12289 copylen, mode) != 0) {
12145 12290 status = EFAULT;
12146 12291 }
12147 12292 break;
12148 12293 case MPTIOCTL_GET_PCI_INFO:
12149 12294 /*
12150 12295 * The user has requested to read pci info. Call
12151 12296 * our routine which does this.
12152 12297 */
12153 12298 bzero(&pci_info, sizeof (mptsas_pci_info_t));
12154 12299 mutex_enter(&mpt->m_mutex);
12155 12300 mptsas_read_pci_info(mpt, &pci_info);
12156 12301 mutex_exit(&mpt->m_mutex);
12157 12302 if (ddi_copyout((void *)(&pci_info), (void *)data,
12158 12303 sizeof (mptsas_pci_info_t), mode) != 0) {
12159 12304 status = EFAULT;
12160 12305 }
12161 12306 break;
12162 12307 case MPTIOCTL_RESET_ADAPTER:
12163 12308 mutex_enter(&mpt->m_mutex);
12164 12309 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
12165 12310 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
12166 12311 mptsas_log(mpt, CE_WARN, "reset adapter IOCTL "
12167 12312 "failed");
12168 12313 status = EFAULT;
12169 12314 }
12170 12315 mutex_exit(&mpt->m_mutex);
12171 12316 break;
12172 12317 case MPTIOCTL_DIAG_ACTION:
12173 12318 /*
12174 12319 * The user has done a diag buffer action. Call our
12175 12320 * routine which does this. Only allow one diag action
12176 12321 * at one time.
12177 12322 */
12178 12323 mutex_enter(&mpt->m_mutex);
12179 12324 if (mpt->m_diag_action_in_progress) {
12180 12325 mutex_exit(&mpt->m_mutex);
12181 12326 return (EBUSY);
12182 12327 }
12183 12328 mpt->m_diag_action_in_progress = 1;
12184 12329 status = mptsas_diag_action(mpt,
12185 12330 (mptsas_diag_action_t *)data, mode);
12186 12331 mpt->m_diag_action_in_progress = 0;
12187 12332 mutex_exit(&mpt->m_mutex);
12188 12333 break;
12189 12334 case MPTIOCTL_EVENT_QUERY:
12190 12335 /*
12191 12336 * The user has done an event query. Call our routine
12192 12337 * which does this.
12193 12338 */
12194 12339 status = mptsas_event_query(mpt,
12195 12340 (mptsas_event_query_t *)data, mode, rval);
12196 12341 break;
12197 12342 case MPTIOCTL_EVENT_ENABLE:
12198 12343 /*
12199 12344 * The user has done an event enable. Call our routine
12200 12345 * which does this.
12201 12346 */
12202 12347 status = mptsas_event_enable(mpt,
12203 12348 (mptsas_event_enable_t *)data, mode, rval);
12204 12349 break;
12205 12350 case MPTIOCTL_EVENT_REPORT:
12206 12351 /*
12207 12352 * The user has done an event report. Call our routine
12208 12353 * which does this.
12209 12354 */
12210 12355 status = mptsas_event_report(mpt,
12211 12356 (mptsas_event_report_t *)data, mode, rval);
12212 12357 break;
12213 12358 case MPTIOCTL_REG_ACCESS:
12214 12359 /*
12215 12360 * The user has requested register access. Call our
12216 12361 * routine which does this.
12217 12362 */
12218 12363 status = mptsas_reg_access(mpt,
12219 12364 (mptsas_reg_access_t *)data, mode);
12220 12365 break;
12221 12366 default:
12222 12367 status = scsi_hba_ioctl(dev, cmd, data, mode, credp,
12223 12368 rval);
12224 12369 break;
12225 12370 }
12226 12371
12227 12372 out:
12228 12373 if (mpt->m_options & MPTSAS_OPT_PM)
12229 12374 (void) pm_idle_component(mpt->m_dip, 0);
12230 12375 return (status);
12231 12376 }
12232 12377
12233 12378 int
12234 12379 mptsas_restart_ioc(mptsas_t *mpt)
12235 12380 {
12236 12381 int rval = DDI_SUCCESS;
12237 12382 mptsas_target_t *ptgt = NULL;
12238 12383
12239 12384 ASSERT(mutex_owned(&mpt->m_mutex));
12240 12385
12241 12386 /*
12242 12387 * Set a flag telling I/O path that we're processing a reset. This is
12243 12388 * needed because after the reset is complete, the hash table still
12244 12389 * needs to be rebuilt. If I/Os are started before the hash table is
12245 12390 * rebuilt, I/O errors will occur. This flag allows I/Os to be marked
12246 12391 * so that they can be retried.
12247 12392 */
12248 12393 mpt->m_in_reset = TRUE;
12249 12394
12250 12395 /*
12251 12396 * Set all throttles to HOLD
12252 12397 */
12253 12398 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
12254 12399 MPTSAS_HASH_FIRST);
12255 12400 while (ptgt != NULL) {
12256 12401 mutex_enter(&ptgt->m_tgt_intr_mutex);
12257 12402 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
12258 12403 mutex_exit(&ptgt->m_tgt_intr_mutex);
12259 12404
12260 12405 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
12261 12406 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
12262 12407 }
12263 12408
12264 12409 /*
12265 12410 * Disable interrupts
12266 12411 */
12267 12412 MPTSAS_DISABLE_INTR(mpt);
12268 12413
12269 12414 /*
12270 12415 * Abort all commands: outstanding commands, commands in waitq
12271 12416 */
12272 12417 mptsas_flush_hba(mpt);
12273 12418
12274 12419 /*
12275 12420 * Reinitialize the chip.
12276 12421 */
12277 12422 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) {
12278 12423 rval = DDI_FAILURE;
12279 12424 }
12280 12425
12281 12426 /*
12282 12427 * Enable interrupts again
12283 12428 */
12284 12429 MPTSAS_ENABLE_INTR(mpt);
12285 12430
12286 12431 /*
12287 12432 * If mptsas_init_chip was successful, update the driver data.
12288 12433 */
12289 12434 if (rval == DDI_SUCCESS) {
12290 12435 mptsas_update_driver_data(mpt);
12291 12436 }
12292 12437
12293 12438 /*
12294 12439 * Reset the throttles
12295 12440 */
12296 12441 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
12297 12442 MPTSAS_HASH_FIRST);
12298 12443 while (ptgt != NULL) {
12299 12444 mutex_enter(&ptgt->m_tgt_intr_mutex);
12300 12445 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
12301 12446 mutex_exit(&ptgt->m_tgt_intr_mutex);
12302 12447
12303 12448 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
12304 12449 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
12305 12450 }
12306 12451
12307 12452 mptsas_doneq_empty(mpt);
12308 12453 mptsas_restart_hba(mpt);
12309 12454
12310 12455 if (rval != DDI_SUCCESS) {
12311 12456 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE);
12312 12457 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST);
12313 12458 }
12314 12459
12315 12460 /*
12316 12461 * Clear the reset flag so that I/Os can continue.
12317 12462 */
12318 12463 mpt->m_in_reset = FALSE;
12319 12464
12320 12465 return (rval);
12321 12466 }
12322 12467
12323 12468 static int
12324 12469 mptsas_init_chip(mptsas_t *mpt, int first_time)
12325 12470 {
12326 12471 ddi_dma_cookie_t cookie;
12327 12472 uint32_t i;
12328 12473 int rval;
12329 12474
12330 12475 /*
12331 12476 * Check to see if the firmware image is valid
12332 12477 */
12333 12478 if (ddi_get32(mpt->m_datap, &mpt->m_reg->HostDiagnostic) &
12334 12479 MPI2_DIAG_FLASH_BAD_SIG) {
12335 12480 mptsas_log(mpt, CE_WARN, "mptsas bad flash signature!");
12336 12481 goto fail;
12337 12482 }
12338 12483
12339 12484 /*
12340 12485 * Reset the chip
12341 12486 */
12342 12487 rval = mptsas_ioc_reset(mpt, first_time);
12343 12488 if (rval == MPTSAS_RESET_FAIL) {
12344 12489 mptsas_log(mpt, CE_WARN, "hard reset failed!");
12345 12490 goto fail;
12346 12491 }
12347 12492
12348 12493 if ((rval == MPTSAS_SUCCESS_MUR) && (!first_time)) {
12349 12494 goto mur;
12350 12495 }
12351 12496 /*
12352 12497 * Setup configuration space
12353 12498 */
12354 12499 if (mptsas_config_space_init(mpt) == FALSE) {
12355 12500 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init "
12356 12501 "failed!");
12357 12502 goto fail;
12358 12503 }
12359 12504
12360 12505 /*
12361 12506 * IOC facts can change after a diag reset so all buffers that are
12362 12507 * based on these numbers must be de-allocated and re-allocated. Get
12363 12508 * new IOC facts each time chip is initialized.
12364 12509 */
12365 12510 if (mptsas_ioc_get_facts(mpt) == DDI_FAILURE) {
12366 12511 mptsas_log(mpt, CE_WARN, "mptsas_ioc_get_facts failed");
12367 12512 goto fail;
12368 12513 }
12369 12514
12370 12515 if (mptsas_alloc_active_slots(mpt, KM_SLEEP)) {
12371 12516 goto fail;
12372 12517 }
12373 12518 /*
12374 12519 * Allocate request message frames, reply free queue, reply descriptor
12375 12520 * post queue, and reply message frames using latest IOC facts.
12376 12521 */
12377 12522 if (mptsas_alloc_request_frames(mpt) == DDI_FAILURE) {
12378 12523 mptsas_log(mpt, CE_WARN, "mptsas_alloc_request_frames failed");
12379 12524 goto fail;
12380 12525 }
12381 12526 if (mptsas_alloc_free_queue(mpt) == DDI_FAILURE) {
12382 12527 mptsas_log(mpt, CE_WARN, "mptsas_alloc_free_queue failed!");
12383 12528 goto fail;
12384 12529 }
12385 12530 if (mptsas_alloc_post_queue(mpt) == DDI_FAILURE) {
12386 12531 mptsas_log(mpt, CE_WARN, "mptsas_alloc_post_queue failed!");
12387 12532 goto fail;
12388 12533 }
12389 12534 if (mptsas_alloc_reply_frames(mpt) == DDI_FAILURE) {
12390 12535 mptsas_log(mpt, CE_WARN, "mptsas_alloc_reply_frames failed!");
12391 12536 goto fail;
12392 12537 }
12393 12538
12394 12539 mur:
12395 12540 /*
12396 12541 * Re-Initialize ioc to operational state
12397 12542 */
12398 12543 if (mptsas_ioc_init(mpt) == DDI_FAILURE) {
12399 12544 mptsas_log(mpt, CE_WARN, "mptsas_ioc_init failed");
12400 12545 goto fail;
12401 12546 }
12402 12547
12403 12548 mptsas_alloc_reply_args(mpt);
12404 12549
12405 12550 /*
12406 12551 * Initialize reply post index. Reply free index is initialized after
12407 12552 * the next loop.
12408 12553 */
12409 12554 mpt->m_post_index = 0;
12410 12555
12411 12556 /*
12412 12557 * Initialize the Reply Free Queue with the physical addresses of our
12413 12558 * reply frames.
12414 12559 */
12415 12560 cookie.dmac_address = mpt->m_reply_frame_dma_addr;
12416 12561 for (i = 0; i < mpt->m_max_replies; i++) {
12417 12562 ddi_put32(mpt->m_acc_free_queue_hdl,
12418 12563 &((uint32_t *)(void *)mpt->m_free_queue)[i],
12419 12564 cookie.dmac_address);
12420 12565 cookie.dmac_address += mpt->m_reply_frame_size;
12421 12566 }
12422 12567 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
12423 12568 DDI_DMA_SYNC_FORDEV);
12424 12569
12425 12570 /*
12426 12571 * Initialize the reply free index to one past the last frame on the
12427 12572 * queue. This will signify that the queue is empty to start with.
12428 12573 */
12429 12574 mpt->m_free_index = i;
12430 12575 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, i);
12431 12576
12432 12577 /*
12433 12578 * Initialize the reply post queue to 0xFFFFFFFF,0xFFFFFFFF's.
12434 12579 */
12435 12580 for (i = 0; i < mpt->m_post_queue_depth; i++) {
12436 12581 ddi_put64(mpt->m_acc_post_queue_hdl,
12437 12582 &((uint64_t *)(void *)mpt->m_post_queue)[i],
12438 12583 0xFFFFFFFFFFFFFFFF);
12439 12584 }
12440 12585 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
12441 12586 DDI_DMA_SYNC_FORDEV);
12442 12587
12443 12588 /*
12444 12589 * Enable ports
12445 12590 */
12446 12591 if (mptsas_ioc_enable_port(mpt) == DDI_FAILURE) {
12447 12592 mptsas_log(mpt, CE_WARN, "mptsas_ioc_enable_port failed");
12448 12593 goto fail;
12449 12594 }
12450 12595
12451 12596 /*
12452 12597 * enable events
12453 12598 */
12454 12599 if (mptsas_ioc_enable_event_notification(mpt)) {
12455 12600 goto fail;
12456 12601 }
12457 12602
12458 12603 /*
12459 12604 * We need checks in attach and these.
12460 12605 * chip_init is called in mult. places
12461 12606 */
12462 12607
12463 12608 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
12464 12609 DDI_SUCCESS) ||
12465 12610 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) !=
12466 12611 DDI_SUCCESS) ||
12467 12612 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) !=
12468 12613 DDI_SUCCESS) ||
12469 12614 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) !=
12470 12615 DDI_SUCCESS) ||
12471 12616 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) !=
12472 12617 DDI_SUCCESS)) {
12473 12618 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
12474 12619 goto fail;
12475 12620 }
12476 12621
12477 12622 /* Check all acc handles */
12478 12623 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) ||
12479 12624 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
12480 12625 DDI_SUCCESS) ||
12481 12626 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) !=
12482 12627 DDI_SUCCESS) ||
12483 12628 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) !=
12484 12629 DDI_SUCCESS) ||
12485 12630 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) !=
12486 12631 DDI_SUCCESS) ||
12487 12632 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) !=
12488 12633 DDI_SUCCESS) ||
12489 12634 (mptsas_check_acc_handle(mpt->m_config_handle) !=
12490 12635 DDI_SUCCESS)) {
12491 12636 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
12492 12637 goto fail;
12493 12638 }
12494 12639
12495 12640 return (DDI_SUCCESS);
12496 12641
12497 12642 fail:
12498 12643 return (DDI_FAILURE);
12499 12644 }
12500 12645
12501 12646 static int
12502 12647 mptsas_get_pci_cap(mptsas_t *mpt)
12503 12648 {
12504 12649 ushort_t caps_ptr, cap, cap_count;
12505 12650
12506 12651 if (mpt->m_config_handle == NULL)
12507 12652 return (FALSE);
12508 12653 /*
12509 12654 * Check if capabilities list is supported and if so,
12510 12655 * get initial capabilities pointer and clear bits 0,1.
12511 12656 */
12512 12657 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT)
12513 12658 & PCI_STAT_CAP) {
12514 12659 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle,
12515 12660 PCI_CONF_CAP_PTR), 4);
12516 12661 } else {
12517 12662 caps_ptr = PCI_CAP_NEXT_PTR_NULL;
12518 12663 }
12519 12664
12520 12665 /*
12521 12666 * Walk capabilities if supported.
12522 12667 */
12523 12668 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) {
12524 12669
12525 12670 /*
12526 12671 * Check that we haven't exceeded the maximum number of
12527 12672 * capabilities and that the pointer is in a valid range.
12528 12673 */
12529 12674 if (++cap_count > 48) {
12530 12675 mptsas_log(mpt, CE_WARN,
12531 12676 "too many device capabilities.\n");
12532 12677 break;
12533 12678 }
12534 12679 if (caps_ptr < 64) {
12535 12680 mptsas_log(mpt, CE_WARN,
12536 12681 "capabilities pointer 0x%x out of range.\n",
12537 12682 caps_ptr);
12538 12683 break;
12539 12684 }
12540 12685
12541 12686 /*
12542 12687 * Get next capability and check that it is valid.
12543 12688 * For now, we only support power management.
12544 12689 */
12545 12690 cap = pci_config_get8(mpt->m_config_handle, caps_ptr);
12546 12691 switch (cap) {
12547 12692 case PCI_CAP_ID_PM:
12548 12693 mptsas_log(mpt, CE_NOTE,
12549 12694 "?mptsas%d supports power management.\n",
12550 12695 mpt->m_instance);
12551 12696 mpt->m_options |= MPTSAS_OPT_PM;
12552 12697
12553 12698 /* Save PMCSR offset */
12554 12699 mpt->m_pmcsr_offset = caps_ptr + PCI_PMCSR;
12555 12700 break;
12556 12701 /*
12557 12702 * The following capabilities are valid. Any others
12558 12703 * will cause a message to be logged.
12559 12704 */
12560 12705 case PCI_CAP_ID_VPD:
12561 12706 case PCI_CAP_ID_MSI:
12562 12707 case PCI_CAP_ID_PCIX:
12563 12708 case PCI_CAP_ID_PCI_E:
12564 12709 case PCI_CAP_ID_MSI_X:
12565 12710 break;
12566 12711 default:
12567 12712 mptsas_log(mpt, CE_NOTE,
12568 12713 "?mptsas%d unrecognized capability "
12569 12714 "0x%x.\n", mpt->m_instance, cap);
12570 12715 break;
12571 12716 }
12572 12717
12573 12718 /*
12574 12719 * Get next capabilities pointer and clear bits 0,1.
12575 12720 */
12576 12721 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle,
12577 12722 (caps_ptr + PCI_CAP_NEXT_PTR)), 4);
12578 12723 }
12579 12724 return (TRUE);
12580 12725 }
12581 12726
12582 12727 static int
12583 12728 mptsas_init_pm(mptsas_t *mpt)
12584 12729 {
12585 12730 char pmc_name[16];
12586 12731 char *pmc[] = {
12587 12732 NULL,
12588 12733 "0=Off (PCI D3 State)",
12589 12734 "3=On (PCI D0 State)",
12590 12735 NULL
12591 12736 };
12592 12737 uint16_t pmcsr_stat;
12593 12738
12594 12739 if (mptsas_get_pci_cap(mpt) == FALSE) {
12595 12740 return (DDI_FAILURE);
12596 12741 }
12597 12742 /*
12598 12743 * If PCI's capability does not support PM, then don't need
12599 12744 * to registe the pm-components
12600 12745 */
12601 12746 if (!(mpt->m_options & MPTSAS_OPT_PM))
12602 12747 return (DDI_SUCCESS);
12603 12748 /*
12604 12749 * If power management is supported by this chip, create
12605 12750 * pm-components property for the power management framework
12606 12751 */
12607 12752 (void) sprintf(pmc_name, "NAME=mptsas%d", mpt->m_instance);
12608 12753 pmc[0] = pmc_name;
12609 12754 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, mpt->m_dip,
12610 12755 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) {
12611 12756 mutex_enter(&mpt->m_intr_mutex);
12612 12757 mpt->m_options &= ~MPTSAS_OPT_PM;
12613 12758 mutex_exit(&mpt->m_intr_mutex);
12614 12759 mptsas_log(mpt, CE_WARN,
12615 12760 "mptsas%d: pm-component property creation failed.",
12616 12761 mpt->m_instance);
12617 12762 return (DDI_FAILURE);
12618 12763 }
12619 12764
12620 12765 /*
12621 12766 * Power on device.
12622 12767 */
12623 12768 (void) pm_busy_component(mpt->m_dip, 0);
12624 12769 pmcsr_stat = pci_config_get16(mpt->m_config_handle,
12625 12770 mpt->m_pmcsr_offset);
12626 12771 if ((pmcsr_stat & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_D0) {
12627 12772 mptsas_log(mpt, CE_WARN, "mptsas%d: Power up the device",
12628 12773 mpt->m_instance);
12629 12774 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset,
12630 12775 PCI_PMCSR_D0);
12631 12776 }
12632 12777 if (pm_power_has_changed(mpt->m_dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) {
12633 12778 mptsas_log(mpt, CE_WARN, "pm_power_has_changed failed");
12634 12779 return (DDI_FAILURE);
12635 12780 }
12636 12781 mutex_enter(&mpt->m_intr_mutex);
12637 12782 mpt->m_power_level = PM_LEVEL_D0;
12638 12783 mutex_exit(&mpt->m_intr_mutex);
12639 12784 /*
12640 12785 * Set pm idle delay.
12641 12786 */
12642 12787 mpt->m_pm_idle_delay = ddi_prop_get_int(DDI_DEV_T_ANY,
12643 12788 mpt->m_dip, 0, "mptsas-pm-idle-delay", MPTSAS_PM_IDLE_TIMEOUT);
12644 12789
12645 12790 return (DDI_SUCCESS);
12646 12791 }
12647 12792
12648 12793 static int
12649 12794 mptsas_register_intrs(mptsas_t *mpt)
12650 12795 {
12651 12796 dev_info_t *dip;
12652 12797 int intr_types;
12653 12798
12654 12799 dip = mpt->m_dip;
12655 12800
12656 12801 /* Get supported interrupt types */
12657 12802 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) {
12658 12803 mptsas_log(mpt, CE_WARN, "ddi_intr_get_supported_types "
12659 12804 "failed\n");
12660 12805 return (FALSE);
12661 12806 }
12662 12807
12663 12808 NDBG6(("ddi_intr_get_supported_types() returned: 0x%x", intr_types));
12664 12809
12665 12810 /*
12666 12811 * Try MSI, but fall back to FIXED
12667 12812 */
12668 12813 if (mptsas_enable_msi && (intr_types & DDI_INTR_TYPE_MSI)) {
12669 12814 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_MSI) == DDI_SUCCESS) {
12670 12815 NDBG0(("Using MSI interrupt type"));
12671 12816 mpt->m_intr_type = DDI_INTR_TYPE_MSI;
12672 12817 return (TRUE);
12673 12818 }
12674 12819 }
12675 12820 if (intr_types & DDI_INTR_TYPE_FIXED) {
12676 12821 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_FIXED) == DDI_SUCCESS) {
12677 12822 NDBG0(("Using FIXED interrupt type"));
12678 12823 mpt->m_intr_type = DDI_INTR_TYPE_FIXED;
12679 12824 return (TRUE);
12680 12825 } else {
12681 12826 NDBG0(("FIXED interrupt registration failed"));
12682 12827 return (FALSE);
12683 12828 }
12684 12829 }
12685 12830
12686 12831 return (FALSE);
12687 12832 }
12688 12833
12689 12834 static void
12690 12835 mptsas_unregister_intrs(mptsas_t *mpt)
12691 12836 {
12692 12837 mptsas_rem_intrs(mpt);
12693 12838 }
12694 12839
12695 12840 /*
12696 12841 * mptsas_add_intrs:
12697 12842 *
12698 12843 * Register FIXED or MSI interrupts.
12699 12844 */
12700 12845 static int
12701 12846 mptsas_add_intrs(mptsas_t *mpt, int intr_type)
12702 12847 {
12703 12848 dev_info_t *dip = mpt->m_dip;
12704 12849 int avail, actual, count = 0;
12705 12850 int i, flag, ret;
12706 12851
12707 12852 NDBG6(("mptsas_add_intrs:interrupt type 0x%x", intr_type));
12708 12853
12709 12854 /* Get number of interrupts */
12710 12855 ret = ddi_intr_get_nintrs(dip, intr_type, &count);
12711 12856 if ((ret != DDI_SUCCESS) || (count <= 0)) {
12712 12857 mptsas_log(mpt, CE_WARN, "ddi_intr_get_nintrs() failed, "
12713 12858 "ret %d count %d\n", ret, count);
12714 12859
12715 12860 return (DDI_FAILURE);
12716 12861 }
12717 12862
12718 12863 /* Get number of available interrupts */
12719 12864 ret = ddi_intr_get_navail(dip, intr_type, &avail);
12720 12865 if ((ret != DDI_SUCCESS) || (avail == 0)) {
12721 12866 mptsas_log(mpt, CE_WARN, "ddi_intr_get_navail() failed, "
12722 12867 "ret %d avail %d\n", ret, avail);
12723 12868
12724 12869 return (DDI_FAILURE);
12725 12870 }
12726 12871
12727 12872 if (avail < count) {
12728 12873 mptsas_log(mpt, CE_NOTE, "ddi_intr_get_nvail returned %d, "
12729 12874 "navail() returned %d", count, avail);
12730 12875 }
12731 12876
12732 12877 /* Mpt only have one interrupt routine */
12733 12878 if ((intr_type == DDI_INTR_TYPE_MSI) && (count > 1)) {
12734 12879 count = 1;
12735 12880 }
12736 12881
12737 12882 /* Allocate an array of interrupt handles */
12738 12883 mpt->m_intr_size = count * sizeof (ddi_intr_handle_t);
12739 12884 mpt->m_htable = kmem_alloc(mpt->m_intr_size, KM_SLEEP);
12740 12885
12741 12886 flag = DDI_INTR_ALLOC_NORMAL;
12742 12887
12743 12888 /* call ddi_intr_alloc() */
12744 12889 ret = ddi_intr_alloc(dip, mpt->m_htable, intr_type, 0,
12745 12890 count, &actual, flag);
12746 12891
12747 12892 if ((ret != DDI_SUCCESS) || (actual == 0)) {
12748 12893 mptsas_log(mpt, CE_WARN, "ddi_intr_alloc() failed, ret %d\n",
12749 12894 ret);
12750 12895 kmem_free(mpt->m_htable, mpt->m_intr_size);
12751 12896 return (DDI_FAILURE);
12752 12897 }
12753 12898
12754 12899 /* use interrupt count returned or abort? */
12755 12900 if (actual < count) {
12756 12901 mptsas_log(mpt, CE_NOTE, "Requested: %d, Received: %d\n",
12757 12902 count, actual);
12758 12903 }
12759 12904
12760 12905 mpt->m_intr_cnt = actual;
12761 12906
12762 12907 /*
12763 12908 * Get priority for first msi, assume remaining are all the same
12764 12909 */
12765 12910 if ((ret = ddi_intr_get_pri(mpt->m_htable[0],
12766 12911 &mpt->m_intr_pri)) != DDI_SUCCESS) {
12767 12912 mptsas_log(mpt, CE_WARN, "ddi_intr_get_pri() failed %d\n", ret);
12768 12913
12769 12914 /* Free already allocated intr */
12770 12915 for (i = 0; i < actual; i++) {
12771 12916 (void) ddi_intr_free(mpt->m_htable[i]);
12772 12917 }
12773 12918
12774 12919 kmem_free(mpt->m_htable, mpt->m_intr_size);
12775 12920 return (DDI_FAILURE);
12776 12921 }
12777 12922
12778 12923 /* Test for high level mutex */
12779 12924 if (mpt->m_intr_pri >= ddi_intr_get_hilevel_pri()) {
12780 12925 mptsas_log(mpt, CE_WARN, "mptsas_add_intrs: "
12781 12926 "Hi level interrupt not supported\n");
12782 12927
12783 12928 /* Free already allocated intr */
12784 12929 for (i = 0; i < actual; i++) {
12785 12930 (void) ddi_intr_free(mpt->m_htable[i]);
12786 12931 }
12787 12932
12788 12933 kmem_free(mpt->m_htable, mpt->m_intr_size);
12789 12934 return (DDI_FAILURE);
12790 12935 }
12791 12936
12792 12937 /* Call ddi_intr_add_handler() */
12793 12938 for (i = 0; i < actual; i++) {
12794 12939 if ((ret = ddi_intr_add_handler(mpt->m_htable[i], mptsas_intr,
12795 12940 (caddr_t)mpt, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) {
12796 12941 mptsas_log(mpt, CE_WARN, "ddi_intr_add_handler() "
12797 12942 "failed %d\n", ret);
12798 12943
12799 12944 /* Free already allocated intr */
12800 12945 for (i = 0; i < actual; i++) {
12801 12946 (void) ddi_intr_free(mpt->m_htable[i]);
12802 12947 }
12803 12948
12804 12949 kmem_free(mpt->m_htable, mpt->m_intr_size);
12805 12950 return (DDI_FAILURE);
12806 12951 }
12807 12952 }
12808 12953
12809 12954 if ((ret = ddi_intr_get_cap(mpt->m_htable[0], &mpt->m_intr_cap))
12810 12955 != DDI_SUCCESS) {
12811 12956 mptsas_log(mpt, CE_WARN, "ddi_intr_get_cap() failed %d\n", ret);
12812 12957
12813 12958 /* Free already allocated intr */
12814 12959 for (i = 0; i < actual; i++) {
12815 12960 (void) ddi_intr_free(mpt->m_htable[i]);
12816 12961 }
12817 12962
12818 12963 kmem_free(mpt->m_htable, mpt->m_intr_size);
12819 12964 return (DDI_FAILURE);
12820 12965 }
12821 12966
12822 12967 /*
12823 12968 * Enable interrupts
12824 12969 */
12825 12970 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) {
12826 12971 /* Call ddi_intr_block_enable() for MSI interrupts */
12827 12972 (void) ddi_intr_block_enable(mpt->m_htable, mpt->m_intr_cnt);
12828 12973 } else {
12829 12974 /* Call ddi_intr_enable for MSI or FIXED interrupts */
12830 12975 for (i = 0; i < mpt->m_intr_cnt; i++) {
12831 12976 (void) ddi_intr_enable(mpt->m_htable[i]);
12832 12977 }
12833 12978 }
12834 12979 return (DDI_SUCCESS);
12835 12980 }
12836 12981
12837 12982 /*
12838 12983 * mptsas_rem_intrs:
12839 12984 *
12840 12985 * Unregister FIXED or MSI interrupts
12841 12986 */
12842 12987 static void
12843 12988 mptsas_rem_intrs(mptsas_t *mpt)
12844 12989 {
12845 12990 int i;
12846 12991
12847 12992 NDBG6(("mptsas_rem_intrs"));
12848 12993
12849 12994 /* Disable all interrupts */
12850 12995 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) {
12851 12996 /* Call ddi_intr_block_disable() */
12852 12997 (void) ddi_intr_block_disable(mpt->m_htable, mpt->m_intr_cnt);
12853 12998 } else {
12854 12999 for (i = 0; i < mpt->m_intr_cnt; i++) {
12855 13000 (void) ddi_intr_disable(mpt->m_htable[i]);
12856 13001 }
12857 13002 }
12858 13003
12859 13004 /* Call ddi_intr_remove_handler() */
12860 13005 for (i = 0; i < mpt->m_intr_cnt; i++) {
12861 13006 (void) ddi_intr_remove_handler(mpt->m_htable[i]);
12862 13007 (void) ddi_intr_free(mpt->m_htable[i]);
12863 13008 }
12864 13009
12865 13010 kmem_free(mpt->m_htable, mpt->m_intr_size);
12866 13011 }
12867 13012
12868 13013 /*
12869 13014 * The IO fault service error handling callback function
12870 13015 */
12871 13016 /*ARGSUSED*/
12872 13017 static int
12873 13018 mptsas_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
12874 13019 {
12875 13020 /*
12876 13021 * as the driver can always deal with an error in any dma or
12877 13022 * access handle, we can just return the fme_status value.
12878 13023 */
12879 13024 pci_ereport_post(dip, err, NULL);
12880 13025 return (err->fme_status);
12881 13026 }
12882 13027
12883 13028 /*
12884 13029 * mptsas_fm_init - initialize fma capabilities and register with IO
12885 13030 * fault services.
12886 13031 */
12887 13032 static void
12888 13033 mptsas_fm_init(mptsas_t *mpt)
12889 13034 {
12890 13035 /*
12891 13036 * Need to change iblock to priority for new MSI intr
12892 13037 */
12893 13038 ddi_iblock_cookie_t fm_ibc;
12894 13039
12895 13040 /* Only register with IO Fault Services if we have some capability */
12896 13041 if (mpt->m_fm_capabilities) {
12897 13042 /* Adjust access and dma attributes for FMA */
12898 13043 mpt->m_reg_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC;
12899 13044 mpt->m_msg_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
12900 13045 mpt->m_io_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
12901 13046
12902 13047 /*
12903 13048 * Register capabilities with IO Fault Services.
12904 13049 * mpt->m_fm_capabilities will be updated to indicate
12905 13050 * capabilities actually supported (not requested.)
12906 13051 */
12907 13052 ddi_fm_init(mpt->m_dip, &mpt->m_fm_capabilities, &fm_ibc);
12908 13053
12909 13054 /*
12910 13055 * Initialize pci ereport capabilities if ereport
12911 13056 * capable (should always be.)
12912 13057 */
12913 13058 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) ||
12914 13059 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
12915 13060 pci_ereport_setup(mpt->m_dip);
12916 13061 }
12917 13062
12918 13063 /*
12919 13064 * Register error callback if error callback capable.
12920 13065 */
12921 13066 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
12922 13067 ddi_fm_handler_register(mpt->m_dip,
12923 13068 mptsas_fm_error_cb, (void *) mpt);
12924 13069 }
12925 13070 }
12926 13071 }
12927 13072
12928 13073 /*
12929 13074 * mptsas_fm_fini - Releases fma capabilities and un-registers with IO
12930 13075 * fault services.
12931 13076 *
12932 13077 */
12933 13078 static void
12934 13079 mptsas_fm_fini(mptsas_t *mpt)
12935 13080 {
12936 13081 /* Only unregister FMA capabilities if registered */
12937 13082 if (mpt->m_fm_capabilities) {
12938 13083
12939 13084 /*
12940 13085 * Un-register error callback if error callback capable.
12941 13086 */
12942 13087
12943 13088 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
12944 13089 ddi_fm_handler_unregister(mpt->m_dip);
12945 13090 }
12946 13091
12947 13092 /*
12948 13093 * Release any resources allocated by pci_ereport_setup()
12949 13094 */
12950 13095
12951 13096 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) ||
12952 13097 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
12953 13098 pci_ereport_teardown(mpt->m_dip);
12954 13099 }
12955 13100
12956 13101 /* Unregister from IO Fault Services */
12957 13102 ddi_fm_fini(mpt->m_dip);
12958 13103
12959 13104 /* Adjust access and dma attributes for FMA */
12960 13105 mpt->m_reg_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC;
12961 13106 mpt->m_msg_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
12962 13107 mpt->m_io_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
12963 13108
12964 13109 }
12965 13110 }
12966 13111
12967 13112 int
12968 13113 mptsas_check_acc_handle(ddi_acc_handle_t handle)
12969 13114 {
12970 13115 ddi_fm_error_t de;
12971 13116
12972 13117 if (handle == NULL)
12973 13118 return (DDI_FAILURE);
12974 13119 ddi_fm_acc_err_get(handle, &de, DDI_FME_VER0);
12975 13120 return (de.fme_status);
12976 13121 }
12977 13122
12978 13123 int
12979 13124 mptsas_check_dma_handle(ddi_dma_handle_t handle)
12980 13125 {
12981 13126 ddi_fm_error_t de;
12982 13127
12983 13128 if (handle == NULL)
12984 13129 return (DDI_FAILURE);
12985 13130 ddi_fm_dma_err_get(handle, &de, DDI_FME_VER0);
12986 13131 return (de.fme_status);
12987 13132 }
12988 13133
12989 13134 void
12990 13135 mptsas_fm_ereport(mptsas_t *mpt, char *detail)
12991 13136 {
12992 13137 uint64_t ena;
12993 13138 char buf[FM_MAX_CLASS];
12994 13139
12995 13140 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
12996 13141 ena = fm_ena_generate(0, FM_ENA_FMT1);
12997 13142 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities)) {
12998 13143 ddi_fm_ereport_post(mpt->m_dip, buf, ena, DDI_NOSLEEP,
12999 13144 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL);
13000 13145 }
13001 13146 }
13002 13147
13003 13148 static int
13004 13149 mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address,
13005 13150 uint16_t *dev_handle, mptsas_target_t **pptgt)
13006 13151 {
13007 13152 int rval;
13008 13153 uint32_t dev_info;
13009 13154 uint64_t sas_wwn;
13010 13155 mptsas_phymask_t phymask;
13011 13156 uint8_t physport, phynum, config, disk;
13012 13157 mptsas_slots_t *slots = mpt->m_active;
13013 13158 uint64_t devicename;
13014 13159 uint16_t pdev_hdl;
13015 13160 mptsas_target_t *tmp_tgt = NULL;
13016 13161 uint16_t bay_num, enclosure;
13017 13162
13018 13163 ASSERT(*pptgt == NULL);
13019 13164
13020 13165 rval = mptsas_get_sas_device_page0(mpt, page_address, dev_handle,
13021 13166 &sas_wwn, &dev_info, &physport, &phynum, &pdev_hdl,
13022 13167 &bay_num, &enclosure);
13023 13168 if (rval != DDI_SUCCESS) {
13024 13169 rval = DEV_INFO_FAIL_PAGE0;
13025 13170 return (rval);
13026 13171 }
13027 13172
13028 13173 if ((dev_info & (MPI2_SAS_DEVICE_INFO_SSP_TARGET |
13029 13174 MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
13030 13175 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) == NULL) {
13031 13176 rval = DEV_INFO_WRONG_DEVICE_TYPE;
13032 13177 return (rval);
13033 13178 }
13034 13179
13035 13180 /*
13036 13181 * Check if the dev handle is for a Phys Disk. If so, set return value
13037 13182 * and exit. Don't add Phys Disks to hash.
13038 13183 */
13039 13184 for (config = 0; config < slots->m_num_raid_configs; config++) {
13040 13185 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) {
13041 13186 if (*dev_handle == slots->m_raidconfig[config].
13042 13187 m_physdisk_devhdl[disk]) {
13043 13188 rval = DEV_INFO_PHYS_DISK;
13044 13189 return (rval);
13045 13190 }
13046 13191 }
13047 13192 }
13048 13193
13049 13194 /*
13050 13195 * Get SATA Device Name from SAS device page0 for
13051 13196 * sata device, if device name doesn't exist, set m_sas_wwn to
13052 13197 * 0 for direct attached SATA. For the device behind the expander
13053 13198 * we still can use STP address assigned by expander.
13054 13199 */
13055 13200 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
13056 13201 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
13057 13202 mutex_exit(&mpt->m_mutex);
13058 13203 /* alloc a tmp_tgt to send the cmd */
13059 13204 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target),
13060 13205 KM_SLEEP);
13061 13206 tmp_tgt->m_devhdl = *dev_handle;
13062 13207 tmp_tgt->m_deviceinfo = dev_info;
13063 13208 tmp_tgt->m_qfull_retries = QFULL_RETRIES;
13064 13209 tmp_tgt->m_qfull_retry_interval =
13065 13210 drv_usectohz(QFULL_RETRY_INTERVAL * 1000);
13066 13211 tmp_tgt->m_t_throttle = MAX_THROTTLE;
13067 13212 devicename = mptsas_get_sata_guid(mpt, tmp_tgt, 0);
13068 13213 kmem_free(tmp_tgt, sizeof (struct mptsas_target));
13069 13214 mutex_enter(&mpt->m_mutex);
13070 13215 if (devicename != 0 && (((devicename >> 56) & 0xf0) == 0x50)) {
13071 13216 sas_wwn = devicename;
13072 13217 } else if (dev_info & MPI2_SAS_DEVICE_INFO_DIRECT_ATTACH) {
13073 13218 sas_wwn = 0;
13074 13219 }
13075 13220 }
13076 13221
13077 13222 phymask = mptsas_physport_to_phymask(mpt, physport);
13078 13223 *pptgt = mptsas_tgt_alloc(&slots->m_tgttbl, *dev_handle, sas_wwn,
13079 13224 dev_info, phymask, phynum, mpt);
13080 13225 if (*pptgt == NULL) {
13081 13226 mptsas_log(mpt, CE_WARN, "Failed to allocated target"
13082 13227 "structure!");
13083 13228 rval = DEV_INFO_FAIL_ALLOC;
13084 13229 return (rval);
13085 13230 }
13086 13231 (*pptgt)->m_enclosure = enclosure;
13087 13232 (*pptgt)->m_slot_num = bay_num;
13088 13233 return (DEV_INFO_SUCCESS);
13089 13234 }
13090 13235
13091 13236 uint64_t
13092 13237 mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun)
13093 13238 {
13094 13239 uint64_t sata_guid = 0, *pwwn = NULL;
13095 13240 int target = ptgt->m_devhdl;
13096 13241 uchar_t *inq83 = NULL;
13097 13242 int inq83_len = 0xFF;
13098 13243 uchar_t *dblk = NULL;
13099 13244 int inq83_retry = 3;
13100 13245 int rval = DDI_FAILURE;
13101 13246
13102 13247 inq83 = kmem_zalloc(inq83_len, KM_SLEEP);
13103 13248
13104 13249 inq83_retry:
13105 13250 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83,
13106 13251 inq83_len, NULL, 1);
13107 13252 if (rval != DDI_SUCCESS) {
13108 13253 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
13109 13254 "0x83 for target:%x, lun:%x failed!", target, lun);
13110 13255 goto out;
13111 13256 }
13112 13257 /* According to SAT2, the first descriptor is logic unit name */
13113 13258 dblk = &inq83[4];
13114 13259 if ((dblk[1] & 0x30) != 0) {
13115 13260 mptsas_log(mpt, CE_WARN, "!Descriptor is not lun associated.");
13116 13261 goto out;
13117 13262 }
13118 13263 pwwn = (uint64_t *)(void *)(&dblk[4]);
13119 13264 if ((dblk[4] & 0xf0) == 0x50) {
13120 13265 sata_guid = BE_64(*pwwn);
13121 13266 goto out;
13122 13267 } else if (dblk[4] == 'A') {
13123 13268 NDBG20(("SATA drive has no NAA format GUID."));
13124 13269 goto out;
13125 13270 } else {
13126 13271 /* The data is not ready, wait and retry */
13127 13272 inq83_retry--;
13128 13273 if (inq83_retry <= 0) {
13129 13274 goto out;
13130 13275 }
13131 13276 NDBG20(("The GUID is not ready, retry..."));
13132 13277 delay(1 * drv_usectohz(1000000));
13133 13278 goto inq83_retry;
13134 13279 }
13135 13280 out:
13136 13281 kmem_free(inq83, inq83_len);
13137 13282 return (sata_guid);
13138 13283 }
13139 13284
13140 13285 static int
13141 13286 mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, uchar_t page,
13142 13287 unsigned char *buf, int len, int *reallen, uchar_t evpd)
13143 13288 {
13144 13289 uchar_t cdb[CDB_GROUP0];
13145 13290 struct scsi_address ap;
13146 13291 struct buf *data_bp = NULL;
13147 13292 int resid = 0;
13148 13293 int ret = DDI_FAILURE;
13149 13294
13150 13295 ASSERT(len <= 0xffff);
13151 13296
13152 13297 ap.a_target = MPTSAS_INVALID_DEVHDL;
13153 13298 ap.a_lun = (uchar_t)(lun);
13154 13299 ap.a_hba_tran = mpt->m_tran;
13155 13300
13156 13301 data_bp = scsi_alloc_consistent_buf(&ap,
13157 13302 (struct buf *)NULL, len, B_READ, NULL_FUNC, NULL);
13158 13303 if (data_bp == NULL) {
13159 13304 return (ret);
13160 13305 }
13161 13306 bzero(cdb, CDB_GROUP0);
13162 13307 cdb[0] = SCMD_INQUIRY;
13163 13308 cdb[1] = evpd;
13164 13309 cdb[2] = page;
13165 13310 cdb[3] = (len & 0xff00) >> 8;
13166 13311 cdb[4] = (len & 0x00ff);
13167 13312 cdb[5] = 0;
13168 13313
13169 13314 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP0, data_bp,
13170 13315 &resid);
13171 13316 if (ret == DDI_SUCCESS) {
13172 13317 if (reallen) {
13173 13318 *reallen = len - resid;
13174 13319 }
13175 13320 bcopy((caddr_t)data_bp->b_un.b_addr, buf, len);
13176 13321 }
13177 13322 if (data_bp) {
13178 13323 scsi_free_consistent_buf(data_bp);
13179 13324 }
13180 13325 return (ret);
13181 13326 }
13182 13327
13183 13328 static int
13184 13329 mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap,
13185 13330 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp,
13186 13331 int *resid)
13187 13332 {
13188 13333 struct scsi_pkt *pktp = NULL;
13189 13334 scsi_hba_tran_t *tran_clone = NULL;
13190 13335 mptsas_tgt_private_t *tgt_private = NULL;
13191 13336 int ret = DDI_FAILURE;
13192 13337
13193 13338 /*
13194 13339 * scsi_hba_tran_t->tran_tgt_private is used to pass the address
13195 13340 * information to scsi_init_pkt, allocate a scsi_hba_tran structure
13196 13341 * to simulate the cmds from sd
13197 13342 */
13198 13343 tran_clone = kmem_alloc(
13199 13344 sizeof (scsi_hba_tran_t), KM_SLEEP);
13200 13345 if (tran_clone == NULL) {
13201 13346 goto out;
13202 13347 }
13203 13348 bcopy((caddr_t)mpt->m_tran,
13204 13349 (caddr_t)tran_clone, sizeof (scsi_hba_tran_t));
13205 13350 tgt_private = kmem_alloc(
13206 13351 sizeof (mptsas_tgt_private_t), KM_SLEEP);
13207 13352 if (tgt_private == NULL) {
13208 13353 goto out;
13209 13354 }
13210 13355 tgt_private->t_lun = ap->a_lun;
13211 13356 tgt_private->t_private = ptgt;
13212 13357 tran_clone->tran_tgt_private = tgt_private;
13213 13358 ap->a_hba_tran = tran_clone;
13214 13359
13215 13360 pktp = scsi_init_pkt(ap, (struct scsi_pkt *)NULL,
13216 13361 data_bp, cdblen, sizeof (struct scsi_arq_status),
13217 13362 0, PKT_CONSISTENT, NULL, NULL);
13218 13363 if (pktp == NULL) {
13219 13364 goto out;
13220 13365 }
13221 13366 bcopy(cdb, pktp->pkt_cdbp, cdblen);
13222 13367 pktp->pkt_flags = FLAG_NOPARITY;
13223 13368 if (scsi_poll(pktp) < 0) {
13224 13369 goto out;
13225 13370 }
13226 13371 if (((struct scsi_status *)pktp->pkt_scbp)->sts_chk) {
13227 13372 goto out;
13228 13373 }
13229 13374 if (resid != NULL) {
13230 13375 *resid = pktp->pkt_resid;
13231 13376 }
13232 13377
13233 13378 ret = DDI_SUCCESS;
13234 13379 out:
13235 13380 if (pktp) {
13236 13381 scsi_destroy_pkt(pktp);
13237 13382 }
13238 13383 if (tran_clone) {
13239 13384 kmem_free(tran_clone, sizeof (scsi_hba_tran_t));
13240 13385 }
13241 13386 if (tgt_private) {
13242 13387 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t));
13243 13388 }
13244 13389 return (ret);
13245 13390 }
13246 13391 static int
13247 13392 mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, int *lun)
13248 13393 {
13249 13394 char *cp = NULL;
13250 13395 char *ptr = NULL;
13251 13396 size_t s = 0;
13252 13397 char *wwid_str = NULL;
13253 13398 char *lun_str = NULL;
13254 13399 long lunnum;
13255 13400 long phyid = -1;
13256 13401 int rc = DDI_FAILURE;
13257 13402
13258 13403 ptr = name;
13259 13404 ASSERT(ptr[0] == 'w' || ptr[0] == 'p');
13260 13405 ptr++;
13261 13406 if ((cp = strchr(ptr, ',')) == NULL) {
13262 13407 return (DDI_FAILURE);
13263 13408 }
13264 13409
13265 13410 wwid_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13266 13411 s = (uintptr_t)cp - (uintptr_t)ptr;
13267 13412
13268 13413 bcopy(ptr, wwid_str, s);
13269 13414 wwid_str[s] = '\0';
13270 13415
13271 13416 ptr = ++cp;
13272 13417
13273 13418 if ((cp = strchr(ptr, '\0')) == NULL) {
13274 13419 goto out;
13275 13420 }
13276 13421 lun_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13277 13422 s = (uintptr_t)cp - (uintptr_t)ptr;
13278 13423
13279 13424 bcopy(ptr, lun_str, s);
13280 13425 lun_str[s] = '\0';
13281 13426
13282 13427 if (name[0] == 'p') {
13283 13428 rc = ddi_strtol(wwid_str, NULL, 0x10, &phyid);
13284 13429 } else {
13285 13430 rc = scsi_wwnstr_to_wwn(wwid_str, wwid);
13286 13431 }
13287 13432 if (rc != DDI_SUCCESS)
13288 13433 goto out;
13289 13434
13290 13435 if (phyid != -1) {
13291 13436 ASSERT(phyid < MPTSAS_MAX_PHYS);
13292 13437 *phy = (uint8_t)phyid;
13293 13438 }
13294 13439 rc = ddi_strtol(lun_str, NULL, 0x10, &lunnum);
13295 13440 if (rc != 0)
13296 13441 goto out;
13297 13442
13298 13443 *lun = (int)lunnum;
13299 13444 rc = DDI_SUCCESS;
13300 13445 out:
13301 13446 if (wwid_str)
13302 13447 kmem_free(wwid_str, SCSI_MAXNAMELEN);
13303 13448 if (lun_str)
13304 13449 kmem_free(lun_str, SCSI_MAXNAMELEN);
13305 13450
13306 13451 return (rc);
13307 13452 }
13308 13453
13309 13454 /*
13310 13455 * mptsas_parse_smp_name() is to parse sas wwn string
13311 13456 * which format is "wWWN"
13312 13457 */
13313 13458 static int
13314 13459 mptsas_parse_smp_name(char *name, uint64_t *wwn)
13315 13460 {
13316 13461 char *ptr = name;
13317 13462
13318 13463 if (*ptr != 'w') {
13319 13464 return (DDI_FAILURE);
13320 13465 }
13321 13466
13322 13467 ptr++;
13323 13468 if (scsi_wwnstr_to_wwn(ptr, wwn)) {
13324 13469 return (DDI_FAILURE);
13325 13470 }
13326 13471 return (DDI_SUCCESS);
13327 13472 }
13328 13473
13329 13474 static int
13330 13475 mptsas_bus_config(dev_info_t *pdip, uint_t flag,
13331 13476 ddi_bus_config_op_t op, void *arg, dev_info_t **childp)
13332 13477 {
13333 13478 int ret = NDI_FAILURE;
13334 13479 int circ = 0;
13335 13480 int circ1 = 0;
13336 13481 mptsas_t *mpt;
13337 13482 char *ptr = NULL;
13338 13483 char *devnm = NULL;
13339 13484 uint64_t wwid = 0;
13340 13485 uint8_t phy = 0xFF;
13341 13486 int lun = 0;
13342 13487 uint_t mflags = flag;
13343 13488 int bconfig = TRUE;
13344 13489
13345 13490 if (scsi_hba_iport_unit_address(pdip) == 0) {
13346 13491 return (DDI_FAILURE);
13347 13492 }
13348 13493
13349 13494 mpt = DIP2MPT(pdip);
13350 13495 if (!mpt) {
13351 13496 return (DDI_FAILURE);
13352 13497 }
13353 13498 /*
13354 13499 * Hold the nexus across the bus_config
13355 13500 */
13356 13501 ndi_devi_enter(scsi_vhci_dip, &circ);
13357 13502 ndi_devi_enter(pdip, &circ1);
13358 13503 switch (op) {
13359 13504 case BUS_CONFIG_ONE:
13360 13505 /* parse wwid/target name out of name given */
13361 13506 if ((ptr = strchr((char *)arg, '@')) == NULL) {
13362 13507 ret = NDI_FAILURE;
13363 13508 break;
13364 13509 }
13365 13510 ptr++;
13366 13511 if (strncmp((char *)arg, "smp", 3) == 0) {
13367 13512 /*
13368 13513 * This is a SMP target device
13369 13514 */
13370 13515 ret = mptsas_parse_smp_name(ptr, &wwid);
13371 13516 if (ret != DDI_SUCCESS) {
13372 13517 ret = NDI_FAILURE;
13373 13518 break;
13374 13519 }
13375 13520 ret = mptsas_config_smp(pdip, wwid, childp);
13376 13521 } else if ((ptr[0] == 'w') || (ptr[0] == 'p')) {
13377 13522 /*
13378 13523 * OBP could pass down a non-canonical form
13379 13524 * bootpath without LUN part when LUN is 0.
13380 13525 * So driver need adjust the string.
13381 13526 */
13382 13527 if (strchr(ptr, ',') == NULL) {
13383 13528 devnm = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13384 13529 (void) sprintf(devnm, "%s,0", (char *)arg);
13385 13530 ptr = strchr(devnm, '@');
13386 13531 ptr++;
13387 13532 }
13388 13533
13389 13534 /*
13390 13535 * The device path is wWWID format and the device
13391 13536 * is not SMP target device.
13392 13537 */
13393 13538 ret = mptsas_parse_address(ptr, &wwid, &phy, &lun);
13394 13539 if (ret != DDI_SUCCESS) {
13395 13540 ret = NDI_FAILURE;
13396 13541 break;
13397 13542 }
13398 13543 *childp = NULL;
13399 13544 if (ptr[0] == 'w') {
13400 13545 ret = mptsas_config_one_addr(pdip, wwid,
13401 13546 lun, childp);
13402 13547 } else if (ptr[0] == 'p') {
13403 13548 ret = mptsas_config_one_phy(pdip, phy, lun,
13404 13549 childp);
13405 13550 }
13406 13551
13407 13552 /*
13408 13553 * If this is CD/DVD device in OBP path, the
13409 13554 * ndi_busop_bus_config can be skipped as config one
13410 13555 * operation is done above.
13411 13556 */
13412 13557 if ((ret == NDI_SUCCESS) && (*childp != NULL) &&
13413 13558 (strcmp(ddi_node_name(*childp), "cdrom") == 0) &&
13414 13559 (strncmp((char *)arg, "disk", 4) == 0)) {
13415 13560 bconfig = FALSE;
13416 13561 ndi_hold_devi(*childp);
13417 13562 }
13418 13563 } else {
13419 13564 ret = NDI_FAILURE;
13420 13565 break;
13421 13566 }
13422 13567
13423 13568 /*
13424 13569 * DDI group instructed us to use this flag.
13425 13570 */
13426 13571 mflags |= NDI_MDI_FALLBACK;
13427 13572 break;
13428 13573 case BUS_CONFIG_DRIVER:
13429 13574 case BUS_CONFIG_ALL:
13430 13575 mptsas_config_all(pdip);
13431 13576 ret = NDI_SUCCESS;
13432 13577 break;
13433 13578 }
13434 13579
13435 13580 if ((ret == NDI_SUCCESS) && bconfig) {
13436 13581 ret = ndi_busop_bus_config(pdip, mflags, op,
13437 13582 (devnm == NULL) ? arg : devnm, childp, 0);
13438 13583 }
13439 13584
13440 13585 ndi_devi_exit(pdip, circ1);
13441 13586 ndi_devi_exit(scsi_vhci_dip, circ);
13442 13587 if (devnm != NULL)
13443 13588 kmem_free(devnm, SCSI_MAXNAMELEN);
13444 13589 return (ret);
13445 13590 }
13446 13591
13447 13592 static int
13448 13593 mptsas_probe_lun(dev_info_t *pdip, int lun, dev_info_t **dip,
13449 13594 mptsas_target_t *ptgt)
13450 13595 {
13451 13596 int rval = DDI_FAILURE;
13452 13597 struct scsi_inquiry *sd_inq = NULL;
13453 13598 mptsas_t *mpt = DIP2MPT(pdip);
13454 13599
13455 13600 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP);
13456 13601
13457 13602 rval = mptsas_inquiry(mpt, ptgt, lun, 0, (uchar_t *)sd_inq,
13458 13603 SUN_INQSIZE, 0, (uchar_t)0);
13459 13604
13460 13605 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) {
13461 13606 rval = mptsas_create_lun(pdip, sd_inq, dip, ptgt, lun);
13462 13607 } else {
13463 13608 rval = DDI_FAILURE;
13464 13609 }
13465 13610
13466 13611 kmem_free(sd_inq, SUN_INQSIZE);
13467 13612 return (rval);
13468 13613 }
13469 13614
13470 13615 static int
13471 13616 mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun,
13472 13617 dev_info_t **lundip)
13473 13618 {
13474 13619 int rval;
13475 13620 mptsas_t *mpt = DIP2MPT(pdip);
13476 13621 int phymask;
13477 13622 mptsas_target_t *ptgt = NULL;
13478 13623
13479 13624 /*
13480 13625 * Get the physical port associated to the iport
13481 13626 */
13482 13627 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
13483 13628 "phymask", 0);
13484 13629
13485 13630 ptgt = mptsas_wwid_to_ptgt(mpt, phymask, sasaddr);
13486 13631 if (ptgt == NULL) {
13487 13632 /*
13488 13633 * didn't match any device by searching
13489 13634 */
13490 13635 return (DDI_FAILURE);
13491 13636 }
13492 13637 /*
13493 13638 * If the LUN already exists and the status is online,
13494 13639 * we just return the pointer to dev_info_t directly.
13495 13640 * For the mdi_pathinfo node, we'll handle it in
13496 13641 * mptsas_create_virt_lun()
13497 13642 * TODO should be also in mptsas_handle_dr
13498 13643 */
13499 13644
13500 13645 *lundip = mptsas_find_child_addr(pdip, sasaddr, lun);
13501 13646 if (*lundip != NULL) {
13502 13647 /*
13503 13648 * TODO Another senario is, we hotplug the same disk
13504 13649 * on the same slot, the devhdl changed, is this
13505 13650 * possible?
13506 13651 * tgt_private->t_private != ptgt
13507 13652 */
13508 13653 if (sasaddr != ptgt->m_sas_wwn) {
13509 13654 /*
13510 13655 * The device has changed although the devhdl is the
13511 13656 * same (Enclosure mapping mode, change drive on the
13512 13657 * same slot)
13513 13658 */
13514 13659 return (DDI_FAILURE);
13515 13660 }
13516 13661 return (DDI_SUCCESS);
13517 13662 }
13518 13663
13519 13664 if (phymask == 0) {
13520 13665 /*
13521 13666 * Configure IR volume
13522 13667 */
13523 13668 rval = mptsas_config_raid(pdip, ptgt->m_devhdl, lundip);
13524 13669 return (rval);
13525 13670 }
13526 13671 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt);
13527 13672
13528 13673 return (rval);
13529 13674 }
13530 13675
13531 13676 static int
13532 13677 mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun,
13533 13678 dev_info_t **lundip)
13534 13679 {
13535 13680 int rval;
13536 13681 mptsas_t *mpt = DIP2MPT(pdip);
13537 13682 int phymask;
13538 13683 mptsas_target_t *ptgt = NULL;
13539 13684
13540 13685 /*
13541 13686 * Get the physical port associated to the iport
13542 13687 */
13543 13688 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
13544 13689 "phymask", 0);
13545 13690
13546 13691 ptgt = mptsas_phy_to_tgt(mpt, phymask, phy);
13547 13692 if (ptgt == NULL) {
13548 13693 /*
13549 13694 * didn't match any device by searching
13550 13695 */
13551 13696 return (DDI_FAILURE);
13552 13697 }
13553 13698
13554 13699 /*
13555 13700 * If the LUN already exists and the status is online,
13556 13701 * we just return the pointer to dev_info_t directly.
13557 13702 * For the mdi_pathinfo node, we'll handle it in
13558 13703 * mptsas_create_virt_lun().
13559 13704 */
13560 13705
13561 13706 *lundip = mptsas_find_child_phy(pdip, phy);
13562 13707 if (*lundip != NULL) {
13563 13708 return (DDI_SUCCESS);
13564 13709 }
13565 13710
13566 13711 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt);
13567 13712
13568 13713 return (rval);
13569 13714 }
13570 13715
13571 13716 static int
13572 13717 mptsas_retrieve_lundata(int lun_cnt, uint8_t *buf, uint16_t *lun_num,
13573 13718 uint8_t *lun_addr_type)
13574 13719 {
13575 13720 uint32_t lun_idx = 0;
13576 13721
13577 13722 ASSERT(lun_num != NULL);
13578 13723 ASSERT(lun_addr_type != NULL);
13579 13724
13580 13725 lun_idx = (lun_cnt + 1) * MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE;
13581 13726 /* determine report luns addressing type */
13582 13727 switch (buf[lun_idx] & MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) {
13583 13728 /*
13584 13729 * Vendors in the field have been found to be concatenating
13585 13730 * bus/target/lun to equal the complete lun value instead
13586 13731 * of switching to flat space addressing
13587 13732 */
13588 13733 /* 00b - peripheral device addressing method */
13589 13734 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL:
13590 13735 /* FALLTHRU */
13591 13736 /* 10b - logical unit addressing method */
13592 13737 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT:
13593 13738 /* FALLTHRU */
13594 13739 /* 01b - flat space addressing method */
13595 13740 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE:
13596 13741 /* byte0 bit0-5=msb lun byte1 bit0-7=lsb lun */
13597 13742 *lun_addr_type = (buf[lun_idx] &
13598 13743 MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) >> 6;
13599 13744 *lun_num = (buf[lun_idx] & 0x3F) << 8;
13600 13745 *lun_num |= buf[lun_idx + 1];
13601 13746 return (DDI_SUCCESS);
13602 13747 default:
13603 13748 return (DDI_FAILURE);
13604 13749 }
13605 13750 }
13606 13751
13607 13752 static int
13608 13753 mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt)
13609 13754 {
13610 13755 struct buf *repluns_bp = NULL;
13611 13756 struct scsi_address ap;
13612 13757 uchar_t cdb[CDB_GROUP5];
13613 13758 int ret = DDI_FAILURE;
13614 13759 int retry = 0;
13615 13760 int lun_list_len = 0;
13616 13761 uint16_t lun_num = 0;
13617 13762 uint8_t lun_addr_type = 0;
13618 13763 uint32_t lun_cnt = 0;
13619 13764 uint32_t lun_total = 0;
13620 13765 dev_info_t *cdip = NULL;
13621 13766 uint16_t *saved_repluns = NULL;
13622 13767 char *buffer = NULL;
13623 13768 int buf_len = 128;
13624 13769 mptsas_t *mpt = DIP2MPT(pdip);
13625 13770 uint64_t sas_wwn = 0;
13626 13771 uint8_t phy = 0xFF;
13627 13772 uint32_t dev_info = 0;
13628 13773
13629 13774 mutex_enter(&mpt->m_mutex);
13630 13775 sas_wwn = ptgt->m_sas_wwn;
13631 13776 phy = ptgt->m_phynum;
13632 13777 dev_info = ptgt->m_deviceinfo;
13633 13778 mutex_exit(&mpt->m_mutex);
13634 13779
13635 13780 if (sas_wwn == 0) {
13636 13781 /*
13637 13782 * It's a SATA without Device Name
13638 13783 * So don't try multi-LUNs
13639 13784 */
13640 13785 if (mptsas_find_child_phy(pdip, phy)) {
13641 13786 return (DDI_SUCCESS);
13642 13787 } else {
13643 13788 /*
13644 13789 * need configure and create node
13645 13790 */
13646 13791 return (DDI_FAILURE);
13647 13792 }
13648 13793 }
13649 13794
13650 13795 /*
13651 13796 * WWN (SAS address or Device Name exist)
13652 13797 */
13653 13798 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
13654 13799 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
13655 13800 /*
13656 13801 * SATA device with Device Name
13657 13802 * So don't try multi-LUNs
13658 13803 */
13659 13804 if (mptsas_find_child_addr(pdip, sas_wwn, 0)) {
13660 13805 return (DDI_SUCCESS);
13661 13806 } else {
13662 13807 return (DDI_FAILURE);
13663 13808 }
13664 13809 }
13665 13810
13666 13811 do {
13667 13812 ap.a_target = MPTSAS_INVALID_DEVHDL;
13668 13813 ap.a_lun = 0;
13669 13814 ap.a_hba_tran = mpt->m_tran;
13670 13815 repluns_bp = scsi_alloc_consistent_buf(&ap,
13671 13816 (struct buf *)NULL, buf_len, B_READ, NULL_FUNC, NULL);
13672 13817 if (repluns_bp == NULL) {
13673 13818 retry++;
13674 13819 continue;
13675 13820 }
13676 13821 bzero(cdb, CDB_GROUP5);
13677 13822 cdb[0] = SCMD_REPORT_LUNS;
13678 13823 cdb[6] = (buf_len & 0xff000000) >> 24;
13679 13824 cdb[7] = (buf_len & 0x00ff0000) >> 16;
13680 13825 cdb[8] = (buf_len & 0x0000ff00) >> 8;
13681 13826 cdb[9] = (buf_len & 0x000000ff);
13682 13827
13683 13828 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP5,
13684 13829 repluns_bp, NULL);
13685 13830 if (ret != DDI_SUCCESS) {
13686 13831 scsi_free_consistent_buf(repluns_bp);
13687 13832 retry++;
13688 13833 continue;
13689 13834 }
13690 13835 lun_list_len = BE_32(*(int *)((void *)(
13691 13836 repluns_bp->b_un.b_addr)));
13692 13837 if (buf_len >= lun_list_len + 8) {
13693 13838 ret = DDI_SUCCESS;
13694 13839 break;
13695 13840 }
13696 13841 scsi_free_consistent_buf(repluns_bp);
13697 13842 buf_len = lun_list_len + 8;
13698 13843
13699 13844 } while (retry < 3);
13700 13845
13701 13846 if (ret != DDI_SUCCESS)
13702 13847 return (ret);
13703 13848 buffer = (char *)repluns_bp->b_un.b_addr;
13704 13849 /*
13705 13850 * find out the number of luns returned by the SCSI ReportLun call
13706 13851 * and allocate buffer space
13707 13852 */
13708 13853 lun_total = lun_list_len / MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE;
13709 13854 saved_repluns = kmem_zalloc(sizeof (uint16_t) * lun_total, KM_SLEEP);
13710 13855 if (saved_repluns == NULL) {
13711 13856 scsi_free_consistent_buf(repluns_bp);
13712 13857 return (DDI_FAILURE);
13713 13858 }
13714 13859 for (lun_cnt = 0; lun_cnt < lun_total; lun_cnt++) {
13715 13860 if (mptsas_retrieve_lundata(lun_cnt, (uint8_t *)(buffer),
13716 13861 &lun_num, &lun_addr_type) != DDI_SUCCESS) {
13717 13862 continue;
13718 13863 }
13719 13864 saved_repluns[lun_cnt] = lun_num;
13720 13865 if (cdip = mptsas_find_child_addr(pdip, sas_wwn, lun_num))
13721 13866 ret = DDI_SUCCESS;
13722 13867 else
13723 13868 ret = mptsas_probe_lun(pdip, lun_num, &cdip,
13724 13869 ptgt);
13725 13870 if ((ret == DDI_SUCCESS) && (cdip != NULL)) {
13726 13871 (void) ndi_prop_remove(DDI_DEV_T_NONE, cdip,
13727 13872 MPTSAS_DEV_GONE);
13728 13873 }
13729 13874 }
13730 13875 mptsas_offline_missed_luns(pdip, saved_repluns, lun_total, ptgt);
13731 13876 kmem_free(saved_repluns, sizeof (uint16_t) * lun_total);
13732 13877 scsi_free_consistent_buf(repluns_bp);
13733 13878 return (DDI_SUCCESS);
13734 13879 }
13735 13880
13736 13881 static int
13737 13882 mptsas_config_raid(dev_info_t *pdip, uint16_t target, dev_info_t **dip)
13738 13883 {
13739 13884 int rval = DDI_FAILURE;
13740 13885 struct scsi_inquiry *sd_inq = NULL;
13741 13886 mptsas_t *mpt = DIP2MPT(pdip);
13742 13887 mptsas_target_t *ptgt = NULL;
13743 13888
13744 13889 mutex_enter(&mpt->m_mutex);
13745 13890 ptgt = mptsas_search_by_devhdl(&mpt->m_active->m_tgttbl, target);
13746 13891 mutex_exit(&mpt->m_mutex);
13747 13892 if (ptgt == NULL) {
13748 13893 mptsas_log(mpt, CE_WARN, "Volume with VolDevHandle of 0x%x "
13749 13894 "not found.", target);
13750 13895 return (rval);
13751 13896 }
13752 13897
13753 13898 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP);
13754 13899 rval = mptsas_inquiry(mpt, ptgt, 0, 0, (uchar_t *)sd_inq,
13755 13900 SUN_INQSIZE, 0, (uchar_t)0);
13756 13901
13757 13902 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) {
13758 13903 rval = mptsas_create_phys_lun(pdip, sd_inq, NULL, dip, ptgt,
13759 13904 0);
13760 13905 } else {
13761 13906 rval = DDI_FAILURE;
13762 13907 }
13763 13908
13764 13909 kmem_free(sd_inq, SUN_INQSIZE);
13765 13910 return (rval);
13766 13911 }
13767 13912
13768 13913 /*
13769 13914 * configure all RAID volumes for virtual iport
13770 13915 */
13771 13916 static void
13772 13917 mptsas_config_all_viport(dev_info_t *pdip)
13773 13918 {
13774 13919 mptsas_t *mpt = DIP2MPT(pdip);
13775 13920 int config, vol;
13776 13921 int target;
13777 13922 dev_info_t *lundip = NULL;
13778 13923 mptsas_slots_t *slots = mpt->m_active;
13779 13924
13780 13925 /*
13781 13926 * Get latest RAID info and search for any Volume DevHandles. If any
13782 13927 * are found, configure the volume.
13783 13928 */
13784 13929 mutex_enter(&mpt->m_mutex);
13785 13930 for (config = 0; config < slots->m_num_raid_configs; config++) {
13786 13931 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) {
13787 13932 if (slots->m_raidconfig[config].m_raidvol[vol].m_israid
13788 13933 == 1) {
13789 13934 target = slots->m_raidconfig[config].
13790 13935 m_raidvol[vol].m_raidhandle;
13791 13936 mutex_exit(&mpt->m_mutex);
13792 13937 (void) mptsas_config_raid(pdip, target,
13793 13938 &lundip);
13794 13939 mutex_enter(&mpt->m_mutex);
13795 13940 }
13796 13941 }
13797 13942 }
13798 13943 mutex_exit(&mpt->m_mutex);
13799 13944 }
13800 13945
13801 13946 static void
13802 13947 mptsas_offline_missed_luns(dev_info_t *pdip, uint16_t *repluns,
13803 13948 int lun_cnt, mptsas_target_t *ptgt)
13804 13949 {
13805 13950 dev_info_t *child = NULL, *savechild = NULL;
13806 13951 mdi_pathinfo_t *pip = NULL, *savepip = NULL;
13807 13952 uint64_t sas_wwn, wwid;
13808 13953 uint8_t phy;
13809 13954 int lun;
13810 13955 int i;
13811 13956 int find;
13812 13957 char *addr;
13813 13958 char *nodename;
13814 13959 mptsas_t *mpt = DIP2MPT(pdip);
13815 13960
13816 13961 mutex_enter(&mpt->m_mutex);
13817 13962 wwid = ptgt->m_sas_wwn;
13818 13963 mutex_exit(&mpt->m_mutex);
13819 13964
13820 13965 child = ddi_get_child(pdip);
13821 13966 while (child) {
13822 13967 find = 0;
13823 13968 savechild = child;
13824 13969 child = ddi_get_next_sibling(child);
13825 13970
13826 13971 nodename = ddi_node_name(savechild);
13827 13972 if (strcmp(nodename, "smp") == 0) {
13828 13973 continue;
13829 13974 }
13830 13975
13831 13976 addr = ddi_get_name_addr(savechild);
13832 13977 if (addr == NULL) {
13833 13978 continue;
13834 13979 }
13835 13980
13836 13981 if (mptsas_parse_address(addr, &sas_wwn, &phy, &lun) !=
13837 13982 DDI_SUCCESS) {
13838 13983 continue;
13839 13984 }
13840 13985
13841 13986 if (wwid == sas_wwn) {
13842 13987 for (i = 0; i < lun_cnt; i++) {
13843 13988 if (repluns[i] == lun) {
13844 13989 find = 1;
13845 13990 break;
13846 13991 }
13847 13992 }
13848 13993 } else {
13849 13994 continue;
13850 13995 }
13851 13996 if (find == 0) {
13852 13997 /*
13853 13998 * The lun has not been there already
13854 13999 */
13855 14000 (void) mptsas_offline_lun(pdip, savechild, NULL,
13856 14001 NDI_DEVI_REMOVE);
13857 14002 }
13858 14003 }
13859 14004
13860 14005 pip = mdi_get_next_client_path(pdip, NULL);
13861 14006 while (pip) {
13862 14007 find = 0;
13863 14008 savepip = pip;
13864 14009 addr = MDI_PI(pip)->pi_addr;
13865 14010
13866 14011 pip = mdi_get_next_client_path(pdip, pip);
13867 14012
13868 14013 if (addr == NULL) {
13869 14014 continue;
13870 14015 }
13871 14016
13872 14017 if (mptsas_parse_address(addr, &sas_wwn, &phy,
13873 14018 &lun) != DDI_SUCCESS) {
13874 14019 continue;
13875 14020 }
13876 14021
13877 14022 if (sas_wwn == wwid) {
13878 14023 for (i = 0; i < lun_cnt; i++) {
13879 14024 if (repluns[i] == lun) {
13880 14025 find = 1;
13881 14026 break;
13882 14027 }
13883 14028 }
13884 14029 } else {
13885 14030 continue;
13886 14031 }
13887 14032
13888 14033 if (find == 0) {
13889 14034 /*
13890 14035 * The lun has not been there already
13891 14036 */
13892 14037 (void) mptsas_offline_lun(pdip, NULL, savepip,
13893 14038 NDI_DEVI_REMOVE);
13894 14039 }
13895 14040 }
13896 14041 }
13897 14042
13898 14043 void
13899 14044 mptsas_update_hashtab(struct mptsas *mpt)
13900 14045 {
13901 14046 uint32_t page_address;
13902 14047 int rval = 0;
13903 14048 uint16_t dev_handle;
13904 14049 mptsas_target_t *ptgt = NULL;
13905 14050 mptsas_smp_t smp_node;
13906 14051
13907 14052 /*
13908 14053 * Get latest RAID info.
13909 14054 */
13910 14055 (void) mptsas_get_raid_info(mpt);
13911 14056
13912 14057 dev_handle = mpt->m_smp_devhdl;
13913 14058 for (; mpt->m_done_traverse_smp == 0; ) {
13914 14059 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL &
13915 14060 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)dev_handle;
13916 14061 if (mptsas_get_sas_expander_page0(mpt, page_address, &smp_node)
13917 14062 != DDI_SUCCESS) {
13918 14063 break;
13919 14064 }
13920 14065 mpt->m_smp_devhdl = dev_handle = smp_node.m_devhdl;
13921 14066 (void) mptsas_smp_alloc(&mpt->m_active->m_smptbl, &smp_node);
13922 14067 }
13923 14068
13924 14069 /*
13925 14070 * Config target devices
13926 14071 */
13927 14072 dev_handle = mpt->m_dev_handle;
13928 14073
13929 14074 /*
13930 14075 * Do loop to get sas device page 0 by GetNextHandle till the
13931 14076 * the last handle. If the sas device is a SATA/SSP target,
13932 14077 * we try to config it.
13933 14078 */
13934 14079 for (; mpt->m_done_traverse_dev == 0; ) {
13935 14080 ptgt = NULL;
13936 14081 page_address =
13937 14082 (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
13938 14083 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
13939 14084 (uint32_t)dev_handle;
13940 14085 rval = mptsas_get_target_device_info(mpt, page_address,
13941 14086 &dev_handle, &ptgt);
13942 14087 if ((rval == DEV_INFO_FAIL_PAGE0) ||
13943 14088 (rval == DEV_INFO_FAIL_ALLOC)) {
13944 14089 break;
13945 14090 }
13946 14091
13947 14092 mpt->m_dev_handle = dev_handle;
13948 14093 }
13949 14094
13950 14095 }
13951 14096
13952 14097 void
13953 14098 mptsas_invalid_hashtab(mptsas_hash_table_t *hashtab)
13954 14099 {
13955 14100 mptsas_hash_data_t *data;
13956 14101 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_FIRST);
13957 14102 while (data != NULL) {
13958 14103 data->devhdl = MPTSAS_INVALID_DEVHDL;
13959 14104 data->device_info = 0;
13960 14105 /*
13961 14106 * For tgttbl, clear dr_flag.
13962 14107 */
13963 14108 data->dr_flag = MPTSAS_DR_INACTIVE;
13964 14109 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_NEXT);
13965 14110 }
13966 14111 }
13967 14112
13968 14113 void
13969 14114 mptsas_update_driver_data(struct mptsas *mpt)
13970 14115 {
13971 14116 /*
13972 14117 * TODO after hard reset, update the driver data structures
13973 14118 * 1. update port/phymask mapping table mpt->m_phy_info
13974 14119 * 2. invalid all the entries in hash table
13975 14120 * m_devhdl = 0xffff and m_deviceinfo = 0
13976 14121 * 3. call sas_device_page/expander_page to update hash table
13977 14122 */
13978 14123 mptsas_update_phymask(mpt);
13979 14124 /*
13980 14125 * Invalid the existing entries
13981 14126 */
13982 14127 mptsas_invalid_hashtab(&mpt->m_active->m_tgttbl);
13983 14128 mptsas_invalid_hashtab(&mpt->m_active->m_smptbl);
13984 14129 mpt->m_done_traverse_dev = 0;
13985 14130 mpt->m_done_traverse_smp = 0;
13986 14131 mpt->m_dev_handle = mpt->m_smp_devhdl = MPTSAS_INVALID_DEVHDL;
13987 14132 mptsas_update_hashtab(mpt);
13988 14133 }
13989 14134
13990 14135 static void
13991 14136 mptsas_config_all(dev_info_t *pdip)
13992 14137 {
13993 14138 dev_info_t *smpdip = NULL;
13994 14139 mptsas_t *mpt = DIP2MPT(pdip);
13995 14140 int phymask = 0;
13996 14141 mptsas_phymask_t phy_mask;
13997 14142 mptsas_target_t *ptgt = NULL;
13998 14143 mptsas_smp_t *psmp;
13999 14144
14000 14145 /*
14001 14146 * Get the phymask associated to the iport
14002 14147 */
14003 14148 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
14004 14149 "phymask", 0);
14005 14150
14006 14151 /*
14007 14152 * Enumerate RAID volumes here (phymask == 0).
14008 14153 */
14009 14154 if (phymask == 0) {
14010 14155 mptsas_config_all_viport(pdip);
14011 14156 return;
14012 14157 }
14013 14158
14014 14159 mutex_enter(&mpt->m_mutex);
14015 14160
14016 14161 if (!mpt->m_done_traverse_dev || !mpt->m_done_traverse_smp) {
14017 14162 mptsas_update_hashtab(mpt);
14018 14163 }
14019 14164
14020 14165 psmp = (mptsas_smp_t *)mptsas_hash_traverse(&mpt->m_active->m_smptbl,
14021 14166 MPTSAS_HASH_FIRST);
14022 14167 while (psmp != NULL) {
14023 14168 phy_mask = psmp->m_phymask;
14024 14169 if (phy_mask == phymask) {
14025 14170 smpdip = NULL;
14026 14171 mutex_exit(&mpt->m_mutex);
14027 14172 (void) mptsas_online_smp(pdip, psmp, &smpdip);
14028 14173 mutex_enter(&mpt->m_mutex);
14029 14174 }
14030 14175 psmp = (mptsas_smp_t *)mptsas_hash_traverse(
14031 14176 &mpt->m_active->m_smptbl, MPTSAS_HASH_NEXT);
14032 14177 }
14033 14178
14034 14179 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
14035 14180 MPTSAS_HASH_FIRST);
14036 14181 while (ptgt != NULL) {
14037 14182 phy_mask = ptgt->m_phymask;
14038 14183 if (phy_mask == phymask) {
14039 14184 mutex_exit(&mpt->m_mutex);
14040 14185 (void) mptsas_config_target(pdip, ptgt);
14041 14186 mutex_enter(&mpt->m_mutex);
14042 14187 }
14043 14188
14044 14189 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
14045 14190 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
14046 14191 }
14047 14192 mutex_exit(&mpt->m_mutex);
14048 14193 }
14049 14194
14050 14195 static int
14051 14196 mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt)
14052 14197 {
14053 14198 int rval = DDI_FAILURE;
14054 14199 dev_info_t *tdip;
14055 14200
14056 14201 rval = mptsas_config_luns(pdip, ptgt);
14057 14202 if (rval != DDI_SUCCESS) {
14058 14203 /*
14059 14204 * The return value means the SCMD_REPORT_LUNS
14060 14205 * did not execute successfully. The target maybe
14061 14206 * doesn't support such command.
14062 14207 */
14063 14208 rval = mptsas_probe_lun(pdip, 0, &tdip, ptgt);
14064 14209 }
14065 14210 return (rval);
14066 14211 }
14067 14212
14068 14213 /*
14069 14214 * Return fail if not all the childs/paths are freed.
14070 14215 * if there is any path under the HBA, the return value will be always fail
14071 14216 * because we didn't call mdi_pi_free for path
14072 14217 */
14073 14218 static int
14074 14219 mptsas_offline_target(dev_info_t *pdip, char *name)
14075 14220 {
14076 14221 dev_info_t *child = NULL, *prechild = NULL;
14077 14222 mdi_pathinfo_t *pip = NULL, *savepip = NULL;
14078 14223 int tmp_rval, rval = DDI_SUCCESS;
14079 14224 char *addr, *cp;
14080 14225 size_t s;
14081 14226 mptsas_t *mpt = DIP2MPT(pdip);
14082 14227
14083 14228 child = ddi_get_child(pdip);
14084 14229 while (child) {
14085 14230 addr = ddi_get_name_addr(child);
14086 14231 prechild = child;
14087 14232 child = ddi_get_next_sibling(child);
14088 14233
14089 14234 if (addr == NULL) {
14090 14235 continue;
14091 14236 }
14092 14237 if ((cp = strchr(addr, ',')) == NULL) {
14093 14238 continue;
14094 14239 }
14095 14240
14096 14241 s = (uintptr_t)cp - (uintptr_t)addr;
14097 14242
14098 14243 if (strncmp(addr, name, s) != 0) {
14099 14244 continue;
14100 14245 }
14101 14246
14102 14247 tmp_rval = mptsas_offline_lun(pdip, prechild, NULL,
14103 14248 NDI_DEVI_REMOVE);
14104 14249 if (tmp_rval != DDI_SUCCESS) {
14105 14250 rval = DDI_FAILURE;
14106 14251 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
14107 14252 prechild, MPTSAS_DEV_GONE) !=
14108 14253 DDI_PROP_SUCCESS) {
14109 14254 mptsas_log(mpt, CE_WARN, "mptsas driver "
14110 14255 "unable to create property for "
14111 14256 "SAS %s (MPTSAS_DEV_GONE)", addr);
14112 14257 }
14113 14258 }
14114 14259 }
14115 14260
14116 14261 pip = mdi_get_next_client_path(pdip, NULL);
14117 14262 while (pip) {
14118 14263 addr = MDI_PI(pip)->pi_addr;
14119 14264 savepip = pip;
14120 14265 pip = mdi_get_next_client_path(pdip, pip);
14121 14266 if (addr == NULL) {
14122 14267 continue;
14123 14268 }
14124 14269
14125 14270 if ((cp = strchr(addr, ',')) == NULL) {
14126 14271 continue;
14127 14272 }
14128 14273
14129 14274 s = (uintptr_t)cp - (uintptr_t)addr;
14130 14275
14131 14276 if (strncmp(addr, name, s) != 0) {
14132 14277 continue;
14133 14278 }
14134 14279
14135 14280 (void) mptsas_offline_lun(pdip, NULL, savepip,
14136 14281 NDI_DEVI_REMOVE);
14137 14282 /*
14138 14283 * driver will not invoke mdi_pi_free, so path will not
14139 14284 * be freed forever, return DDI_FAILURE.
14140 14285 */
14141 14286 rval = DDI_FAILURE;
14142 14287 }
14143 14288 return (rval);
14144 14289 }
14145 14290
14146 14291 static int
14147 14292 mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip,
14148 14293 mdi_pathinfo_t *rpip, uint_t flags)
14149 14294 {
14150 14295 int rval = DDI_FAILURE;
14151 14296 char *devname;
14152 14297 dev_info_t *cdip, *parent;
14153 14298
14154 14299 if (rpip != NULL) {
14155 14300 parent = scsi_vhci_dip;
14156 14301 cdip = mdi_pi_get_client(rpip);
14157 14302 } else if (rdip != NULL) {
14158 14303 parent = pdip;
14159 14304 cdip = rdip;
14160 14305 } else {
14161 14306 return (DDI_FAILURE);
14162 14307 }
14163 14308
14164 14309 /*
14165 14310 * Make sure node is attached otherwise
14166 14311 * it won't have related cache nodes to
14167 14312 * clean up. i_ddi_devi_attached is
14168 14313 * similiar to i_ddi_node_state(cdip) >=
14169 14314 * DS_ATTACHED.
14170 14315 */
14171 14316 if (i_ddi_devi_attached(cdip)) {
14172 14317
14173 14318 /* Get full devname */
14174 14319 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP);
14175 14320 (void) ddi_deviname(cdip, devname);
14176 14321 /* Clean cache */
14177 14322 (void) devfs_clean(parent, devname + 1,
14178 14323 DV_CLEAN_FORCE);
14179 14324 kmem_free(devname, MAXNAMELEN + 1);
14180 14325 }
14181 14326 if (rpip != NULL) {
14182 14327 if (MDI_PI_IS_OFFLINE(rpip)) {
14183 14328 rval = DDI_SUCCESS;
14184 14329 } else {
14185 14330 rval = mdi_pi_offline(rpip, 0);
14186 14331 }
14187 14332 } else {
14188 14333 rval = ndi_devi_offline(cdip, flags);
14189 14334 }
14190 14335
14191 14336 return (rval);
14192 14337 }
14193 14338
14194 14339 static dev_info_t *
14195 14340 mptsas_find_smp_child(dev_info_t *parent, char *str_wwn)
14196 14341 {
14197 14342 dev_info_t *child = NULL;
14198 14343 char *smp_wwn = NULL;
14199 14344
14200 14345 child = ddi_get_child(parent);
14201 14346 while (child) {
14202 14347 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, child,
14203 14348 DDI_PROP_DONTPASS, SMP_WWN, &smp_wwn)
14204 14349 != DDI_SUCCESS) {
14205 14350 child = ddi_get_next_sibling(child);
14206 14351 continue;
14207 14352 }
14208 14353
14209 14354 if (strcmp(smp_wwn, str_wwn) == 0) {
14210 14355 ddi_prop_free(smp_wwn);
14211 14356 break;
14212 14357 }
14213 14358 child = ddi_get_next_sibling(child);
14214 14359 ddi_prop_free(smp_wwn);
14215 14360 }
14216 14361 return (child);
14217 14362 }
14218 14363
14219 14364 static int
14220 14365 mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, uint_t flags)
14221 14366 {
14222 14367 int rval = DDI_FAILURE;
14223 14368 char *devname;
14224 14369 char wwn_str[MPTSAS_WWN_STRLEN];
14225 14370 dev_info_t *cdip;
14226 14371
14227 14372 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_sasaddr);
14228 14373
14229 14374 cdip = mptsas_find_smp_child(pdip, wwn_str);
14230 14375
14231 14376 if (cdip == NULL)
14232 14377 return (DDI_SUCCESS);
14233 14378
14234 14379 /*
14235 14380 * Make sure node is attached otherwise
14236 14381 * it won't have related cache nodes to
14237 14382 * clean up. i_ddi_devi_attached is
14238 14383 * similiar to i_ddi_node_state(cdip) >=
14239 14384 * DS_ATTACHED.
14240 14385 */
14241 14386 if (i_ddi_devi_attached(cdip)) {
14242 14387
14243 14388 /* Get full devname */
14244 14389 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP);
14245 14390 (void) ddi_deviname(cdip, devname);
14246 14391 /* Clean cache */
14247 14392 (void) devfs_clean(pdip, devname + 1,
14248 14393 DV_CLEAN_FORCE);
14249 14394 kmem_free(devname, MAXNAMELEN + 1);
14250 14395 }
14251 14396
14252 14397 rval = ndi_devi_offline(cdip, flags);
14253 14398
14254 14399 return (rval);
14255 14400 }
14256 14401
14257 14402 static dev_info_t *
14258 14403 mptsas_find_child(dev_info_t *pdip, char *name)
14259 14404 {
14260 14405 dev_info_t *child = NULL;
14261 14406 char *rname = NULL;
14262 14407 int rval = DDI_FAILURE;
14263 14408
14264 14409 rname = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14265 14410
14266 14411 child = ddi_get_child(pdip);
14267 14412 while (child) {
14268 14413 rval = mptsas_name_child(child, rname, SCSI_MAXNAMELEN);
14269 14414 if (rval != DDI_SUCCESS) {
14270 14415 child = ddi_get_next_sibling(child);
14271 14416 bzero(rname, SCSI_MAXNAMELEN);
14272 14417 continue;
14273 14418 }
14274 14419
14275 14420 if (strcmp(rname, name) == 0) {
14276 14421 break;
14277 14422 }
14278 14423 child = ddi_get_next_sibling(child);
14279 14424 bzero(rname, SCSI_MAXNAMELEN);
14280 14425 }
14281 14426
14282 14427 kmem_free(rname, SCSI_MAXNAMELEN);
14283 14428
14284 14429 return (child);
14285 14430 }
14286 14431
14287 14432
14288 14433 static dev_info_t *
14289 14434 mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, int lun)
14290 14435 {
14291 14436 dev_info_t *child = NULL;
14292 14437 char *name = NULL;
14293 14438 char *addr = NULL;
14294 14439
14295 14440 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14296 14441 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14297 14442 (void) sprintf(name, "%016"PRIx64, sasaddr);
14298 14443 (void) sprintf(addr, "w%s,%x", name, lun);
14299 14444 child = mptsas_find_child(pdip, addr);
14300 14445 kmem_free(name, SCSI_MAXNAMELEN);
14301 14446 kmem_free(addr, SCSI_MAXNAMELEN);
14302 14447 return (child);
14303 14448 }
14304 14449
14305 14450 static dev_info_t *
14306 14451 mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy)
14307 14452 {
14308 14453 dev_info_t *child;
14309 14454 char *addr;
14310 14455
14311 14456 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14312 14457 (void) sprintf(addr, "p%x,0", phy);
14313 14458 child = mptsas_find_child(pdip, addr);
14314 14459 kmem_free(addr, SCSI_MAXNAMELEN);
14315 14460 return (child);
14316 14461 }
14317 14462
14318 14463 static mdi_pathinfo_t *
14319 14464 mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy)
14320 14465 {
14321 14466 mdi_pathinfo_t *path;
14322 14467 char *addr = NULL;
14323 14468
14324 14469 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14325 14470 (void) sprintf(addr, "p%x,0", phy);
14326 14471 path = mdi_pi_find(pdip, NULL, addr);
14327 14472 kmem_free(addr, SCSI_MAXNAMELEN);
14328 14473 return (path);
14329 14474 }
14330 14475
14331 14476 static mdi_pathinfo_t *
14332 14477 mptsas_find_path_addr(dev_info_t *parent, uint64_t sasaddr, int lun)
14333 14478 {
14334 14479 mdi_pathinfo_t *path;
14335 14480 char *name = NULL;
14336 14481 char *addr = NULL;
14337 14482
14338 14483 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14339 14484 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14340 14485 (void) sprintf(name, "%016"PRIx64, sasaddr);
14341 14486 (void) sprintf(addr, "w%s,%x", name, lun);
14342 14487 path = mdi_pi_find(parent, NULL, addr);
14343 14488 kmem_free(name, SCSI_MAXNAMELEN);
14344 14489 kmem_free(addr, SCSI_MAXNAMELEN);
14345 14490
14346 14491 return (path);
14347 14492 }
14348 14493
14349 14494 static int
14350 14495 mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq,
14351 14496 dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun)
14352 14497 {
14353 14498 int i = 0;
14354 14499 uchar_t *inq83 = NULL;
14355 14500 int inq83_len1 = 0xFF;
14356 14501 int inq83_len = 0;
14357 14502 int rval = DDI_FAILURE;
14358 14503 ddi_devid_t devid;
14359 14504 char *guid = NULL;
14360 14505 int target = ptgt->m_devhdl;
14361 14506 mdi_pathinfo_t *pip = NULL;
14362 14507 mptsas_t *mpt = DIP2MPT(pdip);
14363 14508
14364 14509 /*
14365 14510 * For DVD/CD ROM and tape devices and optical
14366 14511 * devices, we won't try to enumerate them under
14367 14512 * scsi_vhci, so no need to try page83
14368 14513 */
14369 14514 if (sd_inq && (sd_inq->inq_dtype == DTYPE_RODIRECT ||
14370 14515 sd_inq->inq_dtype == DTYPE_OPTICAL ||
14371 14516 sd_inq->inq_dtype == DTYPE_ESI))
14372 14517 goto create_lun;
14373 14518
14374 14519 /*
14375 14520 * The LCA returns good SCSI status, but corrupt page 83 data the first
14376 14521 * time it is queried. The solution is to keep trying to request page83
14377 14522 * and verify the GUID is not (DDI_NOT_WELL_FORMED) in
14378 14523 * mptsas_inq83_retry_timeout seconds. If the timeout expires, driver
14379 14524 * give up to get VPD page at this stage and fail the enumeration.
14380 14525 */
14381 14526
14382 14527 inq83 = kmem_zalloc(inq83_len1, KM_SLEEP);
14383 14528
14384 14529 for (i = 0; i < mptsas_inq83_retry_timeout; i++) {
14385 14530 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83,
14386 14531 inq83_len1, &inq83_len, 1);
14387 14532 if (rval != 0) {
14388 14533 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
14389 14534 "0x83 for target:%x, lun:%x failed!", target, lun);
14390 14535 if (mptsas_physical_bind_failed_page_83 != B_FALSE)
14391 14536 goto create_lun;
14392 14537 goto out;
14393 14538 }
14394 14539 /*
14395 14540 * create DEVID from inquiry data
14396 14541 */
14397 14542 if ((rval = ddi_devid_scsi_encode(
14398 14543 DEVID_SCSI_ENCODE_VERSION_LATEST, NULL, (uchar_t *)sd_inq,
14399 14544 sizeof (struct scsi_inquiry), NULL, 0, inq83,
14400 14545 (size_t)inq83_len, &devid)) == DDI_SUCCESS) {
14401 14546 /*
14402 14547 * extract GUID from DEVID
14403 14548 */
14404 14549 guid = ddi_devid_to_guid(devid);
14405 14550
14406 14551 /*
14407 14552 * Do not enable MPXIO if the strlen(guid) is greater
14408 14553 * than MPTSAS_MAX_GUID_LEN, this constrain would be
14409 14554 * handled by framework later.
14410 14555 */
14411 14556 if (guid && (strlen(guid) > MPTSAS_MAX_GUID_LEN)) {
14412 14557 ddi_devid_free_guid(guid);
14413 14558 guid = NULL;
14414 14559 if (mpt->m_mpxio_enable == TRUE) {
14415 14560 mptsas_log(mpt, CE_NOTE, "!Target:%x, "
14416 14561 "lun:%x doesn't have a valid GUID, "
14417 14562 "multipathing for this drive is "
14418 14563 "not enabled", target, lun);
14419 14564 }
14420 14565 }
14421 14566
14422 14567 /*
14423 14568 * devid no longer needed
14424 14569 */
14425 14570 ddi_devid_free(devid);
14426 14571 break;
14427 14572 } else if (rval == DDI_NOT_WELL_FORMED) {
14428 14573 /*
14429 14574 * return value of ddi_devid_scsi_encode equal to
14430 14575 * DDI_NOT_WELL_FORMED means DEVID_RETRY, it worth
14431 14576 * to retry inquiry page 0x83 and get GUID.
14432 14577 */
14433 14578 NDBG20(("Not well formed devid, retry..."));
14434 14579 delay(1 * drv_usectohz(1000000));
14435 14580 continue;
14436 14581 } else {
14437 14582 mptsas_log(mpt, CE_WARN, "!Encode devid failed for "
14438 14583 "path target:%x, lun:%x", target, lun);
14439 14584 rval = DDI_FAILURE;
14440 14585 goto create_lun;
14441 14586 }
14442 14587 }
14443 14588
14444 14589 if (i == mptsas_inq83_retry_timeout) {
14445 14590 mptsas_log(mpt, CE_WARN, "!Repeated page83 requests timeout "
14446 14591 "for path target:%x, lun:%x", target, lun);
14447 14592 }
14448 14593
14449 14594 rval = DDI_FAILURE;
14450 14595
14451 14596 create_lun:
14452 14597 if ((guid != NULL) && (mpt->m_mpxio_enable == TRUE)) {
14453 14598 rval = mptsas_create_virt_lun(pdip, sd_inq, guid, lun_dip, &pip,
14454 14599 ptgt, lun);
14455 14600 }
14456 14601 if (rval != DDI_SUCCESS) {
14457 14602 rval = mptsas_create_phys_lun(pdip, sd_inq, guid, lun_dip,
14458 14603 ptgt, lun);
14459 14604
14460 14605 }
14461 14606 out:
14462 14607 if (guid != NULL) {
14463 14608 /*
14464 14609 * guid no longer needed
14465 14610 */
14466 14611 ddi_devid_free_guid(guid);
14467 14612 }
14468 14613 if (inq83 != NULL)
14469 14614 kmem_free(inq83, inq83_len1);
14470 14615 return (rval);
14471 14616 }
14472 14617
14473 14618 static int
14474 14619 mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *inq, char *guid,
14475 14620 dev_info_t **lun_dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, int lun)
14476 14621 {
14477 14622 int target;
14478 14623 char *nodename = NULL;
14479 14624 char **compatible = NULL;
14480 14625 int ncompatible = 0;
14481 14626 int mdi_rtn = MDI_FAILURE;
14482 14627 int rval = DDI_FAILURE;
14483 14628 char *old_guid = NULL;
14484 14629 mptsas_t *mpt = DIP2MPT(pdip);
14485 14630 char *lun_addr = NULL;
14486 14631 char *wwn_str = NULL;
14487 14632 char *attached_wwn_str = NULL;
14488 14633 char *component = NULL;
14489 14634 uint8_t phy = 0xFF;
14490 14635 uint64_t sas_wwn;
14491 14636 int64_t lun64 = 0;
14492 14637 uint32_t devinfo;
14493 14638 uint16_t dev_hdl;
14494 14639 uint16_t pdev_hdl;
14495 14640 uint64_t dev_sas_wwn;
14496 14641 uint64_t pdev_sas_wwn;
14497 14642 uint32_t pdev_info;
14498 14643 uint8_t physport;
14499 14644 uint8_t phy_id;
14500 14645 uint32_t page_address;
14501 14646 uint16_t bay_num, enclosure;
14502 14647 char pdev_wwn_str[MPTSAS_WWN_STRLEN];
14503 14648 uint32_t dev_info;
14504 14649
14505 14650 mutex_enter(&mpt->m_mutex);
14506 14651 target = ptgt->m_devhdl;
14507 14652 sas_wwn = ptgt->m_sas_wwn;
14508 14653 devinfo = ptgt->m_deviceinfo;
14509 14654 phy = ptgt->m_phynum;
14510 14655 mutex_exit(&mpt->m_mutex);
14511 14656
14512 14657 if (sas_wwn) {
14513 14658 *pip = mptsas_find_path_addr(pdip, sas_wwn, lun);
14514 14659 } else {
14515 14660 *pip = mptsas_find_path_phy(pdip, phy);
14516 14661 }
14517 14662
14518 14663 if (*pip != NULL) {
14519 14664 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip;
14520 14665 ASSERT(*lun_dip != NULL);
14521 14666 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, *lun_dip,
14522 14667 (DDI_PROP_DONTPASS | DDI_PROP_NOTPROM),
14523 14668 MDI_CLIENT_GUID_PROP, &old_guid) == DDI_SUCCESS) {
↓ open down ↓ |
2440 lines elided |
↑ open up ↑ |
14524 14669 if (strncmp(guid, old_guid, strlen(guid)) == 0) {
14525 14670 /*
14526 14671 * Same path back online again.
14527 14672 */
14528 14673 (void) ddi_prop_free(old_guid);
14529 14674 if ((!MDI_PI_IS_ONLINE(*pip)) &&
14530 14675 (!MDI_PI_IS_STANDBY(*pip)) &&
14531 14676 (ptgt->m_tgt_unconfigured == 0)) {
14532 14677 rval = mdi_pi_online(*pip, 0);
14533 14678 mutex_enter(&mpt->m_mutex);
14534 - (void) mptsas_set_led_status(mpt, ptgt,
14535 - 0);
14679 + ptgt->m_led_status = 0;
14680 + (void) mptsas_flush_led_status(mpt,
14681 + ptgt);
14536 14682 mutex_exit(&mpt->m_mutex);
14537 14683 } else {
14538 14684 rval = DDI_SUCCESS;
14539 14685 }
14540 14686 if (rval != DDI_SUCCESS) {
14541 14687 mptsas_log(mpt, CE_WARN, "path:target: "
14542 14688 "%x, lun:%x online failed!", target,
14543 14689 lun);
14544 14690 *pip = NULL;
14545 14691 *lun_dip = NULL;
14546 14692 }
14547 14693 return (rval);
14548 14694 } else {
14549 14695 /*
14550 14696 * The GUID of the LUN has changed which maybe
14551 14697 * because customer mapped another volume to the
14552 14698 * same LUN.
14553 14699 */
14554 14700 mptsas_log(mpt, CE_WARN, "The GUID of the "
14555 14701 "target:%x, lun:%x was changed, maybe "
14556 14702 "because someone mapped another volume "
14557 14703 "to the same LUN", target, lun);
14558 14704 (void) ddi_prop_free(old_guid);
14559 14705 if (!MDI_PI_IS_OFFLINE(*pip)) {
14560 14706 rval = mdi_pi_offline(*pip, 0);
14561 14707 if (rval != MDI_SUCCESS) {
14562 14708 mptsas_log(mpt, CE_WARN, "path:"
14563 14709 "target:%x, lun:%x offline "
14564 14710 "failed!", target, lun);
14565 14711 *pip = NULL;
14566 14712 *lun_dip = NULL;
14567 14713 return (DDI_FAILURE);
14568 14714 }
14569 14715 }
14570 14716 if (mdi_pi_free(*pip, 0) != MDI_SUCCESS) {
14571 14717 mptsas_log(mpt, CE_WARN, "path:target:"
14572 14718 "%x, lun:%x free failed!", target,
14573 14719 lun);
14574 14720 *pip = NULL;
14575 14721 *lun_dip = NULL;
14576 14722 return (DDI_FAILURE);
14577 14723 }
14578 14724 }
14579 14725 } else {
14580 14726 mptsas_log(mpt, CE_WARN, "Can't get client-guid "
14581 14727 "property for path:target:%x, lun:%x", target, lun);
14582 14728 *pip = NULL;
14583 14729 *lun_dip = NULL;
14584 14730 return (DDI_FAILURE);
14585 14731 }
14586 14732 }
14587 14733 scsi_hba_nodename_compatible_get(inq, NULL,
14588 14734 inq->inq_dtype, NULL, &nodename, &compatible, &ncompatible);
14589 14735
14590 14736 /*
14591 14737 * if nodename can't be determined then print a message and skip it
14592 14738 */
14593 14739 if (nodename == NULL) {
14594 14740 mptsas_log(mpt, CE_WARN, "mptsas driver found no compatible "
14595 14741 "driver for target%d lun %d dtype:0x%02x", target, lun,
14596 14742 inq->inq_dtype);
14597 14743 return (DDI_FAILURE);
14598 14744 }
14599 14745
14600 14746 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP);
14601 14747 /* The property is needed by MPAPI */
14602 14748 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn);
14603 14749
14604 14750 lun_addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14605 14751 if (guid) {
14606 14752 (void) sprintf(lun_addr, "w%s,%x", wwn_str, lun);
14607 14753 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
14608 14754 } else {
14609 14755 (void) sprintf(lun_addr, "p%x,%x", phy, lun);
14610 14756 (void) sprintf(wwn_str, "p%x", phy);
14611 14757 }
14612 14758
14613 14759 mdi_rtn = mdi_pi_alloc_compatible(pdip, nodename,
14614 14760 guid, lun_addr, compatible, ncompatible,
14615 14761 0, pip);
14616 14762 if (mdi_rtn == MDI_SUCCESS) {
14617 14763
14618 14764 if (mdi_prop_update_string(*pip, MDI_GUID,
14619 14765 guid) != DDI_SUCCESS) {
14620 14766 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14621 14767 "create prop for target %d lun %d (MDI_GUID)",
14622 14768 target, lun);
14623 14769 mdi_rtn = MDI_FAILURE;
14624 14770 goto virt_create_done;
14625 14771 }
14626 14772
14627 14773 if (mdi_prop_update_int(*pip, LUN_PROP,
14628 14774 lun) != DDI_SUCCESS) {
14629 14775 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14630 14776 "create prop for target %d lun %d (LUN_PROP)",
14631 14777 target, lun);
14632 14778 mdi_rtn = MDI_FAILURE;
14633 14779 goto virt_create_done;
14634 14780 }
14635 14781 lun64 = (int64_t)lun;
14636 14782 if (mdi_prop_update_int64(*pip, LUN64_PROP,
14637 14783 lun64) != DDI_SUCCESS) {
14638 14784 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14639 14785 "create prop for target %d (LUN64_PROP)",
14640 14786 target);
14641 14787 mdi_rtn = MDI_FAILURE;
14642 14788 goto virt_create_done;
14643 14789 }
14644 14790 if (mdi_prop_update_string_array(*pip, "compatible",
14645 14791 compatible, ncompatible) !=
14646 14792 DDI_PROP_SUCCESS) {
14647 14793 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14648 14794 "create prop for target %d lun %d (COMPATIBLE)",
14649 14795 target, lun);
14650 14796 mdi_rtn = MDI_FAILURE;
14651 14797 goto virt_create_done;
14652 14798 }
14653 14799 if (sas_wwn && (mdi_prop_update_string(*pip,
14654 14800 SCSI_ADDR_PROP_TARGET_PORT, wwn_str) != DDI_PROP_SUCCESS)) {
14655 14801 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14656 14802 "create prop for target %d lun %d "
14657 14803 "(target-port)", target, lun);
14658 14804 mdi_rtn = MDI_FAILURE;
14659 14805 goto virt_create_done;
14660 14806 } else if ((sas_wwn == 0) && (mdi_prop_update_int(*pip,
14661 14807 "sata-phy", phy) != DDI_PROP_SUCCESS)) {
14662 14808 /*
14663 14809 * Direct attached SATA device without DeviceName
14664 14810 */
14665 14811 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14666 14812 "create prop for SAS target %d lun %d "
14667 14813 "(sata-phy)", target, lun);
14668 14814 mdi_rtn = MDI_FAILURE;
14669 14815 goto virt_create_done;
14670 14816 }
14671 14817 mutex_enter(&mpt->m_mutex);
14672 14818
14673 14819 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14674 14820 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
14675 14821 (uint32_t)ptgt->m_devhdl;
14676 14822 rval = mptsas_get_sas_device_page0(mpt, page_address,
14677 14823 &dev_hdl, &dev_sas_wwn, &dev_info, &physport,
14678 14824 &phy_id, &pdev_hdl, &bay_num, &enclosure);
14679 14825 if (rval != DDI_SUCCESS) {
14680 14826 mutex_exit(&mpt->m_mutex);
14681 14827 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
14682 14828 "parent device for handle %d", page_address);
14683 14829 mdi_rtn = MDI_FAILURE;
14684 14830 goto virt_create_done;
14685 14831 }
14686 14832
14687 14833 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14688 14834 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl;
14689 14835 rval = mptsas_get_sas_device_page0(mpt, page_address,
14690 14836 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport,
14691 14837 &phy_id, &pdev_hdl, &bay_num, &enclosure);
14692 14838 if (rval != DDI_SUCCESS) {
14693 14839 mutex_exit(&mpt->m_mutex);
14694 14840 mptsas_log(mpt, CE_WARN, "mptsas unable to get"
14695 14841 "device info for handle %d", page_address);
14696 14842 mdi_rtn = MDI_FAILURE;
14697 14843 goto virt_create_done;
14698 14844 }
14699 14845
14700 14846 mutex_exit(&mpt->m_mutex);
14701 14847
14702 14848 /*
14703 14849 * If this device direct attached to the controller
14704 14850 * set the attached-port to the base wwid
14705 14851 */
14706 14852 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
14707 14853 != DEVINFO_DIRECT_ATTACHED) {
14708 14854 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
14709 14855 pdev_sas_wwn);
14710 14856 } else {
14711 14857 /*
14712 14858 * Update the iport's attached-port to guid
14713 14859 */
14714 14860 if (sas_wwn == 0) {
14715 14861 (void) sprintf(wwn_str, "p%x", phy);
14716 14862 } else {
14717 14863 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
14718 14864 }
14719 14865 if (ddi_prop_update_string(DDI_DEV_T_NONE,
14720 14866 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
14721 14867 DDI_PROP_SUCCESS) {
14722 14868 mptsas_log(mpt, CE_WARN,
14723 14869 "mptsas unable to create "
14724 14870 "property for iport target-port"
14725 14871 " %s (sas_wwn)",
14726 14872 wwn_str);
14727 14873 mdi_rtn = MDI_FAILURE;
14728 14874 goto virt_create_done;
14729 14875 }
14730 14876
14731 14877 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
14732 14878 mpt->un.m_base_wwid);
14733 14879 }
14734 14880
14735 14881 if (mdi_prop_update_string(*pip,
14736 14882 SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) !=
14737 14883 DDI_PROP_SUCCESS) {
14738 14884 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14739 14885 "property for iport attached-port %s (sas_wwn)",
14740 14886 attached_wwn_str);
14741 14887 mdi_rtn = MDI_FAILURE;
14742 14888 goto virt_create_done;
14743 14889 }
14744 14890
14745 14891
14746 14892 if (inq->inq_dtype == 0) {
14747 14893 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP);
14748 14894 /*
14749 14895 * set obp path for pathinfo
14750 14896 */
14751 14897 (void) snprintf(component, MAXPATHLEN,
14752 14898 "disk@%s", lun_addr);
14753 14899
14754 14900 if (mdi_pi_pathname_obp_set(*pip, component) !=
14755 14901 DDI_SUCCESS) {
14756 14902 mptsas_log(mpt, CE_WARN, "mpt_sas driver "
14757 14903 "unable to set obp-path for object %s",
14758 14904 component);
14759 14905 mdi_rtn = MDI_FAILURE;
14760 14906 goto virt_create_done;
14761 14907 }
14762 14908 }
14763 14909
14764 14910 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip;
14765 14911 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
14766 14912 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
14767 14913 if ((ndi_prop_update_int(DDI_DEV_T_NONE, *lun_dip,
14768 14914 "pm-capable", 1)) !=
14769 14915 DDI_PROP_SUCCESS) {
14770 14916 mptsas_log(mpt, CE_WARN, "mptsas driver"
14771 14917 "failed to create pm-capable "
14772 14918 "property, target %d", target);
14773 14919 mdi_rtn = MDI_FAILURE;
14774 14920 goto virt_create_done;
14775 14921 }
14776 14922 }
14777 14923 /*
14778 14924 * Create the phy-num property
14779 14925 */
14780 14926 if (mdi_prop_update_int(*pip, "phy-num",
14781 14927 ptgt->m_phynum) != DDI_SUCCESS) {
↓ open down ↓ |
236 lines elided |
↑ open up ↑ |
14782 14928 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14783 14929 "create phy-num property for target %d lun %d",
14784 14930 target, lun);
14785 14931 mdi_rtn = MDI_FAILURE;
14786 14932 goto virt_create_done;
14787 14933 }
14788 14934 NDBG20(("new path:%s onlining,", MDI_PI(*pip)->pi_addr));
14789 14935 mdi_rtn = mdi_pi_online(*pip, 0);
14790 14936 if (mdi_rtn == MDI_SUCCESS) {
14791 14937 mutex_enter(&mpt->m_mutex);
14792 - if (mptsas_set_led_status(mpt, ptgt, 0) !=
14793 - DDI_SUCCESS) {
14938 + ptgt->m_led_status = 0;
14939 + if (mptsas_flush_led_status(mpt, ptgt) != DDI_SUCCESS) {
14794 14940 NDBG14(("mptsas: clear LED for slot %x "
14795 14941 "failed", ptgt->m_slot_num));
14796 14942 }
14797 14943 mutex_exit(&mpt->m_mutex);
14798 14944 }
14799 14945 if (mdi_rtn == MDI_NOT_SUPPORTED) {
14800 14946 mdi_rtn = MDI_FAILURE;
14801 14947 }
14802 14948 virt_create_done:
14803 14949 if (*pip && mdi_rtn != MDI_SUCCESS) {
14804 14950 (void) mdi_pi_free(*pip, 0);
14805 14951 *pip = NULL;
14806 14952 *lun_dip = NULL;
14807 14953 }
14808 14954 }
14809 14955
14810 14956 scsi_hba_nodename_compatible_free(nodename, compatible);
14811 14957 if (lun_addr != NULL) {
14812 14958 kmem_free(lun_addr, SCSI_MAXNAMELEN);
14813 14959 }
14814 14960 if (wwn_str != NULL) {
14815 14961 kmem_free(wwn_str, MPTSAS_WWN_STRLEN);
14816 14962 }
14817 14963 if (component != NULL) {
14818 14964 kmem_free(component, MAXPATHLEN);
14819 14965 }
14820 14966
14821 14967 return ((mdi_rtn == MDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
14822 14968 }
14823 14969
14824 14970 static int
14825 14971 mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *inq,
14826 14972 char *guid, dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun)
14827 14973 {
14828 14974 int target;
14829 14975 int rval;
14830 14976 int ndi_rtn = NDI_FAILURE;
14831 14977 uint64_t be_sas_wwn;
14832 14978 char *nodename = NULL;
14833 14979 char **compatible = NULL;
14834 14980 int ncompatible = 0;
14835 14981 int instance = 0;
14836 14982 mptsas_t *mpt = DIP2MPT(pdip);
14837 14983 char *wwn_str = NULL;
14838 14984 char *component = NULL;
14839 14985 char *attached_wwn_str = NULL;
14840 14986 uint8_t phy = 0xFF;
14841 14987 uint64_t sas_wwn;
14842 14988 uint32_t devinfo;
14843 14989 uint16_t dev_hdl;
14844 14990 uint16_t pdev_hdl;
14845 14991 uint64_t pdev_sas_wwn;
14846 14992 uint64_t dev_sas_wwn;
14847 14993 uint32_t pdev_info;
14848 14994 uint8_t physport;
14849 14995 uint8_t phy_id;
14850 14996 uint32_t page_address;
14851 14997 uint16_t bay_num, enclosure;
14852 14998 char pdev_wwn_str[MPTSAS_WWN_STRLEN];
14853 14999 uint32_t dev_info;
14854 15000 int64_t lun64 = 0;
14855 15001
14856 15002 mutex_enter(&mpt->m_mutex);
14857 15003 target = ptgt->m_devhdl;
14858 15004 sas_wwn = ptgt->m_sas_wwn;
14859 15005 devinfo = ptgt->m_deviceinfo;
14860 15006 phy = ptgt->m_phynum;
14861 15007 mutex_exit(&mpt->m_mutex);
14862 15008
14863 15009 /*
14864 15010 * generate compatible property with binding-set "mpt"
14865 15011 */
14866 15012 scsi_hba_nodename_compatible_get(inq, NULL, inq->inq_dtype, NULL,
14867 15013 &nodename, &compatible, &ncompatible);
14868 15014
14869 15015 /*
14870 15016 * if nodename can't be determined then print a message and skip it
14871 15017 */
14872 15018 if (nodename == NULL) {
14873 15019 mptsas_log(mpt, CE_WARN, "mptsas found no compatible driver "
14874 15020 "for target %d lun %d", target, lun);
14875 15021 return (DDI_FAILURE);
14876 15022 }
14877 15023
14878 15024 ndi_rtn = ndi_devi_alloc(pdip, nodename,
14879 15025 DEVI_SID_NODEID, lun_dip);
14880 15026
14881 15027 /*
14882 15028 * if lun alloc success, set props
14883 15029 */
14884 15030 if (ndi_rtn == NDI_SUCCESS) {
14885 15031
14886 15032 if (ndi_prop_update_int(DDI_DEV_T_NONE,
14887 15033 *lun_dip, LUN_PROP, lun) !=
14888 15034 DDI_PROP_SUCCESS) {
14889 15035 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14890 15036 "property for target %d lun %d (LUN_PROP)",
14891 15037 target, lun);
14892 15038 ndi_rtn = NDI_FAILURE;
14893 15039 goto phys_create_done;
14894 15040 }
14895 15041
14896 15042 lun64 = (int64_t)lun;
14897 15043 if (ndi_prop_update_int64(DDI_DEV_T_NONE,
14898 15044 *lun_dip, LUN64_PROP, lun64) !=
14899 15045 DDI_PROP_SUCCESS) {
14900 15046 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14901 15047 "property for target %d lun64 %d (LUN64_PROP)",
14902 15048 target, lun);
14903 15049 ndi_rtn = NDI_FAILURE;
14904 15050 goto phys_create_done;
14905 15051 }
14906 15052 if (ndi_prop_update_string_array(DDI_DEV_T_NONE,
14907 15053 *lun_dip, "compatible", compatible, ncompatible)
14908 15054 != DDI_PROP_SUCCESS) {
14909 15055 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14910 15056 "property for target %d lun %d (COMPATIBLE)",
14911 15057 target, lun);
14912 15058 ndi_rtn = NDI_FAILURE;
14913 15059 goto phys_create_done;
14914 15060 }
14915 15061
14916 15062 /*
14917 15063 * We need the SAS WWN for non-multipath devices, so
14918 15064 * we'll use the same property as that multipathing
14919 15065 * devices need to present for MPAPI. If we don't have
14920 15066 * a WWN (e.g. parallel SCSI), don't create the prop.
14921 15067 */
14922 15068 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP);
14923 15069 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
14924 15070 if (sas_wwn && ndi_prop_update_string(DDI_DEV_T_NONE,
14925 15071 *lun_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str)
14926 15072 != DDI_PROP_SUCCESS) {
14927 15073 mptsas_log(mpt, CE_WARN, "mptsas unable to "
14928 15074 "create property for SAS target %d lun %d "
14929 15075 "(target-port)", target, lun);
14930 15076 ndi_rtn = NDI_FAILURE;
14931 15077 goto phys_create_done;
14932 15078 }
14933 15079
14934 15080 be_sas_wwn = BE_64(sas_wwn);
14935 15081 if (sas_wwn && ndi_prop_update_byte_array(
14936 15082 DDI_DEV_T_NONE, *lun_dip, "port-wwn",
14937 15083 (uchar_t *)&be_sas_wwn, 8) != DDI_PROP_SUCCESS) {
14938 15084 mptsas_log(mpt, CE_WARN, "mptsas unable to "
14939 15085 "create property for SAS target %d lun %d "
14940 15086 "(port-wwn)", target, lun);
14941 15087 ndi_rtn = NDI_FAILURE;
14942 15088 goto phys_create_done;
14943 15089 } else if ((sas_wwn == 0) && (ndi_prop_update_int(
14944 15090 DDI_DEV_T_NONE, *lun_dip, "sata-phy", phy) !=
14945 15091 DDI_PROP_SUCCESS)) {
14946 15092 /*
14947 15093 * Direct attached SATA device without DeviceName
14948 15094 */
14949 15095 mptsas_log(mpt, CE_WARN, "mptsas unable to "
14950 15096 "create property for SAS target %d lun %d "
14951 15097 "(sata-phy)", target, lun);
14952 15098 ndi_rtn = NDI_FAILURE;
14953 15099 goto phys_create_done;
14954 15100 }
14955 15101
14956 15102 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
14957 15103 *lun_dip, SAS_PROP) != DDI_PROP_SUCCESS) {
14958 15104 mptsas_log(mpt, CE_WARN, "mptsas unable to"
14959 15105 "create property for SAS target %d lun %d"
14960 15106 " (SAS_PROP)", target, lun);
14961 15107 ndi_rtn = NDI_FAILURE;
14962 15108 goto phys_create_done;
14963 15109 }
14964 15110 if (guid && (ndi_prop_update_string(DDI_DEV_T_NONE,
14965 15111 *lun_dip, NDI_GUID, guid) != DDI_SUCCESS)) {
14966 15112 mptsas_log(mpt, CE_WARN, "mptsas unable "
14967 15113 "to create guid property for target %d "
14968 15114 "lun %d", target, lun);
14969 15115 ndi_rtn = NDI_FAILURE;
14970 15116 goto phys_create_done;
14971 15117 }
14972 15118
14973 15119 /*
14974 15120 * The following code is to set properties for SM-HBA support,
14975 15121 * it doesn't apply to RAID volumes
14976 15122 */
14977 15123 if (ptgt->m_phymask == 0)
14978 15124 goto phys_raid_lun;
14979 15125
14980 15126 mutex_enter(&mpt->m_mutex);
14981 15127
14982 15128 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14983 15129 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
14984 15130 (uint32_t)ptgt->m_devhdl;
14985 15131 rval = mptsas_get_sas_device_page0(mpt, page_address,
14986 15132 &dev_hdl, &dev_sas_wwn, &dev_info,
14987 15133 &physport, &phy_id, &pdev_hdl,
14988 15134 &bay_num, &enclosure);
14989 15135 if (rval != DDI_SUCCESS) {
14990 15136 mutex_exit(&mpt->m_mutex);
14991 15137 mptsas_log(mpt, CE_WARN, "mptsas unable to get"
14992 15138 "parent device for handle %d.", page_address);
14993 15139 ndi_rtn = NDI_FAILURE;
14994 15140 goto phys_create_done;
14995 15141 }
14996 15142
14997 15143 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14998 15144 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl;
14999 15145 rval = mptsas_get_sas_device_page0(mpt, page_address,
15000 15146 &dev_hdl, &pdev_sas_wwn, &pdev_info,
15001 15147 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure);
15002 15148 if (rval != DDI_SUCCESS) {
15003 15149 mutex_exit(&mpt->m_mutex);
15004 15150 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15005 15151 "device for handle %d.", page_address);
15006 15152 ndi_rtn = NDI_FAILURE;
15007 15153 goto phys_create_done;
15008 15154 }
15009 15155
15010 15156 mutex_exit(&mpt->m_mutex);
15011 15157
15012 15158 /*
15013 15159 * If this device direct attached to the controller
15014 15160 * set the attached-port to the base wwid
15015 15161 */
15016 15162 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
15017 15163 != DEVINFO_DIRECT_ATTACHED) {
15018 15164 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
15019 15165 pdev_sas_wwn);
15020 15166 } else {
15021 15167 /*
15022 15168 * Update the iport's attached-port to guid
15023 15169 */
15024 15170 if (sas_wwn == 0) {
15025 15171 (void) sprintf(wwn_str, "p%x", phy);
15026 15172 } else {
15027 15173 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
15028 15174 }
15029 15175 if (ddi_prop_update_string(DDI_DEV_T_NONE,
15030 15176 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
15031 15177 DDI_PROP_SUCCESS) {
15032 15178 mptsas_log(mpt, CE_WARN,
15033 15179 "mptsas unable to create "
15034 15180 "property for iport target-port"
15035 15181 " %s (sas_wwn)",
15036 15182 wwn_str);
15037 15183 ndi_rtn = NDI_FAILURE;
15038 15184 goto phys_create_done;
15039 15185 }
15040 15186
15041 15187 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
15042 15188 mpt->un.m_base_wwid);
15043 15189 }
15044 15190
15045 15191 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15046 15192 *lun_dip, SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) !=
15047 15193 DDI_PROP_SUCCESS) {
15048 15194 mptsas_log(mpt, CE_WARN,
15049 15195 "mptsas unable to create "
15050 15196 "property for iport attached-port %s (sas_wwn)",
15051 15197 attached_wwn_str);
15052 15198 ndi_rtn = NDI_FAILURE;
15053 15199 goto phys_create_done;
15054 15200 }
15055 15201
15056 15202 if (IS_SATA_DEVICE(dev_info)) {
15057 15203 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15058 15204 *lun_dip, MPTSAS_VARIANT, "sata") !=
15059 15205 DDI_PROP_SUCCESS) {
15060 15206 mptsas_log(mpt, CE_WARN,
15061 15207 "mptsas unable to create "
15062 15208 "property for device variant ");
15063 15209 ndi_rtn = NDI_FAILURE;
15064 15210 goto phys_create_done;
15065 15211 }
15066 15212 }
15067 15213
15068 15214 if (IS_ATAPI_DEVICE(dev_info)) {
15069 15215 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15070 15216 *lun_dip, MPTSAS_VARIANT, "atapi") !=
15071 15217 DDI_PROP_SUCCESS) {
15072 15218 mptsas_log(mpt, CE_WARN,
15073 15219 "mptsas unable to create "
15074 15220 "property for device variant ");
15075 15221 ndi_rtn = NDI_FAILURE;
15076 15222 goto phys_create_done;
15077 15223 }
15078 15224 }
15079 15225
15080 15226 phys_raid_lun:
15081 15227 /*
15082 15228 * if this is a SAS controller, and the target is a SATA
15083 15229 * drive, set the 'pm-capable' property for sd and if on
15084 15230 * an OPL platform, also check if this is an ATAPI
15085 15231 * device.
15086 15232 */
15087 15233 instance = ddi_get_instance(mpt->m_dip);
15088 15234 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
15089 15235 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
15090 15236 NDBG2(("mptsas%d: creating pm-capable property, "
15091 15237 "target %d", instance, target));
15092 15238
15093 15239 if ((ndi_prop_update_int(DDI_DEV_T_NONE,
15094 15240 *lun_dip, "pm-capable", 1)) !=
15095 15241 DDI_PROP_SUCCESS) {
15096 15242 mptsas_log(mpt, CE_WARN, "mptsas "
15097 15243 "failed to create pm-capable "
15098 15244 "property, target %d", target);
15099 15245 ndi_rtn = NDI_FAILURE;
15100 15246 goto phys_create_done;
15101 15247 }
15102 15248
15103 15249 }
15104 15250
15105 15251 if ((inq->inq_dtype == 0) || (inq->inq_dtype == 5)) {
15106 15252 /*
15107 15253 * add 'obp-path' properties for devinfo
15108 15254 */
15109 15255 bzero(wwn_str, sizeof (wwn_str));
15110 15256 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn);
15111 15257 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP);
15112 15258 if (guid) {
15113 15259 (void) snprintf(component, MAXPATHLEN,
15114 15260 "disk@w%s,%x", wwn_str, lun);
15115 15261 } else {
15116 15262 (void) snprintf(component, MAXPATHLEN,
15117 15263 "disk@p%x,%x", phy, lun);
15118 15264 }
15119 15265 if (ddi_pathname_obp_set(*lun_dip, component)
15120 15266 != DDI_SUCCESS) {
15121 15267 mptsas_log(mpt, CE_WARN, "mpt_sas driver "
15122 15268 "unable to set obp-path for SAS "
15123 15269 "object %s", component);
15124 15270 ndi_rtn = NDI_FAILURE;
15125 15271 goto phys_create_done;
15126 15272 }
15127 15273 }
15128 15274 /*
15129 15275 * Create the phy-num property for non-raid disk
15130 15276 */
15131 15277 if (ptgt->m_phymask != 0) {
15132 15278 if (ndi_prop_update_int(DDI_DEV_T_NONE,
15133 15279 *lun_dip, "phy-num", ptgt->m_phynum) !=
15134 15280 DDI_PROP_SUCCESS) {
15135 15281 mptsas_log(mpt, CE_WARN, "mptsas driver "
15136 15282 "failed to create phy-num property for "
15137 15283 "target %d", target);
15138 15284 ndi_rtn = NDI_FAILURE;
15139 15285 goto phys_create_done;
15140 15286 }
15141 15287 }
15142 15288 phys_create_done:
15143 15289 /*
↓ open down ↓ |
340 lines elided |
↑ open up ↑ |
15144 15290 * If props were setup ok, online the lun
15145 15291 */
15146 15292 if (ndi_rtn == NDI_SUCCESS) {
15147 15293 /*
15148 15294 * Try to online the new node
15149 15295 */
15150 15296 ndi_rtn = ndi_devi_online(*lun_dip, NDI_ONLINE_ATTACH);
15151 15297 }
15152 15298 if (ndi_rtn == NDI_SUCCESS) {
15153 15299 mutex_enter(&mpt->m_mutex);
15154 - if (mptsas_set_led_status(mpt, ptgt, 0) !=
15155 - DDI_SUCCESS) {
15300 + ptgt->m_led_status = 0;
15301 + if (mptsas_flush_led_status(mpt, ptgt) != DDI_SUCCESS) {
15156 15302 NDBG14(("mptsas: clear LED for tgt %x "
15157 15303 "failed", ptgt->m_slot_num));
15158 15304 }
15159 15305 mutex_exit(&mpt->m_mutex);
15160 15306 }
15161 15307
15162 15308 /*
15163 15309 * If success set rtn flag, else unwire alloc'd lun
15164 15310 */
15165 15311 if (ndi_rtn != NDI_SUCCESS) {
15166 15312 NDBG12(("mptsas driver unable to online "
15167 15313 "target %d lun %d", target, lun));
15168 15314 ndi_prop_remove_all(*lun_dip);
15169 15315 (void) ndi_devi_free(*lun_dip);
15170 15316 *lun_dip = NULL;
15171 15317 }
15172 15318 }
15173 15319
15174 15320 scsi_hba_nodename_compatible_free(nodename, compatible);
15175 15321
15176 15322 if (wwn_str != NULL) {
15177 15323 kmem_free(wwn_str, MPTSAS_WWN_STRLEN);
15178 15324 }
15179 15325 if (component != NULL) {
15180 15326 kmem_free(component, MAXPATHLEN);
15181 15327 }
15182 15328
15183 15329
15184 15330 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
15185 15331 }
15186 15332
15187 15333 static int
15188 15334 mptsas_probe_smp(dev_info_t *pdip, uint64_t wwn)
15189 15335 {
15190 15336 mptsas_t *mpt = DIP2MPT(pdip);
15191 15337 struct smp_device smp_sd;
15192 15338
15193 15339 /* XXX An HBA driver should not be allocating an smp_device. */
15194 15340 bzero(&smp_sd, sizeof (struct smp_device));
15195 15341 smp_sd.smp_sd_address.smp_a_hba_tran = mpt->m_smptran;
15196 15342 bcopy(&wwn, smp_sd.smp_sd_address.smp_a_wwn, SAS_WWN_BYTE_SIZE);
15197 15343
15198 15344 if (smp_probe(&smp_sd) != DDI_PROBE_SUCCESS)
15199 15345 return (NDI_FAILURE);
15200 15346 return (NDI_SUCCESS);
15201 15347 }
15202 15348
15203 15349 static int
15204 15350 mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, dev_info_t **smp_dip)
15205 15351 {
15206 15352 mptsas_t *mpt = DIP2MPT(pdip);
15207 15353 mptsas_smp_t *psmp = NULL;
15208 15354 int rval;
15209 15355 int phymask;
15210 15356
15211 15357 /*
15212 15358 * Get the physical port associated to the iport
15213 15359 * PHYMASK TODO
15214 15360 */
15215 15361 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
15216 15362 "phymask", 0);
15217 15363 /*
15218 15364 * Find the smp node in hash table with specified sas address and
15219 15365 * physical port
15220 15366 */
15221 15367 psmp = mptsas_wwid_to_psmp(mpt, phymask, sas_wwn);
15222 15368 if (psmp == NULL) {
15223 15369 return (DDI_FAILURE);
15224 15370 }
15225 15371
15226 15372 rval = mptsas_online_smp(pdip, psmp, smp_dip);
15227 15373
15228 15374 return (rval);
15229 15375 }
15230 15376
15231 15377 static int
15232 15378 mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
15233 15379 dev_info_t **smp_dip)
15234 15380 {
15235 15381 char wwn_str[MPTSAS_WWN_STRLEN];
15236 15382 char attached_wwn_str[MPTSAS_WWN_STRLEN];
15237 15383 int ndi_rtn = NDI_FAILURE;
15238 15384 int rval = 0;
15239 15385 mptsas_smp_t dev_info;
15240 15386 uint32_t page_address;
15241 15387 mptsas_t *mpt = DIP2MPT(pdip);
15242 15388 uint16_t dev_hdl;
15243 15389 uint64_t sas_wwn;
15244 15390 uint64_t smp_sas_wwn;
15245 15391 uint8_t physport;
15246 15392 uint8_t phy_id;
15247 15393 uint16_t pdev_hdl;
15248 15394 uint8_t numphys = 0;
15249 15395 uint16_t i = 0;
15250 15396 char phymask[MPTSAS_MAX_PHYS];
15251 15397 char *iport = NULL;
15252 15398 mptsas_phymask_t phy_mask = 0;
15253 15399 uint16_t attached_devhdl;
15254 15400 uint16_t bay_num, enclosure;
15255 15401
15256 15402 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_sasaddr);
15257 15403
15258 15404 /*
15259 15405 * Probe smp device, prevent the node of removed device from being
15260 15406 * configured succesfully
15261 15407 */
15262 15408 if (mptsas_probe_smp(pdip, smp_node->m_sasaddr) != NDI_SUCCESS) {
15263 15409 return (DDI_FAILURE);
15264 15410 }
15265 15411
15266 15412 if ((*smp_dip = mptsas_find_smp_child(pdip, wwn_str)) != NULL) {
15267 15413 return (DDI_SUCCESS);
15268 15414 }
15269 15415
15270 15416 ndi_rtn = ndi_devi_alloc(pdip, "smp", DEVI_SID_NODEID, smp_dip);
15271 15417
15272 15418 /*
15273 15419 * if lun alloc success, set props
15274 15420 */
15275 15421 if (ndi_rtn == NDI_SUCCESS) {
15276 15422 /*
15277 15423 * Set the flavor of the child to be SMP flavored
15278 15424 */
15279 15425 ndi_flavor_set(*smp_dip, SCSA_FLAVOR_SMP);
15280 15426
15281 15427 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15282 15428 *smp_dip, SMP_WWN, wwn_str) !=
15283 15429 DDI_PROP_SUCCESS) {
15284 15430 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15285 15431 "property for smp device %s (sas_wwn)",
15286 15432 wwn_str);
15287 15433 ndi_rtn = NDI_FAILURE;
15288 15434 goto smp_create_done;
15289 15435 }
15290 15436 (void) sprintf(wwn_str, "w%"PRIx64, smp_node->m_sasaddr);
15291 15437 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15292 15438 *smp_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str) !=
15293 15439 DDI_PROP_SUCCESS) {
15294 15440 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15295 15441 "property for iport target-port %s (sas_wwn)",
15296 15442 wwn_str);
15297 15443 ndi_rtn = NDI_FAILURE;
15298 15444 goto smp_create_done;
15299 15445 }
15300 15446
15301 15447 mutex_enter(&mpt->m_mutex);
15302 15448
15303 15449 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL &
15304 15450 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | smp_node->m_devhdl;
15305 15451 rval = mptsas_get_sas_expander_page0(mpt, page_address,
15306 15452 &dev_info);
15307 15453 if (rval != DDI_SUCCESS) {
15308 15454 mutex_exit(&mpt->m_mutex);
15309 15455 mptsas_log(mpt, CE_WARN,
15310 15456 "mptsas unable to get expander "
15311 15457 "parent device info for %x", page_address);
15312 15458 ndi_rtn = NDI_FAILURE;
15313 15459 goto smp_create_done;
15314 15460 }
15315 15461
15316 15462 smp_node->m_pdevhdl = dev_info.m_pdevhdl;
15317 15463 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15318 15464 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
15319 15465 (uint32_t)dev_info.m_pdevhdl;
15320 15466 rval = mptsas_get_sas_device_page0(mpt, page_address,
15321 15467 &dev_hdl, &sas_wwn, &smp_node->m_pdevinfo,
15322 15468 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure);
15323 15469 if (rval != DDI_SUCCESS) {
15324 15470 mutex_exit(&mpt->m_mutex);
15325 15471 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
15326 15472 "device info for %x", page_address);
15327 15473 ndi_rtn = NDI_FAILURE;
15328 15474 goto smp_create_done;
15329 15475 }
15330 15476
15331 15477 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15332 15478 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
15333 15479 (uint32_t)dev_info.m_devhdl;
15334 15480 rval = mptsas_get_sas_device_page0(mpt, page_address,
15335 15481 &dev_hdl, &smp_sas_wwn, &smp_node->m_deviceinfo,
15336 15482 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure);
15337 15483 if (rval != DDI_SUCCESS) {
15338 15484 mutex_exit(&mpt->m_mutex);
15339 15485 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
15340 15486 "device info for %x", page_address);
15341 15487 ndi_rtn = NDI_FAILURE;
15342 15488 goto smp_create_done;
15343 15489 }
15344 15490 mutex_exit(&mpt->m_mutex);
15345 15491
15346 15492 /*
15347 15493 * If this smp direct attached to the controller
15348 15494 * set the attached-port to the base wwid
15349 15495 */
15350 15496 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
15351 15497 != DEVINFO_DIRECT_ATTACHED) {
15352 15498 (void) sprintf(attached_wwn_str, "w%016"PRIx64,
15353 15499 sas_wwn);
15354 15500 } else {
15355 15501 (void) sprintf(attached_wwn_str, "w%016"PRIx64,
15356 15502 mpt->un.m_base_wwid);
15357 15503 }
15358 15504
15359 15505 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15360 15506 *smp_dip, SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwn_str) !=
15361 15507 DDI_PROP_SUCCESS) {
15362 15508 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15363 15509 "property for smp attached-port %s (sas_wwn)",
15364 15510 attached_wwn_str);
15365 15511 ndi_rtn = NDI_FAILURE;
15366 15512 goto smp_create_done;
15367 15513 }
15368 15514
15369 15515 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
15370 15516 *smp_dip, SMP_PROP) != DDI_PROP_SUCCESS) {
15371 15517 mptsas_log(mpt, CE_WARN, "mptsas unable to "
15372 15518 "create property for SMP %s (SMP_PROP) ",
15373 15519 wwn_str);
15374 15520 ndi_rtn = NDI_FAILURE;
15375 15521 goto smp_create_done;
15376 15522 }
15377 15523
15378 15524 /*
15379 15525 * check the smp to see whether it direct
15380 15526 * attached to the controller
15381 15527 */
15382 15528 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
15383 15529 != DEVINFO_DIRECT_ATTACHED) {
15384 15530 goto smp_create_done;
15385 15531 }
15386 15532 numphys = ddi_prop_get_int(DDI_DEV_T_ANY, pdip,
15387 15533 DDI_PROP_DONTPASS, MPTSAS_NUM_PHYS, -1);
15388 15534 if (numphys > 0) {
15389 15535 goto smp_create_done;
15390 15536 }
15391 15537 /*
15392 15538 * this iport is an old iport, we need to
15393 15539 * reconfig the props for it.
15394 15540 */
15395 15541 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip,
15396 15542 MPTSAS_VIRTUAL_PORT, 0) !=
15397 15543 DDI_PROP_SUCCESS) {
15398 15544 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
15399 15545 MPTSAS_VIRTUAL_PORT);
15400 15546 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
15401 15547 "prop update failed");
15402 15548 goto smp_create_done;
15403 15549 }
15404 15550
15405 15551 mutex_enter(&mpt->m_mutex);
15406 15552 numphys = 0;
15407 15553 iport = ddi_get_name_addr(pdip);
15408 15554 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
15409 15555 bzero(phymask, sizeof (phymask));
15410 15556 (void) sprintf(phymask,
15411 15557 "%x", mpt->m_phy_info[i].phy_mask);
15412 15558 if (strcmp(phymask, iport) == 0) {
15413 15559 phy_mask = mpt->m_phy_info[i].phy_mask;
15414 15560 break;
15415 15561 }
15416 15562 }
15417 15563
15418 15564 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
15419 15565 if ((phy_mask >> i) & 0x01) {
15420 15566 numphys++;
15421 15567 }
15422 15568 }
15423 15569 /*
15424 15570 * Update PHY info for smhba
15425 15571 */
15426 15572 if (mptsas_smhba_phy_init(mpt)) {
15427 15573 mutex_exit(&mpt->m_mutex);
15428 15574 mptsas_log(mpt, CE_WARN, "mptsas phy update "
15429 15575 "failed");
15430 15576 goto smp_create_done;
15431 15577 }
15432 15578 mutex_exit(&mpt->m_mutex);
15433 15579
15434 15580 mptsas_smhba_set_phy_props(mpt, iport, pdip,
15435 15581 numphys, &attached_devhdl);
15436 15582
15437 15583 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip,
15438 15584 MPTSAS_NUM_PHYS, numphys) !=
15439 15585 DDI_PROP_SUCCESS) {
15440 15586 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
15441 15587 MPTSAS_NUM_PHYS);
15442 15588 mptsas_log(mpt, CE_WARN, "mptsas update "
15443 15589 "num phys props failed");
15444 15590 goto smp_create_done;
15445 15591 }
15446 15592 /*
15447 15593 * Add parent's props for SMHBA support
15448 15594 */
15449 15595 if (ddi_prop_update_string(DDI_DEV_T_NONE, pdip,
15450 15596 SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
15451 15597 DDI_PROP_SUCCESS) {
15452 15598 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
15453 15599 SCSI_ADDR_PROP_ATTACHED_PORT);
15454 15600 mptsas_log(mpt, CE_WARN, "mptsas update iport"
15455 15601 "attached-port failed");
15456 15602 goto smp_create_done;
15457 15603 }
15458 15604
15459 15605 smp_create_done:
15460 15606 /*
15461 15607 * If props were setup ok, online the lun
15462 15608 */
15463 15609 if (ndi_rtn == NDI_SUCCESS) {
15464 15610 /*
15465 15611 * Try to online the new node
15466 15612 */
15467 15613 ndi_rtn = ndi_devi_online(*smp_dip, NDI_ONLINE_ATTACH);
15468 15614 }
15469 15615
15470 15616 /*
15471 15617 * If success set rtn flag, else unwire alloc'd lun
15472 15618 */
15473 15619 if (ndi_rtn != NDI_SUCCESS) {
15474 15620 NDBG12(("mptsas unable to online "
15475 15621 "SMP target %s", wwn_str));
15476 15622 ndi_prop_remove_all(*smp_dip);
15477 15623 (void) ndi_devi_free(*smp_dip);
15478 15624 }
15479 15625 }
15480 15626
15481 15627 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
15482 15628 }
15483 15629
15484 15630 /* smp transport routine */
15485 15631 static int mptsas_smp_start(struct smp_pkt *smp_pkt)
15486 15632 {
15487 15633 uint64_t wwn;
15488 15634 Mpi2SmpPassthroughRequest_t req;
15489 15635 Mpi2SmpPassthroughReply_t rep;
15490 15636 uint32_t direction = 0;
15491 15637 mptsas_t *mpt;
15492 15638 int ret;
15493 15639 uint64_t tmp64;
15494 15640
15495 15641 mpt = (mptsas_t *)smp_pkt->smp_pkt_address->
15496 15642 smp_a_hba_tran->smp_tran_hba_private;
15497 15643
15498 15644 bcopy(smp_pkt->smp_pkt_address->smp_a_wwn, &wwn, SAS_WWN_BYTE_SIZE);
15499 15645 /*
15500 15646 * Need to compose a SMP request message
15501 15647 * and call mptsas_do_passthru() function
15502 15648 */
15503 15649 bzero(&req, sizeof (req));
15504 15650 bzero(&rep, sizeof (rep));
15505 15651 req.PassthroughFlags = 0;
15506 15652 req.PhysicalPort = 0xff;
15507 15653 req.ChainOffset = 0;
15508 15654 req.Function = MPI2_FUNCTION_SMP_PASSTHROUGH;
15509 15655
15510 15656 if ((smp_pkt->smp_pkt_reqsize & 0xffff0000ul) != 0) {
15511 15657 smp_pkt->smp_pkt_reason = ERANGE;
15512 15658 return (DDI_FAILURE);
15513 15659 }
15514 15660 req.RequestDataLength = LE_16((uint16_t)(smp_pkt->smp_pkt_reqsize - 4));
15515 15661
15516 15662 req.MsgFlags = 0;
15517 15663 tmp64 = LE_64(wwn);
15518 15664 bcopy(&tmp64, &req.SASAddress, SAS_WWN_BYTE_SIZE);
15519 15665 if (smp_pkt->smp_pkt_rspsize > 0) {
15520 15666 direction |= MPTSAS_PASS_THRU_DIRECTION_READ;
15521 15667 }
15522 15668 if (smp_pkt->smp_pkt_reqsize > 0) {
15523 15669 direction |= MPTSAS_PASS_THRU_DIRECTION_WRITE;
15524 15670 }
15525 15671
15526 15672 mutex_enter(&mpt->m_mutex);
15527 15673 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep,
15528 15674 (uint8_t *)smp_pkt->smp_pkt_rsp,
15529 15675 offsetof(Mpi2SmpPassthroughRequest_t, SGL), sizeof (rep),
15530 15676 smp_pkt->smp_pkt_rspsize - 4, direction,
15531 15677 (uint8_t *)smp_pkt->smp_pkt_req, smp_pkt->smp_pkt_reqsize - 4,
15532 15678 smp_pkt->smp_pkt_timeout, FKIOCTL);
15533 15679 mutex_exit(&mpt->m_mutex);
15534 15680 if (ret != 0) {
15535 15681 cmn_err(CE_WARN, "smp_start do passthru error %d", ret);
15536 15682 smp_pkt->smp_pkt_reason = (uchar_t)(ret);
15537 15683 return (DDI_FAILURE);
15538 15684 }
15539 15685 /* do passthrough success, check the smp status */
15540 15686 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
15541 15687 switch (LE_16(rep.IOCStatus)) {
15542 15688 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
15543 15689 smp_pkt->smp_pkt_reason = ENODEV;
15544 15690 break;
15545 15691 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
15546 15692 smp_pkt->smp_pkt_reason = EOVERFLOW;
15547 15693 break;
15548 15694 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
15549 15695 smp_pkt->smp_pkt_reason = EIO;
15550 15696 break;
15551 15697 default:
15552 15698 mptsas_log(mpt, CE_NOTE, "smp_start: get unknown ioc"
15553 15699 "status:%x", LE_16(rep.IOCStatus));
15554 15700 smp_pkt->smp_pkt_reason = EIO;
15555 15701 break;
15556 15702 }
15557 15703 return (DDI_FAILURE);
15558 15704 }
15559 15705 if (rep.SASStatus != MPI2_SASSTATUS_SUCCESS) {
15560 15706 mptsas_log(mpt, CE_NOTE, "smp_start: get error SAS status:%x",
15561 15707 rep.SASStatus);
15562 15708 smp_pkt->smp_pkt_reason = EIO;
15563 15709 return (DDI_FAILURE);
15564 15710 }
15565 15711
15566 15712 return (DDI_SUCCESS);
15567 15713 }
15568 15714
15569 15715 /*
15570 15716 * If we didn't get a match, we need to get sas page0 for each device, and
15571 15717 * untill we get a match. If failed, return NULL
15572 15718 */
15573 15719 static mptsas_target_t *
15574 15720 mptsas_phy_to_tgt(mptsas_t *mpt, int phymask, uint8_t phy)
15575 15721 {
15576 15722 int i, j = 0;
15577 15723 int rval = 0;
15578 15724 uint16_t cur_handle;
15579 15725 uint32_t page_address;
15580 15726 mptsas_target_t *ptgt = NULL;
15581 15727
15582 15728 /*
15583 15729 * PHY named device must be direct attached and attaches to
15584 15730 * narrow port, if the iport is not parent of the device which
15585 15731 * we are looking for.
15586 15732 */
15587 15733 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
15588 15734 if ((1 << i) & phymask)
15589 15735 j++;
15590 15736 }
15591 15737
15592 15738 if (j > 1)
15593 15739 return (NULL);
15594 15740
15595 15741 /*
15596 15742 * Must be a narrow port and single device attached to the narrow port
15597 15743 * So the physical port num of device which is equal to the iport's
15598 15744 * port num is the device what we are looking for.
15599 15745 */
15600 15746
15601 15747 if (mpt->m_phy_info[phy].phy_mask != phymask)
15602 15748 return (NULL);
15603 15749
15604 15750 mutex_enter(&mpt->m_mutex);
15605 15751
15606 15752 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
15607 15753 MPTSAS_HASH_FIRST);
15608 15754 while (ptgt != NULL) {
15609 15755 if ((ptgt->m_sas_wwn == 0) && (ptgt->m_phynum == phy)) {
15610 15756 mutex_exit(&mpt->m_mutex);
15611 15757 return (ptgt);
15612 15758 }
15613 15759
15614 15760 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
15615 15761 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
15616 15762 }
15617 15763
15618 15764 if (mpt->m_done_traverse_dev) {
15619 15765 mutex_exit(&mpt->m_mutex);
15620 15766 return (NULL);
15621 15767 }
15622 15768
15623 15769 /* If didn't get a match, come here */
15624 15770 cur_handle = mpt->m_dev_handle;
15625 15771 for (; ; ) {
15626 15772 ptgt = NULL;
15627 15773 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
15628 15774 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)cur_handle;
15629 15775 rval = mptsas_get_target_device_info(mpt, page_address,
15630 15776 &cur_handle, &ptgt);
15631 15777 if ((rval == DEV_INFO_FAIL_PAGE0) ||
15632 15778 (rval == DEV_INFO_FAIL_ALLOC)) {
15633 15779 break;
15634 15780 }
15635 15781 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) ||
15636 15782 (rval == DEV_INFO_PHYS_DISK)) {
15637 15783 continue;
15638 15784 }
15639 15785 mpt->m_dev_handle = cur_handle;
15640 15786
15641 15787 if ((ptgt->m_sas_wwn == 0) && (ptgt->m_phynum == phy)) {
15642 15788 break;
15643 15789 }
15644 15790 }
15645 15791
15646 15792 mutex_exit(&mpt->m_mutex);
15647 15793 return (ptgt);
15648 15794 }
15649 15795
15650 15796 /*
15651 15797 * The ptgt->m_sas_wwn contains the wwid for each disk.
15652 15798 * For Raid volumes, we need to check m_raidvol[x].m_raidwwid
15653 15799 * If we didn't get a match, we need to get sas page0 for each device, and
15654 15800 * untill we get a match
15655 15801 * If failed, return NULL
15656 15802 */
15657 15803 static mptsas_target_t *
15658 15804 mptsas_wwid_to_ptgt(mptsas_t *mpt, int phymask, uint64_t wwid)
15659 15805 {
15660 15806 int rval = 0;
15661 15807 uint16_t cur_handle;
15662 15808 uint32_t page_address;
15663 15809 mptsas_target_t *tmp_tgt = NULL;
15664 15810
15665 15811 mutex_enter(&mpt->m_mutex);
15666 15812 tmp_tgt = (struct mptsas_target *)mptsas_hash_search(
15667 15813 &mpt->m_active->m_tgttbl, wwid, phymask);
15668 15814 if (tmp_tgt != NULL) {
15669 15815 mutex_exit(&mpt->m_mutex);
15670 15816 return (tmp_tgt);
15671 15817 }
15672 15818
15673 15819 if (phymask == 0) {
15674 15820 /*
15675 15821 * It's IR volume
15676 15822 */
15677 15823 rval = mptsas_get_raid_info(mpt);
15678 15824 if (rval) {
15679 15825 tmp_tgt = (struct mptsas_target *)mptsas_hash_search(
15680 15826 &mpt->m_active->m_tgttbl, wwid, phymask);
15681 15827 }
15682 15828 mutex_exit(&mpt->m_mutex);
15683 15829 return (tmp_tgt);
15684 15830 }
15685 15831
15686 15832 if (mpt->m_done_traverse_dev) {
15687 15833 mutex_exit(&mpt->m_mutex);
15688 15834 return (NULL);
15689 15835 }
15690 15836
15691 15837 /* If didn't get a match, come here */
15692 15838 cur_handle = mpt->m_dev_handle;
15693 15839 for (; ; ) {
15694 15840 tmp_tgt = NULL;
15695 15841 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
15696 15842 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | cur_handle;
15697 15843 rval = mptsas_get_target_device_info(mpt, page_address,
15698 15844 &cur_handle, &tmp_tgt);
15699 15845 if ((rval == DEV_INFO_FAIL_PAGE0) ||
15700 15846 (rval == DEV_INFO_FAIL_ALLOC)) {
15701 15847 tmp_tgt = NULL;
15702 15848 break;
15703 15849 }
15704 15850 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) ||
15705 15851 (rval == DEV_INFO_PHYS_DISK)) {
15706 15852 continue;
15707 15853 }
15708 15854 mpt->m_dev_handle = cur_handle;
15709 15855 if ((tmp_tgt->m_sas_wwn) && (tmp_tgt->m_sas_wwn == wwid) &&
15710 15856 (tmp_tgt->m_phymask == phymask)) {
15711 15857 break;
15712 15858 }
15713 15859 }
15714 15860
15715 15861 mutex_exit(&mpt->m_mutex);
15716 15862 return (tmp_tgt);
15717 15863 }
15718 15864
15719 15865 static mptsas_smp_t *
15720 15866 mptsas_wwid_to_psmp(mptsas_t *mpt, int phymask, uint64_t wwid)
15721 15867 {
15722 15868 int rval = 0;
15723 15869 uint16_t cur_handle;
15724 15870 uint32_t page_address;
15725 15871 mptsas_smp_t smp_node, *psmp = NULL;
15726 15872
15727 15873 mutex_enter(&mpt->m_mutex);
15728 15874 psmp = (struct mptsas_smp *)mptsas_hash_search(&mpt->m_active->m_smptbl,
15729 15875 wwid, phymask);
15730 15876 if (psmp != NULL) {
15731 15877 mutex_exit(&mpt->m_mutex);
15732 15878 return (psmp);
15733 15879 }
15734 15880
15735 15881 if (mpt->m_done_traverse_smp) {
15736 15882 mutex_exit(&mpt->m_mutex);
15737 15883 return (NULL);
15738 15884 }
15739 15885
15740 15886 /* If didn't get a match, come here */
15741 15887 cur_handle = mpt->m_smp_devhdl;
15742 15888 for (; ; ) {
15743 15889 psmp = NULL;
15744 15890 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL &
15745 15891 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)cur_handle;
15746 15892 rval = mptsas_get_sas_expander_page0(mpt, page_address,
15747 15893 &smp_node);
15748 15894 if (rval != DDI_SUCCESS) {
15749 15895 break;
15750 15896 }
15751 15897 mpt->m_smp_devhdl = cur_handle = smp_node.m_devhdl;
15752 15898 psmp = mptsas_smp_alloc(&mpt->m_active->m_smptbl, &smp_node);
15753 15899 ASSERT(psmp);
15754 15900 if ((psmp->m_sasaddr) && (psmp->m_sasaddr == wwid) &&
15755 15901 (psmp->m_phymask == phymask)) {
15756 15902 break;
15757 15903 }
15758 15904 }
15759 15905
15760 15906 mutex_exit(&mpt->m_mutex);
15761 15907 return (psmp);
15762 15908 }
15763 15909
15764 15910 /* helper functions using hash */
15765 15911
15766 15912 /*
15767 15913 * Can't have duplicate entries for same devhdl,
15768 15914 * if there are invalid entries, the devhdl should be set to 0xffff
15769 15915 */
15770 15916 static void *
15771 15917 mptsas_search_by_devhdl(mptsas_hash_table_t *hashtab, uint16_t devhdl)
15772 15918 {
15773 15919 mptsas_hash_data_t *data;
15774 15920
15775 15921 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_FIRST);
15776 15922 while (data != NULL) {
15777 15923 if (data->devhdl == devhdl) {
15778 15924 break;
15779 15925 }
15780 15926 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_NEXT);
15781 15927 }
15782 15928 return (data);
15783 15929 }
15784 15930
15785 15931 mptsas_target_t *
15786 15932 mptsas_tgt_alloc(mptsas_hash_table_t *hashtab, uint16_t devhdl, uint64_t wwid,
15787 15933 uint32_t devinfo, mptsas_phymask_t phymask, uint8_t phynum, mptsas_t *mpt)
15788 15934 {
15789 15935 mptsas_target_t *tmp_tgt = NULL;
15790 15936
15791 15937 tmp_tgt = mptsas_hash_search(hashtab, wwid, phymask);
15792 15938 if (tmp_tgt != NULL) {
15793 15939 NDBG20(("Hash item already exist"));
15794 15940 tmp_tgt->m_deviceinfo = devinfo;
15795 15941 tmp_tgt->m_devhdl = devhdl;
15796 15942 return (tmp_tgt);
15797 15943 }
15798 15944 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target), KM_SLEEP);
15799 15945 if (tmp_tgt == NULL) {
15800 15946 cmn_err(CE_WARN, "Fatal, allocated tgt failed");
15801 15947 return (NULL);
15802 15948 }
15803 15949 tmp_tgt->m_devhdl = devhdl;
15804 15950 tmp_tgt->m_sas_wwn = wwid;
15805 15951 tmp_tgt->m_deviceinfo = devinfo;
15806 15952 tmp_tgt->m_phymask = phymask;
15807 15953 tmp_tgt->m_phynum = phynum;
15808 15954 /* Initialized the tgt structure */
15809 15955 tmp_tgt->m_qfull_retries = QFULL_RETRIES;
15810 15956 tmp_tgt->m_qfull_retry_interval =
15811 15957 drv_usectohz(QFULL_RETRY_INTERVAL * 1000);
15812 15958 tmp_tgt->m_t_throttle = MAX_THROTTLE;
15813 15959 mutex_init(&tmp_tgt->m_tgt_intr_mutex, NULL, MUTEX_DRIVER,
15814 15960 DDI_INTR_PRI(mpt->m_intr_pri));
15815 15961
15816 15962 mptsas_hash_add(hashtab, tmp_tgt);
15817 15963
15818 15964 return (tmp_tgt);
15819 15965 }
15820 15966
15821 15967 static void
15822 15968 mptsas_tgt_free(mptsas_hash_table_t *hashtab, uint64_t wwid,
15823 15969 mptsas_phymask_t phymask)
15824 15970 {
15825 15971 mptsas_target_t *tmp_tgt;
15826 15972 tmp_tgt = mptsas_hash_rem(hashtab, wwid, phymask);
15827 15973 if (tmp_tgt == NULL) {
15828 15974 cmn_err(CE_WARN, "Tgt not found, nothing to free");
15829 15975 } else {
15830 15976 mutex_destroy(&tmp_tgt->m_tgt_intr_mutex);
15831 15977 kmem_free(tmp_tgt, sizeof (struct mptsas_target));
15832 15978 }
15833 15979 }
15834 15980
15835 15981 /*
15836 15982 * Return the entry in the hash table
15837 15983 */
15838 15984 static mptsas_smp_t *
15839 15985 mptsas_smp_alloc(mptsas_hash_table_t *hashtab, mptsas_smp_t *data)
15840 15986 {
15841 15987 uint64_t key1 = data->m_sasaddr;
15842 15988 mptsas_phymask_t key2 = data->m_phymask;
15843 15989 mptsas_smp_t *ret_data;
15844 15990
15845 15991 ret_data = mptsas_hash_search(hashtab, key1, key2);
15846 15992 if (ret_data != NULL) {
15847 15993 bcopy(data, ret_data, sizeof (mptsas_smp_t));
15848 15994 return (ret_data);
15849 15995 }
15850 15996
15851 15997 ret_data = kmem_alloc(sizeof (mptsas_smp_t), KM_SLEEP);
15852 15998 bcopy(data, ret_data, sizeof (mptsas_smp_t));
15853 15999 mptsas_hash_add(hashtab, ret_data);
15854 16000 return (ret_data);
15855 16001 }
15856 16002
15857 16003 static void
15858 16004 mptsas_smp_free(mptsas_hash_table_t *hashtab, uint64_t wwid,
15859 16005 mptsas_phymask_t phymask)
15860 16006 {
15861 16007 mptsas_smp_t *tmp_smp;
15862 16008 tmp_smp = mptsas_hash_rem(hashtab, wwid, phymask);
15863 16009 if (tmp_smp == NULL) {
15864 16010 cmn_err(CE_WARN, "Smp element not found, nothing to free");
15865 16011 } else {
15866 16012 kmem_free(tmp_smp, sizeof (struct mptsas_smp));
15867 16013 }
15868 16014 }
15869 16015
15870 16016 /*
15871 16017 * Hash operation functions
15872 16018 * key1 is the sas_wwn, key2 is the phymask
15873 16019 */
15874 16020 static void
15875 16021 mptsas_hash_init(mptsas_hash_table_t *hashtab)
15876 16022 {
15877 16023 if (hashtab == NULL) {
15878 16024 return;
15879 16025 }
15880 16026 bzero(hashtab->head, sizeof (mptsas_hash_node_t) *
15881 16027 MPTSAS_HASH_ARRAY_SIZE);
15882 16028 hashtab->cur = NULL;
15883 16029 hashtab->line = 0;
15884 16030 }
15885 16031
15886 16032 static void
15887 16033 mptsas_hash_uninit(mptsas_hash_table_t *hashtab, size_t datalen)
15888 16034 {
15889 16035 uint16_t line = 0;
15890 16036 mptsas_hash_node_t *cur = NULL, *last = NULL;
15891 16037
15892 16038 if (hashtab == NULL) {
15893 16039 return;
15894 16040 }
15895 16041 for (line = 0; line < MPTSAS_HASH_ARRAY_SIZE; line++) {
15896 16042 cur = hashtab->head[line];
15897 16043 while (cur != NULL) {
15898 16044 last = cur;
15899 16045 cur = cur->next;
15900 16046 kmem_free(last->data, datalen);
15901 16047 kmem_free(last, sizeof (mptsas_hash_node_t));
15902 16048 }
15903 16049 }
15904 16050 }
15905 16051
15906 16052 /*
15907 16053 * You must guarantee the element doesn't exist in the hash table
15908 16054 * before you call mptsas_hash_add()
15909 16055 */
15910 16056 static void
15911 16057 mptsas_hash_add(mptsas_hash_table_t *hashtab, void *data)
15912 16058 {
15913 16059 uint64_t key1 = ((mptsas_hash_data_t *)data)->key1;
15914 16060 mptsas_phymask_t key2 = ((mptsas_hash_data_t *)data)->key2;
15915 16061 mptsas_hash_node_t **head = NULL;
15916 16062 mptsas_hash_node_t *node = NULL;
15917 16063
15918 16064 if (hashtab == NULL) {
15919 16065 return;
15920 16066 }
15921 16067 ASSERT(mptsas_hash_search(hashtab, key1, key2) == NULL);
15922 16068 node = kmem_zalloc(sizeof (mptsas_hash_node_t), KM_NOSLEEP);
15923 16069 node->data = data;
15924 16070
15925 16071 head = &(hashtab->head[key1 % MPTSAS_HASH_ARRAY_SIZE]);
15926 16072 if (*head == NULL) {
15927 16073 *head = node;
15928 16074 } else {
15929 16075 node->next = *head;
15930 16076 *head = node;
15931 16077 }
15932 16078 }
15933 16079
15934 16080 static void *
15935 16081 mptsas_hash_rem(mptsas_hash_table_t *hashtab, uint64_t key1,
15936 16082 mptsas_phymask_t key2)
15937 16083 {
15938 16084 mptsas_hash_node_t **head = NULL;
15939 16085 mptsas_hash_node_t *last = NULL, *cur = NULL;
15940 16086 mptsas_hash_data_t *data;
15941 16087 if (hashtab == NULL) {
15942 16088 return (NULL);
15943 16089 }
15944 16090 head = &(hashtab->head[key1 % MPTSAS_HASH_ARRAY_SIZE]);
15945 16091 cur = *head;
15946 16092 while (cur != NULL) {
15947 16093 data = cur->data;
15948 16094 if ((data->key1 == key1) && (data->key2 == key2)) {
15949 16095 if (last == NULL) {
15950 16096 (*head) = cur->next;
15951 16097 } else {
15952 16098 last->next = cur->next;
15953 16099 }
15954 16100 kmem_free(cur, sizeof (mptsas_hash_node_t));
15955 16101 return (data);
15956 16102 } else {
15957 16103 last = cur;
15958 16104 cur = cur->next;
15959 16105 }
15960 16106 }
15961 16107 return (NULL);
15962 16108 }
15963 16109
15964 16110 static void *
15965 16111 mptsas_hash_search(mptsas_hash_table_t *hashtab, uint64_t key1,
15966 16112 mptsas_phymask_t key2)
15967 16113 {
15968 16114 mptsas_hash_node_t *cur = NULL;
15969 16115 mptsas_hash_data_t *data;
15970 16116 if (hashtab == NULL) {
15971 16117 return (NULL);
15972 16118 }
15973 16119 cur = hashtab->head[key1 % MPTSAS_HASH_ARRAY_SIZE];
15974 16120 while (cur != NULL) {
15975 16121 data = cur->data;
15976 16122 if ((data->key1 == key1) && (data->key2 == key2)) {
15977 16123 return (data);
15978 16124 } else {
15979 16125 cur = cur->next;
15980 16126 }
15981 16127 }
15982 16128 return (NULL);
15983 16129 }
15984 16130
15985 16131 static void *
15986 16132 mptsas_hash_traverse(mptsas_hash_table_t *hashtab, int pos)
15987 16133 {
15988 16134 mptsas_hash_node_t *this = NULL;
15989 16135
15990 16136 if (hashtab == NULL) {
15991 16137 return (NULL);
15992 16138 }
15993 16139
15994 16140 if (pos == MPTSAS_HASH_FIRST) {
15995 16141 hashtab->line = 0;
15996 16142 hashtab->cur = NULL;
15997 16143 this = hashtab->head[0];
15998 16144 } else {
15999 16145 if (hashtab->cur == NULL) {
16000 16146 return (NULL);
16001 16147 } else {
16002 16148 this = hashtab->cur->next;
16003 16149 }
16004 16150 }
16005 16151
16006 16152 while (this == NULL) {
16007 16153 hashtab->line++;
16008 16154 if (hashtab->line >= MPTSAS_HASH_ARRAY_SIZE) {
16009 16155 /* the traverse reaches the end */
16010 16156 hashtab->cur = NULL;
16011 16157 return (NULL);
16012 16158 } else {
16013 16159 this = hashtab->head[hashtab->line];
16014 16160 }
16015 16161 }
16016 16162 hashtab->cur = this;
16017 16163 return (this->data);
16018 16164 }
16019 16165
16020 16166 /*
16021 16167 * Functions for SGPIO LED support
16022 16168 */
16023 16169 static dev_info_t *
16024 16170 mptsas_get_dip_from_dev(dev_t dev, mptsas_phymask_t *phymask)
16025 16171 {
16026 16172 dev_info_t *dip;
16027 16173 int prop;
16028 16174 dip = e_ddi_hold_devi_by_dev(dev, 0);
16029 16175 if (dip == NULL)
16030 16176 return (dip);
16031 16177 prop = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
16032 16178 "phymask", 0);
16033 16179 *phymask = (mptsas_phymask_t)prop;
16034 16180 ddi_release_devi(dip);
16035 16181 return (dip);
16036 16182 }
16037 16183 static mptsas_target_t *
16038 16184 mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr, mptsas_phymask_t phymask)
16039 16185 {
16040 16186 uint8_t phynum;
16041 16187 uint64_t wwn;
16042 16188 int lun;
16043 16189 mptsas_target_t *ptgt = NULL;
16044 16190
16045 16191 if (mptsas_parse_address(addr, &wwn, &phynum, &lun) != DDI_SUCCESS) {
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16046 16192 return (NULL);
16047 16193 }
16048 16194 if (addr[0] == 'w') {
16049 16195 ptgt = mptsas_wwid_to_ptgt(mpt, (int)phymask, wwn);
16050 16196 } else {
16051 16197 ptgt = mptsas_phy_to_tgt(mpt, (int)phymask, phynum);
16052 16198 }
16053 16199 return (ptgt);
16054 16200 }
16055 16201
16056 -#ifdef MPTSAS_GET_LED
16057 16202 static int
16058 -mptsas_get_led_status(mptsas_t *mpt, mptsas_target_t *ptgt,
16059 - uint32_t *slotstatus)
16203 +mptsas_flush_led_status(mptsas_t *mpt, mptsas_target_t *ptgt)
16060 16204 {
16061 - return (mptsas_send_sep(mpt, ptgt, slotstatus,
16062 - MPI2_SEP_REQ_ACTION_READ_STATUS));
16063 -}
16064 -#endif
16065 -static int
16066 -mptsas_set_led_status(mptsas_t *mpt, mptsas_target_t *ptgt, uint32_t slotstatus)
16067 -{
16205 + uint32_t slotstatus = 0;
16206 +
16207 + /* Build an MPI2 Slot Status based on our view of the world */
16208 + if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_IDENT - 1)))
16209 + slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST;
16210 + if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_FAIL - 1)))
16211 + slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT;
16212 + if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1)))
16213 + slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE;
16214 +
16215 + /* Write it to the controller */
16068 16216 NDBG14(("mptsas_ioctl: set LED status %x for slot %x",
16069 16217 slotstatus, ptgt->m_slot_num));
16070 16218 return (mptsas_send_sep(mpt, ptgt, &slotstatus,
16071 16219 MPI2_SEP_REQ_ACTION_WRITE_STATUS));
16072 16220 }
16221 +
16073 16222 /*
16074 16223 * send sep request, use enclosure/slot addressing
16075 16224 */
16076 16225 static int mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt,
16077 16226 uint32_t *status, uint8_t act)
16078 16227 {
16079 16228 Mpi2SepRequest_t req;
16080 16229 Mpi2SepReply_t rep;
16081 16230 int ret;
16082 16231
16083 16232 ASSERT(mutex_owned(&mpt->m_mutex));
16084 16233
16085 16234 bzero(&req, sizeof (req));
16086 16235 bzero(&rep, sizeof (rep));
16087 16236
16088 16237 /* Do nothing for RAID volumes */
16089 16238 if (ptgt->m_phymask == 0) {
16090 16239 NDBG14(("mptsas_send_sep: Skip RAID volumes"));
16091 16240 return (DDI_FAILURE);
16092 16241 }
16093 16242
16094 16243 req.Function = MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR;
16095 16244 req.Action = act;
16096 16245 req.Flags = MPI2_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS;
16097 16246 req.EnclosureHandle = LE_16(ptgt->m_enclosure);
16098 16247 req.Slot = LE_16(ptgt->m_slot_num);
16099 16248 if (act == MPI2_SEP_REQ_ACTION_WRITE_STATUS) {
16100 16249 req.SlotStatus = LE_32(*status);
16101 16250 }
16102 16251 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL,
16103 16252 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL);
16104 16253 if (ret != 0) {
16105 16254 mptsas_log(mpt, CE_NOTE, "mptsas_send_sep: passthru SEP "
16106 16255 "Processor Request message error %d", ret);
16107 16256 return (DDI_FAILURE);
16108 16257 }
16109 16258 /* do passthrough success, check the ioc status */
16110 16259 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
16111 16260 if ((LE_16(rep.IOCStatus) & MPI2_IOCSTATUS_MASK) ==
16112 16261 MPI2_IOCSTATUS_INVALID_FIELD) {
16113 16262 mptsas_log(mpt, CE_NOTE, "send sep act %x: Not "
16114 16263 "supported action, loginfo %x", act,
16115 16264 LE_32(rep.IOCLogInfo));
16116 16265 return (DDI_FAILURE);
16117 16266 }
16118 16267 mptsas_log(mpt, CE_NOTE, "send_sep act %x: ioc "
16119 16268 "status:%x", act, LE_16(rep.IOCStatus));
16120 16269 return (DDI_FAILURE);
16121 16270 }
16122 16271 if (act != MPI2_SEP_REQ_ACTION_WRITE_STATUS) {
16123 16272 *status = LE_32(rep.SlotStatus);
16124 16273 }
16125 16274
16126 16275 return (DDI_SUCCESS);
16127 16276 }
16128 16277
16129 16278 int
16130 16279 mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr,
16131 16280 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp,
16132 16281 uint32_t alloc_size, ddi_dma_cookie_t *cookiep)
16133 16282 {
16134 16283 ddi_dma_cookie_t new_cookie;
16135 16284 size_t alloc_len;
16136 16285 uint_t ncookie;
16137 16286
16138 16287 if (cookiep == NULL)
16139 16288 cookiep = &new_cookie;
16140 16289
16141 16290 if (ddi_dma_alloc_handle(mpt->m_dip, &dma_attr, DDI_DMA_SLEEP,
16142 16291 NULL, dma_hdp) != DDI_SUCCESS) {
16143 16292 dma_hdp = NULL;
16144 16293 return (FALSE);
16145 16294 }
16146 16295
16147 16296 if (ddi_dma_mem_alloc(*dma_hdp, alloc_size, &mpt->m_dev_acc_attr,
16148 16297 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, dma_memp, &alloc_len,
16149 16298 acc_hdp) != DDI_SUCCESS) {
16150 16299 ddi_dma_free_handle(dma_hdp);
16151 16300 dma_hdp = NULL;
16152 16301 return (FALSE);
16153 16302 }
16154 16303
16155 16304 if (ddi_dma_addr_bind_handle(*dma_hdp, NULL, *dma_memp, alloc_len,
16156 16305 (DDI_DMA_RDWR | DDI_DMA_CONSISTENT), DDI_DMA_SLEEP, NULL,
16157 16306 cookiep, &ncookie) != DDI_DMA_MAPPED) {
16158 16307 (void) ddi_dma_mem_free(acc_hdp);
16159 16308 ddi_dma_free_handle(dma_hdp);
16160 16309 dma_hdp = NULL;
16161 16310 return (FALSE);
16162 16311 }
16163 16312
16164 16313 return (TRUE);
16165 16314 }
16166 16315
16167 16316 void
16168 16317 mptsas_dma_addr_destroy(ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp)
16169 16318 {
16170 16319 if (*dma_hdp == NULL)
16171 16320 return;
16172 16321
16173 16322 (void) ddi_dma_unbind_handle(*dma_hdp);
16174 16323 (void) ddi_dma_mem_free(acc_hdp);
16175 16324 ddi_dma_free_handle(dma_hdp);
16176 16325 dma_hdp = NULL;
16177 16326 }
16178 16327
16179 16328 static int
16180 16329 mptsas_outstanding_cmds_n(mptsas_t *mpt)
16181 16330 {
16182 16331 int n = 0, i;
16183 16332 for (i = 0; i < mpt->m_slot_freeq_pair_n; i++) {
16184 16333 mutex_enter(&mpt->m_slot_freeq_pairp[i].
16185 16334 m_slot_allocq.s.m_fq_mutex);
16186 16335 mutex_enter(&mpt->m_slot_freeq_pairp[i].
16187 16336 m_slot_releq.s.m_fq_mutex);
16188 16337 n += (mpt->m_slot_freeq_pairp[i].m_slot_allocq.s.m_fq_n_init -
16189 16338 mpt->m_slot_freeq_pairp[i].m_slot_allocq.s.m_fq_n -
16190 16339 mpt->m_slot_freeq_pairp[i].m_slot_releq.s.m_fq_n);
16191 16340 mutex_exit(&mpt->m_slot_freeq_pairp[i].
16192 16341 m_slot_releq.s.m_fq_mutex);
16193 16342 mutex_exit(&mpt->m_slot_freeq_pairp[i].
16194 16343 m_slot_allocq.s.m_fq_mutex);
16195 16344 }
16196 16345 if (mpt->m_max_requests - 2 < n)
16197 16346 panic("mptsas: free slot allocq and releq crazy");
16198 16347 return (n);
16199 16348 }
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