5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26 #include <sys/sysmacros.h>
27 #include <sys/stack.h>
28 #include <sys/cpuvar.h>
29 #include <sys/ivintr.h>
30 #include <sys/intreg.h>
31 #include <sys/membar.h>
32 #include <sys/kmem.h>
33 #include <sys/intr.h>
34 #include <sys/sunddi.h>
35 #include <sys/sunndi.h>
36 #include <sys/cmn_err.h>
37 #include <sys/privregs.h>
38 #include <sys/systm.h>
39 #include <sys/archsystm.h>
40 #include <sys/machsystm.h>
41 #include <sys/x_call.h>
42 #include <vm/seg_kp.h>
43 #include <sys/debug.h>
44 #include <sys/cyclic.h>
45 #include <sys/kdi_impl.h>
46 #include <sys/ddi_timer.h>
47
48 #include <sys/cpu_sgnblk_defs.h>
49
50 /* Global locks which protect the interrupt distribution lists */
51 static kmutex_t intr_dist_lock;
52 static kmutex_t intr_dist_cpu_lock;
53
54 /* Head of the interrupt distribution lists */
55 static struct intr_dist *intr_dist_head = NULL;
56 static struct intr_dist *intr_dist_whead = NULL;
57
58 static uint64_t siron_inum[DDI_IPL_10]; /* software interrupt numbers */
59 uint64_t *siron_cpu_inum = NULL;
60 uint64_t siron_poke_cpu_inum;
61 static int siron_cpu_setup(cpu_setup_t, int, void *);
62 extern uint_t softlevel1();
63
64 static uint64_t siron1_inum; /* backward compatibility */
65 uint64_t poke_cpu_inum;
66 uint_t poke_cpu_intr(caddr_t arg1, caddr_t arg2);
102 #define INTR_DEBUG(args) if (intr_dist_debug) cmn_err args
103
104 /*
105 * intr_init() - Interrupt initialization
106 * Initialize the system's interrupt vector table.
107 */
108 void
109 intr_init(cpu_t *cp)
110 {
111 int i;
112 extern uint_t softlevel1();
113
114 init_ivintr();
115 REGISTER_BBUS_INTR();
116
117 /*
118 * Register these software interrupts for ddi timer.
119 * Software interrupts up to the level 10 are supported.
120 */
121 for (i = DDI_IPL_1; i <= DDI_IPL_10; i++) {
122 siron_inum[i-1] = add_softintr(i, (softintrfunc)timer_softintr,
123 (caddr_t)(uintptr_t)(i), SOFTINT_ST);
124 }
125
126 siron1_inum = add_softintr(PIL_1, softlevel1, 0, SOFTINT_ST);
127 poke_cpu_inum = add_softintr(PIL_13, poke_cpu_intr, 0, SOFTINT_MT);
128 siron_poke_cpu_inum = add_softintr(PIL_13,
129 siron_poke_cpu_intr, 0, SOFTINT_MT);
130 cp->cpu_m.poke_cpu_outstanding = B_FALSE;
131
132 mutex_init(&intr_dist_lock, NULL, MUTEX_DEFAULT, NULL);
133 mutex_init(&intr_dist_cpu_lock, NULL, MUTEX_DEFAULT, NULL);
134
135 /*
136 * A soft interrupt may have been requested prior to the initialization
137 * of soft interrupts. Soft interrupts can't be dispatched until after
138 * init_intr(), so we have to wait until now before we can dispatch the
139 * pending soft interrupt (if any).
140 */
141 for (i = DDI_IPL_1; i <= DDI_IPL_10; i++) {
142 if (siron_pending[i-1]) {
|
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25 /*
26 * Copyright (c) 2013, Joyent, Inc. All rights reserved.
27 */
28
29 #include <sys/sysmacros.h>
30 #include <sys/stack.h>
31 #include <sys/cpuvar.h>
32 #include <sys/ivintr.h>
33 #include <sys/intreg.h>
34 #include <sys/membar.h>
35 #include <sys/kmem.h>
36 #include <sys/intr.h>
37 #include <sys/sunddi.h>
38 #include <sys/sunndi.h>
39 #include <sys/cmn_err.h>
40 #include <sys/privregs.h>
41 #include <sys/systm.h>
42 #include <sys/archsystm.h>
43 #include <sys/machsystm.h>
44 #include <sys/x_call.h>
45 #include <vm/seg_kp.h>
46 #include <sys/debug.h>
47 #include <sys/cyclic.h>
48 #include <sys/kdi_impl.h>
49 #include <sys/ddi_periodic.h>
50
51 #include <sys/cpu_sgnblk_defs.h>
52
53 /* Global locks which protect the interrupt distribution lists */
54 static kmutex_t intr_dist_lock;
55 static kmutex_t intr_dist_cpu_lock;
56
57 /* Head of the interrupt distribution lists */
58 static struct intr_dist *intr_dist_head = NULL;
59 static struct intr_dist *intr_dist_whead = NULL;
60
61 static uint64_t siron_inum[DDI_IPL_10]; /* software interrupt numbers */
62 uint64_t *siron_cpu_inum = NULL;
63 uint64_t siron_poke_cpu_inum;
64 static int siron_cpu_setup(cpu_setup_t, int, void *);
65 extern uint_t softlevel1();
66
67 static uint64_t siron1_inum; /* backward compatibility */
68 uint64_t poke_cpu_inum;
69 uint_t poke_cpu_intr(caddr_t arg1, caddr_t arg2);
105 #define INTR_DEBUG(args) if (intr_dist_debug) cmn_err args
106
107 /*
108 * intr_init() - Interrupt initialization
109 * Initialize the system's interrupt vector table.
110 */
111 void
112 intr_init(cpu_t *cp)
113 {
114 int i;
115 extern uint_t softlevel1();
116
117 init_ivintr();
118 REGISTER_BBUS_INTR();
119
120 /*
121 * Register these software interrupts for ddi timer.
122 * Software interrupts up to the level 10 are supported.
123 */
124 for (i = DDI_IPL_1; i <= DDI_IPL_10; i++) {
125 siron_inum[i - 1] = add_softintr(i,
126 (softintrfunc)ddi_periodic_softintr,
127 (caddr_t)(uintptr_t)(i), SOFTINT_ST);
128 }
129
130 siron1_inum = add_softintr(PIL_1, softlevel1, 0, SOFTINT_ST);
131 poke_cpu_inum = add_softintr(PIL_13, poke_cpu_intr, 0, SOFTINT_MT);
132 siron_poke_cpu_inum = add_softintr(PIL_13,
133 siron_poke_cpu_intr, 0, SOFTINT_MT);
134 cp->cpu_m.poke_cpu_outstanding = B_FALSE;
135
136 mutex_init(&intr_dist_lock, NULL, MUTEX_DEFAULT, NULL);
137 mutex_init(&intr_dist_cpu_lock, NULL, MUTEX_DEFAULT, NULL);
138
139 /*
140 * A soft interrupt may have been requested prior to the initialization
141 * of soft interrupts. Soft interrupts can't be dispatched until after
142 * init_intr(), so we have to wait until now before we can dispatch the
143 * pending soft interrupt (if any).
144 */
145 for (i = DDI_IPL_1; i <= DDI_IPL_10; i++) {
146 if (siron_pending[i-1]) {
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