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OS-1997 mpt_sas: expose LED controls to libtopo
Reviewed by: Keith Wesolowski <keith.wesolowski@joyent.com>
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--- old/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mptsas_var.h
+++ new/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mptsas_var.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
25 + * Copyright (c) 2013, Joyent, Inc. All rights reserved.
25 26 */
26 27
27 28 /*
28 29 * Copyright (c) 2000 to 2010, LSI Corporation.
29 30 * All rights reserved.
30 31 *
31 32 * Redistribution and use in source and binary forms of all code within
32 33 * this file that is exclusively owned by LSI, with or without
33 34 * modification, is permitted provided that, in addition to the CDDL 1.0
34 35 * License requirements, the following conditions are met:
35 36 *
36 37 * Neither the name of the author nor the names of its contributors may be
37 38 * used to endorse or promote products derived from this software without
38 39 * specific prior written permission.
39 40 *
40 41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
41 42 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
42 43 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
43 44 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
44 45 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
45 46 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
46 47 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
47 48 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
48 49 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
49 50 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
50 51 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
51 52 * DAMAGE.
52 53 */
53 54
54 55 #ifndef _SYS_SCSI_ADAPTERS_MPTVAR_H
55 56 #define _SYS_SCSI_ADAPTERS_MPTVAR_H
56 57
57 58 #include <sys/byteorder.h>
58 59 #include <sys/isa_defs.h>
59 60 #include <sys/sunmdi.h>
60 61 #include <sys/mdi_impldefs.h>
61 62 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h>
62 63 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h>
63 64 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h>
64 65
65 66 #ifdef __cplusplus
66 67 extern "C" {
67 68 #endif
68 69
69 70 /*
70 71 * Compile options
71 72 */
72 73 #ifdef DEBUG
73 74 #define MPTSAS_DEBUG /* turn on debugging code */
74 75 #endif /* DEBUG */
75 76
76 77 #define MPTSAS_INITIAL_SOFT_SPACE 4
77 78
78 79 #define MAX_MPI_PORTS 16
79 80
80 81 /*
81 82 * Note below macro definition and data type definition
82 83 * are used for phy mask handling, it should be changed
83 84 * simultaneously.
84 85 */
85 86 #define MPTSAS_MAX_PHYS 16
86 87 typedef uint16_t mptsas_phymask_t;
87 88
88 89 #define MPTSAS_INVALID_DEVHDL 0xffff
89 90 #define MPTSAS_SATA_GUID "sata-guid"
90 91
91 92 /*
92 93 * MPT HW defines
93 94 */
94 95 #define MPTSAS_MAX_DISKS_IN_CONFIG 14
95 96 #define MPTSAS_MAX_DISKS_IN_VOL 10
96 97 #define MPTSAS_MAX_HOTSPARES 2
97 98 #define MPTSAS_MAX_RAIDVOLS 2
98 99 #define MPTSAS_MAX_RAIDCONFIGS 5
99 100
100 101 /*
101 102 * 64-bit SAS WWN is displayed as 16 characters as HEX characters,
102 103 * plus two means the prefix 'w' and end of the string '\0'.
103 104 */
104 105 #define MPTSAS_WWN_STRLEN (16 + 2)
105 106 #define MPTSAS_MAX_GUID_LEN 64
106 107
107 108 /*
108 109 * DMA routine flags
109 110 */
110 111 #define MPTSAS_DMA_HANDLE_ALLOCD 0x2
111 112 #define MPTSAS_DMA_MEMORY_ALLOCD 0x4
112 113 #define MPTSAS_DMA_HANDLE_BOUND 0x8
113 114
114 115 /*
115 116 * If the HBA supports DMA or bus-mastering, you may have your own
116 117 * scatter-gather list for physically non-contiguous memory in one
117 118 * I/O operation; if so, there's probably a size for that list.
118 119 * It must be placed in the ddi_dma_lim_t structure, so that the system
119 120 * DMA-support routines can use it to break up the I/O request, so we
120 121 * define it here.
121 122 */
122 123 #if defined(__sparc)
123 124 #define MPTSAS_MAX_DMA_SEGS 1
124 125 #define MPTSAS_MAX_CMD_SEGS 1
125 126 #else
126 127 #define MPTSAS_MAX_DMA_SEGS 256
127 128 #define MPTSAS_MAX_CMD_SEGS 257
128 129 #endif
129 130 #define MPTSAS_MAX_FRAME_SGES(mpt) \
130 131 (((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1)
131 132
132 133 /*
133 134 * Caculating how many 64-bit DMA simple elements can be stored in the first
134 135 * frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for
135 136 * element storage. And 64-bit dma element is 3 double-words (12 bytes) in
136 137 * size.
137 138 */
138 139 #define MPTSAS_MAX_FRAME_SGES64(mpt) \
139 140 ((mpt->m_req_frame_size - \
140 141 (sizeof (MPI2_SCSI_IO_REQUEST)) + sizeof (MPI2_SGE_IO_UNION)) / 12)
141 142
142 143 /*
143 144 * Scatter-gather list structure defined by HBA hardware
144 145 */
145 146 typedef struct NcrTableIndirect { /* Table Indirect entries */
146 147 uint32_t count; /* 24 bit count */
147 148 union {
148 149 uint32_t address32; /* 32 bit address */
149 150 struct {
150 151 uint32_t Low;
151 152 uint32_t High;
152 153 } address64; /* 64 bit address */
153 154 } addr;
154 155 } mptti_t;
155 156
156 157 /*
157 158 * preferred pkt_private length in 64-bit quantities
158 159 */
159 160 #ifdef _LP64
160 161 #define PKT_PRIV_SIZE 2
161 162 #define PKT_PRIV_LEN 16 /* in bytes */
162 163 #else /* _ILP32 */
163 164 #define PKT_PRIV_SIZE 1
164 165 #define PKT_PRIV_LEN 8 /* in bytes */
165 166 #endif
166 167
167 168 #define PKT2CMD(pkt) ((struct mptsas_cmd *)((pkt)->pkt_ha_private))
168 169 #define CMD2PKT(cmdp) ((struct scsi_pkt *)((cmdp)->cmd_pkt))
169 170 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status))
170 171
171 172 /*
172 173 * get offset of item in structure
173 174 */
174 175 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member))
175 176
176 177 /*
177 178 * WWID provided by LSI firmware is generated by firmware but the WWID is not
178 179 * IEEE NAA standard format, OBP has no chance to distinguish format of unit
179 180 * address. According LSI's confirmation, the top nibble of RAID WWID is
180 181 * meanless, so the consensus between Solaris and OBP is to replace top nibble
181 182 * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID
182 183 * format unit address.
183 184 */
184 185 #define MPTSAS_RAID_WWID(wwid) \
185 186 ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000)
186 187
187 188 typedef struct mptsas_target {
188 189 uint64_t m_sas_wwn; /* hash key1 */
189 190 mptsas_phymask_t m_phymask; /* hash key2 */
190 191 /*
191 192 * m_dr_flag is a flag for DR, make sure the member
192 193 * take the place of dr_flag of mptsas_hash_data.
193 194 */
194 195 uint8_t m_dr_flag; /* dr_flag */
195 196 uint16_t m_devhdl;
196 197 uint32_t m_deviceinfo;
197 198 uint8_t m_phynum;
198 199 uint32_t m_dups;
199 200 int32_t m_timeout;
200 201 int32_t m_timebase;
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201 202 int32_t m_t_throttle;
202 203 int32_t m_t_ncmds;
203 204 int32_t m_reset_delay;
204 205 int32_t m_t_nwait;
205 206
206 207 uint16_t m_qfull_retry_interval;
207 208 uint8_t m_qfull_retries;
208 209 uint16_t m_enclosure;
209 210 uint16_t m_slot_num;
210 211 uint32_t m_tgt_unconfigured;
212 + uint8_t m_led_status;
211 213
212 214 /*
213 215 * For the common case, the elements in this structure are
214 216 * protected by the per hba instance mutex. In order to make
215 217 * the key code path in ISR lockless, a separate mutex is
216 218 * introdeced to protect those shown in ISR.
217 219 */
218 220 kmutex_t m_tgt_intr_mutex;
219 221
220 222 } mptsas_target_t;
221 223
222 224 typedef struct mptsas_smp {
223 225 uint64_t m_sasaddr; /* hash key1 */
224 226 mptsas_phymask_t m_phymask; /* hash key2 */
225 227 uint8_t reserved1;
226 228 uint16_t m_devhdl;
227 229 uint32_t m_deviceinfo;
228 230 uint16_t m_pdevhdl;
229 231 uint32_t m_pdevinfo;
230 232 } mptsas_smp_t;
231 233
232 234 typedef struct mptsas_hash_data {
233 235 uint64_t key1;
234 236 mptsas_phymask_t key2;
235 237 uint8_t dr_flag;
236 238 uint16_t devhdl;
237 239 uint32_t device_info;
238 240 } mptsas_hash_data_t;
239 241
240 242 typedef struct mptsas_cache_frames {
241 243 ddi_dma_handle_t m_dma_hdl;
242 244 ddi_acc_handle_t m_acc_hdl;
243 245 caddr_t m_frames_addr;
244 246 uint32_t m_phys_addr;
245 247 } mptsas_cache_frames_t;
246 248
247 249 typedef struct mptsas_cmd {
248 250 uint_t cmd_flags; /* flags from scsi_init_pkt */
249 251 ddi_dma_handle_t cmd_dmahandle; /* dma handle */
250 252 ddi_dma_cookie_t cmd_cookie;
251 253 uint_t cmd_cookiec;
252 254 uint_t cmd_winindex;
253 255 uint_t cmd_nwin;
254 256 uint_t cmd_cur_cookie;
255 257 off_t cmd_dma_offset;
256 258 size_t cmd_dma_len;
257 259 uint32_t cmd_totaldmacount;
258 260
259 261 ddi_dma_handle_t cmd_arqhandle; /* dma arq handle */
260 262 ddi_dma_cookie_t cmd_arqcookie;
261 263 struct buf *cmd_arq_buf;
262 264 ddi_dma_handle_t cmd_ext_arqhandle; /* dma extern arq handle */
263 265 ddi_dma_cookie_t cmd_ext_arqcookie;
264 266 struct buf *cmd_ext_arq_buf;
265 267
266 268 int cmd_pkt_flags;
267 269
268 270 /* timer for command in active slot */
269 271 int cmd_active_timeout;
270 272
271 273 struct scsi_pkt *cmd_pkt;
272 274 struct scsi_arq_status cmd_scb;
273 275 uchar_t cmd_cdblen; /* length of cdb */
274 276 uchar_t cmd_rqslen; /* len of requested rqsense */
275 277 uchar_t cmd_privlen;
276 278 uint_t cmd_scblen;
277 279 uint32_t cmd_dmacount;
278 280 uint64_t cmd_dma_addr;
279 281 uchar_t cmd_age;
280 282 ushort_t cmd_qfull_retries;
281 283 uchar_t cmd_queued; /* true if queued */
282 284 struct mptsas_cmd *cmd_linkp;
283 285 mptti_t *cmd_sg; /* Scatter/Gather structure */
284 286 uchar_t cmd_cdb[SCSI_CDB_SIZE];
285 287 uint64_t cmd_pkt_private[PKT_PRIV_LEN];
286 288 uint32_t cmd_slot;
287 289 uint32_t ioc_cmd_slot;
288 290
289 291 mptsas_cache_frames_t *cmd_extra_frames;
290 292
291 293 uint32_t cmd_rfm;
292 294 mptsas_target_t *cmd_tgt_addr;
293 295 } mptsas_cmd_t;
294 296
295 297 /*
296 298 * These are the defined cmd_flags for this structure.
297 299 */
298 300 #define CFLAG_CMDDISC 0x000001 /* cmd currently disconnected */
299 301 #define CFLAG_WATCH 0x000002 /* watchdog time for this command */
300 302 #define CFLAG_FINISHED 0x000004 /* command completed */
301 303 #define CFLAG_CHKSEG 0x000008 /* check cmd_data within seg */
302 304 #define CFLAG_COMPLETED 0x000010 /* completion routine called */
303 305 #define CFLAG_PREPARED 0x000020 /* pkt has been init'ed */
304 306 #define CFLAG_IN_TRANSPORT 0x000040 /* in use by host adapter driver */
305 307 #define CFLAG_RESTORE_PTRS 0x000080 /* implicit restore ptr on reconnect */
306 308 #define CFLAG_ARQ_IN_PROGRESS 0x000100 /* auto request sense in progress */
307 309 #define CFLAG_TRANFLAG 0x0001ff /* covers transport part of flags */
308 310 #define CFLAG_TM_CMD 0x000200 /* cmd is a task management command */
309 311 #define CFLAG_CMDARQ 0x000400 /* cmd is a 'rqsense' command */
310 312 #define CFLAG_DMAVALID 0x000800 /* dma mapping valid */
311 313 #define CFLAG_DMASEND 0x001000 /* data is going 'out' */
312 314 #define CFLAG_CMDIOPB 0x002000 /* this is an 'iopb' packet */
313 315 #define CFLAG_CDBEXTERN 0x004000 /* cdb kmem_alloc'd */
314 316 #define CFLAG_SCBEXTERN 0x008000 /* scb kmem_alloc'd */
315 317 #define CFLAG_FREE 0x010000 /* packet is on free list */
316 318 #define CFLAG_PRIVEXTERN 0x020000 /* target private kmem_alloc'd */
317 319 #define CFLAG_DMA_PARTIAL 0x040000 /* partial xfer OK */
318 320 #define CFLAG_QFULL_STATUS 0x080000 /* pkt got qfull status */
319 321 #define CFLAG_TIMEOUT 0x100000 /* passthru/config command timeout */
320 322 #define CFLAG_PMM_RECEIVED 0x200000 /* use cmd_pmm* for saving pointers */
321 323 #define CFLAG_RETRY 0x400000 /* cmd has been retried */
322 324 #define CFLAG_CMDIOC 0x800000 /* cmd is just for for ioc, no io */
323 325 #define CFLAG_EXTARQBUFVALID 0x1000000 /* extern arq buf handle is valid */
324 326 #define CFLAG_PASSTHRU 0x2000000 /* cmd is a passthrough command */
325 327 #define CFLAG_XARQ 0x4000000 /* cmd requests for extra sense */
326 328 #define CFLAG_CMDACK 0x8000000 /* cmd for event ack */
327 329 #define CFLAG_TXQ 0x10000000 /* cmd queued in the tx_waitq */
328 330 #define CFLAG_FW_CMD 0x20000000 /* cmd is a fw up/down command */
329 331 #define CFLAG_CONFIG 0x40000000 /* cmd is for config header/page */
330 332 #define CFLAG_FW_DIAG 0x80000000 /* cmd is for FW diag buffers */
331 333
332 334 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE 8
333 335 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK 0xC0
334 336 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL 0x00
335 337 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE 0x40
336 338 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT 0x80
337 339 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_EXTENDED_UNIT 0xC0
338 340 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_2B 0x00
339 341 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_4B 0x01
340 342 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_6B 0x10
341 343 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_8B 0x20
342 344 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_SIZE 0x30
343 345
344 346 #define MPTSAS_HASH_ARRAY_SIZE 16
345 347 /*
346 348 * hash table definition
347 349 */
348 350
349 351 #define MPTSAS_HASH_FIRST 0xffff
350 352 #define MPTSAS_HASH_NEXT 0x0000
351 353
352 354 typedef struct mptsas_dma_alloc_state
353 355 {
354 356 ddi_dma_handle_t handle;
355 357 caddr_t memp;
356 358 size_t size;
357 359 ddi_acc_handle_t accessp;
358 360 ddi_dma_cookie_t cookie;
359 361 } mptsas_dma_alloc_state_t;
360 362
361 363 /*
362 364 * passthrough request structure
363 365 */
364 366 typedef struct mptsas_pt_request {
365 367 uint8_t *request;
366 368 uint32_t request_size;
367 369 uint32_t data_size;
368 370 uint32_t dataout_size;
369 371 uint32_t direction;
370 372 ddi_dma_cookie_t data_cookie;
371 373 ddi_dma_cookie_t dataout_cookie;
372 374 } mptsas_pt_request_t;
373 375
374 376 /*
375 377 * config page request structure
376 378 */
377 379 typedef struct mptsas_config_request {
378 380 uint32_t page_address;
379 381 uint8_t action;
380 382 uint8_t page_type;
381 383 uint8_t page_number;
382 384 uint8_t page_length;
383 385 uint8_t page_version;
384 386 uint8_t ext_page_type;
385 387 uint16_t ext_page_length;
386 388 } mptsas_config_request_t;
387 389
388 390 typedef struct mptsas_fw_diagnostic_buffer {
389 391 mptsas_dma_alloc_state_t buffer_data;
390 392 uint8_t extended_type;
391 393 uint8_t buffer_type;
392 394 uint8_t force_release;
393 395 uint32_t product_specific[23];
394 396 uint8_t immediate;
395 397 uint8_t enabled;
396 398 uint8_t valid_data;
397 399 uint8_t owned_by_firmware;
398 400 uint32_t unique_id;
399 401 } mptsas_fw_diagnostic_buffer_t;
400 402
401 403 /*
402 404 * FW diag request structure
403 405 */
404 406 typedef struct mptsas_diag_request {
405 407 mptsas_fw_diagnostic_buffer_t *pBuffer;
406 408 uint8_t function;
407 409 } mptsas_diag_request_t;
408 410
409 411 typedef struct mptsas_hash_node {
410 412 void *data;
411 413 struct mptsas_hash_node *next;
412 414 } mptsas_hash_node_t;
413 415
414 416 typedef struct mptsas_hash_table {
415 417 struct mptsas_hash_node *head[MPTSAS_HASH_ARRAY_SIZE];
416 418 /*
417 419 * last position in traverse
418 420 */
419 421 struct mptsas_hash_node *cur;
420 422 uint16_t line;
421 423
422 424 } mptsas_hash_table_t;
423 425
424 426 /*
425 427 * RAID volume information
426 428 */
427 429 typedef struct mptsas_raidvol {
428 430 ushort_t m_israid;
429 431 uint16_t m_raidhandle;
430 432 uint64_t m_raidwwid;
431 433 uint8_t m_state;
432 434 uint32_t m_statusflags;
433 435 uint32_t m_settings;
434 436 uint16_t m_devhdl[MPTSAS_MAX_DISKS_IN_VOL];
435 437 uint8_t m_disknum[MPTSAS_MAX_DISKS_IN_VOL];
436 438 ushort_t m_diskstatus[MPTSAS_MAX_DISKS_IN_VOL];
437 439 uint64_t m_raidsize;
438 440 int m_raidlevel;
439 441 int m_ndisks;
440 442 mptsas_target_t *m_raidtgt;
441 443 } mptsas_raidvol_t;
442 444
443 445 /*
444 446 * RAID configurations
445 447 */
446 448 typedef struct mptsas_raidconfig {
447 449 mptsas_raidvol_t m_raidvol[MPTSAS_MAX_RAIDVOLS];
448 450 uint16_t m_physdisk_devhdl[
449 451 MPTSAS_MAX_DISKS_IN_CONFIG];
450 452 uint8_t m_native;
451 453 } m_raidconfig_t;
452 454
453 455 /*
454 456 * Structure to hold active outstanding cmds. Also, keep
455 457 * timeout on a per target basis.
456 458 */
457 459 typedef struct mptsas_slots {
458 460 mptsas_hash_table_t m_tgttbl;
459 461 mptsas_hash_table_t m_smptbl;
460 462 m_raidconfig_t m_raidconfig[MPTSAS_MAX_RAIDCONFIGS];
461 463 uint8_t m_num_raid_configs;
462 464 uint16_t m_tags;
463 465 size_t m_size;
464 466 uint16_t m_n_slots;
465 467 mptsas_cmd_t *m_slot[1];
466 468 } mptsas_slots_t;
467 469
468 470 /*
469 471 * Structure to hold command and packets for event ack
470 472 * and task management commands.
471 473 */
472 474 typedef struct m_event_struct {
473 475 struct mptsas_cmd m_event_cmd;
474 476 struct m_event_struct *m_event_linkp;
475 477 /*
476 478 * event member record the failure event and eventcntx
477 479 * event member would be used in send ack pending process
478 480 */
479 481 uint32_t m_event;
480 482 uint32_t m_eventcntx;
481 483 uint_t in_use;
482 484 struct scsi_pkt m_event_pkt; /* must be last */
483 485 /* ... scsi_pkt_size() */
484 486 } m_event_struct_t;
485 487 #define M_EVENT_STRUCT_SIZE (sizeof (m_event_struct_t) - \
486 488 sizeof (struct scsi_pkt) + scsi_pkt_size())
487 489
488 490 #define MAX_IOC_COMMANDS 8
489 491
490 492 /*
491 493 * A pool of MAX_IOC_COMMANDS is maintained for event ack commands.
492 494 * A new event ack command requests mptsas_cmd and scsi_pkt structures
493 495 * from this pool, and returns it back when done.
494 496 */
495 497
496 498 typedef struct m_replyh_arg {
497 499 void *mpt;
498 500 uint32_t rfm;
499 501 } m_replyh_arg_t;
500 502 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::mpt))
501 503 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::rfm))
502 504
503 505 /*
504 506 * Flags for DR handler topology change
505 507 */
506 508 #define MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE 0x0
507 509 #define MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED 0x1
508 510 #define MPTSAS_TOPO_FLAG_LUN_ASSOCIATED 0x2
509 511 #define MPTSAS_TOPO_FLAG_RAID_ASSOCIATED 0x4
510 512 #define MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED 0x8
511 513 #define MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE 0x10
512 514
513 515 typedef struct mptsas_topo_change_list {
514 516 void *mpt;
515 517 uint_t event;
516 518 union {
517 519 uint8_t physport;
518 520 mptsas_phymask_t phymask;
519 521 } un;
520 522 uint16_t devhdl;
521 523 void *object;
522 524 uint8_t flags;
523 525 struct mptsas_topo_change_list *next;
524 526 } mptsas_topo_change_list_t;
525 527
526 528
527 529 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::mpt))
528 530 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::event))
529 531 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::physport))
530 532 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::devhdl))
531 533 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::object))
532 534 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::flags))
533 535
534 536 /*
535 537 * Status types when calling mptsas_get_target_device_info
536 538 */
537 539 #define DEV_INFO_SUCCESS 0x0
538 540 #define DEV_INFO_FAIL_PAGE0 0x1
539 541 #define DEV_INFO_WRONG_DEVICE_TYPE 0x2
540 542 #define DEV_INFO_PHYS_DISK 0x3
541 543 #define DEV_INFO_FAIL_ALLOC 0x4
542 544
543 545 /*
544 546 * mpt hotplug event defines
545 547 */
546 548 #define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01
547 549 #define MPTSAS_DR_EVENT_OFFLINE_TARGET 0x02
548 550 #define MPTSAS_TOPO_FLAG_REMOVE_HANDLE 0x04
549 551
550 552 /*
551 553 * SMP target hotplug events
552 554 */
553 555 #define MPTSAS_DR_EVENT_RECONFIG_SMP 0x10
554 556 #define MPTSAS_DR_EVENT_OFFLINE_SMP 0x20
555 557 #define MPTSAS_DR_EVENT_MASK 0x3F
556 558
557 559 /*
558 560 * mpt hotplug status definition for m_dr_flag
559 561 */
560 562
561 563 /*
562 564 * MPTSAS_DR_INACTIVE
563 565 *
564 566 * The target is in a normal operating state.
565 567 * No dynamic reconfiguration operation is in progress.
566 568 */
567 569 #define MPTSAS_DR_INACTIVE 0x0
568 570 /*
569 571 * MPTSAS_DR_INTRANSITION
570 572 *
571 573 * The target is in a transition mode since
572 574 * hotplug event happens and offline procedure has not
573 575 * been finished
574 576 */
575 577 #define MPTSAS_DR_INTRANSITION 0x1
576 578
577 579 typedef struct mptsas_tgt_private {
578 580 int t_lun;
579 581 struct mptsas_target *t_private;
580 582 } mptsas_tgt_private_t;
581 583
582 584 /*
583 585 * The following defines are used in mptsas_set_init_mode to track the current
584 586 * state as we progress through reprogramming the HBA from target mode into
585 587 * initiator mode.
586 588 */
587 589
588 590 #define IOUC_READ_PAGE0 0x00000100
589 591 #define IOUC_READ_PAGE1 0x00000200
590 592 #define IOUC_WRITE_PAGE1 0x00000400
591 593 #define IOUC_DONE 0x00000800
592 594 #define DISCOVERY_IN_PROGRESS MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS
593 595 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG
594 596
595 597 /*
596 598 * Last allocated slot is used for TM requests. Since only m_max_requests
597 599 * frames are allocated, the last SMID will be m_max_requests - 1.
598 600 */
599 601 #define MPTSAS_SLOTS_SIZE(mpt) \
600 602 (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \
601 603 mpt->m_max_requests))
602 604 #define MPTSAS_TM_SLOT(mpt) (mpt->m_max_requests - 1)
603 605
604 606 typedef struct mptsas_slot_free_e {
605 607 processorid_t cpuid;
606 608 int slot;
607 609 list_node_t node;
608 610 } mptsas_slot_free_e_t;
609 611
610 612 /*
611 613 * each of the allocq and releaseq in all CPU groups resides in separate
612 614 * cacheline(64 bytes). Multiple mutex in the same cacheline is not good
613 615 * for performance.
614 616 */
615 617 typedef union mptsas_slot_freeq {
616 618 struct {
617 619 kmutex_t m_fq_mutex;
618 620 list_t m_fq_list;
619 621 int m_fq_n;
620 622 int m_fq_n_init;
621 623 } s;
622 624 char pad[64];
623 625 } mptsas_slot_freeq_t;
624 626
625 627 typedef struct mptsas_slot_freeq_pair {
626 628 mptsas_slot_freeq_t m_slot_allocq;
627 629 mptsas_slot_freeq_t m_slot_releq;
628 630 } mptsas_slot_freeq_pair_t;
629 631
630 632 /*
631 633 * Macro for phy_flags
632 634 */
633 635
634 636 typedef struct smhba_info {
635 637 kmutex_t phy_mutex;
636 638 uint8_t phy_id;
637 639 uint64_t sas_addr;
638 640 char path[8];
639 641 uint16_t owner_devhdl;
640 642 uint16_t attached_devhdl;
641 643 uint8_t attached_phy_identify;
642 644 uint32_t attached_phy_info;
643 645 uint8_t programmed_link_rate;
644 646 uint8_t hw_link_rate;
645 647 uint8_t change_count;
646 648 uint32_t phy_info;
647 649 uint8_t negotiated_link_rate;
648 650 uint8_t port_num;
649 651 kstat_t *phy_stats;
650 652 uint32_t invalid_dword_count;
651 653 uint32_t running_disparity_error_count;
652 654 uint32_t loss_of_dword_sync_count;
653 655 uint32_t phy_reset_problem_count;
654 656 void *mpt;
655 657 } smhba_info_t;
656 658
657 659 typedef struct mptsas_phy_info {
658 660 uint8_t port_num;
659 661 uint8_t port_flags;
660 662 uint16_t ctrl_devhdl;
661 663 uint32_t phy_device_type;
662 664 uint16_t attached_devhdl;
663 665 mptsas_phymask_t phy_mask;
664 666 smhba_info_t smhba_info;
665 667 } mptsas_phy_info_t;
666 668
667 669
668 670 typedef struct mptsas_doneq_thread_arg {
669 671 void *mpt;
670 672 uint64_t t;
671 673 } mptsas_doneq_thread_arg_t;
672 674
673 675 #define MPTSAS_DONEQ_THREAD_ACTIVE 0x1
674 676 typedef struct mptsas_doneq_thread_list {
675 677 mptsas_cmd_t *doneq;
676 678 mptsas_cmd_t **donetail;
677 679 kthread_t *threadp;
678 680 kcondvar_t cv;
679 681 ushort_t reserv1;
680 682 uint32_t reserv2;
681 683 kmutex_t mutex;
682 684 uint32_t flag;
683 685 uint32_t len;
684 686 mptsas_doneq_thread_arg_t arg;
685 687 } mptsas_doneq_thread_list_t;
686 688
687 689 typedef struct mptsas {
688 690 int m_instance;
689 691
690 692 struct mptsas *m_next;
691 693
692 694 scsi_hba_tran_t *m_tran;
693 695 smp_hba_tran_t *m_smptran;
694 696 kmutex_t m_mutex;
695 697 kcondvar_t m_cv;
696 698 kcondvar_t m_fw_cv;
697 699 kcondvar_t m_config_cv;
698 700 kcondvar_t m_fw_diag_cv;
699 701 dev_info_t *m_dip;
700 702
701 703 /*
702 704 * soft state flags
703 705 */
704 706 uint_t m_softstate;
705 707
706 708 struct mptsas_slots *m_active; /* outstanding cmds */
707 709
708 710 mptsas_cmd_t *m_waitq; /* cmd queue for active request */
709 711 mptsas_cmd_t **m_waitqtail; /* wait queue tail ptr */
710 712
711 713 mptsas_cmd_t *m_doneq; /* queue of completed commands */
712 714 mptsas_cmd_t **m_donetail; /* queue tail ptr */
713 715
714 716 kmutex_t m_passthru_mutex;
715 717 kcondvar_t m_passthru_cv;
716 718 /*
717 719 * variables for helper threads (fan-out interrupts)
718 720 */
719 721 mptsas_doneq_thread_list_t *m_doneq_thread_id;
720 722 uint32_t m_doneq_thread_n;
721 723 uint32_t m_doneq_thread_threshold;
722 724 uint32_t m_doneq_length_threshold;
723 725 uint32_t m_doneq_len;
724 726 kcondvar_t m_doneq_thread_cv;
725 727 kmutex_t m_doneq_mutex;
726 728
727 729 int m_ncmds; /* number of outstanding commands */
728 730 m_event_struct_t *m_ioc_event_cmdq; /* cmd queue for ioc event */
729 731 m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */
730 732
731 733 ddi_acc_handle_t m_datap; /* operating regs data access handle */
732 734
733 735 struct _MPI2_SYSTEM_INTERFACE_REGS *m_reg;
734 736
735 737 ushort_t m_devid; /* device id of chip. */
736 738 uchar_t m_revid; /* revision of chip. */
737 739 uint16_t m_svid; /* subsystem Vendor ID of chip */
738 740 uint16_t m_ssid; /* subsystem Device ID of chip */
739 741
740 742 uchar_t m_sync_offset; /* default offset for this chip. */
741 743
742 744 timeout_id_t m_quiesce_timeid;
743 745
744 746 ddi_dma_handle_t m_dma_req_frame_hdl;
745 747 ddi_acc_handle_t m_acc_req_frame_hdl;
746 748 ddi_dma_handle_t m_dma_reply_frame_hdl;
747 749 ddi_acc_handle_t m_acc_reply_frame_hdl;
748 750 ddi_dma_handle_t m_dma_free_queue_hdl;
749 751 ddi_acc_handle_t m_acc_free_queue_hdl;
750 752 ddi_dma_handle_t m_dma_post_queue_hdl;
751 753 ddi_acc_handle_t m_acc_post_queue_hdl;
752 754
753 755 /*
754 756 * Try the best to make the key code path in the ISR lockless.
755 757 * so avoid to use the per instance mutex m_mutex in the ISR. Introduce
756 758 * a separate mutex to protect the elements shown in ISR.
757 759 */
758 760 kmutex_t m_intr_mutex;
759 761
760 762 /*
761 763 * list of reset notification requests
762 764 */
763 765 struct scsi_reset_notify_entry *m_reset_notify_listf;
764 766
765 767 /*
766 768 * qfull handling
767 769 */
768 770 timeout_id_t m_restart_cmd_timeid;
769 771
770 772 /*
771 773 * scsi reset delay per bus
772 774 */
773 775 uint_t m_scsi_reset_delay;
774 776
775 777 int m_pm_idle_delay;
776 778
777 779 uchar_t m_polled_intr; /* intr was polled. */
778 780 uchar_t m_suspended; /* true if driver is suspended */
779 781
780 782 struct kmem_cache *m_kmem_cache;
781 783 struct kmem_cache *m_cache_frames;
782 784
783 785 /*
784 786 * hba options.
785 787 */
786 788 uint_t m_options;
787 789
788 790 int m_in_callback;
789 791
790 792 int m_power_level; /* current power level */
791 793
792 794 int m_busy; /* power management busy state */
793 795
794 796 off_t m_pmcsr_offset; /* PMCSR offset */
795 797
796 798 ddi_acc_handle_t m_config_handle;
797 799
798 800 ddi_dma_attr_t m_io_dma_attr; /* Used for data I/O */
799 801 ddi_dma_attr_t m_msg_dma_attr; /* Used for message frames */
800 802 ddi_device_acc_attr_t m_dev_acc_attr;
801 803 ddi_device_acc_attr_t m_reg_acc_attr;
802 804
803 805 /*
804 806 * request/reply variables
805 807 */
806 808 caddr_t m_req_frame;
807 809 uint64_t m_req_frame_dma_addr;
808 810 caddr_t m_reply_frame;
809 811 uint64_t m_reply_frame_dma_addr;
810 812 caddr_t m_free_queue;
811 813 uint64_t m_free_queue_dma_addr;
812 814 caddr_t m_post_queue;
813 815 uint64_t m_post_queue_dma_addr;
814 816
815 817 m_replyh_arg_t *m_replyh_args;
816 818
817 819 uint16_t m_max_requests;
818 820 uint16_t m_req_frame_size;
819 821
820 822 /*
821 823 * Max frames per request reprted in IOC Facts
822 824 */
823 825 uint8_t m_max_chain_depth;
824 826 /*
825 827 * Max frames per request which is used in reality. It's adjusted
826 828 * according DMA SG length attribute, and shall not exceed the
827 829 * m_max_chain_depth.
828 830 */
829 831 uint8_t m_max_request_frames;
830 832
831 833 uint16_t m_free_queue_depth;
832 834 uint16_t m_post_queue_depth;
833 835 uint16_t m_max_replies;
834 836 uint32_t m_free_index;
835 837 uint32_t m_post_index;
836 838 uint8_t m_reply_frame_size;
837 839 uint32_t m_ioc_capabilities;
838 840
839 841 /*
840 842 * indicates if the firmware was upload by the driver
841 843 * at boot time
842 844 */
843 845 ushort_t m_fwupload;
844 846
845 847 uint16_t m_productid;
846 848
847 849 /*
848 850 * per instance data structures for dma memory resources for
849 851 * MPI handshake protocol. only one handshake cmd can run at a time.
850 852 */
851 853 ddi_dma_handle_t m_hshk_dma_hdl;
852 854
853 855 ddi_acc_handle_t m_hshk_acc_hdl;
854 856
855 857 caddr_t m_hshk_memp;
856 858
857 859 size_t m_hshk_dma_size;
858 860
859 861 /* Firmware version on the card at boot time */
860 862 uint32_t m_fwversion;
861 863
862 864 /* MSI specific fields */
863 865 ddi_intr_handle_t *m_htable; /* For array of interrupts */
864 866 int m_intr_type; /* What type of interrupt */
865 867 int m_intr_cnt; /* # of intrs count returned */
866 868 size_t m_intr_size; /* Size of intr array */
867 869 uint_t m_intr_pri; /* Interrupt priority */
868 870 int m_intr_cap; /* Interrupt capabilities */
869 871 ddi_taskq_t *m_event_taskq;
870 872
871 873 /* SAS specific information */
872 874
873 875 union {
874 876 uint64_t m_base_wwid; /* Base WWID */
875 877 struct {
876 878 #ifdef _BIG_ENDIAN
877 879 uint32_t m_base_wwid_hi;
878 880 uint32_t m_base_wwid_lo;
879 881 #else
880 882 uint32_t m_base_wwid_lo;
881 883 uint32_t m_base_wwid_hi;
882 884 #endif
883 885 } sasaddr;
884 886 } un;
885 887
886 888 uint8_t m_num_phys; /* # of PHYs */
887 889 mptsas_phy_info_t m_phy_info[MPTSAS_MAX_PHYS];
888 890 uint8_t m_port_chng; /* initiator port changes */
889 891 MPI2_CONFIG_PAGE_MAN_0 m_MANU_page0; /* Manufactor page 0 info */
890 892 MPI2_CONFIG_PAGE_MAN_1 m_MANU_page1; /* Manufactor page 1 info */
891 893
892 894 /* FMA Capabilities */
893 895 int m_fm_capabilities;
894 896 ddi_taskq_t *m_dr_taskq;
895 897 int m_mpxio_enable;
896 898 uint8_t m_done_traverse_dev;
897 899 uint8_t m_done_traverse_smp;
898 900 int m_diag_action_in_progress;
899 901 uint16_t m_dev_handle;
900 902 uint16_t m_smp_devhdl;
901 903
902 904 /*
903 905 * Event recording
904 906 */
905 907 uint8_t m_event_index;
906 908 uint32_t m_event_number;
907 909 uint32_t m_event_mask[4];
908 910 mptsas_event_entry_t m_events[MPTSAS_EVENT_QUEUE_SIZE];
909 911
910 912 /*
911 913 * FW diag Buffer List
912 914 */
913 915 mptsas_fw_diagnostic_buffer_t
914 916 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT];
915 917
916 918 /*
917 919 * Event Replay flag (MUR support)
918 920 */
919 921 uint8_t m_event_replay;
920 922
921 923 /*
922 924 * IR Capable flag
923 925 */
924 926 uint8_t m_ir_capable;
925 927
926 928 /*
927 929 * release and alloc queue for slot
928 930 */
929 931 int m_slot_freeq_pair_n;
930 932 mptsas_slot_freeq_pair_t *m_slot_freeq_pairp;
931 933 mptsas_slot_free_e_t *m_slot_free_ae;
932 934 #define MPI_ADDRESS_COALSCE_MAX 128
933 935 pMpi2ReplyDescriptorsUnion_t m_reply;
934 936
935 937 /*
936 938 * Is HBA processing a diag reset?
937 939 */
938 940 uint8_t m_in_reset;
939 941
940 942 /*
941 943 * per instance cmd data structures for task management cmds
942 944 */
943 945 m_event_struct_t m_event_task_mgmt; /* must be last */
944 946 /* ... scsi_pkt_size */
945 947 } mptsas_t;
946 948 #define MPTSAS_SIZE (sizeof (struct mptsas) - \
947 949 sizeof (struct scsi_pkt) + scsi_pkt_size())
948 950 /*
949 951 * Only one of below two conditions is satisfied, we
950 952 * think the target is associated to the iport and
951 953 * allow call into mptsas_probe_lun().
952 954 * 1. physicalsport == physport
953 955 * 2. (phymask & (1 << physport)) == 0
954 956 * The condition #2 is because LSI uses lowest PHY
955 957 * number as the value of physical port when auto port
956 958 * configuration.
957 959 */
958 960 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \
959 961 ((physicalport == physport) || (dynamicport && (phymask & \
960 962 (1 << physport))))
961 963
962 964 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas))
963 965 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next))
964 966 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran))
965 967 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_kmem_cache))
966 968 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_io_dma_attr.dma_attr_sgllen))
967 969 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_devid))
968 970 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_productid))
969 971 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_port_type))
970 972 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_mpxio_enable))
971 973 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_ntargets))
972 974 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_instance))
973 975
974 976 /*
975 977 * These should eventually migrate into the mpt header files
976 978 * that may become the /kernel/misc/mpt module...
977 979 */
978 980 #define mptsas_init_std_hdr(hdl, mp, DevHandle, Lun, ChainOffset, Function) \
979 981 mptsas_put_msg_DevHandle(hdl, mp, DevHandle); \
980 982 mptsas_put_msg_ChainOffset(hdl, mp, ChainOffset); \
981 983 mptsas_put_msg_Function(hdl, mp, Function); \
982 984 mptsas_put_msg_Lun(hdl, mp, Lun)
983 985
984 986 #define mptsas_put_msg_DevHandle(hdl, mp, val) \
985 987 ddi_put16(hdl, &(mp)->DevHandle, (val))
986 988 #define mptsas_put_msg_ChainOffset(hdl, mp, val) \
987 989 ddi_put8(hdl, &(mp)->ChainOffset, (val))
988 990 #define mptsas_put_msg_Function(hdl, mp, val) \
989 991 ddi_put8(hdl, &(mp)->Function, (val))
990 992 #define mptsas_put_msg_Lun(hdl, mp, val) \
991 993 ddi_put8(hdl, &(mp)->LUN[1], (val))
992 994
993 995 #define mptsas_get_msg_Function(hdl, mp) \
994 996 ddi_get8(hdl, &(mp)->Function)
995 997
996 998 #define mptsas_get_msg_MsgFlags(hdl, mp) \
997 999 ddi_get8(hdl, &(mp)->MsgFlags)
998 1000
999 1001 #define MPTSAS_ENABLE_DRWE(hdl) \
1000 1002 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1001 1003 MPI2_WRSEQ_FLUSH_KEY_VALUE); \
1002 1004 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1003 1005 MPI2_WRSEQ_1ST_KEY_VALUE); \
1004 1006 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1005 1007 MPI2_WRSEQ_2ND_KEY_VALUE); \
1006 1008 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1007 1009 MPI2_WRSEQ_3RD_KEY_VALUE); \
1008 1010 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1009 1011 MPI2_WRSEQ_4TH_KEY_VALUE); \
1010 1012 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1011 1013 MPI2_WRSEQ_5TH_KEY_VALUE); \
1012 1014 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1013 1015 MPI2_WRSEQ_6TH_KEY_VALUE);
1014 1016
1015 1017 /*
1016 1018 * m_options flags
1017 1019 */
1018 1020 #define MPTSAS_OPT_PM 0x01 /* Power Management */
1019 1021
1020 1022 /*
1021 1023 * m_softstate flags
1022 1024 */
1023 1025 #define MPTSAS_SS_DRAINING 0x02
1024 1026 #define MPTSAS_SS_QUIESCED 0x04
1025 1027 #define MPTSAS_SS_MSG_UNIT_RESET 0x08
1026 1028 #define MPTSAS_DID_MSG_UNIT_RESET 0x10
1027 1029
1028 1030 /*
1029 1031 * regspec defines.
1030 1032 */
1031 1033 #define CONFIG_SPACE 0 /* regset[0] - configuration space */
1032 1034 #define IO_SPACE 1 /* regset[1] - used for i/o mapped device */
1033 1035 #define MEM_SPACE 2 /* regset[2] - used for memory mapped device */
1034 1036 #define BASE_REG2 3 /* regset[3] - used for 875 scripts ram */
1035 1037
1036 1038 /*
1037 1039 * Handy constants
1038 1040 */
1039 1041 #define FALSE 0
1040 1042 #define TRUE 1
1041 1043 #define UNDEFINED -1
1042 1044 #define FAILED -2
1043 1045
1044 1046 /*
1045 1047 * power management.
1046 1048 */
1047 1049 #define MPTSAS_POWER_ON(mpt) { \
1048 1050 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \
1049 1051 PCI_PMCSR_D0); \
1050 1052 delay(drv_usectohz(10000)); \
1051 1053 (void) pci_restore_config_regs(mpt->m_dip); \
1052 1054 mptsas_setup_cmd_reg(mpt); \
1053 1055 }
1054 1056
1055 1057 #define MPTSAS_POWER_OFF(mpt) { \
1056 1058 (void) pci_save_config_regs(mpt->m_dip); \
1057 1059 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \
1058 1060 PCI_PMCSR_D3HOT); \
1059 1061 mpt->m_power_level = PM_LEVEL_D3; \
1060 1062 }
1061 1063
1062 1064 /*
1063 1065 * inq_dtype:
1064 1066 * Bits 5 through 7 are the Peripheral Device Qualifier
1065 1067 * 001b: device not connected to the LUN
1066 1068 * Bits 0 through 4 are the Peripheral Device Type
1067 1069 * 1fh: Unknown or no device type
1068 1070 *
1069 1071 * Although the inquiry may return success, the following value
1070 1072 * means no valid LUN connected.
1071 1073 */
1072 1074 #define MPTSAS_VALID_LUN(sd_inq) \
1073 1075 (((sd_inq->inq_dtype & 0xe0) != 0x20) && \
1074 1076 ((sd_inq->inq_dtype & 0x1f) != 0x1f))
1075 1077
1076 1078 /*
1077 1079 * Default is to have 10 retries on receiving QFULL status and
1078 1080 * each retry to be after 100 ms.
1079 1081 */
1080 1082 #define QFULL_RETRIES 10
1081 1083 #define QFULL_RETRY_INTERVAL 100
1082 1084
1083 1085 /*
1084 1086 * Handy macros
1085 1087 */
1086 1088 #define Tgt(sp) ((sp)->cmd_pkt->pkt_address.a_target)
1087 1089 #define Lun(sp) ((sp)->cmd_pkt->pkt_address.a_lun)
1088 1090
1089 1091 #define IS_HEX_DIGIT(n) (((n) >= '0' && (n) <= '9') || \
1090 1092 ((n) >= 'a' && (n) <= 'f') || ((n) >= 'A' && (n) <= 'F'))
1091 1093
1092 1094 /*
1093 1095 * poll time for mptsas_pollret() and mptsas_wait_intr()
1094 1096 */
1095 1097 #define MPTSAS_POLL_TIME 30000 /* 30 seconds */
1096 1098
1097 1099 /*
1098 1100 * default time for mptsas_do_passthru
1099 1101 */
1100 1102 #define MPTSAS_PASS_THRU_TIME_DEFAULT 60 /* 60 seconds */
1101 1103
1102 1104 /*
1103 1105 * macro to return the effective address of a given per-target field
1104 1106 */
1105 1107 #define EFF_ADDR(start, offset) ((start) + (offset))
1106 1108
1107 1109 #define SDEV2ADDR(devp) (&((devp)->sd_address))
1108 1110 #define SDEV2TRAN(devp) ((devp)->sd_address.a_hba_tran)
1109 1111 #define PKT2TRAN(pkt) ((pkt)->pkt_address.a_hba_tran)
1110 1112 #define ADDR2TRAN(ap) ((ap)->a_hba_tran)
1111 1113 #define DIP2TRAN(dip) (ddi_get_driver_private(dip))
1112 1114
1113 1115
1114 1116 #define TRAN2MPT(hba) ((mptsas_t *)(hba)->tran_hba_private)
1115 1117 #define DIP2MPT(dip) (TRAN2MPT((scsi_hba_tran_t *)DIP2TRAN(dip)))
1116 1118 #define SDEV2MPT(sd) (TRAN2MPT(SDEV2TRAN(sd)))
1117 1119 #define PKT2MPT(pkt) (TRAN2MPT(PKT2TRAN(pkt)))
1118 1120
1119 1121 #define ADDR2MPT(ap) (TRAN2MPT(ADDR2TRAN(ap)))
1120 1122
1121 1123 #define POLL_TIMEOUT (2 * SCSI_POLL_TIMEOUT * 1000000)
1122 1124 #define SHORT_POLL_TIMEOUT (1000000) /* in usec, about 1 secs */
1123 1125 #define MPTSAS_QUIESCE_TIMEOUT 1 /* 1 sec */
1124 1126 #define MPTSAS_PM_IDLE_TIMEOUT 60 /* 60 seconds */
1125 1127
1126 1128 #define MPTSAS_GET_ISTAT(mpt) (ddi_get32((mpt)->m_datap, \
1127 1129 &(mpt)->m_reg->HostInterruptStatus))
1128 1130
1129 1131 #define MPTSAS_SET_SIGP(P) \
1130 1132 ClrSetBits(mpt->m_devaddr + NREG_ISTAT, 0, NB_ISTAT_SIGP)
1131 1133
1132 1134 #define MPTSAS_RESET_SIGP(P) (void) ddi_get8(mpt->m_datap, \
1133 1135 (uint8_t *)(mpt->m_devaddr + NREG_CTEST2))
1134 1136
1135 1137 #define MPTSAS_GET_INTCODE(P) (ddi_get32(mpt->m_datap, \
1136 1138 (uint32_t *)(mpt->m_devaddr + NREG_DSPS)))
1137 1139
1138 1140
1139 1141 #define MPTSAS_START_CMD(mpt, req_desc_lo, req_desc_hi) \
1140 1142 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostLow,\
1141 1143 req_desc_lo);\
1142 1144 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostHigh,\
1143 1145 req_desc_hi);
1144 1146
1145 1147 #define INTPENDING(mpt) \
1146 1148 (MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT)
1147 1149
1148 1150 /*
1149 1151 * Mask all interrupts to disable
1150 1152 */
1151 1153 #define MPTSAS_DISABLE_INTR(mpt) \
1152 1154 ddi_put32((mpt)->m_datap, &(mpt)->m_reg->HostInterruptMask, \
1153 1155 (MPI2_HIM_RIM | MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK))
1154 1156
1155 1157 /*
1156 1158 * Mask Doorbell and Reset interrupts to enable reply desc int.
1157 1159 */
1158 1160 #define MPTSAS_ENABLE_INTR(mpt) \
1159 1161 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \
1160 1162 (MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK))
1161 1163
1162 1164 #define MPTSAS_GET_NEXT_REPLY(mpt, index) \
1163 1165 &((uint64_t *)(void *)mpt->m_post_queue)[index]
1164 1166
1165 1167 #define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \
1166 1168 (mpt->m_req_frame + (mpt->m_req_frame_size * SMID))
1167 1169
1168 1170 #define ClrSetBits32(hdl, reg, clr, set) \
1169 1171 ddi_put32(hdl, (reg), \
1170 1172 ((ddi_get32(mpt->m_datap, (reg)) & ~(clr)) | (set)))
1171 1173
1172 1174 #define ClrSetBits(reg, clr, set) \
1173 1175 ddi_put8(mpt->m_datap, (uint8_t *)(reg), \
1174 1176 ((ddi_get8(mpt->m_datap, (uint8_t *)(reg)) & ~(clr)) | (set)))
1175 1177
1176 1178 #define MPTSAS_WAITQ_RM(mpt, cmdp) \
1177 1179 if ((cmdp = mpt->m_waitq) != NULL) { \
1178 1180 /* If the queue is now empty fix the tail pointer */ \
1179 1181 if ((mpt->m_waitq = cmdp->cmd_linkp) == NULL) \
1180 1182 mpt->m_waitqtail = &mpt->m_waitq; \
1181 1183 cmdp->cmd_linkp = NULL; \
1182 1184 cmdp->cmd_queued = FALSE; \
1183 1185 }
1184 1186
1185 1187 #define MPTSAS_TX_WAITQ_RM(mpt, cmdp) \
1186 1188 if ((cmdp = mpt->m_tx_waitq) != NULL) { \
1187 1189 /* If the queue is now empty fix the tail pointer */ \
1188 1190 if ((mpt->m_tx_waitq = cmdp->cmd_linkp) == NULL) \
1189 1191 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; \
1190 1192 cmdp->cmd_linkp = NULL; \
1191 1193 cmdp->cmd_queued = FALSE; \
1192 1194 }
1193 1195
1194 1196 /*
1195 1197 * defaults for the global properties
1196 1198 */
1197 1199 #define DEFAULT_SCSI_OPTIONS SCSI_OPTIONS_DR
1198 1200 #define DEFAULT_TAG_AGE_LIMIT 2
1199 1201 #define DEFAULT_WD_TICK 10
1200 1202
1201 1203 /*
1202 1204 * invalid hostid.
1203 1205 */
1204 1206 #define MPTSAS_INVALID_HOSTID -1
1205 1207
1206 1208 /*
1207 1209 * Get/Set hostid from SCSI port configuration page
1208 1210 */
1209 1211 #define MPTSAS_GET_HOST_ID(configuration) (configuration & 0xFF)
1210 1212 #define MPTSAS_SET_HOST_ID(hostid) (hostid | ((1 << hostid) << 16))
1211 1213
1212 1214 /*
1213 1215 * Config space.
1214 1216 */
1215 1217 #define MPTSAS_LATENCY_TIMER 0x40
1216 1218
1217 1219 /*
1218 1220 * Offset to firmware version
1219 1221 */
1220 1222 #define MPTSAS_FW_VERSION_OFFSET 9
1221 1223
1222 1224 /*
1223 1225 * Offset and masks to get at the ProductId field
1224 1226 */
1225 1227 #define MPTSAS_FW_PRODUCTID_OFFSET 8
1226 1228 #define MPTSAS_FW_PRODUCTID_MASK 0xFFFF0000
1227 1229 #define MPTSAS_FW_PRODUCTID_SHIFT 16
1228 1230
1229 1231 /*
1230 1232 * Subsystem ID for HBAs.
1231 1233 */
1232 1234 #define MPTSAS_HBA_SUBSYSTEM_ID 0x10C0
1233 1235 #define MPTSAS_RHEA_SUBSYSTEM_ID 0x10B0
1234 1236
1235 1237 /*
1236 1238 * reset delay tick
1237 1239 */
1238 1240 #define MPTSAS_WATCH_RESET_DELAY_TICK 50 /* specified in milli seconds */
1239 1241
1240 1242 /*
1241 1243 * Ioc reset return values
1242 1244 */
1243 1245 #define MPTSAS_RESET_FAIL -1
1244 1246 #define MPTSAS_NO_RESET 0
1245 1247 #define MPTSAS_SUCCESS_HARDRESET 1
1246 1248 #define MPTSAS_SUCCESS_MUR 2
1247 1249
1248 1250 /*
1249 1251 * throttle support.
1250 1252 */
1251 1253 #define MAX_THROTTLE 32
1252 1254 #define HOLD_THROTTLE 0
1253 1255 #define DRAIN_THROTTLE -1
1254 1256 #define QFULL_THROTTLE -2
1255 1257
1256 1258 /*
1257 1259 * Passthrough/config request flags
1258 1260 */
1259 1261 #define MPTSAS_DATA_ALLOCATED 0x0001
1260 1262 #define MPTSAS_DATAOUT_ALLOCATED 0x0002
1261 1263 #define MPTSAS_REQUEST_POOL_CMD 0x0004
1262 1264 #define MPTSAS_ADDRESS_REPLY 0x0008
1263 1265 #define MPTSAS_CMD_TIMEOUT 0x0010
1264 1266
1265 1267 /*
1266 1268 * response code tlr flag
1267 1269 */
1268 1270 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF 0x02
1269 1271
1270 1272 /*
1271 1273 * System Events
1272 1274 */
1273 1275 #ifndef DDI_VENDOR_LSI
1274 1276 #define DDI_VENDOR_LSI "LSI"
1275 1277 #endif /* DDI_VENDOR_LSI */
1276 1278
1277 1279 /*
1278 1280 * Shared functions
1279 1281 */
1280 1282 int mptsas_save_cmd(struct mptsas *mpt, struct mptsas_cmd *cmd);
1281 1283 void mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
1282 1284 void mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd);
1283 1285 void mptsas_log(struct mptsas *mpt, int level, char *fmt, ...);
1284 1286 int mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime);
1285 1287 int mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)());
1286 1288 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action,
1287 1289 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber,
1288 1290 uint8_t pageversion, uint8_t pagelength, uint32_t
1289 1291 SGEflagslength, uint32_t SGEaddress32);
1290 1292 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action,
1291 1293 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber,
1292 1294 uint8_t pageversion, uint16_t extpagelength,
1293 1295 uint32_t SGEflagslength, uint32_t SGEaddress32);
1294 1296 int mptsas_update_flash(mptsas_t *mpt, caddr_t ptrbuffer, uint32_t size,
1295 1297 uint8_t type, int mode);
1296 1298 int mptsas_check_flash(mptsas_t *mpt, caddr_t origfile, uint32_t size,
1297 1299 uint8_t type, int mode);
1298 1300 int mptsas_download_firmware();
1299 1301 int mptsas_can_download_firmware();
1300 1302 int mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep);
1301 1303 void mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep);
1302 1304 mptsas_phymask_t mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport);
1303 1305 void mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd);
1304 1306 int mptsas_check_acc_handle(ddi_acc_handle_t handle);
1305 1307 int mptsas_check_dma_handle(ddi_dma_handle_t handle);
1306 1308 void mptsas_fm_ereport(mptsas_t *mpt, char *detail);
1307 1309 int mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr,
1308 1310 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp,
1309 1311 uint32_t alloc_size, ddi_dma_cookie_t *cookiep);
1310 1312 void mptsas_dma_addr_destroy(ddi_dma_handle_t *, ddi_acc_handle_t *);
1311 1313
1312 1314 /*
1313 1315 * impl functions
1314 1316 */
1315 1317 int mptsas_ioc_wait_for_response(mptsas_t *mpt);
1316 1318 int mptsas_ioc_wait_for_doorbell(mptsas_t *mpt);
1317 1319 int mptsas_ioc_reset(mptsas_t *mpt, int);
1318 1320 int mptsas_send_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes,
1319 1321 ddi_acc_handle_t accessp);
1320 1322 int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes,
1321 1323 ddi_acc_handle_t accessp);
1322 1324 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action,
1323 1325 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber,
1324 1326 uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength,
1325 1327 uint32_t SGEaddress32);
1326 1328 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action,
1327 1329 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber,
1328 1330 uint8_t pageversion, uint16_t extpagelength,
1329 1331 uint32_t SGEflagslength, uint32_t SGEaddress32);
1330 1332
1331 1333 int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd,
1332 1334 struct scsi_pkt **pkt);
1333 1335 void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd);
1334 1336 void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt);
1335 1337 void mptsas_start_config_page_access(mptsas_t *mpt, mptsas_cmd_t *cmd);
1336 1338 int mptsas_access_config_page(mptsas_t *mpt, uint8_t action, uint8_t page_type,
1337 1339 uint8_t page_number, uint32_t page_address, int (*callback) (mptsas_t *,
1338 1340 caddr_t, ddi_acc_handle_t, uint16_t, uint32_t, va_list), ...);
1339 1341
1340 1342 int mptsas_ioc_task_management(mptsas_t *mpt, int task_type,
1341 1343 uint16_t dev_handle, int lun, uint8_t *reply, uint32_t reply_size,
1342 1344 int mode);
1343 1345 int mptsas_send_event_ack(mptsas_t *mpt, uint32_t event, uint32_t eventcntx);
1344 1346 void mptsas_send_pending_event_ack(mptsas_t *mpt);
1345 1347 void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt, int what);
1346 1348 int mptsas_restart_ioc(mptsas_t *mpt);
1347 1349 void mptsas_update_driver_data(struct mptsas *mpt);
1348 1350 uint64_t mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun);
1349 1351
1350 1352 /*
1351 1353 * init functions
1352 1354 */
1353 1355 int mptsas_ioc_get_facts(mptsas_t *mpt);
1354 1356 int mptsas_ioc_get_port_facts(mptsas_t *mpt, int port);
1355 1357 int mptsas_ioc_enable_port(mptsas_t *mpt);
1356 1358 int mptsas_ioc_enable_event_notification(mptsas_t *mpt);
1357 1359 int mptsas_ioc_init(mptsas_t *mpt);
1358 1360
1359 1361 /*
1360 1362 * configuration pages operation
1361 1363 */
1362 1364 int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address,
1363 1365 uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info,
1364 1366 uint8_t *physport, uint8_t *phynum, uint16_t *pdevhandle,
1365 1367 uint16_t *slot_num, uint16_t *enclosure);
1366 1368 int mptsas_get_sas_io_unit_page(mptsas_t *mpt);
1367 1369 int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt);
1368 1370 int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address,
1369 1371 mptsas_smp_t *info);
1370 1372 int mptsas_set_ioc_params(mptsas_t *mpt);
1371 1373 int mptsas_get_manufacture_page5(mptsas_t *mpt);
1372 1374 int mptsas_get_sas_port_page0(mptsas_t *mpt, uint32_t page_address,
1373 1375 uint64_t *sas_wwn, uint8_t *portwidth);
1374 1376 int mptsas_get_bios_page3(mptsas_t *mpt, uint32_t *bios_version);
1375 1377 int
1376 1378 mptsas_get_sas_phy_page0(mptsas_t *mpt, uint32_t page_address,
1377 1379 smhba_info_t *info);
1378 1380 int
1379 1381 mptsas_get_sas_phy_page1(mptsas_t *mpt, uint32_t page_address,
1380 1382 smhba_info_t *info);
1381 1383 int
1382 1384 mptsas_get_manufacture_page0(mptsas_t *mpt);
1383 1385 void
1384 1386 mptsas_create_phy_stats(mptsas_t *mpt, char *iport, dev_info_t *dip);
1385 1387 void mptsas_destroy_phy_stats(mptsas_t *mpt);
1386 1388 int mptsas_smhba_phy_init(mptsas_t *mpt);
1387 1389 /*
1388 1390 * RAID functions
1389 1391 */
1390 1392 int mptsas_get_raid_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol);
1391 1393 int mptsas_get_raid_info(mptsas_t *mpt);
1392 1394 int mptsas_get_physdisk_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol,
1393 1395 uint8_t physdisknum);
1394 1396 int mptsas_delete_volume(mptsas_t *mpt, uint16_t volid);
1395 1397 void mptsas_raid_action_system_shutdown(mptsas_t *mpt);
1396 1398
1397 1399 #define MPTSAS_IOCSTATUS(status) (status & MPI2_IOCSTATUS_MASK)
1398 1400 /*
1399 1401 * debugging.
1400 1402 */
1401 1403 #if defined(MPTSAS_DEBUG)
1402 1404
1403 1405 void mptsas_printf(char *fmt, ...);
1404 1406
1405 1407 #define MPTSAS_DBGPR(m, args) \
1406 1408 if (mptsas_debug_flags & (m)) \
1407 1409 mptsas_printf args
1408 1410 #else /* ! defined(MPTSAS_DEBUG) */
1409 1411 #define MPTSAS_DBGPR(m, args)
1410 1412 #endif /* defined(MPTSAS_DEBUG) */
1411 1413
1412 1414 #define NDBG0(args) MPTSAS_DBGPR(0x01, args) /* init */
1413 1415 #define NDBG1(args) MPTSAS_DBGPR(0x02, args) /* normal running */
1414 1416 #define NDBG2(args) MPTSAS_DBGPR(0x04, args) /* property handling */
1415 1417 #define NDBG3(args) MPTSAS_DBGPR(0x08, args) /* pkt handling */
1416 1418
1417 1419 #define NDBG4(args) MPTSAS_DBGPR(0x10, args) /* kmem alloc/free */
1418 1420 #define NDBG5(args) MPTSAS_DBGPR(0x20, args) /* polled cmds */
1419 1421 #define NDBG6(args) MPTSAS_DBGPR(0x40, args) /* interrupts */
1420 1422 #define NDBG7(args) MPTSAS_DBGPR(0x80, args) /* queue handling */
1421 1423
1422 1424 #define NDBG8(args) MPTSAS_DBGPR(0x0100, args) /* arq */
1423 1425 #define NDBG9(args) MPTSAS_DBGPR(0x0200, args) /* Tagged Q'ing */
1424 1426 #define NDBG10(args) MPTSAS_DBGPR(0x0400, args) /* halting chip */
1425 1427 #define NDBG11(args) MPTSAS_DBGPR(0x0800, args) /* power management */
1426 1428
1427 1429 #define NDBG12(args) MPTSAS_DBGPR(0x1000, args) /* enumeration */
1428 1430 #define NDBG13(args) MPTSAS_DBGPR(0x2000, args) /* configuration page */
1429 1431 #define NDBG14(args) MPTSAS_DBGPR(0x4000, args) /* LED control */
1430 1432 #define NDBG15(args) MPTSAS_DBGPR(0x8000, args)
1431 1433
1432 1434 #define NDBG16(args) MPTSAS_DBGPR(0x010000, args)
1433 1435 #define NDBG17(args) MPTSAS_DBGPR(0x020000, args) /* scatter/gather */
1434 1436 #define NDBG18(args) MPTSAS_DBGPR(0x040000, args)
1435 1437 #define NDBG19(args) MPTSAS_DBGPR(0x080000, args) /* handshaking */
1436 1438
1437 1439 #define NDBG20(args) MPTSAS_DBGPR(0x100000, args) /* events */
1438 1440 #define NDBG21(args) MPTSAS_DBGPR(0x200000, args) /* dma */
1439 1441 #define NDBG22(args) MPTSAS_DBGPR(0x400000, args) /* reset */
1440 1442 #define NDBG23(args) MPTSAS_DBGPR(0x800000, args) /* abort */
1441 1443
1442 1444 #define NDBG24(args) MPTSAS_DBGPR(0x1000000, args) /* capabilities */
1443 1445 #define NDBG25(args) MPTSAS_DBGPR(0x2000000, args) /* flushing */
1444 1446 #define NDBG26(args) MPTSAS_DBGPR(0x4000000, args)
1445 1447 #define NDBG27(args) MPTSAS_DBGPR(0x8000000, args)
1446 1448
1447 1449 #define NDBG28(args) MPTSAS_DBGPR(0x10000000, args) /* hotplug */
1448 1450 #define NDBG29(args) MPTSAS_DBGPR(0x20000000, args) /* timeouts */
1449 1451 #define NDBG30(args) MPTSAS_DBGPR(0x40000000, args) /* mptsas_watch */
1450 1452 #define NDBG31(args) MPTSAS_DBGPR(0x80000000, args) /* negotations */
1451 1453
1452 1454 /*
1453 1455 * auto request sense
1454 1456 */
1455 1457 #define RQ_MAKECOM_COMMON(pkt, flag, cmd) \
1456 1458 (pkt)->pkt_flags = (flag), \
1457 1459 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_cmd = (cmd), \
1458 1460 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_lun = \
1459 1461 (pkt)->pkt_address.a_lun
1460 1462
1461 1463 #define RQ_MAKECOM_G0(pkt, flag, cmd, addr, cnt) \
1462 1464 RQ_MAKECOM_COMMON((pkt), (flag), (cmd)), \
1463 1465 FORMG0ADDR(((union scsi_cdb *)(pkt)->pkt_cdbp), (addr)), \
1464 1466 FORMG0COUNT(((union scsi_cdb *)(pkt)->pkt_cdbp), (cnt))
1465 1467
1466 1468
1467 1469 #ifdef __cplusplus
1468 1470 }
1469 1471 #endif
1470 1472
1471 1473 #endif /* _SYS_SCSI_ADAPTERS_MPTVAR_H */
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