1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 
  22 /*
  23  * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
  24  * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
  25  * Copyright (c) 2013, Joyent, Inc. All rights reserved.
  26  */
  27 
  28 /*
  29  * Copyright (c) 2000 to 2010, LSI Corporation.
  30  * All rights reserved.
  31  *
  32  * Redistribution and use in source and binary forms of all code within
  33  * this file that is exclusively owned by LSI, with or without
  34  * modification, is permitted provided that, in addition to the CDDL 1.0
  35  * License requirements, the following conditions are met:
  36  *
  37  *    Neither the name of the author nor the names of its contributors may be
  38  *    used to endorse or promote products derived from this software without
  39  *    specific prior written permission.
  40  *
  41  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  42  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  43  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  44  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  45  * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  46  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  47  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  48  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  49  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  50  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  51  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  52  * DAMAGE.
  53  */
  54 
  55 #ifndef _SYS_SCSI_ADAPTERS_MPTVAR_H
  56 #define _SYS_SCSI_ADAPTERS_MPTVAR_H
  57 
  58 #include <sys/byteorder.h>
  59 #include <sys/isa_defs.h>
  60 #include <sys/sunmdi.h>
  61 #include <sys/mdi_impldefs.h>
  62 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h>
  63 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h>
  64 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h>
  65 
  66 #ifdef  __cplusplus
  67 extern "C" {
  68 #endif
  69 
  70 /*
  71  * Compile options
  72  */
  73 #ifdef DEBUG
  74 #define MPTSAS_DEBUG            /* turn on debugging code */
  75 #endif  /* DEBUG */
  76 
  77 #define MPTSAS_INITIAL_SOFT_SPACE       4
  78 
  79 #define MAX_MPI_PORTS           16
  80 
  81 /*
  82  * Note below macro definition and data type definition
  83  * are used for phy mask handling, it should be changed
  84  * simultaneously.
  85  */
  86 #define MPTSAS_MAX_PHYS         16
  87 typedef uint16_t                mptsas_phymask_t;
  88 
  89 #define MPTSAS_INVALID_DEVHDL   0xffff
  90 #define MPTSAS_SATA_GUID        "sata-guid"
  91 
  92 /*
  93  * MPT HW defines
  94  */
  95 #define MPTSAS_MAX_DISKS_IN_CONFIG      14
  96 #define MPTSAS_MAX_DISKS_IN_VOL         10
  97 #define MPTSAS_MAX_HOTSPARES            2
  98 #define MPTSAS_MAX_RAIDVOLS             2
  99 #define MPTSAS_MAX_RAIDCONFIGS          5
 100 
 101 /*
 102  * 64-bit SAS WWN is displayed as 16 characters as HEX characters,
 103  * plus two means the prefix 'w' and end of the string '\0'.
 104  */
 105 #define MPTSAS_WWN_STRLEN       (16 + 2)
 106 #define MPTSAS_MAX_GUID_LEN     64
 107 
 108 /*
 109  * DMA routine flags
 110  */
 111 #define MPTSAS_DMA_HANDLE_ALLOCD        0x2
 112 #define MPTSAS_DMA_MEMORY_ALLOCD        0x4
 113 #define MPTSAS_DMA_HANDLE_BOUND 0x8
 114 
 115 /*
 116  * If the HBA supports DMA or bus-mastering, you may have your own
 117  * scatter-gather list for physically non-contiguous memory in one
 118  * I/O operation; if so, there's probably a size for that list.
 119  * It must be placed in the ddi_dma_lim_t structure, so that the system
 120  * DMA-support routines can use it to break up the I/O request, so we
 121  * define it here.
 122  */
 123 #if defined(__sparc)
 124 #define MPTSAS_MAX_DMA_SEGS     1
 125 #define MPTSAS_MAX_CMD_SEGS     1
 126 #else
 127 #define MPTSAS_MAX_DMA_SEGS     256
 128 #define MPTSAS_MAX_CMD_SEGS     257
 129 #endif
 130 #define MPTSAS_MAX_FRAME_SGES(mpt) \
 131         (((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1)
 132 
 133 /*
 134  * Caculating how many 64-bit DMA simple elements can be stored in the first
 135  * frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for
 136  * element storage.  And 64-bit dma element is 3 double-words (12 bytes) in
 137  * size.
 138  */
 139 #define MPTSAS_MAX_FRAME_SGES64(mpt) \
 140         ((mpt->m_req_frame_size - \
 141         (sizeof (MPI2_SCSI_IO_REQUEST)) + sizeof (MPI2_SGE_IO_UNION)) / 12)
 142 
 143 /*
 144  * Scatter-gather list structure defined by HBA hardware
 145  */
 146 typedef struct NcrTableIndirect {       /* Table Indirect entries */
 147         uint32_t count;         /* 24 bit count */
 148         union {
 149                 uint32_t address32;     /* 32 bit address */
 150                 struct {
 151                         uint32_t Low;
 152                         uint32_t High;
 153                 } address64;            /* 64 bit address */
 154         } addr;
 155 } mptti_t;
 156 
 157 /*
 158  * preferred pkt_private length in 64-bit quantities
 159  */
 160 #ifdef  _LP64
 161 #define PKT_PRIV_SIZE   2
 162 #define PKT_PRIV_LEN    16      /* in bytes */
 163 #else /* _ILP32 */
 164 #define PKT_PRIV_SIZE   1
 165 #define PKT_PRIV_LEN    8       /* in bytes */
 166 #endif
 167 
 168 #define PKT2CMD(pkt)    ((struct mptsas_cmd *)((pkt)->pkt_ha_private))
 169 #define CMD2PKT(cmdp)   ((struct scsi_pkt *)((cmdp)->cmd_pkt))
 170 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status))
 171 
 172 /*
 173  * get offset of item in structure
 174  */
 175 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member))
 176 
 177 /*
 178  * WWID provided by LSI firmware is generated by firmware but the WWID is not
 179  * IEEE NAA standard format, OBP has no chance to distinguish format of unit
 180  * address. According LSI's confirmation, the top nibble of RAID WWID is
 181  * meanless, so the consensus between Solaris and OBP is to replace top nibble
 182  * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID
 183  * format unit address.
 184  */
 185 #define MPTSAS_RAID_WWID(wwid) \
 186         ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000)
 187 
 188 typedef struct mptsas_target {
 189                 uint64_t                m_sas_wwn;      /* hash key1 */
 190                 mptsas_phymask_t        m_phymask;      /* hash key2 */
 191                 /*
 192                  * m_dr_flag is a flag for DR, make sure the member
 193                  * take the place of dr_flag of mptsas_hash_data.
 194                  */
 195                 uint8_t                 m_dr_flag;      /* dr_flag */
 196                 uint16_t                m_devhdl;
 197                 uint32_t                m_deviceinfo;
 198                 uint8_t                 m_phynum;
 199                 uint32_t                m_dups;
 200                 int32_t                 m_timeout;
 201                 int32_t                 m_timebase;
 202                 int32_t                 m_t_throttle;
 203                 int32_t                 m_t_ncmds;
 204                 int32_t                 m_reset_delay;
 205                 int32_t                 m_t_nwait;
 206 
 207                 uint16_t                m_qfull_retry_interval;
 208                 uint8_t                 m_qfull_retries;
 209                 uint16_t                m_enclosure;
 210                 uint16_t                m_slot_num;
 211                 uint32_t                m_tgt_unconfigured;
 212                 uint8_t                 m_led_status;
 213 
 214                 /*
 215                  * For the common case, the elements in this structure are
 216                  * protected by the per hba instance mutex. In order to make
 217                  * the key code path in ISR lockless, a separate mutex is
 218                  * introdeced to protect those shown in ISR.
 219                  */
 220                 kmutex_t                m_tgt_intr_mutex;
 221 
 222 } mptsas_target_t;
 223 
 224 typedef struct mptsas_smp {
 225         uint64_t        m_sasaddr;      /* hash key1 */
 226         mptsas_phymask_t m_phymask;     /* hash key2 */
 227         uint8_t         reserved1;
 228         uint16_t        m_devhdl;
 229         uint32_t        m_deviceinfo;
 230         uint16_t        m_pdevhdl;
 231         uint32_t        m_pdevinfo;
 232 } mptsas_smp_t;
 233 
 234 typedef struct mptsas_hash_data {
 235         uint64_t        key1;
 236         mptsas_phymask_t key2;
 237         uint8_t         dr_flag;
 238         uint16_t        devhdl;
 239         uint32_t        device_info;
 240 } mptsas_hash_data_t;
 241 
 242 typedef struct mptsas_cache_frames {
 243         ddi_dma_handle_t m_dma_hdl;
 244         ddi_acc_handle_t m_acc_hdl;
 245         caddr_t m_frames_addr;
 246         uint32_t m_phys_addr;
 247 } mptsas_cache_frames_t;
 248 
 249 typedef struct  mptsas_cmd {
 250         uint_t                  cmd_flags;      /* flags from scsi_init_pkt */
 251         ddi_dma_handle_t        cmd_dmahandle;  /* dma handle */
 252         ddi_dma_cookie_t        cmd_cookie;
 253         uint_t                  cmd_cookiec;
 254         uint_t                  cmd_winindex;
 255         uint_t                  cmd_nwin;
 256         uint_t                  cmd_cur_cookie;
 257         off_t                   cmd_dma_offset;
 258         size_t                  cmd_dma_len;
 259         uint32_t                cmd_totaldmacount;
 260 
 261         ddi_dma_handle_t        cmd_arqhandle;  /* dma arq handle */
 262         ddi_dma_cookie_t        cmd_arqcookie;
 263         struct buf              *cmd_arq_buf;
 264         ddi_dma_handle_t        cmd_ext_arqhandle; /* dma extern arq handle */
 265         ddi_dma_cookie_t        cmd_ext_arqcookie;
 266         struct buf              *cmd_ext_arq_buf;
 267 
 268         int                     cmd_pkt_flags;
 269 
 270         /* timer for command in active slot */
 271         int                     cmd_active_timeout;
 272 
 273         struct scsi_pkt         *cmd_pkt;
 274         struct scsi_arq_status  cmd_scb;
 275         uchar_t                 cmd_cdblen;     /* length of cdb */
 276         uchar_t                 cmd_rqslen;     /* len of requested rqsense */
 277         uchar_t                 cmd_privlen;
 278         uint_t                  cmd_scblen;
 279         uint32_t                cmd_dmacount;
 280         uint64_t                cmd_dma_addr;
 281         uchar_t                 cmd_age;
 282         ushort_t                cmd_qfull_retries;
 283         uchar_t                 cmd_queued;     /* true if queued */
 284         struct mptsas_cmd       *cmd_linkp;
 285         mptti_t                 *cmd_sg; /* Scatter/Gather structure */
 286         uchar_t                 cmd_cdb[SCSI_CDB_SIZE];
 287         uint64_t                cmd_pkt_private[PKT_PRIV_LEN];
 288         uint32_t                cmd_slot;
 289         uint32_t                ioc_cmd_slot;
 290 
 291         mptsas_cache_frames_t   *cmd_extra_frames;
 292 
 293         uint32_t                cmd_rfm;
 294         mptsas_target_t         *cmd_tgt_addr;
 295 } mptsas_cmd_t;
 296 
 297 /*
 298  * These are the defined cmd_flags for this structure.
 299  */
 300 #define CFLAG_CMDDISC           0x000001 /* cmd currently disconnected */
 301 #define CFLAG_WATCH             0x000002 /* watchdog time for this command */
 302 #define CFLAG_FINISHED          0x000004 /* command completed */
 303 #define CFLAG_CHKSEG            0x000008 /* check cmd_data within seg */
 304 #define CFLAG_COMPLETED         0x000010 /* completion routine called */
 305 #define CFLAG_PREPARED          0x000020 /* pkt has been init'ed */
 306 #define CFLAG_IN_TRANSPORT      0x000040 /* in use by host adapter driver */
 307 #define CFLAG_RESTORE_PTRS      0x000080 /* implicit restore ptr on reconnect */
 308 #define CFLAG_ARQ_IN_PROGRESS   0x000100 /* auto request sense in progress */
 309 #define CFLAG_TRANFLAG          0x0001ff /* covers transport part of flags */
 310 #define CFLAG_TM_CMD            0x000200 /* cmd is a task management command */
 311 #define CFLAG_CMDARQ            0x000400 /* cmd is a 'rqsense' command */
 312 #define CFLAG_DMAVALID          0x000800 /* dma mapping valid */
 313 #define CFLAG_DMASEND           0x001000 /* data is going 'out' */
 314 #define CFLAG_CMDIOPB           0x002000 /* this is an 'iopb' packet */
 315 #define CFLAG_CDBEXTERN         0x004000 /* cdb kmem_alloc'd */
 316 #define CFLAG_SCBEXTERN         0x008000 /* scb kmem_alloc'd */
 317 #define CFLAG_FREE              0x010000 /* packet is on free list */
 318 #define CFLAG_PRIVEXTERN        0x020000 /* target private kmem_alloc'd */
 319 #define CFLAG_DMA_PARTIAL       0x040000 /* partial xfer OK */
 320 #define CFLAG_QFULL_STATUS      0x080000 /* pkt got qfull status */
 321 #define CFLAG_TIMEOUT           0x100000 /* passthru/config command timeout */
 322 #define CFLAG_PMM_RECEIVED      0x200000 /* use cmd_pmm* for saving pointers */
 323 #define CFLAG_RETRY             0x400000 /* cmd has been retried */
 324 #define CFLAG_CMDIOC            0x800000 /* cmd is just for for ioc, no io */
 325 #define CFLAG_EXTARQBUFVALID    0x1000000 /* extern arq buf handle is valid */
 326 #define CFLAG_PASSTHRU          0x2000000 /* cmd is a passthrough command */
 327 #define CFLAG_XARQ              0x4000000 /* cmd requests for extra sense */
 328 #define CFLAG_CMDACK            0x8000000 /* cmd for event ack */
 329 #define CFLAG_TXQ               0x10000000 /* cmd queued in the tx_waitq */
 330 #define CFLAG_FW_CMD            0x20000000 /* cmd is a fw up/down command */
 331 #define CFLAG_CONFIG            0x40000000 /* cmd is for config header/page */
 332 #define CFLAG_FW_DIAG           0x80000000 /* cmd is for FW diag buffers */
 333 
 334 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE                     8
 335 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK                     0xC0
 336 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL                       0x00
 337 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE                       0x40
 338 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT             0x80
 339 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_EXTENDED_UNIT            0xC0
 340 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_2B          0x00
 341 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_4B          0x01
 342 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_6B          0x10
 343 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_8B          0x20
 344 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_SIZE                0x30
 345 
 346 #define MPTSAS_HASH_ARRAY_SIZE  16
 347 /*
 348  * hash table definition
 349  */
 350 
 351 #define MPTSAS_HASH_FIRST       0xffff
 352 #define MPTSAS_HASH_NEXT        0x0000
 353 
 354 typedef struct mptsas_dma_alloc_state
 355 {
 356         ddi_dma_handle_t        handle;
 357         caddr_t                 memp;
 358         size_t                  size;
 359         ddi_acc_handle_t        accessp;
 360         ddi_dma_cookie_t        cookie;
 361 } mptsas_dma_alloc_state_t;
 362 
 363 /*
 364  * passthrough request structure
 365  */
 366 typedef struct mptsas_pt_request {
 367         uint8_t *request;
 368         uint32_t request_size;
 369         uint32_t data_size;
 370         uint32_t dataout_size;
 371         uint32_t direction;
 372         ddi_dma_cookie_t data_cookie;
 373         ddi_dma_cookie_t dataout_cookie;
 374 } mptsas_pt_request_t;
 375 
 376 /*
 377  * config page request structure
 378  */
 379 typedef struct mptsas_config_request {
 380         uint32_t        page_address;
 381         uint8_t         action;
 382         uint8_t         page_type;
 383         uint8_t         page_number;
 384         uint8_t         page_length;
 385         uint8_t         page_version;
 386         uint8_t         ext_page_type;
 387         uint16_t        ext_page_length;
 388 } mptsas_config_request_t;
 389 
 390 typedef struct mptsas_fw_diagnostic_buffer {
 391         mptsas_dma_alloc_state_t        buffer_data;
 392         uint8_t                         extended_type;
 393         uint8_t                         buffer_type;
 394         uint8_t                         force_release;
 395         uint32_t                        product_specific[23];
 396         uint8_t                         immediate;
 397         uint8_t                         enabled;
 398         uint8_t                         valid_data;
 399         uint8_t                         owned_by_firmware;
 400         uint32_t                        unique_id;
 401 } mptsas_fw_diagnostic_buffer_t;
 402 
 403 /*
 404  * FW diag request structure
 405  */
 406 typedef struct mptsas_diag_request {
 407         mptsas_fw_diagnostic_buffer_t   *pBuffer;
 408         uint8_t                         function;
 409 } mptsas_diag_request_t;
 410 
 411 typedef struct mptsas_hash_node {
 412         void *data;
 413         struct mptsas_hash_node *next;
 414 } mptsas_hash_node_t;
 415 
 416 typedef struct mptsas_hash_table {
 417         struct mptsas_hash_node *head[MPTSAS_HASH_ARRAY_SIZE];
 418         /*
 419          * last position in traverse
 420          */
 421         struct mptsas_hash_node *cur;
 422         uint16_t line;
 423 
 424 } mptsas_hash_table_t;
 425 
 426 /*
 427  * RAID volume information
 428  */
 429 typedef struct mptsas_raidvol {
 430         ushort_t        m_israid;
 431         uint16_t        m_raidhandle;
 432         uint64_t        m_raidwwid;
 433         uint8_t         m_state;
 434         uint32_t        m_statusflags;
 435         uint32_t        m_settings;
 436         uint16_t        m_devhdl[MPTSAS_MAX_DISKS_IN_VOL];
 437         uint8_t         m_disknum[MPTSAS_MAX_DISKS_IN_VOL];
 438         ushort_t        m_diskstatus[MPTSAS_MAX_DISKS_IN_VOL];
 439         uint64_t        m_raidsize;
 440         int             m_raidlevel;
 441         int             m_ndisks;
 442         mptsas_target_t *m_raidtgt;
 443 } mptsas_raidvol_t;
 444 
 445 /*
 446  * RAID configurations
 447  */
 448 typedef struct mptsas_raidconfig {
 449                 mptsas_raidvol_t        m_raidvol[MPTSAS_MAX_RAIDVOLS];
 450                 uint16_t                m_physdisk_devhdl[
 451                                             MPTSAS_MAX_DISKS_IN_CONFIG];
 452                 uint8_t                 m_native;
 453 } m_raidconfig_t;
 454 
 455 /*
 456  * Structure to hold active outstanding cmds.  Also, keep
 457  * timeout on a per target basis.
 458  */
 459 typedef struct mptsas_slots {
 460         mptsas_hash_table_t     m_tgttbl;
 461         mptsas_hash_table_t     m_smptbl;
 462         m_raidconfig_t          m_raidconfig[MPTSAS_MAX_RAIDCONFIGS];
 463         uint8_t                 m_num_raid_configs;
 464         uint16_t                m_tags;
 465         size_t                  m_size;
 466         uint16_t                m_n_slots;
 467         mptsas_cmd_t            *m_slot[1];
 468 } mptsas_slots_t;
 469 
 470 /*
 471  * Structure to hold command and packets for event ack
 472  * and task management commands.
 473  */
 474 typedef struct  m_event_struct {
 475         struct mptsas_cmd               m_event_cmd;
 476         struct m_event_struct   *m_event_linkp;
 477         /*
 478          * event member record the failure event and eventcntx
 479          * event member would be used in send ack pending process
 480          */
 481         uint32_t                m_event;
 482         uint32_t                m_eventcntx;
 483         uint_t                  in_use;
 484         struct scsi_pkt         m_event_pkt;    /* must be last */
 485                                                 /* ... scsi_pkt_size() */
 486 } m_event_struct_t;
 487 #define M_EVENT_STRUCT_SIZE     (sizeof (m_event_struct_t) - \
 488                                 sizeof (struct scsi_pkt) + scsi_pkt_size())
 489 
 490 #define MAX_IOC_COMMANDS        8
 491 
 492 /*
 493  * A pool of MAX_IOC_COMMANDS is maintained for event ack commands.
 494  * A new event ack command requests mptsas_cmd and scsi_pkt structures
 495  * from this pool, and returns it back when done.
 496  */
 497 
 498 typedef struct m_replyh_arg {
 499         void *mpt;
 500         uint32_t rfm;
 501 } m_replyh_arg_t;
 502 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::mpt))
 503 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::rfm))
 504 
 505 /*
 506  * Flags for DR handler topology change
 507  */
 508 #define MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE         0x0
 509 #define MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED            0x1
 510 #define MPTSAS_TOPO_FLAG_LUN_ASSOCIATED                 0x2
 511 #define MPTSAS_TOPO_FLAG_RAID_ASSOCIATED                0x4
 512 #define MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED        0x8
 513 #define MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE       0x10
 514 
 515 typedef struct mptsas_topo_change_list {
 516         void *mpt;
 517         uint_t  event;
 518         union {
 519                 uint8_t physport;
 520                 mptsas_phymask_t phymask;
 521         } un;
 522         uint16_t devhdl;
 523         void *object;
 524         uint8_t flags;
 525         struct mptsas_topo_change_list *next;
 526 } mptsas_topo_change_list_t;
 527 
 528 
 529 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::mpt))
 530 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::event))
 531 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::physport))
 532 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::devhdl))
 533 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::object))
 534 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::flags))
 535 
 536 /*
 537  * Status types when calling mptsas_get_target_device_info
 538  */
 539 #define DEV_INFO_SUCCESS                0x0
 540 #define DEV_INFO_FAIL_PAGE0             0x1
 541 #define DEV_INFO_WRONG_DEVICE_TYPE      0x2
 542 #define DEV_INFO_PHYS_DISK              0x3
 543 #define DEV_INFO_FAIL_ALLOC             0x4
 544 
 545 /*
 546  * mpt hotplug event defines
 547  */
 548 #define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01
 549 #define MPTSAS_DR_EVENT_OFFLINE_TARGET  0x02
 550 #define MPTSAS_TOPO_FLAG_REMOVE_HANDLE  0x04
 551 
 552 /*
 553  * SMP target hotplug events
 554  */
 555 #define MPTSAS_DR_EVENT_RECONFIG_SMP    0x10
 556 #define MPTSAS_DR_EVENT_OFFLINE_SMP     0x20
 557 #define MPTSAS_DR_EVENT_MASK            0x3F
 558 
 559 /*
 560  * mpt hotplug status definition for m_dr_flag
 561  */
 562 
 563 /*
 564  * MPTSAS_DR_INACTIVE
 565  *
 566  * The target is in a normal operating state.
 567  * No dynamic reconfiguration operation is in progress.
 568  */
 569 #define MPTSAS_DR_INACTIVE                              0x0
 570 /*
 571  * MPTSAS_DR_INTRANSITION
 572  *
 573  * The target is in a transition mode since
 574  * hotplug event happens and offline procedure has not
 575  * been finished
 576  */
 577 #define MPTSAS_DR_INTRANSITION                  0x1
 578 
 579 typedef struct mptsas_tgt_private {
 580         int t_lun;
 581         struct mptsas_target *t_private;
 582 } mptsas_tgt_private_t;
 583 
 584 /*
 585  * The following defines are used in mptsas_set_init_mode to track the current
 586  * state as we progress through reprogramming the HBA from target mode into
 587  * initiator mode.
 588  */
 589 
 590 #define IOUC_READ_PAGE0         0x00000100
 591 #define IOUC_READ_PAGE1         0x00000200
 592 #define IOUC_WRITE_PAGE1        0x00000400
 593 #define IOUC_DONE               0x00000800
 594 #define DISCOVERY_IN_PROGRESS   MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS
 595 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG
 596 
 597 /*
 598  * Last allocated slot is used for TM requests.  Since only m_max_requests
 599  * frames are allocated, the last SMID will be m_max_requests - 1.
 600  */
 601 #define MPTSAS_SLOTS_SIZE(mpt) \
 602         (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \
 603                 mpt->m_max_requests))
 604 #define MPTSAS_TM_SLOT(mpt)     (mpt->m_max_requests - 1)
 605 
 606 typedef struct mptsas_slot_free_e {
 607         processorid_t           cpuid;
 608         int                     slot;
 609         list_node_t             node;
 610 } mptsas_slot_free_e_t;
 611 
 612 /*
 613  * each of the allocq and releaseq in all CPU groups resides in separate
 614  * cacheline(64 bytes). Multiple mutex in the same cacheline is not good
 615  * for performance.
 616  */
 617 typedef union mptsas_slot_freeq {
 618         struct {
 619                 kmutex_t        m_fq_mutex;
 620                 list_t          m_fq_list;
 621                 int             m_fq_n;
 622                 int             m_fq_n_init;
 623         } s;
 624         char pad[64];
 625 } mptsas_slot_freeq_t;
 626 
 627 typedef struct mptsas_slot_freeq_pair {
 628         mptsas_slot_freeq_t     m_slot_allocq;
 629         mptsas_slot_freeq_t     m_slot_releq;
 630 } mptsas_slot_freeq_pair_t;
 631 
 632 /*
 633  * Macro for phy_flags
 634  */
 635 
 636 typedef struct smhba_info {
 637         kmutex_t        phy_mutex;
 638         uint8_t         phy_id;
 639         uint64_t        sas_addr;
 640         char            path[8];
 641         uint16_t        owner_devhdl;
 642         uint16_t        attached_devhdl;
 643         uint8_t         attached_phy_identify;
 644         uint32_t        attached_phy_info;
 645         uint8_t         programmed_link_rate;
 646         uint8_t         hw_link_rate;
 647         uint8_t         change_count;
 648         uint32_t        phy_info;
 649         uint8_t         negotiated_link_rate;
 650         uint8_t         port_num;
 651         kstat_t         *phy_stats;
 652         uint32_t        invalid_dword_count;
 653         uint32_t        running_disparity_error_count;
 654         uint32_t        loss_of_dword_sync_count;
 655         uint32_t        phy_reset_problem_count;
 656         void            *mpt;
 657 } smhba_info_t;
 658 
 659 typedef struct mptsas_phy_info {
 660         uint8_t                 port_num;
 661         uint8_t                 port_flags;
 662         uint16_t                ctrl_devhdl;
 663         uint32_t                phy_device_type;
 664         uint16_t                attached_devhdl;
 665         mptsas_phymask_t        phy_mask;
 666         smhba_info_t            smhba_info;
 667 } mptsas_phy_info_t;
 668 
 669 
 670 typedef struct mptsas_doneq_thread_arg {
 671         void            *mpt;
 672         uint64_t        t;
 673 } mptsas_doneq_thread_arg_t;
 674 
 675 #define MPTSAS_DONEQ_THREAD_ACTIVE      0x1
 676 typedef struct mptsas_doneq_thread_list {
 677         mptsas_cmd_t            *doneq;
 678         mptsas_cmd_t            **donetail;
 679         kthread_t               *threadp;
 680         kcondvar_t              cv;
 681         ushort_t                reserv1;
 682         uint32_t                reserv2;
 683         kmutex_t                mutex;
 684         uint32_t                flag;
 685         uint32_t                len;
 686         mptsas_doneq_thread_arg_t       arg;
 687 } mptsas_doneq_thread_list_t;
 688 
 689 typedef struct mptsas {
 690         int             m_instance;
 691 
 692         struct mptsas *m_next;
 693 
 694         scsi_hba_tran_t         *m_tran;
 695         smp_hba_tran_t          *m_smptran;
 696         kmutex_t                m_mutex;
 697         kcondvar_t              m_cv;
 698         kcondvar_t              m_fw_cv;
 699         kcondvar_t              m_config_cv;
 700         kcondvar_t              m_fw_diag_cv;
 701         dev_info_t              *m_dip;
 702 
 703         /*
 704          * soft state flags
 705          */
 706         uint_t          m_softstate;
 707 
 708         struct mptsas_slots *m_active;  /* outstanding cmds */
 709 
 710         mptsas_cmd_t    *m_waitq;       /* cmd queue for active request */
 711         mptsas_cmd_t    **m_waitqtail;  /* wait queue tail ptr */
 712 
 713         mptsas_cmd_t    *m_doneq;       /* queue of completed commands */
 714         mptsas_cmd_t    **m_donetail;   /* queue tail ptr */
 715 
 716         kmutex_t                m_passthru_mutex;
 717         kcondvar_t              m_passthru_cv;
 718         /*
 719          * variables for helper threads (fan-out interrupts)
 720          */
 721         mptsas_doneq_thread_list_t      *m_doneq_thread_id;
 722         uint32_t                m_doneq_thread_n;
 723         uint32_t                m_doneq_thread_threshold;
 724         uint32_t                m_doneq_length_threshold;
 725         uint32_t                m_doneq_len;
 726         kcondvar_t              m_doneq_thread_cv;
 727         kmutex_t                m_doneq_mutex;
 728 
 729         int             m_ncmds;        /* number of outstanding commands */
 730         m_event_struct_t *m_ioc_event_cmdq;     /* cmd queue for ioc event */
 731         m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */
 732 
 733         ddi_acc_handle_t m_datap;       /* operating regs data access handle */
 734 
 735         struct _MPI2_SYSTEM_INTERFACE_REGS      *m_reg;
 736 
 737         ushort_t        m_devid;        /* device id of chip. */
 738         uchar_t         m_revid;        /* revision of chip. */
 739         uint16_t        m_svid;         /* subsystem Vendor ID of chip */
 740         uint16_t        m_ssid;         /* subsystem Device ID of chip */
 741 
 742         uchar_t         m_sync_offset;  /* default offset for this chip. */
 743 
 744         timeout_id_t    m_quiesce_timeid;
 745 
 746         ddi_dma_handle_t m_dma_req_frame_hdl;
 747         ddi_acc_handle_t m_acc_req_frame_hdl;
 748         ddi_dma_handle_t m_dma_reply_frame_hdl;
 749         ddi_acc_handle_t m_acc_reply_frame_hdl;
 750         ddi_dma_handle_t m_dma_free_queue_hdl;
 751         ddi_acc_handle_t m_acc_free_queue_hdl;
 752         ddi_dma_handle_t m_dma_post_queue_hdl;
 753         ddi_acc_handle_t m_acc_post_queue_hdl;
 754 
 755         /*
 756          * Try the best to make the key code path in the ISR lockless.
 757          * so avoid to use the per instance mutex m_mutex in the ISR. Introduce
 758          * a separate mutex to protect the elements shown in ISR.
 759          */
 760         kmutex_t        m_intr_mutex;
 761 
 762         /*
 763          * list of reset notification requests
 764          */
 765         struct scsi_reset_notify_entry  *m_reset_notify_listf;
 766 
 767         /*
 768          * qfull handling
 769          */
 770         timeout_id_t    m_restart_cmd_timeid;
 771 
 772         /*
 773          * scsi reset delay per bus
 774          */
 775         uint_t          m_scsi_reset_delay;
 776 
 777         int             m_pm_idle_delay;
 778 
 779         uchar_t         m_polled_intr;  /* intr was polled. */
 780         uchar_t         m_suspended;    /* true if driver is suspended */
 781 
 782         struct kmem_cache *m_kmem_cache;
 783         struct kmem_cache *m_cache_frames;
 784 
 785         /*
 786          * hba options.
 787          */
 788         uint_t          m_options;
 789 
 790         int             m_in_callback;
 791 
 792         int             m_power_level;  /* current power level */
 793 
 794         int             m_busy;         /* power management busy state */
 795 
 796         off_t           m_pmcsr_offset; /* PMCSR offset */
 797 
 798         ddi_acc_handle_t m_config_handle;
 799 
 800         ddi_dma_attr_t          m_io_dma_attr;  /* Used for data I/O */
 801         ddi_dma_attr_t          m_msg_dma_attr; /* Used for message frames */
 802         ddi_device_acc_attr_t   m_dev_acc_attr;
 803         ddi_device_acc_attr_t   m_reg_acc_attr;
 804 
 805         /*
 806          * request/reply variables
 807          */
 808         caddr_t         m_req_frame;
 809         uint64_t        m_req_frame_dma_addr;
 810         caddr_t         m_reply_frame;
 811         uint64_t        m_reply_frame_dma_addr;
 812         caddr_t         m_free_queue;
 813         uint64_t        m_free_queue_dma_addr;
 814         caddr_t         m_post_queue;
 815         uint64_t        m_post_queue_dma_addr;
 816 
 817         m_replyh_arg_t *m_replyh_args;
 818 
 819         uint16_t        m_max_requests;
 820         uint16_t        m_req_frame_size;
 821 
 822         /*
 823          * Max frames per request reprted in IOC Facts
 824          */
 825         uint8_t         m_max_chain_depth;
 826         /*
 827          * Max frames per request which is used in reality. It's adjusted
 828          * according DMA SG length attribute, and shall not exceed the
 829          * m_max_chain_depth.
 830          */
 831         uint8_t         m_max_request_frames;
 832 
 833         uint16_t        m_free_queue_depth;
 834         uint16_t        m_post_queue_depth;
 835         uint16_t        m_max_replies;
 836         uint32_t        m_free_index;
 837         uint32_t        m_post_index;
 838         uint8_t         m_reply_frame_size;
 839         uint32_t        m_ioc_capabilities;
 840 
 841         /*
 842          * indicates if the firmware was upload by the driver
 843          * at boot time
 844          */
 845         ushort_t        m_fwupload;
 846 
 847         uint16_t        m_productid;
 848 
 849         /*
 850          * per instance data structures for dma memory resources for
 851          * MPI handshake protocol. only one handshake cmd can run at a time.
 852          */
 853         ddi_dma_handle_t        m_hshk_dma_hdl;
 854 
 855         ddi_acc_handle_t        m_hshk_acc_hdl;
 856 
 857         caddr_t                 m_hshk_memp;
 858 
 859         size_t                  m_hshk_dma_size;
 860 
 861         /* Firmware version on the card at boot time */
 862         uint32_t                m_fwversion;
 863 
 864         /* MSI specific fields */
 865         ddi_intr_handle_t       *m_htable;      /* For array of interrupts */
 866         int                     m_intr_type;    /* What type of interrupt */
 867         int                     m_intr_cnt;     /* # of intrs count returned */
 868         size_t                  m_intr_size;    /* Size of intr array */
 869         uint_t                  m_intr_pri;     /* Interrupt priority   */
 870         int                     m_intr_cap;     /* Interrupt capabilities */
 871         ddi_taskq_t             *m_event_taskq;
 872 
 873         /* SAS specific information */
 874 
 875         union {
 876                 uint64_t        m_base_wwid;    /* Base WWID */
 877                 struct {
 878 #ifdef _BIG_ENDIAN
 879                         uint32_t        m_base_wwid_hi;
 880                         uint32_t        m_base_wwid_lo;
 881 #else
 882                         uint32_t        m_base_wwid_lo;
 883                         uint32_t        m_base_wwid_hi;
 884 #endif
 885                 } sasaddr;
 886         } un;
 887 
 888         uint8_t                 m_num_phys;             /* # of PHYs */
 889         mptsas_phy_info_t       m_phy_info[MPTSAS_MAX_PHYS];
 890         uint8_t                 m_port_chng;    /* initiator port changes */
 891         MPI2_CONFIG_PAGE_MAN_0   m_MANU_page0;   /* Manufactor page 0 info */
 892         MPI2_CONFIG_PAGE_MAN_1   m_MANU_page1;   /* Manufactor page 1 info */
 893 
 894         /* FMA Capabilities */
 895         int                     m_fm_capabilities;
 896         ddi_taskq_t             *m_dr_taskq;
 897         int                     m_mpxio_enable;
 898         uint8_t                 m_done_traverse_dev;
 899         uint8_t                 m_done_traverse_smp;
 900         int                     m_diag_action_in_progress;
 901         uint16_t                m_dev_handle;
 902         uint16_t                m_smp_devhdl;
 903 
 904         /*
 905          * Event recording
 906          */
 907         uint8_t                 m_event_index;
 908         uint32_t                m_event_number;
 909         uint32_t                m_event_mask[4];
 910         mptsas_event_entry_t    m_events[MPTSAS_EVENT_QUEUE_SIZE];
 911 
 912         /*
 913          * FW diag Buffer List
 914          */
 915         mptsas_fw_diagnostic_buffer_t
 916                 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT];
 917 
 918         /*
 919          * Event Replay flag (MUR support)
 920          */
 921         uint8_t                 m_event_replay;
 922 
 923         /*
 924          * IR Capable flag
 925          */
 926         uint8_t                 m_ir_capable;
 927 
 928         /*
 929          * release and alloc queue for slot
 930          */
 931         int                     m_slot_freeq_pair_n;
 932         mptsas_slot_freeq_pair_t        *m_slot_freeq_pairp;
 933         mptsas_slot_free_e_t    *m_slot_free_ae;
 934 #define MPI_ADDRESS_COALSCE_MAX 128
 935         pMpi2ReplyDescriptorsUnion_t    m_reply;
 936 
 937         /*
 938          * Is HBA processing a diag reset?
 939          */
 940         uint8_t                 m_in_reset;
 941 
 942         /*
 943          * per instance cmd data structures for task management cmds
 944          */
 945         m_event_struct_t        m_event_task_mgmt;      /* must be last */
 946                                                         /* ... scsi_pkt_size */
 947 } mptsas_t;
 948 #define MPTSAS_SIZE     (sizeof (struct mptsas) - \
 949                         sizeof (struct scsi_pkt) + scsi_pkt_size())
 950 /*
 951  * Only one of below two conditions is satisfied, we
 952  * think the target is associated to the iport and
 953  * allow call into mptsas_probe_lun().
 954  * 1. physicalsport == physport
 955  * 2. (phymask & (1 << physport)) == 0
 956  * The condition #2 is because LSI uses lowest PHY
 957  * number as the value of physical port when auto port
 958  * configuration.
 959  */
 960 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \
 961         ((physicalport == physport) || (dynamicport && (phymask & \
 962         (1 << physport))))
 963 
 964 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas))
 965 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next))
 966 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran))
 967 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_kmem_cache))
 968 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_io_dma_attr.dma_attr_sgllen))
 969 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_devid))
 970 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_productid))
 971 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_port_type))
 972 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_mpxio_enable))
 973 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_ntargets))
 974 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_instance))
 975 
 976 /*
 977  * These should eventually migrate into the mpt header files
 978  * that may become the /kernel/misc/mpt module...
 979  */
 980 #define mptsas_init_std_hdr(hdl, mp, DevHandle, Lun, ChainOffset, Function) \
 981         mptsas_put_msg_DevHandle(hdl, mp, DevHandle); \
 982         mptsas_put_msg_ChainOffset(hdl, mp, ChainOffset); \
 983         mptsas_put_msg_Function(hdl, mp, Function); \
 984         mptsas_put_msg_Lun(hdl, mp, Lun)
 985 
 986 #define mptsas_put_msg_DevHandle(hdl, mp, val) \
 987         ddi_put16(hdl, &(mp)->DevHandle, (val))
 988 #define mptsas_put_msg_ChainOffset(hdl, mp, val) \
 989         ddi_put8(hdl, &(mp)->ChainOffset, (val))
 990 #define mptsas_put_msg_Function(hdl, mp, val) \
 991         ddi_put8(hdl, &(mp)->Function, (val))
 992 #define mptsas_put_msg_Lun(hdl, mp, val) \
 993         ddi_put8(hdl, &(mp)->LUN[1], (val))
 994 
 995 #define mptsas_get_msg_Function(hdl, mp) \
 996         ddi_get8(hdl, &(mp)->Function)
 997 
 998 #define mptsas_get_msg_MsgFlags(hdl, mp) \
 999         ddi_get8(hdl, &(mp)->MsgFlags)
1000 
1001 #define MPTSAS_ENABLE_DRWE(hdl) \
1002         ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1003                 MPI2_WRSEQ_FLUSH_KEY_VALUE); \
1004         ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1005                 MPI2_WRSEQ_1ST_KEY_VALUE); \
1006         ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1007                 MPI2_WRSEQ_2ND_KEY_VALUE); \
1008         ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1009                 MPI2_WRSEQ_3RD_KEY_VALUE); \
1010         ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1011                 MPI2_WRSEQ_4TH_KEY_VALUE); \
1012         ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1013                 MPI2_WRSEQ_5TH_KEY_VALUE); \
1014         ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1015                 MPI2_WRSEQ_6TH_KEY_VALUE);
1016 
1017 /*
1018  * m_options flags
1019  */
1020 #define MPTSAS_OPT_PM           0x01    /* Power Management */
1021 
1022 /*
1023  * m_softstate flags
1024  */
1025 #define MPTSAS_SS_DRAINING              0x02
1026 #define MPTSAS_SS_QUIESCED              0x04
1027 #define MPTSAS_SS_MSG_UNIT_RESET        0x08
1028 #define MPTSAS_DID_MSG_UNIT_RESET       0x10
1029 
1030 /*
1031  * regspec defines.
1032  */
1033 #define CONFIG_SPACE    0       /* regset[0] - configuration space */
1034 #define IO_SPACE        1       /* regset[1] - used for i/o mapped device */
1035 #define MEM_SPACE       2       /* regset[2] - used for memory mapped device */
1036 #define BASE_REG2       3       /* regset[3] - used for 875 scripts ram */
1037 
1038 /*
1039  * Handy constants
1040  */
1041 #define FALSE           0
1042 #define TRUE            1
1043 #define UNDEFINED       -1
1044 #define FAILED          -2
1045 
1046 /*
1047  * power management.
1048  */
1049 #define MPTSAS_POWER_ON(mpt) { \
1050         pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \
1051             PCI_PMCSR_D0); \
1052         delay(drv_usectohz(10000)); \
1053         (void) pci_restore_config_regs(mpt->m_dip); \
1054         mptsas_setup_cmd_reg(mpt); \
1055 }
1056 
1057 #define MPTSAS_POWER_OFF(mpt) { \
1058         (void) pci_save_config_regs(mpt->m_dip); \
1059         pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \
1060             PCI_PMCSR_D3HOT); \
1061         mpt->m_power_level = PM_LEVEL_D3; \
1062 }
1063 
1064 /*
1065  * inq_dtype:
1066  * Bits 5 through 7 are the Peripheral Device Qualifier
1067  * 001b: device not connected to the LUN
1068  * Bits 0 through 4 are the Peripheral Device Type
1069  * 1fh: Unknown or no device type
1070  *
1071  * Although the inquiry may return success, the following value
1072  * means no valid LUN connected.
1073  */
1074 #define MPTSAS_VALID_LUN(sd_inq) \
1075         (((sd_inq->inq_dtype & 0xe0) != 0x20) && \
1076         ((sd_inq->inq_dtype & 0x1f) != 0x1f))
1077 
1078 /*
1079  * Default is to have 10 retries on receiving QFULL status and
1080  * each retry to be after 100 ms.
1081  */
1082 #define QFULL_RETRIES           10
1083 #define QFULL_RETRY_INTERVAL    100
1084 
1085 /*
1086  * Handy macros
1087  */
1088 #define Tgt(sp) ((sp)->cmd_pkt->pkt_address.a_target)
1089 #define Lun(sp) ((sp)->cmd_pkt->pkt_address.a_lun)
1090 
1091 #define IS_HEX_DIGIT(n) (((n) >= '0' && (n) <= '9') || \
1092         ((n) >= 'a' && (n) <= 'f') || ((n) >= 'A' && (n) <= 'F'))
1093 
1094 /*
1095  * poll time for mptsas_pollret() and mptsas_wait_intr()
1096  */
1097 #define MPTSAS_POLL_TIME        30000   /* 30 seconds */
1098 
1099 /*
1100  * default time for mptsas_do_passthru
1101  */
1102 #define MPTSAS_PASS_THRU_TIME_DEFAULT   60      /* 60 seconds */
1103 
1104 /*
1105  * macro to return the effective address of a given per-target field
1106  */
1107 #define EFF_ADDR(start, offset)         ((start) + (offset))
1108 
1109 #define SDEV2ADDR(devp)         (&((devp)->sd_address))
1110 #define SDEV2TRAN(devp)         ((devp)->sd_address.a_hba_tran)
1111 #define PKT2TRAN(pkt)           ((pkt)->pkt_address.a_hba_tran)
1112 #define ADDR2TRAN(ap)           ((ap)->a_hba_tran)
1113 #define DIP2TRAN(dip)           (ddi_get_driver_private(dip))
1114 
1115 
1116 #define TRAN2MPT(hba)           ((mptsas_t *)(hba)->tran_hba_private)
1117 #define DIP2MPT(dip)            (TRAN2MPT((scsi_hba_tran_t *)DIP2TRAN(dip)))
1118 #define SDEV2MPT(sd)            (TRAN2MPT(SDEV2TRAN(sd)))
1119 #define PKT2MPT(pkt)            (TRAN2MPT(PKT2TRAN(pkt)))
1120 
1121 #define ADDR2MPT(ap)            (TRAN2MPT(ADDR2TRAN(ap)))
1122 
1123 #define POLL_TIMEOUT            (2 * SCSI_POLL_TIMEOUT * 1000000)
1124 #define SHORT_POLL_TIMEOUT      (1000000)       /* in usec, about 1 secs */
1125 #define MPTSAS_QUIESCE_TIMEOUT  1               /* 1 sec */
1126 #define MPTSAS_PM_IDLE_TIMEOUT  60              /* 60 seconds */
1127 
1128 #define MPTSAS_GET_ISTAT(mpt)  (ddi_get32((mpt)->m_datap, \
1129                         &(mpt)->m_reg->HostInterruptStatus))
1130 
1131 #define MPTSAS_SET_SIGP(P) \
1132                 ClrSetBits(mpt->m_devaddr + NREG_ISTAT, 0, NB_ISTAT_SIGP)
1133 
1134 #define MPTSAS_RESET_SIGP(P) (void) ddi_get8(mpt->m_datap, \
1135                         (uint8_t *)(mpt->m_devaddr + NREG_CTEST2))
1136 
1137 #define MPTSAS_GET_INTCODE(P) (ddi_get32(mpt->m_datap, \
1138                         (uint32_t *)(mpt->m_devaddr + NREG_DSPS)))
1139 
1140 
1141 #define MPTSAS_START_CMD(mpt, req_desc_lo, req_desc_hi) \
1142         ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostLow,\
1143             req_desc_lo);\
1144         ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostHigh,\
1145             req_desc_hi);
1146 
1147 #define INTPENDING(mpt) \
1148         (MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT)
1149 
1150 /*
1151  * Mask all interrupts to disable
1152  */
1153 #define MPTSAS_DISABLE_INTR(mpt)        \
1154         ddi_put32((mpt)->m_datap, &(mpt)->m_reg->HostInterruptMask, \
1155             (MPI2_HIM_RIM | MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK))
1156 
1157 /*
1158  * Mask Doorbell and Reset interrupts to enable reply desc int.
1159  */
1160 #define MPTSAS_ENABLE_INTR(mpt) \
1161         ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \
1162         (MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK))
1163 
1164 #define MPTSAS_GET_NEXT_REPLY(mpt, index)  \
1165         &((uint64_t *)(void *)mpt->m_post_queue)[index]
1166 
1167 #define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \
1168         (mpt->m_req_frame + (mpt->m_req_frame_size * SMID))
1169 
1170 #define ClrSetBits32(hdl, reg, clr, set) \
1171         ddi_put32(hdl, (reg), \
1172             ((ddi_get32(mpt->m_datap, (reg)) & ~(clr)) | (set)))
1173 
1174 #define ClrSetBits(reg, clr, set) \
1175         ddi_put8(mpt->m_datap, (uint8_t *)(reg), \
1176                 ((ddi_get8(mpt->m_datap, (uint8_t *)(reg)) & ~(clr)) | (set)))
1177 
1178 #define MPTSAS_WAITQ_RM(mpt, cmdp)      \
1179         if ((cmdp = mpt->m_waitq) != NULL) { \
1180                 /* If the queue is now empty fix the tail pointer */    \
1181                 if ((mpt->m_waitq = cmdp->cmd_linkp) == NULL) \
1182                         mpt->m_waitqtail = &mpt->m_waitq; \
1183                 cmdp->cmd_linkp = NULL; \
1184                 cmdp->cmd_queued = FALSE; \
1185         }
1186 
1187 #define MPTSAS_TX_WAITQ_RM(mpt, cmdp)   \
1188         if ((cmdp = mpt->m_tx_waitq) != NULL) { \
1189                 /* If the queue is now empty fix the tail pointer */    \
1190                 if ((mpt->m_tx_waitq = cmdp->cmd_linkp) == NULL) \
1191                         mpt->m_tx_waitqtail = &mpt->m_tx_waitq; \
1192                 cmdp->cmd_linkp = NULL; \
1193                 cmdp->cmd_queued = FALSE; \
1194         }
1195 
1196 /*
1197  * defaults for the global properties
1198  */
1199 #define DEFAULT_SCSI_OPTIONS    SCSI_OPTIONS_DR
1200 #define DEFAULT_TAG_AGE_LIMIT   2
1201 #define DEFAULT_WD_TICK         10
1202 
1203 /*
1204  * invalid hostid.
1205  */
1206 #define MPTSAS_INVALID_HOSTID  -1
1207 
1208 /*
1209  * Get/Set hostid from SCSI port configuration page
1210  */
1211 #define MPTSAS_GET_HOST_ID(configuration) (configuration & 0xFF)
1212 #define MPTSAS_SET_HOST_ID(hostid) (hostid | ((1 << hostid) << 16))
1213 
1214 /*
1215  * Config space.
1216  */
1217 #define MPTSAS_LATENCY_TIMER    0x40
1218 
1219 /*
1220  * Offset to firmware version
1221  */
1222 #define MPTSAS_FW_VERSION_OFFSET        9
1223 
1224 /*
1225  * Offset and masks to get at the ProductId field
1226  */
1227 #define MPTSAS_FW_PRODUCTID_OFFSET      8
1228 #define MPTSAS_FW_PRODUCTID_MASK        0xFFFF0000
1229 #define MPTSAS_FW_PRODUCTID_SHIFT       16
1230 
1231 /*
1232  * Subsystem ID for HBAs.
1233  */
1234 #define MPTSAS_HBA_SUBSYSTEM_ID    0x10C0
1235 #define MPTSAS_RHEA_SUBSYSTEM_ID        0x10B0
1236 
1237 /*
1238  * reset delay tick
1239  */
1240 #define MPTSAS_WATCH_RESET_DELAY_TICK 50        /* specified in milli seconds */
1241 
1242 /*
1243  * Ioc reset return values
1244  */
1245 #define MPTSAS_RESET_FAIL       -1
1246 #define MPTSAS_NO_RESET         0
1247 #define MPTSAS_SUCCESS_HARDRESET        1
1248 #define MPTSAS_SUCCESS_MUR      2
1249 
1250 /*
1251  * throttle support.
1252  */
1253 #define MAX_THROTTLE    32
1254 #define HOLD_THROTTLE   0
1255 #define DRAIN_THROTTLE  -1
1256 #define QFULL_THROTTLE  -2
1257 
1258 /*
1259  * Passthrough/config request flags
1260  */
1261 #define MPTSAS_DATA_ALLOCATED           0x0001
1262 #define MPTSAS_DATAOUT_ALLOCATED        0x0002
1263 #define MPTSAS_REQUEST_POOL_CMD         0x0004
1264 #define MPTSAS_ADDRESS_REPLY            0x0008
1265 #define MPTSAS_CMD_TIMEOUT              0x0010
1266 
1267 /*
1268  * response code tlr flag
1269  */
1270 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF       0x02
1271 
1272 /*
1273  * System Events
1274  */
1275 #ifndef DDI_VENDOR_LSI
1276 #define DDI_VENDOR_LSI  "LSI"
1277 #endif  /* DDI_VENDOR_LSI */
1278 
1279 /*
1280  * Shared functions
1281  */
1282 int mptsas_save_cmd(struct mptsas *mpt, struct mptsas_cmd *cmd);
1283 void mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
1284 void mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd);
1285 void mptsas_log(struct mptsas *mpt, int level, char *fmt, ...);
1286 int mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime);
1287 int mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)());
1288 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action,
1289         uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber,
1290         uint8_t pageversion, uint8_t pagelength, uint32_t
1291         SGEflagslength, uint32_t SGEaddress32);
1292 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action,
1293         uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber,
1294         uint8_t pageversion, uint16_t extpagelength,
1295         uint32_t SGEflagslength, uint32_t SGEaddress32);
1296 int mptsas_update_flash(mptsas_t *mpt, caddr_t ptrbuffer, uint32_t size,
1297         uint8_t type, int mode);
1298 int mptsas_check_flash(mptsas_t *mpt, caddr_t origfile, uint32_t size,
1299         uint8_t type, int mode);
1300 int mptsas_download_firmware();
1301 int mptsas_can_download_firmware();
1302 int mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep);
1303 void mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep);
1304 mptsas_phymask_t mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport);
1305 void mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd);
1306 int mptsas_check_acc_handle(ddi_acc_handle_t handle);
1307 int mptsas_check_dma_handle(ddi_dma_handle_t handle);
1308 void mptsas_fm_ereport(mptsas_t *mpt, char *detail);
1309 int mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr,
1310     ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp,
1311     uint32_t alloc_size, ddi_dma_cookie_t *cookiep);
1312 void mptsas_dma_addr_destroy(ddi_dma_handle_t *, ddi_acc_handle_t *);
1313 
1314 /*
1315  * impl functions
1316  */
1317 int mptsas_ioc_wait_for_response(mptsas_t *mpt);
1318 int mptsas_ioc_wait_for_doorbell(mptsas_t *mpt);
1319 int mptsas_ioc_reset(mptsas_t *mpt, int);
1320 int mptsas_send_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes,
1321     ddi_acc_handle_t accessp);
1322 int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes,
1323     ddi_acc_handle_t accessp);
1324 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action,
1325     uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber,
1326     uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength,
1327     uint32_t SGEaddress32);
1328 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action,
1329     uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber,
1330     uint8_t pageversion, uint16_t extpagelength,
1331     uint32_t SGEflagslength, uint32_t SGEaddress32);
1332 
1333 int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd,
1334     struct scsi_pkt **pkt);
1335 void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd);
1336 void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt);
1337 void mptsas_start_config_page_access(mptsas_t *mpt, mptsas_cmd_t *cmd);
1338 int mptsas_access_config_page(mptsas_t *mpt, uint8_t action, uint8_t page_type,
1339     uint8_t page_number, uint32_t page_address, int (*callback) (mptsas_t *,
1340     caddr_t, ddi_acc_handle_t, uint16_t, uint32_t, va_list), ...);
1341 
1342 int mptsas_ioc_task_management(mptsas_t *mpt, int task_type,
1343     uint16_t dev_handle, int lun, uint8_t *reply, uint32_t reply_size,
1344     int mode);
1345 int mptsas_send_event_ack(mptsas_t *mpt, uint32_t event, uint32_t eventcntx);
1346 void mptsas_send_pending_event_ack(mptsas_t *mpt);
1347 void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt, int what);
1348 int mptsas_restart_ioc(mptsas_t *mpt);
1349 void mptsas_update_driver_data(struct mptsas *mpt);
1350 uint64_t mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun);
1351 
1352 /*
1353  * init functions
1354  */
1355 int mptsas_ioc_get_facts(mptsas_t *mpt);
1356 int mptsas_ioc_get_port_facts(mptsas_t *mpt, int port);
1357 int mptsas_ioc_enable_port(mptsas_t *mpt);
1358 int mptsas_ioc_enable_event_notification(mptsas_t *mpt);
1359 int mptsas_ioc_init(mptsas_t *mpt);
1360 
1361 /*
1362  * configuration pages operation
1363  */
1364 int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address,
1365     uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info,
1366     uint8_t *physport, uint8_t *phynum, uint16_t *pdevhandle,
1367     uint16_t *slot_num, uint16_t *enclosure);
1368 int mptsas_get_sas_io_unit_page(mptsas_t *mpt);
1369 int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt);
1370 int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address,
1371     mptsas_smp_t *info);
1372 int mptsas_set_ioc_params(mptsas_t *mpt);
1373 int mptsas_get_manufacture_page5(mptsas_t *mpt);
1374 int mptsas_get_sas_port_page0(mptsas_t *mpt, uint32_t page_address,
1375     uint64_t *sas_wwn, uint8_t *portwidth);
1376 int mptsas_get_bios_page3(mptsas_t *mpt,  uint32_t *bios_version);
1377 int
1378 mptsas_get_sas_phy_page0(mptsas_t *mpt, uint32_t page_address,
1379     smhba_info_t *info);
1380 int
1381 mptsas_get_sas_phy_page1(mptsas_t *mpt, uint32_t page_address,
1382     smhba_info_t *info);
1383 int
1384 mptsas_get_manufacture_page0(mptsas_t *mpt);
1385 void
1386 mptsas_create_phy_stats(mptsas_t *mpt, char *iport, dev_info_t *dip);
1387 void mptsas_destroy_phy_stats(mptsas_t *mpt);
1388 int mptsas_smhba_phy_init(mptsas_t *mpt);
1389 /*
1390  * RAID functions
1391  */
1392 int mptsas_get_raid_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol);
1393 int mptsas_get_raid_info(mptsas_t *mpt);
1394 int mptsas_get_physdisk_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol,
1395     uint8_t physdisknum);
1396 int mptsas_delete_volume(mptsas_t *mpt, uint16_t volid);
1397 void mptsas_raid_action_system_shutdown(mptsas_t *mpt);
1398 
1399 #define MPTSAS_IOCSTATUS(status) (status & MPI2_IOCSTATUS_MASK)
1400 /*
1401  * debugging.
1402  */
1403 #if defined(MPTSAS_DEBUG)
1404 
1405 void mptsas_printf(char *fmt, ...);
1406 
1407 #define MPTSAS_DBGPR(m, args)   \
1408         if (mptsas_debug_flags & (m)) \
1409                 mptsas_printf args
1410 #else   /* ! defined(MPTSAS_DEBUG) */
1411 #define MPTSAS_DBGPR(m, args)
1412 #endif  /* defined(MPTSAS_DEBUG) */
1413 
1414 #define NDBG0(args)     MPTSAS_DBGPR(0x01, args)        /* init */
1415 #define NDBG1(args)     MPTSAS_DBGPR(0x02, args)        /* normal running */
1416 #define NDBG2(args)     MPTSAS_DBGPR(0x04, args)        /* property handling */
1417 #define NDBG3(args)     MPTSAS_DBGPR(0x08, args)        /* pkt handling */
1418 
1419 #define NDBG4(args)     MPTSAS_DBGPR(0x10, args)        /* kmem alloc/free */
1420 #define NDBG5(args)     MPTSAS_DBGPR(0x20, args)        /* polled cmds */
1421 #define NDBG6(args)     MPTSAS_DBGPR(0x40, args)        /* interrupts */
1422 #define NDBG7(args)     MPTSAS_DBGPR(0x80, args)        /* queue handling */
1423 
1424 #define NDBG8(args)     MPTSAS_DBGPR(0x0100, args)      /* arq */
1425 #define NDBG9(args)     MPTSAS_DBGPR(0x0200, args)      /* Tagged Q'ing */
1426 #define NDBG10(args)    MPTSAS_DBGPR(0x0400, args)      /* halting chip */
1427 #define NDBG11(args)    MPTSAS_DBGPR(0x0800, args)      /* power management */
1428 
1429 #define NDBG12(args)    MPTSAS_DBGPR(0x1000, args)      /* enumeration */
1430 #define NDBG13(args)    MPTSAS_DBGPR(0x2000, args)      /* configuration page */
1431 #define NDBG14(args)    MPTSAS_DBGPR(0x4000, args)      /* LED control */
1432 #define NDBG15(args)    MPTSAS_DBGPR(0x8000, args)
1433 
1434 #define NDBG16(args)    MPTSAS_DBGPR(0x010000, args)
1435 #define NDBG17(args)    MPTSAS_DBGPR(0x020000, args)    /* scatter/gather */
1436 #define NDBG18(args)    MPTSAS_DBGPR(0x040000, args)
1437 #define NDBG19(args)    MPTSAS_DBGPR(0x080000, args)    /* handshaking */
1438 
1439 #define NDBG20(args)    MPTSAS_DBGPR(0x100000, args)    /* events */
1440 #define NDBG21(args)    MPTSAS_DBGPR(0x200000, args)    /* dma */
1441 #define NDBG22(args)    MPTSAS_DBGPR(0x400000, args)    /* reset */
1442 #define NDBG23(args)    MPTSAS_DBGPR(0x800000, args)    /* abort */
1443 
1444 #define NDBG24(args)    MPTSAS_DBGPR(0x1000000, args)   /* capabilities */
1445 #define NDBG25(args)    MPTSAS_DBGPR(0x2000000, args)   /* flushing */
1446 #define NDBG26(args)    MPTSAS_DBGPR(0x4000000, args)
1447 #define NDBG27(args)    MPTSAS_DBGPR(0x8000000, args)
1448 
1449 #define NDBG28(args)    MPTSAS_DBGPR(0x10000000, args)  /* hotplug */
1450 #define NDBG29(args)    MPTSAS_DBGPR(0x20000000, args)  /* timeouts */
1451 #define NDBG30(args)    MPTSAS_DBGPR(0x40000000, args)  /* mptsas_watch */
1452 #define NDBG31(args)    MPTSAS_DBGPR(0x80000000, args)  /* negotations */
1453 
1454 /*
1455  * auto request sense
1456  */
1457 #define RQ_MAKECOM_COMMON(pkt, flag, cmd) \
1458         (pkt)->pkt_flags = (flag), \
1459         ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_cmd = (cmd), \
1460         ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_lun = \
1461             (pkt)->pkt_address.a_lun
1462 
1463 #define RQ_MAKECOM_G0(pkt, flag, cmd, addr, cnt) \
1464         RQ_MAKECOM_COMMON((pkt), (flag), (cmd)), \
1465         FORMG0ADDR(((union scsi_cdb *)(pkt)->pkt_cdbp), (addr)), \
1466         FORMG0COUNT(((union scsi_cdb *)(pkt)->pkt_cdbp), (cnt))
1467 
1468 
1469 #ifdef  __cplusplus
1470 }
1471 #endif
1472 
1473 #endif  /* _SYS_SCSI_ADAPTERS_MPTVAR_H */