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OS-1996 mpt_sas: allow physical topology enumeration in libtopo
Reviewed by: Keith Wesolowski <keith.wesolowski@joyent.com>
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--- old/usr/src/uts/common/io/scsi/adapters/mpt_sas/mptsas.c
+++ new/usr/src/uts/common/io/scsi/adapters/mpt_sas/mptsas.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
25 + * Copyright (c) 2013, Joyent, Inc. All rights reserved.
25 26 */
26 27
27 28 /*
28 29 * Copyright (c) 2000 to 2010, LSI Corporation.
29 30 * All rights reserved.
30 31 *
31 32 * Redistribution and use in source and binary forms of all code within
32 33 * this file that is exclusively owned by LSI, with or without
33 34 * modification, is permitted provided that, in addition to the CDDL 1.0
34 35 * License requirements, the following conditions are met:
35 36 *
36 37 * Neither the name of the author nor the names of its contributors may be
37 38 * used to endorse or promote products derived from this software without
38 39 * specific prior written permission.
39 40 *
40 41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
41 42 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
42 43 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
43 44 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
44 45 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
45 46 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
46 47 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
47 48 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
48 49 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
49 50 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
50 51 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
51 52 * DAMAGE.
52 53 */
53 54
54 55 /*
55 56 * mptsas - This is a driver based on LSI Logic's MPT2.0 interface.
56 57 *
57 58 */
58 59
59 60 #if defined(lint) || defined(DEBUG)
60 61 #define MPTSAS_DEBUG
61 62 #endif
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62 63
63 64 /*
64 65 * standard header files.
65 66 */
66 67 #include <sys/note.h>
67 68 #include <sys/scsi/scsi.h>
68 69 #include <sys/pci.h>
69 70 #include <sys/file.h>
70 71 #include <sys/cpuvar.h>
71 72 #include <sys/policy.h>
73 +#include <sys/model.h>
72 74 #include <sys/sysevent.h>
73 75 #include <sys/sysevent/eventdefs.h>
74 76 #include <sys/sysevent/dr.h>
75 77 #include <sys/sata/sata_defs.h>
76 78 #include <sys/scsi/generic/sas.h>
77 79 #include <sys/scsi/impl/scsi_sas.h>
78 80
79 81 #pragma pack(1)
80 82 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h>
81 83 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2.h>
82 84 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h>
83 85 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h>
84 86 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h>
85 87 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h>
86 88 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h>
87 89 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h>
88 90 #pragma pack()
89 91
90 92 /*
91 93 * private header files.
92 94 *
93 95 */
94 96 #include <sys/scsi/impl/scsi_reset_notify.h>
95 97 #include <sys/scsi/adapters/mpt_sas/mptsas_var.h>
96 98 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h>
97 99 #include <sys/scsi/adapters/mpt_sas/mptsas_smhba.h>
98 100
99 101 #include <sys/raidioctl.h>
100 102
101 103 #include <sys/fs/dv_node.h> /* devfs_clean */
102 104
103 105 /*
104 106 * FMA header files
105 107 */
106 108 #include <sys/ddifm.h>
107 109 #include <sys/fm/protocol.h>
108 110 #include <sys/fm/util.h>
109 111 #include <sys/fm/io/ddi.h>
110 112
111 113 /*
112 114 * For anyone who would modify the code in mptsas_driver, it must be awared
113 115 * that from snv_145 where CR6910752(mpt_sas driver performance can be
114 116 * improved) is integrated, the per_instance mutex m_mutex is not hold
115 117 * in the key IO code path, including mptsas_scsi_start(), mptsas_intr()
116 118 * and all of the recursive functions called in them, so don't
117 119 * make it for granted that all operations are sync/exclude correctly. Before
118 120 * doing any modification in key code path, and even other code path such as
119 121 * DR, watchsubr, ioctl, passthrough etc, make sure the elements modified have
120 122 * no releationship to elements shown in the fastpath
121 123 * (function mptsas_handle_io_fastpath()) in ISR and its recursive functions.
122 124 * otherwise, you have to use the new introduced mutex to protect them.
123 125 * As to how to do correctly, refer to the comments in mptsas_intr().
124 126 */
125 127
126 128 /*
127 129 * autoconfiguration data and routines.
128 130 */
129 131 static int mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
130 132 static int mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd);
131 133 static int mptsas_power(dev_info_t *dip, int component, int level);
132 134
133 135 /*
134 136 * cb_ops function
135 137 */
136 138 static int mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode,
137 139 cred_t *credp, int *rval);
138 140 #ifdef __sparc
139 141 static int mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd);
140 142 #else /* __sparc */
141 143 static int mptsas_quiesce(dev_info_t *devi);
142 144 #endif /* __sparc */
143 145
144 146 /*
145 147 * Resource initilaization for hardware
146 148 */
147 149 static void mptsas_setup_cmd_reg(mptsas_t *mpt);
148 150 static void mptsas_disable_bus_master(mptsas_t *mpt);
149 151 static void mptsas_hba_fini(mptsas_t *mpt);
150 152 static void mptsas_cfg_fini(mptsas_t *mptsas_blkp);
151 153 static int mptsas_hba_setup(mptsas_t *mpt);
152 154 static void mptsas_hba_teardown(mptsas_t *mpt);
153 155 static int mptsas_config_space_init(mptsas_t *mpt);
154 156 static void mptsas_config_space_fini(mptsas_t *mpt);
155 157 static void mptsas_iport_register(mptsas_t *mpt);
156 158 static int mptsas_smp_setup(mptsas_t *mpt);
157 159 static void mptsas_smp_teardown(mptsas_t *mpt);
158 160 static int mptsas_cache_create(mptsas_t *mpt);
159 161 static void mptsas_cache_destroy(mptsas_t *mpt);
160 162 static int mptsas_alloc_request_frames(mptsas_t *mpt);
161 163 static int mptsas_alloc_reply_frames(mptsas_t *mpt);
162 164 static int mptsas_alloc_free_queue(mptsas_t *mpt);
163 165 static int mptsas_alloc_post_queue(mptsas_t *mpt);
164 166 static void mptsas_alloc_reply_args(mptsas_t *mpt);
165 167 static int mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd);
166 168 static void mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd);
167 169 static int mptsas_init_chip(mptsas_t *mpt, int first_time);
168 170
169 171 /*
170 172 * SCSA function prototypes
171 173 */
172 174 static int mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt);
173 175 static int mptsas_scsi_reset(struct scsi_address *ap, int level);
174 176 static int mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt);
175 177 static int mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly);
176 178 static int mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value,
177 179 int tgtonly);
178 180 static void mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt);
179 181 static struct scsi_pkt *mptsas_scsi_init_pkt(struct scsi_address *ap,
180 182 struct scsi_pkt *pkt, struct buf *bp, int cmdlen, int statuslen,
181 183 int tgtlen, int flags, int (*callback)(), caddr_t arg);
182 184 static void mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt);
183 185 static void mptsas_scsi_destroy_pkt(struct scsi_address *ap,
184 186 struct scsi_pkt *pkt);
185 187 static int mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
186 188 scsi_hba_tran_t *hba_tran, struct scsi_device *sd);
187 189 static void mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
188 190 scsi_hba_tran_t *hba_tran, struct scsi_device *sd);
189 191 static int mptsas_scsi_reset_notify(struct scsi_address *ap, int flag,
190 192 void (*callback)(caddr_t), caddr_t arg);
191 193 static int mptsas_get_name(struct scsi_device *sd, char *name, int len);
192 194 static int mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len);
193 195 static int mptsas_scsi_quiesce(dev_info_t *dip);
194 196 static int mptsas_scsi_unquiesce(dev_info_t *dip);
195 197 static int mptsas_bus_config(dev_info_t *pdip, uint_t flags,
196 198 ddi_bus_config_op_t op, void *arg, dev_info_t **childp);
197 199
198 200 /*
199 201 * SMP functions
200 202 */
201 203 static int mptsas_smp_start(struct smp_pkt *smp_pkt);
202 204
203 205 /*
204 206 * internal function prototypes.
205 207 */
206 208 static void mptsas_list_add(mptsas_t *mpt);
207 209 static void mptsas_list_del(mptsas_t *mpt);
208 210
209 211 static int mptsas_quiesce_bus(mptsas_t *mpt);
210 212 static int mptsas_unquiesce_bus(mptsas_t *mpt);
211 213
212 214 static int mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size);
213 215 static void mptsas_free_handshake_msg(mptsas_t *mpt);
214 216
215 217 static void mptsas_ncmds_checkdrain(void *arg);
216 218
217 219 static int mptsas_prepare_pkt(mptsas_cmd_t *cmd);
218 220 static int mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *sp);
219 221
220 222 static int mptsas_do_detach(dev_info_t *dev);
221 223 static int mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl);
222 224 static int mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun,
223 225 struct scsi_pkt *pkt);
224 226 static int mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp);
225 227
226 228 static void mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd);
227 229 static void mptsas_handle_event(void *args);
228 230 static int mptsas_handle_event_sync(void *args);
229 231 static void mptsas_handle_dr(void *args);
230 232 static void mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node,
231 233 dev_info_t *pdip);
232 234
233 235 static void mptsas_restart_cmd(void *);
234 236
235 237 static void mptsas_flush_hba(mptsas_t *mpt);
236 238 static void mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun,
237 239 uint8_t tasktype);
238 240 static void mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd,
239 241 uchar_t reason, uint_t stat);
240 242
241 243 static uint_t mptsas_intr(caddr_t arg1, caddr_t arg2);
242 244 static void mptsas_process_intr(mptsas_t *mpt,
243 245 pMpi2ReplyDescriptorsUnion_t reply_desc_union);
244 246 static int mptsas_handle_io_fastpath(mptsas_t *mpt, uint16_t SMID);
245 247 static void mptsas_handle_scsi_io_success(mptsas_t *mpt,
246 248 pMpi2ReplyDescriptorsUnion_t reply_desc);
247 249 static void mptsas_handle_address_reply(mptsas_t *mpt,
248 250 pMpi2ReplyDescriptorsUnion_t reply_desc);
249 251 static int mptsas_wait_intr(mptsas_t *mpt, int polltime);
250 252 static void mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd,
251 253 uint32_t *control, pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl);
252 254
253 255 static void mptsas_watch(void *arg);
254 256 static void mptsas_watchsubr(mptsas_t *mpt);
255 257 static void mptsas_cmd_timeout(mptsas_t *mpt, uint16_t devhdl);
256 258
257 259 static void mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd);
258 260 static int mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply,
259 261 uint8_t *data, uint32_t request_size, uint32_t reply_size,
260 262 uint32_t data_size, uint32_t direction, uint8_t *dataout,
261 263 uint32_t dataout_size, short timeout, int mode);
262 264 static int mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl);
263 265
264 266 static uint8_t mptsas_get_fw_diag_buffer_number(mptsas_t *mpt,
265 267 uint32_t unique_id);
266 268 static void mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd);
267 269 static int mptsas_post_fw_diag_buffer(mptsas_t *mpt,
268 270 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code);
269 271 static int mptsas_release_fw_diag_buffer(mptsas_t *mpt,
270 272 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code,
271 273 uint32_t diag_type);
272 274 static int mptsas_diag_register(mptsas_t *mpt,
273 275 mptsas_fw_diag_register_t *diag_register, uint32_t *return_code);
274 276 static int mptsas_diag_unregister(mptsas_t *mpt,
275 277 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code);
276 278 static int mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query,
277 279 uint32_t *return_code);
278 280 static int mptsas_diag_read_buffer(mptsas_t *mpt,
279 281 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf,
280 282 uint32_t *return_code, int ioctl_mode);
281 283 static int mptsas_diag_release(mptsas_t *mpt,
282 284 mptsas_fw_diag_release_t *diag_release, uint32_t *return_code);
283 285 static int mptsas_do_diag_action(mptsas_t *mpt, uint32_t action,
284 286 uint8_t *diag_action, uint32_t length, uint32_t *return_code,
285 287 int ioctl_mode);
286 288 static int mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *data,
287 289 int mode);
288 290
289 291 static int mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd,
290 292 int cmdlen, int tgtlen, int statuslen, int kf);
291 293 static void mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd);
292 294
293 295 static int mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags);
294 296 static void mptsas_kmem_cache_destructor(void *buf, void *cdrarg);
295 297
296 298 static int mptsas_cache_frames_constructor(void *buf, void *cdrarg,
297 299 int kmflags);
298 300 static void mptsas_cache_frames_destructor(void *buf, void *cdrarg);
299 301
300 302 static void mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply,
301 303 mptsas_cmd_t *cmd);
302 304 static void mptsas_check_task_mgt(mptsas_t *mpt,
303 305 pMpi2SCSIManagementReply_t reply, mptsas_cmd_t *cmd);
304 306 static int mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap,
305 307 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp,
306 308 int *resid);
307 309
308 310 static int mptsas_alloc_active_slots(mptsas_t *mpt, int flag);
309 311 static void mptsas_free_active_slots(mptsas_t *mpt);
310 312 static int mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
311 313 static int mptsas_start_cmd0(mptsas_t *mpt, mptsas_cmd_t *cmd);
312 314
313 315 static void mptsas_restart_hba(mptsas_t *mpt);
314 316
315 317 static void mptsas_deliver_doneq_thread(mptsas_t *mpt);
316 318 static void mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd);
317 319 static inline void mptsas_doneq_add0(mptsas_t *mpt, mptsas_cmd_t *cmd);
318 320 static void mptsas_doneq_mv(mptsas_t *mpt, uint64_t t);
319 321
320 322 static mptsas_cmd_t *mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t);
321 323 static void mptsas_doneq_empty(mptsas_t *mpt);
322 324 static void mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg);
323 325
324 326 static mptsas_cmd_t *mptsas_waitq_rm(mptsas_t *mpt);
325 327 static void mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd);
326 328
327 329 static void mptsas_start_watch_reset_delay();
328 330 static void mptsas_setup_bus_reset_delay(mptsas_t *mpt);
329 331 static void mptsas_watch_reset_delay(void *arg);
330 332 static int mptsas_watch_reset_delay_subr(mptsas_t *mpt);
331 333
332 334 static int mptsas_outstanding_cmds_n(mptsas_t *mpt);
333 335 /*
334 336 * helper functions
335 337 */
336 338 static void mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
337 339
338 340 static dev_info_t *mptsas_find_child(dev_info_t *pdip, char *name);
339 341 static dev_info_t *mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy);
340 342 static dev_info_t *mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr,
341 343 int lun);
342 344 static mdi_pathinfo_t *mptsas_find_path_addr(dev_info_t *pdip, uint64_t sasaddr,
343 345 int lun);
344 346 static mdi_pathinfo_t *mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy);
345 347 static dev_info_t *mptsas_find_smp_child(dev_info_t *pdip, char *str_wwn);
346 348
347 349 static int mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy,
348 350 int *lun);
349 351 static int mptsas_parse_smp_name(char *name, uint64_t *wwn);
350 352
351 353 static mptsas_target_t *mptsas_phy_to_tgt(mptsas_t *mpt, int phymask,
352 354 uint8_t phy);
353 355 static mptsas_target_t *mptsas_wwid_to_ptgt(mptsas_t *mpt, int phymask,
354 356 uint64_t wwid);
355 357 static mptsas_smp_t *mptsas_wwid_to_psmp(mptsas_t *mpt, int phymask,
356 358 uint64_t wwid);
357 359
358 360 static int mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun,
359 361 uchar_t page, unsigned char *buf, int len, int *rlen, uchar_t evpd);
360 362
361 363 static int mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address,
362 364 uint16_t *handle, mptsas_target_t **pptgt);
363 365 static void mptsas_update_phymask(mptsas_t *mpt);
364 366 static inline void mptsas_remove_cmd0(mptsas_t *mpt, mptsas_cmd_t *cmd);
365 367
366 368 static int mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt,
367 369 uint32_t *status, uint8_t cmd);
368 370 static dev_info_t *mptsas_get_dip_from_dev(dev_t dev,
369 371 mptsas_phymask_t *phymask);
370 372 static mptsas_target_t *mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr,
371 373 mptsas_phymask_t phymask);
372 374 static int mptsas_set_led_status(mptsas_t *mpt, mptsas_target_t *ptgt,
373 375 uint32_t slotstatus);
374 376
375 377
376 378 /*
377 379 * Enumeration / DR functions
378 380 */
379 381 static void mptsas_config_all(dev_info_t *pdip);
380 382 static int mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun,
381 383 dev_info_t **lundip);
382 384 static int mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun,
383 385 dev_info_t **lundip);
384 386
385 387 static int mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt);
386 388 static int mptsas_offline_target(dev_info_t *pdip, char *name);
387 389
388 390 static int mptsas_config_raid(dev_info_t *pdip, uint16_t target,
389 391 dev_info_t **dip);
390 392
391 393 static int mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt);
392 394 static int mptsas_probe_lun(dev_info_t *pdip, int lun,
393 395 dev_info_t **dip, mptsas_target_t *ptgt);
394 396
395 397 static int mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq,
396 398 dev_info_t **dip, mptsas_target_t *ptgt, int lun);
397 399
398 400 static int mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *sd,
399 401 char *guid, dev_info_t **dip, mptsas_target_t *ptgt, int lun);
400 402 static int mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *sd,
401 403 char *guid, dev_info_t **dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt,
402 404 int lun);
403 405
404 406 static void mptsas_offline_missed_luns(dev_info_t *pdip,
405 407 uint16_t *repluns, int lun_cnt, mptsas_target_t *ptgt);
406 408 static int mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip,
407 409 mdi_pathinfo_t *rpip, uint_t flags);
408 410
409 411 static int mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn,
410 412 dev_info_t **smp_dip);
411 413 static int mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
412 414 uint_t flags);
413 415
414 416 static int mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data,
415 417 int mode, int *rval);
416 418 static int mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data,
417 419 int mode, int *rval);
418 420 static int mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data,
419 421 int mode, int *rval);
420 422 static void mptsas_record_event(void *args);
421 423 static int mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data,
422 424 int mode);
423 425
424 426 static void mptsas_hash_init(mptsas_hash_table_t *hashtab);
425 427 static void mptsas_hash_uninit(mptsas_hash_table_t *hashtab, size_t datalen);
426 428 static void mptsas_hash_add(mptsas_hash_table_t *hashtab, void *data);
427 429 static void * mptsas_hash_rem(mptsas_hash_table_t *hashtab, uint64_t key1,
428 430 mptsas_phymask_t key2);
429 431 static void * mptsas_hash_search(mptsas_hash_table_t *hashtab, uint64_t key1,
430 432 mptsas_phymask_t key2);
431 433 static void * mptsas_hash_traverse(mptsas_hash_table_t *hashtab, int pos);
432 434
433 435 mptsas_target_t *mptsas_tgt_alloc(mptsas_hash_table_t *, uint16_t, uint64_t,
434 436 uint32_t, mptsas_phymask_t, uint8_t, mptsas_t *);
435 437 static mptsas_smp_t *mptsas_smp_alloc(mptsas_hash_table_t *hashtab,
436 438 mptsas_smp_t *data);
437 439 static void mptsas_smp_free(mptsas_hash_table_t *hashtab, uint64_t wwid,
438 440 mptsas_phymask_t phymask);
439 441 static void mptsas_tgt_free(mptsas_hash_table_t *, uint64_t, mptsas_phymask_t);
440 442 static void * mptsas_search_by_devhdl(mptsas_hash_table_t *, uint16_t);
441 443 static int mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
442 444 dev_info_t **smp_dip);
443 445
444 446 /*
445 447 * Power management functions
446 448 */
447 449 static int mptsas_get_pci_cap(mptsas_t *mpt);
448 450 static int mptsas_init_pm(mptsas_t *mpt);
449 451
450 452 /*
451 453 * MPT MSI tunable:
452 454 *
453 455 * By default MSI is enabled on all supported platforms.
454 456 */
455 457 boolean_t mptsas_enable_msi = B_TRUE;
456 458 boolean_t mptsas_physical_bind_failed_page_83 = B_FALSE;
457 459
458 460 static int mptsas_register_intrs(mptsas_t *);
459 461 static void mptsas_unregister_intrs(mptsas_t *);
460 462 static int mptsas_add_intrs(mptsas_t *, int);
461 463 static void mptsas_rem_intrs(mptsas_t *);
462 464
463 465 /*
464 466 * FMA Prototypes
465 467 */
466 468 static void mptsas_fm_init(mptsas_t *mpt);
467 469 static void mptsas_fm_fini(mptsas_t *mpt);
468 470 static int mptsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *, const void *);
469 471
470 472 extern pri_t minclsyspri, maxclsyspri;
471 473
472 474 /*
473 475 * This device is created by the SCSI pseudo nexus driver (SCSI vHCI). It is
474 476 * under this device that the paths to a physical device are created when
475 477 * MPxIO is used.
476 478 */
477 479 extern dev_info_t *scsi_vhci_dip;
478 480
479 481 /*
480 482 * Tunable timeout value for Inquiry VPD page 0x83
481 483 * By default the value is 30 seconds.
482 484 */
483 485 int mptsas_inq83_retry_timeout = 30;
484 486
485 487 /*
486 488 * This is used to allocate memory for message frame storage, not for
487 489 * data I/O DMA. All message frames must be stored in the first 4G of
488 490 * physical memory.
489 491 */
490 492 ddi_dma_attr_t mptsas_dma_attrs = {
491 493 DMA_ATTR_V0, /* attribute layout version */
492 494 0x0ull, /* address low - should be 0 (longlong) */
493 495 0xffffffffull, /* address high - 32-bit max range */
494 496 0x00ffffffull, /* count max - max DMA object size */
495 497 4, /* allocation alignment requirements */
496 498 0x78, /* burstsizes - binary encoded values */
497 499 1, /* minxfer - gran. of DMA engine */
498 500 0x00ffffffull, /* maxxfer - gran. of DMA engine */
499 501 0xffffffffull, /* max segment size (DMA boundary) */
500 502 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */
501 503 512, /* granularity - device transfer size */
502 504 0 /* flags, set to 0 */
503 505 };
504 506
505 507 /*
506 508 * This is used for data I/O DMA memory allocation. (full 64-bit DMA
507 509 * physical addresses are supported.)
508 510 */
509 511 ddi_dma_attr_t mptsas_dma_attrs64 = {
510 512 DMA_ATTR_V0, /* attribute layout version */
511 513 0x0ull, /* address low - should be 0 (longlong) */
512 514 0xffffffffffffffffull, /* address high - 64-bit max */
513 515 0x00ffffffull, /* count max - max DMA object size */
514 516 4, /* allocation alignment requirements */
515 517 0x78, /* burstsizes - binary encoded values */
516 518 1, /* minxfer - gran. of DMA engine */
517 519 0x00ffffffull, /* maxxfer - gran. of DMA engine */
518 520 0xffffffffull, /* max segment size (DMA boundary) */
519 521 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */
520 522 512, /* granularity - device transfer size */
521 523 DDI_DMA_RELAXED_ORDERING /* flags, enable relaxed ordering */
522 524 };
523 525
524 526 ddi_device_acc_attr_t mptsas_dev_attr = {
525 527 DDI_DEVICE_ATTR_V1,
526 528 DDI_STRUCTURE_LE_ACC,
527 529 DDI_STRICTORDER_ACC,
528 530 DDI_DEFAULT_ACC
529 531 };
530 532
531 533 static struct cb_ops mptsas_cb_ops = {
532 534 scsi_hba_open, /* open */
533 535 scsi_hba_close, /* close */
534 536 nodev, /* strategy */
535 537 nodev, /* print */
536 538 nodev, /* dump */
537 539 nodev, /* read */
538 540 nodev, /* write */
539 541 mptsas_ioctl, /* ioctl */
540 542 nodev, /* devmap */
541 543 nodev, /* mmap */
542 544 nodev, /* segmap */
543 545 nochpoll, /* chpoll */
544 546 ddi_prop_op, /* cb_prop_op */
545 547 NULL, /* streamtab */
546 548 D_MP, /* cb_flag */
547 549 CB_REV, /* rev */
548 550 nodev, /* aread */
549 551 nodev /* awrite */
550 552 };
551 553
552 554 static struct dev_ops mptsas_ops = {
553 555 DEVO_REV, /* devo_rev, */
554 556 0, /* refcnt */
555 557 ddi_no_info, /* info */
556 558 nulldev, /* identify */
557 559 nulldev, /* probe */
558 560 mptsas_attach, /* attach */
559 561 mptsas_detach, /* detach */
560 562 #ifdef __sparc
561 563 mptsas_reset,
562 564 #else
563 565 nodev, /* reset */
564 566 #endif /* __sparc */
565 567 &mptsas_cb_ops, /* driver operations */
566 568 NULL, /* bus operations */
567 569 mptsas_power, /* power management */
568 570 #ifdef __sparc
569 571 ddi_quiesce_not_needed
570 572 #else
571 573 mptsas_quiesce /* quiesce */
572 574 #endif /* __sparc */
573 575 };
574 576
575 577
576 578 #define MPTSAS_MOD_STRING "MPTSAS HBA Driver 00.00.00.24"
577 579
578 580 static struct modldrv modldrv = {
579 581 &mod_driverops, /* Type of module. This one is a driver */
580 582 MPTSAS_MOD_STRING, /* Name of the module. */
581 583 &mptsas_ops, /* driver ops */
582 584 };
583 585
584 586 static struct modlinkage modlinkage = {
585 587 MODREV_1, &modldrv, NULL
586 588 };
587 589 #define TARGET_PROP "target"
588 590 #define LUN_PROP "lun"
589 591 #define LUN64_PROP "lun64"
590 592 #define SAS_PROP "sas-mpt"
591 593 #define MDI_GUID "wwn"
592 594 #define NDI_GUID "guid"
593 595 #define MPTSAS_DEV_GONE "mptsas_dev_gone"
594 596
595 597 /*
596 598 * Local static data
597 599 */
598 600 #if defined(MPTSAS_DEBUG)
599 601 uint32_t mptsas_debug_flags = 0;
600 602 #endif /* defined(MPTSAS_DEBUG) */
601 603 uint32_t mptsas_debug_resets = 0;
602 604
603 605 static kmutex_t mptsas_global_mutex;
604 606 static void *mptsas_state; /* soft state ptr */
605 607 static krwlock_t mptsas_global_rwlock;
606 608
607 609 static kmutex_t mptsas_log_mutex;
608 610 static char mptsas_log_buf[256];
609 611 _NOTE(MUTEX_PROTECTS_DATA(mptsas_log_mutex, mptsas_log_buf))
610 612
611 613 static mptsas_t *mptsas_head, *mptsas_tail;
612 614 static clock_t mptsas_scsi_watchdog_tick;
613 615 static clock_t mptsas_tick;
614 616 static timeout_id_t mptsas_reset_watch;
615 617 static timeout_id_t mptsas_timeout_id;
616 618 static int mptsas_timeouts_enabled = 0;
617 619 /*
618 620 * warlock directives
619 621 */
620 622 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", scsi_pkt \
621 623 mptsas_cmd NcrTableIndirect buf scsi_cdb scsi_status))
622 624 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", smp_pkt))
623 625 _NOTE(SCHEME_PROTECTS_DATA("stable data", scsi_device scsi_address))
624 626 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", mptsas_tgt_private))
625 627 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", scsi_hba_tran::tran_tgt_private))
626 628
627 629 /*
628 630 * SM - HBA statics
629 631 */
630 632 char *mptsas_driver_rev = MPTSAS_MOD_STRING;
631 633
632 634 #ifdef MPTSAS_DEBUG
633 635 void debug_enter(char *);
634 636 #endif
635 637
636 638 /*
637 639 * Notes:
638 640 * - scsi_hba_init(9F) initializes SCSI HBA modules
639 641 * - must call scsi_hba_fini(9F) if modload() fails
640 642 */
641 643 int
642 644 _init(void)
643 645 {
644 646 int status;
645 647 /* CONSTCOND */
646 648 ASSERT(NO_COMPETING_THREADS);
647 649
648 650 NDBG0(("_init"));
649 651
650 652 status = ddi_soft_state_init(&mptsas_state, MPTSAS_SIZE,
651 653 MPTSAS_INITIAL_SOFT_SPACE);
652 654 if (status != 0) {
653 655 return (status);
654 656 }
655 657
656 658 if ((status = scsi_hba_init(&modlinkage)) != 0) {
657 659 ddi_soft_state_fini(&mptsas_state);
658 660 return (status);
659 661 }
660 662
661 663 mutex_init(&mptsas_global_mutex, NULL, MUTEX_DRIVER, NULL);
662 664 rw_init(&mptsas_global_rwlock, NULL, RW_DRIVER, NULL);
663 665 mutex_init(&mptsas_log_mutex, NULL, MUTEX_DRIVER, NULL);
664 666
665 667 if ((status = mod_install(&modlinkage)) != 0) {
666 668 mutex_destroy(&mptsas_log_mutex);
667 669 rw_destroy(&mptsas_global_rwlock);
668 670 mutex_destroy(&mptsas_global_mutex);
669 671 ddi_soft_state_fini(&mptsas_state);
670 672 scsi_hba_fini(&modlinkage);
671 673 }
672 674
673 675 return (status);
674 676 }
675 677
676 678 /*
677 679 * Notes:
678 680 * - scsi_hba_fini(9F) uninitializes SCSI HBA modules
679 681 */
680 682 int
681 683 _fini(void)
682 684 {
683 685 int status;
684 686 /* CONSTCOND */
685 687 ASSERT(NO_COMPETING_THREADS);
686 688
687 689 NDBG0(("_fini"));
688 690
689 691 if ((status = mod_remove(&modlinkage)) == 0) {
690 692 ddi_soft_state_fini(&mptsas_state);
691 693 scsi_hba_fini(&modlinkage);
692 694 mutex_destroy(&mptsas_global_mutex);
693 695 rw_destroy(&mptsas_global_rwlock);
694 696 mutex_destroy(&mptsas_log_mutex);
695 697 }
696 698 return (status);
697 699 }
698 700
699 701 /*
700 702 * The loadable-module _info(9E) entry point
701 703 */
702 704 int
703 705 _info(struct modinfo *modinfop)
704 706 {
705 707 /* CONSTCOND */
706 708 ASSERT(NO_COMPETING_THREADS);
707 709 NDBG0(("mptsas _info"));
708 710
709 711 return (mod_info(&modlinkage, modinfop));
710 712 }
711 713
712 714
713 715 static int
714 716 mptsas_iport_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
715 717 {
716 718 dev_info_t *pdip;
717 719 mptsas_t *mpt;
718 720 scsi_hba_tran_t *hba_tran;
719 721 char *iport = NULL;
720 722 char phymask[MPTSAS_MAX_PHYS];
721 723 mptsas_phymask_t phy_mask = 0;
722 724 int dynamic_port = 0;
723 725 uint32_t page_address;
724 726 char initiator_wwnstr[MPTSAS_WWN_STRLEN];
725 727 int rval = DDI_FAILURE;
726 728 int i = 0;
727 729 uint8_t numphys = 0;
728 730 uint8_t phy_id;
729 731 uint8_t phy_port = 0;
730 732 uint16_t attached_devhdl = 0;
731 733 uint32_t dev_info;
732 734 uint64_t attached_sas_wwn;
733 735 uint16_t dev_hdl;
734 736 uint16_t pdev_hdl;
735 737 uint16_t bay_num, enclosure;
736 738 char attached_wwnstr[MPTSAS_WWN_STRLEN];
737 739
738 740 /* CONSTCOND */
739 741 ASSERT(NO_COMPETING_THREADS);
740 742
741 743 switch (cmd) {
742 744 case DDI_ATTACH:
743 745 break;
744 746
745 747 case DDI_RESUME:
746 748 /*
747 749 * If this a scsi-iport node, nothing to do here.
748 750 */
749 751 return (DDI_SUCCESS);
750 752
751 753 default:
752 754 return (DDI_FAILURE);
753 755 }
754 756
755 757 pdip = ddi_get_parent(dip);
756 758
757 759 if ((hba_tran = ndi_flavorv_get(pdip, SCSA_FLAVOR_SCSI_DEVICE)) ==
758 760 NULL) {
759 761 cmn_err(CE_WARN, "Failed attach iport because fail to "
760 762 "get tran vector for the HBA node");
761 763 return (DDI_FAILURE);
762 764 }
763 765
764 766 mpt = TRAN2MPT(hba_tran);
765 767 ASSERT(mpt != NULL);
766 768 if (mpt == NULL)
767 769 return (DDI_FAILURE);
768 770
769 771 if ((hba_tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) ==
770 772 NULL) {
771 773 mptsas_log(mpt, CE_WARN, "Failed attach iport because fail to "
772 774 "get tran vector for the iport node");
773 775 return (DDI_FAILURE);
774 776 }
775 777
776 778 /*
777 779 * Overwrite parent's tran_hba_private to iport's tran vector
778 780 */
779 781 hba_tran->tran_hba_private = mpt;
780 782
781 783 ddi_report_dev(dip);
782 784
783 785 /*
784 786 * Get SAS address for initiator port according dev_handle
785 787 */
786 788 iport = ddi_get_name_addr(dip);
787 789 if (iport && strncmp(iport, "v0", 2) == 0) {
788 790 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
789 791 MPTSAS_VIRTUAL_PORT, 1) !=
790 792 DDI_PROP_SUCCESS) {
791 793 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
792 794 MPTSAS_VIRTUAL_PORT);
793 795 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
794 796 "prop update failed");
795 797 return (DDI_FAILURE);
796 798 }
797 799 return (DDI_SUCCESS);
798 800 }
799 801
800 802 mutex_enter(&mpt->m_mutex);
801 803 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
802 804 bzero(phymask, sizeof (phymask));
803 805 (void) sprintf(phymask,
804 806 "%x", mpt->m_phy_info[i].phy_mask);
805 807 if (strcmp(phymask, iport) == 0) {
806 808 break;
807 809 }
808 810 }
809 811
810 812 if (i == MPTSAS_MAX_PHYS) {
811 813 mptsas_log(mpt, CE_WARN, "Failed attach port %s because port"
812 814 "seems not exist", iport);
813 815 mutex_exit(&mpt->m_mutex);
814 816 return (DDI_FAILURE);
815 817 }
816 818
817 819 phy_mask = mpt->m_phy_info[i].phy_mask;
818 820
819 821 if (mpt->m_phy_info[i].port_flags & AUTO_PORT_CONFIGURATION)
820 822 dynamic_port = 1;
821 823 else
822 824 dynamic_port = 0;
823 825
824 826 /*
825 827 * Update PHY info for smhba
826 828 */
827 829 if (mptsas_smhba_phy_init(mpt)) {
828 830 mutex_exit(&mpt->m_mutex);
829 831 mptsas_log(mpt, CE_WARN, "mptsas phy update "
830 832 "failed");
831 833 return (DDI_FAILURE);
832 834 }
833 835
834 836 mutex_exit(&mpt->m_mutex);
835 837
836 838 numphys = 0;
837 839 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
838 840 if ((phy_mask >> i) & 0x01) {
839 841 numphys++;
840 842 }
841 843 }
842 844
843 845 bzero(initiator_wwnstr, sizeof (initiator_wwnstr));
844 846 (void) sprintf(initiator_wwnstr, "w%016"PRIx64,
845 847 mpt->un.m_base_wwid);
846 848
847 849 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip,
848 850 SCSI_ADDR_PROP_INITIATOR_PORT, initiator_wwnstr) !=
849 851 DDI_PROP_SUCCESS) {
850 852 (void) ddi_prop_remove(DDI_DEV_T_NONE,
851 853 dip, SCSI_ADDR_PROP_INITIATOR_PORT);
852 854 mptsas_log(mpt, CE_WARN, "mptsas Initiator port "
853 855 "prop update failed");
854 856 return (DDI_FAILURE);
855 857 }
856 858 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
857 859 MPTSAS_NUM_PHYS, numphys) !=
858 860 DDI_PROP_SUCCESS) {
859 861 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, MPTSAS_NUM_PHYS);
860 862 return (DDI_FAILURE);
861 863 }
862 864
863 865 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
864 866 "phymask", phy_mask) !=
865 867 DDI_PROP_SUCCESS) {
866 868 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "phymask");
867 869 mptsas_log(mpt, CE_WARN, "mptsas phy mask "
868 870 "prop update failed");
869 871 return (DDI_FAILURE);
870 872 }
871 873
872 874 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
873 875 "dynamic-port", dynamic_port) !=
874 876 DDI_PROP_SUCCESS) {
875 877 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "dynamic-port");
876 878 mptsas_log(mpt, CE_WARN, "mptsas dynamic port "
877 879 "prop update failed");
878 880 return (DDI_FAILURE);
879 881 }
880 882 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
881 883 MPTSAS_VIRTUAL_PORT, 0) !=
882 884 DDI_PROP_SUCCESS) {
883 885 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
884 886 MPTSAS_VIRTUAL_PORT);
885 887 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
886 888 "prop update failed");
887 889 return (DDI_FAILURE);
888 890 }
889 891 mptsas_smhba_set_phy_props(mpt,
890 892 iport, dip, numphys, &attached_devhdl);
891 893
892 894 mutex_enter(&mpt->m_mutex);
893 895 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
894 896 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)attached_devhdl;
895 897 rval = mptsas_get_sas_device_page0(mpt, page_address, &dev_hdl,
896 898 &attached_sas_wwn, &dev_info, &phy_port, &phy_id,
897 899 &pdev_hdl, &bay_num, &enclosure);
898 900 if (rval != DDI_SUCCESS) {
899 901 mptsas_log(mpt, CE_WARN,
900 902 "Failed to get device page0 for handle:%d",
901 903 attached_devhdl);
902 904 mutex_exit(&mpt->m_mutex);
903 905 return (DDI_FAILURE);
904 906 }
905 907
906 908 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
907 909 bzero(phymask, sizeof (phymask));
908 910 (void) sprintf(phymask, "%x", mpt->m_phy_info[i].phy_mask);
909 911 if (strcmp(phymask, iport) == 0) {
910 912 (void) sprintf(&mpt->m_phy_info[i].smhba_info.path[0],
911 913 "%x",
912 914 mpt->m_phy_info[i].phy_mask);
913 915 }
914 916 }
915 917 mutex_exit(&mpt->m_mutex);
916 918
917 919 bzero(attached_wwnstr, sizeof (attached_wwnstr));
918 920 (void) sprintf(attached_wwnstr, "w%016"PRIx64,
919 921 attached_sas_wwn);
920 922 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip,
921 923 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
922 924 DDI_PROP_SUCCESS) {
923 925 (void) ddi_prop_remove(DDI_DEV_T_NONE,
924 926 dip, SCSI_ADDR_PROP_ATTACHED_PORT);
925 927 return (DDI_FAILURE);
926 928 }
927 929
928 930 /* Create kstats for each phy on this iport */
929 931
930 932 mptsas_create_phy_stats(mpt, iport, dip);
931 933
932 934 /*
933 935 * register sas hba iport with mdi (MPxIO/vhci)
934 936 */
935 937 if (mdi_phci_register(MDI_HCI_CLASS_SCSI,
936 938 dip, 0) == MDI_SUCCESS) {
937 939 mpt->m_mpxio_enable = TRUE;
938 940 }
939 941 return (DDI_SUCCESS);
940 942 }
941 943
942 944 /*
943 945 * Notes:
944 946 * Set up all device state and allocate data structures,
945 947 * mutexes, condition variables, etc. for device operation.
946 948 * Add interrupts needed.
947 949 * Return DDI_SUCCESS if device is ready, else return DDI_FAILURE.
948 950 */
949 951 static int
950 952 mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
951 953 {
952 954 mptsas_t *mpt = NULL;
953 955 int instance, i, j;
954 956 int doneq_thread_num;
955 957 char intr_added = 0;
956 958 char map_setup = 0;
957 959 char config_setup = 0;
958 960 char hba_attach_setup = 0;
959 961 char smp_attach_setup = 0;
960 962 char mutex_init_done = 0;
961 963 char event_taskq_create = 0;
962 964 char dr_taskq_create = 0;
963 965 char doneq_thread_create = 0;
964 966 scsi_hba_tran_t *hba_tran;
965 967 uint_t mem_bar = MEM_SPACE;
966 968 int rval = DDI_FAILURE;
967 969
968 970 /* CONSTCOND */
969 971 ASSERT(NO_COMPETING_THREADS);
970 972
971 973 if (scsi_hba_iport_unit_address(dip)) {
972 974 return (mptsas_iport_attach(dip, cmd));
973 975 }
974 976
975 977 switch (cmd) {
976 978 case DDI_ATTACH:
977 979 break;
978 980
979 981 case DDI_RESUME:
980 982 if ((hba_tran = ddi_get_driver_private(dip)) == NULL)
981 983 return (DDI_FAILURE);
982 984
983 985 mpt = TRAN2MPT(hba_tran);
984 986
985 987 if (!mpt) {
986 988 return (DDI_FAILURE);
987 989 }
988 990
989 991 /*
990 992 * Reset hardware and softc to "no outstanding commands"
991 993 * Note that a check condition can result on first command
992 994 * to a target.
993 995 */
994 996 mutex_enter(&mpt->m_mutex);
995 997
996 998 /*
997 999 * raise power.
998 1000 */
999 1001 if (mpt->m_options & MPTSAS_OPT_PM) {
1000 1002 mutex_exit(&mpt->m_mutex);
1001 1003 (void) pm_busy_component(dip, 0);
1002 1004 rval = pm_power_has_changed(dip, 0, PM_LEVEL_D0);
1003 1005 if (rval == DDI_SUCCESS) {
1004 1006 mutex_enter(&mpt->m_mutex);
1005 1007 } else {
1006 1008 /*
1007 1009 * The pm_raise_power() call above failed,
1008 1010 * and that can only occur if we were unable
1009 1011 * to reset the hardware. This is probably
1010 1012 * due to unhealty hardware, and because
1011 1013 * important filesystems(such as the root
1012 1014 * filesystem) could be on the attached disks,
1013 1015 * it would not be a good idea to continue,
1014 1016 * as we won't be entirely certain we are
1015 1017 * writing correct data. So we panic() here
1016 1018 * to not only prevent possible data corruption,
1017 1019 * but to give developers or end users a hope
1018 1020 * of identifying and correcting any problems.
1019 1021 */
1020 1022 fm_panic("mptsas could not reset hardware "
1021 1023 "during resume");
1022 1024 }
1023 1025 }
1024 1026
1025 1027 mpt->m_suspended = 0;
1026 1028
1027 1029 /*
1028 1030 * Reinitialize ioc
1029 1031 */
1030 1032 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1031 1033 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) {
1032 1034 mutex_exit(&mpt->m_mutex);
1033 1035 if (mpt->m_options & MPTSAS_OPT_PM) {
1034 1036 (void) pm_idle_component(dip, 0);
1035 1037 }
1036 1038 fm_panic("mptsas init chip fail during resume");
1037 1039 }
1038 1040 /*
1039 1041 * mptsas_update_driver_data needs interrupts so enable them
1040 1042 * first.
1041 1043 */
1042 1044 MPTSAS_ENABLE_INTR(mpt);
1043 1045 mptsas_update_driver_data(mpt);
1044 1046
1045 1047 /* start requests, if possible */
1046 1048 mptsas_restart_hba(mpt);
1047 1049
1048 1050 mutex_exit(&mpt->m_mutex);
1049 1051
1050 1052 /*
1051 1053 * Restart watch thread
1052 1054 */
1053 1055 mutex_enter(&mptsas_global_mutex);
1054 1056 if (mptsas_timeout_id == 0) {
1055 1057 mptsas_timeout_id = timeout(mptsas_watch, NULL,
1056 1058 mptsas_tick);
1057 1059 mptsas_timeouts_enabled = 1;
1058 1060 }
1059 1061 mutex_exit(&mptsas_global_mutex);
1060 1062
1061 1063 /* report idle status to pm framework */
1062 1064 if (mpt->m_options & MPTSAS_OPT_PM) {
1063 1065 (void) pm_idle_component(dip, 0);
1064 1066 }
1065 1067
1066 1068 return (DDI_SUCCESS);
1067 1069
1068 1070 default:
1069 1071 return (DDI_FAILURE);
1070 1072
1071 1073 }
1072 1074
1073 1075 instance = ddi_get_instance(dip);
1074 1076
1075 1077 /*
1076 1078 * Allocate softc information.
1077 1079 */
1078 1080 if (ddi_soft_state_zalloc(mptsas_state, instance) != DDI_SUCCESS) {
1079 1081 mptsas_log(NULL, CE_WARN,
1080 1082 "mptsas%d: cannot allocate soft state", instance);
1081 1083 goto fail;
1082 1084 }
1083 1085
1084 1086 mpt = ddi_get_soft_state(mptsas_state, instance);
1085 1087
1086 1088 if (mpt == NULL) {
1087 1089 mptsas_log(NULL, CE_WARN,
1088 1090 "mptsas%d: cannot get soft state", instance);
1089 1091 goto fail;
1090 1092 }
1091 1093
1092 1094 /* Indicate that we are 'sizeof (scsi_*(9S))' clean. */
1093 1095 scsi_size_clean(dip);
1094 1096
1095 1097 mpt->m_dip = dip;
1096 1098 mpt->m_instance = instance;
1097 1099
1098 1100 /* Make a per-instance copy of the structures */
1099 1101 mpt->m_io_dma_attr = mptsas_dma_attrs64;
1100 1102 mpt->m_msg_dma_attr = mptsas_dma_attrs;
1101 1103 mpt->m_reg_acc_attr = mptsas_dev_attr;
1102 1104 mpt->m_dev_acc_attr = mptsas_dev_attr;
1103 1105
1104 1106 /*
1105 1107 * Initialize FMA
1106 1108 */
1107 1109 mpt->m_fm_capabilities = ddi_getprop(DDI_DEV_T_ANY, mpt->m_dip,
1108 1110 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable",
1109 1111 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
1110 1112 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
1111 1113
1112 1114 mptsas_fm_init(mpt);
1113 1115
1114 1116 if (mptsas_alloc_handshake_msg(mpt,
1115 1117 sizeof (Mpi2SCSITaskManagementRequest_t)) == DDI_FAILURE) {
1116 1118 mptsas_log(mpt, CE_WARN, "cannot initialize handshake msg.");
1117 1119 goto fail;
1118 1120 }
1119 1121
1120 1122 /*
1121 1123 * Setup configuration space
1122 1124 */
1123 1125 if (mptsas_config_space_init(mpt) == FALSE) {
1124 1126 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init failed");
1125 1127 goto fail;
1126 1128 }
1127 1129 config_setup++;
1128 1130
1129 1131 if (ddi_regs_map_setup(dip, mem_bar, (caddr_t *)&mpt->m_reg,
1130 1132 0, 0, &mpt->m_reg_acc_attr, &mpt->m_datap) != DDI_SUCCESS) {
1131 1133 mptsas_log(mpt, CE_WARN, "map setup failed");
1132 1134 goto fail;
1133 1135 }
1134 1136 map_setup++;
1135 1137
1136 1138 /*
1137 1139 * A taskq is created for dealing with the event handler
1138 1140 */
1139 1141 if ((mpt->m_event_taskq = ddi_taskq_create(dip, "mptsas_event_taskq",
1140 1142 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
1141 1143 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create failed");
1142 1144 goto fail;
1143 1145 }
1144 1146 event_taskq_create++;
1145 1147
1146 1148 /*
1147 1149 * A taskq is created for dealing with dr events
1148 1150 */
1149 1151 if ((mpt->m_dr_taskq = ddi_taskq_create(dip,
1150 1152 "mptsas_dr_taskq",
1151 1153 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
1152 1154 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create for discovery "
1153 1155 "failed");
1154 1156 goto fail;
1155 1157 }
1156 1158 dr_taskq_create++;
1157 1159
1158 1160 mpt->m_doneq_thread_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1159 1161 0, "mptsas_doneq_thread_threshold_prop", 10);
1160 1162 mpt->m_doneq_length_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1161 1163 0, "mptsas_doneq_length_threshold_prop", 8);
1162 1164 mpt->m_doneq_thread_n = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1163 1165 0, "mptsas_doneq_thread_n_prop", 8);
1164 1166
1165 1167 if (mpt->m_doneq_thread_n) {
1166 1168 cv_init(&mpt->m_doneq_thread_cv, NULL, CV_DRIVER, NULL);
1167 1169 mutex_init(&mpt->m_doneq_mutex, NULL, MUTEX_DRIVER, NULL);
1168 1170
1169 1171 mutex_enter(&mpt->m_doneq_mutex);
1170 1172 mpt->m_doneq_thread_id =
1171 1173 kmem_zalloc(sizeof (mptsas_doneq_thread_list_t)
1172 1174 * mpt->m_doneq_thread_n, KM_SLEEP);
1173 1175
1174 1176 for (j = 0; j < mpt->m_doneq_thread_n; j++) {
1175 1177 cv_init(&mpt->m_doneq_thread_id[j].cv, NULL,
1176 1178 CV_DRIVER, NULL);
1177 1179 mutex_init(&mpt->m_doneq_thread_id[j].mutex, NULL,
1178 1180 MUTEX_DRIVER, NULL);
1179 1181 mutex_enter(&mpt->m_doneq_thread_id[j].mutex);
1180 1182 mpt->m_doneq_thread_id[j].flag |=
1181 1183 MPTSAS_DONEQ_THREAD_ACTIVE;
1182 1184 mpt->m_doneq_thread_id[j].arg.mpt = mpt;
1183 1185 mpt->m_doneq_thread_id[j].arg.t = j;
1184 1186 mpt->m_doneq_thread_id[j].threadp =
1185 1187 thread_create(NULL, 0, mptsas_doneq_thread,
1186 1188 &mpt->m_doneq_thread_id[j].arg,
1187 1189 0, &p0, TS_RUN, minclsyspri);
1188 1190 mpt->m_doneq_thread_id[j].donetail =
1189 1191 &mpt->m_doneq_thread_id[j].doneq;
1190 1192 mutex_exit(&mpt->m_doneq_thread_id[j].mutex);
1191 1193 }
1192 1194 mutex_exit(&mpt->m_doneq_mutex);
1193 1195 doneq_thread_create++;
1194 1196 }
1195 1197
1196 1198 /* Initialize mutex used in interrupt handler */
1197 1199 mutex_init(&mpt->m_mutex, NULL, MUTEX_DRIVER,
1198 1200 DDI_INTR_PRI(mpt->m_intr_pri));
1199 1201 mutex_init(&mpt->m_passthru_mutex, NULL, MUTEX_DRIVER, NULL);
1200 1202 mutex_init(&mpt->m_intr_mutex, NULL, MUTEX_DRIVER,
1201 1203 DDI_INTR_PRI(mpt->m_intr_pri));
1202 1204 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1203 1205 mutex_init(&mpt->m_phy_info[i].smhba_info.phy_mutex,
1204 1206 NULL, MUTEX_DRIVER,
1205 1207 DDI_INTR_PRI(mpt->m_intr_pri));
1206 1208 }
1207 1209
1208 1210 cv_init(&mpt->m_cv, NULL, CV_DRIVER, NULL);
1209 1211 cv_init(&mpt->m_passthru_cv, NULL, CV_DRIVER, NULL);
1210 1212 cv_init(&mpt->m_fw_cv, NULL, CV_DRIVER, NULL);
1211 1213 cv_init(&mpt->m_config_cv, NULL, CV_DRIVER, NULL);
1212 1214 cv_init(&mpt->m_fw_diag_cv, NULL, CV_DRIVER, NULL);
1213 1215 mutex_init_done++;
1214 1216
1215 1217 /*
1216 1218 * Disable hardware interrupt since we're not ready to
1217 1219 * handle it yet.
1218 1220 */
1219 1221 MPTSAS_DISABLE_INTR(mpt);
1220 1222 if (mptsas_register_intrs(mpt) == FALSE)
1221 1223 goto fail;
1222 1224 intr_added++;
1223 1225
1224 1226 mutex_enter(&mpt->m_mutex);
1225 1227 /*
1226 1228 * Initialize power management component
1227 1229 */
1228 1230 if (mpt->m_options & MPTSAS_OPT_PM) {
1229 1231 if (mptsas_init_pm(mpt)) {
1230 1232 mutex_exit(&mpt->m_mutex);
1231 1233 mptsas_log(mpt, CE_WARN, "mptsas pm initialization "
1232 1234 "failed");
1233 1235 goto fail;
1234 1236 }
1235 1237 }
1236 1238
1237 1239 /*
1238 1240 * Initialize chip using Message Unit Reset, if allowed
1239 1241 */
1240 1242 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1241 1243 if (mptsas_init_chip(mpt, TRUE) == DDI_FAILURE) {
1242 1244 mutex_exit(&mpt->m_mutex);
1243 1245 mptsas_log(mpt, CE_WARN, "mptsas chip initialization failed");
1244 1246 goto fail;
1245 1247 }
1246 1248
1247 1249 /*
1248 1250 * Fill in the phy_info structure and get the base WWID
1249 1251 */
1250 1252 if (mptsas_get_manufacture_page5(mpt) == DDI_FAILURE) {
1251 1253 mptsas_log(mpt, CE_WARN,
1252 1254 "mptsas_get_manufacture_page5 failed!");
1253 1255 goto fail;
1254 1256 }
1255 1257
1256 1258 if (mptsas_get_sas_io_unit_page_hndshk(mpt)) {
1257 1259 mptsas_log(mpt, CE_WARN,
1258 1260 "mptsas_get_sas_io_unit_page_hndshk failed!");
1259 1261 goto fail;
1260 1262 }
1261 1263
1262 1264 if (mptsas_get_manufacture_page0(mpt) == DDI_FAILURE) {
1263 1265 mptsas_log(mpt, CE_WARN,
1264 1266 "mptsas_get_manufacture_page0 failed!");
1265 1267 goto fail;
1266 1268 }
1267 1269
1268 1270 mutex_exit(&mpt->m_mutex);
1269 1271
1270 1272 /*
1271 1273 * Register the iport for multiple port HBA
1272 1274 */
1273 1275 mptsas_iport_register(mpt);
1274 1276
1275 1277 /*
1276 1278 * initialize SCSI HBA transport structure
1277 1279 */
1278 1280 if (mptsas_hba_setup(mpt) == FALSE)
1279 1281 goto fail;
1280 1282 hba_attach_setup++;
1281 1283
1282 1284 if (mptsas_smp_setup(mpt) == FALSE)
1283 1285 goto fail;
1284 1286 smp_attach_setup++;
1285 1287
1286 1288 if (mptsas_cache_create(mpt) == FALSE)
1287 1289 goto fail;
1288 1290
1289 1291 mpt->m_scsi_reset_delay = ddi_prop_get_int(DDI_DEV_T_ANY,
1290 1292 dip, 0, "scsi-reset-delay", SCSI_DEFAULT_RESET_DELAY);
1291 1293 if (mpt->m_scsi_reset_delay == 0) {
1292 1294 mptsas_log(mpt, CE_NOTE,
1293 1295 "scsi_reset_delay of 0 is not recommended,"
1294 1296 " resetting to SCSI_DEFAULT_RESET_DELAY\n");
1295 1297 mpt->m_scsi_reset_delay = SCSI_DEFAULT_RESET_DELAY;
1296 1298 }
1297 1299
1298 1300 /*
1299 1301 * Initialize the wait and done FIFO queue
1300 1302 */
1301 1303 mpt->m_donetail = &mpt->m_doneq;
1302 1304 mpt->m_waitqtail = &mpt->m_waitq;
1303 1305
1304 1306 /*
1305 1307 * ioc cmd queue initialize
1306 1308 */
1307 1309 mpt->m_ioc_event_cmdtail = &mpt->m_ioc_event_cmdq;
1308 1310 mpt->m_dev_handle = 0xFFFF;
1309 1311
1310 1312 MPTSAS_ENABLE_INTR(mpt);
1311 1313
1312 1314 /*
1313 1315 * enable event notification
1314 1316 */
1315 1317 mutex_enter(&mpt->m_mutex);
1316 1318 if (mptsas_ioc_enable_event_notification(mpt)) {
1317 1319 mutex_exit(&mpt->m_mutex);
1318 1320 goto fail;
1319 1321 }
1320 1322 mutex_exit(&mpt->m_mutex);
1321 1323
1322 1324 /*
1323 1325 * Initialize PHY info for smhba
1324 1326 */
1325 1327 if (mptsas_smhba_setup(mpt)) {
1326 1328 mptsas_log(mpt, CE_WARN, "mptsas phy initialization "
1327 1329 "failed");
1328 1330 goto fail;
1329 1331 }
1330 1332
1331 1333 /* Check all dma handles allocated in attach */
1332 1334 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl)
1333 1335 != DDI_SUCCESS) ||
1334 1336 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl)
1335 1337 != DDI_SUCCESS) ||
1336 1338 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl)
1337 1339 != DDI_SUCCESS) ||
1338 1340 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl)
1339 1341 != DDI_SUCCESS) ||
1340 1342 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl)
1341 1343 != DDI_SUCCESS)) {
1342 1344 goto fail;
1343 1345 }
1344 1346
1345 1347 /* Check all acc handles allocated in attach */
1346 1348 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) ||
1347 1349 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl)
1348 1350 != DDI_SUCCESS) ||
1349 1351 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl)
1350 1352 != DDI_SUCCESS) ||
1351 1353 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl)
1352 1354 != DDI_SUCCESS) ||
1353 1355 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl)
1354 1356 != DDI_SUCCESS) ||
1355 1357 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl)
1356 1358 != DDI_SUCCESS) ||
1357 1359 (mptsas_check_acc_handle(mpt->m_config_handle)
1358 1360 != DDI_SUCCESS)) {
1359 1361 goto fail;
1360 1362 }
1361 1363
1362 1364 /*
1363 1365 * After this point, we are not going to fail the attach.
1364 1366 */
1365 1367 /*
1366 1368 * used for mptsas_watch
1367 1369 */
1368 1370 mptsas_list_add(mpt);
1369 1371
1370 1372 mutex_enter(&mptsas_global_mutex);
1371 1373 if (mptsas_timeouts_enabled == 0) {
1372 1374 mptsas_scsi_watchdog_tick = ddi_prop_get_int(DDI_DEV_T_ANY,
1373 1375 dip, 0, "scsi-watchdog-tick", DEFAULT_WD_TICK);
1374 1376
1375 1377 mptsas_tick = mptsas_scsi_watchdog_tick *
1376 1378 drv_usectohz((clock_t)1000000);
1377 1379
1378 1380 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick);
1379 1381 mptsas_timeouts_enabled = 1;
1380 1382 }
1381 1383 mutex_exit(&mptsas_global_mutex);
1382 1384
1383 1385 /* Print message of HBA present */
1384 1386 ddi_report_dev(dip);
1385 1387
1386 1388 /* report idle status to pm framework */
1387 1389 if (mpt->m_options & MPTSAS_OPT_PM) {
1388 1390 (void) pm_idle_component(dip, 0);
1389 1391 }
1390 1392
1391 1393 return (DDI_SUCCESS);
1392 1394
1393 1395 fail:
1394 1396 mptsas_log(mpt, CE_WARN, "attach failed");
1395 1397 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE);
1396 1398 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST);
1397 1399 if (mpt) {
1398 1400 mutex_enter(&mptsas_global_mutex);
1399 1401
1400 1402 if (mptsas_timeout_id && (mptsas_head == NULL)) {
1401 1403 timeout_id_t tid = mptsas_timeout_id;
1402 1404 mptsas_timeouts_enabled = 0;
1403 1405 mptsas_timeout_id = 0;
1404 1406 mutex_exit(&mptsas_global_mutex);
1405 1407 (void) untimeout(tid);
1406 1408 mutex_enter(&mptsas_global_mutex);
1407 1409 }
1408 1410 mutex_exit(&mptsas_global_mutex);
1409 1411 /* deallocate in reverse order */
1410 1412 mptsas_cache_destroy(mpt);
1411 1413
1412 1414 if (smp_attach_setup) {
1413 1415 mptsas_smp_teardown(mpt);
1414 1416 }
1415 1417 if (hba_attach_setup) {
1416 1418 mptsas_hba_teardown(mpt);
1417 1419 }
1418 1420
1419 1421 if (mpt->m_active) {
1420 1422 mptsas_hash_uninit(&mpt->m_active->m_smptbl,
1421 1423 sizeof (mptsas_smp_t));
1422 1424 mptsas_hash_uninit(&mpt->m_active->m_tgttbl,
1423 1425 sizeof (mptsas_target_t));
1424 1426 mptsas_free_active_slots(mpt);
1425 1427 }
1426 1428 if (intr_added) {
1427 1429 mptsas_unregister_intrs(mpt);
1428 1430 }
1429 1431
1430 1432 if (doneq_thread_create) {
1431 1433 mutex_enter(&mpt->m_doneq_mutex);
1432 1434 doneq_thread_num = mpt->m_doneq_thread_n;
1433 1435 for (j = 0; j < mpt->m_doneq_thread_n; j++) {
1434 1436 mutex_enter(&mpt->m_doneq_thread_id[j].mutex);
1435 1437 mpt->m_doneq_thread_id[j].flag &=
1436 1438 (~MPTSAS_DONEQ_THREAD_ACTIVE);
1437 1439 cv_signal(&mpt->m_doneq_thread_id[j].cv);
1438 1440 mutex_exit(&mpt->m_doneq_thread_id[j].mutex);
1439 1441 }
1440 1442 while (mpt->m_doneq_thread_n) {
1441 1443 cv_wait(&mpt->m_doneq_thread_cv,
1442 1444 &mpt->m_doneq_mutex);
1443 1445 }
1444 1446 for (j = 0; j < doneq_thread_num; j++) {
1445 1447 cv_destroy(&mpt->m_doneq_thread_id[j].cv);
1446 1448 mutex_destroy(&mpt->m_doneq_thread_id[j].mutex);
1447 1449 }
1448 1450 kmem_free(mpt->m_doneq_thread_id,
1449 1451 sizeof (mptsas_doneq_thread_list_t)
1450 1452 * doneq_thread_num);
1451 1453 mutex_exit(&mpt->m_doneq_mutex);
1452 1454 cv_destroy(&mpt->m_doneq_thread_cv);
1453 1455 mutex_destroy(&mpt->m_doneq_mutex);
1454 1456 }
1455 1457 if (event_taskq_create) {
1456 1458 ddi_taskq_destroy(mpt->m_event_taskq);
1457 1459 }
1458 1460 if (dr_taskq_create) {
1459 1461 ddi_taskq_destroy(mpt->m_dr_taskq);
1460 1462 }
1461 1463 if (mutex_init_done) {
1462 1464 mutex_destroy(&mpt->m_intr_mutex);
1463 1465 mutex_destroy(&mpt->m_passthru_mutex);
1464 1466 mutex_destroy(&mpt->m_mutex);
1465 1467 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1466 1468 mutex_destroy(
1467 1469 &mpt->m_phy_info[i].smhba_info.phy_mutex);
1468 1470 }
1469 1471 cv_destroy(&mpt->m_cv);
1470 1472 cv_destroy(&mpt->m_passthru_cv);
1471 1473 cv_destroy(&mpt->m_fw_cv);
1472 1474 cv_destroy(&mpt->m_config_cv);
1473 1475 cv_destroy(&mpt->m_fw_diag_cv);
1474 1476 }
1475 1477
1476 1478 if (map_setup) {
1477 1479 mptsas_cfg_fini(mpt);
1478 1480 }
1479 1481 if (config_setup) {
1480 1482 mptsas_config_space_fini(mpt);
1481 1483 }
1482 1484 mptsas_free_handshake_msg(mpt);
1483 1485 mptsas_hba_fini(mpt);
1484 1486
1485 1487 mptsas_fm_fini(mpt);
1486 1488 ddi_soft_state_free(mptsas_state, instance);
1487 1489 ddi_prop_remove_all(dip);
1488 1490 }
1489 1491 return (DDI_FAILURE);
1490 1492 }
1491 1493
1492 1494 static int
1493 1495 mptsas_suspend(dev_info_t *devi)
1494 1496 {
1495 1497 mptsas_t *mpt, *g;
1496 1498 scsi_hba_tran_t *tran;
1497 1499
1498 1500 if (scsi_hba_iport_unit_address(devi)) {
1499 1501 return (DDI_SUCCESS);
1500 1502 }
1501 1503
1502 1504 if ((tran = ddi_get_driver_private(devi)) == NULL)
1503 1505 return (DDI_SUCCESS);
1504 1506
1505 1507 mpt = TRAN2MPT(tran);
1506 1508 if (!mpt) {
1507 1509 return (DDI_SUCCESS);
1508 1510 }
1509 1511
1510 1512 mutex_enter(&mpt->m_mutex);
1511 1513
1512 1514 if (mpt->m_suspended++) {
1513 1515 mutex_exit(&mpt->m_mutex);
1514 1516 return (DDI_SUCCESS);
1515 1517 }
1516 1518
1517 1519 /*
1518 1520 * Cancel timeout threads for this mpt
1519 1521 */
1520 1522 if (mpt->m_quiesce_timeid) {
1521 1523 timeout_id_t tid = mpt->m_quiesce_timeid;
1522 1524 mpt->m_quiesce_timeid = 0;
1523 1525 mutex_exit(&mpt->m_mutex);
1524 1526 (void) untimeout(tid);
1525 1527 mutex_enter(&mpt->m_mutex);
1526 1528 }
1527 1529
1528 1530 if (mpt->m_restart_cmd_timeid) {
1529 1531 timeout_id_t tid = mpt->m_restart_cmd_timeid;
1530 1532 mpt->m_restart_cmd_timeid = 0;
1531 1533 mutex_exit(&mpt->m_mutex);
1532 1534 (void) untimeout(tid);
1533 1535 mutex_enter(&mpt->m_mutex);
1534 1536 }
1535 1537
1536 1538 mutex_exit(&mpt->m_mutex);
1537 1539
1538 1540 (void) pm_idle_component(mpt->m_dip, 0);
1539 1541
1540 1542 /*
1541 1543 * Cancel watch threads if all mpts suspended
1542 1544 */
1543 1545 rw_enter(&mptsas_global_rwlock, RW_WRITER);
1544 1546 for (g = mptsas_head; g != NULL; g = g->m_next) {
1545 1547 if (!g->m_suspended)
1546 1548 break;
1547 1549 }
1548 1550 rw_exit(&mptsas_global_rwlock);
1549 1551
1550 1552 mutex_enter(&mptsas_global_mutex);
1551 1553 if (g == NULL) {
1552 1554 timeout_id_t tid;
1553 1555
1554 1556 mptsas_timeouts_enabled = 0;
1555 1557 if (mptsas_timeout_id) {
1556 1558 tid = mptsas_timeout_id;
1557 1559 mptsas_timeout_id = 0;
1558 1560 mutex_exit(&mptsas_global_mutex);
1559 1561 (void) untimeout(tid);
1560 1562 mutex_enter(&mptsas_global_mutex);
1561 1563 }
1562 1564 if (mptsas_reset_watch) {
1563 1565 tid = mptsas_reset_watch;
1564 1566 mptsas_reset_watch = 0;
1565 1567 mutex_exit(&mptsas_global_mutex);
1566 1568 (void) untimeout(tid);
1567 1569 mutex_enter(&mptsas_global_mutex);
1568 1570 }
1569 1571 }
1570 1572 mutex_exit(&mptsas_global_mutex);
1571 1573
1572 1574 mutex_enter(&mpt->m_mutex);
1573 1575
1574 1576 /*
1575 1577 * If this mpt is not in full power(PM_LEVEL_D0), just return.
1576 1578 */
1577 1579 if ((mpt->m_options & MPTSAS_OPT_PM) &&
1578 1580 (mpt->m_power_level != PM_LEVEL_D0)) {
1579 1581 mutex_exit(&mpt->m_mutex);
1580 1582 return (DDI_SUCCESS);
1581 1583 }
1582 1584
1583 1585 /* Disable HBA interrupts in hardware */
1584 1586 MPTSAS_DISABLE_INTR(mpt);
1585 1587 /*
1586 1588 * Send RAID action system shutdown to sync IR
1587 1589 */
1588 1590 mptsas_raid_action_system_shutdown(mpt);
1589 1591
1590 1592 mutex_exit(&mpt->m_mutex);
1591 1593
1592 1594 /* drain the taskq */
1593 1595 ddi_taskq_wait(mpt->m_event_taskq);
1594 1596 ddi_taskq_wait(mpt->m_dr_taskq);
1595 1597
1596 1598 return (DDI_SUCCESS);
1597 1599 }
1598 1600
1599 1601 #ifdef __sparc
1600 1602 /*ARGSUSED*/
1601 1603 static int
1602 1604 mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd)
1603 1605 {
1604 1606 mptsas_t *mpt;
1605 1607 scsi_hba_tran_t *tran;
1606 1608
1607 1609 /*
1608 1610 * If this call is for iport, just return.
1609 1611 */
1610 1612 if (scsi_hba_iport_unit_address(devi))
1611 1613 return (DDI_SUCCESS);
1612 1614
1613 1615 if ((tran = ddi_get_driver_private(devi)) == NULL)
1614 1616 return (DDI_SUCCESS);
1615 1617
1616 1618 if ((mpt = TRAN2MPT(tran)) == NULL)
1617 1619 return (DDI_SUCCESS);
1618 1620
1619 1621 /*
1620 1622 * Send RAID action system shutdown to sync IR. Disable HBA
1621 1623 * interrupts in hardware first.
1622 1624 */
1623 1625 MPTSAS_DISABLE_INTR(mpt);
1624 1626 mptsas_raid_action_system_shutdown(mpt);
1625 1627
1626 1628 return (DDI_SUCCESS);
1627 1629 }
1628 1630 #else /* __sparc */
1629 1631 /*
1630 1632 * quiesce(9E) entry point.
1631 1633 *
1632 1634 * This function is called when the system is single-threaded at high
1633 1635 * PIL with preemption disabled. Therefore, this function must not be
1634 1636 * blocked.
1635 1637 *
1636 1638 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
1637 1639 * DDI_FAILURE indicates an error condition and should almost never happen.
1638 1640 */
1639 1641 static int
1640 1642 mptsas_quiesce(dev_info_t *devi)
1641 1643 {
1642 1644 mptsas_t *mpt;
1643 1645 scsi_hba_tran_t *tran;
1644 1646
1645 1647 /*
1646 1648 * If this call is for iport, just return.
1647 1649 */
1648 1650 if (scsi_hba_iport_unit_address(devi))
1649 1651 return (DDI_SUCCESS);
1650 1652
1651 1653 if ((tran = ddi_get_driver_private(devi)) == NULL)
1652 1654 return (DDI_SUCCESS);
1653 1655
1654 1656 if ((mpt = TRAN2MPT(tran)) == NULL)
1655 1657 return (DDI_SUCCESS);
1656 1658
1657 1659 /* Disable HBA interrupts in hardware */
1658 1660 MPTSAS_DISABLE_INTR(mpt);
1659 1661 /* Send RAID action system shutdonw to sync IR */
1660 1662 mptsas_raid_action_system_shutdown(mpt);
1661 1663
1662 1664 return (DDI_SUCCESS);
1663 1665 }
1664 1666 #endif /* __sparc */
1665 1667
1666 1668 /*
1667 1669 * detach(9E). Remove all device allocations and system resources;
1668 1670 * disable device interrupts.
1669 1671 * Return DDI_SUCCESS if done; DDI_FAILURE if there's a problem.
1670 1672 */
1671 1673 static int
1672 1674 mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd)
1673 1675 {
1674 1676 /* CONSTCOND */
1675 1677 ASSERT(NO_COMPETING_THREADS);
1676 1678 NDBG0(("mptsas_detach: dip=0x%p cmd=0x%p", (void *)devi, (void *)cmd));
1677 1679
1678 1680 switch (cmd) {
1679 1681 case DDI_DETACH:
1680 1682 return (mptsas_do_detach(devi));
1681 1683
1682 1684 case DDI_SUSPEND:
1683 1685 return (mptsas_suspend(devi));
1684 1686
1685 1687 default:
1686 1688 return (DDI_FAILURE);
1687 1689 }
1688 1690 /* NOTREACHED */
1689 1691 }
1690 1692
1691 1693 static int
1692 1694 mptsas_do_detach(dev_info_t *dip)
1693 1695 {
1694 1696 mptsas_t *mpt;
1695 1697 scsi_hba_tran_t *tran;
1696 1698 int circ = 0;
1697 1699 int circ1 = 0;
1698 1700 mdi_pathinfo_t *pip = NULL;
1699 1701 int i;
1700 1702 int doneq_thread_num = 0;
1701 1703
1702 1704 NDBG0(("mptsas_do_detach: dip=0x%p", (void *)dip));
1703 1705
1704 1706 if ((tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == NULL)
1705 1707 return (DDI_FAILURE);
1706 1708
1707 1709 mpt = TRAN2MPT(tran);
1708 1710 if (!mpt) {
1709 1711 return (DDI_FAILURE);
1710 1712 }
1711 1713 /*
1712 1714 * Still have pathinfo child, should not detach mpt driver
1713 1715 */
1714 1716 if (scsi_hba_iport_unit_address(dip)) {
1715 1717 if (mpt->m_mpxio_enable) {
1716 1718 /*
1717 1719 * MPxIO enabled for the iport
1718 1720 */
1719 1721 ndi_devi_enter(scsi_vhci_dip, &circ1);
1720 1722 ndi_devi_enter(dip, &circ);
1721 1723 while (pip = mdi_get_next_client_path(dip, NULL)) {
1722 1724 if (mdi_pi_free(pip, 0) == MDI_SUCCESS) {
1723 1725 continue;
1724 1726 }
1725 1727 ndi_devi_exit(dip, circ);
1726 1728 ndi_devi_exit(scsi_vhci_dip, circ1);
1727 1729 NDBG12(("detach failed because of "
1728 1730 "outstanding path info"));
1729 1731 return (DDI_FAILURE);
1730 1732 }
1731 1733 ndi_devi_exit(dip, circ);
1732 1734 ndi_devi_exit(scsi_vhci_dip, circ1);
1733 1735 (void) mdi_phci_unregister(dip, 0);
1734 1736 }
1735 1737
1736 1738 ddi_prop_remove_all(dip);
1737 1739
1738 1740 return (DDI_SUCCESS);
1739 1741 }
1740 1742
1741 1743 /* Make sure power level is D0 before accessing registers */
1742 1744 if (mpt->m_options & MPTSAS_OPT_PM) {
1743 1745 (void) pm_busy_component(dip, 0);
1744 1746 if (mpt->m_power_level != PM_LEVEL_D0) {
1745 1747 if (pm_raise_power(dip, 0, PM_LEVEL_D0) !=
1746 1748 DDI_SUCCESS) {
1747 1749 mptsas_log(mpt, CE_WARN,
1748 1750 "mptsas%d: Raise power request failed.",
1749 1751 mpt->m_instance);
1750 1752 (void) pm_idle_component(dip, 0);
1751 1753 return (DDI_FAILURE);
1752 1754 }
1753 1755 }
1754 1756 }
1755 1757
1756 1758 /*
1757 1759 * Send RAID action system shutdown to sync IR. After action, send a
1758 1760 * Message Unit Reset. Since after that DMA resource will be freed,
1759 1761 * set ioc to READY state will avoid HBA initiated DMA operation.
1760 1762 */
1761 1763 mutex_enter(&mpt->m_mutex);
1762 1764 MPTSAS_DISABLE_INTR(mpt);
1763 1765 mptsas_raid_action_system_shutdown(mpt);
1764 1766 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1765 1767 (void) mptsas_ioc_reset(mpt, FALSE);
1766 1768 mutex_exit(&mpt->m_mutex);
1767 1769 mptsas_rem_intrs(mpt);
1768 1770 ddi_taskq_destroy(mpt->m_event_taskq);
1769 1771 ddi_taskq_destroy(mpt->m_dr_taskq);
1770 1772
1771 1773 if (mpt->m_doneq_thread_n) {
1772 1774 mutex_enter(&mpt->m_doneq_mutex);
1773 1775 doneq_thread_num = mpt->m_doneq_thread_n;
1774 1776 for (i = 0; i < mpt->m_doneq_thread_n; i++) {
1775 1777 mutex_enter(&mpt->m_doneq_thread_id[i].mutex);
1776 1778 mpt->m_doneq_thread_id[i].flag &=
1777 1779 (~MPTSAS_DONEQ_THREAD_ACTIVE);
1778 1780 cv_signal(&mpt->m_doneq_thread_id[i].cv);
1779 1781 mutex_exit(&mpt->m_doneq_thread_id[i].mutex);
1780 1782 }
1781 1783 while (mpt->m_doneq_thread_n) {
1782 1784 cv_wait(&mpt->m_doneq_thread_cv,
1783 1785 &mpt->m_doneq_mutex);
1784 1786 }
1785 1787 for (i = 0; i < doneq_thread_num; i++) {
1786 1788 cv_destroy(&mpt->m_doneq_thread_id[i].cv);
1787 1789 mutex_destroy(&mpt->m_doneq_thread_id[i].mutex);
1788 1790 }
1789 1791 kmem_free(mpt->m_doneq_thread_id,
1790 1792 sizeof (mptsas_doneq_thread_list_t)
1791 1793 * doneq_thread_num);
1792 1794 mutex_exit(&mpt->m_doneq_mutex);
1793 1795 cv_destroy(&mpt->m_doneq_thread_cv);
1794 1796 mutex_destroy(&mpt->m_doneq_mutex);
1795 1797 }
1796 1798
1797 1799 scsi_hba_reset_notify_tear_down(mpt->m_reset_notify_listf);
1798 1800
1799 1801 mptsas_list_del(mpt);
1800 1802
1801 1803 /*
1802 1804 * Cancel timeout threads for this mpt
1803 1805 */
1804 1806 mutex_enter(&mpt->m_mutex);
1805 1807 if (mpt->m_quiesce_timeid) {
1806 1808 timeout_id_t tid = mpt->m_quiesce_timeid;
1807 1809 mpt->m_quiesce_timeid = 0;
1808 1810 mutex_exit(&mpt->m_mutex);
1809 1811 (void) untimeout(tid);
1810 1812 mutex_enter(&mpt->m_mutex);
1811 1813 }
1812 1814
1813 1815 if (mpt->m_restart_cmd_timeid) {
1814 1816 timeout_id_t tid = mpt->m_restart_cmd_timeid;
1815 1817 mpt->m_restart_cmd_timeid = 0;
1816 1818 mutex_exit(&mpt->m_mutex);
1817 1819 (void) untimeout(tid);
1818 1820 mutex_enter(&mpt->m_mutex);
1819 1821 }
1820 1822
1821 1823 mutex_exit(&mpt->m_mutex);
1822 1824
1823 1825 /*
1824 1826 * last mpt? ... if active, CANCEL watch threads.
1825 1827 */
1826 1828 mutex_enter(&mptsas_global_mutex);
1827 1829 if (mptsas_head == NULL) {
1828 1830 timeout_id_t tid;
1829 1831 /*
1830 1832 * Clear mptsas_timeouts_enable so that the watch thread
1831 1833 * gets restarted on DDI_ATTACH
1832 1834 */
1833 1835 mptsas_timeouts_enabled = 0;
1834 1836 if (mptsas_timeout_id) {
1835 1837 tid = mptsas_timeout_id;
1836 1838 mptsas_timeout_id = 0;
1837 1839 mutex_exit(&mptsas_global_mutex);
1838 1840 (void) untimeout(tid);
1839 1841 mutex_enter(&mptsas_global_mutex);
1840 1842 }
1841 1843 if (mptsas_reset_watch) {
1842 1844 tid = mptsas_reset_watch;
1843 1845 mptsas_reset_watch = 0;
1844 1846 mutex_exit(&mptsas_global_mutex);
1845 1847 (void) untimeout(tid);
1846 1848 mutex_enter(&mptsas_global_mutex);
1847 1849 }
1848 1850 }
1849 1851 mutex_exit(&mptsas_global_mutex);
1850 1852
1851 1853 /*
1852 1854 * Delete Phy stats
1853 1855 */
1854 1856 mptsas_destroy_phy_stats(mpt);
1855 1857
1856 1858 /*
1857 1859 * Delete nt_active.
1858 1860 */
1859 1861 mutex_enter(&mpt->m_mutex);
1860 1862 mptsas_hash_uninit(&mpt->m_active->m_tgttbl, sizeof (mptsas_target_t));
1861 1863 mptsas_hash_uninit(&mpt->m_active->m_smptbl, sizeof (mptsas_smp_t));
1862 1864 mptsas_free_active_slots(mpt);
1863 1865 mutex_exit(&mpt->m_mutex);
1864 1866
1865 1867 /* deallocate everything that was allocated in mptsas_attach */
1866 1868 mptsas_cache_destroy(mpt);
1867 1869
1868 1870 mptsas_hba_fini(mpt);
1869 1871 mptsas_cfg_fini(mpt);
1870 1872
1871 1873 /* Lower the power informing PM Framework */
1872 1874 if (mpt->m_options & MPTSAS_OPT_PM) {
1873 1875 if (pm_lower_power(dip, 0, PM_LEVEL_D3) != DDI_SUCCESS)
1874 1876 mptsas_log(mpt, CE_WARN,
1875 1877 "!mptsas%d: Lower power request failed "
1876 1878 "during detach, ignoring.",
1877 1879 mpt->m_instance);
1878 1880 }
1879 1881
1880 1882 mutex_destroy(&mpt->m_intr_mutex);
1881 1883 mutex_destroy(&mpt->m_passthru_mutex);
1882 1884 mutex_destroy(&mpt->m_mutex);
1883 1885 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1884 1886 mutex_destroy(&mpt->m_phy_info[i].smhba_info.phy_mutex);
1885 1887 }
1886 1888 cv_destroy(&mpt->m_cv);
1887 1889 cv_destroy(&mpt->m_passthru_cv);
1888 1890 cv_destroy(&mpt->m_fw_cv);
1889 1891 cv_destroy(&mpt->m_config_cv);
1890 1892 cv_destroy(&mpt->m_fw_diag_cv);
1891 1893
1892 1894
1893 1895 mptsas_smp_teardown(mpt);
1894 1896 mptsas_hba_teardown(mpt);
1895 1897
1896 1898 mptsas_config_space_fini(mpt);
1897 1899
1898 1900 mptsas_free_handshake_msg(mpt);
1899 1901
1900 1902 mptsas_fm_fini(mpt);
1901 1903 ddi_soft_state_free(mptsas_state, ddi_get_instance(dip));
1902 1904 ddi_prop_remove_all(dip);
1903 1905
1904 1906 return (DDI_SUCCESS);
1905 1907 }
1906 1908
1907 1909 static void
1908 1910 mptsas_list_add(mptsas_t *mpt)
1909 1911 {
1910 1912 rw_enter(&mptsas_global_rwlock, RW_WRITER);
1911 1913
1912 1914 if (mptsas_head == NULL) {
1913 1915 mptsas_head = mpt;
1914 1916 } else {
1915 1917 mptsas_tail->m_next = mpt;
1916 1918 }
1917 1919 mptsas_tail = mpt;
1918 1920 rw_exit(&mptsas_global_rwlock);
1919 1921 }
1920 1922
1921 1923 static void
1922 1924 mptsas_list_del(mptsas_t *mpt)
1923 1925 {
1924 1926 mptsas_t *m;
1925 1927 /*
1926 1928 * Remove device instance from the global linked list
1927 1929 */
1928 1930 rw_enter(&mptsas_global_rwlock, RW_WRITER);
1929 1931 if (mptsas_head == mpt) {
1930 1932 m = mptsas_head = mpt->m_next;
1931 1933 } else {
1932 1934 for (m = mptsas_head; m != NULL; m = m->m_next) {
1933 1935 if (m->m_next == mpt) {
1934 1936 m->m_next = mpt->m_next;
1935 1937 break;
1936 1938 }
1937 1939 }
1938 1940 if (m == NULL) {
1939 1941 mptsas_log(mpt, CE_PANIC, "Not in softc list!");
1940 1942 }
1941 1943 }
1942 1944
1943 1945 if (mptsas_tail == mpt) {
1944 1946 mptsas_tail = m;
1945 1947 }
1946 1948 rw_exit(&mptsas_global_rwlock);
1947 1949 }
1948 1950
1949 1951 static int
1950 1952 mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size)
1951 1953 {
1952 1954 ddi_dma_attr_t task_dma_attrs;
1953 1955
1954 1956 task_dma_attrs = mpt->m_msg_dma_attr;
1955 1957 task_dma_attrs.dma_attr_sgllen = 1;
1956 1958 task_dma_attrs.dma_attr_granular = (uint32_t)(alloc_size);
1957 1959
1958 1960 /* allocate Task Management ddi_dma resources */
1959 1961 if (mptsas_dma_addr_create(mpt, task_dma_attrs,
1960 1962 &mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl, &mpt->m_hshk_memp,
1961 1963 alloc_size, NULL) == FALSE) {
1962 1964 return (DDI_FAILURE);
1963 1965 }
1964 1966 mpt->m_hshk_dma_size = alloc_size;
1965 1967
1966 1968 return (DDI_SUCCESS);
1967 1969 }
1968 1970
1969 1971 static void
1970 1972 mptsas_free_handshake_msg(mptsas_t *mpt)
1971 1973 {
1972 1974 mptsas_dma_addr_destroy(&mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl);
1973 1975 mpt->m_hshk_dma_size = 0;
1974 1976 }
1975 1977
1976 1978 static int
1977 1979 mptsas_hba_setup(mptsas_t *mpt)
1978 1980 {
1979 1981 scsi_hba_tran_t *hba_tran;
1980 1982 int tran_flags;
1981 1983
1982 1984 /* Allocate a transport structure */
1983 1985 hba_tran = mpt->m_tran = scsi_hba_tran_alloc(mpt->m_dip,
1984 1986 SCSI_HBA_CANSLEEP);
1985 1987 ASSERT(mpt->m_tran != NULL);
1986 1988
1987 1989 hba_tran->tran_hba_private = mpt;
1988 1990 hba_tran->tran_tgt_private = NULL;
1989 1991
1990 1992 hba_tran->tran_tgt_init = mptsas_scsi_tgt_init;
1991 1993 hba_tran->tran_tgt_free = mptsas_scsi_tgt_free;
1992 1994
1993 1995 hba_tran->tran_start = mptsas_scsi_start;
1994 1996 hba_tran->tran_reset = mptsas_scsi_reset;
1995 1997 hba_tran->tran_abort = mptsas_scsi_abort;
1996 1998 hba_tran->tran_getcap = mptsas_scsi_getcap;
1997 1999 hba_tran->tran_setcap = mptsas_scsi_setcap;
1998 2000 hba_tran->tran_init_pkt = mptsas_scsi_init_pkt;
1999 2001 hba_tran->tran_destroy_pkt = mptsas_scsi_destroy_pkt;
2000 2002
2001 2003 hba_tran->tran_dmafree = mptsas_scsi_dmafree;
2002 2004 hba_tran->tran_sync_pkt = mptsas_scsi_sync_pkt;
2003 2005 hba_tran->tran_reset_notify = mptsas_scsi_reset_notify;
2004 2006
2005 2007 hba_tran->tran_get_bus_addr = mptsas_get_bus_addr;
2006 2008 hba_tran->tran_get_name = mptsas_get_name;
2007 2009
2008 2010 hba_tran->tran_quiesce = mptsas_scsi_quiesce;
2009 2011 hba_tran->tran_unquiesce = mptsas_scsi_unquiesce;
2010 2012 hba_tran->tran_bus_reset = NULL;
2011 2013
2012 2014 hba_tran->tran_add_eventcall = NULL;
2013 2015 hba_tran->tran_get_eventcookie = NULL;
2014 2016 hba_tran->tran_post_event = NULL;
2015 2017 hba_tran->tran_remove_eventcall = NULL;
2016 2018
2017 2019 hba_tran->tran_bus_config = mptsas_bus_config;
2018 2020
2019 2021 hba_tran->tran_interconnect_type = INTERCONNECT_SAS;
2020 2022
2021 2023 /*
2022 2024 * All children of the HBA are iports. We need tran was cloned.
2023 2025 * So we pass the flags to SCSA. SCSI_HBA_TRAN_CLONE will be
2024 2026 * inherited to iport's tran vector.
2025 2027 */
2026 2028 tran_flags = (SCSI_HBA_HBA | SCSI_HBA_TRAN_CLONE);
2027 2029
2028 2030 if (scsi_hba_attach_setup(mpt->m_dip, &mpt->m_msg_dma_attr,
2029 2031 hba_tran, tran_flags) != DDI_SUCCESS) {
2030 2032 mptsas_log(mpt, CE_WARN, "hba attach setup failed");
2031 2033 scsi_hba_tran_free(hba_tran);
2032 2034 mpt->m_tran = NULL;
2033 2035 return (FALSE);
2034 2036 }
2035 2037 return (TRUE);
2036 2038 }
2037 2039
2038 2040 static void
2039 2041 mptsas_hba_teardown(mptsas_t *mpt)
2040 2042 {
2041 2043 (void) scsi_hba_detach(mpt->m_dip);
2042 2044 if (mpt->m_tran != NULL) {
2043 2045 scsi_hba_tran_free(mpt->m_tran);
2044 2046 mpt->m_tran = NULL;
2045 2047 }
2046 2048 }
2047 2049
2048 2050 static void
2049 2051 mptsas_iport_register(mptsas_t *mpt)
2050 2052 {
2051 2053 int i, j;
2052 2054 mptsas_phymask_t mask = 0x0;
2053 2055 /*
2054 2056 * initial value of mask is 0
2055 2057 */
2056 2058 mutex_enter(&mpt->m_mutex);
2057 2059 for (i = 0; i < mpt->m_num_phys; i++) {
2058 2060 mptsas_phymask_t phy_mask = 0x0;
2059 2061 char phy_mask_name[MPTSAS_MAX_PHYS];
2060 2062 uint8_t current_port;
2061 2063
2062 2064 if (mpt->m_phy_info[i].attached_devhdl == 0)
2063 2065 continue;
2064 2066
2065 2067 bzero(phy_mask_name, sizeof (phy_mask_name));
2066 2068
2067 2069 current_port = mpt->m_phy_info[i].port_num;
2068 2070
2069 2071 if ((mask & (1 << i)) != 0)
2070 2072 continue;
2071 2073
2072 2074 for (j = 0; j < mpt->m_num_phys; j++) {
2073 2075 if (mpt->m_phy_info[j].attached_devhdl &&
2074 2076 (mpt->m_phy_info[j].port_num == current_port)) {
2075 2077 phy_mask |= (1 << j);
2076 2078 }
2077 2079 }
2078 2080 mask = mask | phy_mask;
2079 2081
2080 2082 for (j = 0; j < mpt->m_num_phys; j++) {
2081 2083 if ((phy_mask >> j) & 0x01) {
2082 2084 mpt->m_phy_info[j].phy_mask = phy_mask;
2083 2085 }
2084 2086 }
2085 2087
2086 2088 (void) sprintf(phy_mask_name, "%x", phy_mask);
2087 2089
2088 2090 mutex_exit(&mpt->m_mutex);
2089 2091 /*
2090 2092 * register a iport
2091 2093 */
2092 2094 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name);
2093 2095 mutex_enter(&mpt->m_mutex);
2094 2096 }
2095 2097 mutex_exit(&mpt->m_mutex);
2096 2098 /*
2097 2099 * register a virtual port for RAID volume always
2098 2100 */
2099 2101 (void) scsi_hba_iport_register(mpt->m_dip, "v0");
2100 2102
2101 2103 }
2102 2104
2103 2105 static int
2104 2106 mptsas_smp_setup(mptsas_t *mpt)
2105 2107 {
2106 2108 mpt->m_smptran = smp_hba_tran_alloc(mpt->m_dip);
2107 2109 ASSERT(mpt->m_smptran != NULL);
2108 2110 mpt->m_smptran->smp_tran_hba_private = mpt;
2109 2111 mpt->m_smptran->smp_tran_start = mptsas_smp_start;
2110 2112 if (smp_hba_attach_setup(mpt->m_dip, mpt->m_smptran) != DDI_SUCCESS) {
2111 2113 mptsas_log(mpt, CE_WARN, "smp attach setup failed");
2112 2114 smp_hba_tran_free(mpt->m_smptran);
2113 2115 mpt->m_smptran = NULL;
2114 2116 return (FALSE);
2115 2117 }
2116 2118 /*
2117 2119 * Initialize smp hash table
2118 2120 */
2119 2121 mptsas_hash_init(&mpt->m_active->m_smptbl);
2120 2122 mpt->m_smp_devhdl = 0xFFFF;
2121 2123
2122 2124 return (TRUE);
2123 2125 }
2124 2126
2125 2127 static void
2126 2128 mptsas_smp_teardown(mptsas_t *mpt)
2127 2129 {
2128 2130 (void) smp_hba_detach(mpt->m_dip);
2129 2131 if (mpt->m_smptran != NULL) {
2130 2132 smp_hba_tran_free(mpt->m_smptran);
2131 2133 mpt->m_smptran = NULL;
2132 2134 }
2133 2135 mpt->m_smp_devhdl = 0;
2134 2136 }
2135 2137
2136 2138 static int
2137 2139 mptsas_cache_create(mptsas_t *mpt)
2138 2140 {
2139 2141 int instance = mpt->m_instance;
2140 2142 char buf[64];
2141 2143
2142 2144 /*
2143 2145 * create kmem cache for packets
2144 2146 */
2145 2147 (void) sprintf(buf, "mptsas%d_cache", instance);
2146 2148 mpt->m_kmem_cache = kmem_cache_create(buf,
2147 2149 sizeof (struct mptsas_cmd) + scsi_pkt_size(), 8,
2148 2150 mptsas_kmem_cache_constructor, mptsas_kmem_cache_destructor,
2149 2151 NULL, (void *)mpt, NULL, 0);
2150 2152
2151 2153 if (mpt->m_kmem_cache == NULL) {
2152 2154 mptsas_log(mpt, CE_WARN, "creating kmem cache failed");
2153 2155 return (FALSE);
2154 2156 }
2155 2157
2156 2158 /*
2157 2159 * create kmem cache for extra SGL frames if SGL cannot
2158 2160 * be accomodated into main request frame.
2159 2161 */
2160 2162 (void) sprintf(buf, "mptsas%d_cache_frames", instance);
2161 2163 mpt->m_cache_frames = kmem_cache_create(buf,
2162 2164 sizeof (mptsas_cache_frames_t), 8,
2163 2165 mptsas_cache_frames_constructor, mptsas_cache_frames_destructor,
2164 2166 NULL, (void *)mpt, NULL, 0);
2165 2167
2166 2168 if (mpt->m_cache_frames == NULL) {
2167 2169 mptsas_log(mpt, CE_WARN, "creating cache for frames failed");
2168 2170 return (FALSE);
2169 2171 }
2170 2172
2171 2173 return (TRUE);
2172 2174 }
2173 2175
2174 2176 static void
2175 2177 mptsas_cache_destroy(mptsas_t *mpt)
2176 2178 {
2177 2179 /* deallocate in reverse order */
2178 2180 if (mpt->m_cache_frames) {
2179 2181 kmem_cache_destroy(mpt->m_cache_frames);
2180 2182 mpt->m_cache_frames = NULL;
2181 2183 }
2182 2184 if (mpt->m_kmem_cache) {
2183 2185 kmem_cache_destroy(mpt->m_kmem_cache);
2184 2186 mpt->m_kmem_cache = NULL;
2185 2187 }
2186 2188 }
2187 2189
2188 2190 static int
2189 2191 mptsas_power(dev_info_t *dip, int component, int level)
2190 2192 {
2191 2193 #ifndef __lock_lint
2192 2194 _NOTE(ARGUNUSED(component))
2193 2195 #endif
2194 2196 mptsas_t *mpt;
2195 2197 int rval = DDI_SUCCESS;
2196 2198 int polls = 0;
2197 2199 uint32_t ioc_status;
2198 2200
2199 2201 if (scsi_hba_iport_unit_address(dip) != 0)
2200 2202 return (DDI_SUCCESS);
2201 2203
2202 2204 mpt = ddi_get_soft_state(mptsas_state, ddi_get_instance(dip));
2203 2205 if (mpt == NULL) {
2204 2206 return (DDI_FAILURE);
2205 2207 }
2206 2208
2207 2209 mutex_enter(&mpt->m_mutex);
2208 2210
2209 2211 /*
2210 2212 * If the device is busy, don't lower its power level
2211 2213 */
2212 2214 if (mpt->m_busy && (mpt->m_power_level > level)) {
2213 2215 mutex_exit(&mpt->m_mutex);
2214 2216 return (DDI_FAILURE);
2215 2217 }
2216 2218 switch (level) {
2217 2219 case PM_LEVEL_D0:
2218 2220 NDBG11(("mptsas%d: turning power ON.", mpt->m_instance));
2219 2221 MPTSAS_POWER_ON(mpt);
2220 2222 /*
2221 2223 * Wait up to 30 seconds for IOC to come out of reset.
2222 2224 */
2223 2225 while (((ioc_status = ddi_get32(mpt->m_datap,
2224 2226 &mpt->m_reg->Doorbell)) &
2225 2227 MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
2226 2228 if (polls++ > 3000) {
2227 2229 break;
2228 2230 }
2229 2231 delay(drv_usectohz(10000));
2230 2232 }
2231 2233 /*
2232 2234 * If IOC is not in operational state, try to hard reset it.
2233 2235 */
2234 2236 if ((ioc_status & MPI2_IOC_STATE_MASK) !=
2235 2237 MPI2_IOC_STATE_OPERATIONAL) {
2236 2238 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
2237 2239 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) {
2238 2240 mptsas_log(mpt, CE_WARN,
2239 2241 "mptsas_power: hard reset failed");
2240 2242 mutex_exit(&mpt->m_mutex);
2241 2243 return (DDI_FAILURE);
2242 2244 }
2243 2245 }
2244 2246 mutex_enter(&mpt->m_intr_mutex);
2245 2247 mpt->m_power_level = PM_LEVEL_D0;
2246 2248 mutex_exit(&mpt->m_intr_mutex);
2247 2249 break;
2248 2250 case PM_LEVEL_D3:
2249 2251 NDBG11(("mptsas%d: turning power OFF.", mpt->m_instance));
2250 2252 MPTSAS_POWER_OFF(mpt);
2251 2253 break;
2252 2254 default:
2253 2255 mptsas_log(mpt, CE_WARN, "mptsas%d: unknown power level <%x>.",
2254 2256 mpt->m_instance, level);
2255 2257 rval = DDI_FAILURE;
2256 2258 break;
2257 2259 }
2258 2260 mutex_exit(&mpt->m_mutex);
2259 2261 return (rval);
2260 2262 }
2261 2263
2262 2264 /*
2263 2265 * Initialize configuration space and figure out which
2264 2266 * chip and revison of the chip the mpt driver is using.
2265 2267 */
2266 2268 static int
2267 2269 mptsas_config_space_init(mptsas_t *mpt)
2268 2270 {
2269 2271 NDBG0(("mptsas_config_space_init"));
2270 2272
2271 2273 if (mpt->m_config_handle != NULL)
2272 2274 return (TRUE);
2273 2275
2274 2276 if (pci_config_setup(mpt->m_dip,
2275 2277 &mpt->m_config_handle) != DDI_SUCCESS) {
2276 2278 mptsas_log(mpt, CE_WARN, "cannot map configuration space.");
2277 2279 return (FALSE);
2278 2280 }
2279 2281
2280 2282 /*
2281 2283 * This is a workaround for a XMITS ASIC bug which does not
2282 2284 * drive the CBE upper bits.
2283 2285 */
2284 2286 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) &
2285 2287 PCI_STAT_PERROR) {
2286 2288 pci_config_put16(mpt->m_config_handle, PCI_CONF_STAT,
2287 2289 PCI_STAT_PERROR);
2288 2290 }
2289 2291
2290 2292 mptsas_setup_cmd_reg(mpt);
2291 2293
2292 2294 /*
2293 2295 * Get the chip device id:
2294 2296 */
2295 2297 mpt->m_devid = pci_config_get16(mpt->m_config_handle, PCI_CONF_DEVID);
2296 2298
2297 2299 /*
2298 2300 * Save the revision.
2299 2301 */
2300 2302 mpt->m_revid = pci_config_get8(mpt->m_config_handle, PCI_CONF_REVID);
2301 2303
2302 2304 /*
2303 2305 * Save the SubSystem Vendor and Device IDs
2304 2306 */
2305 2307 mpt->m_svid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBVENID);
2306 2308 mpt->m_ssid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBSYSID);
2307 2309
2308 2310 /*
2309 2311 * Set the latency timer to 0x40 as specified by the upa -> pci
2310 2312 * bridge chip design team. This may be done by the sparc pci
2311 2313 * bus nexus driver, but the driver should make sure the latency
2312 2314 * timer is correct for performance reasons.
2313 2315 */
2314 2316 pci_config_put8(mpt->m_config_handle, PCI_CONF_LATENCY_TIMER,
2315 2317 MPTSAS_LATENCY_TIMER);
2316 2318
2317 2319 (void) mptsas_get_pci_cap(mpt);
2318 2320 return (TRUE);
2319 2321 }
2320 2322
2321 2323 static void
2322 2324 mptsas_config_space_fini(mptsas_t *mpt)
2323 2325 {
2324 2326 if (mpt->m_config_handle != NULL) {
2325 2327 mptsas_disable_bus_master(mpt);
2326 2328 pci_config_teardown(&mpt->m_config_handle);
2327 2329 mpt->m_config_handle = NULL;
2328 2330 }
2329 2331 }
2330 2332
2331 2333 static void
2332 2334 mptsas_setup_cmd_reg(mptsas_t *mpt)
2333 2335 {
2334 2336 ushort_t cmdreg;
2335 2337
2336 2338 /*
2337 2339 * Set the command register to the needed values.
2338 2340 */
2339 2341 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM);
2340 2342 cmdreg |= (PCI_COMM_ME | PCI_COMM_SERR_ENABLE |
2341 2343 PCI_COMM_PARITY_DETECT | PCI_COMM_MAE);
2342 2344 cmdreg &= ~PCI_COMM_IO;
2343 2345 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg);
2344 2346 }
2345 2347
2346 2348 static void
2347 2349 mptsas_disable_bus_master(mptsas_t *mpt)
2348 2350 {
2349 2351 ushort_t cmdreg;
2350 2352
2351 2353 /*
2352 2354 * Clear the master enable bit in the PCI command register.
2353 2355 * This prevents any bus mastering activity like DMA.
2354 2356 */
2355 2357 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM);
2356 2358 cmdreg &= ~PCI_COMM_ME;
2357 2359 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg);
2358 2360 }
2359 2361
2360 2362 int
2361 2363 mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep)
2362 2364 {
2363 2365 ddi_dma_attr_t attrs;
2364 2366
2365 2367 attrs = mpt->m_io_dma_attr;
2366 2368 attrs.dma_attr_sgllen = 1;
2367 2369
2368 2370 ASSERT(dma_statep != NULL);
2369 2371
2370 2372 if (mptsas_dma_addr_create(mpt, attrs, &dma_statep->handle,
2371 2373 &dma_statep->accessp, &dma_statep->memp, dma_statep->size,
2372 2374 &dma_statep->cookie) == FALSE) {
2373 2375 return (DDI_FAILURE);
2374 2376 }
2375 2377
2376 2378 return (DDI_SUCCESS);
2377 2379 }
2378 2380
2379 2381 void
2380 2382 mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep)
2381 2383 {
2382 2384 ASSERT(dma_statep != NULL);
2383 2385 mptsas_dma_addr_destroy(&dma_statep->handle, &dma_statep->accessp);
2384 2386 dma_statep->size = 0;
2385 2387 }
2386 2388
2387 2389 int
2388 2390 mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)())
2389 2391 {
2390 2392 ddi_dma_attr_t attrs;
2391 2393 ddi_dma_handle_t dma_handle;
2392 2394 caddr_t memp;
2393 2395 ddi_acc_handle_t accessp;
2394 2396 int rval;
2395 2397
2396 2398 ASSERT(mutex_owned(&mpt->m_mutex));
2397 2399
2398 2400 attrs = mpt->m_msg_dma_attr;
2399 2401 attrs.dma_attr_sgllen = 1;
2400 2402 attrs.dma_attr_granular = size;
2401 2403
2402 2404 if (mptsas_dma_addr_create(mpt, attrs, &dma_handle,
2403 2405 &accessp, &memp, size, NULL) == FALSE) {
2404 2406 return (DDI_FAILURE);
2405 2407 }
2406 2408
2407 2409 rval = (*callback) (mpt, memp, var, accessp);
2408 2410
2409 2411 if ((mptsas_check_dma_handle(dma_handle) != DDI_SUCCESS) ||
2410 2412 (mptsas_check_acc_handle(accessp) != DDI_SUCCESS)) {
2411 2413 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
2412 2414 rval = DDI_FAILURE;
2413 2415 }
2414 2416
2415 2417 mptsas_dma_addr_destroy(&dma_handle, &accessp);
2416 2418 return (rval);
2417 2419
2418 2420 }
2419 2421
2420 2422 static int
2421 2423 mptsas_alloc_request_frames(mptsas_t *mpt)
2422 2424 {
2423 2425 ddi_dma_attr_t frame_dma_attrs;
2424 2426 caddr_t memp;
2425 2427 ddi_dma_cookie_t cookie;
2426 2428 size_t mem_size;
2427 2429
2428 2430 /*
2429 2431 * re-alloc when it has already alloced
2430 2432 */
2431 2433 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl,
2432 2434 &mpt->m_acc_req_frame_hdl);
2433 2435
2434 2436 /*
2435 2437 * The size of the request frame pool is:
2436 2438 * Number of Request Frames * Request Frame Size
2437 2439 */
2438 2440 mem_size = mpt->m_max_requests * mpt->m_req_frame_size;
2439 2441
2440 2442 /*
2441 2443 * set the DMA attributes. System Request Message Frames must be
2442 2444 * aligned on a 16-byte boundry.
2443 2445 */
2444 2446 frame_dma_attrs = mpt->m_msg_dma_attr;
2445 2447 frame_dma_attrs.dma_attr_align = 16;
2446 2448 frame_dma_attrs.dma_attr_sgllen = 1;
2447 2449
2448 2450 /*
2449 2451 * allocate the request frame pool.
2450 2452 */
2451 2453 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2452 2454 &mpt->m_dma_req_frame_hdl, &mpt->m_acc_req_frame_hdl, &memp,
2453 2455 mem_size, &cookie) == FALSE) {
2454 2456 return (DDI_FAILURE);
2455 2457 }
2456 2458
2457 2459 /*
2458 2460 * Store the request frame memory address. This chip uses this
2459 2461 * address to dma to and from the driver's frame. The second
2460 2462 * address is the address mpt uses to fill in the frame.
2461 2463 */
2462 2464 mpt->m_req_frame_dma_addr = cookie.dmac_laddress;
2463 2465 mpt->m_req_frame = memp;
2464 2466
2465 2467 /*
2466 2468 * Clear the request frame pool.
2467 2469 */
2468 2470 bzero(mpt->m_req_frame, mem_size);
2469 2471
2470 2472 return (DDI_SUCCESS);
2471 2473 }
2472 2474
2473 2475 static int
2474 2476 mptsas_alloc_reply_frames(mptsas_t *mpt)
2475 2477 {
2476 2478 ddi_dma_attr_t frame_dma_attrs;
2477 2479 caddr_t memp;
2478 2480 ddi_dma_cookie_t cookie;
2479 2481 size_t mem_size;
2480 2482
2481 2483 /*
2482 2484 * re-alloc when it has already alloced
2483 2485 */
2484 2486 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl,
2485 2487 &mpt->m_acc_reply_frame_hdl);
2486 2488
2487 2489 /*
2488 2490 * The size of the reply frame pool is:
2489 2491 * Number of Reply Frames * Reply Frame Size
2490 2492 */
2491 2493 mem_size = mpt->m_max_replies * mpt->m_reply_frame_size;
2492 2494
2493 2495 /*
2494 2496 * set the DMA attributes. System Reply Message Frames must be
2495 2497 * aligned on a 4-byte boundry. This is the default.
2496 2498 */
2497 2499 frame_dma_attrs = mpt->m_msg_dma_attr;
2498 2500 frame_dma_attrs.dma_attr_sgllen = 1;
2499 2501
2500 2502 /*
2501 2503 * allocate the reply frame pool
2502 2504 */
2503 2505 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2504 2506 &mpt->m_dma_reply_frame_hdl, &mpt->m_acc_reply_frame_hdl, &memp,
2505 2507 mem_size, &cookie) == FALSE) {
2506 2508 return (DDI_FAILURE);
2507 2509 }
2508 2510
2509 2511 /*
2510 2512 * Store the reply frame memory address. This chip uses this
2511 2513 * address to dma to and from the driver's frame. The second
2512 2514 * address is the address mpt uses to process the frame.
2513 2515 */
2514 2516 mpt->m_reply_frame_dma_addr = cookie.dmac_laddress;
2515 2517 mpt->m_reply_frame = memp;
2516 2518
2517 2519 /*
2518 2520 * Clear the reply frame pool.
2519 2521 */
2520 2522 bzero(mpt->m_reply_frame, mem_size);
2521 2523
2522 2524 return (DDI_SUCCESS);
2523 2525 }
2524 2526
2525 2527 static int
2526 2528 mptsas_alloc_free_queue(mptsas_t *mpt)
2527 2529 {
2528 2530 ddi_dma_attr_t frame_dma_attrs;
2529 2531 caddr_t memp;
2530 2532 ddi_dma_cookie_t cookie;
2531 2533 size_t mem_size;
2532 2534
2533 2535 /*
2534 2536 * re-alloc when it has already alloced
2535 2537 */
2536 2538 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl,
2537 2539 &mpt->m_acc_free_queue_hdl);
2538 2540
2539 2541 /*
2540 2542 * The reply free queue size is:
2541 2543 * Reply Free Queue Depth * 4
2542 2544 * The "4" is the size of one 32 bit address (low part of 64-bit
2543 2545 * address)
2544 2546 */
2545 2547 mem_size = mpt->m_free_queue_depth * 4;
2546 2548
2547 2549 /*
2548 2550 * set the DMA attributes The Reply Free Queue must be aligned on a
2549 2551 * 16-byte boundry.
2550 2552 */
2551 2553 frame_dma_attrs = mpt->m_msg_dma_attr;
2552 2554 frame_dma_attrs.dma_attr_align = 16;
2553 2555 frame_dma_attrs.dma_attr_sgllen = 1;
2554 2556
2555 2557 /*
2556 2558 * allocate the reply free queue
2557 2559 */
2558 2560 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2559 2561 &mpt->m_dma_free_queue_hdl, &mpt->m_acc_free_queue_hdl, &memp,
2560 2562 mem_size, &cookie) == FALSE) {
2561 2563 return (DDI_FAILURE);
2562 2564 }
2563 2565
2564 2566 /*
2565 2567 * Store the reply free queue memory address. This chip uses this
2566 2568 * address to read from the reply free queue. The second address
2567 2569 * is the address mpt uses to manage the queue.
2568 2570 */
2569 2571 mpt->m_free_queue_dma_addr = cookie.dmac_laddress;
2570 2572 mpt->m_free_queue = memp;
2571 2573
2572 2574 /*
2573 2575 * Clear the reply free queue memory.
2574 2576 */
2575 2577 bzero(mpt->m_free_queue, mem_size);
2576 2578
2577 2579 return (DDI_SUCCESS);
2578 2580 }
2579 2581
2580 2582 static int
2581 2583 mptsas_alloc_post_queue(mptsas_t *mpt)
2582 2584 {
2583 2585 ddi_dma_attr_t frame_dma_attrs;
2584 2586 caddr_t memp;
2585 2587 ddi_dma_cookie_t cookie;
2586 2588 size_t mem_size;
2587 2589
2588 2590 /*
2589 2591 * re-alloc when it has already alloced
2590 2592 */
2591 2593 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl,
2592 2594 &mpt->m_acc_post_queue_hdl);
2593 2595
2594 2596 /*
2595 2597 * The reply descriptor post queue size is:
2596 2598 * Reply Descriptor Post Queue Depth * 8
2597 2599 * The "8" is the size of each descriptor (8 bytes or 64 bits).
2598 2600 */
2599 2601 mem_size = mpt->m_post_queue_depth * 8;
2600 2602
2601 2603 /*
2602 2604 * set the DMA attributes. The Reply Descriptor Post Queue must be
2603 2605 * aligned on a 16-byte boundry.
2604 2606 */
2605 2607 frame_dma_attrs = mpt->m_msg_dma_attr;
2606 2608 frame_dma_attrs.dma_attr_align = 16;
2607 2609 frame_dma_attrs.dma_attr_sgllen = 1;
2608 2610
2609 2611 /*
2610 2612 * allocate the reply post queue
2611 2613 */
2612 2614 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2613 2615 &mpt->m_dma_post_queue_hdl, &mpt->m_acc_post_queue_hdl, &memp,
2614 2616 mem_size, &cookie) == FALSE) {
2615 2617 return (DDI_FAILURE);
2616 2618 }
2617 2619
2618 2620 /*
2619 2621 * Store the reply descriptor post queue memory address. This chip
2620 2622 * uses this address to write to the reply descriptor post queue. The
2621 2623 * second address is the address mpt uses to manage the queue.
2622 2624 */
2623 2625 mpt->m_post_queue_dma_addr = cookie.dmac_laddress;
2624 2626 mpt->m_post_queue = memp;
2625 2627
2626 2628 /*
2627 2629 * Clear the reply post queue memory.
2628 2630 */
2629 2631 bzero(mpt->m_post_queue, mem_size);
2630 2632
2631 2633 return (DDI_SUCCESS);
2632 2634 }
2633 2635
2634 2636 static void
2635 2637 mptsas_alloc_reply_args(mptsas_t *mpt)
2636 2638 {
2637 2639 if (mpt->m_replyh_args != NULL) {
2638 2640 kmem_free(mpt->m_replyh_args, sizeof (m_replyh_arg_t)
2639 2641 * mpt->m_max_replies);
2640 2642 mpt->m_replyh_args = NULL;
2641 2643 }
2642 2644 mpt->m_replyh_args = kmem_zalloc(sizeof (m_replyh_arg_t) *
2643 2645 mpt->m_max_replies, KM_SLEEP);
2644 2646 }
2645 2647
2646 2648 static int
2647 2649 mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd)
2648 2650 {
2649 2651 mptsas_cache_frames_t *frames = NULL;
2650 2652 if (cmd->cmd_extra_frames == NULL) {
2651 2653 frames = kmem_cache_alloc(mpt->m_cache_frames, KM_NOSLEEP);
2652 2654 if (frames == NULL) {
2653 2655 return (DDI_FAILURE);
2654 2656 }
2655 2657 cmd->cmd_extra_frames = frames;
2656 2658 }
2657 2659 return (DDI_SUCCESS);
2658 2660 }
2659 2661
2660 2662 static void
2661 2663 mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd)
2662 2664 {
2663 2665 if (cmd->cmd_extra_frames) {
2664 2666 kmem_cache_free(mpt->m_cache_frames,
2665 2667 (void *)cmd->cmd_extra_frames);
2666 2668 cmd->cmd_extra_frames = NULL;
2667 2669 }
2668 2670 }
2669 2671
2670 2672 static void
2671 2673 mptsas_cfg_fini(mptsas_t *mpt)
2672 2674 {
2673 2675 NDBG0(("mptsas_cfg_fini"));
2674 2676 ddi_regs_map_free(&mpt->m_datap);
2675 2677 }
2676 2678
2677 2679 static void
2678 2680 mptsas_hba_fini(mptsas_t *mpt)
2679 2681 {
2680 2682 NDBG0(("mptsas_hba_fini"));
2681 2683
2682 2684 /*
2683 2685 * Free up any allocated memory
2684 2686 */
2685 2687 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl,
2686 2688 &mpt->m_acc_req_frame_hdl);
2687 2689
2688 2690 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl,
2689 2691 &mpt->m_acc_reply_frame_hdl);
2690 2692
2691 2693 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl,
2692 2694 &mpt->m_acc_free_queue_hdl);
2693 2695
2694 2696 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl,
2695 2697 &mpt->m_acc_post_queue_hdl);
2696 2698
2697 2699 if (mpt->m_replyh_args != NULL) {
2698 2700 kmem_free(mpt->m_replyh_args, sizeof (m_replyh_arg_t)
2699 2701 * mpt->m_max_replies);
2700 2702 }
2701 2703 }
2702 2704
2703 2705 static int
2704 2706 mptsas_name_child(dev_info_t *lun_dip, char *name, int len)
2705 2707 {
2706 2708 int lun = 0;
2707 2709 char *sas_wwn = NULL;
2708 2710 int phynum = -1;
2709 2711 int reallen = 0;
2710 2712
2711 2713 /* Get the target num */
2712 2714 lun = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, DDI_PROP_DONTPASS,
2713 2715 LUN_PROP, 0);
2714 2716
2715 2717 if ((phynum = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip,
2716 2718 DDI_PROP_DONTPASS, "sata-phy", -1)) != -1) {
2717 2719 /*
2718 2720 * Stick in the address of form "pPHY,LUN"
2719 2721 */
2720 2722 reallen = snprintf(name, len, "p%x,%x", phynum, lun);
2721 2723 } else if (ddi_prop_lookup_string(DDI_DEV_T_ANY, lun_dip,
2722 2724 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &sas_wwn)
2723 2725 == DDI_PROP_SUCCESS) {
2724 2726 /*
2725 2727 * Stick in the address of the form "wWWN,LUN"
2726 2728 */
2727 2729 reallen = snprintf(name, len, "%s,%x", sas_wwn, lun);
2728 2730 ddi_prop_free(sas_wwn);
2729 2731 } else {
2730 2732 return (DDI_FAILURE);
2731 2733 }
2732 2734
2733 2735 ASSERT(reallen < len);
2734 2736 if (reallen >= len) {
2735 2737 mptsas_log(0, CE_WARN, "!mptsas_get_name: name parameter "
2736 2738 "length too small, it needs to be %d bytes", reallen + 1);
2737 2739 }
2738 2740 return (DDI_SUCCESS);
2739 2741 }
2740 2742
2741 2743 /*
2742 2744 * tran_tgt_init(9E) - target device instance initialization
2743 2745 */
2744 2746 static int
2745 2747 mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
2746 2748 scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
2747 2749 {
2748 2750 #ifndef __lock_lint
2749 2751 _NOTE(ARGUNUSED(hba_tran))
2750 2752 #endif
2751 2753
2752 2754 /*
2753 2755 * At this point, the scsi_device structure already exists
2754 2756 * and has been initialized.
2755 2757 *
2756 2758 * Use this function to allocate target-private data structures,
2757 2759 * if needed by this HBA. Add revised flow-control and queue
2758 2760 * properties for child here, if desired and if you can tell they
2759 2761 * support tagged queueing by now.
2760 2762 */
2761 2763 mptsas_t *mpt;
2762 2764 int lun = sd->sd_address.a_lun;
2763 2765 mdi_pathinfo_t *pip = NULL;
2764 2766 mptsas_tgt_private_t *tgt_private = NULL;
2765 2767 mptsas_target_t *ptgt = NULL;
2766 2768 char *psas_wwn = NULL;
2767 2769 int phymask = 0;
2768 2770 uint64_t sas_wwn = 0;
2769 2771 mpt = SDEV2MPT(sd);
2770 2772
2771 2773 ASSERT(scsi_hba_iport_unit_address(hba_dip) != 0);
2772 2774
2773 2775 NDBG0(("mptsas_scsi_tgt_init: hbadip=0x%p tgtdip=0x%p lun=%d",
2774 2776 (void *)hba_dip, (void *)tgt_dip, lun));
2775 2777
2776 2778 if (ndi_dev_is_persistent_node(tgt_dip) == 0) {
2777 2779 (void) ndi_merge_node(tgt_dip, mptsas_name_child);
2778 2780 ddi_set_name_addr(tgt_dip, NULL);
2779 2781 return (DDI_FAILURE);
2780 2782 }
2781 2783 /*
2782 2784 * phymask is 0 means the virtual port for RAID
2783 2785 */
2784 2786 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, hba_dip, 0,
2785 2787 "phymask", 0);
2786 2788 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) {
2787 2789 if ((pip = (void *)(sd->sd_private)) == NULL) {
2788 2790 /*
2789 2791 * Very bad news if this occurs. Somehow scsi_vhci has
2790 2792 * lost the pathinfo node for this target.
2791 2793 */
2792 2794 return (DDI_NOT_WELL_FORMED);
2793 2795 }
2794 2796
2795 2797 if (mdi_prop_lookup_int(pip, LUN_PROP, &lun) !=
2796 2798 DDI_PROP_SUCCESS) {
2797 2799 mptsas_log(mpt, CE_WARN, "Get lun property failed\n");
2798 2800 return (DDI_FAILURE);
2799 2801 }
2800 2802
2801 2803 if (mdi_prop_lookup_string(pip, SCSI_ADDR_PROP_TARGET_PORT,
2802 2804 &psas_wwn) == MDI_SUCCESS) {
2803 2805 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) {
2804 2806 sas_wwn = 0;
2805 2807 }
2806 2808 (void) mdi_prop_free(psas_wwn);
2807 2809 }
2808 2810 } else {
2809 2811 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tgt_dip,
2810 2812 DDI_PROP_DONTPASS, LUN_PROP, 0);
2811 2813 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, tgt_dip,
2812 2814 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &psas_wwn) ==
2813 2815 DDI_PROP_SUCCESS) {
2814 2816 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) {
2815 2817 sas_wwn = 0;
2816 2818 }
2817 2819 ddi_prop_free(psas_wwn);
2818 2820 } else {
2819 2821 sas_wwn = 0;
2820 2822 }
2821 2823 }
2822 2824 ASSERT((sas_wwn != 0) || (phymask != 0));
2823 2825 mutex_enter(&mpt->m_mutex);
2824 2826 ptgt = mptsas_hash_search(&mpt->m_active->m_tgttbl, sas_wwn, phymask);
2825 2827 mutex_exit(&mpt->m_mutex);
2826 2828 if (ptgt == NULL) {
2827 2829 mptsas_log(mpt, CE_WARN, "!tgt_init: target doesn't exist or "
2828 2830 "gone already! phymask:%x, saswwn %"PRIx64, phymask,
2829 2831 sas_wwn);
2830 2832 return (DDI_FAILURE);
2831 2833 }
2832 2834 if (hba_tran->tran_tgt_private == NULL) {
2833 2835 tgt_private = kmem_zalloc(sizeof (mptsas_tgt_private_t),
2834 2836 KM_SLEEP);
2835 2837 tgt_private->t_lun = lun;
2836 2838 tgt_private->t_private = ptgt;
2837 2839 hba_tran->tran_tgt_private = tgt_private;
2838 2840 }
2839 2841
2840 2842 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) {
2841 2843 return (DDI_SUCCESS);
2842 2844 }
2843 2845 mutex_enter(&mpt->m_mutex);
2844 2846
2845 2847 if (ptgt->m_deviceinfo &
2846 2848 (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
2847 2849 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
2848 2850 uchar_t *inq89 = NULL;
2849 2851 int inq89_len = 0x238;
2850 2852 int reallen = 0;
2851 2853 int rval = 0;
2852 2854 struct sata_id *sid = NULL;
2853 2855 char model[SATA_ID_MODEL_LEN + 1];
2854 2856 char fw[SATA_ID_FW_LEN + 1];
2855 2857 char *vid, *pid;
2856 2858 int i;
2857 2859
2858 2860 mutex_exit(&mpt->m_mutex);
2859 2861 /*
2860 2862 * According SCSI/ATA Translation -2 (SAT-2) revision 01a
2861 2863 * chapter 12.4.2 VPD page 89h includes 512 bytes ATA IDENTIFY
2862 2864 * DEVICE data or ATA IDENTIFY PACKET DEVICE data.
2863 2865 */
2864 2866 inq89 = kmem_zalloc(inq89_len, KM_SLEEP);
2865 2867 rval = mptsas_inquiry(mpt, ptgt, 0, 0x89,
2866 2868 inq89, inq89_len, &reallen, 1);
2867 2869
2868 2870 if (rval != 0) {
2869 2871 if (inq89 != NULL) {
2870 2872 kmem_free(inq89, inq89_len);
2871 2873 }
2872 2874
2873 2875 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
2874 2876 "0x89 for SATA target:%x failed!", ptgt->m_devhdl);
2875 2877 return (DDI_SUCCESS);
2876 2878 }
2877 2879 sid = (void *)(&inq89[60]);
2878 2880
2879 2881 swab(sid->ai_model, model, SATA_ID_MODEL_LEN);
2880 2882 swab(sid->ai_fw, fw, SATA_ID_FW_LEN);
2881 2883
2882 2884 model[SATA_ID_MODEL_LEN] = 0;
2883 2885 fw[SATA_ID_FW_LEN] = 0;
2884 2886
2885 2887 /*
2886 2888 * split model into into vid/pid
2887 2889 */
2888 2890 for (i = 0, pid = model; i < SATA_ID_MODEL_LEN; i++, pid++)
2889 2891 if ((*pid == ' ') || (*pid == '\t'))
2890 2892 break;
2891 2893 if (i < SATA_ID_MODEL_LEN) {
2892 2894 vid = model;
2893 2895 /*
2894 2896 * terminate vid, establish pid
2895 2897 */
2896 2898 *pid++ = 0;
2897 2899 } else {
2898 2900 /*
2899 2901 * vid will stay "ATA ", the rule is same
2900 2902 * as sata framework implementation.
2901 2903 */
2902 2904 vid = NULL;
2903 2905 /*
2904 2906 * model is all pid
2905 2907 */
2906 2908 pid = model;
2907 2909 }
2908 2910
2909 2911 /*
2910 2912 * override SCSA "inquiry-*" properties
2911 2913 */
2912 2914 if (vid)
2913 2915 (void) scsi_device_prop_update_inqstring(sd,
2914 2916 INQUIRY_VENDOR_ID, vid, strlen(vid));
2915 2917 if (pid)
2916 2918 (void) scsi_device_prop_update_inqstring(sd,
2917 2919 INQUIRY_PRODUCT_ID, pid, strlen(pid));
2918 2920 (void) scsi_device_prop_update_inqstring(sd,
2919 2921 INQUIRY_REVISION_ID, fw, strlen(fw));
2920 2922
2921 2923 if (inq89 != NULL) {
2922 2924 kmem_free(inq89, inq89_len);
2923 2925 }
2924 2926 } else {
2925 2927 mutex_exit(&mpt->m_mutex);
2926 2928 }
2927 2929
2928 2930 return (DDI_SUCCESS);
2929 2931 }
2930 2932 /*
2931 2933 * tran_tgt_free(9E) - target device instance deallocation
2932 2934 */
2933 2935 static void
2934 2936 mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
2935 2937 scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
2936 2938 {
2937 2939 #ifndef __lock_lint
2938 2940 _NOTE(ARGUNUSED(hba_dip, tgt_dip, hba_tran, sd))
2939 2941 #endif
2940 2942
2941 2943 mptsas_tgt_private_t *tgt_private = hba_tran->tran_tgt_private;
2942 2944
2943 2945 if (tgt_private != NULL) {
2944 2946 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t));
2945 2947 hba_tran->tran_tgt_private = NULL;
2946 2948 }
2947 2949 }
2948 2950
2949 2951 /*
2950 2952 * scsi_pkt handling
2951 2953 *
2952 2954 * Visible to the external world via the transport structure.
2953 2955 */
2954 2956
2955 2957 /*
2956 2958 * Notes:
2957 2959 * - transport the command to the addressed SCSI target/lun device
2958 2960 * - normal operation is to schedule the command to be transported,
2959 2961 * and return TRAN_ACCEPT if this is successful.
2960 2962 * - if NO_INTR, tran_start must poll device for command completion
2961 2963 */
2962 2964 static int
2963 2965 mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt)
2964 2966 {
2965 2967 #ifndef __lock_lint
2966 2968 _NOTE(ARGUNUSED(ap))
2967 2969 #endif
2968 2970 mptsas_t *mpt = PKT2MPT(pkt);
2969 2971 mptsas_cmd_t *cmd = PKT2CMD(pkt);
2970 2972 int rval;
2971 2973 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
2972 2974
2973 2975 NDBG1(("mptsas_scsi_start: pkt=0x%p", (void *)pkt));
2974 2976 ASSERT(ptgt);
2975 2977 if (ptgt == NULL)
2976 2978 return (TRAN_FATAL_ERROR);
2977 2979
2978 2980 /*
2979 2981 * prepare the pkt before taking mutex.
2980 2982 */
2981 2983 rval = mptsas_prepare_pkt(cmd);
2982 2984 if (rval != TRAN_ACCEPT) {
2983 2985 return (rval);
2984 2986 }
2985 2987
2986 2988 /*
2987 2989 * Send the command to target/lun, however your HBA requires it.
2988 2990 * If busy, return TRAN_BUSY; if there's some other formatting error
2989 2991 * in the packet, return TRAN_BADPKT; otherwise, fall through to the
2990 2992 * return of TRAN_ACCEPT.
2991 2993 *
2992 2994 * Remember that access to shared resources, including the mptsas_t
2993 2995 * data structure and the HBA hardware registers, must be protected
2994 2996 * with mutexes, here and everywhere.
2995 2997 *
2996 2998 * Also remember that at interrupt time, you'll get an argument
2997 2999 * to the interrupt handler which is a pointer to your mptsas_t
2998 3000 * structure; you'll have to remember which commands are outstanding
2999 3001 * and which scsi_pkt is the currently-running command so the
3000 3002 * interrupt handler can refer to the pkt to set completion
3001 3003 * status, call the target driver back through pkt_comp, etc.
3002 3004 */
3003 3005
3004 3006 mutex_enter(&ptgt->m_tgt_intr_mutex);
3005 3007 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3006 3008 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3007 3009 /*
3008 3010 * commands should be allowed to retry by
3009 3011 * returning TRAN_BUSY to stall the I/O's
3010 3012 * which come from scsi_vhci since the device/
3011 3013 * path is in unstable state now.
3012 3014 */
3013 3015 mutex_exit(&ptgt->m_tgt_intr_mutex);
3014 3016 return (TRAN_BUSY);
3015 3017 } else {
3016 3018 /*
3017 3019 * The device is offline, just fail the
3018 3020 * command by returning TRAN_FATAL_ERROR.
3019 3021 */
3020 3022 mutex_exit(&ptgt->m_tgt_intr_mutex);
3021 3023 return (TRAN_FATAL_ERROR);
3022 3024 }
3023 3025 }
3024 3026 mutex_exit(&ptgt->m_tgt_intr_mutex);
3025 3027 rval = mptsas_accept_pkt(mpt, cmd);
3026 3028
3027 3029 return (rval);
3028 3030 }
3029 3031
3030 3032 static int
3031 3033 mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd)
3032 3034 {
3033 3035 int rval = TRAN_ACCEPT;
3034 3036 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3035 3037
3036 3038 NDBG1(("mptsas_accept_pkt: cmd=0x%p", (void *)cmd));
3037 3039
3038 3040 if ((cmd->cmd_flags & CFLAG_PREPARED) == 0) {
3039 3041 rval = mptsas_prepare_pkt(cmd);
3040 3042 if (rval != TRAN_ACCEPT) {
3041 3043 cmd->cmd_flags &= ~CFLAG_TRANFLAG;
3042 3044 return (rval);
3043 3045 }
3044 3046 }
3045 3047
3046 3048 /*
3047 3049 * reset the throttle if we were draining
3048 3050 */
3049 3051 mutex_enter(&ptgt->m_tgt_intr_mutex);
3050 3052 if ((ptgt->m_t_ncmds == 0) &&
3051 3053 (ptgt->m_t_throttle == DRAIN_THROTTLE)) {
3052 3054 NDBG23(("reset throttle"));
3053 3055 ASSERT(ptgt->m_reset_delay == 0);
3054 3056 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
3055 3057 }
3056 3058
3057 3059 /*
3058 3060 * If device handle has already been invalidated, just
3059 3061 * fail the command. In theory, command from scsi_vhci
3060 3062 * client is impossible send down command with invalid
3061 3063 * devhdl since devhdl is set after path offline, target
3062 3064 * driver is not suppose to select a offlined path.
3063 3065 */
3064 3066 if (ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) {
3065 3067 NDBG20(("rejecting command, it might because invalid devhdl "
3066 3068 "request."));
3067 3069 mutex_exit(&ptgt->m_tgt_intr_mutex);
3068 3070 mutex_enter(&mpt->m_mutex);
3069 3071 /*
3070 3072 * If HBA is being reset, the DevHandles are being
3071 3073 * re-initialized, which means that they could be invalid
3072 3074 * even if the target is still attached. Check if being reset
3073 3075 * and if DevHandle is being re-initialized. If this is the
3074 3076 * case, return BUSY so the I/O can be retried later.
3075 3077 */
3076 3078 if (mpt->m_in_reset) {
3077 3079 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET,
3078 3080 STAT_BUS_RESET);
3079 3081 if (cmd->cmd_flags & CFLAG_TXQ) {
3080 3082 mptsas_doneq_add(mpt, cmd);
3081 3083 mptsas_doneq_empty(mpt);
3082 3084 mutex_exit(&mpt->m_mutex);
3083 3085 return (rval);
3084 3086 } else {
3085 3087 mutex_exit(&mpt->m_mutex);
3086 3088 return (TRAN_BUSY);
3087 3089 }
3088 3090 }
3089 3091 mptsas_set_pkt_reason(mpt, cmd, CMD_DEV_GONE, STAT_TERMINATED);
3090 3092 if (cmd->cmd_flags & CFLAG_TXQ) {
3091 3093 mptsas_doneq_add(mpt, cmd);
3092 3094 mptsas_doneq_empty(mpt);
3093 3095 mutex_exit(&mpt->m_mutex);
3094 3096 return (rval);
3095 3097 } else {
3096 3098 mutex_exit(&mpt->m_mutex);
3097 3099 return (TRAN_FATAL_ERROR);
3098 3100 }
3099 3101 }
3100 3102 mutex_exit(&ptgt->m_tgt_intr_mutex);
3101 3103 /*
3102 3104 * The first case is the normal case. mpt gets a command from the
3103 3105 * target driver and starts it.
3104 3106 * Since SMID 0 is reserved and the TM slot is reserved, the actual max
3105 3107 * commands is m_max_requests - 2.
3106 3108 */
3107 3109 mutex_enter(&ptgt->m_tgt_intr_mutex);
3108 3110 if ((ptgt->m_t_throttle > HOLD_THROTTLE) &&
3109 3111 (ptgt->m_t_ncmds < ptgt->m_t_throttle) &&
3110 3112 (ptgt->m_reset_delay == 0) &&
3111 3113 (ptgt->m_t_nwait == 0) &&
3112 3114 ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0)) {
3113 3115 mutex_exit(&ptgt->m_tgt_intr_mutex);
3114 3116 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
3115 3117 (void) mptsas_start_cmd0(mpt, cmd);
3116 3118 } else {
3117 3119 mutex_enter(&mpt->m_mutex);
3118 3120 mptsas_waitq_add(mpt, cmd);
3119 3121 mutex_exit(&mpt->m_mutex);
3120 3122 }
3121 3123 } else {
3122 3124 /*
3123 3125 * Add this pkt to the work queue
3124 3126 */
3125 3127 mutex_exit(&ptgt->m_tgt_intr_mutex);
3126 3128 mutex_enter(&mpt->m_mutex);
3127 3129 mptsas_waitq_add(mpt, cmd);
3128 3130
3129 3131 if (cmd->cmd_pkt_flags & FLAG_NOINTR) {
3130 3132 (void) mptsas_poll(mpt, cmd, MPTSAS_POLL_TIME);
3131 3133
3132 3134 /*
3133 3135 * Only flush the doneq if this is not a TM
3134 3136 * cmd. For TM cmds the flushing of the
3135 3137 * doneq will be done in those routines.
3136 3138 */
3137 3139 if ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) {
3138 3140 mptsas_doneq_empty(mpt);
3139 3141 }
3140 3142 }
3141 3143 mutex_exit(&mpt->m_mutex);
3142 3144 }
3143 3145 return (rval);
3144 3146 }
3145 3147
3146 3148 int
3147 3149 mptsas_save_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
3148 3150 {
3149 3151 mptsas_slots_t *slots;
3150 3152 int slot;
3151 3153 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3152 3154 mptsas_slot_free_e_t *pe;
3153 3155 int qn, qn_first;
3154 3156
3155 3157 slots = mpt->m_active;
3156 3158
3157 3159 /*
3158 3160 * Account for reserved TM request slot and reserved SMID of 0.
3159 3161 */
3160 3162 ASSERT(slots->m_n_slots == (mpt->m_max_requests - 2));
3161 3163
3162 3164 qn = qn_first = CPU->cpu_seqid & (mpt->m_slot_freeq_pair_n - 1);
3163 3165
3164 3166 qpair_retry:
3165 3167 ASSERT(qn < mpt->m_slot_freeq_pair_n);
3166 3168 mutex_enter(&mpt->m_slot_freeq_pairp[qn].m_slot_allocq.s.m_fq_mutex);
3167 3169 pe = list_head(&mpt->m_slot_freeq_pairp[qn].m_slot_allocq.
3168 3170 s.m_fq_list);
3169 3171 if (!pe) { /* switch the allocq and releq */
3170 3172 mutex_enter(&mpt->m_slot_freeq_pairp[qn].m_slot_releq.
3171 3173 s.m_fq_mutex);
3172 3174 if (mpt->m_slot_freeq_pairp[qn].m_slot_releq.s.m_fq_n) {
3173 3175 mpt->m_slot_freeq_pairp[qn].
3174 3176 m_slot_allocq.s.m_fq_n =
3175 3177 mpt->m_slot_freeq_pairp[qn].
3176 3178 m_slot_releq.s.m_fq_n;
3177 3179 mpt->m_slot_freeq_pairp[qn].
3178 3180 m_slot_allocq.s.m_fq_list.list_head.list_next =
3179 3181 mpt->m_slot_freeq_pairp[qn].
3180 3182 m_slot_releq.s.m_fq_list.list_head.list_next;
3181 3183 mpt->m_slot_freeq_pairp[qn].
3182 3184 m_slot_allocq.s.m_fq_list.list_head.list_prev =
3183 3185 mpt->m_slot_freeq_pairp[qn].
3184 3186 m_slot_releq.s.m_fq_list.list_head.list_prev;
3185 3187 mpt->m_slot_freeq_pairp[qn].
3186 3188 m_slot_releq.s.m_fq_list.list_head.list_prev->
3187 3189 list_next =
3188 3190 &mpt->m_slot_freeq_pairp[qn].
3189 3191 m_slot_allocq.s.m_fq_list.list_head;
3190 3192 mpt->m_slot_freeq_pairp[qn].
3191 3193 m_slot_releq.s.m_fq_list.list_head.list_next->
3192 3194 list_prev =
3193 3195 &mpt->m_slot_freeq_pairp[qn].
3194 3196 m_slot_allocq.s.m_fq_list.list_head;
3195 3197
3196 3198 mpt->m_slot_freeq_pairp[qn].
3197 3199 m_slot_releq.s.m_fq_list.list_head.list_next =
3198 3200 mpt->m_slot_freeq_pairp[qn].
3199 3201 m_slot_releq.s.m_fq_list.list_head.list_prev =
3200 3202 &mpt->m_slot_freeq_pairp[qn].
3201 3203 m_slot_releq.s.m_fq_list.list_head;
3202 3204 mpt->m_slot_freeq_pairp[qn].
3203 3205 m_slot_releq.s.m_fq_n = 0;
3204 3206 } else {
3205 3207 mutex_exit(&mpt->m_slot_freeq_pairp[qn].
3206 3208 m_slot_releq.s.m_fq_mutex);
3207 3209 mutex_exit(&mpt->m_slot_freeq_pairp[qn].
3208 3210 m_slot_allocq.s.m_fq_mutex);
3209 3211 qn = (qn + 1) & (mpt->m_slot_freeq_pair_n - 1);
3210 3212 if (qn == qn_first)
3211 3213 return (FALSE);
3212 3214 else
3213 3215 goto qpair_retry;
3214 3216 }
3215 3217 mutex_exit(&mpt->m_slot_freeq_pairp[qn].
3216 3218 m_slot_releq.s.m_fq_mutex);
3217 3219 pe = list_head(&mpt->m_slot_freeq_pairp[qn].
3218 3220 m_slot_allocq.s.m_fq_list);
3219 3221 ASSERT(pe);
3220 3222 }
3221 3223 list_remove(&mpt->m_slot_freeq_pairp[qn].
3222 3224 m_slot_allocq.s.m_fq_list, pe);
3223 3225 slot = pe->slot;
3224 3226 /*
3225 3227 * Make sure SMID is not using reserved value of 0
3226 3228 * and the TM request slot.
3227 3229 */
3228 3230 ASSERT((slot > 0) && (slot <= slots->m_n_slots) &&
3229 3231 mpt->m_slot_freeq_pairp[qn].m_slot_allocq.s.m_fq_n > 0);
3230 3232 cmd->cmd_slot = slot;
3231 3233 mpt->m_slot_freeq_pairp[qn].m_slot_allocq.s.m_fq_n--;
3232 3234 ASSERT(mpt->m_slot_freeq_pairp[qn].m_slot_allocq.s.m_fq_n >= 0);
3233 3235
3234 3236 mutex_exit(&mpt->m_slot_freeq_pairp[qn].m_slot_allocq.s.m_fq_mutex);
3235 3237 /*
3236 3238 * only increment per target ncmds if this is not a
3237 3239 * command that has no target associated with it (i.e. a
3238 3240 * event acknoledgment)
3239 3241 */
3240 3242 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
3241 3243 mutex_enter(&ptgt->m_tgt_intr_mutex);
3242 3244 ptgt->m_t_ncmds++;
3243 3245 mutex_exit(&ptgt->m_tgt_intr_mutex);
3244 3246 }
3245 3247 cmd->cmd_active_timeout = cmd->cmd_pkt->pkt_time;
3246 3248
3247 3249 /*
3248 3250 * If initial timout is less than or equal to one tick, bump
3249 3251 * the timeout by a tick so that command doesn't timeout before
3250 3252 * its allotted time.
3251 3253 */
3252 3254 if (cmd->cmd_active_timeout <= mptsas_scsi_watchdog_tick) {
3253 3255 cmd->cmd_active_timeout += mptsas_scsi_watchdog_tick;
3254 3256 }
3255 3257 return (TRUE);
3256 3258 }
3257 3259
3258 3260 /*
3259 3261 * prepare the pkt:
3260 3262 * the pkt may have been resubmitted or just reused so
3261 3263 * initialize some fields and do some checks.
3262 3264 */
3263 3265 static int
3264 3266 mptsas_prepare_pkt(mptsas_cmd_t *cmd)
3265 3267 {
3266 3268 struct scsi_pkt *pkt = CMD2PKT(cmd);
3267 3269
3268 3270 NDBG1(("mptsas_prepare_pkt: cmd=0x%p", (void *)cmd));
3269 3271
3270 3272 /*
3271 3273 * Reinitialize some fields that need it; the packet may
3272 3274 * have been resubmitted
3273 3275 */
3274 3276 pkt->pkt_reason = CMD_CMPLT;
3275 3277 pkt->pkt_state = 0;
3276 3278 pkt->pkt_statistics = 0;
3277 3279 pkt->pkt_resid = 0;
3278 3280 cmd->cmd_age = 0;
3279 3281 cmd->cmd_pkt_flags = pkt->pkt_flags;
3280 3282
3281 3283 /*
3282 3284 * zero status byte.
3283 3285 */
3284 3286 *(pkt->pkt_scbp) = 0;
3285 3287
3286 3288 if (cmd->cmd_flags & CFLAG_DMAVALID) {
3287 3289 pkt->pkt_resid = cmd->cmd_dmacount;
3288 3290
3289 3291 /*
3290 3292 * consistent packets need to be sync'ed first
3291 3293 * (only for data going out)
3292 3294 */
3293 3295 if ((cmd->cmd_flags & CFLAG_CMDIOPB) &&
3294 3296 (cmd->cmd_flags & CFLAG_DMASEND)) {
3295 3297 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
3296 3298 DDI_DMA_SYNC_FORDEV);
3297 3299 }
3298 3300 }
3299 3301
3300 3302 cmd->cmd_flags =
3301 3303 (cmd->cmd_flags & ~(CFLAG_TRANFLAG)) |
3302 3304 CFLAG_PREPARED | CFLAG_IN_TRANSPORT;
3303 3305
3304 3306 return (TRAN_ACCEPT);
3305 3307 }
3306 3308
3307 3309 /*
3308 3310 * tran_init_pkt(9E) - allocate scsi_pkt(9S) for command
3309 3311 *
3310 3312 * One of three possibilities:
3311 3313 * - allocate scsi_pkt
3312 3314 * - allocate scsi_pkt and DMA resources
3313 3315 * - allocate DMA resources to an already-allocated pkt
3314 3316 */
3315 3317 static struct scsi_pkt *
3316 3318 mptsas_scsi_init_pkt(struct scsi_address *ap, struct scsi_pkt *pkt,
3317 3319 struct buf *bp, int cmdlen, int statuslen, int tgtlen, int flags,
3318 3320 int (*callback)(), caddr_t arg)
3319 3321 {
3320 3322 mptsas_cmd_t *cmd, *new_cmd;
3321 3323 mptsas_t *mpt = ADDR2MPT(ap);
3322 3324 int failure = 1;
3323 3325 #ifndef __sparc
3324 3326 uint_t oldcookiec;
3325 3327 #endif /* __sparc */
3326 3328 mptsas_target_t *ptgt = NULL;
3327 3329 int rval;
3328 3330 mptsas_tgt_private_t *tgt_private;
3329 3331 int kf;
3330 3332
3331 3333 kf = (callback == SLEEP_FUNC)? KM_SLEEP: KM_NOSLEEP;
3332 3334
3333 3335 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->
3334 3336 tran_tgt_private;
3335 3337 ASSERT(tgt_private != NULL);
3336 3338 if (tgt_private == NULL) {
3337 3339 return (NULL);
3338 3340 }
3339 3341 ptgt = tgt_private->t_private;
3340 3342 ASSERT(ptgt != NULL);
3341 3343 if (ptgt == NULL)
3342 3344 return (NULL);
3343 3345 ap->a_target = ptgt->m_devhdl;
3344 3346 ap->a_lun = tgt_private->t_lun;
3345 3347
3346 3348 ASSERT(callback == NULL_FUNC || callback == SLEEP_FUNC);
3347 3349 #ifdef MPTSAS_TEST_EXTRN_ALLOC
3348 3350 statuslen *= 100; tgtlen *= 4;
3349 3351 #endif
3350 3352 NDBG3(("mptsas_scsi_init_pkt:\n"
3351 3353 "\ttgt=%d in=0x%p bp=0x%p clen=%d slen=%d tlen=%d flags=%x",
3352 3354 ap->a_target, (void *)pkt, (void *)bp,
3353 3355 cmdlen, statuslen, tgtlen, flags));
3354 3356
3355 3357 /*
3356 3358 * Allocate the new packet.
3357 3359 */
3358 3360 if (pkt == NULL) {
3359 3361 ddi_dma_handle_t save_dma_handle;
3360 3362 ddi_dma_handle_t save_arq_dma_handle;
3361 3363 struct buf *save_arq_bp;
3362 3364 ddi_dma_cookie_t save_arqcookie;
3363 3365 #ifdef __sparc
3364 3366 mptti_t *save_sg;
3365 3367 #endif /* __sparc */
3366 3368
3367 3369 cmd = kmem_cache_alloc(mpt->m_kmem_cache, kf);
3368 3370
3369 3371 if (cmd) {
3370 3372 save_dma_handle = cmd->cmd_dmahandle;
3371 3373 save_arq_dma_handle = cmd->cmd_arqhandle;
3372 3374 save_arq_bp = cmd->cmd_arq_buf;
3373 3375 save_arqcookie = cmd->cmd_arqcookie;
3374 3376 #ifdef __sparc
3375 3377 save_sg = cmd->cmd_sg;
3376 3378 #endif /* __sparc */
3377 3379 bzero(cmd, sizeof (*cmd) + scsi_pkt_size());
3378 3380 cmd->cmd_dmahandle = save_dma_handle;
3379 3381 cmd->cmd_arqhandle = save_arq_dma_handle;
3380 3382 cmd->cmd_arq_buf = save_arq_bp;
3381 3383 cmd->cmd_arqcookie = save_arqcookie;
3382 3384 #ifdef __sparc
3383 3385 cmd->cmd_sg = save_sg;
3384 3386 #endif /* __sparc */
3385 3387 pkt = (void *)((uchar_t *)cmd +
3386 3388 sizeof (struct mptsas_cmd));
3387 3389 pkt->pkt_ha_private = (opaque_t)cmd;
3388 3390 pkt->pkt_address = *ap;
3389 3391 pkt->pkt_private = (opaque_t)cmd->cmd_pkt_private;
3390 3392 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb;
3391 3393 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb;
3392 3394 cmd->cmd_pkt = (struct scsi_pkt *)pkt;
3393 3395 cmd->cmd_cdblen = (uchar_t)cmdlen;
3394 3396 cmd->cmd_scblen = statuslen;
3395 3397 cmd->cmd_rqslen = SENSE_LENGTH;
3396 3398 cmd->cmd_tgt_addr = ptgt;
3397 3399 failure = 0;
3398 3400 }
3399 3401
3400 3402 if (failure || (cmdlen > sizeof (cmd->cmd_cdb)) ||
3401 3403 (tgtlen > PKT_PRIV_LEN) ||
3402 3404 (statuslen > EXTCMDS_STATUS_SIZE)) {
3403 3405 if (failure == 0) {
3404 3406 /*
3405 3407 * if extern alloc fails, all will be
3406 3408 * deallocated, including cmd
3407 3409 */
3408 3410 failure = mptsas_pkt_alloc_extern(mpt, cmd,
3409 3411 cmdlen, tgtlen, statuslen, kf);
3410 3412 }
3411 3413 if (failure) {
3412 3414 /*
3413 3415 * if extern allocation fails, it will
3414 3416 * deallocate the new pkt as well
3415 3417 */
3416 3418 return (NULL);
3417 3419 }
3418 3420 }
3419 3421 new_cmd = cmd;
3420 3422
3421 3423 } else {
3422 3424 cmd = PKT2CMD(pkt);
3423 3425 new_cmd = NULL;
3424 3426 }
3425 3427
3426 3428
3427 3429 #ifndef __sparc
3428 3430 /* grab cmd->cmd_cookiec here as oldcookiec */
3429 3431
3430 3432 oldcookiec = cmd->cmd_cookiec;
3431 3433 #endif /* __sparc */
3432 3434
3433 3435 /*
3434 3436 * If the dma was broken up into PARTIAL transfers cmd_nwin will be
3435 3437 * greater than 0 and we'll need to grab the next dma window
3436 3438 */
3437 3439 /*
3438 3440 * SLM-not doing extra command frame right now; may add later
3439 3441 */
3440 3442
3441 3443 if (cmd->cmd_nwin > 0) {
3442 3444
3443 3445 /*
3444 3446 * Make sure we havn't gone past the the total number
3445 3447 * of windows
3446 3448 */
3447 3449 if (++cmd->cmd_winindex >= cmd->cmd_nwin) {
3448 3450 return (NULL);
3449 3451 }
3450 3452 if (ddi_dma_getwin(cmd->cmd_dmahandle, cmd->cmd_winindex,
3451 3453 &cmd->cmd_dma_offset, &cmd->cmd_dma_len,
3452 3454 &cmd->cmd_cookie, &cmd->cmd_cookiec) == DDI_FAILURE) {
3453 3455 return (NULL);
3454 3456 }
3455 3457 goto get_dma_cookies;
3456 3458 }
3457 3459
3458 3460
3459 3461 if (flags & PKT_XARQ) {
3460 3462 cmd->cmd_flags |= CFLAG_XARQ;
3461 3463 }
3462 3464
3463 3465 /*
3464 3466 * DMA resource allocation. This version assumes your
3465 3467 * HBA has some sort of bus-mastering or onboard DMA capability, with a
3466 3468 * scatter-gather list of length MPTSAS_MAX_DMA_SEGS, as given in the
3467 3469 * ddi_dma_attr_t structure and passed to scsi_impl_dmaget.
3468 3470 */
3469 3471 if (bp && (bp->b_bcount != 0) &&
3470 3472 (cmd->cmd_flags & CFLAG_DMAVALID) == 0) {
3471 3473
3472 3474 int cnt, dma_flags;
3473 3475 mptti_t *dmap; /* ptr to the S/G list */
3474 3476
3475 3477 /*
3476 3478 * Set up DMA memory and position to the next DMA segment.
3477 3479 */
3478 3480 ASSERT(cmd->cmd_dmahandle != NULL);
3479 3481
3480 3482 if (bp->b_flags & B_READ) {
3481 3483 dma_flags = DDI_DMA_READ;
3482 3484 cmd->cmd_flags &= ~CFLAG_DMASEND;
3483 3485 } else {
3484 3486 dma_flags = DDI_DMA_WRITE;
3485 3487 cmd->cmd_flags |= CFLAG_DMASEND;
3486 3488 }
3487 3489 if (flags & PKT_CONSISTENT) {
3488 3490 cmd->cmd_flags |= CFLAG_CMDIOPB;
3489 3491 dma_flags |= DDI_DMA_CONSISTENT;
3490 3492 }
3491 3493
3492 3494 if (flags & PKT_DMA_PARTIAL) {
3493 3495 dma_flags |= DDI_DMA_PARTIAL;
3494 3496 }
3495 3497
3496 3498 /*
3497 3499 * workaround for byte hole issue on psycho and
3498 3500 * schizo pre 2.1
3499 3501 */
3500 3502 if ((bp->b_flags & B_READ) && ((bp->b_flags &
3501 3503 (B_PAGEIO|B_REMAPPED)) != B_PAGEIO) &&
3502 3504 ((uintptr_t)bp->b_un.b_addr & 0x7)) {
3503 3505 dma_flags |= DDI_DMA_CONSISTENT;
3504 3506 }
3505 3507
3506 3508 rval = ddi_dma_buf_bind_handle(cmd->cmd_dmahandle, bp,
3507 3509 dma_flags, callback, arg,
3508 3510 &cmd->cmd_cookie, &cmd->cmd_cookiec);
3509 3511 if (rval == DDI_DMA_PARTIAL_MAP) {
3510 3512 (void) ddi_dma_numwin(cmd->cmd_dmahandle,
3511 3513 &cmd->cmd_nwin);
3512 3514 cmd->cmd_winindex = 0;
3513 3515 (void) ddi_dma_getwin(cmd->cmd_dmahandle,
3514 3516 cmd->cmd_winindex, &cmd->cmd_dma_offset,
3515 3517 &cmd->cmd_dma_len, &cmd->cmd_cookie,
3516 3518 &cmd->cmd_cookiec);
3517 3519 } else if (rval && (rval != DDI_DMA_MAPPED)) {
3518 3520 switch (rval) {
3519 3521 case DDI_DMA_NORESOURCES:
3520 3522 bioerror(bp, 0);
3521 3523 break;
3522 3524 case DDI_DMA_BADATTR:
3523 3525 case DDI_DMA_NOMAPPING:
3524 3526 bioerror(bp, EFAULT);
3525 3527 break;
3526 3528 case DDI_DMA_TOOBIG:
3527 3529 default:
3528 3530 bioerror(bp, EINVAL);
3529 3531 break;
3530 3532 }
3531 3533 cmd->cmd_flags &= ~CFLAG_DMAVALID;
3532 3534 if (new_cmd) {
3533 3535 mptsas_scsi_destroy_pkt(ap, pkt);
3534 3536 }
3535 3537 return ((struct scsi_pkt *)NULL);
3536 3538 }
3537 3539
3538 3540 get_dma_cookies:
3539 3541 cmd->cmd_flags |= CFLAG_DMAVALID;
3540 3542 ASSERT(cmd->cmd_cookiec > 0);
3541 3543
3542 3544 if (cmd->cmd_cookiec > MPTSAS_MAX_CMD_SEGS) {
3543 3545 mptsas_log(mpt, CE_NOTE, "large cookiec received %d\n",
3544 3546 cmd->cmd_cookiec);
3545 3547 bioerror(bp, EINVAL);
3546 3548 if (new_cmd) {
3547 3549 mptsas_scsi_destroy_pkt(ap, pkt);
3548 3550 }
3549 3551 return ((struct scsi_pkt *)NULL);
3550 3552 }
3551 3553
3552 3554 /*
3553 3555 * Allocate extra SGL buffer if needed.
3554 3556 */
3555 3557 if ((cmd->cmd_cookiec > MPTSAS_MAX_FRAME_SGES64(mpt)) &&
3556 3558 (cmd->cmd_extra_frames == NULL)) {
3557 3559 if (mptsas_alloc_extra_sgl_frame(mpt, cmd) ==
3558 3560 DDI_FAILURE) {
3559 3561 mptsas_log(mpt, CE_WARN, "MPT SGL mem alloc "
3560 3562 "failed");
3561 3563 bioerror(bp, ENOMEM);
3562 3564 if (new_cmd) {
3563 3565 mptsas_scsi_destroy_pkt(ap, pkt);
3564 3566 }
3565 3567 return ((struct scsi_pkt *)NULL);
3566 3568 }
3567 3569 }
3568 3570
3569 3571 /*
3570 3572 * Always use scatter-gather transfer
3571 3573 * Use the loop below to store physical addresses of
3572 3574 * DMA segments, from the DMA cookies, into your HBA's
3573 3575 * scatter-gather list.
3574 3576 * We need to ensure we have enough kmem alloc'd
3575 3577 * for the sg entries since we are no longer using an
3576 3578 * array inside mptsas_cmd_t.
3577 3579 *
3578 3580 * We check cmd->cmd_cookiec against oldcookiec so
3579 3581 * the scatter-gather list is correctly allocated
3580 3582 */
3581 3583 #ifndef __sparc
3582 3584 if (oldcookiec != cmd->cmd_cookiec) {
3583 3585 if (cmd->cmd_sg != (mptti_t *)NULL) {
3584 3586 kmem_free(cmd->cmd_sg, sizeof (mptti_t) *
3585 3587 oldcookiec);
3586 3588 cmd->cmd_sg = NULL;
3587 3589 }
3588 3590 }
3589 3591
3590 3592 if (cmd->cmd_sg == (mptti_t *)NULL) {
3591 3593 cmd->cmd_sg = kmem_alloc((size_t)(sizeof (mptti_t)*
3592 3594 cmd->cmd_cookiec), kf);
3593 3595
3594 3596 if (cmd->cmd_sg == (mptti_t *)NULL) {
3595 3597 mptsas_log(mpt, CE_WARN,
3596 3598 "unable to kmem_alloc enough memory "
3597 3599 "for scatter/gather list");
3598 3600 /*
3599 3601 * if we have an ENOMEM condition we need to behave
3600 3602 * the same way as the rest of this routine
3601 3603 */
3602 3604
3603 3605 bioerror(bp, ENOMEM);
3604 3606 if (new_cmd) {
3605 3607 mptsas_scsi_destroy_pkt(ap, pkt);
3606 3608 }
3607 3609 return ((struct scsi_pkt *)NULL);
3608 3610 }
3609 3611 }
3610 3612 #endif /* __sparc */
3611 3613 dmap = cmd->cmd_sg;
3612 3614
3613 3615 ASSERT(cmd->cmd_cookie.dmac_size != 0);
3614 3616
3615 3617 /*
3616 3618 * store the first segment into the S/G list
3617 3619 */
3618 3620 dmap->count = cmd->cmd_cookie.dmac_size;
3619 3621 dmap->addr.address64.Low = (uint32_t)
3620 3622 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull);
3621 3623 dmap->addr.address64.High = (uint32_t)
3622 3624 (cmd->cmd_cookie.dmac_laddress >> 32);
3623 3625
3624 3626 /*
3625 3627 * dmacount counts the size of the dma for this window
3626 3628 * (if partial dma is being used). totaldmacount
3627 3629 * keeps track of the total amount of dma we have
3628 3630 * transferred for all the windows (needed to calculate
3629 3631 * the resid value below).
3630 3632 */
3631 3633 cmd->cmd_dmacount = cmd->cmd_cookie.dmac_size;
3632 3634 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size;
3633 3635
3634 3636 /*
3635 3637 * We already stored the first DMA scatter gather segment,
3636 3638 * start at 1 if we need to store more.
3637 3639 */
3638 3640 for (cnt = 1; cnt < cmd->cmd_cookiec; cnt++) {
3639 3641 /*
3640 3642 * Get next DMA cookie
3641 3643 */
3642 3644 ddi_dma_nextcookie(cmd->cmd_dmahandle,
3643 3645 &cmd->cmd_cookie);
3644 3646 dmap++;
3645 3647
3646 3648 cmd->cmd_dmacount += cmd->cmd_cookie.dmac_size;
3647 3649 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size;
3648 3650
3649 3651 /*
3650 3652 * store the segment parms into the S/G list
3651 3653 */
3652 3654 dmap->count = cmd->cmd_cookie.dmac_size;
3653 3655 dmap->addr.address64.Low = (uint32_t)
3654 3656 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull);
3655 3657 dmap->addr.address64.High = (uint32_t)
3656 3658 (cmd->cmd_cookie.dmac_laddress >> 32);
3657 3659 }
3658 3660
3659 3661 /*
3660 3662 * If this was partially allocated we set the resid
3661 3663 * the amount of data NOT transferred in this window
3662 3664 * If there is only one window, the resid will be 0
3663 3665 */
3664 3666 pkt->pkt_resid = (bp->b_bcount - cmd->cmd_totaldmacount);
3665 3667 NDBG16(("mptsas_dmaget: cmd_dmacount=%d.", cmd->cmd_dmacount));
3666 3668 }
3667 3669 return (pkt);
3668 3670 }
3669 3671
3670 3672 /*
3671 3673 * tran_destroy_pkt(9E) - scsi_pkt(9s) deallocation
3672 3674 *
3673 3675 * Notes:
3674 3676 * - also frees DMA resources if allocated
3675 3677 * - implicit DMA synchonization
3676 3678 */
3677 3679 static void
3678 3680 mptsas_scsi_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
3679 3681 {
3680 3682 mptsas_cmd_t *cmd = PKT2CMD(pkt);
3681 3683 mptsas_t *mpt = ADDR2MPT(ap);
3682 3684
3683 3685 NDBG3(("mptsas_scsi_destroy_pkt: target=%d pkt=0x%p",
3684 3686 ap->a_target, (void *)pkt));
3685 3687
3686 3688 if (cmd->cmd_flags & CFLAG_DMAVALID) {
3687 3689 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle);
3688 3690 cmd->cmd_flags &= ~CFLAG_DMAVALID;
3689 3691 }
3690 3692 #ifndef __sparc
3691 3693 if (cmd->cmd_sg) {
3692 3694 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * cmd->cmd_cookiec);
3693 3695 cmd->cmd_sg = NULL;
3694 3696 }
3695 3697 #endif /* __sparc */
3696 3698 mptsas_free_extra_sgl_frame(mpt, cmd);
3697 3699
3698 3700 if ((cmd->cmd_flags &
3699 3701 (CFLAG_FREE | CFLAG_CDBEXTERN | CFLAG_PRIVEXTERN |
3700 3702 CFLAG_SCBEXTERN)) == 0) {
3701 3703 cmd->cmd_flags = CFLAG_FREE;
3702 3704 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd);
3703 3705 } else {
3704 3706 mptsas_pkt_destroy_extern(mpt, cmd);
3705 3707 }
3706 3708 }
3707 3709
3708 3710 /*
3709 3711 * kmem cache constructor and destructor:
3710 3712 * When constructing, we bzero the cmd and allocate the dma handle
3711 3713 * When destructing, just free the dma handle
3712 3714 */
3713 3715 static int
3714 3716 mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags)
3715 3717 {
3716 3718 mptsas_cmd_t *cmd = buf;
3717 3719 mptsas_t *mpt = cdrarg;
3718 3720 struct scsi_address ap;
3719 3721 uint_t cookiec;
3720 3722 ddi_dma_attr_t arq_dma_attr;
3721 3723 int (*callback)(caddr_t);
3722 3724
3723 3725 callback = (kmflags == KM_SLEEP)? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT;
3724 3726
3725 3727 NDBG4(("mptsas_kmem_cache_constructor"));
3726 3728
3727 3729 ap.a_hba_tran = mpt->m_tran;
3728 3730 ap.a_target = 0;
3729 3731 ap.a_lun = 0;
3730 3732
3731 3733 /*
3732 3734 * allocate a dma handle
3733 3735 */
3734 3736 if ((ddi_dma_alloc_handle(mpt->m_dip, &mpt->m_io_dma_attr, callback,
3735 3737 NULL, &cmd->cmd_dmahandle)) != DDI_SUCCESS) {
3736 3738 cmd->cmd_dmahandle = NULL;
3737 3739 return (-1);
3738 3740 }
3739 3741
3740 3742 cmd->cmd_arq_buf = scsi_alloc_consistent_buf(&ap, (struct buf *)NULL,
3741 3743 SENSE_LENGTH, B_READ, callback, NULL);
3742 3744 if (cmd->cmd_arq_buf == NULL) {
3743 3745 ddi_dma_free_handle(&cmd->cmd_dmahandle);
3744 3746 cmd->cmd_dmahandle = NULL;
3745 3747 return (-1);
3746 3748 }
3747 3749
3748 3750 /*
3749 3751 * allocate a arq handle
3750 3752 */
3751 3753 arq_dma_attr = mpt->m_msg_dma_attr;
3752 3754 arq_dma_attr.dma_attr_sgllen = 1;
3753 3755 if ((ddi_dma_alloc_handle(mpt->m_dip, &arq_dma_attr, callback,
3754 3756 NULL, &cmd->cmd_arqhandle)) != DDI_SUCCESS) {
3755 3757 ddi_dma_free_handle(&cmd->cmd_dmahandle);
3756 3758 scsi_free_consistent_buf(cmd->cmd_arq_buf);
3757 3759 cmd->cmd_dmahandle = NULL;
3758 3760 cmd->cmd_arqhandle = NULL;
3759 3761 return (-1);
3760 3762 }
3761 3763
3762 3764 if (ddi_dma_buf_bind_handle(cmd->cmd_arqhandle,
3763 3765 cmd->cmd_arq_buf, (DDI_DMA_READ | DDI_DMA_CONSISTENT),
3764 3766 callback, NULL, &cmd->cmd_arqcookie, &cookiec) != DDI_SUCCESS) {
3765 3767 ddi_dma_free_handle(&cmd->cmd_dmahandle);
3766 3768 ddi_dma_free_handle(&cmd->cmd_arqhandle);
3767 3769 scsi_free_consistent_buf(cmd->cmd_arq_buf);
3768 3770 cmd->cmd_dmahandle = NULL;
3769 3771 cmd->cmd_arqhandle = NULL;
3770 3772 cmd->cmd_arq_buf = NULL;
3771 3773 return (-1);
3772 3774 }
3773 3775 /*
3774 3776 * In sparc, the sgl length in most of the cases would be 1, so we
3775 3777 * pre-allocate it in cache. On x86, the max number would be 256,
3776 3778 * pre-allocate a maximum would waste a lot of memory especially
3777 3779 * when many cmds are put onto waitq.
3778 3780 */
3779 3781 #ifdef __sparc
3780 3782 cmd->cmd_sg = kmem_alloc((size_t)(sizeof (mptti_t)*
3781 3783 MPTSAS_MAX_CMD_SEGS), KM_SLEEP);
3782 3784 #endif /* __sparc */
3783 3785
3784 3786 return (0);
3785 3787 }
3786 3788
3787 3789 static void
3788 3790 mptsas_kmem_cache_destructor(void *buf, void *cdrarg)
3789 3791 {
3790 3792 #ifndef __lock_lint
3791 3793 _NOTE(ARGUNUSED(cdrarg))
3792 3794 #endif
3793 3795 mptsas_cmd_t *cmd = buf;
3794 3796
3795 3797 NDBG4(("mptsas_kmem_cache_destructor"));
3796 3798
3797 3799 if (cmd->cmd_arqhandle) {
3798 3800 (void) ddi_dma_unbind_handle(cmd->cmd_arqhandle);
3799 3801 ddi_dma_free_handle(&cmd->cmd_arqhandle);
3800 3802 cmd->cmd_arqhandle = NULL;
3801 3803 }
3802 3804 if (cmd->cmd_arq_buf) {
3803 3805 scsi_free_consistent_buf(cmd->cmd_arq_buf);
3804 3806 cmd->cmd_arq_buf = NULL;
3805 3807 }
3806 3808 if (cmd->cmd_dmahandle) {
3807 3809 ddi_dma_free_handle(&cmd->cmd_dmahandle);
3808 3810 cmd->cmd_dmahandle = NULL;
3809 3811 }
3810 3812 #ifdef __sparc
3811 3813 if (cmd->cmd_sg) {
3812 3814 kmem_free(cmd->cmd_sg, sizeof (mptti_t)* MPTSAS_MAX_CMD_SEGS);
3813 3815 cmd->cmd_sg = NULL;
3814 3816 }
3815 3817 #endif /* __sparc */
3816 3818 }
3817 3819
3818 3820 static int
3819 3821 mptsas_cache_frames_constructor(void *buf, void *cdrarg, int kmflags)
3820 3822 {
3821 3823 mptsas_cache_frames_t *p = buf;
3822 3824 mptsas_t *mpt = cdrarg;
3823 3825 ddi_dma_attr_t frame_dma_attr;
3824 3826 size_t mem_size, alloc_len;
3825 3827 ddi_dma_cookie_t cookie;
3826 3828 uint_t ncookie;
3827 3829 int (*callback)(caddr_t) = (kmflags == KM_SLEEP)
3828 3830 ? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT;
3829 3831
3830 3832 frame_dma_attr = mpt->m_msg_dma_attr;
3831 3833 frame_dma_attr.dma_attr_align = 0x10;
3832 3834 frame_dma_attr.dma_attr_sgllen = 1;
3833 3835
3834 3836 if (ddi_dma_alloc_handle(mpt->m_dip, &frame_dma_attr, callback, NULL,
3835 3837 &p->m_dma_hdl) != DDI_SUCCESS) {
3836 3838 mptsas_log(mpt, CE_WARN, "Unable to allocate dma handle for"
3837 3839 " extra SGL.");
3838 3840 return (DDI_FAILURE);
3839 3841 }
3840 3842
3841 3843 mem_size = (mpt->m_max_request_frames - 1) * mpt->m_req_frame_size;
3842 3844
3843 3845 if (ddi_dma_mem_alloc(p->m_dma_hdl, mem_size, &mpt->m_dev_acc_attr,
3844 3846 DDI_DMA_CONSISTENT, callback, NULL, (caddr_t *)&p->m_frames_addr,
3845 3847 &alloc_len, &p->m_acc_hdl) != DDI_SUCCESS) {
3846 3848 ddi_dma_free_handle(&p->m_dma_hdl);
3847 3849 p->m_dma_hdl = NULL;
3848 3850 mptsas_log(mpt, CE_WARN, "Unable to allocate dma memory for"
3849 3851 " extra SGL.");
3850 3852 return (DDI_FAILURE);
3851 3853 }
3852 3854
3853 3855 if (ddi_dma_addr_bind_handle(p->m_dma_hdl, NULL, p->m_frames_addr,
3854 3856 alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, callback, NULL,
3855 3857 &cookie, &ncookie) != DDI_DMA_MAPPED) {
3856 3858 (void) ddi_dma_mem_free(&p->m_acc_hdl);
3857 3859 ddi_dma_free_handle(&p->m_dma_hdl);
3858 3860 p->m_dma_hdl = NULL;
3859 3861 mptsas_log(mpt, CE_WARN, "Unable to bind DMA resources for"
3860 3862 " extra SGL");
3861 3863 return (DDI_FAILURE);
3862 3864 }
3863 3865
3864 3866 /*
3865 3867 * Store the SGL memory address. This chip uses this
3866 3868 * address to dma to and from the driver. The second
3867 3869 * address is the address mpt uses to fill in the SGL.
3868 3870 */
3869 3871 p->m_phys_addr = cookie.dmac_address;
3870 3872
3871 3873 return (DDI_SUCCESS);
3872 3874 }
3873 3875
3874 3876 static void
3875 3877 mptsas_cache_frames_destructor(void *buf, void *cdrarg)
3876 3878 {
3877 3879 #ifndef __lock_lint
3878 3880 _NOTE(ARGUNUSED(cdrarg))
3879 3881 #endif
3880 3882 mptsas_cache_frames_t *p = buf;
3881 3883 if (p->m_dma_hdl != NULL) {
3882 3884 (void) ddi_dma_unbind_handle(p->m_dma_hdl);
3883 3885 (void) ddi_dma_mem_free(&p->m_acc_hdl);
3884 3886 ddi_dma_free_handle(&p->m_dma_hdl);
3885 3887 p->m_phys_addr = NULL;
3886 3888 p->m_frames_addr = NULL;
3887 3889 p->m_dma_hdl = NULL;
3888 3890 p->m_acc_hdl = NULL;
3889 3891 }
3890 3892
3891 3893 }
3892 3894
3893 3895 /*
3894 3896 * allocate and deallocate external pkt space (ie. not part of mptsas_cmd)
3895 3897 * for non-standard length cdb, pkt_private, status areas
3896 3898 * if allocation fails, then deallocate all external space and the pkt
3897 3899 */
3898 3900 /* ARGSUSED */
3899 3901 static int
3900 3902 mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd,
3901 3903 int cmdlen, int tgtlen, int statuslen, int kf)
3902 3904 {
3903 3905 caddr_t cdbp, scbp, tgt;
3904 3906 int (*callback)(caddr_t) = (kf == KM_SLEEP) ?
3905 3907 DDI_DMA_SLEEP : DDI_DMA_DONTWAIT;
3906 3908 struct scsi_address ap;
3907 3909 size_t senselength;
3908 3910 ddi_dma_attr_t ext_arq_dma_attr;
3909 3911 uint_t cookiec;
3910 3912
3911 3913 NDBG3(("mptsas_pkt_alloc_extern: "
3912 3914 "cmd=0x%p cmdlen=%d tgtlen=%d statuslen=%d kf=%x",
3913 3915 (void *)cmd, cmdlen, tgtlen, statuslen, kf));
3914 3916
3915 3917 tgt = cdbp = scbp = NULL;
3916 3918 cmd->cmd_scblen = statuslen;
3917 3919 cmd->cmd_privlen = (uchar_t)tgtlen;
3918 3920
3919 3921 if (cmdlen > sizeof (cmd->cmd_cdb)) {
3920 3922 if ((cdbp = kmem_zalloc((size_t)cmdlen, kf)) == NULL) {
3921 3923 goto fail;
3922 3924 }
3923 3925 cmd->cmd_pkt->pkt_cdbp = (opaque_t)cdbp;
3924 3926 cmd->cmd_flags |= CFLAG_CDBEXTERN;
3925 3927 }
3926 3928 if (tgtlen > PKT_PRIV_LEN) {
3927 3929 if ((tgt = kmem_zalloc((size_t)tgtlen, kf)) == NULL) {
3928 3930 goto fail;
3929 3931 }
3930 3932 cmd->cmd_flags |= CFLAG_PRIVEXTERN;
3931 3933 cmd->cmd_pkt->pkt_private = tgt;
3932 3934 }
3933 3935 if (statuslen > EXTCMDS_STATUS_SIZE) {
3934 3936 if ((scbp = kmem_zalloc((size_t)statuslen, kf)) == NULL) {
3935 3937 goto fail;
3936 3938 }
3937 3939 cmd->cmd_flags |= CFLAG_SCBEXTERN;
3938 3940 cmd->cmd_pkt->pkt_scbp = (opaque_t)scbp;
3939 3941
3940 3942 /* allocate sense data buf for DMA */
3941 3943
3942 3944 senselength = statuslen - MPTSAS_GET_ITEM_OFF(
3943 3945 struct scsi_arq_status, sts_sensedata);
3944 3946 cmd->cmd_rqslen = (uchar_t)senselength;
3945 3947
3946 3948 ap.a_hba_tran = mpt->m_tran;
3947 3949 ap.a_target = 0;
3948 3950 ap.a_lun = 0;
3949 3951
3950 3952 cmd->cmd_ext_arq_buf = scsi_alloc_consistent_buf(&ap,
3951 3953 (struct buf *)NULL, senselength, B_READ,
3952 3954 callback, NULL);
3953 3955
3954 3956 if (cmd->cmd_ext_arq_buf == NULL) {
3955 3957 goto fail;
3956 3958 }
3957 3959 /*
3958 3960 * allocate a extern arq handle and bind the buf
3959 3961 */
3960 3962 ext_arq_dma_attr = mpt->m_msg_dma_attr;
3961 3963 ext_arq_dma_attr.dma_attr_sgllen = 1;
3962 3964 if ((ddi_dma_alloc_handle(mpt->m_dip,
3963 3965 &ext_arq_dma_attr, callback,
3964 3966 NULL, &cmd->cmd_ext_arqhandle)) != DDI_SUCCESS) {
3965 3967 goto fail;
3966 3968 }
3967 3969
3968 3970 if (ddi_dma_buf_bind_handle(cmd->cmd_ext_arqhandle,
3969 3971 cmd->cmd_ext_arq_buf, (DDI_DMA_READ | DDI_DMA_CONSISTENT),
3970 3972 callback, NULL, &cmd->cmd_ext_arqcookie,
3971 3973 &cookiec)
3972 3974 != DDI_SUCCESS) {
3973 3975 goto fail;
3974 3976 }
3975 3977 cmd->cmd_flags |= CFLAG_EXTARQBUFVALID;
3976 3978 }
3977 3979 return (0);
3978 3980 fail:
3979 3981 mptsas_pkt_destroy_extern(mpt, cmd);
3980 3982 return (1);
3981 3983 }
3982 3984
3983 3985 /*
3984 3986 * deallocate external pkt space and deallocate the pkt
3985 3987 */
3986 3988 static void
3987 3989 mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd)
3988 3990 {
3989 3991 NDBG3(("mptsas_pkt_destroy_extern: cmd=0x%p", (void *)cmd));
3990 3992
3991 3993 if (cmd->cmd_flags & CFLAG_FREE) {
3992 3994 mptsas_log(mpt, CE_PANIC,
3993 3995 "mptsas_pkt_destroy_extern: freeing free packet");
3994 3996 _NOTE(NOT_REACHED)
3995 3997 /* NOTREACHED */
3996 3998 }
3997 3999 if (cmd->cmd_flags & CFLAG_CDBEXTERN) {
3998 4000 kmem_free(cmd->cmd_pkt->pkt_cdbp, (size_t)cmd->cmd_cdblen);
3999 4001 }
4000 4002 if (cmd->cmd_flags & CFLAG_SCBEXTERN) {
4001 4003 kmem_free(cmd->cmd_pkt->pkt_scbp, (size_t)cmd->cmd_scblen);
4002 4004 if (cmd->cmd_flags & CFLAG_EXTARQBUFVALID) {
4003 4005 (void) ddi_dma_unbind_handle(cmd->cmd_ext_arqhandle);
4004 4006 }
4005 4007 if (cmd->cmd_ext_arqhandle) {
4006 4008 ddi_dma_free_handle(&cmd->cmd_ext_arqhandle);
4007 4009 cmd->cmd_ext_arqhandle = NULL;
4008 4010 }
4009 4011 if (cmd->cmd_ext_arq_buf)
4010 4012 scsi_free_consistent_buf(cmd->cmd_ext_arq_buf);
4011 4013 }
4012 4014 if (cmd->cmd_flags & CFLAG_PRIVEXTERN) {
4013 4015 kmem_free(cmd->cmd_pkt->pkt_private, (size_t)cmd->cmd_privlen);
4014 4016 }
4015 4017 cmd->cmd_flags = CFLAG_FREE;
4016 4018 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd);
4017 4019 }
4018 4020
4019 4021 /*
4020 4022 * tran_sync_pkt(9E) - explicit DMA synchronization
4021 4023 */
4022 4024 /*ARGSUSED*/
4023 4025 static void
4024 4026 mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
4025 4027 {
4026 4028 mptsas_cmd_t *cmd = PKT2CMD(pkt);
4027 4029
4028 4030 NDBG3(("mptsas_scsi_sync_pkt: target=%d, pkt=0x%p",
4029 4031 ap->a_target, (void *)pkt));
4030 4032
4031 4033 if (cmd->cmd_dmahandle) {
4032 4034 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
4033 4035 (cmd->cmd_flags & CFLAG_DMASEND) ?
4034 4036 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU);
4035 4037 }
4036 4038 }
4037 4039
4038 4040 /*
4039 4041 * tran_dmafree(9E) - deallocate DMA resources allocated for command
4040 4042 */
4041 4043 /*ARGSUSED*/
4042 4044 static void
4043 4045 mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt)
4044 4046 {
4045 4047 mptsas_cmd_t *cmd = PKT2CMD(pkt);
4046 4048 mptsas_t *mpt = ADDR2MPT(ap);
4047 4049
4048 4050 NDBG3(("mptsas_scsi_dmafree: target=%d pkt=0x%p",
4049 4051 ap->a_target, (void *)pkt));
4050 4052
4051 4053 if (cmd->cmd_flags & CFLAG_DMAVALID) {
4052 4054 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle);
4053 4055 cmd->cmd_flags &= ~CFLAG_DMAVALID;
4054 4056 }
4055 4057
4056 4058 if (cmd->cmd_flags & CFLAG_EXTARQBUFVALID) {
4057 4059 (void) ddi_dma_unbind_handle(cmd->cmd_ext_arqhandle);
4058 4060 cmd->cmd_flags &= ~CFLAG_EXTARQBUFVALID;
4059 4061 }
4060 4062
4061 4063 mptsas_free_extra_sgl_frame(mpt, cmd);
4062 4064 }
4063 4065
4064 4066 static void
4065 4067 mptsas_pkt_comp(struct scsi_pkt *pkt, mptsas_cmd_t *cmd)
4066 4068 {
4067 4069 if ((cmd->cmd_flags & CFLAG_CMDIOPB) &&
4068 4070 (!(cmd->cmd_flags & CFLAG_DMASEND))) {
4069 4071 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
4070 4072 DDI_DMA_SYNC_FORCPU);
4071 4073 }
4072 4074 (*pkt->pkt_comp)(pkt);
4073 4075 }
4074 4076
4075 4077 static void
4076 4078 mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, uint32_t *control,
4077 4079 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl)
4078 4080 {
4079 4081 uint_t cookiec;
4080 4082 mptti_t *dmap;
4081 4083 uint32_t flags;
4082 4084 pMpi2SGESimple64_t sge;
4083 4085 pMpi2SGEChain64_t sgechain;
4084 4086 ASSERT(cmd->cmd_flags & CFLAG_DMAVALID);
4085 4087
4086 4088 /*
4087 4089 * Save the number of entries in the DMA
4088 4090 * Scatter/Gather list
4089 4091 */
4090 4092 cookiec = cmd->cmd_cookiec;
4091 4093
4092 4094 NDBG1(("mptsas_sge_setup: cookiec=%d", cookiec));
4093 4095
4094 4096 /*
4095 4097 * Set read/write bit in control.
4096 4098 */
4097 4099 if (cmd->cmd_flags & CFLAG_DMASEND) {
4098 4100 *control |= MPI2_SCSIIO_CONTROL_WRITE;
4099 4101 } else {
4100 4102 *control |= MPI2_SCSIIO_CONTROL_READ;
4101 4103 }
4102 4104
4103 4105 ddi_put32(acc_hdl, &frame->DataLength, cmd->cmd_dmacount);
4104 4106
4105 4107 /*
4106 4108 * We have 2 cases here. First where we can fit all the
4107 4109 * SG elements into the main frame, and the case
4108 4110 * where we can't.
4109 4111 * If we have more cookies than we can attach to a frame
4110 4112 * we will need to use a chain element to point
4111 4113 * a location of memory where the rest of the S/G
4112 4114 * elements reside.
4113 4115 */
4114 4116 if (cookiec <= MPTSAS_MAX_FRAME_SGES64(mpt)) {
4115 4117 dmap = cmd->cmd_sg;
4116 4118 sge = (pMpi2SGESimple64_t)(&frame->SGL);
4117 4119 while (cookiec--) {
4118 4120 ddi_put32(acc_hdl,
4119 4121 &sge->Address.Low, dmap->addr.address64.Low);
4120 4122 ddi_put32(acc_hdl,
4121 4123 &sge->Address.High, dmap->addr.address64.High);
4122 4124 ddi_put32(acc_hdl, &sge->FlagsLength,
4123 4125 dmap->count);
4124 4126 flags = ddi_get32(acc_hdl, &sge->FlagsLength);
4125 4127 flags |= ((uint32_t)
4126 4128 (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4127 4129 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4128 4130 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4129 4131 MPI2_SGE_FLAGS_SHIFT);
4130 4132
4131 4133 /*
4132 4134 * If this is the last cookie, we set the flags
4133 4135 * to indicate so
4134 4136 */
4135 4137 if (cookiec == 0) {
4136 4138 flags |=
4137 4139 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT
4138 4140 | MPI2_SGE_FLAGS_END_OF_BUFFER
4139 4141 | MPI2_SGE_FLAGS_END_OF_LIST) <<
4140 4142 MPI2_SGE_FLAGS_SHIFT);
4141 4143 }
4142 4144 if (cmd->cmd_flags & CFLAG_DMASEND) {
4143 4145 flags |= (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4144 4146 MPI2_SGE_FLAGS_SHIFT);
4145 4147 } else {
4146 4148 flags |= (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4147 4149 MPI2_SGE_FLAGS_SHIFT);
4148 4150 }
4149 4151 ddi_put32(acc_hdl, &sge->FlagsLength, flags);
4150 4152 dmap++;
4151 4153 sge++;
4152 4154 }
4153 4155 } else {
4154 4156 /*
4155 4157 * Hereby we start to deal with multiple frames.
4156 4158 * The process is as follows:
4157 4159 * 1. Determine how many frames are needed for SGL element
4158 4160 * storage; Note that all frames are stored in contiguous
4159 4161 * memory space and in 64-bit DMA mode each element is
4160 4162 * 3 double-words (12 bytes) long.
4161 4163 * 2. Fill up the main frame. We need to do this separately
4162 4164 * since it contains the SCSI IO request header and needs
4163 4165 * dedicated processing. Note that the last 4 double-words
4164 4166 * of the SCSI IO header is for SGL element storage
4165 4167 * (MPI2_SGE_IO_UNION).
4166 4168 * 3. Fill the chain element in the main frame, so the DMA
4167 4169 * engine can use the following frames.
4168 4170 * 4. Enter a loop to fill the remaining frames. Note that the
4169 4171 * last frame contains no chain element. The remaining
4170 4172 * frames go into the mpt SGL buffer allocated on the fly,
4171 4173 * not immediately following the main message frame, as in
4172 4174 * Gen1.
4173 4175 * Some restrictions:
4174 4176 * 1. For 64-bit DMA, the simple element and chain element
4175 4177 * are both of 3 double-words (12 bytes) in size, even
4176 4178 * though all frames are stored in the first 4G of mem
4177 4179 * range and the higher 32-bits of the address are always 0.
4178 4180 * 2. On some controllers (like the 1064/1068), a frame can
4179 4181 * hold SGL elements with the last 1 or 2 double-words
4180 4182 * (4 or 8 bytes) un-used. On these controllers, we should
4181 4183 * recognize that there's not enough room for another SGL
4182 4184 * element and move the sge pointer to the next frame.
4183 4185 */
4184 4186 int i, j, k, l, frames, sgemax;
4185 4187 int temp;
4186 4188 uint8_t chainflags;
4187 4189 uint16_t chainlength;
4188 4190 mptsas_cache_frames_t *p;
4189 4191
4190 4192 /*
4191 4193 * Sgemax is the number of SGE's that will fit
4192 4194 * each extra frame and frames is total
4193 4195 * number of frames we'll need. 1 sge entry per
4194 4196 * frame is reseverd for the chain element thus the -1 below.
4195 4197 */
4196 4198 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_SGE_SIMPLE64))
4197 4199 - 1);
4198 4200 temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax;
4199 4201
4200 4202 /*
4201 4203 * A little check to see if we need to round up the number
4202 4204 * of frames we need
4203 4205 */
4204 4206 if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp *
4205 4207 sgemax) > 1) {
4206 4208 frames = (temp + 1);
4207 4209 } else {
4208 4210 frames = temp;
4209 4211 }
4210 4212 dmap = cmd->cmd_sg;
4211 4213 sge = (pMpi2SGESimple64_t)(&frame->SGL);
4212 4214
4213 4215 /*
4214 4216 * First fill in the main frame
4215 4217 */
4216 4218 for (j = 1; j < MPTSAS_MAX_FRAME_SGES64(mpt); j++) {
4217 4219 ddi_put32(acc_hdl, &sge->Address.Low,
4218 4220 dmap->addr.address64.Low);
4219 4221 ddi_put32(acc_hdl, &sge->Address.High,
4220 4222 dmap->addr.address64.High);
4221 4223 ddi_put32(acc_hdl, &sge->FlagsLength, dmap->count);
4222 4224 flags = ddi_get32(acc_hdl, &sge->FlagsLength);
4223 4225 flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4224 4226 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4225 4227 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4226 4228 MPI2_SGE_FLAGS_SHIFT);
4227 4229
4228 4230 /*
4229 4231 * If this is the last SGE of this frame
4230 4232 * we set the end of list flag
4231 4233 */
4232 4234 if (j == (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) {
4233 4235 flags |= ((uint32_t)
4234 4236 (MPI2_SGE_FLAGS_LAST_ELEMENT) <<
4235 4237 MPI2_SGE_FLAGS_SHIFT);
4236 4238 }
4237 4239 if (cmd->cmd_flags & CFLAG_DMASEND) {
4238 4240 flags |=
4239 4241 (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4240 4242 MPI2_SGE_FLAGS_SHIFT);
4241 4243 } else {
4242 4244 flags |=
4243 4245 (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4244 4246 MPI2_SGE_FLAGS_SHIFT);
4245 4247 }
4246 4248 ddi_put32(acc_hdl, &sge->FlagsLength, flags);
4247 4249 dmap++;
4248 4250 sge++;
4249 4251 }
4250 4252
4251 4253 /*
4252 4254 * Fill in the chain element in the main frame.
4253 4255 * About calculation on ChainOffset:
4254 4256 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes)
4255 4257 * in the end reserved for SGL element storage
4256 4258 * (MPI2_SGE_IO_UNION); we should count it in our
4257 4259 * calculation. See its definition in the header file.
4258 4260 * 2. Constant j is the counter of the current SGL element
4259 4261 * that will be processed, and (j - 1) is the number of
4260 4262 * SGL elements that have been processed (stored in the
4261 4263 * main frame).
4262 4264 * 3. ChainOffset value should be in units of double-words (4
4263 4265 * bytes) so the last value should be divided by 4.
4264 4266 */
4265 4267 ddi_put8(acc_hdl, &frame->ChainOffset,
4266 4268 (sizeof (MPI2_SCSI_IO_REQUEST) -
4267 4269 sizeof (MPI2_SGE_IO_UNION) +
4268 4270 (j - 1) * sizeof (MPI2_SGE_SIMPLE64)) >> 2);
4269 4271 sgechain = (pMpi2SGEChain64_t)sge;
4270 4272 chainflags = (MPI2_SGE_FLAGS_CHAIN_ELEMENT |
4271 4273 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4272 4274 MPI2_SGE_FLAGS_64_BIT_ADDRESSING);
4273 4275 ddi_put8(acc_hdl, &sgechain->Flags, chainflags);
4274 4276
4275 4277 /*
4276 4278 * The size of the next frame is the accurate size of space
4277 4279 * (in bytes) used to store the SGL elements. j is the counter
4278 4280 * of SGL elements. (j - 1) is the number of SGL elements that
4279 4281 * have been processed (stored in frames).
4280 4282 */
4281 4283 if (frames >= 2) {
4282 4284 chainlength = mpt->m_req_frame_size /
4283 4285 sizeof (MPI2_SGE_SIMPLE64) *
4284 4286 sizeof (MPI2_SGE_SIMPLE64);
4285 4287 } else {
4286 4288 chainlength = ((cookiec - (j - 1)) *
4287 4289 sizeof (MPI2_SGE_SIMPLE64));
4288 4290 }
4289 4291
4290 4292 p = cmd->cmd_extra_frames;
4291 4293
4292 4294 ddi_put16(acc_hdl, &sgechain->Length, chainlength);
4293 4295 ddi_put32(acc_hdl, &sgechain->Address.Low,
4294 4296 p->m_phys_addr);
4295 4297 /* SGL is allocated in the first 4G mem range */
4296 4298 ddi_put32(acc_hdl, &sgechain->Address.High, 0);
4297 4299
4298 4300 /*
4299 4301 * If there are more than 2 frames left we have to
4300 4302 * fill in the next chain offset to the location of
4301 4303 * the chain element in the next frame.
4302 4304 * sgemax is the number of simple elements in an extra
4303 4305 * frame. Note that the value NextChainOffset should be
4304 4306 * in double-words (4 bytes).
4305 4307 */
4306 4308 if (frames >= 2) {
4307 4309 ddi_put8(acc_hdl, &sgechain->NextChainOffset,
4308 4310 (sgemax * sizeof (MPI2_SGE_SIMPLE64)) >> 2);
4309 4311 } else {
4310 4312 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 0);
4311 4313 }
4312 4314
4313 4315 /*
4314 4316 * Jump to next frame;
4315 4317 * Starting here, chain buffers go into the per command SGL.
4316 4318 * This buffer is allocated when chain buffers are needed.
4317 4319 */
4318 4320 sge = (pMpi2SGESimple64_t)p->m_frames_addr;
4319 4321 i = cookiec;
4320 4322
4321 4323 /*
4322 4324 * Start filling in frames with SGE's. If we
4323 4325 * reach the end of frame and still have SGE's
4324 4326 * to fill we need to add a chain element and
4325 4327 * use another frame. j will be our counter
4326 4328 * for what cookie we are at and i will be
4327 4329 * the total cookiec. k is the current frame
4328 4330 */
4329 4331 for (k = 1; k <= frames; k++) {
4330 4332 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) {
4331 4333
4332 4334 /*
4333 4335 * If we have reached the end of frame
4334 4336 * and we have more SGE's to fill in
4335 4337 * we have to fill the final entry
4336 4338 * with a chain element and then
4337 4339 * continue to the next frame
4338 4340 */
4339 4341 if ((l == (sgemax + 1)) && (k != frames)) {
4340 4342 sgechain = (pMpi2SGEChain64_t)sge;
4341 4343 j--;
4342 4344 chainflags = (
4343 4345 MPI2_SGE_FLAGS_CHAIN_ELEMENT |
4344 4346 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4345 4347 MPI2_SGE_FLAGS_64_BIT_ADDRESSING);
4346 4348 ddi_put8(p->m_acc_hdl,
4347 4349 &sgechain->Flags, chainflags);
4348 4350 /*
4349 4351 * k is the frame counter and (k + 1)
4350 4352 * is the number of the next frame.
4351 4353 * Note that frames are in contiguous
4352 4354 * memory space.
4353 4355 */
4354 4356 ddi_put32(p->m_acc_hdl,
4355 4357 &sgechain->Address.Low,
4356 4358 (p->m_phys_addr +
4357 4359 (mpt->m_req_frame_size * k)));
4358 4360 ddi_put32(p->m_acc_hdl,
4359 4361 &sgechain->Address.High, 0);
4360 4362
4361 4363 /*
4362 4364 * If there are more than 2 frames left
4363 4365 * we have to next chain offset to
4364 4366 * the location of the chain element
4365 4367 * in the next frame and fill in the
4366 4368 * length of the next chain
4367 4369 */
4368 4370 if ((frames - k) >= 2) {
4369 4371 ddi_put8(p->m_acc_hdl,
4370 4372 &sgechain->NextChainOffset,
4371 4373 (sgemax *
4372 4374 sizeof (MPI2_SGE_SIMPLE64))
4373 4375 >> 2);
4374 4376 ddi_put16(p->m_acc_hdl,
4375 4377 &sgechain->Length,
4376 4378 mpt->m_req_frame_size /
4377 4379 sizeof (MPI2_SGE_SIMPLE64) *
4378 4380 sizeof (MPI2_SGE_SIMPLE64));
4379 4381 } else {
4380 4382 /*
4381 4383 * This is the last frame. Set
4382 4384 * the NextChainOffset to 0 and
4383 4385 * Length is the total size of
4384 4386 * all remaining simple elements
4385 4387 */
4386 4388 ddi_put8(p->m_acc_hdl,
4387 4389 &sgechain->NextChainOffset,
4388 4390 0);
4389 4391 ddi_put16(p->m_acc_hdl,
4390 4392 &sgechain->Length,
4391 4393 (cookiec - j) *
4392 4394 sizeof (MPI2_SGE_SIMPLE64));
4393 4395 }
4394 4396
4395 4397 /* Jump to the next frame */
4396 4398 sge = (pMpi2SGESimple64_t)
4397 4399 ((char *)p->m_frames_addr +
4398 4400 (int)mpt->m_req_frame_size * k);
4399 4401
4400 4402 continue;
4401 4403 }
4402 4404
4403 4405 ddi_put32(p->m_acc_hdl,
4404 4406 &sge->Address.Low,
4405 4407 dmap->addr.address64.Low);
4406 4408 ddi_put32(p->m_acc_hdl,
4407 4409 &sge->Address.High,
4408 4410 dmap->addr.address64.High);
4409 4411 ddi_put32(p->m_acc_hdl,
4410 4412 &sge->FlagsLength, dmap->count);
4411 4413 flags = ddi_get32(p->m_acc_hdl,
4412 4414 &sge->FlagsLength);
4413 4415 flags |= ((uint32_t)(
4414 4416 MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4415 4417 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4416 4418 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4417 4419 MPI2_SGE_FLAGS_SHIFT);
4418 4420
4419 4421 /*
4420 4422 * If we are at the end of the frame and
4421 4423 * there is another frame to fill in
4422 4424 * we set the last simple element as last
4423 4425 * element
4424 4426 */
4425 4427 if ((l == sgemax) && (k != frames)) {
4426 4428 flags |= ((uint32_t)
4427 4429 (MPI2_SGE_FLAGS_LAST_ELEMENT) <<
4428 4430 MPI2_SGE_FLAGS_SHIFT);
4429 4431 }
4430 4432
4431 4433 /*
4432 4434 * If this is the final cookie we
4433 4435 * indicate it by setting the flags
4434 4436 */
4435 4437 if (j == i) {
4436 4438 flags |= ((uint32_t)
4437 4439 (MPI2_SGE_FLAGS_LAST_ELEMENT |
4438 4440 MPI2_SGE_FLAGS_END_OF_BUFFER |
4439 4441 MPI2_SGE_FLAGS_END_OF_LIST) <<
4440 4442 MPI2_SGE_FLAGS_SHIFT);
4441 4443 }
4442 4444 if (cmd->cmd_flags & CFLAG_DMASEND) {
4443 4445 flags |=
4444 4446 (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4445 4447 MPI2_SGE_FLAGS_SHIFT);
4446 4448 } else {
4447 4449 flags |=
4448 4450 (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4449 4451 MPI2_SGE_FLAGS_SHIFT);
4450 4452 }
4451 4453 ddi_put32(p->m_acc_hdl,
4452 4454 &sge->FlagsLength, flags);
4453 4455 dmap++;
4454 4456 sge++;
4455 4457 }
4456 4458 }
4457 4459
4458 4460 /*
4459 4461 * Sync DMA with the chain buffers that were just created
4460 4462 */
4461 4463 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
4462 4464 }
4463 4465 }
4464 4466
4465 4467 /*
4466 4468 * Interrupt handling
4467 4469 * Utility routine. Poll for status of a command sent to HBA
4468 4470 * without interrupts (a FLAG_NOINTR command).
4469 4471 */
4470 4472 int
4471 4473 mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime)
4472 4474 {
4473 4475 int rval = TRUE;
4474 4476
4475 4477 NDBG5(("mptsas_poll: cmd=0x%p", (void *)poll_cmd));
4476 4478
4477 4479 /*
4478 4480 * In order to avoid using m_mutex in ISR(a new separate mutex
4479 4481 * m_intr_mutex is introduced) and keep the same lock logic,
4480 4482 * the m_intr_mutex should be used to protect the getting and
4481 4483 * setting of the ReplyDescriptorIndex.
4482 4484 *
4483 4485 * Since the m_intr_mutex would be released during processing the poll
4484 4486 * cmd, so we should set the poll flag earlier here to make sure the
4485 4487 * polled cmd be handled in this thread/context. A side effect is other
4486 4488 * cmds during the period between the flag set and reset are also
4487 4489 * handled in this thread and not the ISR. Since the poll cmd is not
4488 4490 * so common, so the performance degradation in this case is not a big
4489 4491 * issue.
4490 4492 */
4491 4493 mutex_enter(&mpt->m_intr_mutex);
4492 4494 mpt->m_polled_intr = 1;
4493 4495 mutex_exit(&mpt->m_intr_mutex);
4494 4496
4495 4497 if ((poll_cmd->cmd_flags & CFLAG_TM_CMD) == 0) {
4496 4498 mptsas_restart_hba(mpt);
4497 4499 }
4498 4500
4499 4501 /*
4500 4502 * Wait, using drv_usecwait(), long enough for the command to
4501 4503 * reasonably return from the target if the target isn't
4502 4504 * "dead". A polled command may well be sent from scsi_poll, and
4503 4505 * there are retries built in to scsi_poll if the transport
4504 4506 * accepted the packet (TRAN_ACCEPT). scsi_poll waits 1 second
4505 4507 * and retries the transport up to scsi_poll_busycnt times
4506 4508 * (currently 60) if
4507 4509 * 1. pkt_reason is CMD_INCOMPLETE and pkt_state is 0, or
4508 4510 * 2. pkt_reason is CMD_CMPLT and *pkt_scbp has STATUS_BUSY
4509 4511 *
4510 4512 * limit the waiting to avoid a hang in the event that the
4511 4513 * cmd never gets started but we are still receiving interrupts
4512 4514 */
4513 4515 while (!(poll_cmd->cmd_flags & CFLAG_FINISHED)) {
4514 4516 if (mptsas_wait_intr(mpt, polltime) == FALSE) {
4515 4517 NDBG5(("mptsas_poll: command incomplete"));
4516 4518 rval = FALSE;
4517 4519 break;
4518 4520 }
4519 4521 }
4520 4522
4521 4523 mutex_enter(&mpt->m_intr_mutex);
4522 4524 mpt->m_polled_intr = 0;
4523 4525 mutex_exit(&mpt->m_intr_mutex);
4524 4526
4525 4527 if (rval == FALSE) {
4526 4528
4527 4529 /*
4528 4530 * this isn't supposed to happen, the hba must be wedged
4529 4531 * Mark this cmd as a timeout.
4530 4532 */
4531 4533 mptsas_set_pkt_reason(mpt, poll_cmd, CMD_TIMEOUT,
4532 4534 (STAT_TIMEOUT|STAT_ABORTED));
4533 4535
4534 4536 if (poll_cmd->cmd_queued == FALSE) {
4535 4537
4536 4538 NDBG5(("mptsas_poll: not on waitq"));
4537 4539
4538 4540 poll_cmd->cmd_pkt->pkt_state |=
4539 4541 (STATE_GOT_BUS|STATE_GOT_TARGET|STATE_SENT_CMD);
4540 4542 } else {
4541 4543
4542 4544 /* find and remove it from the waitq */
4543 4545 NDBG5(("mptsas_poll: delete from waitq"));
4544 4546 mptsas_waitq_delete(mpt, poll_cmd);
4545 4547 }
4546 4548
4547 4549 }
4548 4550 mptsas_fma_check(mpt, poll_cmd);
4549 4551 NDBG5(("mptsas_poll: done"));
4550 4552 return (rval);
4551 4553 }
4552 4554
4553 4555 /*
4554 4556 * Used for polling cmds and TM function
4555 4557 */
4556 4558 static int
4557 4559 mptsas_wait_intr(mptsas_t *mpt, int polltime)
4558 4560 {
4559 4561 int cnt;
4560 4562 pMpi2ReplyDescriptorsUnion_t reply_desc_union;
4561 4563 Mpi2ReplyDescriptorsUnion_t reply_desc_union_v;
4562 4564 uint32_t int_mask;
4563 4565 uint8_t reply_type;
4564 4566
4565 4567 NDBG5(("mptsas_wait_intr"));
4566 4568
4567 4569
4568 4570 /*
4569 4571 * Get the current interrupt mask and disable interrupts. When
4570 4572 * re-enabling ints, set mask to saved value.
4571 4573 */
4572 4574 int_mask = ddi_get32(mpt->m_datap, &mpt->m_reg->HostInterruptMask);
4573 4575 MPTSAS_DISABLE_INTR(mpt);
4574 4576
4575 4577 /*
4576 4578 * Keep polling for at least (polltime * 1000) seconds
4577 4579 */
4578 4580 for (cnt = 0; cnt < polltime; cnt++) {
4579 4581 mutex_enter(&mpt->m_intr_mutex);
4580 4582 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
4581 4583 DDI_DMA_SYNC_FORCPU);
4582 4584
4583 4585 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t)
4584 4586 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index);
4585 4587
4586 4588 if (ddi_get32(mpt->m_acc_post_queue_hdl,
4587 4589 &reply_desc_union->Words.Low) == 0xFFFFFFFF ||
4588 4590 ddi_get32(mpt->m_acc_post_queue_hdl,
4589 4591 &reply_desc_union->Words.High) == 0xFFFFFFFF) {
4590 4592 mutex_exit(&mpt->m_intr_mutex);
4591 4593 drv_usecwait(1000);
4592 4594 continue;
4593 4595 }
4594 4596
4595 4597 reply_type = ddi_get8(mpt->m_acc_post_queue_hdl,
4596 4598 &reply_desc_union->Default.ReplyFlags);
4597 4599 reply_type &= MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
4598 4600 reply_desc_union_v.Default.ReplyFlags = reply_type;
4599 4601 if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
4600 4602 reply_desc_union_v.SCSIIOSuccess.SMID =
4601 4603 ddi_get16(mpt->m_acc_post_queue_hdl,
4602 4604 &reply_desc_union->SCSIIOSuccess.SMID);
4603 4605 } else if (reply_type ==
4604 4606 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
4605 4607 reply_desc_union_v.AddressReply.ReplyFrameAddress =
4606 4608 ddi_get32(mpt->m_acc_post_queue_hdl,
4607 4609 &reply_desc_union->AddressReply.ReplyFrameAddress);
4608 4610 reply_desc_union_v.AddressReply.SMID =
4609 4611 ddi_get16(mpt->m_acc_post_queue_hdl,
4610 4612 &reply_desc_union->AddressReply.SMID);
4611 4613 }
4612 4614 /*
4613 4615 * Clear the reply descriptor for re-use and increment
4614 4616 * index.
4615 4617 */
4616 4618 ddi_put64(mpt->m_acc_post_queue_hdl,
4617 4619 &((uint64_t *)(void *)mpt->m_post_queue)[mpt->m_post_index],
4618 4620 0xFFFFFFFFFFFFFFFF);
4619 4621 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
4620 4622 DDI_DMA_SYNC_FORDEV);
4621 4623
4622 4624 if (++mpt->m_post_index == mpt->m_post_queue_depth) {
4623 4625 mpt->m_post_index = 0;
4624 4626 }
4625 4627
4626 4628 /*
4627 4629 * Update the global reply index
4628 4630 */
4629 4631 ddi_put32(mpt->m_datap,
4630 4632 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index);
4631 4633 mutex_exit(&mpt->m_intr_mutex);
4632 4634
4633 4635 /*
4634 4636 * The reply is valid, process it according to its
4635 4637 * type.
4636 4638 */
4637 4639 mptsas_process_intr(mpt, &reply_desc_union_v);
4638 4640
4639 4641
4640 4642 /*
4641 4643 * Re-enable interrupts and quit.
4642 4644 */
4643 4645 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask,
4644 4646 int_mask);
4645 4647 return (TRUE);
4646 4648
4647 4649 }
4648 4650
4649 4651 /*
4650 4652 * Clear polling flag, re-enable interrupts and quit.
4651 4653 */
4652 4654 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, int_mask);
4653 4655 return (FALSE);
4654 4656 }
4655 4657
4656 4658 /*
4657 4659 * For fastpath, the m_intr_mutex should be held from the begining to the end,
4658 4660 * so we only treat those cmds that need not release m_intr_mutex(even just for
4659 4661 * a moment) as candidate for fast processing. otherwise, we don't handle them
4660 4662 * and just return, then in ISR, those cmds would be handled later with m_mutex
4661 4663 * held and m_intr_mutex not held.
4662 4664 */
4663 4665 static int
4664 4666 mptsas_handle_io_fastpath(mptsas_t *mpt,
4665 4667 uint16_t SMID)
4666 4668 {
4667 4669 mptsas_slots_t *slots = mpt->m_active;
4668 4670 mptsas_cmd_t *cmd = NULL;
4669 4671 struct scsi_pkt *pkt;
4670 4672
4671 4673 /*
4672 4674 * This is a success reply so just complete the IO. First, do a sanity
4673 4675 * check on the SMID. The final slot is used for TM requests, which
4674 4676 * would not come into this reply handler.
4675 4677 */
4676 4678 if ((SMID == 0) || (SMID > slots->m_n_slots)) {
4677 4679 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of %d\n",
4678 4680 SMID);
4679 4681 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
4680 4682 return (TRUE);
4681 4683 }
4682 4684
4683 4685 cmd = slots->m_slot[SMID];
4684 4686
4685 4687 /*
4686 4688 * print warning and return if the slot is empty
4687 4689 */
4688 4690 if (cmd == NULL) {
4689 4691 mptsas_log(mpt, CE_WARN, "?NULL command for successful SCSI IO "
4690 4692 "in slot %d", SMID);
4691 4693 return (TRUE);
4692 4694 }
4693 4695
4694 4696 pkt = CMD2PKT(cmd);
4695 4697 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | STATE_SENT_CMD |
4696 4698 STATE_GOT_STATUS);
4697 4699 if (cmd->cmd_flags & CFLAG_DMAVALID) {
4698 4700 pkt->pkt_state |= STATE_XFERRED_DATA;
4699 4701 }
4700 4702 pkt->pkt_resid = 0;
4701 4703
4702 4704 /*
4703 4705 * If the cmd is a IOC, or a passthrough, then we don't process it in
4704 4706 * fastpath, and later it would be handled by mptsas_process_intr()
4705 4707 * with m_mutex protected.
4706 4708 */
4707 4709 if (cmd->cmd_flags & (CFLAG_PASSTHRU | CFLAG_CMDIOC)) {
4708 4710 return (FALSE);
4709 4711 } else {
4710 4712 mptsas_remove_cmd0(mpt, cmd);
4711 4713 }
4712 4714
4713 4715 if (cmd->cmd_flags & CFLAG_RETRY) {
4714 4716 /*
4715 4717 * The target returned QFULL or busy, do not add tihs
4716 4718 * pkt to the doneq since the hba will retry
4717 4719 * this cmd.
4718 4720 *
4719 4721 * The pkt has already been resubmitted in
4720 4722 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error().
4721 4723 * Remove this cmd_flag here.
4722 4724 */
4723 4725 cmd->cmd_flags &= ~CFLAG_RETRY;
4724 4726 } else {
4725 4727 mptsas_doneq_add0(mpt, cmd);
4726 4728 }
4727 4729
4728 4730 /*
4729 4731 * In fastpath, the cmd should only be a context reply, so just check
4730 4732 * the post queue of the reply descriptor and the dmahandle of the cmd
4731 4733 * is enough. No sense data in this case and no need to check the dma
4732 4734 * handle where sense data dma info is saved, the dma handle of the
4733 4735 * reply frame, and the dma handle of the reply free queue.
4734 4736 * For the dma handle of the request queue. Check fma here since we
4735 4737 * are sure the request must have already been sent/DMAed correctly.
4736 4738 * otherwise checking in mptsas_scsi_start() is not correct since
4737 4739 * at that time the dma may not start.
4738 4740 */
4739 4741 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
4740 4742 DDI_SUCCESS) ||
4741 4743 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) !=
4742 4744 DDI_SUCCESS)) {
4743 4745 ddi_fm_service_impact(mpt->m_dip,
4744 4746 DDI_SERVICE_UNAFFECTED);
4745 4747 pkt->pkt_reason = CMD_TRAN_ERR;
4746 4748 pkt->pkt_statistics = 0;
4747 4749 }
4748 4750 if (cmd->cmd_dmahandle &&
4749 4751 (mptsas_check_dma_handle(cmd->cmd_dmahandle) != DDI_SUCCESS)) {
4750 4752 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
4751 4753 pkt->pkt_reason = CMD_TRAN_ERR;
4752 4754 pkt->pkt_statistics = 0;
4753 4755 }
4754 4756 if ((cmd->cmd_extra_frames &&
4755 4757 ((mptsas_check_dma_handle(cmd->cmd_extra_frames->m_dma_hdl) !=
4756 4758 DDI_SUCCESS) ||
4757 4759 (mptsas_check_acc_handle(cmd->cmd_extra_frames->m_acc_hdl) !=
4758 4760 DDI_SUCCESS)))) {
4759 4761 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
4760 4762 pkt->pkt_reason = CMD_TRAN_ERR;
4761 4763 pkt->pkt_statistics = 0;
4762 4764 }
4763 4765
4764 4766 return (TRUE);
4765 4767 }
4766 4768
4767 4769 static void
4768 4770 mptsas_handle_scsi_io_success(mptsas_t *mpt,
4769 4771 pMpi2ReplyDescriptorsUnion_t reply_desc)
4770 4772 {
4771 4773 pMpi2SCSIIOSuccessReplyDescriptor_t scsi_io_success;
4772 4774 uint16_t SMID;
4773 4775 mptsas_slots_t *slots = mpt->m_active;
4774 4776 mptsas_cmd_t *cmd = NULL;
4775 4777 struct scsi_pkt *pkt;
4776 4778
4777 4779 scsi_io_success = (pMpi2SCSIIOSuccessReplyDescriptor_t)reply_desc;
4778 4780 SMID = scsi_io_success->SMID;
4779 4781
4780 4782 /*
4781 4783 * This is a success reply so just complete the IO. First, do a sanity
4782 4784 * check on the SMID. The final slot is used for TM requests, which
4783 4785 * would not come into this reply handler.
4784 4786 */
4785 4787 if ((SMID == 0) || (SMID > slots->m_n_slots)) {
4786 4788 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of %d\n",
4787 4789 SMID);
4788 4790 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
4789 4791 return;
4790 4792 }
4791 4793
4792 4794 cmd = slots->m_slot[SMID];
4793 4795
4794 4796 /*
4795 4797 * print warning and return if the slot is empty
4796 4798 */
4797 4799 if (cmd == NULL) {
4798 4800 mptsas_log(mpt, CE_WARN, "?NULL command for successful SCSI IO "
4799 4801 "in slot %d", SMID);
4800 4802 return;
4801 4803 }
4802 4804
4803 4805 pkt = CMD2PKT(cmd);
4804 4806 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | STATE_SENT_CMD |
4805 4807 STATE_GOT_STATUS);
4806 4808 if (cmd->cmd_flags & CFLAG_DMAVALID) {
4807 4809 pkt->pkt_state |= STATE_XFERRED_DATA;
4808 4810 }
4809 4811 pkt->pkt_resid = 0;
4810 4812
4811 4813 if (cmd->cmd_flags & CFLAG_PASSTHRU) {
4812 4814 cmd->cmd_flags |= CFLAG_FINISHED;
4813 4815 cv_broadcast(&mpt->m_passthru_cv);
4814 4816 return;
4815 4817 } else {
4816 4818 mptsas_remove_cmd(mpt, cmd);
4817 4819 }
4818 4820
4819 4821 if (cmd->cmd_flags & CFLAG_RETRY) {
4820 4822 /*
4821 4823 * The target returned QFULL or busy, do not add tihs
4822 4824 * pkt to the doneq since the hba will retry
4823 4825 * this cmd.
4824 4826 *
4825 4827 * The pkt has already been resubmitted in
4826 4828 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error().
4827 4829 * Remove this cmd_flag here.
4828 4830 */
4829 4831 cmd->cmd_flags &= ~CFLAG_RETRY;
4830 4832 } else {
4831 4833 mptsas_doneq_add(mpt, cmd);
4832 4834 }
4833 4835 }
4834 4836
4835 4837 static void
4836 4838 mptsas_handle_address_reply(mptsas_t *mpt,
4837 4839 pMpi2ReplyDescriptorsUnion_t reply_desc)
4838 4840 {
4839 4841 pMpi2AddressReplyDescriptor_t address_reply;
4840 4842 pMPI2DefaultReply_t reply;
4841 4843 mptsas_fw_diagnostic_buffer_t *pBuffer;
4842 4844 uint32_t reply_addr;
4843 4845 uint16_t SMID, iocstatus;
4844 4846 mptsas_slots_t *slots = mpt->m_active;
4845 4847 mptsas_cmd_t *cmd = NULL;
4846 4848 uint8_t function, buffer_type;
4847 4849 m_replyh_arg_t *args;
4848 4850 int reply_frame_no;
4849 4851
4850 4852 ASSERT(mutex_owned(&mpt->m_mutex));
4851 4853
4852 4854 address_reply = (pMpi2AddressReplyDescriptor_t)reply_desc;
4853 4855
4854 4856 reply_addr = address_reply->ReplyFrameAddress;
4855 4857 SMID = address_reply->SMID;
4856 4858 /*
4857 4859 * If reply frame is not in the proper range we should ignore this
4858 4860 * message and exit the interrupt handler.
4859 4861 */
4860 4862 if ((reply_addr < mpt->m_reply_frame_dma_addr) ||
4861 4863 (reply_addr >= (mpt->m_reply_frame_dma_addr +
4862 4864 (mpt->m_reply_frame_size * mpt->m_max_replies))) ||
4863 4865 ((reply_addr - mpt->m_reply_frame_dma_addr) %
4864 4866 mpt->m_reply_frame_size != 0)) {
4865 4867 mptsas_log(mpt, CE_WARN, "?Received invalid reply frame "
4866 4868 "address 0x%x\n", reply_addr);
4867 4869 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
4868 4870 return;
4869 4871 }
4870 4872
4871 4873 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
4872 4874 DDI_DMA_SYNC_FORCPU);
4873 4875 reply = (pMPI2DefaultReply_t)(mpt->m_reply_frame + (reply_addr -
4874 4876 mpt->m_reply_frame_dma_addr));
4875 4877 function = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->Function);
4876 4878
4877 4879 /*
4878 4880 * don't get slot information and command for events since these values
4879 4881 * don't exist
4880 4882 */
4881 4883 if ((function != MPI2_FUNCTION_EVENT_NOTIFICATION) &&
4882 4884 (function != MPI2_FUNCTION_DIAG_BUFFER_POST)) {
4883 4885 /*
4884 4886 * This could be a TM reply, which use the last allocated SMID,
4885 4887 * so allow for that.
4886 4888 */
4887 4889 if ((SMID == 0) || (SMID > (slots->m_n_slots + 1))) {
4888 4890 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of "
4889 4891 "%d\n", SMID);
4890 4892 ddi_fm_service_impact(mpt->m_dip,
4891 4893 DDI_SERVICE_UNAFFECTED);
4892 4894 return;
4893 4895 }
4894 4896
4895 4897 cmd = slots->m_slot[SMID];
4896 4898
4897 4899 /*
4898 4900 * print warning and return if the slot is empty
4899 4901 */
4900 4902 if (cmd == NULL) {
4901 4903 mptsas_log(mpt, CE_WARN, "?NULL command for address "
4902 4904 "reply in slot %d", SMID);
4903 4905 return;
4904 4906 }
4905 4907 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
4906 4908 (cmd->cmd_flags & CFLAG_CONFIG) ||
4907 4909 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
4908 4910 cmd->cmd_rfm = reply_addr;
4909 4911 cmd->cmd_flags |= CFLAG_FINISHED;
4910 4912 cv_broadcast(&mpt->m_passthru_cv);
4911 4913 cv_broadcast(&mpt->m_config_cv);
4912 4914 cv_broadcast(&mpt->m_fw_diag_cv);
4913 4915 return;
4914 4916 } else if (!(cmd->cmd_flags & CFLAG_FW_CMD)) {
4915 4917 mptsas_remove_cmd(mpt, cmd);
4916 4918 }
4917 4919 NDBG31(("\t\tmptsas_process_intr: slot=%d", SMID));
4918 4920 }
4919 4921 /*
4920 4922 * Depending on the function, we need to handle
4921 4923 * the reply frame (and cmd) differently.
4922 4924 */
4923 4925 switch (function) {
4924 4926 case MPI2_FUNCTION_SCSI_IO_REQUEST:
4925 4927 mptsas_check_scsi_io_error(mpt, (pMpi2SCSIIOReply_t)reply, cmd);
4926 4928 break;
4927 4929 case MPI2_FUNCTION_SCSI_TASK_MGMT:
4928 4930 cmd->cmd_rfm = reply_addr;
4929 4931 mptsas_check_task_mgt(mpt, (pMpi2SCSIManagementReply_t)reply,
4930 4932 cmd);
4931 4933 break;
4932 4934 case MPI2_FUNCTION_FW_DOWNLOAD:
4933 4935 cmd->cmd_flags |= CFLAG_FINISHED;
4934 4936 cv_signal(&mpt->m_fw_cv);
4935 4937 break;
4936 4938 case MPI2_FUNCTION_EVENT_NOTIFICATION:
4937 4939 reply_frame_no = (reply_addr - mpt->m_reply_frame_dma_addr) /
4938 4940 mpt->m_reply_frame_size;
4939 4941 args = &mpt->m_replyh_args[reply_frame_no];
4940 4942 args->mpt = (void *)mpt;
4941 4943 args->rfm = reply_addr;
4942 4944
4943 4945 /*
4944 4946 * Record the event if its type is enabled in
4945 4947 * this mpt instance by ioctl.
4946 4948 */
4947 4949 mptsas_record_event(args);
4948 4950
4949 4951 /*
4950 4952 * Handle time critical events
4951 4953 * NOT_RESPONDING/ADDED only now
4952 4954 */
4953 4955 if (mptsas_handle_event_sync(args) == DDI_SUCCESS) {
4954 4956 /*
4955 4957 * Would not return main process,
4956 4958 * just let taskq resolve ack action
4957 4959 * and ack would be sent in taskq thread
4958 4960 */
4959 4961 NDBG20(("send mptsas_handle_event_sync success"));
4960 4962 }
4961 4963 if ((ddi_taskq_dispatch(mpt->m_event_taskq, mptsas_handle_event,
4962 4964 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) {
4963 4965 mptsas_log(mpt, CE_WARN, "No memory available"
4964 4966 "for dispatch taskq");
4965 4967 /*
4966 4968 * Return the reply frame to the free queue.
4967 4969 */
4968 4970 ddi_put32(mpt->m_acc_free_queue_hdl,
4969 4971 &((uint32_t *)(void *)
4970 4972 mpt->m_free_queue)[mpt->m_free_index], reply_addr);
4971 4973 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
4972 4974 DDI_DMA_SYNC_FORDEV);
4973 4975 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
4974 4976 mpt->m_free_index = 0;
4975 4977 }
4976 4978
4977 4979 ddi_put32(mpt->m_datap,
4978 4980 &mpt->m_reg->ReplyFreeHostIndex, mpt->m_free_index);
4979 4981 }
4980 4982 return;
4981 4983 case MPI2_FUNCTION_DIAG_BUFFER_POST:
4982 4984 /*
4983 4985 * If SMID is 0, this implies that the reply is due to a
4984 4986 * release function with a status that the buffer has been
4985 4987 * released. Set the buffer flags accordingly.
4986 4988 */
4987 4989 if (SMID == 0) {
4988 4990 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
4989 4991 &reply->IOCStatus);
4990 4992 buffer_type = ddi_get8(mpt->m_acc_reply_frame_hdl,
4991 4993 &(((pMpi2DiagBufferPostReply_t)reply)->BufferType));
4992 4994 if (iocstatus == MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED) {
4993 4995 pBuffer =
4994 4996 &mpt->m_fw_diag_buffer_list[buffer_type];
4995 4997 pBuffer->valid_data = TRUE;
4996 4998 pBuffer->owned_by_firmware = FALSE;
4997 4999 pBuffer->immediate = FALSE;
4998 5000 }
4999 5001 } else {
5000 5002 /*
5001 5003 * Normal handling of diag post reply with SMID.
5002 5004 */
5003 5005 cmd = slots->m_slot[SMID];
5004 5006
5005 5007 /*
5006 5008 * print warning and return if the slot is empty
5007 5009 */
5008 5010 if (cmd == NULL) {
5009 5011 mptsas_log(mpt, CE_WARN, "?NULL command for "
5010 5012 "address reply in slot %d", SMID);
5011 5013 return;
5012 5014 }
5013 5015 cmd->cmd_rfm = reply_addr;
5014 5016 cmd->cmd_flags |= CFLAG_FINISHED;
5015 5017 cv_broadcast(&mpt->m_fw_diag_cv);
5016 5018 }
5017 5019 return;
5018 5020 default:
5019 5021 mptsas_log(mpt, CE_WARN, "Unknown function 0x%x ", function);
5020 5022 break;
5021 5023 }
5022 5024
5023 5025 /*
5024 5026 * Return the reply frame to the free queue.
5025 5027 */
5026 5028 ddi_put32(mpt->m_acc_free_queue_hdl,
5027 5029 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
5028 5030 reply_addr);
5029 5031 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
5030 5032 DDI_DMA_SYNC_FORDEV);
5031 5033 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
5032 5034 mpt->m_free_index = 0;
5033 5035 }
5034 5036 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
5035 5037 mpt->m_free_index);
5036 5038
5037 5039 if (cmd->cmd_flags & CFLAG_FW_CMD)
5038 5040 return;
5039 5041
5040 5042 if (cmd->cmd_flags & CFLAG_RETRY) {
5041 5043 /*
5042 5044 * The target returned QFULL or busy, do not add tihs
5043 5045 * pkt to the doneq since the hba will retry
5044 5046 * this cmd.
5045 5047 *
5046 5048 * The pkt has already been resubmitted in
5047 5049 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error().
5048 5050 * Remove this cmd_flag here.
5049 5051 */
5050 5052 cmd->cmd_flags &= ~CFLAG_RETRY;
5051 5053 } else {
5052 5054 mptsas_doneq_add(mpt, cmd);
5053 5055 }
5054 5056 }
5055 5057
5056 5058 static void
5057 5059 mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply,
5058 5060 mptsas_cmd_t *cmd)
5059 5061 {
5060 5062 uint8_t scsi_status, scsi_state;
5061 5063 uint16_t ioc_status;
5062 5064 uint32_t xferred, sensecount, responsedata, loginfo = 0;
5063 5065 struct scsi_pkt *pkt;
5064 5066 struct scsi_arq_status *arqstat;
5065 5067 struct buf *bp;
5066 5068 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
5067 5069 uint8_t *sensedata = NULL;
5068 5070
5069 5071 if ((cmd->cmd_flags & (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) ==
5070 5072 (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) {
5071 5073 bp = cmd->cmd_ext_arq_buf;
5072 5074 } else {
5073 5075 bp = cmd->cmd_arq_buf;
5074 5076 }
5075 5077
5076 5078 scsi_status = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIStatus);
5077 5079 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus);
5078 5080 scsi_state = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIState);
5079 5081 xferred = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->TransferCount);
5080 5082 sensecount = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->SenseCount);
5081 5083 responsedata = ddi_get32(mpt->m_acc_reply_frame_hdl,
5082 5084 &reply->ResponseInfo);
5083 5085
5084 5086 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
5085 5087 loginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
5086 5088 &reply->IOCLogInfo);
5087 5089 mptsas_log(mpt, CE_NOTE,
5088 5090 "?Log info 0x%x received for target %d.\n"
5089 5091 "\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x",
5090 5092 loginfo, Tgt(cmd), scsi_status, ioc_status,
5091 5093 scsi_state);
5092 5094 }
5093 5095
5094 5096 NDBG31(("\t\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x",
5095 5097 scsi_status, ioc_status, scsi_state));
5096 5098
5097 5099 pkt = CMD2PKT(cmd);
5098 5100 *(pkt->pkt_scbp) = scsi_status;
5099 5101
5100 5102 if (loginfo == 0x31170000) {
5101 5103 /*
5102 5104 * if loginfo PL_LOGINFO_CODE_IO_DEVICE_MISSING_DELAY_RETRY
5103 5105 * 0x31170000 comes, that means the device missing delay
5104 5106 * is in progressing, the command need retry later.
5105 5107 */
5106 5108 *(pkt->pkt_scbp) = STATUS_BUSY;
5107 5109 return;
5108 5110 }
5109 5111
5110 5112 if ((scsi_state & MPI2_SCSI_STATE_NO_SCSI_STATUS) &&
5111 5113 ((ioc_status & MPI2_IOCSTATUS_MASK) ==
5112 5114 MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE)) {
5113 5115 pkt->pkt_reason = CMD_INCOMPLETE;
5114 5116 pkt->pkt_state |= STATE_GOT_BUS;
5115 5117 mutex_enter(&ptgt->m_tgt_intr_mutex);
5116 5118 if (ptgt->m_reset_delay == 0) {
5117 5119 mptsas_set_throttle(mpt, ptgt,
5118 5120 DRAIN_THROTTLE);
5119 5121 }
5120 5122 mutex_exit(&ptgt->m_tgt_intr_mutex);
5121 5123 return;
5122 5124 }
5123 5125
5124 5126 if (scsi_state & MPI2_SCSI_STATE_RESPONSE_INFO_VALID) {
5125 5127 responsedata &= 0x000000FF;
5126 5128 if (responsedata & MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF) {
5127 5129 mptsas_log(mpt, CE_NOTE, "Do not support the TLR\n");
5128 5130 pkt->pkt_reason = CMD_TLR_OFF;
5129 5131 return;
5130 5132 }
5131 5133 }
5132 5134
5133 5135
5134 5136 switch (scsi_status) {
5135 5137 case MPI2_SCSI_STATUS_CHECK_CONDITION:
5136 5138 pkt->pkt_resid = (cmd->cmd_dmacount - xferred);
5137 5139 arqstat = (void*)(pkt->pkt_scbp);
5138 5140 arqstat->sts_rqpkt_status = *((struct scsi_status *)
5139 5141 (pkt->pkt_scbp));
5140 5142 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET |
5141 5143 STATE_SENT_CMD | STATE_GOT_STATUS | STATE_ARQ_DONE);
5142 5144 if (cmd->cmd_flags & CFLAG_XARQ) {
5143 5145 pkt->pkt_state |= STATE_XARQ_DONE;
5144 5146 }
5145 5147 if (pkt->pkt_resid != cmd->cmd_dmacount) {
5146 5148 pkt->pkt_state |= STATE_XFERRED_DATA;
5147 5149 }
5148 5150 arqstat->sts_rqpkt_reason = pkt->pkt_reason;
5149 5151 arqstat->sts_rqpkt_state = pkt->pkt_state;
5150 5152 arqstat->sts_rqpkt_state |= STATE_XFERRED_DATA;
5151 5153 arqstat->sts_rqpkt_statistics = pkt->pkt_statistics;
5152 5154 sensedata = (uint8_t *)&arqstat->sts_sensedata;
5153 5155
5154 5156 bcopy((uchar_t *)bp->b_un.b_addr, sensedata,
5155 5157 ((cmd->cmd_rqslen >= sensecount) ? sensecount :
5156 5158 cmd->cmd_rqslen));
5157 5159 arqstat->sts_rqpkt_resid = (cmd->cmd_rqslen - sensecount);
5158 5160 cmd->cmd_flags |= CFLAG_CMDARQ;
5159 5161 /*
5160 5162 * Set proper status for pkt if autosense was valid
5161 5163 */
5162 5164 if (scsi_state & MPI2_SCSI_STATE_AUTOSENSE_VALID) {
5163 5165 struct scsi_status zero_status = { 0 };
5164 5166 arqstat->sts_rqpkt_status = zero_status;
5165 5167 }
5166 5168
5167 5169 /*
5168 5170 * ASC=0x47 is parity error
5169 5171 * ASC=0x48 is initiator detected error received
5170 5172 */
5171 5173 if ((scsi_sense_key(sensedata) == KEY_ABORTED_COMMAND) &&
5172 5174 ((scsi_sense_asc(sensedata) == 0x47) ||
5173 5175 (scsi_sense_asc(sensedata) == 0x48))) {
5174 5176 mptsas_log(mpt, CE_NOTE, "Aborted_command!");
5175 5177 }
5176 5178
5177 5179 /*
5178 5180 * ASC/ASCQ=0x3F/0x0E means report_luns data changed
5179 5181 * ASC/ASCQ=0x25/0x00 means invalid lun
5180 5182 */
5181 5183 if (((scsi_sense_key(sensedata) == KEY_UNIT_ATTENTION) &&
5182 5184 (scsi_sense_asc(sensedata) == 0x3F) &&
5183 5185 (scsi_sense_ascq(sensedata) == 0x0E)) ||
5184 5186 ((scsi_sense_key(sensedata) == KEY_ILLEGAL_REQUEST) &&
5185 5187 (scsi_sense_asc(sensedata) == 0x25) &&
5186 5188 (scsi_sense_ascq(sensedata) == 0x00))) {
5187 5189 mptsas_topo_change_list_t *topo_node = NULL;
5188 5190
5189 5191 topo_node = kmem_zalloc(
5190 5192 sizeof (mptsas_topo_change_list_t),
5191 5193 KM_NOSLEEP);
5192 5194 if (topo_node == NULL) {
5193 5195 mptsas_log(mpt, CE_NOTE, "No memory"
5194 5196 "resource for handle SAS dynamic"
5195 5197 "reconfigure.\n");
5196 5198 break;
5197 5199 }
5198 5200 topo_node->mpt = mpt;
5199 5201 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_TARGET;
5200 5202 topo_node->un.phymask = ptgt->m_phymask;
5201 5203 topo_node->devhdl = ptgt->m_devhdl;
5202 5204 topo_node->object = (void *)ptgt;
5203 5205 topo_node->flags = MPTSAS_TOPO_FLAG_LUN_ASSOCIATED;
5204 5206
5205 5207 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
5206 5208 mptsas_handle_dr,
5207 5209 (void *)topo_node,
5208 5210 DDI_NOSLEEP)) != DDI_SUCCESS) {
5209 5211 mptsas_log(mpt, CE_NOTE, "mptsas start taskq"
5210 5212 "for handle SAS dynamic reconfigure"
5211 5213 "failed. \n");
5212 5214 }
5213 5215 }
5214 5216 break;
5215 5217 case MPI2_SCSI_STATUS_GOOD:
5216 5218 switch (ioc_status & MPI2_IOCSTATUS_MASK) {
5217 5219 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
5218 5220 pkt->pkt_reason = CMD_DEV_GONE;
5219 5221 pkt->pkt_state |= STATE_GOT_BUS;
5220 5222 mutex_enter(&ptgt->m_tgt_intr_mutex);
5221 5223 if (ptgt->m_reset_delay == 0) {
5222 5224 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5223 5225 }
5224 5226 mutex_exit(&ptgt->m_tgt_intr_mutex);
5225 5227 NDBG31(("lost disk for target%d, command:%x",
5226 5228 Tgt(cmd), pkt->pkt_cdbp[0]));
5227 5229 break;
5228 5230 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
5229 5231 NDBG31(("data overrun: xferred=%d", xferred));
5230 5232 NDBG31(("dmacount=%d", cmd->cmd_dmacount));
5231 5233 pkt->pkt_reason = CMD_DATA_OVR;
5232 5234 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET
5233 5235 | STATE_SENT_CMD | STATE_GOT_STATUS
5234 5236 | STATE_XFERRED_DATA);
5235 5237 pkt->pkt_resid = 0;
5236 5238 break;
5237 5239 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
5238 5240 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
5239 5241 NDBG31(("data underrun: xferred=%d", xferred));
5240 5242 NDBG31(("dmacount=%d", cmd->cmd_dmacount));
5241 5243 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET
5242 5244 | STATE_SENT_CMD | STATE_GOT_STATUS);
5243 5245 pkt->pkt_resid = (cmd->cmd_dmacount - xferred);
5244 5246 if (pkt->pkt_resid != cmd->cmd_dmacount) {
5245 5247 pkt->pkt_state |= STATE_XFERRED_DATA;
5246 5248 }
5247 5249 break;
5248 5250 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
5249 5251 mptsas_set_pkt_reason(mpt,
5250 5252 cmd, CMD_RESET, STAT_BUS_RESET);
5251 5253 break;
5252 5254 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
5253 5255 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
5254 5256 mptsas_set_pkt_reason(mpt,
5255 5257 cmd, CMD_RESET, STAT_DEV_RESET);
5256 5258 break;
5257 5259 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
5258 5260 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
5259 5261 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET);
5260 5262 mptsas_set_pkt_reason(mpt,
5261 5263 cmd, CMD_TERMINATED, STAT_TERMINATED);
5262 5264 break;
5263 5265 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
5264 5266 case MPI2_IOCSTATUS_BUSY:
5265 5267 /*
5266 5268 * set throttles to drain
5267 5269 */
5268 5270 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
5269 5271 &mpt->m_active->m_tgttbl, MPTSAS_HASH_FIRST);
5270 5272 while (ptgt != NULL) {
5271 5273 mutex_enter(&ptgt->m_tgt_intr_mutex);
5272 5274 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5273 5275 mutex_exit(&ptgt->m_tgt_intr_mutex);
5274 5276
5275 5277 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
5276 5278 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
5277 5279 }
5278 5280
5279 5281 /*
5280 5282 * retry command
5281 5283 */
5282 5284 cmd->cmd_flags |= CFLAG_RETRY;
5283 5285 cmd->cmd_pkt_flags |= FLAG_HEAD;
5284 5286
5285 5287 mutex_exit(&mpt->m_mutex);
5286 5288 (void) mptsas_accept_pkt(mpt, cmd);
5287 5289 mutex_enter(&mpt->m_mutex);
5288 5290 break;
5289 5291 default:
5290 5292 mptsas_log(mpt, CE_WARN,
5291 5293 "unknown ioc_status = %x\n", ioc_status);
5292 5294 mptsas_log(mpt, CE_CONT, "scsi_state = %x, transfer "
5293 5295 "count = %x, scsi_status = %x", scsi_state,
5294 5296 xferred, scsi_status);
5295 5297 break;
5296 5298 }
5297 5299 break;
5298 5300 case MPI2_SCSI_STATUS_TASK_SET_FULL:
5299 5301 mptsas_handle_qfull(mpt, cmd);
5300 5302 break;
5301 5303 case MPI2_SCSI_STATUS_BUSY:
5302 5304 NDBG31(("scsi_status busy received"));
5303 5305 break;
5304 5306 case MPI2_SCSI_STATUS_RESERVATION_CONFLICT:
5305 5307 NDBG31(("scsi_status reservation conflict received"));
5306 5308 break;
5307 5309 default:
5308 5310 mptsas_log(mpt, CE_WARN, "scsi_status=%x, ioc_status=%x\n",
5309 5311 scsi_status, ioc_status);
5310 5312 mptsas_log(mpt, CE_WARN,
5311 5313 "mptsas_process_intr: invalid scsi status\n");
5312 5314 break;
5313 5315 }
5314 5316 }
5315 5317
5316 5318 static void
5317 5319 mptsas_check_task_mgt(mptsas_t *mpt, pMpi2SCSIManagementReply_t reply,
5318 5320 mptsas_cmd_t *cmd)
5319 5321 {
5320 5322 uint8_t task_type;
5321 5323 uint16_t ioc_status;
5322 5324 uint32_t log_info;
5323 5325 uint16_t dev_handle;
5324 5326 struct scsi_pkt *pkt = CMD2PKT(cmd);
5325 5327
5326 5328 task_type = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->TaskType);
5327 5329 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus);
5328 5330 log_info = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->IOCLogInfo);
5329 5331 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->DevHandle);
5330 5332
5331 5333 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5332 5334 mptsas_log(mpt, CE_WARN, "mptsas_check_task_mgt: Task 0x%x "
5333 5335 "failed. IOCStatus=0x%x IOCLogInfo=0x%x target=%d\n",
5334 5336 task_type, ioc_status, log_info, dev_handle);
5335 5337 pkt->pkt_reason = CMD_INCOMPLETE;
5336 5338 return;
5337 5339 }
5338 5340
5339 5341 switch (task_type) {
5340 5342 case MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK:
5341 5343 case MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET:
5342 5344 case MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK:
5343 5345 case MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA:
5344 5346 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET:
5345 5347 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_UNIT_ATTENTION:
5346 5348 break;
5347 5349 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
5348 5350 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
5349 5351 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
5350 5352 /*
5351 5353 * Check for invalid DevHandle of 0 in case application
5352 5354 * sends bad command. DevHandle of 0 could cause problems.
5353 5355 */
5354 5356 if (dev_handle == 0) {
5355 5357 mptsas_log(mpt, CE_WARN, "!Can't flush target with"
5356 5358 " DevHandle of 0.");
5357 5359 } else {
5358 5360 mptsas_flush_target(mpt, dev_handle, Lun(cmd),
5359 5361 task_type);
5360 5362 }
5361 5363 break;
5362 5364 default:
5363 5365 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.",
5364 5366 task_type);
5365 5367 mptsas_log(mpt, CE_WARN, "ioc status = %x", ioc_status);
5366 5368 break;
5367 5369 }
5368 5370 }
5369 5371
5370 5372 static void
5371 5373 mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg)
5372 5374 {
5373 5375 mptsas_t *mpt = arg->mpt;
5374 5376 uint64_t t = arg->t;
5375 5377 mptsas_cmd_t *cmd;
5376 5378 struct scsi_pkt *pkt;
5377 5379 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
5378 5380
5379 5381 mutex_enter(&item->mutex);
5380 5382 while (item->flag & MPTSAS_DONEQ_THREAD_ACTIVE) {
5381 5383 if (!item->doneq) {
5382 5384 cv_wait(&item->cv, &item->mutex);
5383 5385 }
5384 5386 pkt = NULL;
5385 5387 if ((cmd = mptsas_doneq_thread_rm(mpt, t)) != NULL) {
5386 5388 cmd->cmd_flags |= CFLAG_COMPLETED;
5387 5389 pkt = CMD2PKT(cmd);
5388 5390 }
5389 5391 mutex_exit(&item->mutex);
5390 5392 if (pkt) {
5391 5393 mptsas_pkt_comp(pkt, cmd);
5392 5394 }
5393 5395 mutex_enter(&item->mutex);
5394 5396 }
5395 5397 mutex_exit(&item->mutex);
5396 5398 mutex_enter(&mpt->m_doneq_mutex);
5397 5399 mpt->m_doneq_thread_n--;
5398 5400 cv_broadcast(&mpt->m_doneq_thread_cv);
5399 5401 mutex_exit(&mpt->m_doneq_mutex);
5400 5402 }
5401 5403
5402 5404 /*
5403 5405 * mpt interrupt handler.
5404 5406 */
5405 5407 static uint_t
5406 5408 mptsas_intr(caddr_t arg1, caddr_t arg2)
5407 5409 {
5408 5410 mptsas_t *mpt = (void *)arg1;
5409 5411 pMpi2ReplyDescriptorsUnion_t reply_desc_union;
5410 5412 uchar_t did_reply = FALSE;
5411 5413 int i = 0, j;
5412 5414 uint8_t reply_type;
5413 5415 uint16_t SMID;
5414 5416
5415 5417 NDBG1(("mptsas_intr: arg1 0x%p arg2 0x%p", (void *)arg1, (void *)arg2));
5416 5418
5417 5419 /*
5418 5420 * 1.
5419 5421 * To avoid using m_mutex in the ISR(ISR referes not only mptsas_intr,
5420 5422 * but all of the recursive called functions in it. the same below),
5421 5423 * separate mutexs are introduced to protect the elements shown in ISR.
5422 5424 * 3 type of mutex are involved here:
5423 5425 * a)per instance mutex m_intr_mutex.
5424 5426 * b)per target mutex m_tgt_intr_mutex.
5425 5427 * c)mutex that protect the free slot.
5426 5428 *
5427 5429 * a)per instance mutex m_intr_mutex:
5428 5430 * used to protect m_options, m_power, m_waitq, etc that would be
5429 5431 * checked/modified in ISR; protect the getting and setting the reply
5430 5432 * descriptor index; protect the m_slots[];
5431 5433 *
5432 5434 * b)per target mutex m_tgt_intr_mutex:
5433 5435 * used to protect per target element which has relationship to ISR.
5434 5436 * contention for the new per target mutex is just as high as it in
5435 5437 * sd(7d) driver.
5436 5438 *
5437 5439 * c)mutexs that protect the free slots:
5438 5440 * those mutexs are introduced to minimize the mutex contentions
5439 5441 * between the IO request threads where free slots are allocated
5440 5442 * for sending cmds and ISR where slots holding outstanding cmds
5441 5443 * are returned to the free pool.
5442 5444 * the idea is like this:
5443 5445 * 1) Partition all of the free slot into NCPU groups. For example,
5444 5446 * In system where we have 15 slots, and 4 CPU, then slot s1,s5,s9,s13
5445 5447 * are marked belonging to CPU1, s2,s6,s10,s14 to CPU2, s3,s7,s11,s15
5446 5448 * to CPU3, and s4,s8,s12 to CPU4.
5447 5449 * 2) In each of the group, an alloc/release queue pair is created,
5448 5450 * and both the allocq and the releaseq have a dedicated mutex.
5449 5451 * 3) When init, all of the slots in a CPU group are inserted into the
5450 5452 * allocq of its CPU's pair.
5451 5453 * 4) When doing IO,
5452 5454 * mptsas_scsi_start()
5453 5455 * {
5454 5456 * cpuid = the cpu NO of the cpu where this thread is running on
5455 5457 * retry:
5456 5458 * mutex_enter(&allocq[cpuid]);
5457 5459 * if (get free slot = success) {
5458 5460 * remove the slot from the allocq
5459 5461 * mutex_exit(&allocq[cpuid]);
5460 5462 * return(success);
5461 5463 * } else { // exchange allocq and releaseq and try again
5462 5464 * mutex_enter(&releq[cpuid]);
5463 5465 * exchange the allocq and releaseq of this pair;
5464 5466 * mutex_exit(&releq[cpuid]);
5465 5467 * if (try to get free slot again = success) {
5466 5468 * remove the slot from the allocq
5467 5469 * mutex_exit(&allocq[cpuid]);
5468 5470 * return(success);
5469 5471 * } else {
5470 5472 * MOD(cpuid)++;
5471 5473 * goto retry;
5472 5474 * if (all CPU groups tried)
5473 5475 * mutex_exit(&allocq[cpuid]);
5474 5476 * return(failure);
5475 5477 * }
5476 5478 * }
5477 5479 * }
5478 5480 * ISR()
5479 5481 * {
5480 5482 * cpuid = the CPU group id where the slot sending the
5481 5483 * cmd belongs;
5482 5484 * mutex_enter(&releq[cpuid]);
5483 5485 * remove the slot from the releaseq
5484 5486 * mutex_exit(&releq[cpuid]);
5485 5487 * }
5486 5488 * This way, only when the queue pair doing exchange have mutex
5487 5489 * contentions.
5488 5490 *
5489 5491 * For mutex m_intr_mutex and m_tgt_intr_mutex, there are 2 scenarios:
5490 5492 *
5491 5493 * a)If the elements are only checked but not modified in the ISR, then
5492 5494 * only the places where those elements are modifed(outside of ISR)
5493 5495 * need to be protected by the new introduced mutex.
5494 5496 * For example, data A is only read/checked in ISR, then we need do
5495 5497 * like this:
5496 5498 * In ISR:
5497 5499 * {
5498 5500 * mutex_enter(&new_mutex);
5499 5501 * read(A);
5500 5502 * mutex_exit(&new_mutex);
5501 5503 * //the new_mutex here is either the m_tgt_intr_mutex or
5502 5504 * //the m_intr_mutex.
5503 5505 * }
5504 5506 * In non-ISR
5505 5507 * {
5506 5508 * mutex_enter(&m_mutex); //the stock driver already did this
5507 5509 * mutex_enter(&new_mutex);
5508 5510 * write(A);
5509 5511 * mutex_exit(&new_mutex);
5510 5512 * mutex_exit(&m_mutex); //the stock driver already did this
5511 5513 *
5512 5514 * read(A);
5513 5515 * // read(A) in non-ISR is not required to be protected by new
5514 5516 * // mutex since 'A' has already been protected by m_mutex
5515 5517 * // outside of the ISR
5516 5518 * }
5517 5519 *
5518 5520 * Those fields in mptsas_target_t/ptgt which are only read in ISR
5519 5521 * fall into this catergory. So they, together with the fields which
5520 5522 * are never read in ISR, are not necessary to be protected by
5521 5523 * m_tgt_intr_mutex, don't bother.
5522 5524 * checking of m_waitq also falls into this catergory. so all of the
5523 5525 * place outside of ISR where the m_waitq is modified, such as in
5524 5526 * mptsas_waitq_add(), mptsas_waitq_delete(), mptsas_waitq_rm(),
5525 5527 * m_intr_mutex should be used.
5526 5528 *
5527 5529 * b)If the elements are modified in the ISR, then each place where
5528 5530 * those elements are referred(outside of ISR) need to be protected
5529 5531 * by the new introduced mutex. Of course, if those elements only
5530 5532 * appear in the non-key code path, that is, they don't affect
5531 5533 * performance, then the m_mutex can still be used as before.
5532 5534 * For example, data B is modified in key code path in ISR, and data C
5533 5535 * is modified in non-key code path in ISR, then we can do like this:
5534 5536 * In ISR:
5535 5537 * {
5536 5538 * mutex_enter(&new_mutex);
5537 5539 * wirte(B);
5538 5540 * mutex_exit(&new_mutex);
5539 5541 * if (seldom happen) {
5540 5542 * mutex_enter(&m_mutex);
5541 5543 * write(C);
5542 5544 * mutex_exit(&m_mutex);
5543 5545 * }
5544 5546 * //the new_mutex here is either the m_tgt_intr_mutex or
5545 5547 * //the m_intr_mutex.
5546 5548 * }
5547 5549 * In non-ISR
5548 5550 * {
5549 5551 * mutex_enter(&new_mutex);
5550 5552 * write(B);
5551 5553 * mutex_exit(&new_mutex);
5552 5554 *
5553 5555 * mutex_enter(&new_mutex);
5554 5556 * read(B);
5555 5557 * mutex_exit(&new_mutex);
5556 5558 * // both write(B) and read(B) in non-ISR is required to be
5557 5559 * // protected by new mutex outside of the ISR
5558 5560 *
5559 5561 * mutex_enter(&m_mutex); //the stock driver already did this
5560 5562 * read(C);
5561 5563 * write(C);
5562 5564 * mutex_exit(&m_mutex); //the stock driver already did this
5563 5565 * // both write(C) and read(C) in non-ISR have been already
5564 5566 * // been protected by m_mutex outside of the ISR
5565 5567 * }
5566 5568 *
5567 5569 * For example, ptgt->m_t_ncmds fall into 'B' of this catergory, and
5568 5570 * elements shown in address reply, restart_hba, passthrough, IOC
5569 5571 * fall into 'C' of this catergory.
5570 5572 *
5571 5573 * In any case where mutexs are nested, make sure in the following
5572 5574 * order:
5573 5575 * m_mutex -> m_intr_mutex -> m_tgt_intr_mutex
5574 5576 * m_intr_mutex -> m_tgt_intr_mutex
5575 5577 * m_mutex -> m_intr_mutex
5576 5578 * m_mutex -> m_tgt_intr_mutex
5577 5579 *
5578 5580 * 2.
5579 5581 * Make sure at any time, getting the ReplyDescriptor by m_post_index
5580 5582 * and setting m_post_index to the ReplyDescriptorIndex register are
5581 5583 * atomic. Since m_mutex is not used for this purpose in ISR, the new
5582 5584 * mutex m_intr_mutex must play this role. So mptsas_poll(), where this
5583 5585 * kind of getting/setting is also performed, must use m_intr_mutex.
5584 5586 * Note, since context reply in ISR/process_intr is the only code path
5585 5587 * which affect performance, a fast path is introduced to only handle
5586 5588 * the read/write IO having context reply. For other IOs such as
5587 5589 * passthrough and IOC with context reply and all address reply, we
5588 5590 * use the as-is process_intr() to handle them. In order to keep the
5589 5591 * same semantics in process_intr(), make sure any new mutex is not held
5590 5592 * before enterring it.
5591 5593 */
5592 5594
5593 5595 mutex_enter(&mpt->m_intr_mutex);
5594 5596
5595 5597 /*
5596 5598 * If interrupts are shared by two channels then check whether this
5597 5599 * interrupt is genuinely for this channel by making sure first the
5598 5600 * chip is in high power state.
5599 5601 */
5600 5602 if ((mpt->m_options & MPTSAS_OPT_PM) &&
5601 5603 (mpt->m_power_level != PM_LEVEL_D0)) {
5602 5604 mutex_exit(&mpt->m_intr_mutex);
5603 5605 return (DDI_INTR_UNCLAIMED);
5604 5606 }
5605 5607
5606 5608 /*
5607 5609 * If polling, interrupt was triggered by some shared interrupt because
5608 5610 * IOC interrupts are disabled during polling, so polling routine will
5609 5611 * handle any replies. Considering this, if polling is happening,
5610 5612 * return with interrupt unclaimed.
5611 5613 */
5612 5614 if (mpt->m_polled_intr) {
5613 5615 mutex_exit(&mpt->m_intr_mutex);
5614 5616 mptsas_log(mpt, CE_WARN, "mpt_sas: Unclaimed interrupt");
5615 5617 return (DDI_INTR_UNCLAIMED);
5616 5618 }
5617 5619
5618 5620 /*
5619 5621 * Read the istat register.
5620 5622 */
5621 5623 if ((INTPENDING(mpt)) != 0) {
5622 5624 /*
5623 5625 * read fifo until empty.
5624 5626 */
5625 5627 #ifndef __lock_lint
5626 5628 _NOTE(CONSTCOND)
5627 5629 #endif
5628 5630 while (TRUE) {
5629 5631 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
5630 5632 DDI_DMA_SYNC_FORCPU);
5631 5633 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t)
5632 5634 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index);
5633 5635
5634 5636 if (ddi_get32(mpt->m_acc_post_queue_hdl,
5635 5637 &reply_desc_union->Words.Low) == 0xFFFFFFFF ||
5636 5638 ddi_get32(mpt->m_acc_post_queue_hdl,
5637 5639 &reply_desc_union->Words.High) == 0xFFFFFFFF) {
5638 5640 break;
5639 5641 }
5640 5642
5641 5643 /*
5642 5644 * The reply is valid, process it according to its
5643 5645 * type. Also, set a flag for updating the reply index
5644 5646 * after they've all been processed.
5645 5647 */
5646 5648 did_reply = TRUE;
5647 5649
5648 5650 reply_type = ddi_get8(mpt->m_acc_post_queue_hdl,
5649 5651 &reply_desc_union->Default.ReplyFlags);
5650 5652 reply_type &= MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
5651 5653 mpt->m_reply[i].Default.ReplyFlags = reply_type;
5652 5654 if (reply_type ==
5653 5655 MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
5654 5656 SMID = ddi_get16(mpt->m_acc_post_queue_hdl,
5655 5657 &reply_desc_union->SCSIIOSuccess.SMID);
5656 5658 if (mptsas_handle_io_fastpath(mpt, SMID) !=
5657 5659 TRUE) {
5658 5660 mpt->m_reply[i].SCSIIOSuccess.SMID =
5659 5661 SMID;
5660 5662 i++;
5661 5663 }
5662 5664 } else if (reply_type ==
5663 5665 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
5664 5666 mpt->m_reply[i].AddressReply.ReplyFrameAddress =
5665 5667 ddi_get32(mpt->m_acc_post_queue_hdl,
5666 5668 &reply_desc_union->AddressReply.
5667 5669 ReplyFrameAddress);
5668 5670 mpt->m_reply[i].AddressReply.SMID =
5669 5671 ddi_get16(mpt->m_acc_post_queue_hdl,
5670 5672 &reply_desc_union->AddressReply.SMID);
5671 5673 i++;
5672 5674 }
5673 5675 /*
5674 5676 * Clear the reply descriptor for re-use and increment
5675 5677 * index.
5676 5678 */
5677 5679 ddi_put64(mpt->m_acc_post_queue_hdl,
5678 5680 &((uint64_t *)(void *)mpt->m_post_queue)
5679 5681 [mpt->m_post_index], 0xFFFFFFFFFFFFFFFF);
5680 5682 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
5681 5683 DDI_DMA_SYNC_FORDEV);
5682 5684
5683 5685 /*
5684 5686 * Increment post index and roll over if needed.
5685 5687 */
5686 5688 if (++mpt->m_post_index == mpt->m_post_queue_depth) {
5687 5689 mpt->m_post_index = 0;
5688 5690 }
5689 5691 if (i >= MPI_ADDRESS_COALSCE_MAX)
5690 5692 break;
5691 5693 }
5692 5694
5693 5695 /*
5694 5696 * Update the global reply index if at least one reply was
5695 5697 * processed.
5696 5698 */
5697 5699 if (did_reply) {
5698 5700 ddi_put32(mpt->m_datap,
5699 5701 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index);
5700 5702
5701 5703 /*
5702 5704 * For fma, only check the PIO is required and enough
5703 5705 * here. Those cases where fastpath is not hit, the
5704 5706 * mptsas_fma_check() check all of the types of
5705 5707 * fma. That is not necessary and sometimes not
5706 5708 * correct. fma check should only be done after
5707 5709 * the PIO and/or dma is performed.
5708 5710 */
5709 5711 if ((mptsas_check_acc_handle(mpt->m_datap) !=
5710 5712 DDI_SUCCESS)) {
5711 5713 ddi_fm_service_impact(mpt->m_dip,
5712 5714 DDI_SERVICE_UNAFFECTED);
5713 5715 }
5714 5716
5715 5717 }
5716 5718 } else {
5717 5719 mutex_exit(&mpt->m_intr_mutex);
5718 5720 return (DDI_INTR_UNCLAIMED);
5719 5721 }
5720 5722 NDBG1(("mptsas_intr complete"));
5721 5723 mutex_exit(&mpt->m_intr_mutex);
5722 5724
5723 5725 /*
5724 5726 * Since most of the cmds(read and write IO with success return.)
5725 5727 * have already been processed in fast path in which the m_mutex
5726 5728 * is not held, handling here the address reply and other context reply
5727 5729 * such as passthrough and IOC cmd with m_mutex held should be a big
5728 5730 * issue for performance.
5729 5731 * If holding m_mutex to process these cmds was still an obvious issue,
5730 5732 * we can process them in a taskq.
5731 5733 */
5732 5734 for (j = 0; j < i; j++) {
5733 5735 mutex_enter(&mpt->m_mutex);
5734 5736 mptsas_process_intr(mpt, &mpt->m_reply[j]);
5735 5737 mutex_exit(&mpt->m_mutex);
5736 5738 }
5737 5739
5738 5740 /*
5739 5741 * If no helper threads are created, process the doneq in ISR. If
5740 5742 * helpers are created, use the doneq length as a metric to measure the
5741 5743 * load on the interrupt CPU. If it is long enough, which indicates the
5742 5744 * load is heavy, then we deliver the IO completions to the helpers.
5743 5745 * This measurement has some limitations, although it is simple and
5744 5746 * straightforward and works well for most of the cases at present.
5745 5747 */
5746 5748 if (!mpt->m_doneq_thread_n) {
5747 5749 mptsas_doneq_empty(mpt);
5748 5750 } else {
5749 5751 int helper = 1;
5750 5752 mutex_enter(&mpt->m_intr_mutex);
5751 5753 if (mpt->m_doneq_len <= mpt->m_doneq_length_threshold)
5752 5754 helper = 0;
5753 5755 mutex_exit(&mpt->m_intr_mutex);
5754 5756 if (helper) {
5755 5757 mptsas_deliver_doneq_thread(mpt);
5756 5758 } else {
5757 5759 mptsas_doneq_empty(mpt);
5758 5760 }
5759 5761 }
5760 5762
5761 5763 /*
5762 5764 * If there are queued cmd, start them now.
5763 5765 */
5764 5766 mutex_enter(&mpt->m_intr_mutex);
5765 5767 if (mpt->m_waitq != NULL) {
5766 5768 mutex_exit(&mpt->m_intr_mutex);
5767 5769 mutex_enter(&mpt->m_mutex);
5768 5770 mptsas_restart_hba(mpt);
5769 5771 mutex_exit(&mpt->m_mutex);
5770 5772 return (DDI_INTR_CLAIMED);
5771 5773 }
5772 5774 mutex_exit(&mpt->m_intr_mutex);
5773 5775 return (DDI_INTR_CLAIMED);
5774 5776 }
5775 5777
5776 5778 /*
5777 5779 * In ISR, the successfully completed read and write IO are processed in a
5778 5780 * fast path. This function is only used to handle non-fastpath IO, including
5779 5781 * all of the address reply, and the context reply for IOC cmd, passthrough,
5780 5782 * etc.
5781 5783 * This function is also used to process polled cmd.
5782 5784 */
5783 5785 static void
5784 5786 mptsas_process_intr(mptsas_t *mpt,
5785 5787 pMpi2ReplyDescriptorsUnion_t reply_desc_union)
5786 5788 {
5787 5789 uint8_t reply_type;
5788 5790
5789 5791 /*
5790 5792 * The reply is valid, process it according to its
5791 5793 * type. Also, set a flag for updated the reply index
5792 5794 * after they've all been processed.
5793 5795 */
5794 5796 reply_type = reply_desc_union->Default.ReplyFlags;
5795 5797 if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
5796 5798 mptsas_handle_scsi_io_success(mpt, reply_desc_union);
5797 5799 } else if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
5798 5800 mptsas_handle_address_reply(mpt, reply_desc_union);
5799 5801 } else {
5800 5802 mptsas_log(mpt, CE_WARN, "?Bad reply type %x", reply_type);
5801 5803 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
5802 5804 }
5803 5805 }
5804 5806
5805 5807 /*
5806 5808 * handle qfull condition
5807 5809 */
5808 5810 static void
5809 5811 mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd)
5810 5812 {
5811 5813 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
5812 5814
5813 5815 if ((++cmd->cmd_qfull_retries > ptgt->m_qfull_retries) ||
5814 5816 (ptgt->m_qfull_retries == 0)) {
5815 5817 /*
5816 5818 * We have exhausted the retries on QFULL, or,
5817 5819 * the target driver has indicated that it
5818 5820 * wants to handle QFULL itself by setting
5819 5821 * qfull-retries capability to 0. In either case
5820 5822 * we want the target driver's QFULL handling
5821 5823 * to kick in. We do this by having pkt_reason
5822 5824 * as CMD_CMPLT and pkt_scbp as STATUS_QFULL.
5823 5825 */
5824 5826 mutex_enter(&ptgt->m_tgt_intr_mutex);
5825 5827 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5826 5828 mutex_exit(&ptgt->m_tgt_intr_mutex);
5827 5829 } else {
5828 5830 mutex_enter(&ptgt->m_tgt_intr_mutex);
5829 5831 if (ptgt->m_reset_delay == 0) {
5830 5832 ptgt->m_t_throttle =
5831 5833 max((ptgt->m_t_ncmds - 2), 0);
5832 5834 }
5833 5835 mutex_exit(&ptgt->m_tgt_intr_mutex);
5834 5836
5835 5837 cmd->cmd_pkt_flags |= FLAG_HEAD;
5836 5838 cmd->cmd_flags &= ~(CFLAG_TRANFLAG);
5837 5839 cmd->cmd_flags |= CFLAG_RETRY;
5838 5840
5839 5841 mutex_exit(&mpt->m_mutex);
5840 5842 (void) mptsas_accept_pkt(mpt, cmd);
5841 5843 mutex_enter(&mpt->m_mutex);
5842 5844
5843 5845 /*
5844 5846 * when target gives queue full status with no commands
5845 5847 * outstanding (m_t_ncmds == 0), throttle is set to 0
5846 5848 * (HOLD_THROTTLE), and the queue full handling start
5847 5849 * (see psarc/1994/313); if there are commands outstanding,
5848 5850 * throttle is set to (m_t_ncmds - 2)
5849 5851 */
5850 5852 mutex_enter(&ptgt->m_tgt_intr_mutex);
5851 5853 if (ptgt->m_t_throttle == HOLD_THROTTLE) {
5852 5854 /*
5853 5855 * By setting throttle to QFULL_THROTTLE, we
5854 5856 * avoid submitting new commands and in
5855 5857 * mptsas_restart_cmd find out slots which need
5856 5858 * their throttles to be cleared.
5857 5859 */
5858 5860 mptsas_set_throttle(mpt, ptgt, QFULL_THROTTLE);
5859 5861 if (mpt->m_restart_cmd_timeid == 0) {
5860 5862 mpt->m_restart_cmd_timeid =
5861 5863 timeout(mptsas_restart_cmd, mpt,
5862 5864 ptgt->m_qfull_retry_interval);
5863 5865 }
5864 5866 }
5865 5867 mutex_exit(&ptgt->m_tgt_intr_mutex);
5866 5868 }
5867 5869 }
5868 5870
5869 5871 mptsas_phymask_t
5870 5872 mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport)
5871 5873 {
5872 5874 mptsas_phymask_t phy_mask = 0;
5873 5875 uint8_t i = 0;
5874 5876
5875 5877 NDBG20(("mptsas%d physport_to_phymask enter", mpt->m_instance));
5876 5878
5877 5879 ASSERT(mutex_owned(&mpt->m_mutex));
5878 5880
5879 5881 /*
5880 5882 * If physport is 0xFF, this is a RAID volume. Use phymask of 0.
5881 5883 */
5882 5884 if (physport == 0xFF) {
5883 5885 return (0);
5884 5886 }
5885 5887
5886 5888 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
5887 5889 if (mpt->m_phy_info[i].attached_devhdl &&
5888 5890 (mpt->m_phy_info[i].phy_mask != 0) &&
5889 5891 (mpt->m_phy_info[i].port_num == physport)) {
5890 5892 phy_mask = mpt->m_phy_info[i].phy_mask;
5891 5893 break;
5892 5894 }
5893 5895 }
5894 5896 NDBG20(("mptsas%d physport_to_phymask:physport :%x phymask :%x, ",
5895 5897 mpt->m_instance, physport, phy_mask));
5896 5898 return (phy_mask);
5897 5899 }
5898 5900
5899 5901 /*
5900 5902 * mpt free device handle after device gone, by use of passthrough
5901 5903 */
5902 5904 static int
5903 5905 mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl)
5904 5906 {
5905 5907 Mpi2SasIoUnitControlRequest_t req;
5906 5908 Mpi2SasIoUnitControlReply_t rep;
5907 5909 int ret;
5908 5910
5909 5911 ASSERT(mutex_owned(&mpt->m_mutex));
5910 5912
5911 5913 /*
5912 5914 * Need to compose a SAS IO Unit Control request message
5913 5915 * and call mptsas_do_passthru() function
5914 5916 */
5915 5917 bzero(&req, sizeof (req));
5916 5918 bzero(&rep, sizeof (rep));
5917 5919
5918 5920 req.Function = MPI2_FUNCTION_SAS_IO_UNIT_CONTROL;
5919 5921 req.Operation = MPI2_SAS_OP_REMOVE_DEVICE;
5920 5922 req.DevHandle = LE_16(devhdl);
5921 5923
5922 5924 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL,
5923 5925 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL);
5924 5926 if (ret != 0) {
5925 5927 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit "
5926 5928 "Control error %d", ret);
5927 5929 return (DDI_FAILURE);
5928 5930 }
5929 5931
5930 5932 /* do passthrough success, check the ioc status */
5931 5933 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
5932 5934 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit "
5933 5935 "Control IOCStatus %d", LE_16(rep.IOCStatus));
5934 5936 return (DDI_FAILURE);
5935 5937 }
5936 5938
5937 5939 return (DDI_SUCCESS);
5938 5940 }
5939 5941
5940 5942 static void
5941 5943 mptsas_update_phymask(mptsas_t *mpt)
5942 5944 {
5943 5945 mptsas_phymask_t mask = 0, phy_mask;
5944 5946 char *phy_mask_name;
5945 5947 uint8_t current_port;
5946 5948 int i, j;
5947 5949
5948 5950 NDBG20(("mptsas%d update phymask ", mpt->m_instance));
5949 5951
5950 5952 ASSERT(mutex_owned(&mpt->m_mutex));
5951 5953
5952 5954 (void) mptsas_get_sas_io_unit_page(mpt);
5953 5955
5954 5956 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
5955 5957
5956 5958 for (i = 0; i < mpt->m_num_phys; i++) {
5957 5959 phy_mask = 0x00;
5958 5960
5959 5961 if (mpt->m_phy_info[i].attached_devhdl == 0)
5960 5962 continue;
5961 5963
5962 5964 bzero(phy_mask_name, sizeof (phy_mask_name));
5963 5965
5964 5966 current_port = mpt->m_phy_info[i].port_num;
5965 5967
5966 5968 if ((mask & (1 << i)) != 0)
5967 5969 continue;
5968 5970
5969 5971 for (j = 0; j < mpt->m_num_phys; j++) {
5970 5972 if (mpt->m_phy_info[j].attached_devhdl &&
5971 5973 (mpt->m_phy_info[j].port_num == current_port)) {
5972 5974 phy_mask |= (1 << j);
5973 5975 }
5974 5976 }
5975 5977 mask = mask | phy_mask;
5976 5978
5977 5979 for (j = 0; j < mpt->m_num_phys; j++) {
5978 5980 if ((phy_mask >> j) & 0x01) {
5979 5981 mpt->m_phy_info[j].phy_mask = phy_mask;
5980 5982 }
5981 5983 }
5982 5984
5983 5985 (void) sprintf(phy_mask_name, "%x", phy_mask);
5984 5986
5985 5987 mutex_exit(&mpt->m_mutex);
5986 5988 /*
5987 5989 * register a iport, if the port has already been existed
5988 5990 * SCSA will do nothing and just return.
5989 5991 */
5990 5992 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name);
5991 5993 mutex_enter(&mpt->m_mutex);
5992 5994 }
5993 5995 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
5994 5996 NDBG20(("mptsas%d update phymask return", mpt->m_instance));
5995 5997 }
5996 5998
5997 5999 /*
5998 6000 * mptsas_handle_dr is a task handler for DR, the DR action includes:
5999 6001 * 1. Directly attched Device Added/Removed.
6000 6002 * 2. Expander Device Added/Removed.
6001 6003 * 3. Indirectly Attached Device Added/Expander.
6002 6004 * 4. LUNs of a existing device status change.
6003 6005 * 5. RAID volume created/deleted.
6004 6006 * 6. Member of RAID volume is released because of RAID deletion.
6005 6007 * 7. Physical disks are removed because of RAID creation.
6006 6008 */
6007 6009 static void
6008 6010 mptsas_handle_dr(void *args) {
6009 6011 mptsas_topo_change_list_t *topo_node = NULL;
6010 6012 mptsas_topo_change_list_t *save_node = NULL;
6011 6013 mptsas_t *mpt;
6012 6014 dev_info_t *parent = NULL;
6013 6015 mptsas_phymask_t phymask = 0;
6014 6016 char *phy_mask_name;
6015 6017 uint8_t flags = 0, physport = 0xff;
6016 6018 uint8_t port_update = 0;
6017 6019 uint_t event;
6018 6020
6019 6021 topo_node = (mptsas_topo_change_list_t *)args;
6020 6022
6021 6023 mpt = topo_node->mpt;
6022 6024 event = topo_node->event;
6023 6025 flags = topo_node->flags;
6024 6026
6025 6027 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
6026 6028
6027 6029 NDBG20(("mptsas%d handle_dr enter", mpt->m_instance));
6028 6030
6029 6031 switch (event) {
6030 6032 case MPTSAS_DR_EVENT_RECONFIG_TARGET:
6031 6033 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6032 6034 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE) ||
6033 6035 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) {
6034 6036 /*
6035 6037 * Direct attached or expander attached device added
6036 6038 * into system or a Phys Disk that is being unhidden.
6037 6039 */
6038 6040 port_update = 1;
6039 6041 }
6040 6042 break;
6041 6043 case MPTSAS_DR_EVENT_RECONFIG_SMP:
6042 6044 /*
6043 6045 * New expander added into system, it must be the head
6044 6046 * of topo_change_list_t
6045 6047 */
6046 6048 port_update = 1;
6047 6049 break;
6048 6050 default:
6049 6051 port_update = 0;
6050 6052 break;
6051 6053 }
6052 6054 /*
6053 6055 * All cases port_update == 1 may cause initiator port form change
6054 6056 */
6055 6057 mutex_enter(&mpt->m_mutex);
6056 6058 if (mpt->m_port_chng && port_update) {
6057 6059 /*
6058 6060 * mpt->m_port_chng flag indicates some PHYs of initiator
6059 6061 * port have changed to online. So when expander added or
6060 6062 * directly attached device online event come, we force to
6061 6063 * update port information by issueing SAS IO Unit Page and
6062 6064 * update PHYMASKs.
6063 6065 */
6064 6066 (void) mptsas_update_phymask(mpt);
6065 6067 mpt->m_port_chng = 0;
6066 6068
6067 6069 }
6068 6070 mutex_exit(&mpt->m_mutex);
6069 6071 while (topo_node) {
6070 6072 phymask = 0;
6071 6073 if (parent == NULL) {
6072 6074 physport = topo_node->un.physport;
6073 6075 event = topo_node->event;
6074 6076 flags = topo_node->flags;
6075 6077 if (event & (MPTSAS_DR_EVENT_OFFLINE_TARGET |
6076 6078 MPTSAS_DR_EVENT_OFFLINE_SMP)) {
6077 6079 /*
6078 6080 * For all offline events, phymask is known
6079 6081 */
6080 6082 phymask = topo_node->un.phymask;
6081 6083 goto find_parent;
6082 6084 }
6083 6085 if (event & MPTSAS_TOPO_FLAG_REMOVE_HANDLE) {
6084 6086 goto handle_topo_change;
6085 6087 }
6086 6088 if (flags & MPTSAS_TOPO_FLAG_LUN_ASSOCIATED) {
6087 6089 phymask = topo_node->un.phymask;
6088 6090 goto find_parent;
6089 6091 }
6090 6092
6091 6093 if ((flags ==
6092 6094 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) &&
6093 6095 (event == MPTSAS_DR_EVENT_RECONFIG_TARGET)) {
6094 6096 /*
6095 6097 * There is no any field in IR_CONFIG_CHANGE
6096 6098 * event indicate physport/phynum, let's get
6097 6099 * parent after SAS Device Page0 request.
6098 6100 */
6099 6101 goto handle_topo_change;
6100 6102 }
6101 6103
6102 6104 mutex_enter(&mpt->m_mutex);
6103 6105 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6104 6106 /*
6105 6107 * If the direct attached device added or a
6106 6108 * phys disk is being unhidden, argument
6107 6109 * physport actually is PHY#, so we have to get
6108 6110 * phymask according PHY#.
6109 6111 */
6110 6112 physport = mpt->m_phy_info[physport].port_num;
6111 6113 }
6112 6114
6113 6115 /*
6114 6116 * Translate physport to phymask so that we can search
6115 6117 * parent dip.
6116 6118 */
6117 6119 phymask = mptsas_physport_to_phymask(mpt,
6118 6120 physport);
6119 6121 mutex_exit(&mpt->m_mutex);
6120 6122
6121 6123 find_parent:
6122 6124 bzero(phy_mask_name, MPTSAS_MAX_PHYS);
6123 6125 /*
6124 6126 * For RAID topology change node, write the iport name
6125 6127 * as v0.
6126 6128 */
6127 6129 if (flags & MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
6128 6130 (void) sprintf(phy_mask_name, "v0");
6129 6131 } else {
6130 6132 /*
6131 6133 * phymask can bo 0 if the drive has been
6132 6134 * pulled by the time an add event is
6133 6135 * processed. If phymask is 0, just skip this
6134 6136 * event and continue.
6135 6137 */
6136 6138 if (phymask == 0) {
6137 6139 mutex_enter(&mpt->m_mutex);
6138 6140 save_node = topo_node;
6139 6141 topo_node = topo_node->next;
6140 6142 ASSERT(save_node);
6141 6143 kmem_free(save_node,
6142 6144 sizeof (mptsas_topo_change_list_t));
6143 6145 mutex_exit(&mpt->m_mutex);
6144 6146
6145 6147 parent = NULL;
6146 6148 continue;
6147 6149 }
6148 6150 (void) sprintf(phy_mask_name, "%x", phymask);
6149 6151 }
6150 6152 parent = scsi_hba_iport_find(mpt->m_dip,
6151 6153 phy_mask_name);
6152 6154 if (parent == NULL) {
6153 6155 mptsas_log(mpt, CE_WARN, "Failed to find an "
6154 6156 "iport, should not happen!");
6155 6157 goto out;
6156 6158 }
6157 6159
6158 6160 }
6159 6161 ASSERT(parent);
6160 6162 handle_topo_change:
6161 6163
6162 6164 mutex_enter(&mpt->m_mutex);
6163 6165
6164 6166 mptsas_handle_topo_change(topo_node, parent);
6165 6167 save_node = topo_node;
6166 6168 topo_node = topo_node->next;
6167 6169 ASSERT(save_node);
6168 6170 kmem_free(save_node, sizeof (mptsas_topo_change_list_t));
6169 6171 mutex_exit(&mpt->m_mutex);
6170 6172
6171 6173 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6172 6174 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) ||
6173 6175 (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED)) {
6174 6176 /*
6175 6177 * If direct attached device associated, make sure
6176 6178 * reset the parent before start the next one. But
6177 6179 * all devices associated with expander shares the
6178 6180 * parent. Also, reset parent if this is for RAID.
6179 6181 */
6180 6182 parent = NULL;
6181 6183 }
6182 6184 }
6183 6185 out:
6184 6186 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
6185 6187 }
6186 6188
6187 6189 static void
6188 6190 mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node,
6189 6191 dev_info_t *parent)
6190 6192 {
6191 6193 mptsas_target_t *ptgt = NULL;
6192 6194 mptsas_smp_t *psmp = NULL;
6193 6195 mptsas_t *mpt = (void *)topo_node->mpt;
6194 6196 uint16_t devhdl;
6195 6197 uint16_t attached_devhdl;
6196 6198 uint64_t sas_wwn = 0;
6197 6199 int rval = 0;
6198 6200 uint32_t page_address;
6199 6201 uint8_t phy, flags;
6200 6202 char *addr = NULL;
6201 6203 dev_info_t *lundip;
6202 6204 int circ = 0, circ1 = 0;
6203 6205 char attached_wwnstr[MPTSAS_WWN_STRLEN];
6204 6206
6205 6207 NDBG20(("mptsas%d handle_topo_change enter", mpt->m_instance));
6206 6208
6207 6209 ASSERT(mutex_owned(&mpt->m_mutex));
6208 6210
6209 6211 switch (topo_node->event) {
6210 6212 case MPTSAS_DR_EVENT_RECONFIG_TARGET:
6211 6213 {
6212 6214 char *phy_mask_name;
6213 6215 mptsas_phymask_t phymask = 0;
6214 6216
6215 6217 if (topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
6216 6218 /*
6217 6219 * Get latest RAID info.
6218 6220 */
6219 6221 (void) mptsas_get_raid_info(mpt);
6220 6222 ptgt = mptsas_search_by_devhdl(
6221 6223 &mpt->m_active->m_tgttbl, topo_node->devhdl);
6222 6224 if (ptgt == NULL)
6223 6225 break;
6224 6226 } else {
6225 6227 ptgt = (void *)topo_node->object;
6226 6228 }
6227 6229
6228 6230 if (ptgt == NULL) {
6229 6231 /*
6230 6232 * If a Phys Disk was deleted, RAID info needs to be
6231 6233 * updated to reflect the new topology.
6232 6234 */
6233 6235 (void) mptsas_get_raid_info(mpt);
6234 6236
6235 6237 /*
6236 6238 * Get sas device page 0 by DevHandle to make sure if
6237 6239 * SSP/SATA end device exist.
6238 6240 */
6239 6241 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
6240 6242 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
6241 6243 topo_node->devhdl;
6242 6244
6243 6245 rval = mptsas_get_target_device_info(mpt, page_address,
6244 6246 &devhdl, &ptgt);
6245 6247 if (rval == DEV_INFO_WRONG_DEVICE_TYPE) {
6246 6248 mptsas_log(mpt, CE_NOTE,
6247 6249 "mptsas_handle_topo_change: target %d is "
6248 6250 "not a SAS/SATA device. \n",
6249 6251 topo_node->devhdl);
6250 6252 } else if (rval == DEV_INFO_FAIL_ALLOC) {
6251 6253 mptsas_log(mpt, CE_NOTE,
6252 6254 "mptsas_handle_topo_change: could not "
6253 6255 "allocate memory. \n");
6254 6256 }
6255 6257 /*
6256 6258 * If rval is DEV_INFO_PHYS_DISK than there is nothing
6257 6259 * else to do, just leave.
6258 6260 */
6259 6261 if (rval != DEV_INFO_SUCCESS) {
6260 6262 return;
6261 6263 }
6262 6264 }
6263 6265
6264 6266 ASSERT(ptgt->m_devhdl == topo_node->devhdl);
6265 6267
6266 6268 mutex_exit(&mpt->m_mutex);
6267 6269 flags = topo_node->flags;
6268 6270
6269 6271 if (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) {
6270 6272 phymask = ptgt->m_phymask;
6271 6273 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
6272 6274 (void) sprintf(phy_mask_name, "%x", phymask);
6273 6275 parent = scsi_hba_iport_find(mpt->m_dip,
6274 6276 phy_mask_name);
6275 6277 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
6276 6278 if (parent == NULL) {
6277 6279 mptsas_log(mpt, CE_WARN, "Failed to find a "
6278 6280 "iport for PD, should not happen!");
6279 6281 mutex_enter(&mpt->m_mutex);
6280 6282 break;
6281 6283 }
6282 6284 }
6283 6285
6284 6286 if (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
6285 6287 ndi_devi_enter(parent, &circ1);
6286 6288 (void) mptsas_config_raid(parent, topo_node->devhdl,
6287 6289 &lundip);
6288 6290 ndi_devi_exit(parent, circ1);
6289 6291 } else {
6290 6292 /*
6291 6293 * hold nexus for bus configure
6292 6294 */
6293 6295 ndi_devi_enter(scsi_vhci_dip, &circ);
6294 6296 ndi_devi_enter(parent, &circ1);
6295 6297 rval = mptsas_config_target(parent, ptgt);
6296 6298 /*
6297 6299 * release nexus for bus configure
6298 6300 */
6299 6301 ndi_devi_exit(parent, circ1);
6300 6302 ndi_devi_exit(scsi_vhci_dip, circ);
6301 6303
6302 6304 /*
6303 6305 * Add parent's props for SMHBA support
6304 6306 */
6305 6307 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6306 6308 bzero(attached_wwnstr,
6307 6309 sizeof (attached_wwnstr));
6308 6310 (void) sprintf(attached_wwnstr, "w%016"PRIx64,
6309 6311 ptgt->m_sas_wwn);
6310 6312 if (ddi_prop_update_string(DDI_DEV_T_NONE,
6311 6313 parent,
6312 6314 SCSI_ADDR_PROP_ATTACHED_PORT,
6313 6315 attached_wwnstr)
6314 6316 != DDI_PROP_SUCCESS) {
6315 6317 (void) ddi_prop_remove(DDI_DEV_T_NONE,
6316 6318 parent,
6317 6319 SCSI_ADDR_PROP_ATTACHED_PORT);
6318 6320 mptsas_log(mpt, CE_WARN, "Failed to"
6319 6321 "attached-port props");
6320 6322 return;
6321 6323 }
6322 6324 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6323 6325 MPTSAS_NUM_PHYS, 1) !=
6324 6326 DDI_PROP_SUCCESS) {
6325 6327 (void) ddi_prop_remove(DDI_DEV_T_NONE,
6326 6328 parent, MPTSAS_NUM_PHYS);
6327 6329 mptsas_log(mpt, CE_WARN, "Failed to"
6328 6330 " create num-phys props");
6329 6331 return;
6330 6332 }
6331 6333
6332 6334 /*
6333 6335 * Update PHY info for smhba
6334 6336 */
6335 6337 mutex_enter(&mpt->m_mutex);
6336 6338 if (mptsas_smhba_phy_init(mpt)) {
6337 6339 mutex_exit(&mpt->m_mutex);
6338 6340 mptsas_log(mpt, CE_WARN, "mptsas phy"
6339 6341 " update failed");
6340 6342 return;
6341 6343 }
6342 6344 mutex_exit(&mpt->m_mutex);
6343 6345 mptsas_smhba_set_phy_props(mpt,
6344 6346 ddi_get_name_addr(parent), parent,
6345 6347 1, &attached_devhdl);
6346 6348 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6347 6349 MPTSAS_VIRTUAL_PORT, 0) !=
6348 6350 DDI_PROP_SUCCESS) {
6349 6351 (void) ddi_prop_remove(DDI_DEV_T_NONE,
6350 6352 parent, MPTSAS_VIRTUAL_PORT);
6351 6353 mptsas_log(mpt, CE_WARN,
6352 6354 "mptsas virtual-port"
6353 6355 "port prop update failed");
6354 6356 return;
6355 6357 }
6356 6358 }
6357 6359 }
6358 6360 mutex_enter(&mpt->m_mutex);
6359 6361
6360 6362 NDBG20(("mptsas%d handle_topo_change to online devhdl:%x, "
6361 6363 "phymask:%x.", mpt->m_instance, ptgt->m_devhdl,
6362 6364 ptgt->m_phymask));
6363 6365 break;
6364 6366 }
6365 6367 case MPTSAS_DR_EVENT_OFFLINE_TARGET:
6366 6368 {
6367 6369 mptsas_hash_table_t *tgttbl = &mpt->m_active->m_tgttbl;
6368 6370 devhdl = topo_node->devhdl;
6369 6371 ptgt = mptsas_search_by_devhdl(tgttbl, devhdl);
6370 6372 if (ptgt == NULL)
6371 6373 break;
6372 6374
6373 6375 sas_wwn = ptgt->m_sas_wwn;
6374 6376 phy = ptgt->m_phynum;
6375 6377
6376 6378 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
6377 6379
6378 6380 if (sas_wwn) {
6379 6381 (void) sprintf(addr, "w%016"PRIx64, sas_wwn);
6380 6382 } else {
6381 6383 (void) sprintf(addr, "p%x", phy);
6382 6384 }
6383 6385 ASSERT(ptgt->m_devhdl == devhdl);
6384 6386
6385 6387 if ((topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) ||
6386 6388 (topo_node->flags ==
6387 6389 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) {
6388 6390 /*
6389 6391 * Get latest RAID info if RAID volume status changes
6390 6392 * or Phys Disk status changes
6391 6393 */
6392 6394 (void) mptsas_get_raid_info(mpt);
6393 6395 }
6394 6396 /*
6395 6397 * Abort all outstanding command on the device
6396 6398 */
6397 6399 rval = mptsas_do_scsi_reset(mpt, devhdl);
6398 6400 if (rval) {
6399 6401 NDBG20(("mptsas%d handle_topo_change to reset target "
6400 6402 "before offline devhdl:%x, phymask:%x, rval:%x",
6401 6403 mpt->m_instance, ptgt->m_devhdl, ptgt->m_phymask,
6402 6404 rval));
6403 6405 }
6404 6406
6405 6407 mutex_exit(&mpt->m_mutex);
6406 6408
6407 6409 ndi_devi_enter(scsi_vhci_dip, &circ);
6408 6410 ndi_devi_enter(parent, &circ1);
6409 6411 rval = mptsas_offline_target(parent, addr);
6410 6412 ndi_devi_exit(parent, circ1);
6411 6413 ndi_devi_exit(scsi_vhci_dip, circ);
6412 6414 NDBG20(("mptsas%d handle_topo_change to offline devhdl:%x, "
6413 6415 "phymask:%x, rval:%x", mpt->m_instance,
6414 6416 ptgt->m_devhdl, ptgt->m_phymask, rval));
6415 6417
6416 6418 kmem_free(addr, SCSI_MAXNAMELEN);
6417 6419
6418 6420 /*
6419 6421 * Clear parent's props for SMHBA support
6420 6422 */
6421 6423 flags = topo_node->flags;
6422 6424 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6423 6425 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6424 6426 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent,
6425 6427 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
6426 6428 DDI_PROP_SUCCESS) {
6427 6429 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6428 6430 SCSI_ADDR_PROP_ATTACHED_PORT);
6429 6431 mptsas_log(mpt, CE_WARN, "mptsas attached port "
6430 6432 "prop update failed");
6431 6433 break;
6432 6434 }
6433 6435 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6434 6436 MPTSAS_NUM_PHYS, 0) !=
6435 6437 DDI_PROP_SUCCESS) {
6436 6438 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6437 6439 MPTSAS_NUM_PHYS);
6438 6440 mptsas_log(mpt, CE_WARN, "mptsas num phys "
6439 6441 "prop update failed");
6440 6442 break;
6441 6443 }
6442 6444 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6443 6445 MPTSAS_VIRTUAL_PORT, 1) !=
6444 6446 DDI_PROP_SUCCESS) {
6445 6447 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6446 6448 MPTSAS_VIRTUAL_PORT);
6447 6449 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
6448 6450 "prop update failed");
6449 6451 break;
6450 6452 }
6451 6453 }
6452 6454
6453 6455 mutex_enter(&mpt->m_mutex);
6454 6456 if (mptsas_set_led_status(mpt, ptgt, 0) != DDI_SUCCESS) {
6455 6457 NDBG14(("mptsas: clear LED for tgt %x failed",
6456 6458 ptgt->m_slot_num));
6457 6459 }
6458 6460 if (rval == DDI_SUCCESS) {
6459 6461 mptsas_tgt_free(&mpt->m_active->m_tgttbl,
6460 6462 ptgt->m_sas_wwn, ptgt->m_phymask);
6461 6463 ptgt = NULL;
6462 6464 } else {
6463 6465 /*
6464 6466 * clean DR_INTRANSITION flag to allow I/O down to
6465 6467 * PHCI driver since failover finished.
6466 6468 * Invalidate the devhdl
6467 6469 */
6468 6470 mutex_enter(&ptgt->m_tgt_intr_mutex);
6469 6471 ptgt->m_devhdl = MPTSAS_INVALID_DEVHDL;
6470 6472 ptgt->m_tgt_unconfigured = 0;
6471 6473 ptgt->m_dr_flag = MPTSAS_DR_INACTIVE;
6472 6474 mutex_exit(&ptgt->m_tgt_intr_mutex);
6473 6475 }
6474 6476
6475 6477 /*
6476 6478 * Send SAS IO Unit Control to free the dev handle
6477 6479 */
6478 6480 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6479 6481 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE)) {
6480 6482 rval = mptsas_free_devhdl(mpt, devhdl);
6481 6483
6482 6484 NDBG20(("mptsas%d handle_topo_change to remove "
6483 6485 "devhdl:%x, rval:%x", mpt->m_instance, devhdl,
6484 6486 rval));
6485 6487 }
6486 6488
6487 6489 break;
6488 6490 }
6489 6491 case MPTSAS_TOPO_FLAG_REMOVE_HANDLE:
6490 6492 {
6491 6493 devhdl = topo_node->devhdl;
6492 6494 /*
6493 6495 * If this is the remove handle event, do a reset first.
6494 6496 */
6495 6497 if (topo_node->event == MPTSAS_TOPO_FLAG_REMOVE_HANDLE) {
6496 6498 rval = mptsas_do_scsi_reset(mpt, devhdl);
6497 6499 if (rval) {
6498 6500 NDBG20(("mpt%d reset target before remove "
6499 6501 "devhdl:%x, rval:%x", mpt->m_instance,
6500 6502 devhdl, rval));
6501 6503 }
6502 6504 }
6503 6505
6504 6506 /*
6505 6507 * Send SAS IO Unit Control to free the dev handle
6506 6508 */
6507 6509 rval = mptsas_free_devhdl(mpt, devhdl);
6508 6510 NDBG20(("mptsas%d handle_topo_change to remove "
6509 6511 "devhdl:%x, rval:%x", mpt->m_instance, devhdl,
6510 6512 rval));
6511 6513 break;
6512 6514 }
6513 6515 case MPTSAS_DR_EVENT_RECONFIG_SMP:
6514 6516 {
6515 6517 mptsas_smp_t smp;
6516 6518 dev_info_t *smpdip;
6517 6519 mptsas_hash_table_t *smptbl = &mpt->m_active->m_smptbl;
6518 6520
6519 6521 devhdl = topo_node->devhdl;
6520 6522
6521 6523 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL &
6522 6524 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)devhdl;
6523 6525 rval = mptsas_get_sas_expander_page0(mpt, page_address, &smp);
6524 6526 if (rval != DDI_SUCCESS) {
6525 6527 mptsas_log(mpt, CE_WARN, "failed to online smp, "
6526 6528 "handle %x", devhdl);
6527 6529 return;
6528 6530 }
6529 6531
6530 6532 psmp = mptsas_smp_alloc(smptbl, &smp);
6531 6533 if (psmp == NULL) {
6532 6534 return;
6533 6535 }
6534 6536
6535 6537 mutex_exit(&mpt->m_mutex);
6536 6538 ndi_devi_enter(parent, &circ1);
6537 6539 (void) mptsas_online_smp(parent, psmp, &smpdip);
6538 6540 ndi_devi_exit(parent, circ1);
6539 6541
6540 6542 mutex_enter(&mpt->m_mutex);
6541 6543 break;
6542 6544 }
6543 6545 case MPTSAS_DR_EVENT_OFFLINE_SMP:
6544 6546 {
6545 6547 mptsas_hash_table_t *smptbl = &mpt->m_active->m_smptbl;
6546 6548 devhdl = topo_node->devhdl;
6547 6549 uint32_t dev_info;
6548 6550
6549 6551 psmp = mptsas_search_by_devhdl(smptbl, devhdl);
6550 6552 if (psmp == NULL)
6551 6553 break;
6552 6554 /*
6553 6555 * The mptsas_smp_t data is released only if the dip is offlined
6554 6556 * successfully.
6555 6557 */
6556 6558 mutex_exit(&mpt->m_mutex);
6557 6559
6558 6560 ndi_devi_enter(parent, &circ1);
6559 6561 rval = mptsas_offline_smp(parent, psmp, NDI_DEVI_REMOVE);
6560 6562 ndi_devi_exit(parent, circ1);
6561 6563
6562 6564 dev_info = psmp->m_deviceinfo;
6563 6565 if ((dev_info & DEVINFO_DIRECT_ATTACHED) ==
6564 6566 DEVINFO_DIRECT_ATTACHED) {
6565 6567 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6566 6568 MPTSAS_VIRTUAL_PORT, 1) !=
6567 6569 DDI_PROP_SUCCESS) {
6568 6570 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6569 6571 MPTSAS_VIRTUAL_PORT);
6570 6572 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
6571 6573 "prop update failed");
6572 6574 return;
6573 6575 }
6574 6576 /*
6575 6577 * Check whether the smp connected to the iport,
6576 6578 */
6577 6579 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6578 6580 MPTSAS_NUM_PHYS, 0) !=
6579 6581 DDI_PROP_SUCCESS) {
6580 6582 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6581 6583 MPTSAS_NUM_PHYS);
6582 6584 mptsas_log(mpt, CE_WARN, "mptsas num phys"
6583 6585 "prop update failed");
6584 6586 return;
6585 6587 }
6586 6588 /*
6587 6589 * Clear parent's attached-port props
6588 6590 */
6589 6591 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6590 6592 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent,
6591 6593 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
6592 6594 DDI_PROP_SUCCESS) {
6593 6595 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6594 6596 SCSI_ADDR_PROP_ATTACHED_PORT);
6595 6597 mptsas_log(mpt, CE_WARN, "mptsas attached port "
6596 6598 "prop update failed");
6597 6599 return;
6598 6600 }
6599 6601 }
6600 6602
6601 6603 mutex_enter(&mpt->m_mutex);
6602 6604 NDBG20(("mptsas%d handle_topo_change to remove devhdl:%x, "
6603 6605 "rval:%x", mpt->m_instance, psmp->m_devhdl, rval));
6604 6606 if (rval == DDI_SUCCESS) {
6605 6607 mptsas_smp_free(smptbl, psmp->m_sasaddr,
6606 6608 psmp->m_phymask);
6607 6609 } else {
6608 6610 psmp->m_devhdl = MPTSAS_INVALID_DEVHDL;
6609 6611 }
6610 6612
6611 6613 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6612 6614
6613 6615 break;
6614 6616 }
6615 6617 default:
6616 6618 return;
6617 6619 }
6618 6620 }
6619 6621
6620 6622 /*
6621 6623 * Record the event if its type is enabled in mpt instance by ioctl.
6622 6624 */
6623 6625 static void
6624 6626 mptsas_record_event(void *args)
6625 6627 {
6626 6628 m_replyh_arg_t *replyh_arg;
6627 6629 pMpi2EventNotificationReply_t eventreply;
6628 6630 uint32_t event, rfm;
6629 6631 mptsas_t *mpt;
6630 6632 int i, j;
6631 6633 uint16_t event_data_len;
6632 6634 boolean_t sendAEN = FALSE;
6633 6635
6634 6636 replyh_arg = (m_replyh_arg_t *)args;
6635 6637 rfm = replyh_arg->rfm;
6636 6638 mpt = replyh_arg->mpt;
6637 6639
6638 6640 eventreply = (pMpi2EventNotificationReply_t)
6639 6641 (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr));
6640 6642 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
6641 6643
6642 6644
6643 6645 /*
6644 6646 * Generate a system event to let anyone who cares know that a
6645 6647 * LOG_ENTRY_ADDED event has occurred. This is sent no matter what the
6646 6648 * event mask is set to.
6647 6649 */
6648 6650 if (event == MPI2_EVENT_LOG_ENTRY_ADDED) {
6649 6651 sendAEN = TRUE;
6650 6652 }
6651 6653
6652 6654 /*
6653 6655 * Record the event only if it is not masked. Determine which dword
6654 6656 * and bit of event mask to test.
6655 6657 */
6656 6658 i = (uint8_t)(event / 32);
6657 6659 j = (uint8_t)(event % 32);
6658 6660 if ((i < 4) && ((1 << j) & mpt->m_event_mask[i])) {
6659 6661 i = mpt->m_event_index;
6660 6662 mpt->m_events[i].Type = event;
6661 6663 mpt->m_events[i].Number = ++mpt->m_event_number;
6662 6664 bzero(mpt->m_events[i].Data, MPTSAS_MAX_EVENT_DATA_LENGTH * 4);
6663 6665 event_data_len = ddi_get16(mpt->m_acc_reply_frame_hdl,
6664 6666 &eventreply->EventDataLength);
6665 6667
6666 6668 if (event_data_len > 0) {
6667 6669 /*
6668 6670 * Limit data to size in m_event entry
6669 6671 */
6670 6672 if (event_data_len > MPTSAS_MAX_EVENT_DATA_LENGTH) {
6671 6673 event_data_len = MPTSAS_MAX_EVENT_DATA_LENGTH;
6672 6674 }
6673 6675 for (j = 0; j < event_data_len; j++) {
6674 6676 mpt->m_events[i].Data[j] =
6675 6677 ddi_get32(mpt->m_acc_reply_frame_hdl,
6676 6678 &(eventreply->EventData[j]));
6677 6679 }
6678 6680
6679 6681 /*
6680 6682 * check for index wrap-around
6681 6683 */
6682 6684 if (++i == MPTSAS_EVENT_QUEUE_SIZE) {
6683 6685 i = 0;
6684 6686 }
6685 6687 mpt->m_event_index = (uint8_t)i;
6686 6688
6687 6689 /*
6688 6690 * Set flag to send the event.
6689 6691 */
6690 6692 sendAEN = TRUE;
6691 6693 }
6692 6694 }
6693 6695
6694 6696 /*
6695 6697 * Generate a system event if flag is set to let anyone who cares know
6696 6698 * that an event has occurred.
6697 6699 */
6698 6700 if (sendAEN) {
6699 6701 (void) ddi_log_sysevent(mpt->m_dip, DDI_VENDOR_LSI, "MPT_SAS",
6700 6702 "SAS", NULL, NULL, DDI_NOSLEEP);
6701 6703 }
6702 6704 }
6703 6705
6704 6706 #define SMP_RESET_IN_PROGRESS MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS
6705 6707 /*
6706 6708 * handle sync events from ioc in interrupt
6707 6709 * return value:
6708 6710 * DDI_SUCCESS: The event is handled by this func
6709 6711 * DDI_FAILURE: Event is not handled
6710 6712 */
6711 6713 static int
6712 6714 mptsas_handle_event_sync(void *args)
6713 6715 {
6714 6716 m_replyh_arg_t *replyh_arg;
6715 6717 pMpi2EventNotificationReply_t eventreply;
6716 6718 uint32_t event, rfm;
6717 6719 mptsas_t *mpt;
6718 6720 uint_t iocstatus;
6719 6721
6720 6722 replyh_arg = (m_replyh_arg_t *)args;
6721 6723 rfm = replyh_arg->rfm;
6722 6724 mpt = replyh_arg->mpt;
6723 6725
6724 6726 ASSERT(mutex_owned(&mpt->m_mutex));
6725 6727
6726 6728 eventreply = (pMpi2EventNotificationReply_t)
6727 6729 (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr));
6728 6730 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
6729 6731
6730 6732 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
6731 6733 &eventreply->IOCStatus)) {
6732 6734 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
6733 6735 mptsas_log(mpt, CE_WARN,
6734 6736 "!mptsas_handle_event_sync: IOCStatus=0x%x, "
6735 6737 "IOCLogInfo=0x%x", iocstatus,
6736 6738 ddi_get32(mpt->m_acc_reply_frame_hdl,
6737 6739 &eventreply->IOCLogInfo));
6738 6740 } else {
6739 6741 mptsas_log(mpt, CE_WARN,
6740 6742 "mptsas_handle_event_sync: IOCStatus=0x%x, "
6741 6743 "IOCLogInfo=0x%x", iocstatus,
6742 6744 ddi_get32(mpt->m_acc_reply_frame_hdl,
6743 6745 &eventreply->IOCLogInfo));
6744 6746 }
6745 6747 }
6746 6748
6747 6749 /*
6748 6750 * figure out what kind of event we got and handle accordingly
6749 6751 */
6750 6752 switch (event) {
6751 6753 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
6752 6754 {
6753 6755 pMpi2EventDataSasTopologyChangeList_t sas_topo_change_list;
6754 6756 uint8_t num_entries, expstatus, phy;
6755 6757 uint8_t phystatus, physport, state, i;
6756 6758 uint8_t start_phy_num, link_rate;
6757 6759 uint16_t dev_handle, reason_code;
6758 6760 uint16_t enc_handle, expd_handle;
6759 6761 char string[80], curr[80], prev[80];
6760 6762 mptsas_topo_change_list_t *topo_head = NULL;
6761 6763 mptsas_topo_change_list_t *topo_tail = NULL;
6762 6764 mptsas_topo_change_list_t *topo_node = NULL;
6763 6765 mptsas_target_t *ptgt;
6764 6766 mptsas_smp_t *psmp;
6765 6767 mptsas_hash_table_t *tgttbl, *smptbl;
6766 6768 uint8_t flags = 0, exp_flag;
6767 6769 smhba_info_t *pSmhba = NULL;
6768 6770
6769 6771 NDBG20(("mptsas_handle_event_sync: SAS topology change"));
6770 6772
6771 6773 tgttbl = &mpt->m_active->m_tgttbl;
6772 6774 smptbl = &mpt->m_active->m_smptbl;
6773 6775
6774 6776 sas_topo_change_list = (pMpi2EventDataSasTopologyChangeList_t)
6775 6777 eventreply->EventData;
6776 6778
6777 6779 enc_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6778 6780 &sas_topo_change_list->EnclosureHandle);
6779 6781 expd_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6780 6782 &sas_topo_change_list->ExpanderDevHandle);
6781 6783 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl,
6782 6784 &sas_topo_change_list->NumEntries);
6783 6785 start_phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl,
6784 6786 &sas_topo_change_list->StartPhyNum);
6785 6787 expstatus = ddi_get8(mpt->m_acc_reply_frame_hdl,
6786 6788 &sas_topo_change_list->ExpStatus);
6787 6789 physport = ddi_get8(mpt->m_acc_reply_frame_hdl,
6788 6790 &sas_topo_change_list->PhysicalPort);
6789 6791
6790 6792 string[0] = 0;
6791 6793 if (expd_handle) {
6792 6794 flags = MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED;
6793 6795 switch (expstatus) {
6794 6796 case MPI2_EVENT_SAS_TOPO_ES_ADDED:
6795 6797 (void) sprintf(string, " added");
6796 6798 /*
6797 6799 * New expander device added
6798 6800 */
6799 6801 mpt->m_port_chng = 1;
6800 6802 topo_node = kmem_zalloc(
6801 6803 sizeof (mptsas_topo_change_list_t),
6802 6804 KM_SLEEP);
6803 6805 topo_node->mpt = mpt;
6804 6806 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_SMP;
6805 6807 topo_node->un.physport = physport;
6806 6808 topo_node->devhdl = expd_handle;
6807 6809 topo_node->flags = flags;
6808 6810 topo_node->object = NULL;
6809 6811 if (topo_head == NULL) {
6810 6812 topo_head = topo_tail = topo_node;
6811 6813 } else {
6812 6814 topo_tail->next = topo_node;
6813 6815 topo_tail = topo_node;
6814 6816 }
6815 6817 break;
6816 6818 case MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING:
6817 6819 (void) sprintf(string, " not responding, "
6818 6820 "removed");
6819 6821 psmp = mptsas_search_by_devhdl(smptbl,
6820 6822 expd_handle);
6821 6823 if (psmp == NULL)
6822 6824 break;
6823 6825
6824 6826 topo_node = kmem_zalloc(
6825 6827 sizeof (mptsas_topo_change_list_t),
6826 6828 KM_SLEEP);
6827 6829 topo_node->mpt = mpt;
6828 6830 topo_node->un.phymask = psmp->m_phymask;
6829 6831 topo_node->event = MPTSAS_DR_EVENT_OFFLINE_SMP;
6830 6832 topo_node->devhdl = expd_handle;
6831 6833 topo_node->flags = flags;
6832 6834 topo_node->object = NULL;
6833 6835 if (topo_head == NULL) {
6834 6836 topo_head = topo_tail = topo_node;
6835 6837 } else {
6836 6838 topo_tail->next = topo_node;
6837 6839 topo_tail = topo_node;
6838 6840 }
6839 6841 break;
6840 6842 case MPI2_EVENT_SAS_TOPO_ES_RESPONDING:
6841 6843 break;
6842 6844 case MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING:
6843 6845 (void) sprintf(string, " not responding, "
6844 6846 "delaying removal");
6845 6847 break;
6846 6848 default:
6847 6849 break;
6848 6850 }
6849 6851 } else {
6850 6852 flags = MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE;
6851 6853 }
6852 6854
6853 6855 NDBG20(("SAS TOPOLOGY CHANGE for enclosure %x expander %x%s\n",
6854 6856 enc_handle, expd_handle, string));
6855 6857 for (i = 0; i < num_entries; i++) {
6856 6858 phy = i + start_phy_num;
6857 6859 phystatus = ddi_get8(mpt->m_acc_reply_frame_hdl,
6858 6860 &sas_topo_change_list->PHY[i].PhyStatus);
6859 6861 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6860 6862 &sas_topo_change_list->PHY[i].AttachedDevHandle);
6861 6863 reason_code = phystatus & MPI2_EVENT_SAS_TOPO_RC_MASK;
6862 6864 /*
6863 6865 * Filter out processing of Phy Vacant Status unless
6864 6866 * the reason code is "Not Responding". Process all
6865 6867 * other combinations of Phy Status and Reason Codes.
6866 6868 */
6867 6869 if ((phystatus &
6868 6870 MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT) &&
6869 6871 (reason_code !=
6870 6872 MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING)) {
6871 6873 continue;
6872 6874 }
6873 6875 curr[0] = 0;
6874 6876 prev[0] = 0;
6875 6877 string[0] = 0;
6876 6878 switch (reason_code) {
6877 6879 case MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED:
6878 6880 {
6879 6881 NDBG20(("mptsas%d phy %d physical_port %d "
6880 6882 "dev_handle %d added", mpt->m_instance, phy,
6881 6883 physport, dev_handle));
6882 6884 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl,
6883 6885 &sas_topo_change_list->PHY[i].LinkRate);
6884 6886 state = (link_rate &
6885 6887 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >>
6886 6888 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT;
6887 6889 switch (state) {
6888 6890 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
6889 6891 (void) sprintf(curr, "is disabled");
6890 6892 break;
6891 6893 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
6892 6894 (void) sprintf(curr, "is offline, "
6893 6895 "failed speed negotiation");
6894 6896 break;
6895 6897 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
6896 6898 (void) sprintf(curr, "SATA OOB "
6897 6899 "complete");
6898 6900 break;
6899 6901 case SMP_RESET_IN_PROGRESS:
6900 6902 (void) sprintf(curr, "SMP reset in "
6901 6903 "progress");
6902 6904 break;
6903 6905 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
6904 6906 (void) sprintf(curr, "is online at "
6905 6907 "1.5 Gbps");
6906 6908 break;
6907 6909 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
6908 6910 (void) sprintf(curr, "is online at 3.0 "
6909 6911 "Gbps");
6910 6912 break;
6911 6913 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
6912 6914 (void) sprintf(curr, "is online at 6.0 "
6913 6915 "Gbps");
6914 6916 break;
6915 6917 default:
6916 6918 (void) sprintf(curr, "state is "
6917 6919 "unknown");
6918 6920 break;
6919 6921 }
6920 6922 /*
6921 6923 * New target device added into the system.
6922 6924 * Set association flag according to if an
6923 6925 * expander is used or not.
6924 6926 */
6925 6927 exp_flag =
6926 6928 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE;
6927 6929 if (flags ==
6928 6930 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) {
6929 6931 flags = exp_flag;
6930 6932 }
6931 6933 topo_node = kmem_zalloc(
6932 6934 sizeof (mptsas_topo_change_list_t),
6933 6935 KM_SLEEP);
6934 6936 topo_node->mpt = mpt;
6935 6937 topo_node->event =
6936 6938 MPTSAS_DR_EVENT_RECONFIG_TARGET;
6937 6939 if (expd_handle == 0) {
6938 6940 /*
6939 6941 * Per MPI 2, if expander dev handle
6940 6942 * is 0, it's a directly attached
6941 6943 * device. So driver use PHY to decide
6942 6944 * which iport is associated
6943 6945 */
6944 6946 physport = phy;
6945 6947 mpt->m_port_chng = 1;
6946 6948 }
6947 6949 topo_node->un.physport = physport;
6948 6950 topo_node->devhdl = dev_handle;
6949 6951 topo_node->flags = flags;
6950 6952 topo_node->object = NULL;
6951 6953 if (topo_head == NULL) {
6952 6954 topo_head = topo_tail = topo_node;
6953 6955 } else {
6954 6956 topo_tail->next = topo_node;
6955 6957 topo_tail = topo_node;
6956 6958 }
6957 6959 break;
6958 6960 }
6959 6961 case MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING:
6960 6962 {
6961 6963 NDBG20(("mptsas%d phy %d physical_port %d "
6962 6964 "dev_handle %d removed", mpt->m_instance,
6963 6965 phy, physport, dev_handle));
6964 6966 /*
6965 6967 * Set association flag according to if an
6966 6968 * expander is used or not.
6967 6969 */
6968 6970 exp_flag =
6969 6971 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE;
6970 6972 if (flags ==
6971 6973 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) {
6972 6974 flags = exp_flag;
6973 6975 }
6974 6976 /*
6975 6977 * Target device is removed from the system
6976 6978 * Before the device is really offline from
6977 6979 * from system.
6978 6980 */
6979 6981 ptgt = mptsas_search_by_devhdl(tgttbl,
6980 6982 dev_handle);
6981 6983 /*
6982 6984 * If ptgt is NULL here, it means that the
6983 6985 * DevHandle is not in the hash table. This is
6984 6986 * reasonable sometimes. For example, if a
6985 6987 * disk was pulled, then added, then pulled
6986 6988 * again, the disk will not have been put into
6987 6989 * the hash table because the add event will
6988 6990 * have an invalid phymask. BUT, this does not
6989 6991 * mean that the DevHandle is invalid. The
6990 6992 * controller will still have a valid DevHandle
6991 6993 * that must be removed. To do this, use the
6992 6994 * MPTSAS_TOPO_FLAG_REMOVE_HANDLE event.
6993 6995 */
6994 6996 if (ptgt == NULL) {
6995 6997 topo_node = kmem_zalloc(
6996 6998 sizeof (mptsas_topo_change_list_t),
6997 6999 KM_SLEEP);
6998 7000 topo_node->mpt = mpt;
6999 7001 topo_node->un.phymask = 0;
7000 7002 topo_node->event =
7001 7003 MPTSAS_TOPO_FLAG_REMOVE_HANDLE;
7002 7004 topo_node->devhdl = dev_handle;
7003 7005 topo_node->flags = flags;
7004 7006 topo_node->object = NULL;
7005 7007 if (topo_head == NULL) {
7006 7008 topo_head = topo_tail =
7007 7009 topo_node;
7008 7010 } else {
7009 7011 topo_tail->next = topo_node;
7010 7012 topo_tail = topo_node;
7011 7013 }
7012 7014 break;
7013 7015 }
7014 7016
7015 7017 /*
7016 7018 * Update DR flag immediately avoid I/O failure
7017 7019 * before failover finish. Pay attention to the
7018 7020 * mutex protect, we need grab the per target
7019 7021 * mutex during set m_dr_flag because the
7020 7022 * m_mutex would not be held all the time in
7021 7023 * mptsas_scsi_start().
7022 7024 */
7023 7025 mutex_enter(&ptgt->m_tgt_intr_mutex);
7024 7026 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
7025 7027 mutex_exit(&ptgt->m_tgt_intr_mutex);
7026 7028
7027 7029 topo_node = kmem_zalloc(
7028 7030 sizeof (mptsas_topo_change_list_t),
7029 7031 KM_SLEEP);
7030 7032 topo_node->mpt = mpt;
7031 7033 topo_node->un.phymask = ptgt->m_phymask;
7032 7034 topo_node->event =
7033 7035 MPTSAS_DR_EVENT_OFFLINE_TARGET;
7034 7036 topo_node->devhdl = dev_handle;
7035 7037 topo_node->flags = flags;
7036 7038 topo_node->object = NULL;
7037 7039 if (topo_head == NULL) {
7038 7040 topo_head = topo_tail = topo_node;
7039 7041 } else {
7040 7042 topo_tail->next = topo_node;
7041 7043 topo_tail = topo_node;
7042 7044 }
7043 7045 break;
7044 7046 }
7045 7047 case MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED:
7046 7048 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl,
7047 7049 &sas_topo_change_list->PHY[i].LinkRate);
7048 7050 state = (link_rate &
7049 7051 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >>
7050 7052 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT;
7051 7053 pSmhba = &mpt->m_phy_info[i].smhba_info;
7052 7054 pSmhba->negotiated_link_rate = state;
7053 7055 switch (state) {
7054 7056 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
7055 7057 (void) sprintf(curr, "is disabled");
7056 7058 mptsas_smhba_log_sysevent(mpt,
7057 7059 ESC_SAS_PHY_EVENT,
7058 7060 SAS_PHY_REMOVE,
7059 7061 &mpt->m_phy_info[i].smhba_info);
7060 7062 mpt->m_phy_info[i].smhba_info.
7061 7063 negotiated_link_rate
7062 7064 = 0x1;
7063 7065 break;
7064 7066 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
7065 7067 (void) sprintf(curr, "is offline, "
7066 7068 "failed speed negotiation");
7067 7069 mptsas_smhba_log_sysevent(mpt,
7068 7070 ESC_SAS_PHY_EVENT,
7069 7071 SAS_PHY_OFFLINE,
7070 7072 &mpt->m_phy_info[i].smhba_info);
7071 7073 break;
7072 7074 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
7073 7075 (void) sprintf(curr, "SATA OOB "
7074 7076 "complete");
7075 7077 break;
7076 7078 case SMP_RESET_IN_PROGRESS:
7077 7079 (void) sprintf(curr, "SMP reset in "
7078 7080 "progress");
7079 7081 break;
7080 7082 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
7081 7083 (void) sprintf(curr, "is online at "
7082 7084 "1.5 Gbps");
7083 7085 if ((expd_handle == 0) &&
7084 7086 (enc_handle == 1)) {
7085 7087 mpt->m_port_chng = 1;
7086 7088 }
7087 7089 mptsas_smhba_log_sysevent(mpt,
7088 7090 ESC_SAS_PHY_EVENT,
7089 7091 SAS_PHY_ONLINE,
7090 7092 &mpt->m_phy_info[i].smhba_info);
7091 7093 break;
7092 7094 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
7093 7095 (void) sprintf(curr, "is online at 3.0 "
7094 7096 "Gbps");
7095 7097 if ((expd_handle == 0) &&
7096 7098 (enc_handle == 1)) {
7097 7099 mpt->m_port_chng = 1;
7098 7100 }
7099 7101 mptsas_smhba_log_sysevent(mpt,
7100 7102 ESC_SAS_PHY_EVENT,
7101 7103 SAS_PHY_ONLINE,
7102 7104 &mpt->m_phy_info[i].smhba_info);
7103 7105 break;
7104 7106 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
7105 7107 (void) sprintf(curr, "is online at "
7106 7108 "6.0 Gbps");
7107 7109 if ((expd_handle == 0) &&
7108 7110 (enc_handle == 1)) {
7109 7111 mpt->m_port_chng = 1;
7110 7112 }
7111 7113 mptsas_smhba_log_sysevent(mpt,
7112 7114 ESC_SAS_PHY_EVENT,
7113 7115 SAS_PHY_ONLINE,
7114 7116 &mpt->m_phy_info[i].smhba_info);
7115 7117 break;
7116 7118 default:
7117 7119 (void) sprintf(curr, "state is "
7118 7120 "unknown");
7119 7121 break;
7120 7122 }
7121 7123
7122 7124 state = (link_rate &
7123 7125 MPI2_EVENT_SAS_TOPO_LR_PREV_MASK) >>
7124 7126 MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT;
7125 7127 switch (state) {
7126 7128 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
7127 7129 (void) sprintf(prev, ", was disabled");
7128 7130 break;
7129 7131 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
7130 7132 (void) sprintf(prev, ", was offline, "
7131 7133 "failed speed negotiation");
7132 7134 break;
7133 7135 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
7134 7136 (void) sprintf(prev, ", was SATA OOB "
7135 7137 "complete");
7136 7138 break;
7137 7139 case SMP_RESET_IN_PROGRESS:
7138 7140 (void) sprintf(prev, ", was SMP reset "
7139 7141 "in progress");
7140 7142 break;
7141 7143 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
7142 7144 (void) sprintf(prev, ", was online at "
7143 7145 "1.5 Gbps");
7144 7146 break;
7145 7147 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
7146 7148 (void) sprintf(prev, ", was online at "
7147 7149 "3.0 Gbps");
7148 7150 break;
7149 7151 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
7150 7152 (void) sprintf(prev, ", was online at "
7151 7153 "6.0 Gbps");
7152 7154 break;
7153 7155 default:
7154 7156 break;
7155 7157 }
7156 7158 (void) sprintf(&string[strlen(string)], "link "
7157 7159 "changed, ");
7158 7160 break;
7159 7161 case MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE:
7160 7162 continue;
7161 7163 case MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING:
7162 7164 (void) sprintf(&string[strlen(string)],
7163 7165 "target not responding, delaying "
7164 7166 "removal");
7165 7167 break;
7166 7168 }
7167 7169 NDBG20(("mptsas%d phy %d DevHandle %x, %s%s%s\n",
7168 7170 mpt->m_instance, phy, dev_handle, string, curr,
7169 7171 prev));
7170 7172 }
7171 7173 if (topo_head != NULL) {
7172 7174 /*
7173 7175 * Launch DR taskq to handle topology change
7174 7176 */
7175 7177 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
7176 7178 mptsas_handle_dr, (void *)topo_head,
7177 7179 DDI_NOSLEEP)) != DDI_SUCCESS) {
7178 7180 mptsas_log(mpt, CE_NOTE, "mptsas start taskq "
7179 7181 "for handle SAS DR event failed. \n");
7180 7182 }
7181 7183 }
7182 7184 break;
7183 7185 }
7184 7186 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
7185 7187 {
7186 7188 Mpi2EventDataIrConfigChangeList_t *irChangeList;
7187 7189 mptsas_topo_change_list_t *topo_head = NULL;
7188 7190 mptsas_topo_change_list_t *topo_tail = NULL;
7189 7191 mptsas_topo_change_list_t *topo_node = NULL;
7190 7192 mptsas_target_t *ptgt;
7191 7193 mptsas_hash_table_t *tgttbl;
7192 7194 uint8_t num_entries, i, reason;
7193 7195 uint16_t volhandle, diskhandle;
7194 7196
7195 7197 irChangeList = (pMpi2EventDataIrConfigChangeList_t)
7196 7198 eventreply->EventData;
7197 7199 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl,
7198 7200 &irChangeList->NumElements);
7199 7201
7200 7202 tgttbl = &mpt->m_active->m_tgttbl;
7201 7203
7202 7204 NDBG20(("mptsas%d IR_CONFIGURATION_CHANGE_LIST event received",
7203 7205 mpt->m_instance));
7204 7206
7205 7207 for (i = 0; i < num_entries; i++) {
7206 7208 reason = ddi_get8(mpt->m_acc_reply_frame_hdl,
7207 7209 &irChangeList->ConfigElement[i].ReasonCode);
7208 7210 volhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7209 7211 &irChangeList->ConfigElement[i].VolDevHandle);
7210 7212 diskhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7211 7213 &irChangeList->ConfigElement[i].PhysDiskDevHandle);
7212 7214
7213 7215 switch (reason) {
7214 7216 case MPI2_EVENT_IR_CHANGE_RC_ADDED:
7215 7217 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED:
7216 7218 {
7217 7219 NDBG20(("mptsas %d volume added\n",
7218 7220 mpt->m_instance));
7219 7221
7220 7222 topo_node = kmem_zalloc(
7221 7223 sizeof (mptsas_topo_change_list_t),
7222 7224 KM_SLEEP);
7223 7225
7224 7226 topo_node->mpt = mpt;
7225 7227 topo_node->event =
7226 7228 MPTSAS_DR_EVENT_RECONFIG_TARGET;
7227 7229 topo_node->un.physport = 0xff;
7228 7230 topo_node->devhdl = volhandle;
7229 7231 topo_node->flags =
7230 7232 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED;
7231 7233 topo_node->object = NULL;
7232 7234 if (topo_head == NULL) {
7233 7235 topo_head = topo_tail = topo_node;
7234 7236 } else {
7235 7237 topo_tail->next = topo_node;
7236 7238 topo_tail = topo_node;
7237 7239 }
7238 7240 break;
7239 7241 }
7240 7242 case MPI2_EVENT_IR_CHANGE_RC_REMOVED:
7241 7243 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED:
7242 7244 {
7243 7245 NDBG20(("mptsas %d volume deleted\n",
7244 7246 mpt->m_instance));
7245 7247 ptgt = mptsas_search_by_devhdl(tgttbl,
7246 7248 volhandle);
7247 7249 if (ptgt == NULL)
7248 7250 break;
7249 7251
7250 7252 /*
7251 7253 * Clear any flags related to volume
7252 7254 */
7253 7255 (void) mptsas_delete_volume(mpt, volhandle);
7254 7256
7255 7257 /*
7256 7258 * Update DR flag immediately avoid I/O failure
7257 7259 */
7258 7260 mutex_enter(&ptgt->m_tgt_intr_mutex);
7259 7261 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
7260 7262 mutex_exit(&ptgt->m_tgt_intr_mutex);
7261 7263
7262 7264 topo_node = kmem_zalloc(
7263 7265 sizeof (mptsas_topo_change_list_t),
7264 7266 KM_SLEEP);
7265 7267 topo_node->mpt = mpt;
7266 7268 topo_node->un.phymask = ptgt->m_phymask;
7267 7269 topo_node->event =
7268 7270 MPTSAS_DR_EVENT_OFFLINE_TARGET;
7269 7271 topo_node->devhdl = volhandle;
7270 7272 topo_node->flags =
7271 7273 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED;
7272 7274 topo_node->object = (void *)ptgt;
7273 7275 if (topo_head == NULL) {
7274 7276 topo_head = topo_tail = topo_node;
7275 7277 } else {
7276 7278 topo_tail->next = topo_node;
7277 7279 topo_tail = topo_node;
7278 7280 }
7279 7281 break;
7280 7282 }
7281 7283 case MPI2_EVENT_IR_CHANGE_RC_PD_CREATED:
7282 7284 case MPI2_EVENT_IR_CHANGE_RC_HIDE:
7283 7285 {
7284 7286 ptgt = mptsas_search_by_devhdl(tgttbl,
7285 7287 diskhandle);
7286 7288 if (ptgt == NULL)
7287 7289 break;
7288 7290
7289 7291 /*
7290 7292 * Update DR flag immediately avoid I/O failure
7291 7293 */
7292 7294 mutex_enter(&ptgt->m_tgt_intr_mutex);
7293 7295 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
7294 7296 mutex_exit(&ptgt->m_tgt_intr_mutex);
7295 7297
7296 7298 topo_node = kmem_zalloc(
7297 7299 sizeof (mptsas_topo_change_list_t),
7298 7300 KM_SLEEP);
7299 7301 topo_node->mpt = mpt;
7300 7302 topo_node->un.phymask = ptgt->m_phymask;
7301 7303 topo_node->event =
7302 7304 MPTSAS_DR_EVENT_OFFLINE_TARGET;
7303 7305 topo_node->devhdl = diskhandle;
7304 7306 topo_node->flags =
7305 7307 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED;
7306 7308 topo_node->object = (void *)ptgt;
7307 7309 if (topo_head == NULL) {
7308 7310 topo_head = topo_tail = topo_node;
7309 7311 } else {
7310 7312 topo_tail->next = topo_node;
7311 7313 topo_tail = topo_node;
7312 7314 }
7313 7315 break;
7314 7316 }
7315 7317 case MPI2_EVENT_IR_CHANGE_RC_UNHIDE:
7316 7318 case MPI2_EVENT_IR_CHANGE_RC_PD_DELETED:
7317 7319 {
7318 7320 /*
7319 7321 * The physical drive is released by a IR
7320 7322 * volume. But we cannot get the the physport
7321 7323 * or phynum from the event data, so we only
7322 7324 * can get the physport/phynum after SAS
7323 7325 * Device Page0 request for the devhdl.
7324 7326 */
7325 7327 topo_node = kmem_zalloc(
7326 7328 sizeof (mptsas_topo_change_list_t),
7327 7329 KM_SLEEP);
7328 7330 topo_node->mpt = mpt;
7329 7331 topo_node->un.phymask = 0;
7330 7332 topo_node->event =
7331 7333 MPTSAS_DR_EVENT_RECONFIG_TARGET;
7332 7334 topo_node->devhdl = diskhandle;
7333 7335 topo_node->flags =
7334 7336 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED;
7335 7337 topo_node->object = NULL;
7336 7338 mpt->m_port_chng = 1;
7337 7339 if (topo_head == NULL) {
7338 7340 topo_head = topo_tail = topo_node;
7339 7341 } else {
7340 7342 topo_tail->next = topo_node;
7341 7343 topo_tail = topo_node;
7342 7344 }
7343 7345 break;
7344 7346 }
7345 7347 default:
7346 7348 break;
7347 7349 }
7348 7350 }
7349 7351
7350 7352 if (topo_head != NULL) {
7351 7353 /*
7352 7354 * Launch DR taskq to handle topology change
7353 7355 */
7354 7356 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
7355 7357 mptsas_handle_dr, (void *)topo_head,
7356 7358 DDI_NOSLEEP)) != DDI_SUCCESS) {
7357 7359 mptsas_log(mpt, CE_NOTE, "mptsas start taskq "
7358 7360 "for handle SAS DR event failed. \n");
7359 7361 }
7360 7362 }
7361 7363 break;
7362 7364 }
7363 7365 default:
7364 7366 return (DDI_FAILURE);
7365 7367 }
7366 7368
7367 7369 return (DDI_SUCCESS);
7368 7370 }
7369 7371
7370 7372 /*
7371 7373 * handle events from ioc
7372 7374 */
7373 7375 static void
7374 7376 mptsas_handle_event(void *args)
7375 7377 {
7376 7378 m_replyh_arg_t *replyh_arg;
7377 7379 pMpi2EventNotificationReply_t eventreply;
7378 7380 uint32_t event, iocloginfo, rfm;
7379 7381 uint32_t status;
7380 7382 uint8_t port;
7381 7383 mptsas_t *mpt;
7382 7384 uint_t iocstatus;
7383 7385
7384 7386 replyh_arg = (m_replyh_arg_t *)args;
7385 7387 rfm = replyh_arg->rfm;
7386 7388 mpt = replyh_arg->mpt;
7387 7389
7388 7390 mutex_enter(&mpt->m_mutex);
7389 7391
7390 7392 eventreply = (pMpi2EventNotificationReply_t)
7391 7393 (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr));
7392 7394 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
7393 7395
7394 7396 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
7395 7397 &eventreply->IOCStatus)) {
7396 7398 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
7397 7399 mptsas_log(mpt, CE_WARN,
7398 7400 "!mptsas_handle_event: IOCStatus=0x%x, "
7399 7401 "IOCLogInfo=0x%x", iocstatus,
7400 7402 ddi_get32(mpt->m_acc_reply_frame_hdl,
7401 7403 &eventreply->IOCLogInfo));
7402 7404 } else {
7403 7405 mptsas_log(mpt, CE_WARN,
7404 7406 "mptsas_handle_event: IOCStatus=0x%x, "
7405 7407 "IOCLogInfo=0x%x", iocstatus,
7406 7408 ddi_get32(mpt->m_acc_reply_frame_hdl,
7407 7409 &eventreply->IOCLogInfo));
7408 7410 }
7409 7411 }
7410 7412
7411 7413 /*
7412 7414 * figure out what kind of event we got and handle accordingly
7413 7415 */
7414 7416 switch (event) {
7415 7417 case MPI2_EVENT_LOG_ENTRY_ADDED:
7416 7418 break;
7417 7419 case MPI2_EVENT_LOG_DATA:
7418 7420 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
7419 7421 &eventreply->IOCLogInfo);
7420 7422 NDBG20(("mptsas %d log info %x received.\n", mpt->m_instance,
7421 7423 iocloginfo));
7422 7424 break;
7423 7425 case MPI2_EVENT_STATE_CHANGE:
7424 7426 NDBG20(("mptsas%d state change.", mpt->m_instance));
7425 7427 break;
7426 7428 case MPI2_EVENT_HARD_RESET_RECEIVED:
7427 7429 NDBG20(("mptsas%d event change.", mpt->m_instance));
7428 7430 break;
7429 7431 case MPI2_EVENT_SAS_DISCOVERY:
7430 7432 {
7431 7433 MPI2_EVENT_DATA_SAS_DISCOVERY *sasdiscovery;
7432 7434 char string[80];
7433 7435 uint8_t rc;
7434 7436
7435 7437 sasdiscovery =
7436 7438 (pMpi2EventDataSasDiscovery_t)eventreply->EventData;
7437 7439
7438 7440 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7439 7441 &sasdiscovery->ReasonCode);
7440 7442 port = ddi_get8(mpt->m_acc_reply_frame_hdl,
7441 7443 &sasdiscovery->PhysicalPort);
7442 7444 status = ddi_get32(mpt->m_acc_reply_frame_hdl,
7443 7445 &sasdiscovery->DiscoveryStatus);
7444 7446
7445 7447 string[0] = 0;
7446 7448 switch (rc) {
7447 7449 case MPI2_EVENT_SAS_DISC_RC_STARTED:
7448 7450 (void) sprintf(string, "STARTING");
7449 7451 break;
7450 7452 case MPI2_EVENT_SAS_DISC_RC_COMPLETED:
7451 7453 (void) sprintf(string, "COMPLETED");
7452 7454 break;
7453 7455 default:
7454 7456 (void) sprintf(string, "UNKNOWN");
7455 7457 break;
7456 7458 }
7457 7459
7458 7460 NDBG20(("SAS DISCOVERY is %s for port %d, status %x", string,
7459 7461 port, status));
7460 7462
7461 7463 break;
7462 7464 }
7463 7465 case MPI2_EVENT_EVENT_CHANGE:
7464 7466 NDBG20(("mptsas%d event change.", mpt->m_instance));
7465 7467 break;
7466 7468 case MPI2_EVENT_TASK_SET_FULL:
7467 7469 {
7468 7470 pMpi2EventDataTaskSetFull_t taskfull;
7469 7471
7470 7472 taskfull = (pMpi2EventDataTaskSetFull_t)eventreply->EventData;
7471 7473
7472 7474 NDBG20(("TASK_SET_FULL received for mptsas%d, depth %d\n",
7473 7475 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl,
7474 7476 &taskfull->CurrentDepth)));
7475 7477 break;
7476 7478 }
7477 7479 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
7478 7480 {
7479 7481 /*
7480 7482 * SAS TOPOLOGY CHANGE LIST Event has already been handled
7481 7483 * in mptsas_handle_event_sync() of interrupt context
7482 7484 */
7483 7485 break;
7484 7486 }
7485 7487 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
7486 7488 {
7487 7489 pMpi2EventDataSasEnclDevStatusChange_t encstatus;
7488 7490 uint8_t rc;
7489 7491 char string[80];
7490 7492
7491 7493 encstatus = (pMpi2EventDataSasEnclDevStatusChange_t)
7492 7494 eventreply->EventData;
7493 7495
7494 7496 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7495 7497 &encstatus->ReasonCode);
7496 7498 switch (rc) {
7497 7499 case MPI2_EVENT_SAS_ENCL_RC_ADDED:
7498 7500 (void) sprintf(string, "added");
7499 7501 break;
7500 7502 case MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING:
7501 7503 (void) sprintf(string, ", not responding");
7502 7504 break;
7503 7505 default:
7504 7506 break;
7505 7507 }
7506 7508 NDBG20(("mptsas%d ENCLOSURE STATUS CHANGE for enclosure %x%s\n",
7507 7509 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl,
7508 7510 &encstatus->EnclosureHandle), string));
7509 7511 break;
7510 7512 }
7511 7513
7512 7514 /*
7513 7515 * MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE is handled by
7514 7516 * mptsas_handle_event_sync,in here just send ack message.
7515 7517 */
7516 7518 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
7517 7519 {
7518 7520 pMpi2EventDataSasDeviceStatusChange_t statuschange;
7519 7521 uint8_t rc;
7520 7522 uint16_t devhdl;
7521 7523 uint64_t wwn = 0;
7522 7524 uint32_t wwn_lo, wwn_hi;
7523 7525
7524 7526 statuschange = (pMpi2EventDataSasDeviceStatusChange_t)
7525 7527 eventreply->EventData;
7526 7528 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7527 7529 &statuschange->ReasonCode);
7528 7530 wwn_lo = ddi_get32(mpt->m_acc_reply_frame_hdl,
7529 7531 (uint32_t *)(void *)&statuschange->SASAddress);
7530 7532 wwn_hi = ddi_get32(mpt->m_acc_reply_frame_hdl,
7531 7533 (uint32_t *)(void *)&statuschange->SASAddress + 1);
7532 7534 wwn = ((uint64_t)wwn_hi << 32) | wwn_lo;
7533 7535 devhdl = ddi_get16(mpt->m_acc_reply_frame_hdl,
7534 7536 &statuschange->DevHandle);
7535 7537
7536 7538 NDBG13(("MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE wwn is %"PRIx64,
7537 7539 wwn));
7538 7540
7539 7541 switch (rc) {
7540 7542 case MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA:
7541 7543 NDBG20(("SMART data received, ASC/ASCQ = %02x/%02x",
7542 7544 ddi_get8(mpt->m_acc_reply_frame_hdl,
7543 7545 &statuschange->ASC),
7544 7546 ddi_get8(mpt->m_acc_reply_frame_hdl,
7545 7547 &statuschange->ASCQ)));
7546 7548 break;
7547 7549
7548 7550 case MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED:
7549 7551 NDBG20(("Device not supported"));
7550 7552 break;
7551 7553
7552 7554 case MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET:
7553 7555 NDBG20(("IOC internally generated the Target Reset "
7554 7556 "for devhdl:%x", devhdl));
7555 7557 break;
7556 7558
7557 7559 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET:
7558 7560 NDBG20(("IOC's internally generated Target Reset "
7559 7561 "completed for devhdl:%x", devhdl));
7560 7562 break;
7561 7563
7562 7564 case MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL:
7563 7565 NDBG20(("IOC internally generated Abort Task"));
7564 7566 break;
7565 7567
7566 7568 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL:
7567 7569 NDBG20(("IOC's internally generated Abort Task "
7568 7570 "completed"));
7569 7571 break;
7570 7572
7571 7573 case MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL:
7572 7574 NDBG20(("IOC internally generated Abort Task Set"));
7573 7575 break;
7574 7576
7575 7577 case MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL:
7576 7578 NDBG20(("IOC internally generated Clear Task Set"));
7577 7579 break;
7578 7580
7579 7581 case MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL:
7580 7582 NDBG20(("IOC internally generated Query Task"));
7581 7583 break;
7582 7584
7583 7585 case MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION:
7584 7586 NDBG20(("Device sent an Asynchronous Notification"));
7585 7587 break;
7586 7588
7587 7589 default:
7588 7590 break;
7589 7591 }
7590 7592 break;
7591 7593 }
7592 7594 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
7593 7595 {
7594 7596 /*
7595 7597 * IR TOPOLOGY CHANGE LIST Event has already been handled
7596 7598 * in mpt_handle_event_sync() of interrupt context
7597 7599 */
7598 7600 break;
7599 7601 }
7600 7602 case MPI2_EVENT_IR_OPERATION_STATUS:
7601 7603 {
7602 7604 Mpi2EventDataIrOperationStatus_t *irOpStatus;
7603 7605 char reason_str[80];
7604 7606 uint8_t rc, percent;
7605 7607 uint16_t handle;
7606 7608
7607 7609 irOpStatus = (pMpi2EventDataIrOperationStatus_t)
7608 7610 eventreply->EventData;
7609 7611 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7610 7612 &irOpStatus->RAIDOperation);
7611 7613 percent = ddi_get8(mpt->m_acc_reply_frame_hdl,
7612 7614 &irOpStatus->PercentComplete);
7613 7615 handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7614 7616 &irOpStatus->VolDevHandle);
7615 7617
7616 7618 switch (rc) {
7617 7619 case MPI2_EVENT_IR_RAIDOP_RESYNC:
7618 7620 (void) sprintf(reason_str, "resync");
7619 7621 break;
7620 7622 case MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION:
7621 7623 (void) sprintf(reason_str, "online capacity "
7622 7624 "expansion");
7623 7625 break;
7624 7626 case MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK:
7625 7627 (void) sprintf(reason_str, "consistency check");
7626 7628 break;
7627 7629 default:
7628 7630 (void) sprintf(reason_str, "unknown reason %x",
7629 7631 rc);
7630 7632 }
7631 7633
7632 7634 NDBG20(("mptsas%d raid operational status: (%s)"
7633 7635 "\thandle(0x%04x), percent complete(%d)\n",
7634 7636 mpt->m_instance, reason_str, handle, percent));
7635 7637 break;
7636 7638 }
7637 7639 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
7638 7640 {
7639 7641 pMpi2EventDataSasBroadcastPrimitive_t sas_broadcast;
7640 7642 uint8_t phy_num;
7641 7643 uint8_t primitive;
7642 7644
7643 7645 sas_broadcast = (pMpi2EventDataSasBroadcastPrimitive_t)
7644 7646 eventreply->EventData;
7645 7647
7646 7648 phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl,
7647 7649 &sas_broadcast->PhyNum);
7648 7650 primitive = ddi_get8(mpt->m_acc_reply_frame_hdl,
7649 7651 &sas_broadcast->Primitive);
7650 7652
7651 7653 switch (primitive) {
7652 7654 case MPI2_EVENT_PRIMITIVE_CHANGE:
7653 7655 mptsas_smhba_log_sysevent(mpt,
7654 7656 ESC_SAS_HBA_PORT_BROADCAST,
7655 7657 SAS_PORT_BROADCAST_CHANGE,
7656 7658 &mpt->m_phy_info[phy_num].smhba_info);
7657 7659 break;
7658 7660 case MPI2_EVENT_PRIMITIVE_SES:
7659 7661 mptsas_smhba_log_sysevent(mpt,
7660 7662 ESC_SAS_HBA_PORT_BROADCAST,
7661 7663 SAS_PORT_BROADCAST_SES,
7662 7664 &mpt->m_phy_info[phy_num].smhba_info);
7663 7665 break;
7664 7666 case MPI2_EVENT_PRIMITIVE_EXPANDER:
7665 7667 mptsas_smhba_log_sysevent(mpt,
7666 7668 ESC_SAS_HBA_PORT_BROADCAST,
7667 7669 SAS_PORT_BROADCAST_D01_4,
7668 7670 &mpt->m_phy_info[phy_num].smhba_info);
7669 7671 break;
7670 7672 case MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT:
7671 7673 mptsas_smhba_log_sysevent(mpt,
7672 7674 ESC_SAS_HBA_PORT_BROADCAST,
7673 7675 SAS_PORT_BROADCAST_D04_7,
7674 7676 &mpt->m_phy_info[phy_num].smhba_info);
7675 7677 break;
7676 7678 case MPI2_EVENT_PRIMITIVE_RESERVED3:
7677 7679 mptsas_smhba_log_sysevent(mpt,
7678 7680 ESC_SAS_HBA_PORT_BROADCAST,
7679 7681 SAS_PORT_BROADCAST_D16_7,
7680 7682 &mpt->m_phy_info[phy_num].smhba_info);
7681 7683 break;
7682 7684 case MPI2_EVENT_PRIMITIVE_RESERVED4:
7683 7685 mptsas_smhba_log_sysevent(mpt,
7684 7686 ESC_SAS_HBA_PORT_BROADCAST,
7685 7687 SAS_PORT_BROADCAST_D29_7,
7686 7688 &mpt->m_phy_info[phy_num].smhba_info);
7687 7689 break;
7688 7690 case MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED:
7689 7691 mptsas_smhba_log_sysevent(mpt,
7690 7692 ESC_SAS_HBA_PORT_BROADCAST,
7691 7693 SAS_PORT_BROADCAST_D24_0,
7692 7694 &mpt->m_phy_info[phy_num].smhba_info);
7693 7695 break;
7694 7696 case MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED:
7695 7697 mptsas_smhba_log_sysevent(mpt,
7696 7698 ESC_SAS_HBA_PORT_BROADCAST,
7697 7699 SAS_PORT_BROADCAST_D27_4,
7698 7700 &mpt->m_phy_info[phy_num].smhba_info);
7699 7701 break;
7700 7702 default:
7701 7703 NDBG20(("mptsas%d: unknown BROADCAST PRIMITIVE"
7702 7704 " %x received",
7703 7705 mpt->m_instance, primitive));
7704 7706 break;
7705 7707 }
7706 7708 NDBG20(("mptsas%d sas broadcast primitive: "
7707 7709 "\tprimitive(0x%04x), phy(%d) complete\n",
7708 7710 mpt->m_instance, primitive, phy_num));
7709 7711 break;
7710 7712 }
7711 7713 case MPI2_EVENT_IR_VOLUME:
7712 7714 {
7713 7715 Mpi2EventDataIrVolume_t *irVolume;
7714 7716 uint16_t devhandle;
7715 7717 uint32_t state;
7716 7718 int config, vol;
7717 7719 mptsas_slots_t *slots = mpt->m_active;
7718 7720 uint8_t found = FALSE;
7719 7721
7720 7722 irVolume = (pMpi2EventDataIrVolume_t)eventreply->EventData;
7721 7723 state = ddi_get32(mpt->m_acc_reply_frame_hdl,
7722 7724 &irVolume->NewValue);
7723 7725 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7724 7726 &irVolume->VolDevHandle);
7725 7727
7726 7728 NDBG20(("EVENT_IR_VOLUME event is received"));
7727 7729
7728 7730 /*
7729 7731 * Get latest RAID info and then find the DevHandle for this
7730 7732 * event in the configuration. If the DevHandle is not found
7731 7733 * just exit the event.
7732 7734 */
7733 7735 (void) mptsas_get_raid_info(mpt);
7734 7736 for (config = 0; (config < slots->m_num_raid_configs) &&
7735 7737 (!found); config++) {
7736 7738 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) {
7737 7739 if (slots->m_raidconfig[config].m_raidvol[vol].
7738 7740 m_raidhandle == devhandle) {
7739 7741 found = TRUE;
7740 7742 break;
7741 7743 }
7742 7744 }
7743 7745 }
7744 7746 if (!found) {
7745 7747 break;
7746 7748 }
7747 7749
7748 7750 switch (irVolume->ReasonCode) {
7749 7751 case MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED:
7750 7752 {
7751 7753 uint32_t i;
7752 7754 slots->m_raidconfig[config].m_raidvol[vol].m_settings =
7753 7755 state;
7754 7756
7755 7757 i = state & MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING;
7756 7758 mptsas_log(mpt, CE_NOTE, " Volume %d settings changed"
7757 7759 ", auto-config of hot-swap drives is %s"
7758 7760 ", write caching is %s"
7759 7761 ", hot-spare pool mask is %02x\n",
7760 7762 vol, state &
7761 7763 MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE
7762 7764 ? "disabled" : "enabled",
7763 7765 i == MPI2_RAIDVOL0_SETTING_UNCHANGED
7764 7766 ? "controlled by member disks" :
7765 7767 i == MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING
7766 7768 ? "disabled" :
7767 7769 i == MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING
7768 7770 ? "enabled" :
7769 7771 "incorrectly set",
7770 7772 (state >> 16) & 0xff);
7771 7773 break;
7772 7774 }
7773 7775 case MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED:
7774 7776 {
7775 7777 slots->m_raidconfig[config].m_raidvol[vol].m_state =
7776 7778 (uint8_t)state;
7777 7779
7778 7780 mptsas_log(mpt, CE_NOTE,
7779 7781 "Volume %d is now %s\n", vol,
7780 7782 state == MPI2_RAID_VOL_STATE_OPTIMAL
7781 7783 ? "optimal" :
7782 7784 state == MPI2_RAID_VOL_STATE_DEGRADED
7783 7785 ? "degraded" :
7784 7786 state == MPI2_RAID_VOL_STATE_ONLINE
7785 7787 ? "online" :
7786 7788 state == MPI2_RAID_VOL_STATE_INITIALIZING
7787 7789 ? "initializing" :
7788 7790 state == MPI2_RAID_VOL_STATE_FAILED
7789 7791 ? "failed" :
7790 7792 state == MPI2_RAID_VOL_STATE_MISSING
7791 7793 ? "missing" :
7792 7794 "state unknown");
7793 7795 break;
7794 7796 }
7795 7797 case MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED:
7796 7798 {
7797 7799 slots->m_raidconfig[config].m_raidvol[vol].
7798 7800 m_statusflags = state;
7799 7801
7800 7802 mptsas_log(mpt, CE_NOTE,
7801 7803 " Volume %d is now %s%s%s%s%s%s%s%s%s\n",
7802 7804 vol,
7803 7805 state & MPI2_RAIDVOL0_STATUS_FLAG_ENABLED
7804 7806 ? ", enabled" : ", disabled",
7805 7807 state & MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED
7806 7808 ? ", quiesced" : "",
7807 7809 state & MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE
7808 7810 ? ", inactive" : ", active",
7809 7811 state &
7810 7812 MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL
7811 7813 ? ", bad block table is full" : "",
7812 7814 state &
7813 7815 MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS
7814 7816 ? ", resync in progress" : "",
7815 7817 state & MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT
7816 7818 ? ", background initialization in progress" : "",
7817 7819 state &
7818 7820 MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION
7819 7821 ? ", capacity expansion in progress" : "",
7820 7822 state &
7821 7823 MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK
7822 7824 ? ", consistency check in progress" : "",
7823 7825 state & MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB
7824 7826 ? ", data scrub in progress" : "");
7825 7827 break;
7826 7828 }
7827 7829 default:
7828 7830 break;
7829 7831 }
7830 7832 break;
7831 7833 }
7832 7834 case MPI2_EVENT_IR_PHYSICAL_DISK:
7833 7835 {
7834 7836 Mpi2EventDataIrPhysicalDisk_t *irPhysDisk;
7835 7837 uint16_t devhandle, enchandle, slot;
7836 7838 uint32_t status, state;
7837 7839 uint8_t physdisknum, reason;
7838 7840
7839 7841 irPhysDisk = (Mpi2EventDataIrPhysicalDisk_t *)
7840 7842 eventreply->EventData;
7841 7843 physdisknum = ddi_get8(mpt->m_acc_reply_frame_hdl,
7842 7844 &irPhysDisk->PhysDiskNum);
7843 7845 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7844 7846 &irPhysDisk->PhysDiskDevHandle);
7845 7847 enchandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7846 7848 &irPhysDisk->EnclosureHandle);
7847 7849 slot = ddi_get16(mpt->m_acc_reply_frame_hdl,
7848 7850 &irPhysDisk->Slot);
7849 7851 state = ddi_get32(mpt->m_acc_reply_frame_hdl,
7850 7852 &irPhysDisk->NewValue);
7851 7853 reason = ddi_get8(mpt->m_acc_reply_frame_hdl,
7852 7854 &irPhysDisk->ReasonCode);
7853 7855
7854 7856 NDBG20(("EVENT_IR_PHYSICAL_DISK event is received"));
7855 7857
7856 7858 switch (reason) {
7857 7859 case MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED:
7858 7860 mptsas_log(mpt, CE_NOTE,
7859 7861 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
7860 7862 "for enclosure with handle 0x%x is now in hot "
7861 7863 "spare pool %d",
7862 7864 physdisknum, devhandle, slot, enchandle,
7863 7865 (state >> 16) & 0xff);
7864 7866 break;
7865 7867
7866 7868 case MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED:
7867 7869 status = state;
7868 7870 mptsas_log(mpt, CE_NOTE,
7869 7871 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
7870 7872 "for enclosure with handle 0x%x is now "
7871 7873 "%s%s%s%s%s\n", physdisknum, devhandle, slot,
7872 7874 enchandle,
7873 7875 status & MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME
7874 7876 ? ", inactive" : ", active",
7875 7877 status & MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC
7876 7878 ? ", out of sync" : "",
7877 7879 status & MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED
7878 7880 ? ", quiesced" : "",
7879 7881 status &
7880 7882 MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED
7881 7883 ? ", write cache enabled" : "",
7882 7884 status & MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET
7883 7885 ? ", capacity expansion target" : "");
7884 7886 break;
7885 7887
7886 7888 case MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED:
7887 7889 mptsas_log(mpt, CE_NOTE,
7888 7890 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
7889 7891 "for enclosure with handle 0x%x is now %s\n",
7890 7892 physdisknum, devhandle, slot, enchandle,
7891 7893 state == MPI2_RAID_PD_STATE_OPTIMAL
7892 7894 ? "optimal" :
7893 7895 state == MPI2_RAID_PD_STATE_REBUILDING
7894 7896 ? "rebuilding" :
7895 7897 state == MPI2_RAID_PD_STATE_DEGRADED
7896 7898 ? "degraded" :
7897 7899 state == MPI2_RAID_PD_STATE_HOT_SPARE
7898 7900 ? "a hot spare" :
7899 7901 state == MPI2_RAID_PD_STATE_ONLINE
7900 7902 ? "online" :
7901 7903 state == MPI2_RAID_PD_STATE_OFFLINE
7902 7904 ? "offline" :
7903 7905 state == MPI2_RAID_PD_STATE_NOT_COMPATIBLE
7904 7906 ? "not compatible" :
7905 7907 state == MPI2_RAID_PD_STATE_NOT_CONFIGURED
7906 7908 ? "not configured" :
7907 7909 "state unknown");
7908 7910 break;
7909 7911 }
7910 7912 break;
7911 7913 }
7912 7914 default:
7913 7915 NDBG20(("mptsas%d: unknown event %x received",
7914 7916 mpt->m_instance, event));
7915 7917 break;
7916 7918 }
7917 7919
7918 7920 /*
7919 7921 * Return the reply frame to the free queue.
7920 7922 */
7921 7923 ddi_put32(mpt->m_acc_free_queue_hdl,
7922 7924 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], rfm);
7923 7925 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
7924 7926 DDI_DMA_SYNC_FORDEV);
7925 7927 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
7926 7928 mpt->m_free_index = 0;
7927 7929 }
7928 7930 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
7929 7931 mpt->m_free_index);
7930 7932 mutex_exit(&mpt->m_mutex);
7931 7933 }
7932 7934
7933 7935 /*
7934 7936 * invoked from timeout() to restart qfull cmds with throttle == 0
7935 7937 */
7936 7938 static void
7937 7939 mptsas_restart_cmd(void *arg)
7938 7940 {
7939 7941 mptsas_t *mpt = arg;
7940 7942 mptsas_target_t *ptgt = NULL;
7941 7943
7942 7944 mutex_enter(&mpt->m_mutex);
7943 7945
7944 7946 mpt->m_restart_cmd_timeid = 0;
7945 7947
7946 7948 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
7947 7949 MPTSAS_HASH_FIRST);
7948 7950 while (ptgt != NULL) {
7949 7951 mutex_enter(&ptgt->m_tgt_intr_mutex);
7950 7952 if (ptgt->m_reset_delay == 0) {
7951 7953 if (ptgt->m_t_throttle == QFULL_THROTTLE) {
7952 7954 mptsas_set_throttle(mpt, ptgt,
7953 7955 MAX_THROTTLE);
7954 7956 }
7955 7957 }
7956 7958 mutex_exit(&ptgt->m_tgt_intr_mutex);
7957 7959
7958 7960 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
7959 7961 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
7960 7962 }
7961 7963 mptsas_restart_hba(mpt);
7962 7964 mutex_exit(&mpt->m_mutex);
7963 7965 }
7964 7966
7965 7967 /*
7966 7968 * mptsas_remove_cmd0 is similar to mptsas_remove_cmd except that it is called
7967 7969 * where m_intr_mutex has already been held.
7968 7970 */
7969 7971 void
7970 7972 mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
7971 7973 {
7972 7974 ASSERT(mutex_owned(&mpt->m_mutex));
7973 7975
7974 7976 /*
7975 7977 * With new fine-grained lock mechanism, the outstanding cmd is only
7976 7978 * linked to m_active before the dma is triggerred(MPTSAS_START_CMD)
7977 7979 * to send it. that is, mptsas_save_cmd() doesn't link the outstanding
7978 7980 * cmd now. So when mptsas_remove_cmd is called, a mptsas_save_cmd must
7979 7981 * have been called, but the cmd may have not been linked.
7980 7982 * For mptsas_remove_cmd0, the cmd must have been linked.
7981 7983 * In order to keep the same semantic, we link the cmd to the
7982 7984 * outstanding cmd list.
7983 7985 */
7984 7986 mpt->m_active->m_slot[cmd->cmd_slot] = cmd;
7985 7987
7986 7988 mutex_enter(&mpt->m_intr_mutex);
7987 7989 mptsas_remove_cmd0(mpt, cmd);
7988 7990 mutex_exit(&mpt->m_intr_mutex);
7989 7991 }
7990 7992
7991 7993 static inline void
7992 7994 mptsas_remove_cmd0(mptsas_t *mpt, mptsas_cmd_t *cmd)
7993 7995 {
7994 7996 int slot;
7995 7997 mptsas_slots_t *slots = mpt->m_active;
7996 7998 int t;
7997 7999 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
7998 8000 mptsas_slot_free_e_t *pe;
7999 8001
8000 8002 ASSERT(cmd != NULL);
8001 8003 ASSERT(cmd->cmd_queued == FALSE);
8002 8004
8003 8005 /*
8004 8006 * Task Management cmds are removed in their own routines. Also,
8005 8007 * we don't want to modify timeout based on TM cmds.
8006 8008 */
8007 8009 if (cmd->cmd_flags & CFLAG_TM_CMD) {
8008 8010 return;
8009 8011 }
8010 8012
8011 8013 t = Tgt(cmd);
8012 8014 slot = cmd->cmd_slot;
8013 8015 pe = mpt->m_slot_free_ae + slot - 1;
8014 8016 ASSERT(cmd == slots->m_slot[slot]);
8015 8017 ASSERT((slot > 0) && slot < (mpt->m_max_requests - 1));
8016 8018
8017 8019 /*
8018 8020 * remove the cmd.
8019 8021 */
8020 8022 mutex_enter(&mpt->m_slot_freeq_pairp[pe->cpuid].
8021 8023 m_slot_releq.s.m_fq_mutex);
8022 8024 NDBG31(("mptsas_remove_cmd0: removing cmd=0x%p", (void *)cmd));
8023 8025 slots->m_slot[slot] = NULL;
8024 8026 ASSERT(pe->slot == slot);
8025 8027 list_insert_tail(&mpt->m_slot_freeq_pairp[pe->cpuid].
8026 8028 m_slot_releq.s.m_fq_list, pe);
8027 8029 mpt->m_slot_freeq_pairp[pe->cpuid].m_slot_releq.s.m_fq_n++;
8028 8030 ASSERT(mpt->m_slot_freeq_pairp[pe->cpuid].
8029 8031 m_slot_releq.s.m_fq_n <= mpt->m_max_requests - 2);
8030 8032 mutex_exit(&mpt->m_slot_freeq_pairp[pe->cpuid].
8031 8033 m_slot_releq.s.m_fq_mutex);
8032 8034
8033 8035 /*
8034 8036 * only decrement per target ncmds if command
8035 8037 * has a target associated with it.
8036 8038 */
8037 8039 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
8038 8040 mutex_enter(&ptgt->m_tgt_intr_mutex);
8039 8041 ptgt->m_t_ncmds--;
8040 8042 /*
8041 8043 * reset throttle if we just ran an untagged command
8042 8044 * to a tagged target
8043 8045 */
8044 8046 if ((ptgt->m_t_ncmds == 0) &&
8045 8047 ((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0)) {
8046 8048 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
8047 8049 }
8048 8050 mutex_exit(&ptgt->m_tgt_intr_mutex);
8049 8051 }
8050 8052
8051 8053 /*
8052 8054 * This is all we need to do for ioc commands.
8053 8055 * The ioc cmds would never be handled in fastpath in ISR, so we make
8054 8056 * sure the mptsas_return_to_pool() would always be called with
8055 8057 * m_mutex protected.
8056 8058 */
8057 8059 if (cmd->cmd_flags & CFLAG_CMDIOC) {
8058 8060 ASSERT(mutex_owned(&mpt->m_mutex));
8059 8061 mptsas_return_to_pool(mpt, cmd);
8060 8062 return;
8061 8063 }
8062 8064
8063 8065 /*
8064 8066 * Figure out what to set tag Q timeout for...
8065 8067 *
8066 8068 * Optimize: If we have duplicate's of same timeout
8067 8069 * we're using, then we'll use it again until we run
8068 8070 * out of duplicates. This should be the normal case
8069 8071 * for block and raw I/O.
8070 8072 * If no duplicates, we have to scan through tag que and
8071 8073 * find the longest timeout value and use it. This is
8072 8074 * going to take a while...
8073 8075 * Add 1 to m_n_slots to account for TM request.
8074 8076 */
8075 8077 mutex_enter(&ptgt->m_tgt_intr_mutex);
8076 8078 if (cmd->cmd_pkt->pkt_time == ptgt->m_timebase) {
8077 8079 if (--(ptgt->m_dups) == 0) {
8078 8080 if (ptgt->m_t_ncmds) {
8079 8081 mptsas_cmd_t *ssp;
8080 8082 uint_t n = 0;
8081 8083 ushort_t nslots = (slots->m_n_slots + 1);
8082 8084 ushort_t i;
8083 8085 /*
8084 8086 * This crude check assumes we don't do
8085 8087 * this too often which seems reasonable
8086 8088 * for block and raw I/O.
8087 8089 */
8088 8090 for (i = 0; i < nslots; i++) {
8089 8091 ssp = slots->m_slot[i];
8090 8092 if (ssp && (Tgt(ssp) == t) &&
8091 8093 (ssp->cmd_pkt->pkt_time > n)) {
8092 8094 n = ssp->cmd_pkt->pkt_time;
8093 8095 ptgt->m_dups = 1;
8094 8096 } else if (ssp && (Tgt(ssp) == t) &&
8095 8097 (ssp->cmd_pkt->pkt_time == n)) {
8096 8098 ptgt->m_dups++;
8097 8099 }
8098 8100 }
8099 8101 ptgt->m_timebase = n;
8100 8102 } else {
8101 8103 ptgt->m_dups = 0;
8102 8104 ptgt->m_timebase = 0;
8103 8105 }
8104 8106 }
8105 8107 }
8106 8108 ptgt->m_timeout = ptgt->m_timebase;
8107 8109
8108 8110 ASSERT(cmd != slots->m_slot[cmd->cmd_slot]);
8109 8111 mutex_exit(&ptgt->m_tgt_intr_mutex);
8110 8112 }
8111 8113
8112 8114 /*
8113 8115 * start a fresh request from the top of the device queue.
8114 8116 */
8115 8117 static void
8116 8118 mptsas_restart_hba(mptsas_t *mpt)
8117 8119 {
8118 8120 mptsas_cmd_t *cmd, *next_cmd;
8119 8121 mptsas_target_t *ptgt = NULL;
8120 8122
8121 8123 NDBG1(("mptsas_restart_hba: mpt=0x%p", (void *)mpt));
8122 8124
8123 8125 ASSERT(mutex_owned(&mpt->m_mutex));
8124 8126
8125 8127 /*
8126 8128 * If there is a reset delay, don't start any cmds. Otherwise, start
8127 8129 * as many cmds as possible.
8128 8130 * Since SMID 0 is reserved and the TM slot is reserved, the actual max
8129 8131 * commands is m_max_requests - 2.
8130 8132 */
8131 8133 cmd = mpt->m_waitq;
8132 8134
8133 8135 while (cmd != NULL) {
8134 8136 next_cmd = cmd->cmd_linkp;
8135 8137 if (cmd->cmd_flags & CFLAG_PASSTHRU) {
8136 8138 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8137 8139 /*
8138 8140 * passthru command get slot need
8139 8141 * set CFLAG_PREPARED.
8140 8142 */
8141 8143 cmd->cmd_flags |= CFLAG_PREPARED;
8142 8144 mptsas_waitq_delete(mpt, cmd);
8143 8145 mptsas_start_passthru(mpt, cmd);
8144 8146 }
8145 8147 cmd = next_cmd;
8146 8148 continue;
8147 8149 }
8148 8150 if (cmd->cmd_flags & CFLAG_CONFIG) {
8149 8151 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8150 8152 /*
8151 8153 * Send the config page request and delete it
8152 8154 * from the waitq.
8153 8155 */
8154 8156 cmd->cmd_flags |= CFLAG_PREPARED;
8155 8157 mptsas_waitq_delete(mpt, cmd);
8156 8158 mptsas_start_config_page_access(mpt, cmd);
8157 8159 }
8158 8160 cmd = next_cmd;
8159 8161 continue;
8160 8162 }
8161 8163 if (cmd->cmd_flags & CFLAG_FW_DIAG) {
8162 8164 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8163 8165 /*
8164 8166 * Send the FW Diag request and delete if from
8165 8167 * the waitq.
8166 8168 */
8167 8169 cmd->cmd_flags |= CFLAG_PREPARED;
8168 8170 mptsas_waitq_delete(mpt, cmd);
8169 8171 mptsas_start_diag(mpt, cmd);
8170 8172 }
8171 8173 cmd = next_cmd;
8172 8174 continue;
8173 8175 }
8174 8176
8175 8177 ptgt = cmd->cmd_tgt_addr;
8176 8178 if (ptgt) {
8177 8179 mutex_enter(&mpt->m_intr_mutex);
8178 8180 mutex_enter(&ptgt->m_tgt_intr_mutex);
8179 8181 if ((ptgt->m_t_throttle == DRAIN_THROTTLE) &&
8180 8182 (ptgt->m_t_ncmds == 0)) {
8181 8183 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
8182 8184 }
8183 8185 if ((ptgt->m_reset_delay == 0) &&
8184 8186 (ptgt->m_t_ncmds < ptgt->m_t_throttle)) {
8185 8187 mutex_exit(&ptgt->m_tgt_intr_mutex);
8186 8188 mutex_exit(&mpt->m_intr_mutex);
8187 8189 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8188 8190 mptsas_waitq_delete(mpt, cmd);
8189 8191 (void) mptsas_start_cmd(mpt, cmd);
8190 8192 }
8191 8193 goto out;
8192 8194 }
8193 8195 mutex_exit(&ptgt->m_tgt_intr_mutex);
8194 8196 mutex_exit(&mpt->m_intr_mutex);
8195 8197 }
8196 8198 out:
8197 8199 cmd = next_cmd;
8198 8200 }
8199 8201 }
8200 8202
8201 8203 /*
8202 8204 * mpt tag type lookup
8203 8205 */
8204 8206 static char mptsas_tag_lookup[] =
8205 8207 {0, MSG_HEAD_QTAG, MSG_ORDERED_QTAG, 0, MSG_SIMPLE_QTAG};
8206 8208
8207 8209 /*
8208 8210 * mptsas_start_cmd0 is similar to mptsas_start_cmd, except that, it is called
8209 8211 * without ANY mutex protected, while, mptsas_start_cmd is called with m_mutex
8210 8212 * protected.
8211 8213 *
8212 8214 * the relevant field in ptgt should be protected by m_tgt_intr_mutex in both
8213 8215 * functions.
8214 8216 *
8215 8217 * before the cmds are linked on the slot for monitor as outstanding cmds, they
8216 8218 * are accessed as slab objects, so slab framework ensures the exclusive access,
8217 8219 * and no other mutex is requireed. Linking for monitor and the trigger of dma
8218 8220 * must be done exclusively.
8219 8221 */
8220 8222 static int
8221 8223 mptsas_start_cmd0(mptsas_t *mpt, mptsas_cmd_t *cmd)
8222 8224 {
8223 8225 struct scsi_pkt *pkt = CMD2PKT(cmd);
8224 8226 uint32_t control = 0;
8225 8227 int n;
8226 8228 caddr_t mem;
8227 8229 pMpi2SCSIIORequest_t io_request;
8228 8230 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl;
8229 8231 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl;
8230 8232 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8231 8233 uint16_t SMID, io_flags = 0;
8232 8234 uint32_t request_desc_low, request_desc_high;
8233 8235
8234 8236 NDBG1(("mptsas_start_cmd0: cmd=0x%p", (void *)cmd));
8235 8237
8236 8238 /*
8237 8239 * Set SMID and increment index. Rollover to 1 instead of 0 if index
8238 8240 * is at the max. 0 is an invalid SMID, so we call the first index 1.
8239 8241 */
8240 8242 SMID = cmd->cmd_slot;
8241 8243
8242 8244 /*
8243 8245 * It is possible for back to back device reset to
8244 8246 * happen before the reset delay has expired. That's
8245 8247 * ok, just let the device reset go out on the bus.
8246 8248 */
8247 8249 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
8248 8250 ASSERT(ptgt->m_reset_delay == 0);
8249 8251 }
8250 8252
8251 8253 /*
8252 8254 * if a non-tagged cmd is submitted to an active tagged target
8253 8255 * then drain before submitting this cmd; SCSI-2 allows RQSENSE
8254 8256 * to be untagged
8255 8257 */
8256 8258 mutex_enter(&ptgt->m_tgt_intr_mutex);
8257 8259 if (((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0) &&
8258 8260 (ptgt->m_t_ncmds > 1) &&
8259 8261 ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) &&
8260 8262 (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE)) {
8261 8263 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
8262 8264 NDBG23(("target=%d, untagged cmd, start draining\n",
8263 8265 ptgt->m_devhdl));
8264 8266
8265 8267 if (ptgt->m_reset_delay == 0) {
8266 8268 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
8267 8269 }
8268 8270 mutex_exit(&ptgt->m_tgt_intr_mutex);
8269 8271
8270 8272 mutex_enter(&mpt->m_mutex);
8271 8273 mptsas_remove_cmd(mpt, cmd);
8272 8274 cmd->cmd_pkt_flags |= FLAG_HEAD;
8273 8275 mptsas_waitq_add(mpt, cmd);
8274 8276 mutex_exit(&mpt->m_mutex);
8275 8277 return (DDI_FAILURE);
8276 8278 }
8277 8279 mutex_exit(&ptgt->m_tgt_intr_mutex);
8278 8280 return (DDI_FAILURE);
8279 8281 }
8280 8282 mutex_exit(&ptgt->m_tgt_intr_mutex);
8281 8283
8282 8284 /*
8283 8285 * Set correct tag bits.
8284 8286 */
8285 8287 if (cmd->cmd_pkt_flags & FLAG_TAGMASK) {
8286 8288 switch (mptsas_tag_lookup[((cmd->cmd_pkt_flags &
8287 8289 FLAG_TAGMASK) >> 12)]) {
8288 8290 case MSG_SIMPLE_QTAG:
8289 8291 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
8290 8292 break;
8291 8293 case MSG_HEAD_QTAG:
8292 8294 control |= MPI2_SCSIIO_CONTROL_HEADOFQ;
8293 8295 break;
8294 8296 case MSG_ORDERED_QTAG:
8295 8297 control |= MPI2_SCSIIO_CONTROL_ORDEREDQ;
8296 8298 break;
8297 8299 default:
8298 8300 mptsas_log(mpt, CE_WARN, "mpt: Invalid tag type\n");
8299 8301 break;
8300 8302 }
8301 8303 } else {
8302 8304 if (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE) {
8303 8305 ptgt->m_t_throttle = 1;
8304 8306 }
8305 8307 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
8306 8308 }
8307 8309
8308 8310 if (cmd->cmd_pkt_flags & FLAG_TLR) {
8309 8311 control |= MPI2_SCSIIO_CONTROL_TLR_ON;
8310 8312 }
8311 8313
8312 8314 mem = mpt->m_req_frame + (mpt->m_req_frame_size * SMID);
8313 8315 io_request = (pMpi2SCSIIORequest_t)mem;
8314 8316
8315 8317 bzero(io_request, sizeof (Mpi2SCSIIORequest_t));
8316 8318 ddi_put8(acc_hdl, &io_request->SGLOffset0, offsetof
8317 8319 (MPI2_SCSI_IO_REQUEST, SGL) / 4);
8318 8320 mptsas_init_std_hdr(acc_hdl, io_request, ptgt->m_devhdl, Lun(cmd), 0,
8319 8321 MPI2_FUNCTION_SCSI_IO_REQUEST);
8320 8322
8321 8323 (void) ddi_rep_put8(acc_hdl, (uint8_t *)pkt->pkt_cdbp,
8322 8324 io_request->CDB.CDB32, cmd->cmd_cdblen, DDI_DEV_AUTOINCR);
8323 8325
8324 8326 io_flags = cmd->cmd_cdblen;
8325 8327 ddi_put16(acc_hdl, &io_request->IoFlags, io_flags);
8326 8328 /*
8327 8329 * setup the Scatter/Gather DMA list for this request
8328 8330 */
8329 8331 if (cmd->cmd_cookiec > 0) {
8330 8332 mptsas_sge_setup(mpt, cmd, &control, io_request, acc_hdl);
8331 8333 } else {
8332 8334 ddi_put32(acc_hdl, &io_request->SGL.MpiSimple.FlagsLength,
8333 8335 ((uint32_t)MPI2_SGE_FLAGS_LAST_ELEMENT |
8334 8336 MPI2_SGE_FLAGS_END_OF_BUFFER |
8335 8337 MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
8336 8338 MPI2_SGE_FLAGS_END_OF_LIST) << MPI2_SGE_FLAGS_SHIFT);
8337 8339 }
8338 8340
8339 8341 /*
8340 8342 * save ARQ information
8341 8343 */
8342 8344 ddi_put8(acc_hdl, &io_request->SenseBufferLength, cmd->cmd_rqslen);
8343 8345 if ((cmd->cmd_flags & (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) ==
8344 8346 (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) {
8345 8347 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress,
8346 8348 cmd->cmd_ext_arqcookie.dmac_address);
8347 8349 } else {
8348 8350 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress,
8349 8351 cmd->cmd_arqcookie.dmac_address);
8350 8352 }
8351 8353
8352 8354 ddi_put32(acc_hdl, &io_request->Control, control);
8353 8355
8354 8356 NDBG31(("starting message=0x%p, with cmd=0x%p",
8355 8357 (void *)(uintptr_t)mpt->m_req_frame_dma_addr, (void *)cmd));
8356 8358
8357 8359 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
8358 8360
8359 8361 /*
8360 8362 * Build request descriptor and write it to the request desc post reg.
8361 8363 */
8362 8364 request_desc_low = (SMID << 16) + MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
8363 8365 request_desc_high = ptgt->m_devhdl << 16;
8364 8366
8365 8367 mutex_enter(&mpt->m_mutex);
8366 8368 mpt->m_active->m_slot[cmd->cmd_slot] = cmd;
8367 8369 MPTSAS_START_CMD(mpt, request_desc_low, request_desc_high);
8368 8370 mutex_exit(&mpt->m_mutex);
8369 8371
8370 8372 /*
8371 8373 * Start timeout.
8372 8374 */
8373 8375 mutex_enter(&ptgt->m_tgt_intr_mutex);
8374 8376 #ifdef MPTSAS_TEST
8375 8377 /*
8376 8378 * Temporarily set timebase = 0; needed for
8377 8379 * timeout torture test.
8378 8380 */
8379 8381 if (mptsas_test_timeouts) {
8380 8382 ptgt->m_timebase = 0;
8381 8383 }
8382 8384 #endif
8383 8385 n = pkt->pkt_time - ptgt->m_timebase;
8384 8386
8385 8387 if (n == 0) {
8386 8388 (ptgt->m_dups)++;
8387 8389 ptgt->m_timeout = ptgt->m_timebase;
8388 8390 } else if (n > 0) {
8389 8391 ptgt->m_timeout =
8390 8392 ptgt->m_timebase = pkt->pkt_time;
8391 8393 ptgt->m_dups = 1;
8392 8394 } else if (n < 0) {
8393 8395 ptgt->m_timeout = ptgt->m_timebase;
8394 8396 }
8395 8397 #ifdef MPTSAS_TEST
8396 8398 /*
8397 8399 * Set back to a number higher than
8398 8400 * mptsas_scsi_watchdog_tick
8399 8401 * so timeouts will happen in mptsas_watchsubr
8400 8402 */
8401 8403 if (mptsas_test_timeouts) {
8402 8404 ptgt->m_timebase = 60;
8403 8405 }
8404 8406 #endif
8405 8407 mutex_exit(&ptgt->m_tgt_intr_mutex);
8406 8408
8407 8409 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) ||
8408 8410 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) {
8409 8411 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8410 8412 return (DDI_FAILURE);
8411 8413 }
8412 8414 return (DDI_SUCCESS);
8413 8415 }
8414 8416
8415 8417 static int
8416 8418 mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
8417 8419 {
8418 8420 struct scsi_pkt *pkt = CMD2PKT(cmd);
8419 8421 uint32_t control = 0;
8420 8422 int n;
8421 8423 caddr_t mem;
8422 8424 pMpi2SCSIIORequest_t io_request;
8423 8425 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl;
8424 8426 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl;
8425 8427 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8426 8428 uint16_t SMID, io_flags = 0;
8427 8429 uint32_t request_desc_low, request_desc_high;
8428 8430
8429 8431 NDBG1(("mptsas_start_cmd: cmd=0x%p", (void *)cmd));
8430 8432
8431 8433 /*
8432 8434 * Set SMID and increment index. Rollover to 1 instead of 0 if index
8433 8435 * is at the max. 0 is an invalid SMID, so we call the first index 1.
8434 8436 */
8435 8437 SMID = cmd->cmd_slot;
8436 8438
8437 8439 /*
8438 8440 * It is possible for back to back device reset to
8439 8441 * happen before the reset delay has expired. That's
8440 8442 * ok, just let the device reset go out on the bus.
8441 8443 */
8442 8444 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
8443 8445 ASSERT(ptgt->m_reset_delay == 0);
8444 8446 }
8445 8447
8446 8448 /*
8447 8449 * if a non-tagged cmd is submitted to an active tagged target
8448 8450 * then drain before submitting this cmd; SCSI-2 allows RQSENSE
8449 8451 * to be untagged
8450 8452 */
8451 8453 mutex_enter(&ptgt->m_tgt_intr_mutex);
8452 8454 if (((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0) &&
8453 8455 (ptgt->m_t_ncmds > 1) &&
8454 8456 ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) &&
8455 8457 (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE)) {
8456 8458 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
8457 8459 NDBG23(("target=%d, untagged cmd, start draining\n",
8458 8460 ptgt->m_devhdl));
8459 8461
8460 8462 if (ptgt->m_reset_delay == 0) {
8461 8463 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
8462 8464 }
8463 8465 mutex_exit(&ptgt->m_tgt_intr_mutex);
8464 8466
8465 8467 mptsas_remove_cmd(mpt, cmd);
8466 8468 cmd->cmd_pkt_flags |= FLAG_HEAD;
8467 8469 mptsas_waitq_add(mpt, cmd);
8468 8470 return (DDI_FAILURE);
8469 8471 }
8470 8472 mutex_exit(&ptgt->m_tgt_intr_mutex);
8471 8473 return (DDI_FAILURE);
8472 8474 }
8473 8475 mutex_exit(&ptgt->m_tgt_intr_mutex);
8474 8476
8475 8477 /*
8476 8478 * Set correct tag bits.
8477 8479 */
8478 8480 if (cmd->cmd_pkt_flags & FLAG_TAGMASK) {
8479 8481 switch (mptsas_tag_lookup[((cmd->cmd_pkt_flags &
8480 8482 FLAG_TAGMASK) >> 12)]) {
8481 8483 case MSG_SIMPLE_QTAG:
8482 8484 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
8483 8485 break;
8484 8486 case MSG_HEAD_QTAG:
8485 8487 control |= MPI2_SCSIIO_CONTROL_HEADOFQ;
8486 8488 break;
8487 8489 case MSG_ORDERED_QTAG:
8488 8490 control |= MPI2_SCSIIO_CONTROL_ORDEREDQ;
8489 8491 break;
8490 8492 default:
8491 8493 mptsas_log(mpt, CE_WARN, "mpt: Invalid tag type\n");
8492 8494 break;
8493 8495 }
8494 8496 } else {
8495 8497 if (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE) {
8496 8498 ptgt->m_t_throttle = 1;
8497 8499 }
8498 8500 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
8499 8501 }
8500 8502
8501 8503 if (cmd->cmd_pkt_flags & FLAG_TLR) {
8502 8504 control |= MPI2_SCSIIO_CONTROL_TLR_ON;
8503 8505 }
8504 8506
8505 8507 mem = mpt->m_req_frame + (mpt->m_req_frame_size * SMID);
8506 8508 io_request = (pMpi2SCSIIORequest_t)mem;
8507 8509
8508 8510 bzero(io_request, sizeof (Mpi2SCSIIORequest_t));
8509 8511 ddi_put8(acc_hdl, &io_request->SGLOffset0, offsetof
8510 8512 (MPI2_SCSI_IO_REQUEST, SGL) / 4);
8511 8513 mptsas_init_std_hdr(acc_hdl, io_request, ptgt->m_devhdl, Lun(cmd), 0,
8512 8514 MPI2_FUNCTION_SCSI_IO_REQUEST);
8513 8515
8514 8516 (void) ddi_rep_put8(acc_hdl, (uint8_t *)pkt->pkt_cdbp,
8515 8517 io_request->CDB.CDB32, cmd->cmd_cdblen, DDI_DEV_AUTOINCR);
8516 8518
8517 8519 io_flags = cmd->cmd_cdblen;
8518 8520 ddi_put16(acc_hdl, &io_request->IoFlags, io_flags);
8519 8521 /*
8520 8522 * setup the Scatter/Gather DMA list for this request
8521 8523 */
8522 8524 if (cmd->cmd_cookiec > 0) {
8523 8525 mptsas_sge_setup(mpt, cmd, &control, io_request, acc_hdl);
8524 8526 } else {
8525 8527 ddi_put32(acc_hdl, &io_request->SGL.MpiSimple.FlagsLength,
8526 8528 ((uint32_t)MPI2_SGE_FLAGS_LAST_ELEMENT |
8527 8529 MPI2_SGE_FLAGS_END_OF_BUFFER |
8528 8530 MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
8529 8531 MPI2_SGE_FLAGS_END_OF_LIST) << MPI2_SGE_FLAGS_SHIFT);
8530 8532 }
8531 8533
8532 8534 /*
8533 8535 * save ARQ information
8534 8536 */
8535 8537 ddi_put8(acc_hdl, &io_request->SenseBufferLength, cmd->cmd_rqslen);
8536 8538 if ((cmd->cmd_flags & (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) ==
8537 8539 (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) {
8538 8540 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress,
8539 8541 cmd->cmd_ext_arqcookie.dmac_address);
8540 8542 } else {
8541 8543 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress,
8542 8544 cmd->cmd_arqcookie.dmac_address);
8543 8545 }
8544 8546
8545 8547 ddi_put32(acc_hdl, &io_request->Control, control);
8546 8548
8547 8549 NDBG31(("starting message=0x%p, with cmd=0x%p",
8548 8550 (void *)(uintptr_t)mpt->m_req_frame_dma_addr, (void *)cmd));
8549 8551
8550 8552 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
8551 8553
8552 8554 /*
8553 8555 * Build request descriptor and write it to the request desc post reg.
8554 8556 */
8555 8557 request_desc_low = (SMID << 16) + MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
8556 8558 request_desc_high = ptgt->m_devhdl << 16;
8557 8559
8558 8560 mpt->m_active->m_slot[cmd->cmd_slot] = cmd;
8559 8561 MPTSAS_START_CMD(mpt, request_desc_low, request_desc_high);
8560 8562
8561 8563 /*
8562 8564 * Start timeout.
8563 8565 */
8564 8566 mutex_enter(&ptgt->m_tgt_intr_mutex);
8565 8567 #ifdef MPTSAS_TEST
8566 8568 /*
8567 8569 * Temporarily set timebase = 0; needed for
8568 8570 * timeout torture test.
8569 8571 */
8570 8572 if (mptsas_test_timeouts) {
8571 8573 ptgt->m_timebase = 0;
8572 8574 }
8573 8575 #endif
8574 8576 n = pkt->pkt_time - ptgt->m_timebase;
8575 8577
8576 8578 if (n == 0) {
8577 8579 (ptgt->m_dups)++;
8578 8580 ptgt->m_timeout = ptgt->m_timebase;
8579 8581 } else if (n > 0) {
8580 8582 ptgt->m_timeout =
8581 8583 ptgt->m_timebase = pkt->pkt_time;
8582 8584 ptgt->m_dups = 1;
8583 8585 } else if (n < 0) {
8584 8586 ptgt->m_timeout = ptgt->m_timebase;
8585 8587 }
8586 8588 #ifdef MPTSAS_TEST
8587 8589 /*
8588 8590 * Set back to a number higher than
8589 8591 * mptsas_scsi_watchdog_tick
8590 8592 * so timeouts will happen in mptsas_watchsubr
8591 8593 */
8592 8594 if (mptsas_test_timeouts) {
8593 8595 ptgt->m_timebase = 60;
8594 8596 }
8595 8597 #endif
8596 8598 mutex_exit(&ptgt->m_tgt_intr_mutex);
8597 8599
8598 8600 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) ||
8599 8601 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) {
8600 8602 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8601 8603 return (DDI_FAILURE);
8602 8604 }
8603 8605 return (DDI_SUCCESS);
8604 8606 }
8605 8607
8606 8608 /*
8607 8609 * Select a helper thread to handle current doneq
8608 8610 */
8609 8611 static void
8610 8612 mptsas_deliver_doneq_thread(mptsas_t *mpt)
8611 8613 {
8612 8614 uint64_t t, i;
8613 8615 uint32_t min = 0xffffffff;
8614 8616 mptsas_doneq_thread_list_t *item;
8615 8617
8616 8618 for (i = 0; i < mpt->m_doneq_thread_n; i++) {
8617 8619 item = &mpt->m_doneq_thread_id[i];
8618 8620 /*
8619 8621 * If the completed command on help thread[i] less than
8620 8622 * doneq_thread_threshold, then pick the thread[i]. Otherwise
8621 8623 * pick a thread which has least completed command.
8622 8624 */
8623 8625
8624 8626 mutex_enter(&item->mutex);
8625 8627 if (item->len < mpt->m_doneq_thread_threshold) {
8626 8628 t = i;
8627 8629 mutex_exit(&item->mutex);
8628 8630 break;
8629 8631 }
8630 8632 if (item->len < min) {
8631 8633 min = item->len;
8632 8634 t = i;
8633 8635 }
8634 8636 mutex_exit(&item->mutex);
8635 8637 }
8636 8638 mutex_enter(&mpt->m_doneq_thread_id[t].mutex);
8637 8639 mptsas_doneq_mv(mpt, t);
8638 8640 cv_signal(&mpt->m_doneq_thread_id[t].cv);
8639 8641 mutex_exit(&mpt->m_doneq_thread_id[t].mutex);
8640 8642 }
8641 8643
8642 8644 /*
8643 8645 * move the current global doneq to the doneq of thread[t]
8644 8646 */
8645 8647 static void
8646 8648 mptsas_doneq_mv(mptsas_t *mpt, uint64_t t)
8647 8649 {
8648 8650 mptsas_cmd_t *cmd;
8649 8651 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
8650 8652
8651 8653 ASSERT(mutex_owned(&item->mutex));
8652 8654 mutex_enter(&mpt->m_intr_mutex);
8653 8655 while ((cmd = mpt->m_doneq) != NULL) {
8654 8656 if ((mpt->m_doneq = cmd->cmd_linkp) == NULL) {
8655 8657 mpt->m_donetail = &mpt->m_doneq;
8656 8658 }
8657 8659 cmd->cmd_linkp = NULL;
8658 8660 *item->donetail = cmd;
8659 8661 item->donetail = &cmd->cmd_linkp;
8660 8662 mpt->m_doneq_len--;
8661 8663 item->len++;
8662 8664 }
8663 8665 mutex_exit(&mpt->m_intr_mutex);
8664 8666 }
8665 8667
8666 8668 void
8667 8669 mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd)
8668 8670 {
8669 8671 struct scsi_pkt *pkt = CMD2PKT(cmd);
8670 8672
8671 8673 /* Check all acc and dma handles */
8672 8674 if ((mptsas_check_acc_handle(mpt->m_datap) !=
8673 8675 DDI_SUCCESS) ||
8674 8676 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
8675 8677 DDI_SUCCESS) ||
8676 8678 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) !=
8677 8679 DDI_SUCCESS) ||
8678 8680 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) !=
8679 8681 DDI_SUCCESS) ||
8680 8682 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) !=
8681 8683 DDI_SUCCESS) ||
8682 8684 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) !=
8683 8685 DDI_SUCCESS) ||
8684 8686 (mptsas_check_acc_handle(mpt->m_config_handle) !=
8685 8687 DDI_SUCCESS)) {
8686 8688 ddi_fm_service_impact(mpt->m_dip,
8687 8689 DDI_SERVICE_UNAFFECTED);
8688 8690 ddi_fm_acc_err_clear(mpt->m_config_handle,
8689 8691 DDI_FME_VER0);
8690 8692 pkt->pkt_reason = CMD_TRAN_ERR;
8691 8693 pkt->pkt_statistics = 0;
8692 8694 }
8693 8695 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
8694 8696 DDI_SUCCESS) ||
8695 8697 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) !=
8696 8698 DDI_SUCCESS) ||
8697 8699 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) !=
8698 8700 DDI_SUCCESS) ||
8699 8701 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) !=
8700 8702 DDI_SUCCESS) ||
8701 8703 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) !=
8702 8704 DDI_SUCCESS)) {
8703 8705 ddi_fm_service_impact(mpt->m_dip,
8704 8706 DDI_SERVICE_UNAFFECTED);
8705 8707 pkt->pkt_reason = CMD_TRAN_ERR;
8706 8708 pkt->pkt_statistics = 0;
8707 8709 }
8708 8710 if (cmd->cmd_dmahandle &&
8709 8711 (mptsas_check_dma_handle(cmd->cmd_dmahandle) != DDI_SUCCESS)) {
8710 8712 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8711 8713 pkt->pkt_reason = CMD_TRAN_ERR;
8712 8714 pkt->pkt_statistics = 0;
8713 8715 }
8714 8716 if ((cmd->cmd_extra_frames &&
8715 8717 ((mptsas_check_dma_handle(cmd->cmd_extra_frames->m_dma_hdl) !=
8716 8718 DDI_SUCCESS) ||
8717 8719 (mptsas_check_acc_handle(cmd->cmd_extra_frames->m_acc_hdl) !=
8718 8720 DDI_SUCCESS)))) {
8719 8721 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8720 8722 pkt->pkt_reason = CMD_TRAN_ERR;
8721 8723 pkt->pkt_statistics = 0;
8722 8724 }
8723 8725 if (cmd->cmd_arqhandle &&
8724 8726 (mptsas_check_dma_handle(cmd->cmd_arqhandle) != DDI_SUCCESS)) {
8725 8727 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8726 8728 pkt->pkt_reason = CMD_TRAN_ERR;
8727 8729 pkt->pkt_statistics = 0;
8728 8730 }
8729 8731 if (cmd->cmd_ext_arqhandle &&
8730 8732 (mptsas_check_dma_handle(cmd->cmd_ext_arqhandle) != DDI_SUCCESS)) {
8731 8733 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8732 8734 pkt->pkt_reason = CMD_TRAN_ERR;
8733 8735 pkt->pkt_statistics = 0;
8734 8736 }
8735 8737 }
8736 8738
8737 8739 /*
8738 8740 * mptsas_doneq_add0 is similar to mptsas_doneq_add except that it is called
8739 8741 * where m_intr_mutex has already been held.
8740 8742 */
8741 8743 static inline void
8742 8744 mptsas_doneq_add0(mptsas_t *mpt, mptsas_cmd_t *cmd)
8743 8745 {
8744 8746 struct scsi_pkt *pkt = CMD2PKT(cmd);
8745 8747
8746 8748 NDBG31(("mptsas_doneq_add0: cmd=0x%p", (void *)cmd));
8747 8749
8748 8750 ASSERT((cmd->cmd_flags & CFLAG_COMPLETED) == 0);
8749 8751 cmd->cmd_linkp = NULL;
8750 8752 cmd->cmd_flags |= CFLAG_FINISHED;
8751 8753 cmd->cmd_flags &= ~CFLAG_IN_TRANSPORT;
8752 8754
8753 8755 /*
8754 8756 * only add scsi pkts that have completion routines to
8755 8757 * the doneq. no intr cmds do not have callbacks.
8756 8758 */
8757 8759 if (pkt && (pkt->pkt_comp)) {
8758 8760 *mpt->m_donetail = cmd;
8759 8761 mpt->m_donetail = &cmd->cmd_linkp;
8760 8762 mpt->m_doneq_len++;
8761 8763 }
8762 8764 }
8763 8765
8764 8766 /*
8765 8767 * These routines manipulate the queue of commands that
8766 8768 * are waiting for their completion routines to be called.
8767 8769 * The queue is usually in FIFO order but on an MP system
8768 8770 * it's possible for the completion routines to get out
8769 8771 * of order. If that's a problem you need to add a global
8770 8772 * mutex around the code that calls the completion routine
8771 8773 * in the interrupt handler.
8772 8774 */
8773 8775 static void
8774 8776 mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd)
8775 8777 {
8776 8778 ASSERT(mutex_owned(&mpt->m_mutex));
8777 8779
8778 8780 mptsas_fma_check(mpt, cmd);
8779 8781
8780 8782 mutex_enter(&mpt->m_intr_mutex);
8781 8783 mptsas_doneq_add0(mpt, cmd);
8782 8784 mutex_exit(&mpt->m_intr_mutex);
8783 8785 }
8784 8786
8785 8787 static mptsas_cmd_t *
8786 8788 mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t)
8787 8789 {
8788 8790 mptsas_cmd_t *cmd;
8789 8791 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
8790 8792
8791 8793 /* pop one off the done queue */
8792 8794 if ((cmd = item->doneq) != NULL) {
8793 8795 /* if the queue is now empty fix the tail pointer */
8794 8796 NDBG31(("mptsas_doneq_thread_rm: cmd=0x%p", (void *)cmd));
8795 8797 if ((item->doneq = cmd->cmd_linkp) == NULL) {
8796 8798 item->donetail = &item->doneq;
8797 8799 }
8798 8800 cmd->cmd_linkp = NULL;
8799 8801 item->len--;
8800 8802 }
8801 8803 return (cmd);
8802 8804 }
8803 8805
8804 8806 static void
8805 8807 mptsas_doneq_empty(mptsas_t *mpt)
8806 8808 {
8807 8809 mutex_enter(&mpt->m_intr_mutex);
8808 8810 if (mpt->m_doneq && !mpt->m_in_callback) {
8809 8811 mptsas_cmd_t *cmd, *next;
8810 8812 struct scsi_pkt *pkt;
8811 8813
8812 8814 mpt->m_in_callback = 1;
8813 8815 cmd = mpt->m_doneq;
8814 8816 mpt->m_doneq = NULL;
8815 8817 mpt->m_donetail = &mpt->m_doneq;
8816 8818 mpt->m_doneq_len = 0;
8817 8819
8818 8820 mutex_exit(&mpt->m_intr_mutex);
8819 8821
8820 8822 /*
8821 8823 * ONLY in ISR, is it called without m_mutex held, otherwise,
8822 8824 * it is always called with m_mutex held.
8823 8825 */
8824 8826 if ((curthread->t_flag & T_INTR_THREAD) == 0)
8825 8827 mutex_exit(&mpt->m_mutex);
8826 8828 /*
8827 8829 * run the completion routines of all the
8828 8830 * completed commands
8829 8831 */
8830 8832 while (cmd != NULL) {
8831 8833 next = cmd->cmd_linkp;
8832 8834 cmd->cmd_linkp = NULL;
8833 8835 /* run this command's completion routine */
8834 8836 cmd->cmd_flags |= CFLAG_COMPLETED;
8835 8837 pkt = CMD2PKT(cmd);
8836 8838 mptsas_pkt_comp(pkt, cmd);
8837 8839 cmd = next;
8838 8840 }
8839 8841 if ((curthread->t_flag & T_INTR_THREAD) == 0)
8840 8842 mutex_enter(&mpt->m_mutex);
8841 8843 mpt->m_in_callback = 0;
8842 8844 return;
8843 8845 }
8844 8846 mutex_exit(&mpt->m_intr_mutex);
8845 8847 }
8846 8848
8847 8849 /*
8848 8850 * These routines manipulate the target's queue of pending requests
8849 8851 */
8850 8852 void
8851 8853 mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd)
8852 8854 {
8853 8855 NDBG7(("mptsas_waitq_add: cmd=0x%p", (void *)cmd));
8854 8856 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8855 8857 cmd->cmd_queued = TRUE;
8856 8858 if (ptgt)
8857 8859 ptgt->m_t_nwait++;
8858 8860 if (cmd->cmd_pkt_flags & FLAG_HEAD) {
8859 8861 mutex_enter(&mpt->m_intr_mutex);
8860 8862 if ((cmd->cmd_linkp = mpt->m_waitq) == NULL) {
8861 8863 mpt->m_waitqtail = &cmd->cmd_linkp;
8862 8864 }
8863 8865 mpt->m_waitq = cmd;
8864 8866 mutex_exit(&mpt->m_intr_mutex);
8865 8867 } else {
8866 8868 cmd->cmd_linkp = NULL;
8867 8869 *(mpt->m_waitqtail) = cmd;
8868 8870 mpt->m_waitqtail = &cmd->cmd_linkp;
8869 8871 }
8870 8872 }
8871 8873
8872 8874 static mptsas_cmd_t *
8873 8875 mptsas_waitq_rm(mptsas_t *mpt)
8874 8876 {
8875 8877 mptsas_cmd_t *cmd;
8876 8878 mptsas_target_t *ptgt;
8877 8879 NDBG7(("mptsas_waitq_rm"));
8878 8880
8879 8881 mutex_enter(&mpt->m_intr_mutex);
8880 8882 MPTSAS_WAITQ_RM(mpt, cmd);
8881 8883 mutex_exit(&mpt->m_intr_mutex);
8882 8884
8883 8885 NDBG7(("mptsas_waitq_rm: cmd=0x%p", (void *)cmd));
8884 8886 if (cmd) {
8885 8887 ptgt = cmd->cmd_tgt_addr;
8886 8888 if (ptgt) {
8887 8889 ptgt->m_t_nwait--;
8888 8890 ASSERT(ptgt->m_t_nwait >= 0);
8889 8891 }
8890 8892 }
8891 8893 return (cmd);
8892 8894 }
8893 8895
8894 8896 /*
8895 8897 * remove specified cmd from the middle of the wait queue.
8896 8898 */
8897 8899 static void
8898 8900 mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd)
8899 8901 {
8900 8902 mptsas_cmd_t *prevp = mpt->m_waitq;
8901 8903 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8902 8904
8903 8905 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
8904 8906 (void *)mpt, (void *)cmd));
8905 8907 if (ptgt) {
8906 8908 ptgt->m_t_nwait--;
8907 8909 ASSERT(ptgt->m_t_nwait >= 0);
8908 8910 }
8909 8911
8910 8912 if (prevp == cmd) {
8911 8913 mutex_enter(&mpt->m_intr_mutex);
8912 8914 if ((mpt->m_waitq = cmd->cmd_linkp) == NULL)
8913 8915 mpt->m_waitqtail = &mpt->m_waitq;
8914 8916 mutex_exit(&mpt->m_intr_mutex);
8915 8917
8916 8918 cmd->cmd_linkp = NULL;
8917 8919 cmd->cmd_queued = FALSE;
8918 8920 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
8919 8921 (void *)mpt, (void *)cmd));
8920 8922 return;
8921 8923 }
8922 8924
8923 8925 while (prevp != NULL) {
8924 8926 if (prevp->cmd_linkp == cmd) {
8925 8927 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL)
8926 8928 mpt->m_waitqtail = &prevp->cmd_linkp;
8927 8929
8928 8930 cmd->cmd_linkp = NULL;
8929 8931 cmd->cmd_queued = FALSE;
8930 8932 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
8931 8933 (void *)mpt, (void *)cmd));
8932 8934 return;
8933 8935 }
8934 8936 prevp = prevp->cmd_linkp;
8935 8937 }
8936 8938 cmn_err(CE_PANIC, "mpt: mptsas_waitq_delete: queue botch");
8937 8939 }
8938 8940
8939 8941 /*
8940 8942 * device and bus reset handling
8941 8943 *
8942 8944 * Notes:
8943 8945 * - RESET_ALL: reset the controller
8944 8946 * - RESET_TARGET: reset the target specified in scsi_address
8945 8947 */
8946 8948 static int
8947 8949 mptsas_scsi_reset(struct scsi_address *ap, int level)
8948 8950 {
8949 8951 mptsas_t *mpt = ADDR2MPT(ap);
8950 8952 int rval;
8951 8953 mptsas_tgt_private_t *tgt_private;
8952 8954 mptsas_target_t *ptgt = NULL;
8953 8955
8954 8956 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->tran_tgt_private;
8955 8957 ptgt = tgt_private->t_private;
8956 8958 if (ptgt == NULL) {
8957 8959 return (FALSE);
8958 8960 }
8959 8961 NDBG22(("mptsas_scsi_reset: target=%d level=%d", ptgt->m_devhdl,
8960 8962 level));
8961 8963
8962 8964 mutex_enter(&mpt->m_mutex);
8963 8965 /*
8964 8966 * if we are not in panic set up a reset delay for this target
8965 8967 */
8966 8968 if (!ddi_in_panic()) {
8967 8969 mptsas_setup_bus_reset_delay(mpt);
8968 8970 } else {
8969 8971 drv_usecwait(mpt->m_scsi_reset_delay * 1000);
8970 8972 }
8971 8973 rval = mptsas_do_scsi_reset(mpt, ptgt->m_devhdl);
8972 8974 mutex_exit(&mpt->m_mutex);
8973 8975
8974 8976 /*
8975 8977 * The transport layer expect to only see TRUE and
8976 8978 * FALSE. Therefore, we will adjust the return value
8977 8979 * if mptsas_do_scsi_reset returns FAILED.
8978 8980 */
8979 8981 if (rval == FAILED)
8980 8982 rval = FALSE;
8981 8983 return (rval);
8982 8984 }
8983 8985
8984 8986 static int
8985 8987 mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl)
8986 8988 {
8987 8989 int rval = FALSE;
8988 8990 uint8_t config, disk;
8989 8991 mptsas_slots_t *slots = mpt->m_active;
8990 8992
8991 8993 ASSERT(mutex_owned(&mpt->m_mutex));
8992 8994
8993 8995 if (mptsas_debug_resets) {
8994 8996 mptsas_log(mpt, CE_WARN, "mptsas_do_scsi_reset: target=%d",
8995 8997 devhdl);
8996 8998 }
8997 8999
8998 9000 /*
8999 9001 * Issue a Target Reset message to the target specified but not to a
9000 9002 * disk making up a raid volume. Just look through the RAID config
9001 9003 * Phys Disk list of DevHandles. If the target's DevHandle is in this
9002 9004 * list, then don't reset this target.
9003 9005 */
9004 9006 for (config = 0; config < slots->m_num_raid_configs; config++) {
9005 9007 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) {
9006 9008 if (devhdl == slots->m_raidconfig[config].
9007 9009 m_physdisk_devhdl[disk]) {
9008 9010 return (TRUE);
9009 9011 }
9010 9012 }
9011 9013 }
9012 9014
9013 9015 rval = mptsas_ioc_task_management(mpt,
9014 9016 MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, devhdl, 0, NULL, 0, 0);
9015 9017
9016 9018 mptsas_doneq_empty(mpt);
9017 9019 return (rval);
9018 9020 }
9019 9021
9020 9022 static int
9021 9023 mptsas_scsi_reset_notify(struct scsi_address *ap, int flag,
9022 9024 void (*callback)(caddr_t), caddr_t arg)
9023 9025 {
9024 9026 mptsas_t *mpt = ADDR2MPT(ap);
9025 9027
9026 9028 NDBG22(("mptsas_scsi_reset_notify: tgt=%d", ap->a_target));
9027 9029
9028 9030 return (scsi_hba_reset_notify_setup(ap, flag, callback, arg,
9029 9031 &mpt->m_mutex, &mpt->m_reset_notify_listf));
9030 9032 }
9031 9033
9032 9034 static int
9033 9035 mptsas_get_name(struct scsi_device *sd, char *name, int len)
9034 9036 {
9035 9037 dev_info_t *lun_dip = NULL;
9036 9038
9037 9039 ASSERT(sd != NULL);
9038 9040 ASSERT(name != NULL);
9039 9041 lun_dip = sd->sd_dev;
9040 9042 ASSERT(lun_dip != NULL);
9041 9043
9042 9044 if (mptsas_name_child(lun_dip, name, len) == DDI_SUCCESS) {
9043 9045 return (1);
9044 9046 } else {
9045 9047 return (0);
9046 9048 }
9047 9049 }
9048 9050
9049 9051 static int
9050 9052 mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len)
9051 9053 {
9052 9054 return (mptsas_get_name(sd, name, len));
9053 9055 }
9054 9056
9055 9057 void
9056 9058 mptsas_set_throttle(mptsas_t *mpt, mptsas_target_t *ptgt, int what)
9057 9059 {
9058 9060
9059 9061 NDBG25(("mptsas_set_throttle: throttle=%x", what));
9060 9062
9061 9063 /*
9062 9064 * if the bus is draining/quiesced, no changes to the throttles
9063 9065 * are allowed. Not allowing change of throttles during draining
9064 9066 * limits error recovery but will reduce draining time
9065 9067 *
9066 9068 * all throttles should have been set to HOLD_THROTTLE
9067 9069 */
9068 9070 if (mpt->m_softstate & (MPTSAS_SS_QUIESCED | MPTSAS_SS_DRAINING)) {
9069 9071 return;
9070 9072 }
9071 9073
9072 9074 if (what == HOLD_THROTTLE) {
9073 9075 ptgt->m_t_throttle = HOLD_THROTTLE;
9074 9076 } else if (ptgt->m_reset_delay == 0) {
9075 9077 ptgt->m_t_throttle = what;
9076 9078 }
9077 9079 }
9078 9080
9079 9081 /*
9080 9082 * Clean up from a device reset.
9081 9083 * For the case of target reset, this function clears the waitq of all
9082 9084 * commands for a particular target. For the case of abort task set, this
9083 9085 * function clears the waitq of all commonds for a particular target/lun.
9084 9086 */
9085 9087 static void
9086 9088 mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, uint8_t tasktype)
9087 9089 {
9088 9090 mptsas_slots_t *slots = mpt->m_active;
9089 9091 mptsas_cmd_t *cmd, *next_cmd;
9090 9092 int slot;
9091 9093 uchar_t reason;
9092 9094 uint_t stat;
9093 9095
9094 9096 NDBG25(("mptsas_flush_target: target=%d lun=%d", target, lun));
9095 9097
9096 9098 /*
9097 9099 * Make sure the I/O Controller has flushed all cmds
9098 9100 * that are associated with this target for a target reset
9099 9101 * and target/lun for abort task set.
9100 9102 * Account for TM requests, which use the last SMID.
9101 9103 */
9102 9104 mutex_enter(&mpt->m_intr_mutex);
9103 9105 for (slot = 0; slot <= mpt->m_active->m_n_slots; slot++) {
9104 9106 if ((cmd = slots->m_slot[slot]) == NULL) {
9105 9107 continue;
9106 9108 }
9107 9109 reason = CMD_RESET;
9108 9110 stat = STAT_DEV_RESET;
9109 9111 switch (tasktype) {
9110 9112 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
9111 9113 if (Tgt(cmd) == target) {
9112 9114 NDBG25(("mptsas_flush_target discovered non-"
9113 9115 "NULL cmd in slot %d, tasktype 0x%x", slot,
9114 9116 tasktype));
9115 9117 mptsas_dump_cmd(mpt, cmd);
9116 9118 mptsas_remove_cmd0(mpt, cmd);
9117 9119 mptsas_set_pkt_reason(mpt, cmd, reason, stat);
9118 9120 mptsas_doneq_add0(mpt, cmd);
9119 9121 }
9120 9122 break;
9121 9123 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
9122 9124 reason = CMD_ABORTED;
9123 9125 stat = STAT_ABORTED;
9124 9126 /*FALLTHROUGH*/
9125 9127 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
9126 9128 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
9127 9129
9128 9130 NDBG25(("mptsas_flush_target discovered non-"
9129 9131 "NULL cmd in slot %d, tasktype 0x%x", slot,
9130 9132 tasktype));
9131 9133 mptsas_dump_cmd(mpt, cmd);
9132 9134 mptsas_remove_cmd0(mpt, cmd);
9133 9135 mptsas_set_pkt_reason(mpt, cmd, reason,
9134 9136 stat);
9135 9137 mptsas_doneq_add0(mpt, cmd);
9136 9138 }
9137 9139 break;
9138 9140 default:
9139 9141 break;
9140 9142 }
9141 9143 }
9142 9144 mutex_exit(&mpt->m_intr_mutex);
9143 9145
9144 9146 /*
9145 9147 * Flush the waitq of this target's cmds
9146 9148 */
9147 9149 cmd = mpt->m_waitq;
9148 9150
9149 9151 reason = CMD_RESET;
9150 9152 stat = STAT_DEV_RESET;
9151 9153
9152 9154 switch (tasktype) {
9153 9155 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
9154 9156 while (cmd != NULL) {
9155 9157 next_cmd = cmd->cmd_linkp;
9156 9158 if (Tgt(cmd) == target) {
9157 9159 mptsas_waitq_delete(mpt, cmd);
9158 9160 mptsas_set_pkt_reason(mpt, cmd,
9159 9161 reason, stat);
9160 9162 mptsas_doneq_add(mpt, cmd);
9161 9163 }
9162 9164 cmd = next_cmd;
9163 9165 }
9164 9166 break;
9165 9167 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
9166 9168 reason = CMD_ABORTED;
9167 9169 stat = STAT_ABORTED;
9168 9170 /*FALLTHROUGH*/
9169 9171 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
9170 9172 while (cmd != NULL) {
9171 9173 next_cmd = cmd->cmd_linkp;
9172 9174 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
9173 9175 mptsas_waitq_delete(mpt, cmd);
9174 9176 mptsas_set_pkt_reason(mpt, cmd,
9175 9177 reason, stat);
9176 9178 mptsas_doneq_add(mpt, cmd);
9177 9179 }
9178 9180 cmd = next_cmd;
9179 9181 }
9180 9182 break;
9181 9183 default:
9182 9184 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.",
9183 9185 tasktype);
9184 9186 break;
9185 9187 }
9186 9188 }
9187 9189
9188 9190 /*
9189 9191 * Clean up hba state, abort all outstanding command and commands in waitq
9190 9192 * reset timeout of all targets.
9191 9193 */
9192 9194 static void
9193 9195 mptsas_flush_hba(mptsas_t *mpt)
9194 9196 {
9195 9197 mptsas_slots_t *slots = mpt->m_active;
9196 9198 mptsas_cmd_t *cmd;
9197 9199 int slot;
9198 9200
9199 9201 NDBG25(("mptsas_flush_hba"));
9200 9202
9201 9203 /*
9202 9204 * The I/O Controller should have already sent back
9203 9205 * all commands via the scsi I/O reply frame. Make
9204 9206 * sure all commands have been flushed.
9205 9207 * Account for TM request, which use the last SMID.
9206 9208 */
9207 9209 mutex_enter(&mpt->m_intr_mutex);
9208 9210 for (slot = 0; slot <= mpt->m_active->m_n_slots; slot++) {
9209 9211 if ((cmd = slots->m_slot[slot]) == NULL) {
9210 9212 continue;
9211 9213 }
9212 9214
9213 9215 if (cmd->cmd_flags & CFLAG_CMDIOC) {
9214 9216 /*
9215 9217 * Need to make sure to tell everyone that might be
9216 9218 * waiting on this command that it's going to fail. If
9217 9219 * we get here, this command will never timeout because
9218 9220 * the active command table is going to be re-allocated,
9219 9221 * so there will be nothing to check against a time out.
9220 9222 * Instead, mark the command as failed due to reset.
9221 9223 */
9222 9224 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET,
9223 9225 STAT_BUS_RESET);
9224 9226 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
9225 9227 (cmd->cmd_flags & CFLAG_CONFIG) ||
9226 9228 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
9227 9229 cmd->cmd_flags |= CFLAG_FINISHED;
9228 9230 cv_broadcast(&mpt->m_passthru_cv);
9229 9231 cv_broadcast(&mpt->m_config_cv);
9230 9232 cv_broadcast(&mpt->m_fw_diag_cv);
9231 9233 }
9232 9234 continue;
9233 9235 }
9234 9236
9235 9237 NDBG25(("mptsas_flush_hba discovered non-NULL cmd in slot %d",
9236 9238 slot));
9237 9239 mptsas_dump_cmd(mpt, cmd);
9238 9240
9239 9241 mptsas_remove_cmd0(mpt, cmd);
9240 9242 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
9241 9243 mptsas_doneq_add0(mpt, cmd);
9242 9244 }
9243 9245 mutex_exit(&mpt->m_intr_mutex);
9244 9246
9245 9247 /*
9246 9248 * Flush the waitq.
9247 9249 */
9248 9250 while ((cmd = mptsas_waitq_rm(mpt)) != NULL) {
9249 9251 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
9250 9252 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
9251 9253 (cmd->cmd_flags & CFLAG_CONFIG) ||
9252 9254 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
9253 9255 cmd->cmd_flags |= CFLAG_FINISHED;
9254 9256 cv_broadcast(&mpt->m_passthru_cv);
9255 9257 cv_broadcast(&mpt->m_config_cv);
9256 9258 cv_broadcast(&mpt->m_fw_diag_cv);
9257 9259 } else {
9258 9260 mptsas_doneq_add(mpt, cmd);
9259 9261 }
9260 9262 }
9261 9263 }
9262 9264
9263 9265 /*
9264 9266 * set pkt_reason and OR in pkt_statistics flag
9265 9267 */
9266 9268 static void
9267 9269 mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, uchar_t reason,
9268 9270 uint_t stat)
9269 9271 {
9270 9272 #ifndef __lock_lint
9271 9273 _NOTE(ARGUNUSED(mpt))
9272 9274 #endif
9273 9275
9274 9276 NDBG25(("mptsas_set_pkt_reason: cmd=0x%p reason=%x stat=%x",
9275 9277 (void *)cmd, reason, stat));
9276 9278
9277 9279 if (cmd) {
9278 9280 if (cmd->cmd_pkt->pkt_reason == CMD_CMPLT) {
9279 9281 cmd->cmd_pkt->pkt_reason = reason;
9280 9282 }
9281 9283 cmd->cmd_pkt->pkt_statistics |= stat;
9282 9284 }
9283 9285 }
9284 9286
9285 9287 static void
9286 9288 mptsas_start_watch_reset_delay()
9287 9289 {
9288 9290 NDBG22(("mptsas_start_watch_reset_delay"));
9289 9291
9290 9292 mutex_enter(&mptsas_global_mutex);
9291 9293 if (mptsas_reset_watch == NULL && mptsas_timeouts_enabled) {
9292 9294 mptsas_reset_watch = timeout(mptsas_watch_reset_delay, NULL,
9293 9295 drv_usectohz((clock_t)
9294 9296 MPTSAS_WATCH_RESET_DELAY_TICK * 1000));
9295 9297 ASSERT(mptsas_reset_watch != NULL);
9296 9298 }
9297 9299 mutex_exit(&mptsas_global_mutex);
9298 9300 }
9299 9301
9300 9302 static void
9301 9303 mptsas_setup_bus_reset_delay(mptsas_t *mpt)
9302 9304 {
9303 9305 mptsas_target_t *ptgt = NULL;
9304 9306
9305 9307 NDBG22(("mptsas_setup_bus_reset_delay"));
9306 9308 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
9307 9309 MPTSAS_HASH_FIRST);
9308 9310 while (ptgt != NULL) {
9309 9311 mutex_enter(&ptgt->m_tgt_intr_mutex);
9310 9312 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
9311 9313 ptgt->m_reset_delay = mpt->m_scsi_reset_delay;
9312 9314 mutex_exit(&ptgt->m_tgt_intr_mutex);
9313 9315
9314 9316 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9315 9317 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9316 9318 }
9317 9319
9318 9320 mptsas_start_watch_reset_delay();
9319 9321 }
9320 9322
9321 9323 /*
9322 9324 * mptsas_watch_reset_delay(_subr) is invoked by timeout() and checks every
9323 9325 * mpt instance for active reset delays
9324 9326 */
9325 9327 static void
9326 9328 mptsas_watch_reset_delay(void *arg)
9327 9329 {
9328 9330 #ifndef __lock_lint
9329 9331 _NOTE(ARGUNUSED(arg))
9330 9332 #endif
9331 9333
9332 9334 mptsas_t *mpt;
9333 9335 int not_done = 0;
9334 9336
9335 9337 NDBG22(("mptsas_watch_reset_delay"));
9336 9338
9337 9339 mutex_enter(&mptsas_global_mutex);
9338 9340 mptsas_reset_watch = 0;
9339 9341 mutex_exit(&mptsas_global_mutex);
9340 9342 rw_enter(&mptsas_global_rwlock, RW_READER);
9341 9343 for (mpt = mptsas_head; mpt != NULL; mpt = mpt->m_next) {
9342 9344 if (mpt->m_tran == 0) {
9343 9345 continue;
9344 9346 }
9345 9347 mutex_enter(&mpt->m_mutex);
9346 9348 not_done += mptsas_watch_reset_delay_subr(mpt);
9347 9349 mutex_exit(&mpt->m_mutex);
9348 9350 }
9349 9351 rw_exit(&mptsas_global_rwlock);
9350 9352
9351 9353 if (not_done) {
9352 9354 mptsas_start_watch_reset_delay();
9353 9355 }
9354 9356 }
9355 9357
9356 9358 static int
9357 9359 mptsas_watch_reset_delay_subr(mptsas_t *mpt)
9358 9360 {
9359 9361 int done = 0;
9360 9362 int restart = 0;
9361 9363 mptsas_target_t *ptgt = NULL;
9362 9364
9363 9365 NDBG22(("mptsas_watch_reset_delay_subr: mpt=0x%p", (void *)mpt));
9364 9366
9365 9367 ASSERT(mutex_owned(&mpt->m_mutex));
9366 9368
9367 9369 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
9368 9370 MPTSAS_HASH_FIRST);
9369 9371 while (ptgt != NULL) {
9370 9372 mutex_enter(&ptgt->m_tgt_intr_mutex);
9371 9373 if (ptgt->m_reset_delay != 0) {
9372 9374 ptgt->m_reset_delay -=
9373 9375 MPTSAS_WATCH_RESET_DELAY_TICK;
9374 9376 if (ptgt->m_reset_delay <= 0) {
9375 9377 ptgt->m_reset_delay = 0;
9376 9378 mptsas_set_throttle(mpt, ptgt,
9377 9379 MAX_THROTTLE);
9378 9380 restart++;
9379 9381 } else {
9380 9382 done = -1;
9381 9383 }
9382 9384 }
9383 9385 mutex_exit(&ptgt->m_tgt_intr_mutex);
9384 9386
9385 9387 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9386 9388 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9387 9389 }
9388 9390
9389 9391 if (restart > 0) {
9390 9392 mptsas_restart_hba(mpt);
9391 9393 }
9392 9394 return (done);
9393 9395 }
9394 9396
9395 9397 #ifdef MPTSAS_TEST
9396 9398 static void
9397 9399 mptsas_test_reset(mptsas_t *mpt, int target)
9398 9400 {
9399 9401 mptsas_target_t *ptgt = NULL;
9400 9402
9401 9403 if (mptsas_rtest == target) {
9402 9404 if (mptsas_do_scsi_reset(mpt, target) == TRUE) {
9403 9405 mptsas_rtest = -1;
9404 9406 }
9405 9407 if (mptsas_rtest == -1) {
9406 9408 NDBG22(("mptsas_test_reset success"));
9407 9409 }
9408 9410 }
9409 9411 }
9410 9412 #endif
9411 9413
9412 9414 /*
9413 9415 * abort handling:
9414 9416 *
9415 9417 * Notes:
9416 9418 * - if pkt is not NULL, abort just that command
9417 9419 * - if pkt is NULL, abort all outstanding commands for target
9418 9420 */
9419 9421 static int
9420 9422 mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt)
9421 9423 {
9422 9424 mptsas_t *mpt = ADDR2MPT(ap);
9423 9425 int rval;
9424 9426 mptsas_tgt_private_t *tgt_private;
9425 9427 int target, lun;
9426 9428
9427 9429 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->
9428 9430 tran_tgt_private;
9429 9431 ASSERT(tgt_private != NULL);
9430 9432 target = tgt_private->t_private->m_devhdl;
9431 9433 lun = tgt_private->t_lun;
9432 9434
9433 9435 NDBG23(("mptsas_scsi_abort: target=%d.%d", target, lun));
9434 9436
9435 9437 mutex_enter(&mpt->m_mutex);
9436 9438 rval = mptsas_do_scsi_abort(mpt, target, lun, pkt);
9437 9439 mutex_exit(&mpt->m_mutex);
9438 9440 return (rval);
9439 9441 }
9440 9442
9441 9443 static int
9442 9444 mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, struct scsi_pkt *pkt)
9443 9445 {
9444 9446 mptsas_cmd_t *sp = NULL;
9445 9447 mptsas_slots_t *slots = mpt->m_active;
9446 9448 int rval = FALSE;
9447 9449
9448 9450 ASSERT(mutex_owned(&mpt->m_mutex));
9449 9451
9450 9452 /*
9451 9453 * Abort the command pkt on the target/lun in ap. If pkt is
9452 9454 * NULL, abort all outstanding commands on that target/lun.
9453 9455 * If you can abort them, return 1, else return 0.
9454 9456 * Each packet that's aborted should be sent back to the target
9455 9457 * driver through the callback routine, with pkt_reason set to
9456 9458 * CMD_ABORTED.
9457 9459 *
9458 9460 * abort cmd pkt on HBA hardware; clean out of outstanding
9459 9461 * command lists, etc.
9460 9462 */
9461 9463 if (pkt != NULL) {
9462 9464 /* abort the specified packet */
9463 9465 sp = PKT2CMD(pkt);
9464 9466
9465 9467 if (sp->cmd_queued) {
9466 9468 NDBG23(("mptsas_do_scsi_abort: queued sp=0x%p aborted",
9467 9469 (void *)sp));
9468 9470 mptsas_waitq_delete(mpt, sp);
9469 9471 mptsas_set_pkt_reason(mpt, sp, CMD_ABORTED,
9470 9472 STAT_ABORTED);
9471 9473 mptsas_doneq_add(mpt, sp);
9472 9474 rval = TRUE;
9473 9475 goto done;
9474 9476 }
9475 9477
9476 9478 /*
9477 9479 * Have mpt firmware abort this command
9478 9480 */
9479 9481 mutex_enter(&mpt->m_intr_mutex);
9480 9482 if (slots->m_slot[sp->cmd_slot] != NULL) {
9481 9483 mutex_exit(&mpt->m_intr_mutex);
9482 9484 rval = mptsas_ioc_task_management(mpt,
9483 9485 MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK, target,
9484 9486 lun, NULL, 0, 0);
9485 9487
9486 9488 /*
9487 9489 * The transport layer expects only TRUE and FALSE.
9488 9490 * Therefore, if mptsas_ioc_task_management returns
9489 9491 * FAILED we will return FALSE.
9490 9492 */
9491 9493 if (rval == FAILED)
9492 9494 rval = FALSE;
9493 9495 goto done;
9494 9496 }
9495 9497 mutex_exit(&mpt->m_intr_mutex);
9496 9498 }
9497 9499
9498 9500 /*
9499 9501 * If pkt is NULL then abort task set
9500 9502 */
9501 9503 rval = mptsas_ioc_task_management(mpt,
9502 9504 MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET, target, lun, NULL, 0, 0);
9503 9505
9504 9506 /*
9505 9507 * The transport layer expects only TRUE and FALSE.
9506 9508 * Therefore, if mptsas_ioc_task_management returns
9507 9509 * FAILED we will return FALSE.
9508 9510 */
9509 9511 if (rval == FAILED)
9510 9512 rval = FALSE;
9511 9513
9512 9514 #ifdef MPTSAS_TEST
9513 9515 if (rval && mptsas_test_stop) {
9514 9516 debug_enter("mptsas_do_scsi_abort");
9515 9517 }
9516 9518 #endif
9517 9519
9518 9520 done:
9519 9521 mptsas_doneq_empty(mpt);
9520 9522 return (rval);
9521 9523 }
9522 9524
9523 9525 /*
9524 9526 * capability handling:
9525 9527 * (*tran_getcap). Get the capability named, and return its value.
9526 9528 */
9527 9529 static int
9528 9530 mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly)
9529 9531 {
9530 9532 mptsas_t *mpt = ADDR2MPT(ap);
9531 9533 int ckey;
9532 9534 int rval = FALSE;
9533 9535
9534 9536 NDBG24(("mptsas_scsi_getcap: target=%d, cap=%s tgtonly=%x",
9535 9537 ap->a_target, cap, tgtonly));
9536 9538
9537 9539 mutex_enter(&mpt->m_mutex);
9538 9540
9539 9541 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) {
9540 9542 mutex_exit(&mpt->m_mutex);
9541 9543 return (UNDEFINED);
9542 9544 }
9543 9545
9544 9546 switch (ckey) {
9545 9547 case SCSI_CAP_DMA_MAX:
9546 9548 rval = (int)mpt->m_msg_dma_attr.dma_attr_maxxfer;
9547 9549 break;
9548 9550 case SCSI_CAP_ARQ:
9549 9551 rval = TRUE;
9550 9552 break;
9551 9553 case SCSI_CAP_MSG_OUT:
9552 9554 case SCSI_CAP_PARITY:
9553 9555 case SCSI_CAP_UNTAGGED_QING:
9554 9556 rval = TRUE;
9555 9557 break;
9556 9558 case SCSI_CAP_TAGGED_QING:
9557 9559 rval = TRUE;
9558 9560 break;
9559 9561 case SCSI_CAP_RESET_NOTIFICATION:
9560 9562 rval = TRUE;
9561 9563 break;
9562 9564 case SCSI_CAP_LINKED_CMDS:
9563 9565 rval = FALSE;
9564 9566 break;
9565 9567 case SCSI_CAP_QFULL_RETRIES:
9566 9568 rval = ((mptsas_tgt_private_t *)(ap->a_hba_tran->
9567 9569 tran_tgt_private))->t_private->m_qfull_retries;
9568 9570 break;
9569 9571 case SCSI_CAP_QFULL_RETRY_INTERVAL:
9570 9572 rval = drv_hztousec(((mptsas_tgt_private_t *)
9571 9573 (ap->a_hba_tran->tran_tgt_private))->
9572 9574 t_private->m_qfull_retry_interval) / 1000;
9573 9575 break;
9574 9576 case SCSI_CAP_CDB_LEN:
9575 9577 rval = CDB_GROUP4;
9576 9578 break;
9577 9579 case SCSI_CAP_INTERCONNECT_TYPE:
9578 9580 rval = INTERCONNECT_SAS;
9579 9581 break;
9580 9582 case SCSI_CAP_TRAN_LAYER_RETRIES:
9581 9583 if (mpt->m_ioc_capabilities &
9582 9584 MPI2_IOCFACTS_CAPABILITY_TLR)
9583 9585 rval = TRUE;
9584 9586 else
9585 9587 rval = FALSE;
9586 9588 break;
9587 9589 default:
9588 9590 rval = UNDEFINED;
9589 9591 break;
9590 9592 }
9591 9593
9592 9594 NDBG24(("mptsas_scsi_getcap: %s, rval=%x", cap, rval));
9593 9595
9594 9596 mutex_exit(&mpt->m_mutex);
9595 9597 return (rval);
9596 9598 }
9597 9599
9598 9600 /*
9599 9601 * (*tran_setcap). Set the capability named to the value given.
9600 9602 */
9601 9603 static int
9602 9604 mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, int tgtonly)
9603 9605 {
9604 9606 mptsas_t *mpt = ADDR2MPT(ap);
9605 9607 int ckey;
9606 9608 int rval = FALSE;
9607 9609 mptsas_target_t *ptgt;
9608 9610
9609 9611 NDBG24(("mptsas_scsi_setcap: target=%d, cap=%s value=%x tgtonly=%x",
9610 9612 ap->a_target, cap, value, tgtonly));
9611 9613
9612 9614 if (!tgtonly) {
9613 9615 return (rval);
9614 9616 }
9615 9617
9616 9618 mutex_enter(&mpt->m_mutex);
9617 9619
9618 9620 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) {
9619 9621 mutex_exit(&mpt->m_mutex);
9620 9622 return (UNDEFINED);
9621 9623 }
9622 9624
9623 9625 switch (ckey) {
9624 9626 case SCSI_CAP_DMA_MAX:
9625 9627 case SCSI_CAP_MSG_OUT:
9626 9628 case SCSI_CAP_PARITY:
9627 9629 case SCSI_CAP_INITIATOR_ID:
9628 9630 case SCSI_CAP_LINKED_CMDS:
9629 9631 case SCSI_CAP_UNTAGGED_QING:
9630 9632 case SCSI_CAP_RESET_NOTIFICATION:
9631 9633 /*
9632 9634 * None of these are settable via
9633 9635 * the capability interface.
9634 9636 */
9635 9637 break;
9636 9638 case SCSI_CAP_ARQ:
9637 9639 /*
9638 9640 * We cannot turn off arq so return false if asked to
9639 9641 */
9640 9642 if (value) {
9641 9643 rval = TRUE;
9642 9644 } else {
9643 9645 rval = FALSE;
9644 9646 }
9645 9647 break;
9646 9648 case SCSI_CAP_TAGGED_QING:
9647 9649 ptgt = ((mptsas_tgt_private_t *)
9648 9650 (ap->a_hba_tran->tran_tgt_private))->t_private;
9649 9651 mutex_enter(&ptgt->m_tgt_intr_mutex);
9650 9652 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
9651 9653 mutex_exit(&ptgt->m_tgt_intr_mutex);
9652 9654 rval = TRUE;
9653 9655 break;
9654 9656 case SCSI_CAP_QFULL_RETRIES:
9655 9657 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))->
9656 9658 t_private->m_qfull_retries = (uchar_t)value;
9657 9659 rval = TRUE;
9658 9660 break;
9659 9661 case SCSI_CAP_QFULL_RETRY_INTERVAL:
9660 9662 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))->
9661 9663 t_private->m_qfull_retry_interval =
9662 9664 drv_usectohz(value * 1000);
9663 9665 rval = TRUE;
9664 9666 break;
9665 9667 default:
9666 9668 rval = UNDEFINED;
9667 9669 break;
9668 9670 }
9669 9671 mutex_exit(&mpt->m_mutex);
9670 9672 return (rval);
9671 9673 }
9672 9674
9673 9675 /*
9674 9676 * Utility routine for mptsas_ifsetcap/ifgetcap
9675 9677 */
9676 9678 /*ARGSUSED*/
9677 9679 static int
9678 9680 mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp)
9679 9681 {
9680 9682 NDBG24(("mptsas_scsi_capchk: cap=%s", cap));
9681 9683
9682 9684 if (!cap)
9683 9685 return (FALSE);
9684 9686
9685 9687 *cidxp = scsi_hba_lookup_capstr(cap);
9686 9688 return (TRUE);
9687 9689 }
9688 9690
9689 9691 static int
9690 9692 mptsas_alloc_active_slots(mptsas_t *mpt, int flag)
9691 9693 {
9692 9694 mptsas_slots_t *old_active = mpt->m_active;
9693 9695 mptsas_slots_t *new_active;
9694 9696 size_t size;
9695 9697 int rval = -1, nslot, i;
9696 9698 mptsas_slot_free_e_t *pe;
9697 9699
9698 9700 if (mptsas_outstanding_cmds_n(mpt)) {
9699 9701 NDBG9(("cannot change size of active slots array"));
9700 9702 return (rval);
9701 9703 }
9702 9704
9703 9705 size = MPTSAS_SLOTS_SIZE(mpt);
9704 9706 new_active = kmem_zalloc(size, flag);
9705 9707 if (new_active == NULL) {
9706 9708 NDBG1(("new active alloc failed"));
9707 9709 return (rval);
9708 9710 }
9709 9711 /*
9710 9712 * Since SMID 0 is reserved and the TM slot is reserved, the
9711 9713 * number of slots that can be used at any one time is
9712 9714 * m_max_requests - 2.
9713 9715 */
9714 9716 new_active->m_n_slots = nslot = (mpt->m_max_requests - 2);
9715 9717 new_active->m_size = size;
9716 9718 new_active->m_tags = 1;
9717 9719
9718 9720 if (old_active) {
9719 9721 new_active->m_tgttbl = old_active->m_tgttbl;
9720 9722 new_active->m_smptbl = old_active->m_smptbl;
9721 9723 new_active->m_num_raid_configs =
9722 9724 old_active->m_num_raid_configs;
9723 9725 for (i = 0; i < new_active->m_num_raid_configs; i++) {
9724 9726 new_active->m_raidconfig[i] =
9725 9727 old_active->m_raidconfig[i];
9726 9728 }
9727 9729 mptsas_free_active_slots(mpt);
9728 9730 }
9729 9731
9730 9732 if (max_ncpus & (max_ncpus - 1)) {
9731 9733 mpt->m_slot_freeq_pair_n = (1 << highbit(max_ncpus));
9732 9734 } else {
9733 9735 mpt->m_slot_freeq_pair_n = max_ncpus;
9734 9736 }
9735 9737 mpt->m_slot_freeq_pairp = kmem_zalloc(
9736 9738 mpt->m_slot_freeq_pair_n *
9737 9739 sizeof (mptsas_slot_freeq_pair_t), KM_SLEEP);
9738 9740 for (i = 0; i < mpt->m_slot_freeq_pair_n; i++) {
9739 9741 list_create(&mpt->m_slot_freeq_pairp[i].
9740 9742 m_slot_allocq.s.m_fq_list,
9741 9743 sizeof (mptsas_slot_free_e_t),
9742 9744 offsetof(mptsas_slot_free_e_t, node));
9743 9745 list_create(&mpt->m_slot_freeq_pairp[i].
9744 9746 m_slot_releq.s.m_fq_list,
9745 9747 sizeof (mptsas_slot_free_e_t),
9746 9748 offsetof(mptsas_slot_free_e_t, node));
9747 9749 mpt->m_slot_freeq_pairp[i].m_slot_allocq.s.m_fq_n = 0;
9748 9750 mpt->m_slot_freeq_pairp[i].m_slot_releq.s.m_fq_n = 0;
9749 9751 mutex_init(&mpt->m_slot_freeq_pairp[i].
9750 9752 m_slot_allocq.s.m_fq_mutex, NULL, MUTEX_DRIVER,
9751 9753 DDI_INTR_PRI(mpt->m_intr_pri));
9752 9754 mutex_init(&mpt->m_slot_freeq_pairp[i].
9753 9755 m_slot_releq.s.m_fq_mutex, NULL, MUTEX_DRIVER,
9754 9756 DDI_INTR_PRI(mpt->m_intr_pri));
9755 9757 }
9756 9758 pe = mpt->m_slot_free_ae = kmem_zalloc(nslot *
9757 9759 sizeof (mptsas_slot_free_e_t), KM_SLEEP);
9758 9760 /*
9759 9761 * An array of Mpi2ReplyDescriptorsUnion_t is defined here.
9760 9762 * We are trying to eliminate the m_mutex in the context
9761 9763 * reply code path in the ISR. Since the read of the
9762 9764 * ReplyDescriptor and update/write of the ReplyIndex must
9763 9765 * be atomic (since the poll thread may also update them at
9764 9766 * the same time) so we first read out of the ReplyDescriptor
9765 9767 * into this array and update the ReplyIndex register with a
9766 9768 * separate mutex m_intr_mutex protected, and then release the
9767 9769 * mutex and process all of them. the length of the array is
9768 9770 * defined as max as 128(128*64=8k), which is
9769 9771 * assumed as the maxmium depth of the interrupt coalese.
9770 9772 */
9771 9773 mpt->m_reply = kmem_zalloc(MPI_ADDRESS_COALSCE_MAX *
9772 9774 sizeof (Mpi2ReplyDescriptorsUnion_t), KM_SLEEP);
9773 9775 for (i = 0; i < nslot; i++, pe++) {
9774 9776 pe->slot = i + 1; /* SMID 0 is reserved */
9775 9777 pe->cpuid = i % mpt->m_slot_freeq_pair_n;
9776 9778 list_insert_tail(&mpt->m_slot_freeq_pairp
9777 9779 [i % mpt->m_slot_freeq_pair_n]
9778 9780 .m_slot_allocq.s.m_fq_list, pe);
9779 9781 mpt->m_slot_freeq_pairp[i % mpt->m_slot_freeq_pair_n]
9780 9782 .m_slot_allocq.s.m_fq_n++;
9781 9783 mpt->m_slot_freeq_pairp[i % mpt->m_slot_freeq_pair_n]
9782 9784 .m_slot_allocq.s.m_fq_n_init++;
9783 9785 }
9784 9786
9785 9787 mpt->m_active = new_active;
9786 9788 rval = 0;
9787 9789
9788 9790 return (rval);
9789 9791 }
9790 9792
9791 9793 static void
9792 9794 mptsas_free_active_slots(mptsas_t *mpt)
9793 9795 {
9794 9796 mptsas_slots_t *active = mpt->m_active;
9795 9797 size_t size;
9796 9798 mptsas_slot_free_e_t *pe;
9797 9799 int i;
9798 9800
9799 9801 if (active == NULL)
9800 9802 return;
9801 9803
9802 9804 if (mpt->m_slot_freeq_pairp) {
9803 9805 for (i = 0; i < mpt->m_slot_freeq_pair_n; i++) {
9804 9806 while ((pe = list_head(&mpt->m_slot_freeq_pairp
9805 9807 [i].m_slot_allocq.s.m_fq_list)) != NULL) {
9806 9808 list_remove(&mpt->m_slot_freeq_pairp[i]
9807 9809 .m_slot_allocq.s.m_fq_list, pe);
9808 9810 }
9809 9811 list_destroy(&mpt->m_slot_freeq_pairp
9810 9812 [i].m_slot_allocq.s.m_fq_list);
9811 9813 while ((pe = list_head(&mpt->m_slot_freeq_pairp
9812 9814 [i].m_slot_releq.s.m_fq_list)) != NULL) {
9813 9815 list_remove(&mpt->m_slot_freeq_pairp[i]
9814 9816 .m_slot_releq.s.m_fq_list, pe);
9815 9817 }
9816 9818 list_destroy(&mpt->m_slot_freeq_pairp
9817 9819 [i].m_slot_releq.s.m_fq_list);
9818 9820 mutex_destroy(&mpt->m_slot_freeq_pairp
9819 9821 [i].m_slot_allocq.s.m_fq_mutex);
9820 9822 mutex_destroy(&mpt->m_slot_freeq_pairp
9821 9823 [i].m_slot_releq.s.m_fq_mutex);
9822 9824 }
9823 9825 kmem_free(mpt->m_slot_freeq_pairp, mpt->m_slot_freeq_pair_n *
9824 9826 sizeof (mptsas_slot_freeq_pair_t));
9825 9827 }
9826 9828 if (mpt->m_slot_free_ae)
9827 9829 kmem_free(mpt->m_slot_free_ae, mpt->m_active->m_n_slots *
9828 9830 sizeof (mptsas_slot_free_e_t));
9829 9831
9830 9832 if (mpt->m_reply)
9831 9833 kmem_free(mpt->m_reply, MPI_ADDRESS_COALSCE_MAX *
9832 9834 sizeof (Mpi2ReplyDescriptorsUnion_t));
9833 9835
9834 9836 size = active->m_size;
9835 9837 kmem_free(active, size);
9836 9838 mpt->m_active = NULL;
9837 9839 }
9838 9840
9839 9841 /*
9840 9842 * Error logging, printing, and debug print routines.
9841 9843 */
9842 9844 static char *mptsas_label = "mpt_sas";
9843 9845
9844 9846 /*PRINTFLIKE3*/
9845 9847 void
9846 9848 mptsas_log(mptsas_t *mpt, int level, char *fmt, ...)
9847 9849 {
9848 9850 dev_info_t *dev;
9849 9851 va_list ap;
9850 9852
9851 9853 if (mpt) {
9852 9854 dev = mpt->m_dip;
9853 9855 } else {
9854 9856 dev = 0;
9855 9857 }
9856 9858
9857 9859 mutex_enter(&mptsas_log_mutex);
9858 9860
9859 9861 va_start(ap, fmt);
9860 9862 (void) vsprintf(mptsas_log_buf, fmt, ap);
9861 9863 va_end(ap);
9862 9864
9863 9865 if (level == CE_CONT) {
9864 9866 scsi_log(dev, mptsas_label, level, "%s\n", mptsas_log_buf);
9865 9867 } else {
9866 9868 scsi_log(dev, mptsas_label, level, "%s", mptsas_log_buf);
9867 9869 }
9868 9870
9869 9871 mutex_exit(&mptsas_log_mutex);
9870 9872 }
9871 9873
9872 9874 #ifdef MPTSAS_DEBUG
9873 9875 /*PRINTFLIKE1*/
9874 9876 void
9875 9877 mptsas_printf(char *fmt, ...)
9876 9878 {
9877 9879 dev_info_t *dev = 0;
9878 9880 va_list ap;
9879 9881
9880 9882 mutex_enter(&mptsas_log_mutex);
9881 9883
9882 9884 va_start(ap, fmt);
9883 9885 (void) vsprintf(mptsas_log_buf, fmt, ap);
9884 9886 va_end(ap);
9885 9887
9886 9888 #ifdef PROM_PRINTF
9887 9889 prom_printf("%s:\t%s\n", mptsas_label, mptsas_log_buf);
9888 9890 #else
9889 9891 scsi_log(dev, mptsas_label, SCSI_DEBUG, "%s\n", mptsas_log_buf);
9890 9892 #endif
9891 9893 mutex_exit(&mptsas_log_mutex);
9892 9894 }
9893 9895 #endif
9894 9896
9895 9897 /*
9896 9898 * timeout handling
9897 9899 */
9898 9900 static void
9899 9901 mptsas_watch(void *arg)
9900 9902 {
9901 9903 #ifndef __lock_lint
9902 9904 _NOTE(ARGUNUSED(arg))
9903 9905 #endif
9904 9906
9905 9907 mptsas_t *mpt;
9906 9908 uint32_t doorbell;
9907 9909
9908 9910 NDBG30(("mptsas_watch"));
9909 9911
9910 9912 rw_enter(&mptsas_global_rwlock, RW_READER);
9911 9913 for (mpt = mptsas_head; mpt != (mptsas_t *)NULL; mpt = mpt->m_next) {
9912 9914
9913 9915 mutex_enter(&mpt->m_mutex);
9914 9916
9915 9917 /* Skip device if not powered on */
9916 9918 if (mpt->m_options & MPTSAS_OPT_PM) {
9917 9919 if (mpt->m_power_level == PM_LEVEL_D0) {
9918 9920 (void) pm_busy_component(mpt->m_dip, 0);
9919 9921 mpt->m_busy = 1;
9920 9922 } else {
9921 9923 mutex_exit(&mpt->m_mutex);
9922 9924 continue;
9923 9925 }
9924 9926 }
9925 9927
9926 9928 /*
9927 9929 * Check if controller is in a FAULT state. If so, reset it.
9928 9930 */
9929 9931 doorbell = ddi_get32(mpt->m_datap, &mpt->m_reg->Doorbell);
9930 9932 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
9931 9933 doorbell &= MPI2_DOORBELL_DATA_MASK;
9932 9934 mptsas_log(mpt, CE_WARN, "MPT Firmware Fault, "
9933 9935 "code: %04x", doorbell);
9934 9936 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
9935 9937 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
9936 9938 mptsas_log(mpt, CE_WARN, "Reset failed"
9937 9939 "after fault was detected");
9938 9940 }
9939 9941 }
9940 9942
9941 9943 /*
9942 9944 * For now, always call mptsas_watchsubr.
9943 9945 */
9944 9946 mptsas_watchsubr(mpt);
9945 9947
9946 9948 if (mpt->m_options & MPTSAS_OPT_PM) {
9947 9949 mpt->m_busy = 0;
9948 9950 (void) pm_idle_component(mpt->m_dip, 0);
9949 9951 }
9950 9952
9951 9953 mutex_exit(&mpt->m_mutex);
9952 9954 }
9953 9955 rw_exit(&mptsas_global_rwlock);
9954 9956
9955 9957 mutex_enter(&mptsas_global_mutex);
9956 9958 if (mptsas_timeouts_enabled)
9957 9959 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick);
9958 9960 mutex_exit(&mptsas_global_mutex);
9959 9961 }
9960 9962
9961 9963 static void
9962 9964 mptsas_watchsubr(mptsas_t *mpt)
9963 9965 {
9964 9966 int i;
9965 9967 mptsas_cmd_t *cmd;
9966 9968 mptsas_target_t *ptgt = NULL;
9967 9969
9968 9970 NDBG30(("mptsas_watchsubr: mpt=0x%p", (void *)mpt));
9969 9971
9970 9972 #ifdef MPTSAS_TEST
9971 9973 if (mptsas_enable_untagged) {
9972 9974 mptsas_test_untagged++;
9973 9975 }
9974 9976 #endif
9975 9977
9976 9978 /*
9977 9979 * Check for commands stuck in active slot
9978 9980 * Account for TM requests, which use the last SMID.
9979 9981 */
9980 9982 mutex_enter(&mpt->m_intr_mutex);
9981 9983 for (i = 0; i <= mpt->m_active->m_n_slots; i++) {
9982 9984 if ((cmd = mpt->m_active->m_slot[i]) != NULL) {
9983 9985 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
9984 9986 cmd->cmd_active_timeout -=
9985 9987 mptsas_scsi_watchdog_tick;
9986 9988 if (cmd->cmd_active_timeout <= 0) {
9987 9989 /*
9988 9990 * There seems to be a command stuck
9989 9991 * in the active slot. Drain throttle.
9990 9992 */
9991 9993 ptgt = cmd->cmd_tgt_addr;
9992 9994 mutex_enter(&ptgt->m_tgt_intr_mutex);
9993 9995 mptsas_set_throttle(mpt, ptgt,
9994 9996 DRAIN_THROTTLE);
9995 9997 mutex_exit(&ptgt->m_tgt_intr_mutex);
9996 9998 }
9997 9999 }
9998 10000 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
9999 10001 (cmd->cmd_flags & CFLAG_CONFIG) ||
10000 10002 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
10001 10003 cmd->cmd_active_timeout -=
10002 10004 mptsas_scsi_watchdog_tick;
10003 10005 if (cmd->cmd_active_timeout <= 0) {
10004 10006 /*
10005 10007 * passthrough command timeout
10006 10008 */
10007 10009 cmd->cmd_flags |= (CFLAG_FINISHED |
10008 10010 CFLAG_TIMEOUT);
10009 10011 cv_broadcast(&mpt->m_passthru_cv);
10010 10012 cv_broadcast(&mpt->m_config_cv);
10011 10013 cv_broadcast(&mpt->m_fw_diag_cv);
10012 10014 }
10013 10015 }
10014 10016 }
10015 10017 }
10016 10018 mutex_exit(&mpt->m_intr_mutex);
10017 10019
10018 10020 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
10019 10021 MPTSAS_HASH_FIRST);
10020 10022 while (ptgt != NULL) {
10021 10023 /*
10022 10024 * In order to avoid using m_mutex in the key code path in ISR,
10023 10025 * separate mutexs are introduced to protect those elements
10024 10026 * shown in ISR.
10025 10027 */
10026 10028 mutex_enter(&ptgt->m_tgt_intr_mutex);
10027 10029
10028 10030 /*
10029 10031 * If we were draining due to a qfull condition,
10030 10032 * go back to full throttle.
10031 10033 */
10032 10034 if ((ptgt->m_t_throttle < MAX_THROTTLE) &&
10033 10035 (ptgt->m_t_throttle > HOLD_THROTTLE) &&
10034 10036 (ptgt->m_t_ncmds < ptgt->m_t_throttle)) {
10035 10037 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
10036 10038 mptsas_restart_hba(mpt);
10037 10039 }
10038 10040
10039 10041 if ((ptgt->m_t_ncmds > 0) &&
10040 10042 (ptgt->m_timebase)) {
10041 10043
10042 10044 if (ptgt->m_timebase <=
10043 10045 mptsas_scsi_watchdog_tick) {
10044 10046 ptgt->m_timebase +=
10045 10047 mptsas_scsi_watchdog_tick;
10046 10048 mutex_exit(&ptgt->m_tgt_intr_mutex);
10047 10049 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
10048 10050 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
10049 10051 continue;
10050 10052 }
10051 10053
10052 10054 ptgt->m_timeout -= mptsas_scsi_watchdog_tick;
10053 10055
10054 10056 if (ptgt->m_timeout < 0) {
10055 10057 mutex_exit(&ptgt->m_tgt_intr_mutex);
10056 10058 mptsas_cmd_timeout(mpt, ptgt->m_devhdl);
10057 10059 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
10058 10060 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
10059 10061 continue;
10060 10062 }
10061 10063
10062 10064 if ((ptgt->m_timeout) <=
10063 10065 mptsas_scsi_watchdog_tick) {
10064 10066 NDBG23(("pending timeout"));
10065 10067 mptsas_set_throttle(mpt, ptgt,
10066 10068 DRAIN_THROTTLE);
10067 10069 }
10068 10070 }
10069 10071 mutex_exit(&ptgt->m_tgt_intr_mutex);
10070 10072 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
10071 10073 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
10072 10074 }
10073 10075 }
10074 10076
10075 10077 /*
10076 10078 * timeout recovery
10077 10079 */
10078 10080 static void
10079 10081 mptsas_cmd_timeout(mptsas_t *mpt, uint16_t devhdl)
10080 10082 {
10081 10083
10082 10084 NDBG29(("mptsas_cmd_timeout: target=%d", devhdl));
10083 10085 mptsas_log(mpt, CE_WARN, "Disconnected command timeout for "
10084 10086 "Target %d", devhdl);
10085 10087
10086 10088 /*
10087 10089 * If the current target is not the target passed in,
10088 10090 * try to reset that target.
10089 10091 */
10090 10092 NDBG29(("mptsas_cmd_timeout: device reset"));
10091 10093 if (mptsas_do_scsi_reset(mpt, devhdl) != TRUE) {
10092 10094 mptsas_log(mpt, CE_WARN, "Target %d reset for command timeout "
10093 10095 "recovery failed!", devhdl);
10094 10096 }
10095 10097 }
10096 10098
10097 10099 /*
10098 10100 * Device / Hotplug control
10099 10101 */
10100 10102 static int
10101 10103 mptsas_scsi_quiesce(dev_info_t *dip)
10102 10104 {
10103 10105 mptsas_t *mpt;
10104 10106 scsi_hba_tran_t *tran;
10105 10107
10106 10108 tran = ddi_get_driver_private(dip);
10107 10109 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL)
10108 10110 return (-1);
10109 10111
10110 10112 return (mptsas_quiesce_bus(mpt));
10111 10113 }
10112 10114
10113 10115 static int
10114 10116 mptsas_scsi_unquiesce(dev_info_t *dip)
10115 10117 {
10116 10118 mptsas_t *mpt;
10117 10119 scsi_hba_tran_t *tran;
10118 10120
10119 10121 tran = ddi_get_driver_private(dip);
10120 10122 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL)
10121 10123 return (-1);
10122 10124
10123 10125 return (mptsas_unquiesce_bus(mpt));
10124 10126 }
10125 10127
10126 10128 static int
10127 10129 mptsas_quiesce_bus(mptsas_t *mpt)
10128 10130 {
10129 10131 mptsas_target_t *ptgt = NULL;
10130 10132
10131 10133 NDBG28(("mptsas_quiesce_bus"));
10132 10134 mutex_enter(&mpt->m_mutex);
10133 10135
10134 10136 /* Set all the throttles to zero */
10135 10137 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
10136 10138 MPTSAS_HASH_FIRST);
10137 10139 while (ptgt != NULL) {
10138 10140 mutex_enter(&ptgt->m_tgt_intr_mutex);
10139 10141 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
10140 10142 mutex_exit(&ptgt->m_tgt_intr_mutex);
10141 10143
10142 10144 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
10143 10145 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
10144 10146 }
10145 10147
10146 10148 /* If there are any outstanding commands in the queue */
10147 10149 mutex_enter(&mpt->m_intr_mutex);
10148 10150 if (mptsas_outstanding_cmds_n(mpt)) {
10149 10151 mutex_exit(&mpt->m_intr_mutex);
10150 10152 mpt->m_softstate |= MPTSAS_SS_DRAINING;
10151 10153 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain,
10152 10154 mpt, (MPTSAS_QUIESCE_TIMEOUT * drv_usectohz(1000000)));
10153 10155 if (cv_wait_sig(&mpt->m_cv, &mpt->m_mutex) == 0) {
10154 10156 /*
10155 10157 * Quiesce has been interrupted
10156 10158 */
10157 10159 mpt->m_softstate &= ~MPTSAS_SS_DRAINING;
10158 10160 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
10159 10161 &mpt->m_active->m_tgttbl, MPTSAS_HASH_FIRST);
10160 10162 while (ptgt != NULL) {
10161 10163 mutex_enter(&ptgt->m_tgt_intr_mutex);
10162 10164 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
10163 10165 mutex_exit(&ptgt->m_tgt_intr_mutex);
10164 10166
10165 10167 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
10166 10168 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
10167 10169 }
10168 10170 mptsas_restart_hba(mpt);
10169 10171 if (mpt->m_quiesce_timeid != 0) {
10170 10172 timeout_id_t tid = mpt->m_quiesce_timeid;
10171 10173 mpt->m_quiesce_timeid = 0;
10172 10174 mutex_exit(&mpt->m_mutex);
10173 10175 (void) untimeout(tid);
10174 10176 return (-1);
10175 10177 }
10176 10178 mutex_exit(&mpt->m_mutex);
10177 10179 return (-1);
10178 10180 } else {
10179 10181 /* Bus has been quiesced */
10180 10182 ASSERT(mpt->m_quiesce_timeid == 0);
10181 10183 mpt->m_softstate &= ~MPTSAS_SS_DRAINING;
10182 10184 mpt->m_softstate |= MPTSAS_SS_QUIESCED;
10183 10185 mutex_exit(&mpt->m_mutex);
10184 10186 return (0);
10185 10187 }
10186 10188 }
10187 10189 mutex_exit(&mpt->m_intr_mutex);
10188 10190 /* Bus was not busy - QUIESCED */
10189 10191 mutex_exit(&mpt->m_mutex);
10190 10192
10191 10193 return (0);
10192 10194 }
10193 10195
10194 10196 static int
10195 10197 mptsas_unquiesce_bus(mptsas_t *mpt)
10196 10198 {
10197 10199 mptsas_target_t *ptgt = NULL;
10198 10200
10199 10201 NDBG28(("mptsas_unquiesce_bus"));
10200 10202 mutex_enter(&mpt->m_mutex);
10201 10203 mpt->m_softstate &= ~MPTSAS_SS_QUIESCED;
10202 10204 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
10203 10205 MPTSAS_HASH_FIRST);
10204 10206 while (ptgt != NULL) {
10205 10207 mutex_enter(&ptgt->m_tgt_intr_mutex);
10206 10208 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
10207 10209 mutex_exit(&ptgt->m_tgt_intr_mutex);
10208 10210
10209 10211 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
10210 10212 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
10211 10213 }
10212 10214 mptsas_restart_hba(mpt);
10213 10215 mutex_exit(&mpt->m_mutex);
10214 10216 return (0);
10215 10217 }
10216 10218
10217 10219 static void
10218 10220 mptsas_ncmds_checkdrain(void *arg)
10219 10221 {
10220 10222 mptsas_t *mpt = arg;
10221 10223 mptsas_target_t *ptgt = NULL;
10222 10224
10223 10225 mutex_enter(&mpt->m_mutex);
10224 10226 if (mpt->m_softstate & MPTSAS_SS_DRAINING) {
10225 10227 mpt->m_quiesce_timeid = 0;
10226 10228 mutex_enter(&mpt->m_intr_mutex);
10227 10229 if (mptsas_outstanding_cmds_n(mpt)) {
10228 10230 mutex_exit(&mpt->m_intr_mutex);
10229 10231 /*
10230 10232 * The throttle may have been reset because
10231 10233 * of a SCSI bus reset
10232 10234 */
10233 10235 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
10234 10236 &mpt->m_active->m_tgttbl, MPTSAS_HASH_FIRST);
10235 10237 while (ptgt != NULL) {
10236 10238 mutex_enter(&ptgt->m_tgt_intr_mutex);
10237 10239 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
10238 10240 mutex_exit(&ptgt->m_tgt_intr_mutex);
10239 10241
10240 10242 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
10241 10243 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
10242 10244 }
10243 10245
10244 10246 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain,
10245 10247 mpt, (MPTSAS_QUIESCE_TIMEOUT *
10246 10248 drv_usectohz(1000000)));
10247 10249 } else {
10248 10250 mutex_exit(&mpt->m_intr_mutex);
10249 10251 /* Command queue has been drained */
10250 10252 cv_signal(&mpt->m_cv);
10251 10253 }
10252 10254 }
10253 10255 mutex_exit(&mpt->m_mutex);
10254 10256 }
10255 10257
10256 10258 /*ARGSUSED*/
10257 10259 static void
10258 10260 mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
10259 10261 {
10260 10262 int i;
10261 10263 uint8_t *cp = (uchar_t *)cmd->cmd_pkt->pkt_cdbp;
10262 10264 char buf[128];
10263 10265
10264 10266 buf[0] = '\0';
10265 10267 NDBG25(("?Cmd (0x%p) dump for Target %d Lun %d:\n", (void *)cmd,
10266 10268 Tgt(cmd), Lun(cmd)));
10267 10269 (void) sprintf(&buf[0], "\tcdb=[");
10268 10270 for (i = 0; i < (int)cmd->cmd_cdblen; i++) {
10269 10271 (void) sprintf(&buf[strlen(buf)], " 0x%x", *cp++);
10270 10272 }
10271 10273 (void) sprintf(&buf[strlen(buf)], " ]");
10272 10274 NDBG25(("?%s\n", buf));
10273 10275 NDBG25(("?pkt_flags=0x%x pkt_statistics=0x%x pkt_state=0x%x\n",
10274 10276 cmd->cmd_pkt->pkt_flags, cmd->cmd_pkt->pkt_statistics,
10275 10277 cmd->cmd_pkt->pkt_state));
10276 10278 NDBG25(("?pkt_scbp=0x%x cmd_flags=0x%x\n", cmd->cmd_pkt->pkt_scbp ?
10277 10279 *(cmd->cmd_pkt->pkt_scbp) : 0, cmd->cmd_flags));
10278 10280 }
10279 10281
10280 10282 static void
10281 10283 mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd)
10282 10284 {
10283 10285 caddr_t memp;
10284 10286 pMPI2RequestHeader_t request_hdrp;
10285 10287 struct scsi_pkt *pkt = cmd->cmd_pkt;
10286 10288 mptsas_pt_request_t *pt = pkt->pkt_ha_private;
10287 10289 uint32_t request_size, data_size, dataout_size;
10288 10290 uint32_t direction;
10289 10291 ddi_dma_cookie_t data_cookie;
10290 10292 ddi_dma_cookie_t dataout_cookie;
10291 10293 uint32_t request_desc_low, request_desc_high = 0;
10292 10294 uint32_t i, sense_bufp;
10293 10295 uint8_t desc_type;
10294 10296 uint8_t *request, function;
10295 10297 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl;
10296 10298 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl;
10297 10299
10298 10300 desc_type = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
10299 10301
10300 10302 request = pt->request;
10301 10303 direction = pt->direction;
10302 10304 request_size = pt->request_size;
10303 10305 data_size = pt->data_size;
10304 10306 dataout_size = pt->dataout_size;
10305 10307 data_cookie = pt->data_cookie;
10306 10308 dataout_cookie = pt->dataout_cookie;
10307 10309
10308 10310 /*
10309 10311 * Store the passthrough message in memory location
10310 10312 * corresponding to our slot number
10311 10313 */
10312 10314 memp = mpt->m_req_frame + (mpt->m_req_frame_size * cmd->cmd_slot);
10313 10315 request_hdrp = (pMPI2RequestHeader_t)memp;
10314 10316 bzero(memp, mpt->m_req_frame_size);
10315 10317
10316 10318 for (i = 0; i < request_size; i++) {
10317 10319 bcopy(request + i, memp + i, 1);
10318 10320 }
10319 10321
10320 10322 if (data_size || dataout_size) {
10321 10323 pMpi2SGESimple64_t sgep;
10322 10324 uint32_t sge_flags;
10323 10325
10324 10326 sgep = (pMpi2SGESimple64_t)((uint8_t *)request_hdrp +
10325 10327 request_size);
10326 10328 if (dataout_size) {
10327 10329
10328 10330 sge_flags = dataout_size |
10329 10331 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
10330 10332 MPI2_SGE_FLAGS_END_OF_BUFFER |
10331 10333 MPI2_SGE_FLAGS_HOST_TO_IOC |
10332 10334 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
10333 10335 MPI2_SGE_FLAGS_SHIFT);
10334 10336 ddi_put32(acc_hdl, &sgep->FlagsLength, sge_flags);
10335 10337 ddi_put32(acc_hdl, &sgep->Address.Low,
10336 10338 (uint32_t)(dataout_cookie.dmac_laddress &
10337 10339 0xffffffffull));
10338 10340 ddi_put32(acc_hdl, &sgep->Address.High,
10339 10341 (uint32_t)(dataout_cookie.dmac_laddress
10340 10342 >> 32));
10341 10343 sgep++;
10342 10344 }
10343 10345 sge_flags = data_size;
10344 10346 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
10345 10347 MPI2_SGE_FLAGS_LAST_ELEMENT |
10346 10348 MPI2_SGE_FLAGS_END_OF_BUFFER |
10347 10349 MPI2_SGE_FLAGS_END_OF_LIST |
10348 10350 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
10349 10351 MPI2_SGE_FLAGS_SHIFT);
10350 10352 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) {
10351 10353 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) <<
10352 10354 MPI2_SGE_FLAGS_SHIFT);
10353 10355 } else {
10354 10356 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) <<
10355 10357 MPI2_SGE_FLAGS_SHIFT);
10356 10358 }
10357 10359 ddi_put32(acc_hdl, &sgep->FlagsLength,
10358 10360 sge_flags);
10359 10361 ddi_put32(acc_hdl, &sgep->Address.Low,
10360 10362 (uint32_t)(data_cookie.dmac_laddress &
10361 10363 0xffffffffull));
10362 10364 ddi_put32(acc_hdl, &sgep->Address.High,
10363 10365 (uint32_t)(data_cookie.dmac_laddress >> 32));
10364 10366 }
10365 10367
10366 10368 function = request_hdrp->Function;
10367 10369 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
10368 10370 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
10369 10371 pMpi2SCSIIORequest_t scsi_io_req;
10370 10372
10371 10373 scsi_io_req = (pMpi2SCSIIORequest_t)request_hdrp;
10372 10374 /*
10373 10375 * Put SGE for data and data_out buffer at the end of
10374 10376 * scsi_io_request message header.(64 bytes in total)
10375 10377 * Following above SGEs, the residual space will be
10376 10378 * used by sense data.
10377 10379 */
10378 10380 ddi_put8(acc_hdl,
10379 10381 &scsi_io_req->SenseBufferLength,
10380 10382 (uint8_t)(request_size - 64));
10381 10383
10382 10384 sense_bufp = mpt->m_req_frame_dma_addr +
10383 10385 (mpt->m_req_frame_size * cmd->cmd_slot);
10384 10386 sense_bufp += 64;
10385 10387 ddi_put32(acc_hdl,
10386 10388 &scsi_io_req->SenseBufferLowAddress, sense_bufp);
10387 10389
10388 10390 /*
10389 10391 * Set SGLOffset0 value
10390 10392 */
10391 10393 ddi_put8(acc_hdl, &scsi_io_req->SGLOffset0,
10392 10394 offsetof(MPI2_SCSI_IO_REQUEST, SGL) / 4);
10393 10395
10394 10396 /*
10395 10397 * Setup descriptor info. RAID passthrough must use the
10396 10398 * default request descriptor which is already set, so if this
10397 10399 * is a SCSI IO request, change the descriptor to SCSI IO.
10398 10400 */
10399 10401 if (function == MPI2_FUNCTION_SCSI_IO_REQUEST) {
10400 10402 desc_type = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
10401 10403 request_desc_high = (ddi_get16(acc_hdl,
10402 10404 &scsi_io_req->DevHandle) << 16);
10403 10405 }
10404 10406 }
10405 10407
10406 10408 /*
10407 10409 * We must wait till the message has been completed before
10408 10410 * beginning the next message so we wait for this one to
10409 10411 * finish.
10410 10412 */
10411 10413 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
10412 10414 request_desc_low = (cmd->cmd_slot << 16) + desc_type;
10413 10415 cmd->cmd_rfm = NULL;
10414 10416 mpt->m_active->m_slot[cmd->cmd_slot] = cmd;
10415 10417 MPTSAS_START_CMD(mpt, request_desc_low, request_desc_high);
10416 10418 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) ||
10417 10419 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) {
10418 10420 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
10419 10421 }
10420 10422 }
10421 10423
10422 10424
10423 10425
10424 10426 static int
10425 10427 mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply,
10426 10428 uint8_t *data, uint32_t request_size, uint32_t reply_size,
10427 10429 uint32_t data_size, uint32_t direction, uint8_t *dataout,
10428 10430 uint32_t dataout_size, short timeout, int mode)
10429 10431 {
10430 10432 mptsas_pt_request_t pt;
10431 10433 mptsas_dma_alloc_state_t data_dma_state;
10432 10434 mptsas_dma_alloc_state_t dataout_dma_state;
10433 10435 caddr_t memp;
10434 10436 mptsas_cmd_t *cmd = NULL;
10435 10437 struct scsi_pkt *pkt;
10436 10438 uint32_t reply_len = 0, sense_len = 0;
10437 10439 pMPI2RequestHeader_t request_hdrp;
10438 10440 pMPI2RequestHeader_t request_msg;
10439 10441 pMPI2DefaultReply_t reply_msg;
10440 10442 Mpi2SCSIIOReply_t rep_msg;
10441 10443 int i, status = 0, pt_flags = 0, rv = 0;
10442 10444 int rvalue;
10443 10445 uint8_t function;
10444 10446
10445 10447 ASSERT(mutex_owned(&mpt->m_mutex));
10446 10448
10447 10449 reply_msg = (pMPI2DefaultReply_t)(&rep_msg);
10448 10450 bzero(reply_msg, sizeof (MPI2_DEFAULT_REPLY));
10449 10451 request_msg = kmem_zalloc(request_size, KM_SLEEP);
10450 10452
10451 10453 mutex_exit(&mpt->m_mutex);
10452 10454 /*
10453 10455 * copy in the request buffer since it could be used by
10454 10456 * another thread when the pt request into waitq
10455 10457 */
10456 10458 if (ddi_copyin(request, request_msg, request_size, mode)) {
10457 10459 mutex_enter(&mpt->m_mutex);
10458 10460 status = EFAULT;
10459 10461 mptsas_log(mpt, CE_WARN, "failed to copy request data");
10460 10462 goto out;
10461 10463 }
10462 10464 mutex_enter(&mpt->m_mutex);
10463 10465
10464 10466 function = request_msg->Function;
10465 10467 if (function == MPI2_FUNCTION_SCSI_TASK_MGMT) {
10466 10468 pMpi2SCSITaskManagementRequest_t task;
10467 10469 task = (pMpi2SCSITaskManagementRequest_t)request_msg;
10468 10470 mptsas_setup_bus_reset_delay(mpt);
10469 10471 rv = mptsas_ioc_task_management(mpt, task->TaskType,
10470 10472 task->DevHandle, (int)task->LUN[1], reply, reply_size,
10471 10473 mode);
10472 10474
10473 10475 if (rv != TRUE) {
10474 10476 status = EIO;
10475 10477 mptsas_log(mpt, CE_WARN, "task management failed");
10476 10478 }
10477 10479 goto out;
10478 10480 }
10479 10481
10480 10482 if (data_size != 0) {
10481 10483 data_dma_state.size = data_size;
10482 10484 if (mptsas_dma_alloc(mpt, &data_dma_state) != DDI_SUCCESS) {
10483 10485 status = ENOMEM;
10484 10486 mptsas_log(mpt, CE_WARN, "failed to alloc DMA "
10485 10487 "resource");
10486 10488 goto out;
10487 10489 }
10488 10490 pt_flags |= MPTSAS_DATA_ALLOCATED;
10489 10491 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) {
10490 10492 mutex_exit(&mpt->m_mutex);
10491 10493 for (i = 0; i < data_size; i++) {
10492 10494 if (ddi_copyin(data + i, (uint8_t *)
10493 10495 data_dma_state.memp + i, 1, mode)) {
10494 10496 mutex_enter(&mpt->m_mutex);
10495 10497 status = EFAULT;
10496 10498 mptsas_log(mpt, CE_WARN, "failed to "
10497 10499 "copy read data");
10498 10500 goto out;
10499 10501 }
10500 10502 }
10501 10503 mutex_enter(&mpt->m_mutex);
10502 10504 }
10503 10505 }
10504 10506
10505 10507 if (dataout_size != 0) {
10506 10508 dataout_dma_state.size = dataout_size;
10507 10509 if (mptsas_dma_alloc(mpt, &dataout_dma_state) != DDI_SUCCESS) {
10508 10510 status = ENOMEM;
10509 10511 mptsas_log(mpt, CE_WARN, "failed to alloc DMA "
10510 10512 "resource");
10511 10513 goto out;
10512 10514 }
10513 10515 pt_flags |= MPTSAS_DATAOUT_ALLOCATED;
10514 10516 mutex_exit(&mpt->m_mutex);
10515 10517 for (i = 0; i < dataout_size; i++) {
10516 10518 if (ddi_copyin(dataout + i, (uint8_t *)
10517 10519 dataout_dma_state.memp + i, 1, mode)) {
10518 10520 mutex_enter(&mpt->m_mutex);
10519 10521 mptsas_log(mpt, CE_WARN, "failed to copy out"
10520 10522 " data");
10521 10523 status = EFAULT;
10522 10524 goto out;
10523 10525 }
10524 10526 }
10525 10527 mutex_enter(&mpt->m_mutex);
10526 10528 }
10527 10529
10528 10530 if ((rvalue = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
10529 10531 status = EAGAIN;
10530 10532 mptsas_log(mpt, CE_NOTE, "event ack command pool is full");
10531 10533 goto out;
10532 10534 }
10533 10535 pt_flags |= MPTSAS_REQUEST_POOL_CMD;
10534 10536
10535 10537 bzero((caddr_t)cmd, sizeof (*cmd));
10536 10538 bzero((caddr_t)pkt, scsi_pkt_size());
10537 10539 bzero((caddr_t)&pt, sizeof (pt));
10538 10540
10539 10541 cmd->ioc_cmd_slot = (uint32_t)(rvalue);
10540 10542
10541 10543 pt.request = (uint8_t *)request_msg;
10542 10544 pt.direction = direction;
10543 10545 pt.request_size = request_size;
10544 10546 pt.data_size = data_size;
10545 10547 pt.dataout_size = dataout_size;
10546 10548 pt.data_cookie = data_dma_state.cookie;
10547 10549 pt.dataout_cookie = dataout_dma_state.cookie;
10548 10550
10549 10551 /*
10550 10552 * Form a blank cmd/pkt to store the acknowledgement message
10551 10553 */
10552 10554 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb[0];
10553 10555 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb;
10554 10556 pkt->pkt_ha_private = (opaque_t)&pt;
10555 10557 pkt->pkt_flags = FLAG_HEAD;
10556 10558 pkt->pkt_time = timeout;
10557 10559 cmd->cmd_pkt = pkt;
10558 10560 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_PASSTHRU;
10559 10561
10560 10562 /*
10561 10563 * Save the command in a slot
10562 10564 */
10563 10565 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
10564 10566 /*
10565 10567 * Once passthru command get slot, set cmd_flags
10566 10568 * CFLAG_PREPARED.
10567 10569 */
10568 10570 cmd->cmd_flags |= CFLAG_PREPARED;
10569 10571 mptsas_start_passthru(mpt, cmd);
10570 10572 } else {
10571 10573 mptsas_waitq_add(mpt, cmd);
10572 10574 }
10573 10575
10574 10576 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
10575 10577 cv_wait(&mpt->m_passthru_cv, &mpt->m_mutex);
10576 10578 }
10577 10579
10578 10580 if (cmd->cmd_flags & CFLAG_PREPARED) {
10579 10581 memp = mpt->m_req_frame + (mpt->m_req_frame_size *
10580 10582 cmd->cmd_slot);
10581 10583 request_hdrp = (pMPI2RequestHeader_t)memp;
10582 10584 }
10583 10585
10584 10586 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
10585 10587 status = ETIMEDOUT;
10586 10588 mptsas_log(mpt, CE_WARN, "passthrough command timeout");
10587 10589 pt_flags |= MPTSAS_CMD_TIMEOUT;
10588 10590 goto out;
10589 10591 }
10590 10592
10591 10593 if (cmd->cmd_rfm) {
10592 10594 /*
10593 10595 * cmd_rfm is zero means the command reply is a CONTEXT
10594 10596 * reply and no PCI Write to post the free reply SMFA
10595 10597 * because no reply message frame is used.
10596 10598 * cmd_rfm is non-zero means the reply is a ADDRESS
10597 10599 * reply and reply message frame is used.
10598 10600 */
10599 10601 pt_flags |= MPTSAS_ADDRESS_REPLY;
10600 10602 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
10601 10603 DDI_DMA_SYNC_FORCPU);
10602 10604 reply_msg = (pMPI2DefaultReply_t)
10603 10605 (mpt->m_reply_frame + (cmd->cmd_rfm -
10604 10606 mpt->m_reply_frame_dma_addr));
10605 10607 }
10606 10608
10607 10609 mptsas_fma_check(mpt, cmd);
10608 10610 if (pkt->pkt_reason == CMD_TRAN_ERR) {
10609 10611 status = EAGAIN;
10610 10612 mptsas_log(mpt, CE_WARN, "passthru fma error");
10611 10613 goto out;
10612 10614 }
10613 10615 if (pkt->pkt_reason == CMD_RESET) {
10614 10616 status = EAGAIN;
10615 10617 mptsas_log(mpt, CE_WARN, "ioc reset abort passthru");
10616 10618 goto out;
10617 10619 }
10618 10620
10619 10621 if (pkt->pkt_reason == CMD_INCOMPLETE) {
10620 10622 status = EIO;
10621 10623 mptsas_log(mpt, CE_WARN, "passthrough command incomplete");
10622 10624 goto out;
10623 10625 }
10624 10626
10625 10627 mutex_exit(&mpt->m_mutex);
10626 10628 if (cmd->cmd_flags & CFLAG_PREPARED) {
10627 10629 function = request_hdrp->Function;
10628 10630 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
10629 10631 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
10630 10632 reply_len = sizeof (MPI2_SCSI_IO_REPLY);
10631 10633 sense_len = reply_size - reply_len;
10632 10634 } else {
10633 10635 reply_len = reply_size;
10634 10636 sense_len = 0;
10635 10637 }
10636 10638
10637 10639 for (i = 0; i < reply_len; i++) {
10638 10640 if (ddi_copyout((uint8_t *)reply_msg + i, reply + i, 1,
10639 10641 mode)) {
10640 10642 mutex_enter(&mpt->m_mutex);
10641 10643 status = EFAULT;
10642 10644 mptsas_log(mpt, CE_WARN, "failed to copy out "
10643 10645 "reply data");
10644 10646 goto out;
10645 10647 }
10646 10648 }
10647 10649 for (i = 0; i < sense_len; i++) {
10648 10650 if (ddi_copyout((uint8_t *)request_hdrp + 64 + i,
10649 10651 reply + reply_len + i, 1, mode)) {
10650 10652 mutex_enter(&mpt->m_mutex);
10651 10653 status = EFAULT;
10652 10654 mptsas_log(mpt, CE_WARN, "failed to copy out "
10653 10655 "sense data");
10654 10656 goto out;
10655 10657 }
10656 10658 }
10657 10659 }
10658 10660
10659 10661 if (data_size) {
10660 10662 if (direction != MPTSAS_PASS_THRU_DIRECTION_WRITE) {
10661 10663 (void) ddi_dma_sync(data_dma_state.handle, 0, 0,
10662 10664 DDI_DMA_SYNC_FORCPU);
10663 10665 for (i = 0; i < data_size; i++) {
10664 10666 if (ddi_copyout((uint8_t *)(
10665 10667 data_dma_state.memp + i), data + i, 1,
10666 10668 mode)) {
10667 10669 mutex_enter(&mpt->m_mutex);
10668 10670 status = EFAULT;
10669 10671 mptsas_log(mpt, CE_WARN, "failed to "
10670 10672 "copy out the reply data");
10671 10673 goto out;
10672 10674 }
10673 10675 }
10674 10676 }
10675 10677 }
10676 10678 mutex_enter(&mpt->m_mutex);
10677 10679 out:
10678 10680 /*
10679 10681 * Put the reply frame back on the free queue, increment the free
10680 10682 * index, and write the new index to the free index register. But only
10681 10683 * if this reply is an ADDRESS reply.
10682 10684 */
10683 10685 if (pt_flags & MPTSAS_ADDRESS_REPLY) {
10684 10686 ddi_put32(mpt->m_acc_free_queue_hdl,
10685 10687 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
10686 10688 cmd->cmd_rfm);
10687 10689 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
10688 10690 DDI_DMA_SYNC_FORDEV);
10689 10691 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
10690 10692 mpt->m_free_index = 0;
10691 10693 }
10692 10694 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
10693 10695 mpt->m_free_index);
10694 10696 }
10695 10697 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
10696 10698 mptsas_remove_cmd(mpt, cmd);
10697 10699 pt_flags &= (~MPTSAS_REQUEST_POOL_CMD);
10698 10700 }
10699 10701 if (pt_flags & MPTSAS_REQUEST_POOL_CMD)
10700 10702 mptsas_return_to_pool(mpt, cmd);
10701 10703 if (pt_flags & MPTSAS_DATA_ALLOCATED) {
10702 10704 if (mptsas_check_dma_handle(data_dma_state.handle) !=
10703 10705 DDI_SUCCESS) {
10704 10706 ddi_fm_service_impact(mpt->m_dip,
10705 10707 DDI_SERVICE_UNAFFECTED);
10706 10708 status = EFAULT;
10707 10709 }
10708 10710 mptsas_dma_free(&data_dma_state);
10709 10711 }
10710 10712 if (pt_flags & MPTSAS_DATAOUT_ALLOCATED) {
10711 10713 if (mptsas_check_dma_handle(dataout_dma_state.handle) !=
10712 10714 DDI_SUCCESS) {
10713 10715 ddi_fm_service_impact(mpt->m_dip,
10714 10716 DDI_SERVICE_UNAFFECTED);
10715 10717 status = EFAULT;
10716 10718 }
10717 10719 mptsas_dma_free(&dataout_dma_state);
10718 10720 }
10719 10721 if (pt_flags & MPTSAS_CMD_TIMEOUT) {
10720 10722 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
10721 10723 mptsas_log(mpt, CE_WARN, "mptsas_restart_ioc failed");
10722 10724 }
10723 10725 }
10724 10726 if (request_msg)
10725 10727 kmem_free(request_msg, request_size);
10726 10728
10727 10729 return (status);
10728 10730 }
10729 10731
10730 10732 static int
10731 10733 mptsas_pass_thru(mptsas_t *mpt, mptsas_pass_thru_t *data, int mode)
10732 10734 {
10733 10735 /*
10734 10736 * If timeout is 0, set timeout to default of 60 seconds.
10735 10737 */
10736 10738 if (data->Timeout == 0) {
10737 10739 data->Timeout = MPTSAS_PASS_THRU_TIME_DEFAULT;
10738 10740 }
10739 10741
10740 10742 if (((data->DataSize == 0) &&
10741 10743 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_NONE)) ||
10742 10744 ((data->DataSize != 0) &&
10743 10745 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_READ) ||
10744 10746 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_WRITE) ||
10745 10747 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) &&
10746 10748 (data->DataOutSize != 0))))) {
10747 10749 if (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) {
10748 10750 data->DataDirection = MPTSAS_PASS_THRU_DIRECTION_READ;
10749 10751 } else {
10750 10752 data->DataOutSize = 0;
10751 10753 }
10752 10754 /*
10753 10755 * Send passthru request messages
10754 10756 */
10755 10757 return (mptsas_do_passthru(mpt,
10756 10758 (uint8_t *)((uintptr_t)data->PtrRequest),
10757 10759 (uint8_t *)((uintptr_t)data->PtrReply),
10758 10760 (uint8_t *)((uintptr_t)data->PtrData),
10759 10761 data->RequestSize, data->ReplySize,
10760 10762 data->DataSize, data->DataDirection,
10761 10763 (uint8_t *)((uintptr_t)data->PtrDataOut),
10762 10764 data->DataOutSize, data->Timeout, mode));
10763 10765 } else {
10764 10766 return (EINVAL);
10765 10767 }
10766 10768 }
10767 10769
10768 10770 static uint8_t
10769 10771 mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, uint32_t unique_id)
10770 10772 {
10771 10773 uint8_t index;
10772 10774
10773 10775 for (index = 0; index < MPI2_DIAG_BUF_TYPE_COUNT; index++) {
10774 10776 if (mpt->m_fw_diag_buffer_list[index].unique_id == unique_id) {
10775 10777 return (index);
10776 10778 }
10777 10779 }
10778 10780
10779 10781 return (MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND);
10780 10782 }
10781 10783
10782 10784 static void
10783 10785 mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd)
10784 10786 {
10785 10787 pMpi2DiagBufferPostRequest_t pDiag_post_msg;
10786 10788 pMpi2DiagReleaseRequest_t pDiag_release_msg;
10787 10789 struct scsi_pkt *pkt = cmd->cmd_pkt;
10788 10790 mptsas_diag_request_t *diag = pkt->pkt_ha_private;
10789 10791 uint32_t request_desc_low, i;
10790 10792
10791 10793 ASSERT(mutex_owned(&mpt->m_mutex));
10792 10794
10793 10795 /*
10794 10796 * Form the diag message depending on the post or release function.
10795 10797 */
10796 10798 if (diag->function == MPI2_FUNCTION_DIAG_BUFFER_POST) {
10797 10799 pDiag_post_msg = (pMpi2DiagBufferPostRequest_t)
10798 10800 (mpt->m_req_frame + (mpt->m_req_frame_size *
10799 10801 cmd->cmd_slot));
10800 10802 bzero(pDiag_post_msg, mpt->m_req_frame_size);
10801 10803 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->Function,
10802 10804 diag->function);
10803 10805 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->BufferType,
10804 10806 diag->pBuffer->buffer_type);
10805 10807 ddi_put8(mpt->m_acc_req_frame_hdl,
10806 10808 &pDiag_post_msg->ExtendedType,
10807 10809 diag->pBuffer->extended_type);
10808 10810 ddi_put32(mpt->m_acc_req_frame_hdl,
10809 10811 &pDiag_post_msg->BufferLength,
10810 10812 diag->pBuffer->buffer_data.size);
10811 10813 for (i = 0; i < (sizeof (pDiag_post_msg->ProductSpecific) / 4);
10812 10814 i++) {
10813 10815 ddi_put32(mpt->m_acc_req_frame_hdl,
10814 10816 &pDiag_post_msg->ProductSpecific[i],
10815 10817 diag->pBuffer->product_specific[i]);
10816 10818 }
10817 10819 ddi_put32(mpt->m_acc_req_frame_hdl,
10818 10820 &pDiag_post_msg->BufferAddress.Low,
10819 10821 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress
10820 10822 & 0xffffffffull));
10821 10823 ddi_put32(mpt->m_acc_req_frame_hdl,
10822 10824 &pDiag_post_msg->BufferAddress.High,
10823 10825 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress
10824 10826 >> 32));
10825 10827 } else {
10826 10828 pDiag_release_msg = (pMpi2DiagReleaseRequest_t)
10827 10829 (mpt->m_req_frame + (mpt->m_req_frame_size *
10828 10830 cmd->cmd_slot));
10829 10831 bzero(pDiag_release_msg, mpt->m_req_frame_size);
10830 10832 ddi_put8(mpt->m_acc_req_frame_hdl,
10831 10833 &pDiag_release_msg->Function, diag->function);
10832 10834 ddi_put8(mpt->m_acc_req_frame_hdl,
10833 10835 &pDiag_release_msg->BufferType,
10834 10836 diag->pBuffer->buffer_type);
10835 10837 }
10836 10838
10837 10839 /*
10838 10840 * Send the message
10839 10841 */
10840 10842 (void) ddi_dma_sync(mpt->m_dma_req_frame_hdl, 0, 0,
10841 10843 DDI_DMA_SYNC_FORDEV);
10842 10844 request_desc_low = (cmd->cmd_slot << 16) +
10843 10845 MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
10844 10846 cmd->cmd_rfm = NULL;
10845 10847 mpt->m_active->m_slot[cmd->cmd_slot] = cmd;
10846 10848 MPTSAS_START_CMD(mpt, request_desc_low, 0);
10847 10849 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
10848 10850 DDI_SUCCESS) ||
10849 10851 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
10850 10852 DDI_SUCCESS)) {
10851 10853 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
10852 10854 }
10853 10855 }
10854 10856
10855 10857 static int
10856 10858 mptsas_post_fw_diag_buffer(mptsas_t *mpt,
10857 10859 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code)
10858 10860 {
10859 10861 mptsas_diag_request_t diag;
10860 10862 int status, slot_num, post_flags = 0;
10861 10863 mptsas_cmd_t *cmd = NULL;
10862 10864 struct scsi_pkt *pkt;
10863 10865 pMpi2DiagBufferPostReply_t reply;
10864 10866 uint16_t iocstatus;
10865 10867 uint32_t iocloginfo, transfer_length;
10866 10868
10867 10869 /*
10868 10870 * If buffer is not enabled, just leave.
10869 10871 */
10870 10872 *return_code = MPTSAS_FW_DIAG_ERROR_POST_FAILED;
10871 10873 if (!pBuffer->enabled) {
10872 10874 status = DDI_FAILURE;
10873 10875 goto out;
10874 10876 }
10875 10877
10876 10878 /*
10877 10879 * Clear some flags initially.
10878 10880 */
10879 10881 pBuffer->force_release = FALSE;
10880 10882 pBuffer->valid_data = FALSE;
10881 10883 pBuffer->owned_by_firmware = FALSE;
10882 10884
10883 10885 /*
10884 10886 * Get a cmd buffer from the cmd buffer pool
10885 10887 */
10886 10888 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
10887 10889 status = DDI_FAILURE;
10888 10890 mptsas_log(mpt, CE_NOTE, "command pool is full: Post FW Diag");
10889 10891 goto out;
10890 10892 }
10891 10893 post_flags |= MPTSAS_REQUEST_POOL_CMD;
10892 10894
10893 10895 bzero((caddr_t)cmd, sizeof (*cmd));
10894 10896 bzero((caddr_t)pkt, scsi_pkt_size());
10895 10897
10896 10898 cmd->ioc_cmd_slot = (uint32_t)(slot_num);
10897 10899
10898 10900 diag.pBuffer = pBuffer;
10899 10901 diag.function = MPI2_FUNCTION_DIAG_BUFFER_POST;
10900 10902
10901 10903 /*
10902 10904 * Form a blank cmd/pkt to store the acknowledgement message
10903 10905 */
10904 10906 pkt->pkt_ha_private = (opaque_t)&diag;
10905 10907 pkt->pkt_flags = FLAG_HEAD;
10906 10908 pkt->pkt_time = 60;
10907 10909 cmd->cmd_pkt = pkt;
10908 10910 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG;
10909 10911
10910 10912 /*
10911 10913 * Save the command in a slot
10912 10914 */
10913 10915 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
10914 10916 /*
10915 10917 * Once passthru command get slot, set cmd_flags
10916 10918 * CFLAG_PREPARED.
10917 10919 */
10918 10920 cmd->cmd_flags |= CFLAG_PREPARED;
10919 10921 mptsas_start_diag(mpt, cmd);
10920 10922 } else {
10921 10923 mptsas_waitq_add(mpt, cmd);
10922 10924 }
10923 10925
10924 10926 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
10925 10927 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex);
10926 10928 }
10927 10929
10928 10930 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
10929 10931 status = DDI_FAILURE;
10930 10932 mptsas_log(mpt, CE_WARN, "Post FW Diag command timeout");
10931 10933 goto out;
10932 10934 }
10933 10935
10934 10936 /*
10935 10937 * cmd_rfm points to the reply message if a reply was given. Check the
10936 10938 * IOCStatus to make sure everything went OK with the FW diag request
10937 10939 * and set buffer flags.
10938 10940 */
10939 10941 if (cmd->cmd_rfm) {
10940 10942 post_flags |= MPTSAS_ADDRESS_REPLY;
10941 10943 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
10942 10944 DDI_DMA_SYNC_FORCPU);
10943 10945 reply = (pMpi2DiagBufferPostReply_t)(mpt->m_reply_frame +
10944 10946 (cmd->cmd_rfm - mpt->m_reply_frame_dma_addr));
10945 10947
10946 10948 /*
10947 10949 * Get the reply message data
10948 10950 */
10949 10951 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
10950 10952 &reply->IOCStatus);
10951 10953 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
10952 10954 &reply->IOCLogInfo);
10953 10955 transfer_length = ddi_get32(mpt->m_acc_reply_frame_hdl,
10954 10956 &reply->TransferLength);
10955 10957
10956 10958 /*
10957 10959 * If post failed quit.
10958 10960 */
10959 10961 if (iocstatus != MPI2_IOCSTATUS_SUCCESS) {
10960 10962 status = DDI_FAILURE;
10961 10963 NDBG13(("post FW Diag Buffer failed: IOCStatus=0x%x, "
10962 10964 "IOCLogInfo=0x%x, TransferLength=0x%x", iocstatus,
10963 10965 iocloginfo, transfer_length));
10964 10966 goto out;
10965 10967 }
10966 10968
10967 10969 /*
10968 10970 * Post was successful.
10969 10971 */
10970 10972 pBuffer->valid_data = TRUE;
10971 10973 pBuffer->owned_by_firmware = TRUE;
10972 10974 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
10973 10975 status = DDI_SUCCESS;
10974 10976 }
10975 10977
10976 10978 out:
10977 10979 /*
10978 10980 * Put the reply frame back on the free queue, increment the free
10979 10981 * index, and write the new index to the free index register. But only
10980 10982 * if this reply is an ADDRESS reply.
10981 10983 */
10982 10984 if (post_flags & MPTSAS_ADDRESS_REPLY) {
10983 10985 ddi_put32(mpt->m_acc_free_queue_hdl,
10984 10986 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
10985 10987 cmd->cmd_rfm);
10986 10988 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
10987 10989 DDI_DMA_SYNC_FORDEV);
10988 10990 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
10989 10991 mpt->m_free_index = 0;
10990 10992 }
10991 10993 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
10992 10994 mpt->m_free_index);
10993 10995 }
10994 10996 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
10995 10997 mptsas_remove_cmd(mpt, cmd);
10996 10998 post_flags &= (~MPTSAS_REQUEST_POOL_CMD);
10997 10999 }
10998 11000 if (post_flags & MPTSAS_REQUEST_POOL_CMD) {
10999 11001 mptsas_return_to_pool(mpt, cmd);
11000 11002 }
11001 11003
11002 11004 return (status);
11003 11005 }
11004 11006
11005 11007 static int
11006 11008 mptsas_release_fw_diag_buffer(mptsas_t *mpt,
11007 11009 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code,
11008 11010 uint32_t diag_type)
11009 11011 {
11010 11012 mptsas_diag_request_t diag;
11011 11013 int status, slot_num, rel_flags = 0;
11012 11014 mptsas_cmd_t *cmd = NULL;
11013 11015 struct scsi_pkt *pkt;
11014 11016 pMpi2DiagReleaseReply_t reply;
11015 11017 uint16_t iocstatus;
11016 11018 uint32_t iocloginfo;
11017 11019
11018 11020 /*
11019 11021 * If buffer is not enabled, just leave.
11020 11022 */
11021 11023 *return_code = MPTSAS_FW_DIAG_ERROR_RELEASE_FAILED;
11022 11024 if (!pBuffer->enabled) {
11023 11025 mptsas_log(mpt, CE_NOTE, "This buffer type is not supported "
11024 11026 "by the IOC");
11025 11027 status = DDI_FAILURE;
11026 11028 goto out;
11027 11029 }
11028 11030
11029 11031 /*
11030 11032 * Clear some flags initially.
11031 11033 */
11032 11034 pBuffer->force_release = FALSE;
11033 11035 pBuffer->valid_data = FALSE;
11034 11036 pBuffer->owned_by_firmware = FALSE;
11035 11037
11036 11038 /*
11037 11039 * Get a cmd buffer from the cmd buffer pool
11038 11040 */
11039 11041 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
11040 11042 status = DDI_FAILURE;
11041 11043 mptsas_log(mpt, CE_NOTE, "command pool is full: Release FW "
11042 11044 "Diag");
11043 11045 goto out;
11044 11046 }
11045 11047 rel_flags |= MPTSAS_REQUEST_POOL_CMD;
11046 11048
11047 11049 bzero((caddr_t)cmd, sizeof (*cmd));
11048 11050 bzero((caddr_t)pkt, scsi_pkt_size());
11049 11051
11050 11052 cmd->ioc_cmd_slot = (uint32_t)(slot_num);
11051 11053
11052 11054 diag.pBuffer = pBuffer;
11053 11055 diag.function = MPI2_FUNCTION_DIAG_RELEASE;
11054 11056
11055 11057 /*
11056 11058 * Form a blank cmd/pkt to store the acknowledgement message
11057 11059 */
11058 11060 pkt->pkt_ha_private = (opaque_t)&diag;
11059 11061 pkt->pkt_flags = FLAG_HEAD;
11060 11062 pkt->pkt_time = 60;
11061 11063 cmd->cmd_pkt = pkt;
11062 11064 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG;
11063 11065
11064 11066 /*
11065 11067 * Save the command in a slot
11066 11068 */
11067 11069 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
11068 11070 /*
11069 11071 * Once passthru command get slot, set cmd_flags
11070 11072 * CFLAG_PREPARED.
11071 11073 */
11072 11074 cmd->cmd_flags |= CFLAG_PREPARED;
11073 11075 mptsas_start_diag(mpt, cmd);
11074 11076 } else {
11075 11077 mptsas_waitq_add(mpt, cmd);
11076 11078 }
11077 11079
11078 11080 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
11079 11081 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex);
11080 11082 }
11081 11083
11082 11084 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
11083 11085 status = DDI_FAILURE;
11084 11086 mptsas_log(mpt, CE_WARN, "Release FW Diag command timeout");
11085 11087 goto out;
11086 11088 }
11087 11089
11088 11090 /*
11089 11091 * cmd_rfm points to the reply message if a reply was given. Check the
11090 11092 * IOCStatus to make sure everything went OK with the FW diag request
11091 11093 * and set buffer flags.
11092 11094 */
11093 11095 if (cmd->cmd_rfm) {
11094 11096 rel_flags |= MPTSAS_ADDRESS_REPLY;
11095 11097 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
11096 11098 DDI_DMA_SYNC_FORCPU);
11097 11099 reply = (pMpi2DiagReleaseReply_t)(mpt->m_reply_frame +
11098 11100 (cmd->cmd_rfm - mpt->m_reply_frame_dma_addr));
11099 11101
11100 11102 /*
11101 11103 * Get the reply message data
11102 11104 */
11103 11105 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
11104 11106 &reply->IOCStatus);
11105 11107 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
11106 11108 &reply->IOCLogInfo);
11107 11109
11108 11110 /*
11109 11111 * If release failed quit.
11110 11112 */
11111 11113 if ((iocstatus != MPI2_IOCSTATUS_SUCCESS) ||
11112 11114 pBuffer->owned_by_firmware) {
11113 11115 status = DDI_FAILURE;
11114 11116 NDBG13(("release FW Diag Buffer failed: "
11115 11117 "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus,
11116 11118 iocloginfo));
11117 11119 goto out;
11118 11120 }
11119 11121
11120 11122 /*
11121 11123 * Release was successful.
11122 11124 */
11123 11125 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
11124 11126 status = DDI_SUCCESS;
11125 11127
11126 11128 /*
11127 11129 * If this was for an UNREGISTER diag type command, clear the
11128 11130 * unique ID.
11129 11131 */
11130 11132 if (diag_type == MPTSAS_FW_DIAG_TYPE_UNREGISTER) {
11131 11133 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID;
11132 11134 }
11133 11135 }
11134 11136
11135 11137 out:
11136 11138 /*
11137 11139 * Put the reply frame back on the free queue, increment the free
11138 11140 * index, and write the new index to the free index register. But only
11139 11141 * if this reply is an ADDRESS reply.
11140 11142 */
11141 11143 if (rel_flags & MPTSAS_ADDRESS_REPLY) {
11142 11144 ddi_put32(mpt->m_acc_free_queue_hdl,
11143 11145 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
11144 11146 cmd->cmd_rfm);
11145 11147 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
11146 11148 DDI_DMA_SYNC_FORDEV);
11147 11149 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
11148 11150 mpt->m_free_index = 0;
11149 11151 }
11150 11152 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
11151 11153 mpt->m_free_index);
11152 11154 }
11153 11155 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
11154 11156 mptsas_remove_cmd(mpt, cmd);
11155 11157 rel_flags &= (~MPTSAS_REQUEST_POOL_CMD);
11156 11158 }
11157 11159 if (rel_flags & MPTSAS_REQUEST_POOL_CMD) {
11158 11160 mptsas_return_to_pool(mpt, cmd);
11159 11161 }
11160 11162
11161 11163 return (status);
11162 11164 }
11163 11165
11164 11166 static int
11165 11167 mptsas_diag_register(mptsas_t *mpt, mptsas_fw_diag_register_t *diag_register,
11166 11168 uint32_t *return_code)
11167 11169 {
11168 11170 mptsas_fw_diagnostic_buffer_t *pBuffer;
11169 11171 uint8_t extended_type, buffer_type, i;
11170 11172 uint32_t buffer_size;
11171 11173 uint32_t unique_id;
11172 11174 int status;
11173 11175
11174 11176 ASSERT(mutex_owned(&mpt->m_mutex));
11175 11177
11176 11178 extended_type = diag_register->ExtendedType;
11177 11179 buffer_type = diag_register->BufferType;
11178 11180 buffer_size = diag_register->RequestedBufferSize;
11179 11181 unique_id = diag_register->UniqueId;
11180 11182
11181 11183 /*
11182 11184 * Check for valid buffer type
11183 11185 */
11184 11186 if (buffer_type >= MPI2_DIAG_BUF_TYPE_COUNT) {
11185 11187 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
11186 11188 return (DDI_FAILURE);
11187 11189 }
11188 11190
11189 11191 /*
11190 11192 * Get the current buffer and look up the unique ID. The unique ID
11191 11193 * should not be found. If it is, the ID is already in use.
11192 11194 */
11193 11195 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
11194 11196 pBuffer = &mpt->m_fw_diag_buffer_list[buffer_type];
11195 11197 if (i != MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
11196 11198 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11197 11199 return (DDI_FAILURE);
11198 11200 }
11199 11201
11200 11202 /*
11201 11203 * The buffer's unique ID should not be registered yet, and the given
11202 11204 * unique ID cannot be 0.
11203 11205 */
11204 11206 if ((pBuffer->unique_id != MPTSAS_FW_DIAG_INVALID_UID) ||
11205 11207 (unique_id == MPTSAS_FW_DIAG_INVALID_UID)) {
11206 11208 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11207 11209 return (DDI_FAILURE);
11208 11210 }
11209 11211
11210 11212 /*
11211 11213 * If this buffer is already posted as immediate, just change owner.
11212 11214 */
11213 11215 if (pBuffer->immediate && pBuffer->owned_by_firmware &&
11214 11216 (pBuffer->unique_id == MPTSAS_FW_DIAG_INVALID_UID)) {
11215 11217 pBuffer->immediate = FALSE;
11216 11218 pBuffer->unique_id = unique_id;
11217 11219 return (DDI_SUCCESS);
11218 11220 }
11219 11221
11220 11222 /*
11221 11223 * Post a new buffer after checking if it's enabled. The DMA buffer
11222 11224 * that is allocated will be contiguous (sgl_len = 1).
11223 11225 */
11224 11226 if (!pBuffer->enabled) {
11225 11227 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER;
11226 11228 return (DDI_FAILURE);
11227 11229 }
11228 11230 bzero(&pBuffer->buffer_data, sizeof (mptsas_dma_alloc_state_t));
11229 11231 pBuffer->buffer_data.size = buffer_size;
11230 11232 if (mptsas_dma_alloc(mpt, &pBuffer->buffer_data) != DDI_SUCCESS) {
11231 11233 mptsas_log(mpt, CE_WARN, "failed to alloc DMA resource for "
11232 11234 "diag buffer: size = %d bytes", buffer_size);
11233 11235 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER;
11234 11236 return (DDI_FAILURE);
11235 11237 }
11236 11238
11237 11239 /*
11238 11240 * Copy the given info to the diag buffer and post the buffer.
11239 11241 */
11240 11242 pBuffer->buffer_type = buffer_type;
11241 11243 pBuffer->immediate = FALSE;
11242 11244 if (buffer_type == MPI2_DIAG_BUF_TYPE_TRACE) {
11243 11245 for (i = 0; i < (sizeof (pBuffer->product_specific) / 4);
11244 11246 i++) {
11245 11247 pBuffer->product_specific[i] =
11246 11248 diag_register->ProductSpecific[i];
11247 11249 }
11248 11250 }
11249 11251 pBuffer->extended_type = extended_type;
11250 11252 pBuffer->unique_id = unique_id;
11251 11253 status = mptsas_post_fw_diag_buffer(mpt, pBuffer, return_code);
11252 11254
11253 11255 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) !=
11254 11256 DDI_SUCCESS) {
11255 11257 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed in "
11256 11258 "mptsas_diag_register.");
11257 11259 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
11258 11260 status = DDI_FAILURE;
11259 11261 }
11260 11262
11261 11263 /*
11262 11264 * In case there was a failure, free the DMA buffer.
11263 11265 */
11264 11266 if (status == DDI_FAILURE) {
11265 11267 mptsas_dma_free(&pBuffer->buffer_data);
11266 11268 }
11267 11269
11268 11270 return (status);
11269 11271 }
11270 11272
11271 11273 static int
11272 11274 mptsas_diag_unregister(mptsas_t *mpt,
11273 11275 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code)
11274 11276 {
11275 11277 mptsas_fw_diagnostic_buffer_t *pBuffer;
11276 11278 uint8_t i;
11277 11279 uint32_t unique_id;
11278 11280 int status;
11279 11281
11280 11282 ASSERT(mutex_owned(&mpt->m_mutex));
11281 11283
11282 11284 unique_id = diag_unregister->UniqueId;
11283 11285
11284 11286 /*
11285 11287 * Get the current buffer and look up the unique ID. The unique ID
11286 11288 * should be there.
11287 11289 */
11288 11290 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
11289 11291 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
11290 11292 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11291 11293 return (DDI_FAILURE);
11292 11294 }
11293 11295
11294 11296 pBuffer = &mpt->m_fw_diag_buffer_list[i];
11295 11297
11296 11298 /*
11297 11299 * Try to release the buffer from FW before freeing it. If release
11298 11300 * fails, don't free the DMA buffer in case FW tries to access it
11299 11301 * later. If buffer is not owned by firmware, can't release it.
11300 11302 */
11301 11303 if (!pBuffer->owned_by_firmware) {
11302 11304 status = DDI_SUCCESS;
11303 11305 } else {
11304 11306 status = mptsas_release_fw_diag_buffer(mpt, pBuffer,
11305 11307 return_code, MPTSAS_FW_DIAG_TYPE_UNREGISTER);
11306 11308 }
11307 11309
11308 11310 /*
11309 11311 * At this point, return the current status no matter what happens with
11310 11312 * the DMA buffer.
11311 11313 */
11312 11314 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID;
11313 11315 if (status == DDI_SUCCESS) {
11314 11316 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) !=
11315 11317 DDI_SUCCESS) {
11316 11318 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed "
11317 11319 "in mptsas_diag_unregister.");
11318 11320 ddi_fm_service_impact(mpt->m_dip,
11319 11321 DDI_SERVICE_UNAFFECTED);
11320 11322 }
11321 11323 mptsas_dma_free(&pBuffer->buffer_data);
11322 11324 }
11323 11325
11324 11326 return (status);
11325 11327 }
11326 11328
11327 11329 static int
11328 11330 mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query,
11329 11331 uint32_t *return_code)
11330 11332 {
11331 11333 mptsas_fw_diagnostic_buffer_t *pBuffer;
11332 11334 uint8_t i;
11333 11335 uint32_t unique_id;
11334 11336
11335 11337 ASSERT(mutex_owned(&mpt->m_mutex));
11336 11338
11337 11339 unique_id = diag_query->UniqueId;
11338 11340
11339 11341 /*
11340 11342 * If ID is valid, query on ID.
11341 11343 * If ID is invalid, query on buffer type.
11342 11344 */
11343 11345 if (unique_id == MPTSAS_FW_DIAG_INVALID_UID) {
11344 11346 i = diag_query->BufferType;
11345 11347 if (i >= MPI2_DIAG_BUF_TYPE_COUNT) {
11346 11348 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11347 11349 return (DDI_FAILURE);
11348 11350 }
11349 11351 } else {
11350 11352 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
11351 11353 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
11352 11354 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11353 11355 return (DDI_FAILURE);
11354 11356 }
11355 11357 }
11356 11358
11357 11359 /*
11358 11360 * Fill query structure with the diag buffer info.
11359 11361 */
11360 11362 pBuffer = &mpt->m_fw_diag_buffer_list[i];
11361 11363 diag_query->BufferType = pBuffer->buffer_type;
11362 11364 diag_query->ExtendedType = pBuffer->extended_type;
11363 11365 if (diag_query->BufferType == MPI2_DIAG_BUF_TYPE_TRACE) {
11364 11366 for (i = 0; i < (sizeof (diag_query->ProductSpecific) / 4);
11365 11367 i++) {
11366 11368 diag_query->ProductSpecific[i] =
11367 11369 pBuffer->product_specific[i];
11368 11370 }
11369 11371 }
11370 11372 diag_query->TotalBufferSize = pBuffer->buffer_data.size;
11371 11373 diag_query->DriverAddedBufferSize = 0;
11372 11374 diag_query->UniqueId = pBuffer->unique_id;
11373 11375 diag_query->ApplicationFlags = 0;
11374 11376 diag_query->DiagnosticFlags = 0;
11375 11377
11376 11378 /*
11377 11379 * Set/Clear application flags
11378 11380 */
11379 11381 if (pBuffer->immediate) {
11380 11382 diag_query->ApplicationFlags &= ~MPTSAS_FW_DIAG_FLAG_APP_OWNED;
11381 11383 } else {
11382 11384 diag_query->ApplicationFlags |= MPTSAS_FW_DIAG_FLAG_APP_OWNED;
11383 11385 }
11384 11386 if (pBuffer->valid_data || pBuffer->owned_by_firmware) {
11385 11387 diag_query->ApplicationFlags |=
11386 11388 MPTSAS_FW_DIAG_FLAG_BUFFER_VALID;
11387 11389 } else {
11388 11390 diag_query->ApplicationFlags &=
11389 11391 ~MPTSAS_FW_DIAG_FLAG_BUFFER_VALID;
11390 11392 }
11391 11393 if (pBuffer->owned_by_firmware) {
11392 11394 diag_query->ApplicationFlags |=
11393 11395 MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS;
11394 11396 } else {
11395 11397 diag_query->ApplicationFlags &=
11396 11398 ~MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS;
11397 11399 }
11398 11400
11399 11401 return (DDI_SUCCESS);
11400 11402 }
11401 11403
11402 11404 static int
11403 11405 mptsas_diag_read_buffer(mptsas_t *mpt,
11404 11406 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf,
11405 11407 uint32_t *return_code, int ioctl_mode)
11406 11408 {
11407 11409 mptsas_fw_diagnostic_buffer_t *pBuffer;
11408 11410 uint8_t i, *pData;
11409 11411 uint32_t unique_id, byte;
11410 11412 int status;
11411 11413
11412 11414 ASSERT(mutex_owned(&mpt->m_mutex));
11413 11415
11414 11416 unique_id = diag_read_buffer->UniqueId;
11415 11417
11416 11418 /*
11417 11419 * Get the current buffer and look up the unique ID. The unique ID
11418 11420 * should be there.
11419 11421 */
11420 11422 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
11421 11423 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
11422 11424 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11423 11425 return (DDI_FAILURE);
11424 11426 }
11425 11427
11426 11428 pBuffer = &mpt->m_fw_diag_buffer_list[i];
11427 11429
11428 11430 /*
11429 11431 * Make sure requested read is within limits
11430 11432 */
11431 11433 if (diag_read_buffer->StartingOffset + diag_read_buffer->BytesToRead >
11432 11434 pBuffer->buffer_data.size) {
11433 11435 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
11434 11436 return (DDI_FAILURE);
11435 11437 }
11436 11438
11437 11439 /*
11438 11440 * Copy the requested data from DMA to the diag_read_buffer. The DMA
11439 11441 * buffer that was allocated is one contiguous buffer.
11440 11442 */
11441 11443 pData = (uint8_t *)(pBuffer->buffer_data.memp +
11442 11444 diag_read_buffer->StartingOffset);
11443 11445 (void) ddi_dma_sync(pBuffer->buffer_data.handle, 0, 0,
11444 11446 DDI_DMA_SYNC_FORCPU);
11445 11447 for (byte = 0; byte < diag_read_buffer->BytesToRead; byte++) {
11446 11448 if (ddi_copyout(pData + byte, ioctl_buf + byte, 1, ioctl_mode)
11447 11449 != 0) {
11448 11450 return (DDI_FAILURE);
11449 11451 }
11450 11452 }
11451 11453 diag_read_buffer->Status = 0;
11452 11454
11453 11455 /*
11454 11456 * Set or clear the Force Release flag.
11455 11457 */
11456 11458 if (pBuffer->force_release) {
11457 11459 diag_read_buffer->Flags |= MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE;
11458 11460 } else {
11459 11461 diag_read_buffer->Flags &= ~MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE;
11460 11462 }
11461 11463
11462 11464 /*
11463 11465 * If buffer is to be reregistered, make sure it's not already owned by
11464 11466 * firmware first.
11465 11467 */
11466 11468 status = DDI_SUCCESS;
11467 11469 if (!pBuffer->owned_by_firmware) {
11468 11470 if (diag_read_buffer->Flags & MPTSAS_FW_DIAG_FLAG_REREGISTER) {
11469 11471 status = mptsas_post_fw_diag_buffer(mpt, pBuffer,
11470 11472 return_code);
11471 11473 }
11472 11474 }
11473 11475
11474 11476 return (status);
11475 11477 }
11476 11478
11477 11479 static int
11478 11480 mptsas_diag_release(mptsas_t *mpt, mptsas_fw_diag_release_t *diag_release,
11479 11481 uint32_t *return_code)
11480 11482 {
11481 11483 mptsas_fw_diagnostic_buffer_t *pBuffer;
11482 11484 uint8_t i;
11483 11485 uint32_t unique_id;
11484 11486 int status;
11485 11487
11486 11488 ASSERT(mutex_owned(&mpt->m_mutex));
11487 11489
11488 11490 unique_id = diag_release->UniqueId;
11489 11491
11490 11492 /*
11491 11493 * Get the current buffer and look up the unique ID. The unique ID
11492 11494 * should be there.
11493 11495 */
11494 11496 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
11495 11497 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
11496 11498 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11497 11499 return (DDI_FAILURE);
11498 11500 }
11499 11501
11500 11502 pBuffer = &mpt->m_fw_diag_buffer_list[i];
11501 11503
11502 11504 /*
11503 11505 * If buffer is not owned by firmware, it's already been released.
11504 11506 */
11505 11507 if (!pBuffer->owned_by_firmware) {
11506 11508 *return_code = MPTSAS_FW_DIAG_ERROR_ALREADY_RELEASED;
11507 11509 return (DDI_FAILURE);
11508 11510 }
11509 11511
11510 11512 /*
11511 11513 * Release the buffer.
11512 11514 */
11513 11515 status = mptsas_release_fw_diag_buffer(mpt, pBuffer, return_code,
11514 11516 MPTSAS_FW_DIAG_TYPE_RELEASE);
11515 11517 return (status);
11516 11518 }
11517 11519
11518 11520 static int
11519 11521 mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, uint8_t *diag_action,
11520 11522 uint32_t length, uint32_t *return_code, int ioctl_mode)
11521 11523 {
11522 11524 mptsas_fw_diag_register_t diag_register;
11523 11525 mptsas_fw_diag_unregister_t diag_unregister;
11524 11526 mptsas_fw_diag_query_t diag_query;
11525 11527 mptsas_diag_read_buffer_t diag_read_buffer;
11526 11528 mptsas_fw_diag_release_t diag_release;
11527 11529 int status = DDI_SUCCESS;
11528 11530 uint32_t original_return_code, read_buf_len;
11529 11531
11530 11532 ASSERT(mutex_owned(&mpt->m_mutex));
11531 11533
11532 11534 original_return_code = *return_code;
11533 11535 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
11534 11536
11535 11537 switch (action) {
11536 11538 case MPTSAS_FW_DIAG_TYPE_REGISTER:
11537 11539 if (!length) {
11538 11540 *return_code =
11539 11541 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
11540 11542 status = DDI_FAILURE;
11541 11543 break;
11542 11544 }
11543 11545 if (ddi_copyin(diag_action, &diag_register,
11544 11546 sizeof (diag_register), ioctl_mode) != 0) {
11545 11547 return (DDI_FAILURE);
11546 11548 }
11547 11549 status = mptsas_diag_register(mpt, &diag_register,
11548 11550 return_code);
11549 11551 break;
11550 11552
11551 11553 case MPTSAS_FW_DIAG_TYPE_UNREGISTER:
11552 11554 if (length < sizeof (diag_unregister)) {
11553 11555 *return_code =
11554 11556 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
11555 11557 status = DDI_FAILURE;
11556 11558 break;
11557 11559 }
11558 11560 if (ddi_copyin(diag_action, &diag_unregister,
11559 11561 sizeof (diag_unregister), ioctl_mode) != 0) {
11560 11562 return (DDI_FAILURE);
11561 11563 }
11562 11564 status = mptsas_diag_unregister(mpt, &diag_unregister,
11563 11565 return_code);
11564 11566 break;
11565 11567
11566 11568 case MPTSAS_FW_DIAG_TYPE_QUERY:
11567 11569 if (length < sizeof (diag_query)) {
11568 11570 *return_code =
11569 11571 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
11570 11572 status = DDI_FAILURE;
11571 11573 break;
11572 11574 }
11573 11575 if (ddi_copyin(diag_action, &diag_query,
11574 11576 sizeof (diag_query), ioctl_mode) != 0) {
11575 11577 return (DDI_FAILURE);
11576 11578 }
11577 11579 status = mptsas_diag_query(mpt, &diag_query,
11578 11580 return_code);
11579 11581 if (status == DDI_SUCCESS) {
11580 11582 if (ddi_copyout(&diag_query, diag_action,
11581 11583 sizeof (diag_query), ioctl_mode) != 0) {
11582 11584 return (DDI_FAILURE);
11583 11585 }
11584 11586 }
11585 11587 break;
11586 11588
11587 11589 case MPTSAS_FW_DIAG_TYPE_READ_BUFFER:
11588 11590 if (ddi_copyin(diag_action, &diag_read_buffer,
11589 11591 sizeof (diag_read_buffer) - 4, ioctl_mode) != 0) {
11590 11592 return (DDI_FAILURE);
11591 11593 }
11592 11594 read_buf_len = sizeof (diag_read_buffer) -
11593 11595 sizeof (diag_read_buffer.DataBuffer) +
11594 11596 diag_read_buffer.BytesToRead;
11595 11597 if (length < read_buf_len) {
11596 11598 *return_code =
11597 11599 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
11598 11600 status = DDI_FAILURE;
11599 11601 break;
11600 11602 }
11601 11603 status = mptsas_diag_read_buffer(mpt,
11602 11604 &diag_read_buffer, diag_action +
11603 11605 sizeof (diag_read_buffer) - 4, return_code,
11604 11606 ioctl_mode);
11605 11607 if (status == DDI_SUCCESS) {
11606 11608 if (ddi_copyout(&diag_read_buffer, diag_action,
11607 11609 sizeof (diag_read_buffer) - 4, ioctl_mode)
11608 11610 != 0) {
11609 11611 return (DDI_FAILURE);
11610 11612 }
11611 11613 }
11612 11614 break;
11613 11615
11614 11616 case MPTSAS_FW_DIAG_TYPE_RELEASE:
11615 11617 if (length < sizeof (diag_release)) {
11616 11618 *return_code =
11617 11619 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
11618 11620 status = DDI_FAILURE;
11619 11621 break;
11620 11622 }
11621 11623 if (ddi_copyin(diag_action, &diag_release,
11622 11624 sizeof (diag_release), ioctl_mode) != 0) {
11623 11625 return (DDI_FAILURE);
11624 11626 }
11625 11627 status = mptsas_diag_release(mpt, &diag_release,
11626 11628 return_code);
11627 11629 break;
11628 11630
11629 11631 default:
11630 11632 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
11631 11633 status = DDI_FAILURE;
11632 11634 break;
11633 11635 }
11634 11636
11635 11637 if ((status == DDI_FAILURE) &&
11636 11638 (original_return_code == MPTSAS_FW_DIAG_NEW) &&
11637 11639 (*return_code != MPTSAS_FW_DIAG_ERROR_SUCCESS)) {
11638 11640 status = DDI_SUCCESS;
11639 11641 }
11640 11642
11641 11643 return (status);
11642 11644 }
11643 11645
11644 11646 static int
11645 11647 mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *user_data, int mode)
11646 11648 {
11647 11649 int status;
11648 11650 mptsas_diag_action_t driver_data;
11649 11651
11650 11652 ASSERT(mutex_owned(&mpt->m_mutex));
11651 11653
11652 11654 /*
11653 11655 * Copy the user data to a driver data buffer.
11654 11656 */
11655 11657 if (ddi_copyin(user_data, &driver_data, sizeof (mptsas_diag_action_t),
11656 11658 mode) == 0) {
11657 11659 /*
11658 11660 * Send diag action request if Action is valid
11659 11661 */
11660 11662 if (driver_data.Action == MPTSAS_FW_DIAG_TYPE_REGISTER ||
11661 11663 driver_data.Action == MPTSAS_FW_DIAG_TYPE_UNREGISTER ||
11662 11664 driver_data.Action == MPTSAS_FW_DIAG_TYPE_QUERY ||
11663 11665 driver_data.Action == MPTSAS_FW_DIAG_TYPE_READ_BUFFER ||
11664 11666 driver_data.Action == MPTSAS_FW_DIAG_TYPE_RELEASE) {
11665 11667 status = mptsas_do_diag_action(mpt, driver_data.Action,
11666 11668 (void *)(uintptr_t)driver_data.PtrDiagAction,
11667 11669 driver_data.Length, &driver_data.ReturnCode,
11668 11670 mode);
11669 11671 if (status == DDI_SUCCESS) {
11670 11672 if (ddi_copyout(&driver_data.ReturnCode,
11671 11673 &user_data->ReturnCode,
11672 11674 sizeof (user_data->ReturnCode), mode)
11673 11675 != 0) {
11674 11676 status = EFAULT;
11675 11677 } else {
11676 11678 status = 0;
11677 11679 }
11678 11680 } else {
11679 11681 status = EIO;
11680 11682 }
11681 11683 } else {
11682 11684 status = EINVAL;
11683 11685 }
11684 11686 } else {
11685 11687 status = EFAULT;
11686 11688 }
11687 11689
11688 11690 return (status);
11689 11691 }
11690 11692
11691 11693 /*
11692 11694 * This routine handles the "event query" ioctl.
11693 11695 */
11694 11696 static int
11695 11697 mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, int mode,
11696 11698 int *rval)
11697 11699 {
11698 11700 int status;
11699 11701 mptsas_event_query_t driverdata;
11700 11702 uint8_t i;
11701 11703
11702 11704 driverdata.Entries = MPTSAS_EVENT_QUEUE_SIZE;
11703 11705
11704 11706 mutex_enter(&mpt->m_mutex);
11705 11707 for (i = 0; i < 4; i++) {
11706 11708 driverdata.Types[i] = mpt->m_event_mask[i];
11707 11709 }
11708 11710 mutex_exit(&mpt->m_mutex);
11709 11711
11710 11712 if (ddi_copyout(&driverdata, data, sizeof (driverdata), mode) != 0) {
11711 11713 status = EFAULT;
11712 11714 } else {
11713 11715 *rval = MPTIOCTL_STATUS_GOOD;
11714 11716 status = 0;
11715 11717 }
11716 11718
11717 11719 return (status);
11718 11720 }
11719 11721
11720 11722 /*
11721 11723 * This routine handles the "event enable" ioctl.
11722 11724 */
11723 11725 static int
11724 11726 mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, int mode,
11725 11727 int *rval)
11726 11728 {
11727 11729 int status;
11728 11730 mptsas_event_enable_t driverdata;
11729 11731 uint8_t i;
11730 11732
11731 11733 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) {
11732 11734 mutex_enter(&mpt->m_mutex);
11733 11735 for (i = 0; i < 4; i++) {
11734 11736 mpt->m_event_mask[i] = driverdata.Types[i];
11735 11737 }
11736 11738 mutex_exit(&mpt->m_mutex);
11737 11739
11738 11740 *rval = MPTIOCTL_STATUS_GOOD;
11739 11741 status = 0;
11740 11742 } else {
11741 11743 status = EFAULT;
11742 11744 }
11743 11745 return (status);
11744 11746 }
11745 11747
11746 11748 /*
11747 11749 * This routine handles the "event report" ioctl.
11748 11750 */
11749 11751 static int
11750 11752 mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, int mode,
11751 11753 int *rval)
11752 11754 {
11753 11755 int status;
11754 11756 mptsas_event_report_t driverdata;
11755 11757
11756 11758 mutex_enter(&mpt->m_mutex);
11757 11759
11758 11760 if (ddi_copyin(&data->Size, &driverdata.Size, sizeof (driverdata.Size),
11759 11761 mode) == 0) {
11760 11762 if (driverdata.Size >= sizeof (mpt->m_events)) {
11761 11763 if (ddi_copyout(mpt->m_events, data->Events,
11762 11764 sizeof (mpt->m_events), mode) != 0) {
11763 11765 status = EFAULT;
11764 11766 } else {
11765 11767 if (driverdata.Size > sizeof (mpt->m_events)) {
11766 11768 driverdata.Size =
11767 11769 sizeof (mpt->m_events);
11768 11770 if (ddi_copyout(&driverdata.Size,
11769 11771 &data->Size,
11770 11772 sizeof (driverdata.Size),
11771 11773 mode) != 0) {
11772 11774 status = EFAULT;
11773 11775 } else {
11774 11776 *rval = MPTIOCTL_STATUS_GOOD;
11775 11777 status = 0;
11776 11778 }
11777 11779 } else {
11778 11780 *rval = MPTIOCTL_STATUS_GOOD;
11779 11781 status = 0;
11780 11782 }
11781 11783 }
11782 11784 } else {
11783 11785 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT;
11784 11786 status = 0;
11785 11787 }
11786 11788 } else {
11787 11789 status = EFAULT;
11788 11790 }
11789 11791
11790 11792 mutex_exit(&mpt->m_mutex);
11791 11793 return (status);
11792 11794 }
11793 11795
11794 11796 static void
11795 11797 mptsas_lookup_pci_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data)
11796 11798 {
11797 11799 int *reg_data;
11798 11800 uint_t reglen;
11799 11801
11800 11802 /*
11801 11803 * Lookup the 'reg' property and extract the other data
11802 11804 */
11803 11805 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip,
11804 11806 DDI_PROP_DONTPASS, "reg", ®_data, ®len) ==
11805 11807 DDI_PROP_SUCCESS) {
11806 11808 /*
11807 11809 * Extract the PCI data from the 'reg' property first DWORD.
11808 11810 * The entry looks like the following:
11809 11811 * First DWORD:
11810 11812 * Bits 0 - 7 8-bit Register number
11811 11813 * Bits 8 - 10 3-bit Function number
11812 11814 * Bits 11 - 15 5-bit Device number
11813 11815 * Bits 16 - 23 8-bit Bus number
11814 11816 * Bits 24 - 25 2-bit Address Space type identifier
11815 11817 *
11816 11818 */
11817 11819 adapter_data->PciInformation.u.bits.BusNumber =
11818 11820 (reg_data[0] & 0x00FF0000) >> 16;
11819 11821 adapter_data->PciInformation.u.bits.DeviceNumber =
11820 11822 (reg_data[0] & 0x0000F800) >> 11;
11821 11823 adapter_data->PciInformation.u.bits.FunctionNumber =
11822 11824 (reg_data[0] & 0x00000700) >> 8;
11823 11825 ddi_prop_free((void *)reg_data);
11824 11826 } else {
11825 11827 /*
11826 11828 * If we can't determine the PCI data then we fill in FF's for
11827 11829 * the data to indicate this.
11828 11830 */
11829 11831 adapter_data->PCIDeviceHwId = 0xFFFFFFFF;
11830 11832 adapter_data->MpiPortNumber = 0xFFFFFFFF;
11831 11833 adapter_data->PciInformation.u.AsDWORD = 0xFFFFFFFF;
11832 11834 }
11833 11835
11834 11836 /*
11835 11837 * Saved in the mpt->m_fwversion
11836 11838 */
11837 11839 adapter_data->MpiFirmwareVersion = mpt->m_fwversion;
11838 11840 }
11839 11841
11840 11842 static void
11841 11843 mptsas_read_adapter_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data)
11842 11844 {
11843 11845 char *driver_verstr = MPTSAS_MOD_STRING;
11844 11846
11845 11847 mptsas_lookup_pci_data(mpt, adapter_data);
11846 11848 adapter_data->AdapterType = MPTIOCTL_ADAPTER_TYPE_SAS2;
11847 11849 adapter_data->PCIDeviceHwId = (uint32_t)mpt->m_devid;
11848 11850 adapter_data->PCIDeviceHwRev = (uint32_t)mpt->m_revid;
11849 11851 adapter_data->SubSystemId = (uint32_t)mpt->m_ssid;
11850 11852 adapter_data->SubsystemVendorId = (uint32_t)mpt->m_svid;
11851 11853 (void) strcpy((char *)&adapter_data->DriverVersion[0], driver_verstr);
11852 11854 adapter_data->BiosVersion = 0;
11853 11855 (void) mptsas_get_bios_page3(mpt, &adapter_data->BiosVersion);
11854 11856 }
11855 11857
11856 11858 static void
11857 11859 mptsas_read_pci_info(mptsas_t *mpt, mptsas_pci_info_t *pci_info)
11858 11860 {
11859 11861 int *reg_data, i;
11860 11862 uint_t reglen;
11861 11863
11862 11864 /*
11863 11865 * Lookup the 'reg' property and extract the other data
11864 11866 */
11865 11867 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip,
11866 11868 DDI_PROP_DONTPASS, "reg", ®_data, ®len) ==
11867 11869 DDI_PROP_SUCCESS) {
11868 11870 /*
11869 11871 * Extract the PCI data from the 'reg' property first DWORD.
11870 11872 * The entry looks like the following:
11871 11873 * First DWORD:
11872 11874 * Bits 8 - 10 3-bit Function number
11873 11875 * Bits 11 - 15 5-bit Device number
11874 11876 * Bits 16 - 23 8-bit Bus number
11875 11877 */
11876 11878 pci_info->BusNumber = (reg_data[0] & 0x00FF0000) >> 16;
11877 11879 pci_info->DeviceNumber = (reg_data[0] & 0x0000F800) >> 11;
11878 11880 pci_info->FunctionNumber = (reg_data[0] & 0x00000700) >> 8;
11879 11881 ddi_prop_free((void *)reg_data);
11880 11882 } else {
11881 11883 /*
11882 11884 * If we can't determine the PCI info then we fill in FF's for
11883 11885 * the data to indicate this.
11884 11886 */
11885 11887 pci_info->BusNumber = 0xFFFFFFFF;
11886 11888 pci_info->DeviceNumber = 0xFF;
11887 11889 pci_info->FunctionNumber = 0xFF;
11888 11890 }
11889 11891
11890 11892 /*
11891 11893 * Now get the interrupt vector and the pci header. The vector can
11892 11894 * only be 0 right now. The header is the first 256 bytes of config
11893 11895 * space.
11894 11896 */
11895 11897 pci_info->InterruptVector = 0;
11896 11898 for (i = 0; i < sizeof (pci_info->PciHeader); i++) {
11897 11899 pci_info->PciHeader[i] = pci_config_get8(mpt->m_config_handle,
11898 11900 i);
11899 11901 }
11900 11902 }
11901 11903
11902 11904 static int
11903 11905 mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, int mode)
11904 11906 {
11905 11907 int status = 0;
11906 11908 mptsas_reg_access_t driverdata;
11907 11909
11908 11910 mutex_enter(&mpt->m_mutex);
11909 11911 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) {
11910 11912 switch (driverdata.Command) {
11911 11913 /*
11912 11914 * IO access is not supported.
11913 11915 */
11914 11916 case REG_IO_READ:
11915 11917 case REG_IO_WRITE:
11916 11918 mptsas_log(mpt, CE_WARN, "IO access is not "
11917 11919 "supported. Use memory access.");
11918 11920 status = EINVAL;
11919 11921 break;
11920 11922
11921 11923 case REG_MEM_READ:
11922 11924 driverdata.RegData = ddi_get32(mpt->m_datap,
11923 11925 (uint32_t *)(void *)mpt->m_reg +
11924 11926 driverdata.RegOffset);
11925 11927 if (ddi_copyout(&driverdata.RegData,
11926 11928 &data->RegData,
11927 11929 sizeof (driverdata.RegData), mode) != 0) {
11928 11930 mptsas_log(mpt, CE_WARN, "Register "
11929 11931 "Read Failed");
11930 11932 status = EFAULT;
11931 11933 }
11932 11934 break;
11933 11935
11934 11936 case REG_MEM_WRITE:
11935 11937 ddi_put32(mpt->m_datap,
11936 11938 (uint32_t *)(void *)mpt->m_reg +
11937 11939 driverdata.RegOffset,
11938 11940 driverdata.RegData);
11939 11941 break;
11940 11942
11941 11943 default:
11942 11944 status = EINVAL;
11943 11945 break;
↓ open down ↓ |
11862 lines elided |
↑ open up ↑ |
11944 11946 }
11945 11947 } else {
11946 11948 status = EFAULT;
11947 11949 }
11948 11950
11949 11951 mutex_exit(&mpt->m_mutex);
11950 11952 return (status);
11951 11953 }
11952 11954
11953 11955 static int
11956 +get_disk_info(mptsas_t *mpt, intptr_t data, int mode)
11957 +{
11958 + int i = 0;
11959 + int count = 0;
11960 + int ret = 0;
11961 + mptsas_target_t *ptgt;
11962 + mptsas_disk_info_t *di;
11963 + STRUCT_DECL(mptsas_get_disk_info, gdi);
11964 +
11965 + STRUCT_INIT(gdi, get_udatamodel());
11966 +
11967 + if (ddi_copyin((void *)data, STRUCT_BUF(gdi), STRUCT_SIZE(gdi),
11968 + mode) != 0) {
11969 + return (EFAULT);
11970 + }
11971 +
11972 + /* Find out how many targets there are. */
11973 + mutex_enter(&mpt->m_mutex);
11974 + ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
11975 + MPTSAS_HASH_FIRST);
11976 + while (ptgt != NULL) {
11977 + count++;
11978 + ptgt = (mptsas_target_t *)mptsas_hash_traverse(
11979 + &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
11980 + }
11981 + mutex_exit(&mpt->m_mutex);
11982 +
11983 + /*
11984 + * If we haven't been asked to copy out information on each target,
11985 + * then just return the count.
11986 + */
11987 + STRUCT_FSET(gdi, DiskCount, count);
11988 + if (STRUCT_FGETP(gdi, PtrDiskInfoArray) == NULL)
11989 + goto copy_out;
11990 +
11991 + /*
11992 + * If we haven't been given a large enough buffer to copy out into,
11993 + * let the caller know.
11994 + */
11995 + if (STRUCT_FGET(gdi, DiskInfoArraySize) <
11996 + count * sizeof (mptsas_disk_info_t)) {
11997 + ret = ENOSPC;
11998 + goto copy_out;
11999 + }
12000 +
12001 + di = kmem_zalloc(count * sizeof (mptsas_disk_info_t), KM_SLEEP);
12002 +
12003 + mutex_enter(&mpt->m_mutex);
12004 + ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
12005 + MPTSAS_HASH_FIRST);
12006 + while (ptgt != NULL) {
12007 + if (i >= count) {
12008 + /*
12009 + * The number of targets changed while we weren't
12010 + * looking, so give up.
12011 + */
12012 + mutex_exit(&mpt->m_mutex);
12013 + kmem_free(di, count * sizeof (mptsas_disk_info_t));
12014 + return (EAGAIN);
12015 + }
12016 + di[i].Instance = mpt->m_instance;
12017 + di[i].Enclosure = ptgt->m_enclosure;
12018 + di[i].Slot = ptgt->m_slot_num;
12019 + di[i].SasAddress = ptgt->m_sas_wwn;
12020 +
12021 + ptgt = (mptsas_target_t *)mptsas_hash_traverse(
12022 + &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
12023 + i++;
12024 + }
12025 + mutex_exit(&mpt->m_mutex);
12026 + STRUCT_FSET(gdi, DiskCount, i);
12027 +
12028 + /* Copy out the disk information to the caller. */
12029 + if (ddi_copyout((void *)di, STRUCT_FGETP(gdi, PtrDiskInfoArray),
12030 + i * sizeof (mptsas_disk_info_t), mode) != 0) {
12031 + ret = EFAULT;
12032 + }
12033 +
12034 + kmem_free(di, count * sizeof (mptsas_disk_info_t));
12035 +
12036 +copy_out:
12037 + if (ddi_copyout(STRUCT_BUF(gdi), (void *)data, STRUCT_SIZE(gdi),
12038 + mode) != 0) {
12039 + ret = EFAULT;
12040 + }
12041 +
12042 + return (ret);
12043 +}
12044 +
12045 +static int
11954 12046 mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, cred_t *credp,
11955 12047 int *rval)
11956 12048 {
11957 12049 int status = 0;
11958 12050 mptsas_t *mpt;
11959 12051 mptsas_update_flash_t flashdata;
11960 12052 mptsas_pass_thru_t passthru_data;
11961 12053 mptsas_adapter_data_t adapter_data;
11962 12054 mptsas_pci_info_t pci_info;
11963 12055 int copylen;
11964 12056
11965 12057 int iport_flag = 0;
11966 12058 dev_info_t *dip = NULL;
11967 12059 mptsas_phymask_t phymask = 0;
11968 12060 struct devctl_iocdata *dcp = NULL;
11969 12061 uint32_t slotstatus = 0;
11970 12062 char *addr = NULL;
11971 12063 mptsas_target_t *ptgt = NULL;
11972 12064
11973 12065 *rval = MPTIOCTL_STATUS_GOOD;
11974 12066 if (secpolicy_sys_config(credp, B_FALSE) != 0) {
11975 12067 return (EPERM);
11976 12068 }
11977 12069
11978 12070 mpt = ddi_get_soft_state(mptsas_state, MINOR2INST(getminor(dev)));
11979 12071 if (mpt == NULL) {
11980 12072 /*
11981 12073 * Called from iport node, get the states
11982 12074 */
11983 12075 iport_flag = 1;
11984 12076 dip = mptsas_get_dip_from_dev(dev, &phymask);
11985 12077 if (dip == NULL) {
11986 12078 return (ENXIO);
11987 12079 }
11988 12080 mpt = DIP2MPT(dip);
11989 12081 }
11990 12082 /* Make sure power level is D0 before accessing registers */
11991 12083 mutex_enter(&mpt->m_mutex);
11992 12084 if (mpt->m_options & MPTSAS_OPT_PM) {
11993 12085 (void) pm_busy_component(mpt->m_dip, 0);
11994 12086 if (mpt->m_power_level != PM_LEVEL_D0) {
11995 12087 mutex_exit(&mpt->m_mutex);
11996 12088 if (pm_raise_power(mpt->m_dip, 0, PM_LEVEL_D0) !=
11997 12089 DDI_SUCCESS) {
11998 12090 mptsas_log(mpt, CE_WARN,
11999 12091 "mptsas%d: mptsas_ioctl: Raise power "
12000 12092 "request failed.", mpt->m_instance);
12001 12093 (void) pm_idle_component(mpt->m_dip, 0);
12002 12094 return (ENXIO);
12003 12095 }
12004 12096 } else {
12005 12097 mutex_exit(&mpt->m_mutex);
12006 12098 }
12007 12099 } else {
12008 12100 mutex_exit(&mpt->m_mutex);
12009 12101 }
12010 12102
12011 12103 if (iport_flag) {
12012 12104 status = scsi_hba_ioctl(dev, cmd, data, mode, credp, rval);
12013 12105 if (status != 0) {
12014 12106 goto out;
12015 12107 }
12016 12108 /*
12017 12109 * The following code control the OK2RM LED, it doesn't affect
12018 12110 * the ioctl return status.
12019 12111 */
12020 12112 if ((cmd == DEVCTL_DEVICE_ONLINE) ||
12021 12113 (cmd == DEVCTL_DEVICE_OFFLINE)) {
12022 12114 if (ndi_dc_allochdl((void *)data, &dcp) !=
12023 12115 NDI_SUCCESS) {
12024 12116 goto out;
12025 12117 }
12026 12118 addr = ndi_dc_getaddr(dcp);
12027 12119 ptgt = mptsas_addr_to_ptgt(mpt, addr, phymask);
12028 12120 if (ptgt == NULL) {
12029 12121 NDBG14(("mptsas_ioctl led control: tgt %s not "
12030 12122 "found", addr));
12031 12123 ndi_dc_freehdl(dcp);
12032 12124 goto out;
12033 12125 }
12034 12126 mutex_enter(&mpt->m_mutex);
12035 12127 if (cmd == DEVCTL_DEVICE_ONLINE) {
12036 12128 ptgt->m_tgt_unconfigured = 0;
12037 12129 } else if (cmd == DEVCTL_DEVICE_OFFLINE) {
12038 12130 ptgt->m_tgt_unconfigured = 1;
12039 12131 }
12040 12132 slotstatus = 0;
12041 12133 #ifdef MPTSAS_GET_LED
12042 12134 /*
12043 12135 * The get led status can't get a valid/reasonable
12044 12136 * state, so ignore the get led status, and write the
12045 12137 * required value directly
12046 12138 */
12047 12139 if (mptsas_get_led_status(mpt, ptgt, &slotstatus) !=
12048 12140 DDI_SUCCESS) {
12049 12141 NDBG14(("mptsas_ioctl: get LED for tgt %s "
12050 12142 "failed %x", addr, slotstatus));
12051 12143 slotstatus = 0;
12052 12144 }
12053 12145 NDBG14(("mptsas_ioctl: LED status %x for %s",
12054 12146 slotstatus, addr));
12055 12147 #endif
12056 12148 if (cmd == DEVCTL_DEVICE_OFFLINE) {
12057 12149 slotstatus |=
12058 12150 MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE;
12059 12151 } else {
12060 12152 slotstatus &=
12061 12153 ~MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE;
12062 12154 }
12063 12155 if (mptsas_set_led_status(mpt, ptgt, slotstatus) !=
↓ open down ↓ |
100 lines elided |
↑ open up ↑ |
12064 12156 DDI_SUCCESS) {
12065 12157 NDBG14(("mptsas_ioctl: set LED for tgt %s "
12066 12158 "failed %x", addr, slotstatus));
12067 12159 }
12068 12160 mutex_exit(&mpt->m_mutex);
12069 12161 ndi_dc_freehdl(dcp);
12070 12162 }
12071 12163 goto out;
12072 12164 }
12073 12165 switch (cmd) {
12166 + case MPTIOCTL_GET_DISK_INFO:
12167 + status = get_disk_info(mpt, data, mode);
12168 + break;
12074 12169 case MPTIOCTL_UPDATE_FLASH:
12075 12170 if (ddi_copyin((void *)data, &flashdata,
12076 12171 sizeof (struct mptsas_update_flash), mode)) {
12077 12172 status = EFAULT;
12078 12173 break;
12079 12174 }
12080 12175
12081 12176 mutex_enter(&mpt->m_mutex);
12082 12177 if (mptsas_update_flash(mpt,
12083 12178 (caddr_t)(long)flashdata.PtrBuffer,
12084 12179 flashdata.ImageSize, flashdata.ImageType, mode)) {
12085 12180 status = EFAULT;
12086 12181 }
12087 12182
12088 12183 /*
12089 12184 * Reset the chip to start using the new
12090 12185 * firmware. Reset if failed also.
12091 12186 */
12092 12187 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
12093 12188 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) {
12094 12189 status = EFAULT;
12095 12190 }
12096 12191 mutex_exit(&mpt->m_mutex);
12097 12192 break;
12098 12193 case MPTIOCTL_PASS_THRU:
12099 12194 /*
12100 12195 * The user has requested to pass through a command to
12101 12196 * be executed by the MPT firmware. Call our routine
12102 12197 * which does this. Only allow one passthru IOCTL at
12103 12198 * one time. Other threads will block on
12104 12199 * m_passthru_mutex, which is of adaptive variant.
12105 12200 */
12106 12201 if (ddi_copyin((void *)data, &passthru_data,
12107 12202 sizeof (mptsas_pass_thru_t), mode)) {
12108 12203 status = EFAULT;
12109 12204 break;
12110 12205 }
12111 12206 mutex_enter(&mpt->m_passthru_mutex);
12112 12207 mutex_enter(&mpt->m_mutex);
12113 12208 status = mptsas_pass_thru(mpt, &passthru_data, mode);
12114 12209 mutex_exit(&mpt->m_mutex);
12115 12210 mutex_exit(&mpt->m_passthru_mutex);
12116 12211
12117 12212 break;
12118 12213 case MPTIOCTL_GET_ADAPTER_DATA:
12119 12214 /*
12120 12215 * The user has requested to read adapter data. Call
12121 12216 * our routine which does this.
12122 12217 */
12123 12218 bzero(&adapter_data, sizeof (mptsas_adapter_data_t));
12124 12219 if (ddi_copyin((void *)data, (void *)&adapter_data,
12125 12220 sizeof (mptsas_adapter_data_t), mode)) {
12126 12221 status = EFAULT;
12127 12222 break;
12128 12223 }
12129 12224 if (adapter_data.StructureLength >=
12130 12225 sizeof (mptsas_adapter_data_t)) {
12131 12226 adapter_data.StructureLength = (uint32_t)
12132 12227 sizeof (mptsas_adapter_data_t);
12133 12228 copylen = sizeof (mptsas_adapter_data_t);
12134 12229 mutex_enter(&mpt->m_mutex);
12135 12230 mptsas_read_adapter_data(mpt, &adapter_data);
12136 12231 mutex_exit(&mpt->m_mutex);
12137 12232 } else {
12138 12233 adapter_data.StructureLength = (uint32_t)
12139 12234 sizeof (mptsas_adapter_data_t);
12140 12235 copylen = sizeof (adapter_data.StructureLength);
12141 12236 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT;
12142 12237 }
12143 12238 if (ddi_copyout((void *)(&adapter_data), (void *)data,
12144 12239 copylen, mode) != 0) {
12145 12240 status = EFAULT;
12146 12241 }
12147 12242 break;
12148 12243 case MPTIOCTL_GET_PCI_INFO:
12149 12244 /*
12150 12245 * The user has requested to read pci info. Call
12151 12246 * our routine which does this.
12152 12247 */
12153 12248 bzero(&pci_info, sizeof (mptsas_pci_info_t));
12154 12249 mutex_enter(&mpt->m_mutex);
12155 12250 mptsas_read_pci_info(mpt, &pci_info);
12156 12251 mutex_exit(&mpt->m_mutex);
12157 12252 if (ddi_copyout((void *)(&pci_info), (void *)data,
12158 12253 sizeof (mptsas_pci_info_t), mode) != 0) {
12159 12254 status = EFAULT;
12160 12255 }
12161 12256 break;
12162 12257 case MPTIOCTL_RESET_ADAPTER:
12163 12258 mutex_enter(&mpt->m_mutex);
12164 12259 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
12165 12260 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
12166 12261 mptsas_log(mpt, CE_WARN, "reset adapter IOCTL "
12167 12262 "failed");
12168 12263 status = EFAULT;
12169 12264 }
12170 12265 mutex_exit(&mpt->m_mutex);
12171 12266 break;
12172 12267 case MPTIOCTL_DIAG_ACTION:
12173 12268 /*
12174 12269 * The user has done a diag buffer action. Call our
12175 12270 * routine which does this. Only allow one diag action
12176 12271 * at one time.
12177 12272 */
12178 12273 mutex_enter(&mpt->m_mutex);
12179 12274 if (mpt->m_diag_action_in_progress) {
12180 12275 mutex_exit(&mpt->m_mutex);
12181 12276 return (EBUSY);
12182 12277 }
12183 12278 mpt->m_diag_action_in_progress = 1;
12184 12279 status = mptsas_diag_action(mpt,
12185 12280 (mptsas_diag_action_t *)data, mode);
12186 12281 mpt->m_diag_action_in_progress = 0;
12187 12282 mutex_exit(&mpt->m_mutex);
12188 12283 break;
12189 12284 case MPTIOCTL_EVENT_QUERY:
12190 12285 /*
12191 12286 * The user has done an event query. Call our routine
12192 12287 * which does this.
12193 12288 */
12194 12289 status = mptsas_event_query(mpt,
12195 12290 (mptsas_event_query_t *)data, mode, rval);
12196 12291 break;
12197 12292 case MPTIOCTL_EVENT_ENABLE:
12198 12293 /*
12199 12294 * The user has done an event enable. Call our routine
12200 12295 * which does this.
12201 12296 */
12202 12297 status = mptsas_event_enable(mpt,
12203 12298 (mptsas_event_enable_t *)data, mode, rval);
12204 12299 break;
12205 12300 case MPTIOCTL_EVENT_REPORT:
12206 12301 /*
12207 12302 * The user has done an event report. Call our routine
12208 12303 * which does this.
12209 12304 */
12210 12305 status = mptsas_event_report(mpt,
12211 12306 (mptsas_event_report_t *)data, mode, rval);
12212 12307 break;
12213 12308 case MPTIOCTL_REG_ACCESS:
12214 12309 /*
12215 12310 * The user has requested register access. Call our
12216 12311 * routine which does this.
12217 12312 */
12218 12313 status = mptsas_reg_access(mpt,
12219 12314 (mptsas_reg_access_t *)data, mode);
12220 12315 break;
12221 12316 default:
12222 12317 status = scsi_hba_ioctl(dev, cmd, data, mode, credp,
12223 12318 rval);
12224 12319 break;
12225 12320 }
12226 12321
12227 12322 out:
12228 12323 if (mpt->m_options & MPTSAS_OPT_PM)
12229 12324 (void) pm_idle_component(mpt->m_dip, 0);
12230 12325 return (status);
12231 12326 }
12232 12327
12233 12328 int
12234 12329 mptsas_restart_ioc(mptsas_t *mpt)
12235 12330 {
12236 12331 int rval = DDI_SUCCESS;
12237 12332 mptsas_target_t *ptgt = NULL;
12238 12333
12239 12334 ASSERT(mutex_owned(&mpt->m_mutex));
12240 12335
12241 12336 /*
12242 12337 * Set a flag telling I/O path that we're processing a reset. This is
12243 12338 * needed because after the reset is complete, the hash table still
12244 12339 * needs to be rebuilt. If I/Os are started before the hash table is
12245 12340 * rebuilt, I/O errors will occur. This flag allows I/Os to be marked
12246 12341 * so that they can be retried.
12247 12342 */
12248 12343 mpt->m_in_reset = TRUE;
12249 12344
12250 12345 /*
12251 12346 * Set all throttles to HOLD
12252 12347 */
12253 12348 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
12254 12349 MPTSAS_HASH_FIRST);
12255 12350 while (ptgt != NULL) {
12256 12351 mutex_enter(&ptgt->m_tgt_intr_mutex);
12257 12352 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
12258 12353 mutex_exit(&ptgt->m_tgt_intr_mutex);
12259 12354
12260 12355 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
12261 12356 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
12262 12357 }
12263 12358
12264 12359 /*
12265 12360 * Disable interrupts
12266 12361 */
12267 12362 MPTSAS_DISABLE_INTR(mpt);
12268 12363
12269 12364 /*
12270 12365 * Abort all commands: outstanding commands, commands in waitq
12271 12366 */
12272 12367 mptsas_flush_hba(mpt);
12273 12368
12274 12369 /*
12275 12370 * Reinitialize the chip.
12276 12371 */
12277 12372 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) {
12278 12373 rval = DDI_FAILURE;
12279 12374 }
12280 12375
12281 12376 /*
12282 12377 * Enable interrupts again
12283 12378 */
12284 12379 MPTSAS_ENABLE_INTR(mpt);
12285 12380
12286 12381 /*
12287 12382 * If mptsas_init_chip was successful, update the driver data.
12288 12383 */
12289 12384 if (rval == DDI_SUCCESS) {
12290 12385 mptsas_update_driver_data(mpt);
12291 12386 }
12292 12387
12293 12388 /*
12294 12389 * Reset the throttles
12295 12390 */
12296 12391 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
12297 12392 MPTSAS_HASH_FIRST);
12298 12393 while (ptgt != NULL) {
12299 12394 mutex_enter(&ptgt->m_tgt_intr_mutex);
12300 12395 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
12301 12396 mutex_exit(&ptgt->m_tgt_intr_mutex);
12302 12397
12303 12398 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
12304 12399 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
12305 12400 }
12306 12401
12307 12402 mptsas_doneq_empty(mpt);
12308 12403 mptsas_restart_hba(mpt);
12309 12404
12310 12405 if (rval != DDI_SUCCESS) {
12311 12406 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE);
12312 12407 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST);
12313 12408 }
12314 12409
12315 12410 /*
12316 12411 * Clear the reset flag so that I/Os can continue.
12317 12412 */
12318 12413 mpt->m_in_reset = FALSE;
12319 12414
12320 12415 return (rval);
12321 12416 }
12322 12417
12323 12418 static int
12324 12419 mptsas_init_chip(mptsas_t *mpt, int first_time)
12325 12420 {
12326 12421 ddi_dma_cookie_t cookie;
12327 12422 uint32_t i;
12328 12423 int rval;
12329 12424
12330 12425 /*
12331 12426 * Check to see if the firmware image is valid
12332 12427 */
12333 12428 if (ddi_get32(mpt->m_datap, &mpt->m_reg->HostDiagnostic) &
12334 12429 MPI2_DIAG_FLASH_BAD_SIG) {
12335 12430 mptsas_log(mpt, CE_WARN, "mptsas bad flash signature!");
12336 12431 goto fail;
12337 12432 }
12338 12433
12339 12434 /*
12340 12435 * Reset the chip
12341 12436 */
12342 12437 rval = mptsas_ioc_reset(mpt, first_time);
12343 12438 if (rval == MPTSAS_RESET_FAIL) {
12344 12439 mptsas_log(mpt, CE_WARN, "hard reset failed!");
12345 12440 goto fail;
12346 12441 }
12347 12442
12348 12443 if ((rval == MPTSAS_SUCCESS_MUR) && (!first_time)) {
12349 12444 goto mur;
12350 12445 }
12351 12446 /*
12352 12447 * Setup configuration space
12353 12448 */
12354 12449 if (mptsas_config_space_init(mpt) == FALSE) {
12355 12450 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init "
12356 12451 "failed!");
12357 12452 goto fail;
12358 12453 }
12359 12454
12360 12455 /*
12361 12456 * IOC facts can change after a diag reset so all buffers that are
12362 12457 * based on these numbers must be de-allocated and re-allocated. Get
12363 12458 * new IOC facts each time chip is initialized.
12364 12459 */
12365 12460 if (mptsas_ioc_get_facts(mpt) == DDI_FAILURE) {
12366 12461 mptsas_log(mpt, CE_WARN, "mptsas_ioc_get_facts failed");
12367 12462 goto fail;
12368 12463 }
12369 12464
12370 12465 if (mptsas_alloc_active_slots(mpt, KM_SLEEP)) {
12371 12466 goto fail;
12372 12467 }
12373 12468 /*
12374 12469 * Allocate request message frames, reply free queue, reply descriptor
12375 12470 * post queue, and reply message frames using latest IOC facts.
12376 12471 */
12377 12472 if (mptsas_alloc_request_frames(mpt) == DDI_FAILURE) {
12378 12473 mptsas_log(mpt, CE_WARN, "mptsas_alloc_request_frames failed");
12379 12474 goto fail;
12380 12475 }
12381 12476 if (mptsas_alloc_free_queue(mpt) == DDI_FAILURE) {
12382 12477 mptsas_log(mpt, CE_WARN, "mptsas_alloc_free_queue failed!");
12383 12478 goto fail;
12384 12479 }
12385 12480 if (mptsas_alloc_post_queue(mpt) == DDI_FAILURE) {
12386 12481 mptsas_log(mpt, CE_WARN, "mptsas_alloc_post_queue failed!");
12387 12482 goto fail;
12388 12483 }
12389 12484 if (mptsas_alloc_reply_frames(mpt) == DDI_FAILURE) {
12390 12485 mptsas_log(mpt, CE_WARN, "mptsas_alloc_reply_frames failed!");
12391 12486 goto fail;
12392 12487 }
12393 12488
12394 12489 mur:
12395 12490 /*
12396 12491 * Re-Initialize ioc to operational state
12397 12492 */
12398 12493 if (mptsas_ioc_init(mpt) == DDI_FAILURE) {
12399 12494 mptsas_log(mpt, CE_WARN, "mptsas_ioc_init failed");
12400 12495 goto fail;
12401 12496 }
12402 12497
12403 12498 mptsas_alloc_reply_args(mpt);
12404 12499
12405 12500 /*
12406 12501 * Initialize reply post index. Reply free index is initialized after
12407 12502 * the next loop.
12408 12503 */
12409 12504 mpt->m_post_index = 0;
12410 12505
12411 12506 /*
12412 12507 * Initialize the Reply Free Queue with the physical addresses of our
12413 12508 * reply frames.
12414 12509 */
12415 12510 cookie.dmac_address = mpt->m_reply_frame_dma_addr;
12416 12511 for (i = 0; i < mpt->m_max_replies; i++) {
12417 12512 ddi_put32(mpt->m_acc_free_queue_hdl,
12418 12513 &((uint32_t *)(void *)mpt->m_free_queue)[i],
12419 12514 cookie.dmac_address);
12420 12515 cookie.dmac_address += mpt->m_reply_frame_size;
12421 12516 }
12422 12517 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
12423 12518 DDI_DMA_SYNC_FORDEV);
12424 12519
12425 12520 /*
12426 12521 * Initialize the reply free index to one past the last frame on the
12427 12522 * queue. This will signify that the queue is empty to start with.
12428 12523 */
12429 12524 mpt->m_free_index = i;
12430 12525 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, i);
12431 12526
12432 12527 /*
12433 12528 * Initialize the reply post queue to 0xFFFFFFFF,0xFFFFFFFF's.
12434 12529 */
12435 12530 for (i = 0; i < mpt->m_post_queue_depth; i++) {
12436 12531 ddi_put64(mpt->m_acc_post_queue_hdl,
12437 12532 &((uint64_t *)(void *)mpt->m_post_queue)[i],
12438 12533 0xFFFFFFFFFFFFFFFF);
12439 12534 }
12440 12535 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
12441 12536 DDI_DMA_SYNC_FORDEV);
12442 12537
12443 12538 /*
12444 12539 * Enable ports
12445 12540 */
12446 12541 if (mptsas_ioc_enable_port(mpt) == DDI_FAILURE) {
12447 12542 mptsas_log(mpt, CE_WARN, "mptsas_ioc_enable_port failed");
12448 12543 goto fail;
12449 12544 }
12450 12545
12451 12546 /*
12452 12547 * enable events
12453 12548 */
12454 12549 if (mptsas_ioc_enable_event_notification(mpt)) {
12455 12550 goto fail;
12456 12551 }
12457 12552
12458 12553 /*
12459 12554 * We need checks in attach and these.
12460 12555 * chip_init is called in mult. places
12461 12556 */
12462 12557
12463 12558 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
12464 12559 DDI_SUCCESS) ||
12465 12560 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) !=
12466 12561 DDI_SUCCESS) ||
12467 12562 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) !=
12468 12563 DDI_SUCCESS) ||
12469 12564 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) !=
12470 12565 DDI_SUCCESS) ||
12471 12566 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) !=
12472 12567 DDI_SUCCESS)) {
12473 12568 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
12474 12569 goto fail;
12475 12570 }
12476 12571
12477 12572 /* Check all acc handles */
12478 12573 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) ||
12479 12574 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
12480 12575 DDI_SUCCESS) ||
12481 12576 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) !=
12482 12577 DDI_SUCCESS) ||
12483 12578 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) !=
12484 12579 DDI_SUCCESS) ||
12485 12580 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) !=
12486 12581 DDI_SUCCESS) ||
12487 12582 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) !=
12488 12583 DDI_SUCCESS) ||
12489 12584 (mptsas_check_acc_handle(mpt->m_config_handle) !=
12490 12585 DDI_SUCCESS)) {
12491 12586 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
12492 12587 goto fail;
12493 12588 }
12494 12589
12495 12590 return (DDI_SUCCESS);
12496 12591
12497 12592 fail:
12498 12593 return (DDI_FAILURE);
12499 12594 }
12500 12595
12501 12596 static int
12502 12597 mptsas_get_pci_cap(mptsas_t *mpt)
12503 12598 {
12504 12599 ushort_t caps_ptr, cap, cap_count;
12505 12600
12506 12601 if (mpt->m_config_handle == NULL)
12507 12602 return (FALSE);
12508 12603 /*
12509 12604 * Check if capabilities list is supported and if so,
12510 12605 * get initial capabilities pointer and clear bits 0,1.
12511 12606 */
12512 12607 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT)
12513 12608 & PCI_STAT_CAP) {
12514 12609 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle,
12515 12610 PCI_CONF_CAP_PTR), 4);
12516 12611 } else {
12517 12612 caps_ptr = PCI_CAP_NEXT_PTR_NULL;
12518 12613 }
12519 12614
12520 12615 /*
12521 12616 * Walk capabilities if supported.
12522 12617 */
12523 12618 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) {
12524 12619
12525 12620 /*
12526 12621 * Check that we haven't exceeded the maximum number of
12527 12622 * capabilities and that the pointer is in a valid range.
12528 12623 */
12529 12624 if (++cap_count > 48) {
12530 12625 mptsas_log(mpt, CE_WARN,
12531 12626 "too many device capabilities.\n");
12532 12627 break;
12533 12628 }
12534 12629 if (caps_ptr < 64) {
12535 12630 mptsas_log(mpt, CE_WARN,
12536 12631 "capabilities pointer 0x%x out of range.\n",
12537 12632 caps_ptr);
12538 12633 break;
12539 12634 }
12540 12635
12541 12636 /*
12542 12637 * Get next capability and check that it is valid.
12543 12638 * For now, we only support power management.
12544 12639 */
12545 12640 cap = pci_config_get8(mpt->m_config_handle, caps_ptr);
12546 12641 switch (cap) {
12547 12642 case PCI_CAP_ID_PM:
12548 12643 mptsas_log(mpt, CE_NOTE,
12549 12644 "?mptsas%d supports power management.\n",
12550 12645 mpt->m_instance);
12551 12646 mpt->m_options |= MPTSAS_OPT_PM;
12552 12647
12553 12648 /* Save PMCSR offset */
12554 12649 mpt->m_pmcsr_offset = caps_ptr + PCI_PMCSR;
12555 12650 break;
12556 12651 /*
12557 12652 * The following capabilities are valid. Any others
12558 12653 * will cause a message to be logged.
12559 12654 */
12560 12655 case PCI_CAP_ID_VPD:
12561 12656 case PCI_CAP_ID_MSI:
12562 12657 case PCI_CAP_ID_PCIX:
12563 12658 case PCI_CAP_ID_PCI_E:
12564 12659 case PCI_CAP_ID_MSI_X:
12565 12660 break;
12566 12661 default:
12567 12662 mptsas_log(mpt, CE_NOTE,
12568 12663 "?mptsas%d unrecognized capability "
12569 12664 "0x%x.\n", mpt->m_instance, cap);
12570 12665 break;
12571 12666 }
12572 12667
12573 12668 /*
12574 12669 * Get next capabilities pointer and clear bits 0,1.
12575 12670 */
12576 12671 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle,
12577 12672 (caps_ptr + PCI_CAP_NEXT_PTR)), 4);
12578 12673 }
12579 12674 return (TRUE);
12580 12675 }
12581 12676
12582 12677 static int
12583 12678 mptsas_init_pm(mptsas_t *mpt)
12584 12679 {
12585 12680 char pmc_name[16];
12586 12681 char *pmc[] = {
12587 12682 NULL,
12588 12683 "0=Off (PCI D3 State)",
12589 12684 "3=On (PCI D0 State)",
12590 12685 NULL
12591 12686 };
12592 12687 uint16_t pmcsr_stat;
12593 12688
12594 12689 if (mptsas_get_pci_cap(mpt) == FALSE) {
12595 12690 return (DDI_FAILURE);
12596 12691 }
12597 12692 /*
12598 12693 * If PCI's capability does not support PM, then don't need
12599 12694 * to registe the pm-components
12600 12695 */
12601 12696 if (!(mpt->m_options & MPTSAS_OPT_PM))
12602 12697 return (DDI_SUCCESS);
12603 12698 /*
12604 12699 * If power management is supported by this chip, create
12605 12700 * pm-components property for the power management framework
12606 12701 */
12607 12702 (void) sprintf(pmc_name, "NAME=mptsas%d", mpt->m_instance);
12608 12703 pmc[0] = pmc_name;
12609 12704 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, mpt->m_dip,
12610 12705 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) {
12611 12706 mutex_enter(&mpt->m_intr_mutex);
12612 12707 mpt->m_options &= ~MPTSAS_OPT_PM;
12613 12708 mutex_exit(&mpt->m_intr_mutex);
12614 12709 mptsas_log(mpt, CE_WARN,
12615 12710 "mptsas%d: pm-component property creation failed.",
12616 12711 mpt->m_instance);
12617 12712 return (DDI_FAILURE);
12618 12713 }
12619 12714
12620 12715 /*
12621 12716 * Power on device.
12622 12717 */
12623 12718 (void) pm_busy_component(mpt->m_dip, 0);
12624 12719 pmcsr_stat = pci_config_get16(mpt->m_config_handle,
12625 12720 mpt->m_pmcsr_offset);
12626 12721 if ((pmcsr_stat & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_D0) {
12627 12722 mptsas_log(mpt, CE_WARN, "mptsas%d: Power up the device",
12628 12723 mpt->m_instance);
12629 12724 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset,
12630 12725 PCI_PMCSR_D0);
12631 12726 }
12632 12727 if (pm_power_has_changed(mpt->m_dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) {
12633 12728 mptsas_log(mpt, CE_WARN, "pm_power_has_changed failed");
12634 12729 return (DDI_FAILURE);
12635 12730 }
12636 12731 mutex_enter(&mpt->m_intr_mutex);
12637 12732 mpt->m_power_level = PM_LEVEL_D0;
12638 12733 mutex_exit(&mpt->m_intr_mutex);
12639 12734 /*
12640 12735 * Set pm idle delay.
12641 12736 */
12642 12737 mpt->m_pm_idle_delay = ddi_prop_get_int(DDI_DEV_T_ANY,
12643 12738 mpt->m_dip, 0, "mptsas-pm-idle-delay", MPTSAS_PM_IDLE_TIMEOUT);
12644 12739
12645 12740 return (DDI_SUCCESS);
12646 12741 }
12647 12742
12648 12743 static int
12649 12744 mptsas_register_intrs(mptsas_t *mpt)
12650 12745 {
12651 12746 dev_info_t *dip;
12652 12747 int intr_types;
12653 12748
12654 12749 dip = mpt->m_dip;
12655 12750
12656 12751 /* Get supported interrupt types */
12657 12752 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) {
12658 12753 mptsas_log(mpt, CE_WARN, "ddi_intr_get_supported_types "
12659 12754 "failed\n");
12660 12755 return (FALSE);
12661 12756 }
12662 12757
12663 12758 NDBG6(("ddi_intr_get_supported_types() returned: 0x%x", intr_types));
12664 12759
12665 12760 /*
12666 12761 * Try MSI, but fall back to FIXED
12667 12762 */
12668 12763 if (mptsas_enable_msi && (intr_types & DDI_INTR_TYPE_MSI)) {
12669 12764 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_MSI) == DDI_SUCCESS) {
12670 12765 NDBG0(("Using MSI interrupt type"));
12671 12766 mpt->m_intr_type = DDI_INTR_TYPE_MSI;
12672 12767 return (TRUE);
12673 12768 }
12674 12769 }
12675 12770 if (intr_types & DDI_INTR_TYPE_FIXED) {
12676 12771 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_FIXED) == DDI_SUCCESS) {
12677 12772 NDBG0(("Using FIXED interrupt type"));
12678 12773 mpt->m_intr_type = DDI_INTR_TYPE_FIXED;
12679 12774 return (TRUE);
12680 12775 } else {
12681 12776 NDBG0(("FIXED interrupt registration failed"));
12682 12777 return (FALSE);
12683 12778 }
12684 12779 }
12685 12780
12686 12781 return (FALSE);
12687 12782 }
12688 12783
12689 12784 static void
12690 12785 mptsas_unregister_intrs(mptsas_t *mpt)
12691 12786 {
12692 12787 mptsas_rem_intrs(mpt);
12693 12788 }
12694 12789
12695 12790 /*
12696 12791 * mptsas_add_intrs:
12697 12792 *
12698 12793 * Register FIXED or MSI interrupts.
12699 12794 */
12700 12795 static int
12701 12796 mptsas_add_intrs(mptsas_t *mpt, int intr_type)
12702 12797 {
12703 12798 dev_info_t *dip = mpt->m_dip;
12704 12799 int avail, actual, count = 0;
12705 12800 int i, flag, ret;
12706 12801
12707 12802 NDBG6(("mptsas_add_intrs:interrupt type 0x%x", intr_type));
12708 12803
12709 12804 /* Get number of interrupts */
12710 12805 ret = ddi_intr_get_nintrs(dip, intr_type, &count);
12711 12806 if ((ret != DDI_SUCCESS) || (count <= 0)) {
12712 12807 mptsas_log(mpt, CE_WARN, "ddi_intr_get_nintrs() failed, "
12713 12808 "ret %d count %d\n", ret, count);
12714 12809
12715 12810 return (DDI_FAILURE);
12716 12811 }
12717 12812
12718 12813 /* Get number of available interrupts */
12719 12814 ret = ddi_intr_get_navail(dip, intr_type, &avail);
12720 12815 if ((ret != DDI_SUCCESS) || (avail == 0)) {
12721 12816 mptsas_log(mpt, CE_WARN, "ddi_intr_get_navail() failed, "
12722 12817 "ret %d avail %d\n", ret, avail);
12723 12818
12724 12819 return (DDI_FAILURE);
12725 12820 }
12726 12821
12727 12822 if (avail < count) {
12728 12823 mptsas_log(mpt, CE_NOTE, "ddi_intr_get_nvail returned %d, "
12729 12824 "navail() returned %d", count, avail);
12730 12825 }
12731 12826
12732 12827 /* Mpt only have one interrupt routine */
12733 12828 if ((intr_type == DDI_INTR_TYPE_MSI) && (count > 1)) {
12734 12829 count = 1;
12735 12830 }
12736 12831
12737 12832 /* Allocate an array of interrupt handles */
12738 12833 mpt->m_intr_size = count * sizeof (ddi_intr_handle_t);
12739 12834 mpt->m_htable = kmem_alloc(mpt->m_intr_size, KM_SLEEP);
12740 12835
12741 12836 flag = DDI_INTR_ALLOC_NORMAL;
12742 12837
12743 12838 /* call ddi_intr_alloc() */
12744 12839 ret = ddi_intr_alloc(dip, mpt->m_htable, intr_type, 0,
12745 12840 count, &actual, flag);
12746 12841
12747 12842 if ((ret != DDI_SUCCESS) || (actual == 0)) {
12748 12843 mptsas_log(mpt, CE_WARN, "ddi_intr_alloc() failed, ret %d\n",
12749 12844 ret);
12750 12845 kmem_free(mpt->m_htable, mpt->m_intr_size);
12751 12846 return (DDI_FAILURE);
12752 12847 }
12753 12848
12754 12849 /* use interrupt count returned or abort? */
12755 12850 if (actual < count) {
12756 12851 mptsas_log(mpt, CE_NOTE, "Requested: %d, Received: %d\n",
12757 12852 count, actual);
12758 12853 }
12759 12854
12760 12855 mpt->m_intr_cnt = actual;
12761 12856
12762 12857 /*
12763 12858 * Get priority for first msi, assume remaining are all the same
12764 12859 */
12765 12860 if ((ret = ddi_intr_get_pri(mpt->m_htable[0],
12766 12861 &mpt->m_intr_pri)) != DDI_SUCCESS) {
12767 12862 mptsas_log(mpt, CE_WARN, "ddi_intr_get_pri() failed %d\n", ret);
12768 12863
12769 12864 /* Free already allocated intr */
12770 12865 for (i = 0; i < actual; i++) {
12771 12866 (void) ddi_intr_free(mpt->m_htable[i]);
12772 12867 }
12773 12868
12774 12869 kmem_free(mpt->m_htable, mpt->m_intr_size);
12775 12870 return (DDI_FAILURE);
12776 12871 }
12777 12872
12778 12873 /* Test for high level mutex */
12779 12874 if (mpt->m_intr_pri >= ddi_intr_get_hilevel_pri()) {
12780 12875 mptsas_log(mpt, CE_WARN, "mptsas_add_intrs: "
12781 12876 "Hi level interrupt not supported\n");
12782 12877
12783 12878 /* Free already allocated intr */
12784 12879 for (i = 0; i < actual; i++) {
12785 12880 (void) ddi_intr_free(mpt->m_htable[i]);
12786 12881 }
12787 12882
12788 12883 kmem_free(mpt->m_htable, mpt->m_intr_size);
12789 12884 return (DDI_FAILURE);
12790 12885 }
12791 12886
12792 12887 /* Call ddi_intr_add_handler() */
12793 12888 for (i = 0; i < actual; i++) {
12794 12889 if ((ret = ddi_intr_add_handler(mpt->m_htable[i], mptsas_intr,
12795 12890 (caddr_t)mpt, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) {
12796 12891 mptsas_log(mpt, CE_WARN, "ddi_intr_add_handler() "
12797 12892 "failed %d\n", ret);
12798 12893
12799 12894 /* Free already allocated intr */
12800 12895 for (i = 0; i < actual; i++) {
12801 12896 (void) ddi_intr_free(mpt->m_htable[i]);
12802 12897 }
12803 12898
12804 12899 kmem_free(mpt->m_htable, mpt->m_intr_size);
12805 12900 return (DDI_FAILURE);
12806 12901 }
12807 12902 }
12808 12903
12809 12904 if ((ret = ddi_intr_get_cap(mpt->m_htable[0], &mpt->m_intr_cap))
12810 12905 != DDI_SUCCESS) {
12811 12906 mptsas_log(mpt, CE_WARN, "ddi_intr_get_cap() failed %d\n", ret);
12812 12907
12813 12908 /* Free already allocated intr */
12814 12909 for (i = 0; i < actual; i++) {
12815 12910 (void) ddi_intr_free(mpt->m_htable[i]);
12816 12911 }
12817 12912
12818 12913 kmem_free(mpt->m_htable, mpt->m_intr_size);
12819 12914 return (DDI_FAILURE);
12820 12915 }
12821 12916
12822 12917 /*
12823 12918 * Enable interrupts
12824 12919 */
12825 12920 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) {
12826 12921 /* Call ddi_intr_block_enable() for MSI interrupts */
12827 12922 (void) ddi_intr_block_enable(mpt->m_htable, mpt->m_intr_cnt);
12828 12923 } else {
12829 12924 /* Call ddi_intr_enable for MSI or FIXED interrupts */
12830 12925 for (i = 0; i < mpt->m_intr_cnt; i++) {
12831 12926 (void) ddi_intr_enable(mpt->m_htable[i]);
12832 12927 }
12833 12928 }
12834 12929 return (DDI_SUCCESS);
12835 12930 }
12836 12931
12837 12932 /*
12838 12933 * mptsas_rem_intrs:
12839 12934 *
12840 12935 * Unregister FIXED or MSI interrupts
12841 12936 */
12842 12937 static void
12843 12938 mptsas_rem_intrs(mptsas_t *mpt)
12844 12939 {
12845 12940 int i;
12846 12941
12847 12942 NDBG6(("mptsas_rem_intrs"));
12848 12943
12849 12944 /* Disable all interrupts */
12850 12945 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) {
12851 12946 /* Call ddi_intr_block_disable() */
12852 12947 (void) ddi_intr_block_disable(mpt->m_htable, mpt->m_intr_cnt);
12853 12948 } else {
12854 12949 for (i = 0; i < mpt->m_intr_cnt; i++) {
12855 12950 (void) ddi_intr_disable(mpt->m_htable[i]);
12856 12951 }
12857 12952 }
12858 12953
12859 12954 /* Call ddi_intr_remove_handler() */
12860 12955 for (i = 0; i < mpt->m_intr_cnt; i++) {
12861 12956 (void) ddi_intr_remove_handler(mpt->m_htable[i]);
12862 12957 (void) ddi_intr_free(mpt->m_htable[i]);
12863 12958 }
12864 12959
12865 12960 kmem_free(mpt->m_htable, mpt->m_intr_size);
12866 12961 }
12867 12962
12868 12963 /*
12869 12964 * The IO fault service error handling callback function
12870 12965 */
12871 12966 /*ARGSUSED*/
12872 12967 static int
12873 12968 mptsas_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
12874 12969 {
12875 12970 /*
12876 12971 * as the driver can always deal with an error in any dma or
12877 12972 * access handle, we can just return the fme_status value.
12878 12973 */
12879 12974 pci_ereport_post(dip, err, NULL);
12880 12975 return (err->fme_status);
12881 12976 }
12882 12977
12883 12978 /*
12884 12979 * mptsas_fm_init - initialize fma capabilities and register with IO
12885 12980 * fault services.
12886 12981 */
12887 12982 static void
12888 12983 mptsas_fm_init(mptsas_t *mpt)
12889 12984 {
12890 12985 /*
12891 12986 * Need to change iblock to priority for new MSI intr
12892 12987 */
12893 12988 ddi_iblock_cookie_t fm_ibc;
12894 12989
12895 12990 /* Only register with IO Fault Services if we have some capability */
12896 12991 if (mpt->m_fm_capabilities) {
12897 12992 /* Adjust access and dma attributes for FMA */
12898 12993 mpt->m_reg_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC;
12899 12994 mpt->m_msg_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
12900 12995 mpt->m_io_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
12901 12996
12902 12997 /*
12903 12998 * Register capabilities with IO Fault Services.
12904 12999 * mpt->m_fm_capabilities will be updated to indicate
12905 13000 * capabilities actually supported (not requested.)
12906 13001 */
12907 13002 ddi_fm_init(mpt->m_dip, &mpt->m_fm_capabilities, &fm_ibc);
12908 13003
12909 13004 /*
12910 13005 * Initialize pci ereport capabilities if ereport
12911 13006 * capable (should always be.)
12912 13007 */
12913 13008 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) ||
12914 13009 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
12915 13010 pci_ereport_setup(mpt->m_dip);
12916 13011 }
12917 13012
12918 13013 /*
12919 13014 * Register error callback if error callback capable.
12920 13015 */
12921 13016 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
12922 13017 ddi_fm_handler_register(mpt->m_dip,
12923 13018 mptsas_fm_error_cb, (void *) mpt);
12924 13019 }
12925 13020 }
12926 13021 }
12927 13022
12928 13023 /*
12929 13024 * mptsas_fm_fini - Releases fma capabilities and un-registers with IO
12930 13025 * fault services.
12931 13026 *
12932 13027 */
12933 13028 static void
12934 13029 mptsas_fm_fini(mptsas_t *mpt)
12935 13030 {
12936 13031 /* Only unregister FMA capabilities if registered */
12937 13032 if (mpt->m_fm_capabilities) {
12938 13033
12939 13034 /*
12940 13035 * Un-register error callback if error callback capable.
12941 13036 */
12942 13037
12943 13038 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
12944 13039 ddi_fm_handler_unregister(mpt->m_dip);
12945 13040 }
12946 13041
12947 13042 /*
12948 13043 * Release any resources allocated by pci_ereport_setup()
12949 13044 */
12950 13045
12951 13046 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) ||
12952 13047 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
12953 13048 pci_ereport_teardown(mpt->m_dip);
12954 13049 }
12955 13050
12956 13051 /* Unregister from IO Fault Services */
12957 13052 ddi_fm_fini(mpt->m_dip);
12958 13053
12959 13054 /* Adjust access and dma attributes for FMA */
12960 13055 mpt->m_reg_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC;
12961 13056 mpt->m_msg_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
12962 13057 mpt->m_io_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
12963 13058
12964 13059 }
12965 13060 }
12966 13061
12967 13062 int
12968 13063 mptsas_check_acc_handle(ddi_acc_handle_t handle)
12969 13064 {
12970 13065 ddi_fm_error_t de;
12971 13066
12972 13067 if (handle == NULL)
12973 13068 return (DDI_FAILURE);
12974 13069 ddi_fm_acc_err_get(handle, &de, DDI_FME_VER0);
12975 13070 return (de.fme_status);
12976 13071 }
12977 13072
12978 13073 int
12979 13074 mptsas_check_dma_handle(ddi_dma_handle_t handle)
12980 13075 {
12981 13076 ddi_fm_error_t de;
12982 13077
12983 13078 if (handle == NULL)
12984 13079 return (DDI_FAILURE);
12985 13080 ddi_fm_dma_err_get(handle, &de, DDI_FME_VER0);
12986 13081 return (de.fme_status);
12987 13082 }
12988 13083
12989 13084 void
12990 13085 mptsas_fm_ereport(mptsas_t *mpt, char *detail)
12991 13086 {
12992 13087 uint64_t ena;
12993 13088 char buf[FM_MAX_CLASS];
12994 13089
12995 13090 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
12996 13091 ena = fm_ena_generate(0, FM_ENA_FMT1);
12997 13092 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities)) {
12998 13093 ddi_fm_ereport_post(mpt->m_dip, buf, ena, DDI_NOSLEEP,
12999 13094 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL);
13000 13095 }
13001 13096 }
13002 13097
13003 13098 static int
13004 13099 mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address,
13005 13100 uint16_t *dev_handle, mptsas_target_t **pptgt)
13006 13101 {
13007 13102 int rval;
13008 13103 uint32_t dev_info;
13009 13104 uint64_t sas_wwn;
13010 13105 mptsas_phymask_t phymask;
13011 13106 uint8_t physport, phynum, config, disk;
13012 13107 mptsas_slots_t *slots = mpt->m_active;
13013 13108 uint64_t devicename;
13014 13109 uint16_t pdev_hdl;
13015 13110 mptsas_target_t *tmp_tgt = NULL;
13016 13111 uint16_t bay_num, enclosure;
13017 13112
13018 13113 ASSERT(*pptgt == NULL);
13019 13114
13020 13115 rval = mptsas_get_sas_device_page0(mpt, page_address, dev_handle,
13021 13116 &sas_wwn, &dev_info, &physport, &phynum, &pdev_hdl,
13022 13117 &bay_num, &enclosure);
13023 13118 if (rval != DDI_SUCCESS) {
13024 13119 rval = DEV_INFO_FAIL_PAGE0;
13025 13120 return (rval);
13026 13121 }
13027 13122
13028 13123 if ((dev_info & (MPI2_SAS_DEVICE_INFO_SSP_TARGET |
13029 13124 MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
13030 13125 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) == NULL) {
13031 13126 rval = DEV_INFO_WRONG_DEVICE_TYPE;
13032 13127 return (rval);
13033 13128 }
13034 13129
13035 13130 /*
13036 13131 * Check if the dev handle is for a Phys Disk. If so, set return value
13037 13132 * and exit. Don't add Phys Disks to hash.
13038 13133 */
13039 13134 for (config = 0; config < slots->m_num_raid_configs; config++) {
13040 13135 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) {
13041 13136 if (*dev_handle == slots->m_raidconfig[config].
13042 13137 m_physdisk_devhdl[disk]) {
13043 13138 rval = DEV_INFO_PHYS_DISK;
13044 13139 return (rval);
13045 13140 }
13046 13141 }
13047 13142 }
13048 13143
13049 13144 /*
13050 13145 * Get SATA Device Name from SAS device page0 for
13051 13146 * sata device, if device name doesn't exist, set m_sas_wwn to
13052 13147 * 0 for direct attached SATA. For the device behind the expander
13053 13148 * we still can use STP address assigned by expander.
13054 13149 */
13055 13150 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
13056 13151 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
13057 13152 mutex_exit(&mpt->m_mutex);
13058 13153 /* alloc a tmp_tgt to send the cmd */
13059 13154 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target),
13060 13155 KM_SLEEP);
13061 13156 tmp_tgt->m_devhdl = *dev_handle;
13062 13157 tmp_tgt->m_deviceinfo = dev_info;
13063 13158 tmp_tgt->m_qfull_retries = QFULL_RETRIES;
13064 13159 tmp_tgt->m_qfull_retry_interval =
13065 13160 drv_usectohz(QFULL_RETRY_INTERVAL * 1000);
13066 13161 tmp_tgt->m_t_throttle = MAX_THROTTLE;
13067 13162 devicename = mptsas_get_sata_guid(mpt, tmp_tgt, 0);
13068 13163 kmem_free(tmp_tgt, sizeof (struct mptsas_target));
13069 13164 mutex_enter(&mpt->m_mutex);
13070 13165 if (devicename != 0 && (((devicename >> 56) & 0xf0) == 0x50)) {
13071 13166 sas_wwn = devicename;
13072 13167 } else if (dev_info & MPI2_SAS_DEVICE_INFO_DIRECT_ATTACH) {
13073 13168 sas_wwn = 0;
13074 13169 }
13075 13170 }
13076 13171
13077 13172 phymask = mptsas_physport_to_phymask(mpt, physport);
13078 13173 *pptgt = mptsas_tgt_alloc(&slots->m_tgttbl, *dev_handle, sas_wwn,
13079 13174 dev_info, phymask, phynum, mpt);
13080 13175 if (*pptgt == NULL) {
13081 13176 mptsas_log(mpt, CE_WARN, "Failed to allocated target"
13082 13177 "structure!");
13083 13178 rval = DEV_INFO_FAIL_ALLOC;
13084 13179 return (rval);
13085 13180 }
13086 13181 (*pptgt)->m_enclosure = enclosure;
13087 13182 (*pptgt)->m_slot_num = bay_num;
13088 13183 return (DEV_INFO_SUCCESS);
13089 13184 }
13090 13185
13091 13186 uint64_t
13092 13187 mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun)
13093 13188 {
13094 13189 uint64_t sata_guid = 0, *pwwn = NULL;
13095 13190 int target = ptgt->m_devhdl;
13096 13191 uchar_t *inq83 = NULL;
13097 13192 int inq83_len = 0xFF;
13098 13193 uchar_t *dblk = NULL;
13099 13194 int inq83_retry = 3;
13100 13195 int rval = DDI_FAILURE;
13101 13196
13102 13197 inq83 = kmem_zalloc(inq83_len, KM_SLEEP);
13103 13198
13104 13199 inq83_retry:
13105 13200 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83,
13106 13201 inq83_len, NULL, 1);
13107 13202 if (rval != DDI_SUCCESS) {
13108 13203 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
13109 13204 "0x83 for target:%x, lun:%x failed!", target, lun);
13110 13205 goto out;
13111 13206 }
13112 13207 /* According to SAT2, the first descriptor is logic unit name */
13113 13208 dblk = &inq83[4];
13114 13209 if ((dblk[1] & 0x30) != 0) {
13115 13210 mptsas_log(mpt, CE_WARN, "!Descriptor is not lun associated.");
13116 13211 goto out;
13117 13212 }
13118 13213 pwwn = (uint64_t *)(void *)(&dblk[4]);
13119 13214 if ((dblk[4] & 0xf0) == 0x50) {
13120 13215 sata_guid = BE_64(*pwwn);
13121 13216 goto out;
13122 13217 } else if (dblk[4] == 'A') {
13123 13218 NDBG20(("SATA drive has no NAA format GUID."));
13124 13219 goto out;
13125 13220 } else {
13126 13221 /* The data is not ready, wait and retry */
13127 13222 inq83_retry--;
13128 13223 if (inq83_retry <= 0) {
13129 13224 goto out;
13130 13225 }
13131 13226 NDBG20(("The GUID is not ready, retry..."));
13132 13227 delay(1 * drv_usectohz(1000000));
13133 13228 goto inq83_retry;
13134 13229 }
13135 13230 out:
13136 13231 kmem_free(inq83, inq83_len);
13137 13232 return (sata_guid);
13138 13233 }
13139 13234
13140 13235 static int
13141 13236 mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, uchar_t page,
13142 13237 unsigned char *buf, int len, int *reallen, uchar_t evpd)
13143 13238 {
13144 13239 uchar_t cdb[CDB_GROUP0];
13145 13240 struct scsi_address ap;
13146 13241 struct buf *data_bp = NULL;
13147 13242 int resid = 0;
13148 13243 int ret = DDI_FAILURE;
13149 13244
13150 13245 ASSERT(len <= 0xffff);
13151 13246
13152 13247 ap.a_target = MPTSAS_INVALID_DEVHDL;
13153 13248 ap.a_lun = (uchar_t)(lun);
13154 13249 ap.a_hba_tran = mpt->m_tran;
13155 13250
13156 13251 data_bp = scsi_alloc_consistent_buf(&ap,
13157 13252 (struct buf *)NULL, len, B_READ, NULL_FUNC, NULL);
13158 13253 if (data_bp == NULL) {
13159 13254 return (ret);
13160 13255 }
13161 13256 bzero(cdb, CDB_GROUP0);
13162 13257 cdb[0] = SCMD_INQUIRY;
13163 13258 cdb[1] = evpd;
13164 13259 cdb[2] = page;
13165 13260 cdb[3] = (len & 0xff00) >> 8;
13166 13261 cdb[4] = (len & 0x00ff);
13167 13262 cdb[5] = 0;
13168 13263
13169 13264 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP0, data_bp,
13170 13265 &resid);
13171 13266 if (ret == DDI_SUCCESS) {
13172 13267 if (reallen) {
13173 13268 *reallen = len - resid;
13174 13269 }
13175 13270 bcopy((caddr_t)data_bp->b_un.b_addr, buf, len);
13176 13271 }
13177 13272 if (data_bp) {
13178 13273 scsi_free_consistent_buf(data_bp);
13179 13274 }
13180 13275 return (ret);
13181 13276 }
13182 13277
13183 13278 static int
13184 13279 mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap,
13185 13280 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp,
13186 13281 int *resid)
13187 13282 {
13188 13283 struct scsi_pkt *pktp = NULL;
13189 13284 scsi_hba_tran_t *tran_clone = NULL;
13190 13285 mptsas_tgt_private_t *tgt_private = NULL;
13191 13286 int ret = DDI_FAILURE;
13192 13287
13193 13288 /*
13194 13289 * scsi_hba_tran_t->tran_tgt_private is used to pass the address
13195 13290 * information to scsi_init_pkt, allocate a scsi_hba_tran structure
13196 13291 * to simulate the cmds from sd
13197 13292 */
13198 13293 tran_clone = kmem_alloc(
13199 13294 sizeof (scsi_hba_tran_t), KM_SLEEP);
13200 13295 if (tran_clone == NULL) {
13201 13296 goto out;
13202 13297 }
13203 13298 bcopy((caddr_t)mpt->m_tran,
13204 13299 (caddr_t)tran_clone, sizeof (scsi_hba_tran_t));
13205 13300 tgt_private = kmem_alloc(
13206 13301 sizeof (mptsas_tgt_private_t), KM_SLEEP);
13207 13302 if (tgt_private == NULL) {
13208 13303 goto out;
13209 13304 }
13210 13305 tgt_private->t_lun = ap->a_lun;
13211 13306 tgt_private->t_private = ptgt;
13212 13307 tran_clone->tran_tgt_private = tgt_private;
13213 13308 ap->a_hba_tran = tran_clone;
13214 13309
13215 13310 pktp = scsi_init_pkt(ap, (struct scsi_pkt *)NULL,
13216 13311 data_bp, cdblen, sizeof (struct scsi_arq_status),
13217 13312 0, PKT_CONSISTENT, NULL, NULL);
13218 13313 if (pktp == NULL) {
13219 13314 goto out;
13220 13315 }
13221 13316 bcopy(cdb, pktp->pkt_cdbp, cdblen);
13222 13317 pktp->pkt_flags = FLAG_NOPARITY;
13223 13318 if (scsi_poll(pktp) < 0) {
13224 13319 goto out;
13225 13320 }
13226 13321 if (((struct scsi_status *)pktp->pkt_scbp)->sts_chk) {
13227 13322 goto out;
13228 13323 }
13229 13324 if (resid != NULL) {
13230 13325 *resid = pktp->pkt_resid;
13231 13326 }
13232 13327
13233 13328 ret = DDI_SUCCESS;
13234 13329 out:
13235 13330 if (pktp) {
13236 13331 scsi_destroy_pkt(pktp);
13237 13332 }
13238 13333 if (tran_clone) {
13239 13334 kmem_free(tran_clone, sizeof (scsi_hba_tran_t));
13240 13335 }
13241 13336 if (tgt_private) {
13242 13337 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t));
13243 13338 }
13244 13339 return (ret);
13245 13340 }
13246 13341 static int
13247 13342 mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, int *lun)
13248 13343 {
13249 13344 char *cp = NULL;
13250 13345 char *ptr = NULL;
13251 13346 size_t s = 0;
13252 13347 char *wwid_str = NULL;
13253 13348 char *lun_str = NULL;
13254 13349 long lunnum;
13255 13350 long phyid = -1;
13256 13351 int rc = DDI_FAILURE;
13257 13352
13258 13353 ptr = name;
13259 13354 ASSERT(ptr[0] == 'w' || ptr[0] == 'p');
13260 13355 ptr++;
13261 13356 if ((cp = strchr(ptr, ',')) == NULL) {
13262 13357 return (DDI_FAILURE);
13263 13358 }
13264 13359
13265 13360 wwid_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13266 13361 s = (uintptr_t)cp - (uintptr_t)ptr;
13267 13362
13268 13363 bcopy(ptr, wwid_str, s);
13269 13364 wwid_str[s] = '\0';
13270 13365
13271 13366 ptr = ++cp;
13272 13367
13273 13368 if ((cp = strchr(ptr, '\0')) == NULL) {
13274 13369 goto out;
13275 13370 }
13276 13371 lun_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13277 13372 s = (uintptr_t)cp - (uintptr_t)ptr;
13278 13373
13279 13374 bcopy(ptr, lun_str, s);
13280 13375 lun_str[s] = '\0';
13281 13376
13282 13377 if (name[0] == 'p') {
13283 13378 rc = ddi_strtol(wwid_str, NULL, 0x10, &phyid);
13284 13379 } else {
13285 13380 rc = scsi_wwnstr_to_wwn(wwid_str, wwid);
13286 13381 }
13287 13382 if (rc != DDI_SUCCESS)
13288 13383 goto out;
13289 13384
13290 13385 if (phyid != -1) {
13291 13386 ASSERT(phyid < MPTSAS_MAX_PHYS);
13292 13387 *phy = (uint8_t)phyid;
13293 13388 }
13294 13389 rc = ddi_strtol(lun_str, NULL, 0x10, &lunnum);
13295 13390 if (rc != 0)
13296 13391 goto out;
13297 13392
13298 13393 *lun = (int)lunnum;
13299 13394 rc = DDI_SUCCESS;
13300 13395 out:
13301 13396 if (wwid_str)
13302 13397 kmem_free(wwid_str, SCSI_MAXNAMELEN);
13303 13398 if (lun_str)
13304 13399 kmem_free(lun_str, SCSI_MAXNAMELEN);
13305 13400
13306 13401 return (rc);
13307 13402 }
13308 13403
13309 13404 /*
13310 13405 * mptsas_parse_smp_name() is to parse sas wwn string
13311 13406 * which format is "wWWN"
13312 13407 */
13313 13408 static int
13314 13409 mptsas_parse_smp_name(char *name, uint64_t *wwn)
13315 13410 {
13316 13411 char *ptr = name;
13317 13412
13318 13413 if (*ptr != 'w') {
13319 13414 return (DDI_FAILURE);
13320 13415 }
13321 13416
13322 13417 ptr++;
13323 13418 if (scsi_wwnstr_to_wwn(ptr, wwn)) {
13324 13419 return (DDI_FAILURE);
13325 13420 }
13326 13421 return (DDI_SUCCESS);
13327 13422 }
13328 13423
13329 13424 static int
13330 13425 mptsas_bus_config(dev_info_t *pdip, uint_t flag,
13331 13426 ddi_bus_config_op_t op, void *arg, dev_info_t **childp)
13332 13427 {
13333 13428 int ret = NDI_FAILURE;
13334 13429 int circ = 0;
13335 13430 int circ1 = 0;
13336 13431 mptsas_t *mpt;
13337 13432 char *ptr = NULL;
13338 13433 char *devnm = NULL;
13339 13434 uint64_t wwid = 0;
13340 13435 uint8_t phy = 0xFF;
13341 13436 int lun = 0;
13342 13437 uint_t mflags = flag;
13343 13438 int bconfig = TRUE;
13344 13439
13345 13440 if (scsi_hba_iport_unit_address(pdip) == 0) {
13346 13441 return (DDI_FAILURE);
13347 13442 }
13348 13443
13349 13444 mpt = DIP2MPT(pdip);
13350 13445 if (!mpt) {
13351 13446 return (DDI_FAILURE);
13352 13447 }
13353 13448 /*
13354 13449 * Hold the nexus across the bus_config
13355 13450 */
13356 13451 ndi_devi_enter(scsi_vhci_dip, &circ);
13357 13452 ndi_devi_enter(pdip, &circ1);
13358 13453 switch (op) {
13359 13454 case BUS_CONFIG_ONE:
13360 13455 /* parse wwid/target name out of name given */
13361 13456 if ((ptr = strchr((char *)arg, '@')) == NULL) {
13362 13457 ret = NDI_FAILURE;
13363 13458 break;
13364 13459 }
13365 13460 ptr++;
13366 13461 if (strncmp((char *)arg, "smp", 3) == 0) {
13367 13462 /*
13368 13463 * This is a SMP target device
13369 13464 */
13370 13465 ret = mptsas_parse_smp_name(ptr, &wwid);
13371 13466 if (ret != DDI_SUCCESS) {
13372 13467 ret = NDI_FAILURE;
13373 13468 break;
13374 13469 }
13375 13470 ret = mptsas_config_smp(pdip, wwid, childp);
13376 13471 } else if ((ptr[0] == 'w') || (ptr[0] == 'p')) {
13377 13472 /*
13378 13473 * OBP could pass down a non-canonical form
13379 13474 * bootpath without LUN part when LUN is 0.
13380 13475 * So driver need adjust the string.
13381 13476 */
13382 13477 if (strchr(ptr, ',') == NULL) {
13383 13478 devnm = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13384 13479 (void) sprintf(devnm, "%s,0", (char *)arg);
13385 13480 ptr = strchr(devnm, '@');
13386 13481 ptr++;
13387 13482 }
13388 13483
13389 13484 /*
13390 13485 * The device path is wWWID format and the device
13391 13486 * is not SMP target device.
13392 13487 */
13393 13488 ret = mptsas_parse_address(ptr, &wwid, &phy, &lun);
13394 13489 if (ret != DDI_SUCCESS) {
13395 13490 ret = NDI_FAILURE;
13396 13491 break;
13397 13492 }
13398 13493 *childp = NULL;
13399 13494 if (ptr[0] == 'w') {
13400 13495 ret = mptsas_config_one_addr(pdip, wwid,
13401 13496 lun, childp);
13402 13497 } else if (ptr[0] == 'p') {
13403 13498 ret = mptsas_config_one_phy(pdip, phy, lun,
13404 13499 childp);
13405 13500 }
13406 13501
13407 13502 /*
13408 13503 * If this is CD/DVD device in OBP path, the
13409 13504 * ndi_busop_bus_config can be skipped as config one
13410 13505 * operation is done above.
13411 13506 */
13412 13507 if ((ret == NDI_SUCCESS) && (*childp != NULL) &&
13413 13508 (strcmp(ddi_node_name(*childp), "cdrom") == 0) &&
13414 13509 (strncmp((char *)arg, "disk", 4) == 0)) {
13415 13510 bconfig = FALSE;
13416 13511 ndi_hold_devi(*childp);
13417 13512 }
13418 13513 } else {
13419 13514 ret = NDI_FAILURE;
13420 13515 break;
13421 13516 }
13422 13517
13423 13518 /*
13424 13519 * DDI group instructed us to use this flag.
13425 13520 */
13426 13521 mflags |= NDI_MDI_FALLBACK;
13427 13522 break;
13428 13523 case BUS_CONFIG_DRIVER:
13429 13524 case BUS_CONFIG_ALL:
13430 13525 mptsas_config_all(pdip);
13431 13526 ret = NDI_SUCCESS;
13432 13527 break;
13433 13528 }
13434 13529
13435 13530 if ((ret == NDI_SUCCESS) && bconfig) {
13436 13531 ret = ndi_busop_bus_config(pdip, mflags, op,
13437 13532 (devnm == NULL) ? arg : devnm, childp, 0);
13438 13533 }
13439 13534
13440 13535 ndi_devi_exit(pdip, circ1);
13441 13536 ndi_devi_exit(scsi_vhci_dip, circ);
13442 13537 if (devnm != NULL)
13443 13538 kmem_free(devnm, SCSI_MAXNAMELEN);
13444 13539 return (ret);
13445 13540 }
13446 13541
13447 13542 static int
13448 13543 mptsas_probe_lun(dev_info_t *pdip, int lun, dev_info_t **dip,
13449 13544 mptsas_target_t *ptgt)
13450 13545 {
13451 13546 int rval = DDI_FAILURE;
13452 13547 struct scsi_inquiry *sd_inq = NULL;
13453 13548 mptsas_t *mpt = DIP2MPT(pdip);
13454 13549
13455 13550 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP);
13456 13551
13457 13552 rval = mptsas_inquiry(mpt, ptgt, lun, 0, (uchar_t *)sd_inq,
13458 13553 SUN_INQSIZE, 0, (uchar_t)0);
13459 13554
13460 13555 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) {
13461 13556 rval = mptsas_create_lun(pdip, sd_inq, dip, ptgt, lun);
13462 13557 } else {
13463 13558 rval = DDI_FAILURE;
13464 13559 }
13465 13560
13466 13561 kmem_free(sd_inq, SUN_INQSIZE);
13467 13562 return (rval);
13468 13563 }
13469 13564
13470 13565 static int
13471 13566 mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun,
13472 13567 dev_info_t **lundip)
13473 13568 {
13474 13569 int rval;
13475 13570 mptsas_t *mpt = DIP2MPT(pdip);
13476 13571 int phymask;
13477 13572 mptsas_target_t *ptgt = NULL;
13478 13573
13479 13574 /*
13480 13575 * Get the physical port associated to the iport
13481 13576 */
13482 13577 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
13483 13578 "phymask", 0);
13484 13579
13485 13580 ptgt = mptsas_wwid_to_ptgt(mpt, phymask, sasaddr);
13486 13581 if (ptgt == NULL) {
13487 13582 /*
13488 13583 * didn't match any device by searching
13489 13584 */
13490 13585 return (DDI_FAILURE);
13491 13586 }
13492 13587 /*
13493 13588 * If the LUN already exists and the status is online,
13494 13589 * we just return the pointer to dev_info_t directly.
13495 13590 * For the mdi_pathinfo node, we'll handle it in
13496 13591 * mptsas_create_virt_lun()
13497 13592 * TODO should be also in mptsas_handle_dr
13498 13593 */
13499 13594
13500 13595 *lundip = mptsas_find_child_addr(pdip, sasaddr, lun);
13501 13596 if (*lundip != NULL) {
13502 13597 /*
13503 13598 * TODO Another senario is, we hotplug the same disk
13504 13599 * on the same slot, the devhdl changed, is this
13505 13600 * possible?
13506 13601 * tgt_private->t_private != ptgt
13507 13602 */
13508 13603 if (sasaddr != ptgt->m_sas_wwn) {
13509 13604 /*
13510 13605 * The device has changed although the devhdl is the
13511 13606 * same (Enclosure mapping mode, change drive on the
13512 13607 * same slot)
13513 13608 */
13514 13609 return (DDI_FAILURE);
13515 13610 }
13516 13611 return (DDI_SUCCESS);
13517 13612 }
13518 13613
13519 13614 if (phymask == 0) {
13520 13615 /*
13521 13616 * Configure IR volume
13522 13617 */
13523 13618 rval = mptsas_config_raid(pdip, ptgt->m_devhdl, lundip);
13524 13619 return (rval);
13525 13620 }
13526 13621 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt);
13527 13622
13528 13623 return (rval);
13529 13624 }
13530 13625
13531 13626 static int
13532 13627 mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun,
13533 13628 dev_info_t **lundip)
13534 13629 {
13535 13630 int rval;
13536 13631 mptsas_t *mpt = DIP2MPT(pdip);
13537 13632 int phymask;
13538 13633 mptsas_target_t *ptgt = NULL;
13539 13634
13540 13635 /*
13541 13636 * Get the physical port associated to the iport
13542 13637 */
13543 13638 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
13544 13639 "phymask", 0);
13545 13640
13546 13641 ptgt = mptsas_phy_to_tgt(mpt, phymask, phy);
13547 13642 if (ptgt == NULL) {
13548 13643 /*
13549 13644 * didn't match any device by searching
13550 13645 */
13551 13646 return (DDI_FAILURE);
13552 13647 }
13553 13648
13554 13649 /*
13555 13650 * If the LUN already exists and the status is online,
13556 13651 * we just return the pointer to dev_info_t directly.
13557 13652 * For the mdi_pathinfo node, we'll handle it in
13558 13653 * mptsas_create_virt_lun().
13559 13654 */
13560 13655
13561 13656 *lundip = mptsas_find_child_phy(pdip, phy);
13562 13657 if (*lundip != NULL) {
13563 13658 return (DDI_SUCCESS);
13564 13659 }
13565 13660
13566 13661 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt);
13567 13662
13568 13663 return (rval);
13569 13664 }
13570 13665
13571 13666 static int
13572 13667 mptsas_retrieve_lundata(int lun_cnt, uint8_t *buf, uint16_t *lun_num,
13573 13668 uint8_t *lun_addr_type)
13574 13669 {
13575 13670 uint32_t lun_idx = 0;
13576 13671
13577 13672 ASSERT(lun_num != NULL);
13578 13673 ASSERT(lun_addr_type != NULL);
13579 13674
13580 13675 lun_idx = (lun_cnt + 1) * MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE;
13581 13676 /* determine report luns addressing type */
13582 13677 switch (buf[lun_idx] & MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) {
13583 13678 /*
13584 13679 * Vendors in the field have been found to be concatenating
13585 13680 * bus/target/lun to equal the complete lun value instead
13586 13681 * of switching to flat space addressing
13587 13682 */
13588 13683 /* 00b - peripheral device addressing method */
13589 13684 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL:
13590 13685 /* FALLTHRU */
13591 13686 /* 10b - logical unit addressing method */
13592 13687 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT:
13593 13688 /* FALLTHRU */
13594 13689 /* 01b - flat space addressing method */
13595 13690 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE:
13596 13691 /* byte0 bit0-5=msb lun byte1 bit0-7=lsb lun */
13597 13692 *lun_addr_type = (buf[lun_idx] &
13598 13693 MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) >> 6;
13599 13694 *lun_num = (buf[lun_idx] & 0x3F) << 8;
13600 13695 *lun_num |= buf[lun_idx + 1];
13601 13696 return (DDI_SUCCESS);
13602 13697 default:
13603 13698 return (DDI_FAILURE);
13604 13699 }
13605 13700 }
13606 13701
13607 13702 static int
13608 13703 mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt)
13609 13704 {
13610 13705 struct buf *repluns_bp = NULL;
13611 13706 struct scsi_address ap;
13612 13707 uchar_t cdb[CDB_GROUP5];
13613 13708 int ret = DDI_FAILURE;
13614 13709 int retry = 0;
13615 13710 int lun_list_len = 0;
13616 13711 uint16_t lun_num = 0;
13617 13712 uint8_t lun_addr_type = 0;
13618 13713 uint32_t lun_cnt = 0;
13619 13714 uint32_t lun_total = 0;
13620 13715 dev_info_t *cdip = NULL;
13621 13716 uint16_t *saved_repluns = NULL;
13622 13717 char *buffer = NULL;
13623 13718 int buf_len = 128;
13624 13719 mptsas_t *mpt = DIP2MPT(pdip);
13625 13720 uint64_t sas_wwn = 0;
13626 13721 uint8_t phy = 0xFF;
13627 13722 uint32_t dev_info = 0;
13628 13723
13629 13724 mutex_enter(&mpt->m_mutex);
13630 13725 sas_wwn = ptgt->m_sas_wwn;
13631 13726 phy = ptgt->m_phynum;
13632 13727 dev_info = ptgt->m_deviceinfo;
13633 13728 mutex_exit(&mpt->m_mutex);
13634 13729
13635 13730 if (sas_wwn == 0) {
13636 13731 /*
13637 13732 * It's a SATA without Device Name
13638 13733 * So don't try multi-LUNs
13639 13734 */
13640 13735 if (mptsas_find_child_phy(pdip, phy)) {
13641 13736 return (DDI_SUCCESS);
13642 13737 } else {
13643 13738 /*
13644 13739 * need configure and create node
13645 13740 */
13646 13741 return (DDI_FAILURE);
13647 13742 }
13648 13743 }
13649 13744
13650 13745 /*
13651 13746 * WWN (SAS address or Device Name exist)
13652 13747 */
13653 13748 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
13654 13749 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
13655 13750 /*
13656 13751 * SATA device with Device Name
13657 13752 * So don't try multi-LUNs
13658 13753 */
13659 13754 if (mptsas_find_child_addr(pdip, sas_wwn, 0)) {
13660 13755 return (DDI_SUCCESS);
13661 13756 } else {
13662 13757 return (DDI_FAILURE);
13663 13758 }
13664 13759 }
13665 13760
13666 13761 do {
13667 13762 ap.a_target = MPTSAS_INVALID_DEVHDL;
13668 13763 ap.a_lun = 0;
13669 13764 ap.a_hba_tran = mpt->m_tran;
13670 13765 repluns_bp = scsi_alloc_consistent_buf(&ap,
13671 13766 (struct buf *)NULL, buf_len, B_READ, NULL_FUNC, NULL);
13672 13767 if (repluns_bp == NULL) {
13673 13768 retry++;
13674 13769 continue;
13675 13770 }
13676 13771 bzero(cdb, CDB_GROUP5);
13677 13772 cdb[0] = SCMD_REPORT_LUNS;
13678 13773 cdb[6] = (buf_len & 0xff000000) >> 24;
13679 13774 cdb[7] = (buf_len & 0x00ff0000) >> 16;
13680 13775 cdb[8] = (buf_len & 0x0000ff00) >> 8;
13681 13776 cdb[9] = (buf_len & 0x000000ff);
13682 13777
13683 13778 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP5,
13684 13779 repluns_bp, NULL);
13685 13780 if (ret != DDI_SUCCESS) {
13686 13781 scsi_free_consistent_buf(repluns_bp);
13687 13782 retry++;
13688 13783 continue;
13689 13784 }
13690 13785 lun_list_len = BE_32(*(int *)((void *)(
13691 13786 repluns_bp->b_un.b_addr)));
13692 13787 if (buf_len >= lun_list_len + 8) {
13693 13788 ret = DDI_SUCCESS;
13694 13789 break;
13695 13790 }
13696 13791 scsi_free_consistent_buf(repluns_bp);
13697 13792 buf_len = lun_list_len + 8;
13698 13793
13699 13794 } while (retry < 3);
13700 13795
13701 13796 if (ret != DDI_SUCCESS)
13702 13797 return (ret);
13703 13798 buffer = (char *)repluns_bp->b_un.b_addr;
13704 13799 /*
13705 13800 * find out the number of luns returned by the SCSI ReportLun call
13706 13801 * and allocate buffer space
13707 13802 */
13708 13803 lun_total = lun_list_len / MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE;
13709 13804 saved_repluns = kmem_zalloc(sizeof (uint16_t) * lun_total, KM_SLEEP);
13710 13805 if (saved_repluns == NULL) {
13711 13806 scsi_free_consistent_buf(repluns_bp);
13712 13807 return (DDI_FAILURE);
13713 13808 }
13714 13809 for (lun_cnt = 0; lun_cnt < lun_total; lun_cnt++) {
13715 13810 if (mptsas_retrieve_lundata(lun_cnt, (uint8_t *)(buffer),
13716 13811 &lun_num, &lun_addr_type) != DDI_SUCCESS) {
13717 13812 continue;
13718 13813 }
13719 13814 saved_repluns[lun_cnt] = lun_num;
13720 13815 if (cdip = mptsas_find_child_addr(pdip, sas_wwn, lun_num))
13721 13816 ret = DDI_SUCCESS;
13722 13817 else
13723 13818 ret = mptsas_probe_lun(pdip, lun_num, &cdip,
13724 13819 ptgt);
13725 13820 if ((ret == DDI_SUCCESS) && (cdip != NULL)) {
13726 13821 (void) ndi_prop_remove(DDI_DEV_T_NONE, cdip,
13727 13822 MPTSAS_DEV_GONE);
13728 13823 }
13729 13824 }
13730 13825 mptsas_offline_missed_luns(pdip, saved_repluns, lun_total, ptgt);
13731 13826 kmem_free(saved_repluns, sizeof (uint16_t) * lun_total);
13732 13827 scsi_free_consistent_buf(repluns_bp);
13733 13828 return (DDI_SUCCESS);
13734 13829 }
13735 13830
13736 13831 static int
13737 13832 mptsas_config_raid(dev_info_t *pdip, uint16_t target, dev_info_t **dip)
13738 13833 {
13739 13834 int rval = DDI_FAILURE;
13740 13835 struct scsi_inquiry *sd_inq = NULL;
13741 13836 mptsas_t *mpt = DIP2MPT(pdip);
13742 13837 mptsas_target_t *ptgt = NULL;
13743 13838
13744 13839 mutex_enter(&mpt->m_mutex);
13745 13840 ptgt = mptsas_search_by_devhdl(&mpt->m_active->m_tgttbl, target);
13746 13841 mutex_exit(&mpt->m_mutex);
13747 13842 if (ptgt == NULL) {
13748 13843 mptsas_log(mpt, CE_WARN, "Volume with VolDevHandle of 0x%x "
13749 13844 "not found.", target);
13750 13845 return (rval);
13751 13846 }
13752 13847
13753 13848 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP);
13754 13849 rval = mptsas_inquiry(mpt, ptgt, 0, 0, (uchar_t *)sd_inq,
13755 13850 SUN_INQSIZE, 0, (uchar_t)0);
13756 13851
13757 13852 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) {
13758 13853 rval = mptsas_create_phys_lun(pdip, sd_inq, NULL, dip, ptgt,
13759 13854 0);
13760 13855 } else {
13761 13856 rval = DDI_FAILURE;
13762 13857 }
13763 13858
13764 13859 kmem_free(sd_inq, SUN_INQSIZE);
13765 13860 return (rval);
13766 13861 }
13767 13862
13768 13863 /*
13769 13864 * configure all RAID volumes for virtual iport
13770 13865 */
13771 13866 static void
13772 13867 mptsas_config_all_viport(dev_info_t *pdip)
13773 13868 {
13774 13869 mptsas_t *mpt = DIP2MPT(pdip);
13775 13870 int config, vol;
13776 13871 int target;
13777 13872 dev_info_t *lundip = NULL;
13778 13873 mptsas_slots_t *slots = mpt->m_active;
13779 13874
13780 13875 /*
13781 13876 * Get latest RAID info and search for any Volume DevHandles. If any
13782 13877 * are found, configure the volume.
13783 13878 */
13784 13879 mutex_enter(&mpt->m_mutex);
13785 13880 for (config = 0; config < slots->m_num_raid_configs; config++) {
13786 13881 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) {
13787 13882 if (slots->m_raidconfig[config].m_raidvol[vol].m_israid
13788 13883 == 1) {
13789 13884 target = slots->m_raidconfig[config].
13790 13885 m_raidvol[vol].m_raidhandle;
13791 13886 mutex_exit(&mpt->m_mutex);
13792 13887 (void) mptsas_config_raid(pdip, target,
13793 13888 &lundip);
13794 13889 mutex_enter(&mpt->m_mutex);
13795 13890 }
13796 13891 }
13797 13892 }
13798 13893 mutex_exit(&mpt->m_mutex);
13799 13894 }
13800 13895
13801 13896 static void
13802 13897 mptsas_offline_missed_luns(dev_info_t *pdip, uint16_t *repluns,
13803 13898 int lun_cnt, mptsas_target_t *ptgt)
13804 13899 {
13805 13900 dev_info_t *child = NULL, *savechild = NULL;
13806 13901 mdi_pathinfo_t *pip = NULL, *savepip = NULL;
13807 13902 uint64_t sas_wwn, wwid;
13808 13903 uint8_t phy;
13809 13904 int lun;
13810 13905 int i;
13811 13906 int find;
13812 13907 char *addr;
13813 13908 char *nodename;
13814 13909 mptsas_t *mpt = DIP2MPT(pdip);
13815 13910
13816 13911 mutex_enter(&mpt->m_mutex);
13817 13912 wwid = ptgt->m_sas_wwn;
13818 13913 mutex_exit(&mpt->m_mutex);
13819 13914
13820 13915 child = ddi_get_child(pdip);
13821 13916 while (child) {
13822 13917 find = 0;
13823 13918 savechild = child;
13824 13919 child = ddi_get_next_sibling(child);
13825 13920
13826 13921 nodename = ddi_node_name(savechild);
13827 13922 if (strcmp(nodename, "smp") == 0) {
13828 13923 continue;
13829 13924 }
13830 13925
13831 13926 addr = ddi_get_name_addr(savechild);
13832 13927 if (addr == NULL) {
13833 13928 continue;
13834 13929 }
13835 13930
13836 13931 if (mptsas_parse_address(addr, &sas_wwn, &phy, &lun) !=
13837 13932 DDI_SUCCESS) {
13838 13933 continue;
13839 13934 }
13840 13935
13841 13936 if (wwid == sas_wwn) {
13842 13937 for (i = 0; i < lun_cnt; i++) {
13843 13938 if (repluns[i] == lun) {
13844 13939 find = 1;
13845 13940 break;
13846 13941 }
13847 13942 }
13848 13943 } else {
13849 13944 continue;
13850 13945 }
13851 13946 if (find == 0) {
13852 13947 /*
13853 13948 * The lun has not been there already
13854 13949 */
13855 13950 (void) mptsas_offline_lun(pdip, savechild, NULL,
13856 13951 NDI_DEVI_REMOVE);
13857 13952 }
13858 13953 }
13859 13954
13860 13955 pip = mdi_get_next_client_path(pdip, NULL);
13861 13956 while (pip) {
13862 13957 find = 0;
13863 13958 savepip = pip;
13864 13959 addr = MDI_PI(pip)->pi_addr;
13865 13960
13866 13961 pip = mdi_get_next_client_path(pdip, pip);
13867 13962
13868 13963 if (addr == NULL) {
13869 13964 continue;
13870 13965 }
13871 13966
13872 13967 if (mptsas_parse_address(addr, &sas_wwn, &phy,
13873 13968 &lun) != DDI_SUCCESS) {
13874 13969 continue;
13875 13970 }
13876 13971
13877 13972 if (sas_wwn == wwid) {
13878 13973 for (i = 0; i < lun_cnt; i++) {
13879 13974 if (repluns[i] == lun) {
13880 13975 find = 1;
13881 13976 break;
13882 13977 }
13883 13978 }
13884 13979 } else {
13885 13980 continue;
13886 13981 }
13887 13982
13888 13983 if (find == 0) {
13889 13984 /*
13890 13985 * The lun has not been there already
13891 13986 */
13892 13987 (void) mptsas_offline_lun(pdip, NULL, savepip,
13893 13988 NDI_DEVI_REMOVE);
13894 13989 }
13895 13990 }
13896 13991 }
13897 13992
13898 13993 void
13899 13994 mptsas_update_hashtab(struct mptsas *mpt)
13900 13995 {
13901 13996 uint32_t page_address;
13902 13997 int rval = 0;
13903 13998 uint16_t dev_handle;
13904 13999 mptsas_target_t *ptgt = NULL;
13905 14000 mptsas_smp_t smp_node;
13906 14001
13907 14002 /*
13908 14003 * Get latest RAID info.
13909 14004 */
13910 14005 (void) mptsas_get_raid_info(mpt);
13911 14006
13912 14007 dev_handle = mpt->m_smp_devhdl;
13913 14008 for (; mpt->m_done_traverse_smp == 0; ) {
13914 14009 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL &
13915 14010 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)dev_handle;
13916 14011 if (mptsas_get_sas_expander_page0(mpt, page_address, &smp_node)
13917 14012 != DDI_SUCCESS) {
13918 14013 break;
13919 14014 }
13920 14015 mpt->m_smp_devhdl = dev_handle = smp_node.m_devhdl;
13921 14016 (void) mptsas_smp_alloc(&mpt->m_active->m_smptbl, &smp_node);
13922 14017 }
13923 14018
13924 14019 /*
13925 14020 * Config target devices
13926 14021 */
13927 14022 dev_handle = mpt->m_dev_handle;
13928 14023
13929 14024 /*
13930 14025 * Do loop to get sas device page 0 by GetNextHandle till the
13931 14026 * the last handle. If the sas device is a SATA/SSP target,
13932 14027 * we try to config it.
13933 14028 */
13934 14029 for (; mpt->m_done_traverse_dev == 0; ) {
13935 14030 ptgt = NULL;
13936 14031 page_address =
13937 14032 (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
13938 14033 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
13939 14034 (uint32_t)dev_handle;
13940 14035 rval = mptsas_get_target_device_info(mpt, page_address,
13941 14036 &dev_handle, &ptgt);
13942 14037 if ((rval == DEV_INFO_FAIL_PAGE0) ||
13943 14038 (rval == DEV_INFO_FAIL_ALLOC)) {
13944 14039 break;
13945 14040 }
13946 14041
13947 14042 mpt->m_dev_handle = dev_handle;
13948 14043 }
13949 14044
13950 14045 }
13951 14046
13952 14047 void
13953 14048 mptsas_invalid_hashtab(mptsas_hash_table_t *hashtab)
13954 14049 {
13955 14050 mptsas_hash_data_t *data;
13956 14051 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_FIRST);
13957 14052 while (data != NULL) {
13958 14053 data->devhdl = MPTSAS_INVALID_DEVHDL;
13959 14054 data->device_info = 0;
13960 14055 /*
13961 14056 * For tgttbl, clear dr_flag.
13962 14057 */
13963 14058 data->dr_flag = MPTSAS_DR_INACTIVE;
13964 14059 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_NEXT);
13965 14060 }
13966 14061 }
13967 14062
13968 14063 void
13969 14064 mptsas_update_driver_data(struct mptsas *mpt)
13970 14065 {
13971 14066 /*
13972 14067 * TODO after hard reset, update the driver data structures
13973 14068 * 1. update port/phymask mapping table mpt->m_phy_info
13974 14069 * 2. invalid all the entries in hash table
13975 14070 * m_devhdl = 0xffff and m_deviceinfo = 0
13976 14071 * 3. call sas_device_page/expander_page to update hash table
13977 14072 */
13978 14073 mptsas_update_phymask(mpt);
13979 14074 /*
13980 14075 * Invalid the existing entries
13981 14076 */
13982 14077 mptsas_invalid_hashtab(&mpt->m_active->m_tgttbl);
13983 14078 mptsas_invalid_hashtab(&mpt->m_active->m_smptbl);
13984 14079 mpt->m_done_traverse_dev = 0;
13985 14080 mpt->m_done_traverse_smp = 0;
13986 14081 mpt->m_dev_handle = mpt->m_smp_devhdl = MPTSAS_INVALID_DEVHDL;
13987 14082 mptsas_update_hashtab(mpt);
13988 14083 }
13989 14084
13990 14085 static void
13991 14086 mptsas_config_all(dev_info_t *pdip)
13992 14087 {
13993 14088 dev_info_t *smpdip = NULL;
13994 14089 mptsas_t *mpt = DIP2MPT(pdip);
13995 14090 int phymask = 0;
13996 14091 mptsas_phymask_t phy_mask;
13997 14092 mptsas_target_t *ptgt = NULL;
13998 14093 mptsas_smp_t *psmp;
13999 14094
14000 14095 /*
14001 14096 * Get the phymask associated to the iport
14002 14097 */
14003 14098 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
14004 14099 "phymask", 0);
14005 14100
14006 14101 /*
14007 14102 * Enumerate RAID volumes here (phymask == 0).
14008 14103 */
14009 14104 if (phymask == 0) {
14010 14105 mptsas_config_all_viport(pdip);
14011 14106 return;
14012 14107 }
14013 14108
14014 14109 mutex_enter(&mpt->m_mutex);
14015 14110
14016 14111 if (!mpt->m_done_traverse_dev || !mpt->m_done_traverse_smp) {
14017 14112 mptsas_update_hashtab(mpt);
14018 14113 }
14019 14114
14020 14115 psmp = (mptsas_smp_t *)mptsas_hash_traverse(&mpt->m_active->m_smptbl,
14021 14116 MPTSAS_HASH_FIRST);
14022 14117 while (psmp != NULL) {
14023 14118 phy_mask = psmp->m_phymask;
14024 14119 if (phy_mask == phymask) {
14025 14120 smpdip = NULL;
14026 14121 mutex_exit(&mpt->m_mutex);
14027 14122 (void) mptsas_online_smp(pdip, psmp, &smpdip);
14028 14123 mutex_enter(&mpt->m_mutex);
14029 14124 }
14030 14125 psmp = (mptsas_smp_t *)mptsas_hash_traverse(
14031 14126 &mpt->m_active->m_smptbl, MPTSAS_HASH_NEXT);
14032 14127 }
14033 14128
14034 14129 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
14035 14130 MPTSAS_HASH_FIRST);
14036 14131 while (ptgt != NULL) {
14037 14132 phy_mask = ptgt->m_phymask;
14038 14133 if (phy_mask == phymask) {
14039 14134 mutex_exit(&mpt->m_mutex);
14040 14135 (void) mptsas_config_target(pdip, ptgt);
14041 14136 mutex_enter(&mpt->m_mutex);
14042 14137 }
14043 14138
14044 14139 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
14045 14140 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
14046 14141 }
14047 14142 mutex_exit(&mpt->m_mutex);
14048 14143 }
14049 14144
14050 14145 static int
14051 14146 mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt)
14052 14147 {
14053 14148 int rval = DDI_FAILURE;
14054 14149 dev_info_t *tdip;
14055 14150
14056 14151 rval = mptsas_config_luns(pdip, ptgt);
14057 14152 if (rval != DDI_SUCCESS) {
14058 14153 /*
14059 14154 * The return value means the SCMD_REPORT_LUNS
14060 14155 * did not execute successfully. The target maybe
14061 14156 * doesn't support such command.
14062 14157 */
14063 14158 rval = mptsas_probe_lun(pdip, 0, &tdip, ptgt);
14064 14159 }
14065 14160 return (rval);
14066 14161 }
14067 14162
14068 14163 /*
14069 14164 * Return fail if not all the childs/paths are freed.
14070 14165 * if there is any path under the HBA, the return value will be always fail
14071 14166 * because we didn't call mdi_pi_free for path
14072 14167 */
14073 14168 static int
14074 14169 mptsas_offline_target(dev_info_t *pdip, char *name)
14075 14170 {
14076 14171 dev_info_t *child = NULL, *prechild = NULL;
14077 14172 mdi_pathinfo_t *pip = NULL, *savepip = NULL;
14078 14173 int tmp_rval, rval = DDI_SUCCESS;
14079 14174 char *addr, *cp;
14080 14175 size_t s;
14081 14176 mptsas_t *mpt = DIP2MPT(pdip);
14082 14177
14083 14178 child = ddi_get_child(pdip);
14084 14179 while (child) {
14085 14180 addr = ddi_get_name_addr(child);
14086 14181 prechild = child;
14087 14182 child = ddi_get_next_sibling(child);
14088 14183
14089 14184 if (addr == NULL) {
14090 14185 continue;
14091 14186 }
14092 14187 if ((cp = strchr(addr, ',')) == NULL) {
14093 14188 continue;
14094 14189 }
14095 14190
14096 14191 s = (uintptr_t)cp - (uintptr_t)addr;
14097 14192
14098 14193 if (strncmp(addr, name, s) != 0) {
14099 14194 continue;
14100 14195 }
14101 14196
14102 14197 tmp_rval = mptsas_offline_lun(pdip, prechild, NULL,
14103 14198 NDI_DEVI_REMOVE);
14104 14199 if (tmp_rval != DDI_SUCCESS) {
14105 14200 rval = DDI_FAILURE;
14106 14201 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
14107 14202 prechild, MPTSAS_DEV_GONE) !=
14108 14203 DDI_PROP_SUCCESS) {
14109 14204 mptsas_log(mpt, CE_WARN, "mptsas driver "
14110 14205 "unable to create property for "
14111 14206 "SAS %s (MPTSAS_DEV_GONE)", addr);
14112 14207 }
14113 14208 }
14114 14209 }
14115 14210
14116 14211 pip = mdi_get_next_client_path(pdip, NULL);
14117 14212 while (pip) {
14118 14213 addr = MDI_PI(pip)->pi_addr;
14119 14214 savepip = pip;
14120 14215 pip = mdi_get_next_client_path(pdip, pip);
14121 14216 if (addr == NULL) {
14122 14217 continue;
14123 14218 }
14124 14219
14125 14220 if ((cp = strchr(addr, ',')) == NULL) {
14126 14221 continue;
14127 14222 }
14128 14223
14129 14224 s = (uintptr_t)cp - (uintptr_t)addr;
14130 14225
14131 14226 if (strncmp(addr, name, s) != 0) {
14132 14227 continue;
14133 14228 }
14134 14229
14135 14230 (void) mptsas_offline_lun(pdip, NULL, savepip,
14136 14231 NDI_DEVI_REMOVE);
14137 14232 /*
14138 14233 * driver will not invoke mdi_pi_free, so path will not
14139 14234 * be freed forever, return DDI_FAILURE.
14140 14235 */
14141 14236 rval = DDI_FAILURE;
14142 14237 }
14143 14238 return (rval);
14144 14239 }
14145 14240
14146 14241 static int
14147 14242 mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip,
14148 14243 mdi_pathinfo_t *rpip, uint_t flags)
14149 14244 {
14150 14245 int rval = DDI_FAILURE;
14151 14246 char *devname;
14152 14247 dev_info_t *cdip, *parent;
14153 14248
14154 14249 if (rpip != NULL) {
14155 14250 parent = scsi_vhci_dip;
14156 14251 cdip = mdi_pi_get_client(rpip);
14157 14252 } else if (rdip != NULL) {
14158 14253 parent = pdip;
14159 14254 cdip = rdip;
14160 14255 } else {
14161 14256 return (DDI_FAILURE);
14162 14257 }
14163 14258
14164 14259 /*
14165 14260 * Make sure node is attached otherwise
14166 14261 * it won't have related cache nodes to
14167 14262 * clean up. i_ddi_devi_attached is
14168 14263 * similiar to i_ddi_node_state(cdip) >=
14169 14264 * DS_ATTACHED.
14170 14265 */
14171 14266 if (i_ddi_devi_attached(cdip)) {
14172 14267
14173 14268 /* Get full devname */
14174 14269 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP);
14175 14270 (void) ddi_deviname(cdip, devname);
14176 14271 /* Clean cache */
14177 14272 (void) devfs_clean(parent, devname + 1,
14178 14273 DV_CLEAN_FORCE);
14179 14274 kmem_free(devname, MAXNAMELEN + 1);
14180 14275 }
14181 14276 if (rpip != NULL) {
14182 14277 if (MDI_PI_IS_OFFLINE(rpip)) {
14183 14278 rval = DDI_SUCCESS;
14184 14279 } else {
14185 14280 rval = mdi_pi_offline(rpip, 0);
14186 14281 }
14187 14282 } else {
14188 14283 rval = ndi_devi_offline(cdip, flags);
14189 14284 }
14190 14285
14191 14286 return (rval);
14192 14287 }
14193 14288
14194 14289 static dev_info_t *
14195 14290 mptsas_find_smp_child(dev_info_t *parent, char *str_wwn)
14196 14291 {
14197 14292 dev_info_t *child = NULL;
14198 14293 char *smp_wwn = NULL;
14199 14294
14200 14295 child = ddi_get_child(parent);
14201 14296 while (child) {
14202 14297 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, child,
14203 14298 DDI_PROP_DONTPASS, SMP_WWN, &smp_wwn)
14204 14299 != DDI_SUCCESS) {
14205 14300 child = ddi_get_next_sibling(child);
14206 14301 continue;
14207 14302 }
14208 14303
14209 14304 if (strcmp(smp_wwn, str_wwn) == 0) {
14210 14305 ddi_prop_free(smp_wwn);
14211 14306 break;
14212 14307 }
14213 14308 child = ddi_get_next_sibling(child);
14214 14309 ddi_prop_free(smp_wwn);
14215 14310 }
14216 14311 return (child);
14217 14312 }
14218 14313
14219 14314 static int
14220 14315 mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, uint_t flags)
14221 14316 {
14222 14317 int rval = DDI_FAILURE;
14223 14318 char *devname;
14224 14319 char wwn_str[MPTSAS_WWN_STRLEN];
14225 14320 dev_info_t *cdip;
14226 14321
14227 14322 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_sasaddr);
14228 14323
14229 14324 cdip = mptsas_find_smp_child(pdip, wwn_str);
14230 14325
14231 14326 if (cdip == NULL)
14232 14327 return (DDI_SUCCESS);
14233 14328
14234 14329 /*
14235 14330 * Make sure node is attached otherwise
14236 14331 * it won't have related cache nodes to
14237 14332 * clean up. i_ddi_devi_attached is
14238 14333 * similiar to i_ddi_node_state(cdip) >=
14239 14334 * DS_ATTACHED.
14240 14335 */
14241 14336 if (i_ddi_devi_attached(cdip)) {
14242 14337
14243 14338 /* Get full devname */
14244 14339 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP);
14245 14340 (void) ddi_deviname(cdip, devname);
14246 14341 /* Clean cache */
14247 14342 (void) devfs_clean(pdip, devname + 1,
14248 14343 DV_CLEAN_FORCE);
14249 14344 kmem_free(devname, MAXNAMELEN + 1);
14250 14345 }
14251 14346
14252 14347 rval = ndi_devi_offline(cdip, flags);
14253 14348
14254 14349 return (rval);
14255 14350 }
14256 14351
14257 14352 static dev_info_t *
14258 14353 mptsas_find_child(dev_info_t *pdip, char *name)
14259 14354 {
14260 14355 dev_info_t *child = NULL;
14261 14356 char *rname = NULL;
14262 14357 int rval = DDI_FAILURE;
14263 14358
14264 14359 rname = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14265 14360
14266 14361 child = ddi_get_child(pdip);
14267 14362 while (child) {
14268 14363 rval = mptsas_name_child(child, rname, SCSI_MAXNAMELEN);
14269 14364 if (rval != DDI_SUCCESS) {
14270 14365 child = ddi_get_next_sibling(child);
14271 14366 bzero(rname, SCSI_MAXNAMELEN);
14272 14367 continue;
14273 14368 }
14274 14369
14275 14370 if (strcmp(rname, name) == 0) {
14276 14371 break;
14277 14372 }
14278 14373 child = ddi_get_next_sibling(child);
14279 14374 bzero(rname, SCSI_MAXNAMELEN);
14280 14375 }
14281 14376
14282 14377 kmem_free(rname, SCSI_MAXNAMELEN);
14283 14378
14284 14379 return (child);
14285 14380 }
14286 14381
14287 14382
14288 14383 static dev_info_t *
14289 14384 mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, int lun)
14290 14385 {
14291 14386 dev_info_t *child = NULL;
14292 14387 char *name = NULL;
14293 14388 char *addr = NULL;
14294 14389
14295 14390 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14296 14391 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14297 14392 (void) sprintf(name, "%016"PRIx64, sasaddr);
14298 14393 (void) sprintf(addr, "w%s,%x", name, lun);
14299 14394 child = mptsas_find_child(pdip, addr);
14300 14395 kmem_free(name, SCSI_MAXNAMELEN);
14301 14396 kmem_free(addr, SCSI_MAXNAMELEN);
14302 14397 return (child);
14303 14398 }
14304 14399
14305 14400 static dev_info_t *
14306 14401 mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy)
14307 14402 {
14308 14403 dev_info_t *child;
14309 14404 char *addr;
14310 14405
14311 14406 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14312 14407 (void) sprintf(addr, "p%x,0", phy);
14313 14408 child = mptsas_find_child(pdip, addr);
14314 14409 kmem_free(addr, SCSI_MAXNAMELEN);
14315 14410 return (child);
14316 14411 }
14317 14412
14318 14413 static mdi_pathinfo_t *
14319 14414 mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy)
14320 14415 {
14321 14416 mdi_pathinfo_t *path;
14322 14417 char *addr = NULL;
14323 14418
14324 14419 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14325 14420 (void) sprintf(addr, "p%x,0", phy);
14326 14421 path = mdi_pi_find(pdip, NULL, addr);
14327 14422 kmem_free(addr, SCSI_MAXNAMELEN);
14328 14423 return (path);
14329 14424 }
14330 14425
14331 14426 static mdi_pathinfo_t *
14332 14427 mptsas_find_path_addr(dev_info_t *parent, uint64_t sasaddr, int lun)
14333 14428 {
14334 14429 mdi_pathinfo_t *path;
14335 14430 char *name = NULL;
14336 14431 char *addr = NULL;
14337 14432
14338 14433 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14339 14434 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14340 14435 (void) sprintf(name, "%016"PRIx64, sasaddr);
14341 14436 (void) sprintf(addr, "w%s,%x", name, lun);
14342 14437 path = mdi_pi_find(parent, NULL, addr);
14343 14438 kmem_free(name, SCSI_MAXNAMELEN);
14344 14439 kmem_free(addr, SCSI_MAXNAMELEN);
14345 14440
14346 14441 return (path);
14347 14442 }
14348 14443
14349 14444 static int
14350 14445 mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq,
14351 14446 dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun)
14352 14447 {
14353 14448 int i = 0;
14354 14449 uchar_t *inq83 = NULL;
14355 14450 int inq83_len1 = 0xFF;
14356 14451 int inq83_len = 0;
14357 14452 int rval = DDI_FAILURE;
14358 14453 ddi_devid_t devid;
14359 14454 char *guid = NULL;
14360 14455 int target = ptgt->m_devhdl;
14361 14456 mdi_pathinfo_t *pip = NULL;
14362 14457 mptsas_t *mpt = DIP2MPT(pdip);
14363 14458
14364 14459 /*
14365 14460 * For DVD/CD ROM and tape devices and optical
14366 14461 * devices, we won't try to enumerate them under
14367 14462 * scsi_vhci, so no need to try page83
14368 14463 */
14369 14464 if (sd_inq && (sd_inq->inq_dtype == DTYPE_RODIRECT ||
14370 14465 sd_inq->inq_dtype == DTYPE_OPTICAL ||
14371 14466 sd_inq->inq_dtype == DTYPE_ESI))
14372 14467 goto create_lun;
14373 14468
14374 14469 /*
14375 14470 * The LCA returns good SCSI status, but corrupt page 83 data the first
14376 14471 * time it is queried. The solution is to keep trying to request page83
14377 14472 * and verify the GUID is not (DDI_NOT_WELL_FORMED) in
14378 14473 * mptsas_inq83_retry_timeout seconds. If the timeout expires, driver
14379 14474 * give up to get VPD page at this stage and fail the enumeration.
14380 14475 */
14381 14476
14382 14477 inq83 = kmem_zalloc(inq83_len1, KM_SLEEP);
14383 14478
14384 14479 for (i = 0; i < mptsas_inq83_retry_timeout; i++) {
14385 14480 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83,
14386 14481 inq83_len1, &inq83_len, 1);
14387 14482 if (rval != 0) {
14388 14483 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
14389 14484 "0x83 for target:%x, lun:%x failed!", target, lun);
14390 14485 if (mptsas_physical_bind_failed_page_83 != B_FALSE)
14391 14486 goto create_lun;
14392 14487 goto out;
14393 14488 }
14394 14489 /*
14395 14490 * create DEVID from inquiry data
14396 14491 */
14397 14492 if ((rval = ddi_devid_scsi_encode(
14398 14493 DEVID_SCSI_ENCODE_VERSION_LATEST, NULL, (uchar_t *)sd_inq,
14399 14494 sizeof (struct scsi_inquiry), NULL, 0, inq83,
14400 14495 (size_t)inq83_len, &devid)) == DDI_SUCCESS) {
14401 14496 /*
14402 14497 * extract GUID from DEVID
14403 14498 */
14404 14499 guid = ddi_devid_to_guid(devid);
14405 14500
14406 14501 /*
14407 14502 * Do not enable MPXIO if the strlen(guid) is greater
14408 14503 * than MPTSAS_MAX_GUID_LEN, this constrain would be
14409 14504 * handled by framework later.
14410 14505 */
14411 14506 if (guid && (strlen(guid) > MPTSAS_MAX_GUID_LEN)) {
14412 14507 ddi_devid_free_guid(guid);
14413 14508 guid = NULL;
14414 14509 if (mpt->m_mpxio_enable == TRUE) {
14415 14510 mptsas_log(mpt, CE_NOTE, "!Target:%x, "
14416 14511 "lun:%x doesn't have a valid GUID, "
14417 14512 "multipathing for this drive is "
14418 14513 "not enabled", target, lun);
14419 14514 }
14420 14515 }
14421 14516
14422 14517 /*
14423 14518 * devid no longer needed
14424 14519 */
14425 14520 ddi_devid_free(devid);
14426 14521 break;
14427 14522 } else if (rval == DDI_NOT_WELL_FORMED) {
14428 14523 /*
14429 14524 * return value of ddi_devid_scsi_encode equal to
14430 14525 * DDI_NOT_WELL_FORMED means DEVID_RETRY, it worth
14431 14526 * to retry inquiry page 0x83 and get GUID.
14432 14527 */
14433 14528 NDBG20(("Not well formed devid, retry..."));
14434 14529 delay(1 * drv_usectohz(1000000));
14435 14530 continue;
14436 14531 } else {
14437 14532 mptsas_log(mpt, CE_WARN, "!Encode devid failed for "
14438 14533 "path target:%x, lun:%x", target, lun);
14439 14534 rval = DDI_FAILURE;
14440 14535 goto create_lun;
14441 14536 }
14442 14537 }
14443 14538
14444 14539 if (i == mptsas_inq83_retry_timeout) {
14445 14540 mptsas_log(mpt, CE_WARN, "!Repeated page83 requests timeout "
14446 14541 "for path target:%x, lun:%x", target, lun);
14447 14542 }
14448 14543
14449 14544 rval = DDI_FAILURE;
14450 14545
14451 14546 create_lun:
14452 14547 if ((guid != NULL) && (mpt->m_mpxio_enable == TRUE)) {
14453 14548 rval = mptsas_create_virt_lun(pdip, sd_inq, guid, lun_dip, &pip,
14454 14549 ptgt, lun);
14455 14550 }
14456 14551 if (rval != DDI_SUCCESS) {
14457 14552 rval = mptsas_create_phys_lun(pdip, sd_inq, guid, lun_dip,
14458 14553 ptgt, lun);
14459 14554
14460 14555 }
14461 14556 out:
14462 14557 if (guid != NULL) {
14463 14558 /*
14464 14559 * guid no longer needed
14465 14560 */
14466 14561 ddi_devid_free_guid(guid);
14467 14562 }
14468 14563 if (inq83 != NULL)
14469 14564 kmem_free(inq83, inq83_len1);
14470 14565 return (rval);
14471 14566 }
14472 14567
14473 14568 static int
14474 14569 mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *inq, char *guid,
14475 14570 dev_info_t **lun_dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, int lun)
14476 14571 {
14477 14572 int target;
14478 14573 char *nodename = NULL;
14479 14574 char **compatible = NULL;
14480 14575 int ncompatible = 0;
14481 14576 int mdi_rtn = MDI_FAILURE;
14482 14577 int rval = DDI_FAILURE;
14483 14578 char *old_guid = NULL;
14484 14579 mptsas_t *mpt = DIP2MPT(pdip);
14485 14580 char *lun_addr = NULL;
14486 14581 char *wwn_str = NULL;
14487 14582 char *attached_wwn_str = NULL;
14488 14583 char *component = NULL;
14489 14584 uint8_t phy = 0xFF;
14490 14585 uint64_t sas_wwn;
14491 14586 int64_t lun64 = 0;
14492 14587 uint32_t devinfo;
14493 14588 uint16_t dev_hdl;
14494 14589 uint16_t pdev_hdl;
14495 14590 uint64_t dev_sas_wwn;
14496 14591 uint64_t pdev_sas_wwn;
14497 14592 uint32_t pdev_info;
14498 14593 uint8_t physport;
14499 14594 uint8_t phy_id;
14500 14595 uint32_t page_address;
14501 14596 uint16_t bay_num, enclosure;
14502 14597 char pdev_wwn_str[MPTSAS_WWN_STRLEN];
14503 14598 uint32_t dev_info;
14504 14599
14505 14600 mutex_enter(&mpt->m_mutex);
14506 14601 target = ptgt->m_devhdl;
14507 14602 sas_wwn = ptgt->m_sas_wwn;
14508 14603 devinfo = ptgt->m_deviceinfo;
14509 14604 phy = ptgt->m_phynum;
14510 14605 mutex_exit(&mpt->m_mutex);
14511 14606
14512 14607 if (sas_wwn) {
14513 14608 *pip = mptsas_find_path_addr(pdip, sas_wwn, lun);
14514 14609 } else {
14515 14610 *pip = mptsas_find_path_phy(pdip, phy);
14516 14611 }
14517 14612
14518 14613 if (*pip != NULL) {
14519 14614 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip;
14520 14615 ASSERT(*lun_dip != NULL);
14521 14616 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, *lun_dip,
14522 14617 (DDI_PROP_DONTPASS | DDI_PROP_NOTPROM),
14523 14618 MDI_CLIENT_GUID_PROP, &old_guid) == DDI_SUCCESS) {
14524 14619 if (strncmp(guid, old_guid, strlen(guid)) == 0) {
14525 14620 /*
14526 14621 * Same path back online again.
14527 14622 */
14528 14623 (void) ddi_prop_free(old_guid);
14529 14624 if ((!MDI_PI_IS_ONLINE(*pip)) &&
14530 14625 (!MDI_PI_IS_STANDBY(*pip)) &&
14531 14626 (ptgt->m_tgt_unconfigured == 0)) {
14532 14627 rval = mdi_pi_online(*pip, 0);
14533 14628 mutex_enter(&mpt->m_mutex);
14534 14629 (void) mptsas_set_led_status(mpt, ptgt,
14535 14630 0);
14536 14631 mutex_exit(&mpt->m_mutex);
14537 14632 } else {
14538 14633 rval = DDI_SUCCESS;
14539 14634 }
14540 14635 if (rval != DDI_SUCCESS) {
14541 14636 mptsas_log(mpt, CE_WARN, "path:target: "
14542 14637 "%x, lun:%x online failed!", target,
14543 14638 lun);
14544 14639 *pip = NULL;
14545 14640 *lun_dip = NULL;
14546 14641 }
14547 14642 return (rval);
14548 14643 } else {
14549 14644 /*
14550 14645 * The GUID of the LUN has changed which maybe
14551 14646 * because customer mapped another volume to the
14552 14647 * same LUN.
14553 14648 */
14554 14649 mptsas_log(mpt, CE_WARN, "The GUID of the "
14555 14650 "target:%x, lun:%x was changed, maybe "
14556 14651 "because someone mapped another volume "
14557 14652 "to the same LUN", target, lun);
14558 14653 (void) ddi_prop_free(old_guid);
14559 14654 if (!MDI_PI_IS_OFFLINE(*pip)) {
14560 14655 rval = mdi_pi_offline(*pip, 0);
14561 14656 if (rval != MDI_SUCCESS) {
14562 14657 mptsas_log(mpt, CE_WARN, "path:"
14563 14658 "target:%x, lun:%x offline "
14564 14659 "failed!", target, lun);
14565 14660 *pip = NULL;
14566 14661 *lun_dip = NULL;
14567 14662 return (DDI_FAILURE);
14568 14663 }
14569 14664 }
14570 14665 if (mdi_pi_free(*pip, 0) != MDI_SUCCESS) {
14571 14666 mptsas_log(mpt, CE_WARN, "path:target:"
14572 14667 "%x, lun:%x free failed!", target,
14573 14668 lun);
14574 14669 *pip = NULL;
14575 14670 *lun_dip = NULL;
14576 14671 return (DDI_FAILURE);
14577 14672 }
14578 14673 }
14579 14674 } else {
14580 14675 mptsas_log(mpt, CE_WARN, "Can't get client-guid "
14581 14676 "property for path:target:%x, lun:%x", target, lun);
14582 14677 *pip = NULL;
14583 14678 *lun_dip = NULL;
14584 14679 return (DDI_FAILURE);
14585 14680 }
14586 14681 }
14587 14682 scsi_hba_nodename_compatible_get(inq, NULL,
14588 14683 inq->inq_dtype, NULL, &nodename, &compatible, &ncompatible);
14589 14684
14590 14685 /*
14591 14686 * if nodename can't be determined then print a message and skip it
14592 14687 */
14593 14688 if (nodename == NULL) {
14594 14689 mptsas_log(mpt, CE_WARN, "mptsas driver found no compatible "
14595 14690 "driver for target%d lun %d dtype:0x%02x", target, lun,
14596 14691 inq->inq_dtype);
14597 14692 return (DDI_FAILURE);
14598 14693 }
14599 14694
14600 14695 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP);
14601 14696 /* The property is needed by MPAPI */
14602 14697 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn);
14603 14698
14604 14699 lun_addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14605 14700 if (guid) {
14606 14701 (void) sprintf(lun_addr, "w%s,%x", wwn_str, lun);
14607 14702 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
14608 14703 } else {
14609 14704 (void) sprintf(lun_addr, "p%x,%x", phy, lun);
14610 14705 (void) sprintf(wwn_str, "p%x", phy);
14611 14706 }
14612 14707
14613 14708 mdi_rtn = mdi_pi_alloc_compatible(pdip, nodename,
14614 14709 guid, lun_addr, compatible, ncompatible,
14615 14710 0, pip);
14616 14711 if (mdi_rtn == MDI_SUCCESS) {
14617 14712
14618 14713 if (mdi_prop_update_string(*pip, MDI_GUID,
14619 14714 guid) != DDI_SUCCESS) {
14620 14715 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14621 14716 "create prop for target %d lun %d (MDI_GUID)",
14622 14717 target, lun);
14623 14718 mdi_rtn = MDI_FAILURE;
14624 14719 goto virt_create_done;
14625 14720 }
14626 14721
14627 14722 if (mdi_prop_update_int(*pip, LUN_PROP,
14628 14723 lun) != DDI_SUCCESS) {
14629 14724 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14630 14725 "create prop for target %d lun %d (LUN_PROP)",
14631 14726 target, lun);
14632 14727 mdi_rtn = MDI_FAILURE;
14633 14728 goto virt_create_done;
14634 14729 }
14635 14730 lun64 = (int64_t)lun;
14636 14731 if (mdi_prop_update_int64(*pip, LUN64_PROP,
14637 14732 lun64) != DDI_SUCCESS) {
14638 14733 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14639 14734 "create prop for target %d (LUN64_PROP)",
14640 14735 target);
14641 14736 mdi_rtn = MDI_FAILURE;
14642 14737 goto virt_create_done;
14643 14738 }
14644 14739 if (mdi_prop_update_string_array(*pip, "compatible",
14645 14740 compatible, ncompatible) !=
14646 14741 DDI_PROP_SUCCESS) {
14647 14742 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14648 14743 "create prop for target %d lun %d (COMPATIBLE)",
14649 14744 target, lun);
14650 14745 mdi_rtn = MDI_FAILURE;
14651 14746 goto virt_create_done;
14652 14747 }
14653 14748 if (sas_wwn && (mdi_prop_update_string(*pip,
14654 14749 SCSI_ADDR_PROP_TARGET_PORT, wwn_str) != DDI_PROP_SUCCESS)) {
14655 14750 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14656 14751 "create prop for target %d lun %d "
14657 14752 "(target-port)", target, lun);
14658 14753 mdi_rtn = MDI_FAILURE;
14659 14754 goto virt_create_done;
14660 14755 } else if ((sas_wwn == 0) && (mdi_prop_update_int(*pip,
14661 14756 "sata-phy", phy) != DDI_PROP_SUCCESS)) {
14662 14757 /*
14663 14758 * Direct attached SATA device without DeviceName
14664 14759 */
14665 14760 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14666 14761 "create prop for SAS target %d lun %d "
14667 14762 "(sata-phy)", target, lun);
14668 14763 mdi_rtn = MDI_FAILURE;
14669 14764 goto virt_create_done;
14670 14765 }
14671 14766 mutex_enter(&mpt->m_mutex);
14672 14767
14673 14768 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14674 14769 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
14675 14770 (uint32_t)ptgt->m_devhdl;
14676 14771 rval = mptsas_get_sas_device_page0(mpt, page_address,
14677 14772 &dev_hdl, &dev_sas_wwn, &dev_info, &physport,
14678 14773 &phy_id, &pdev_hdl, &bay_num, &enclosure);
14679 14774 if (rval != DDI_SUCCESS) {
14680 14775 mutex_exit(&mpt->m_mutex);
14681 14776 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
14682 14777 "parent device for handle %d", page_address);
14683 14778 mdi_rtn = MDI_FAILURE;
14684 14779 goto virt_create_done;
14685 14780 }
14686 14781
14687 14782 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14688 14783 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl;
14689 14784 rval = mptsas_get_sas_device_page0(mpt, page_address,
14690 14785 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport,
14691 14786 &phy_id, &pdev_hdl, &bay_num, &enclosure);
14692 14787 if (rval != DDI_SUCCESS) {
14693 14788 mutex_exit(&mpt->m_mutex);
14694 14789 mptsas_log(mpt, CE_WARN, "mptsas unable to get"
14695 14790 "device info for handle %d", page_address);
14696 14791 mdi_rtn = MDI_FAILURE;
14697 14792 goto virt_create_done;
14698 14793 }
14699 14794
14700 14795 mutex_exit(&mpt->m_mutex);
14701 14796
14702 14797 /*
14703 14798 * If this device direct attached to the controller
14704 14799 * set the attached-port to the base wwid
14705 14800 */
14706 14801 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
14707 14802 != DEVINFO_DIRECT_ATTACHED) {
14708 14803 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
14709 14804 pdev_sas_wwn);
14710 14805 } else {
14711 14806 /*
14712 14807 * Update the iport's attached-port to guid
14713 14808 */
14714 14809 if (sas_wwn == 0) {
14715 14810 (void) sprintf(wwn_str, "p%x", phy);
14716 14811 } else {
14717 14812 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
14718 14813 }
14719 14814 if (ddi_prop_update_string(DDI_DEV_T_NONE,
14720 14815 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
14721 14816 DDI_PROP_SUCCESS) {
14722 14817 mptsas_log(mpt, CE_WARN,
14723 14818 "mptsas unable to create "
14724 14819 "property for iport target-port"
14725 14820 " %s (sas_wwn)",
14726 14821 wwn_str);
14727 14822 mdi_rtn = MDI_FAILURE;
14728 14823 goto virt_create_done;
14729 14824 }
14730 14825
14731 14826 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
14732 14827 mpt->un.m_base_wwid);
14733 14828 }
14734 14829
14735 14830 if (mdi_prop_update_string(*pip,
14736 14831 SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) !=
14737 14832 DDI_PROP_SUCCESS) {
14738 14833 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14739 14834 "property for iport attached-port %s (sas_wwn)",
14740 14835 attached_wwn_str);
14741 14836 mdi_rtn = MDI_FAILURE;
14742 14837 goto virt_create_done;
14743 14838 }
14744 14839
14745 14840
14746 14841 if (inq->inq_dtype == 0) {
14747 14842 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP);
14748 14843 /*
14749 14844 * set obp path for pathinfo
14750 14845 */
14751 14846 (void) snprintf(component, MAXPATHLEN,
14752 14847 "disk@%s", lun_addr);
14753 14848
14754 14849 if (mdi_pi_pathname_obp_set(*pip, component) !=
14755 14850 DDI_SUCCESS) {
14756 14851 mptsas_log(mpt, CE_WARN, "mpt_sas driver "
14757 14852 "unable to set obp-path for object %s",
14758 14853 component);
14759 14854 mdi_rtn = MDI_FAILURE;
14760 14855 goto virt_create_done;
14761 14856 }
14762 14857 }
14763 14858
14764 14859 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip;
14765 14860 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
14766 14861 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
14767 14862 if ((ndi_prop_update_int(DDI_DEV_T_NONE, *lun_dip,
14768 14863 "pm-capable", 1)) !=
14769 14864 DDI_PROP_SUCCESS) {
14770 14865 mptsas_log(mpt, CE_WARN, "mptsas driver"
14771 14866 "failed to create pm-capable "
14772 14867 "property, target %d", target);
14773 14868 mdi_rtn = MDI_FAILURE;
14774 14869 goto virt_create_done;
14775 14870 }
14776 14871 }
14777 14872 /*
14778 14873 * Create the phy-num property
14779 14874 */
14780 14875 if (mdi_prop_update_int(*pip, "phy-num",
14781 14876 ptgt->m_phynum) != DDI_SUCCESS) {
14782 14877 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14783 14878 "create phy-num property for target %d lun %d",
14784 14879 target, lun);
14785 14880 mdi_rtn = MDI_FAILURE;
14786 14881 goto virt_create_done;
14787 14882 }
14788 14883 NDBG20(("new path:%s onlining,", MDI_PI(*pip)->pi_addr));
14789 14884 mdi_rtn = mdi_pi_online(*pip, 0);
14790 14885 if (mdi_rtn == MDI_SUCCESS) {
14791 14886 mutex_enter(&mpt->m_mutex);
14792 14887 if (mptsas_set_led_status(mpt, ptgt, 0) !=
14793 14888 DDI_SUCCESS) {
14794 14889 NDBG14(("mptsas: clear LED for slot %x "
14795 14890 "failed", ptgt->m_slot_num));
14796 14891 }
14797 14892 mutex_exit(&mpt->m_mutex);
14798 14893 }
14799 14894 if (mdi_rtn == MDI_NOT_SUPPORTED) {
14800 14895 mdi_rtn = MDI_FAILURE;
14801 14896 }
14802 14897 virt_create_done:
14803 14898 if (*pip && mdi_rtn != MDI_SUCCESS) {
14804 14899 (void) mdi_pi_free(*pip, 0);
14805 14900 *pip = NULL;
14806 14901 *lun_dip = NULL;
14807 14902 }
14808 14903 }
14809 14904
14810 14905 scsi_hba_nodename_compatible_free(nodename, compatible);
14811 14906 if (lun_addr != NULL) {
14812 14907 kmem_free(lun_addr, SCSI_MAXNAMELEN);
14813 14908 }
14814 14909 if (wwn_str != NULL) {
14815 14910 kmem_free(wwn_str, MPTSAS_WWN_STRLEN);
14816 14911 }
14817 14912 if (component != NULL) {
14818 14913 kmem_free(component, MAXPATHLEN);
14819 14914 }
14820 14915
14821 14916 return ((mdi_rtn == MDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
14822 14917 }
14823 14918
14824 14919 static int
14825 14920 mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *inq,
14826 14921 char *guid, dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun)
14827 14922 {
14828 14923 int target;
14829 14924 int rval;
14830 14925 int ndi_rtn = NDI_FAILURE;
14831 14926 uint64_t be_sas_wwn;
14832 14927 char *nodename = NULL;
14833 14928 char **compatible = NULL;
14834 14929 int ncompatible = 0;
14835 14930 int instance = 0;
14836 14931 mptsas_t *mpt = DIP2MPT(pdip);
14837 14932 char *wwn_str = NULL;
14838 14933 char *component = NULL;
14839 14934 char *attached_wwn_str = NULL;
14840 14935 uint8_t phy = 0xFF;
14841 14936 uint64_t sas_wwn;
14842 14937 uint32_t devinfo;
14843 14938 uint16_t dev_hdl;
14844 14939 uint16_t pdev_hdl;
14845 14940 uint64_t pdev_sas_wwn;
14846 14941 uint64_t dev_sas_wwn;
14847 14942 uint32_t pdev_info;
14848 14943 uint8_t physport;
14849 14944 uint8_t phy_id;
14850 14945 uint32_t page_address;
14851 14946 uint16_t bay_num, enclosure;
14852 14947 char pdev_wwn_str[MPTSAS_WWN_STRLEN];
14853 14948 uint32_t dev_info;
14854 14949 int64_t lun64 = 0;
14855 14950
14856 14951 mutex_enter(&mpt->m_mutex);
14857 14952 target = ptgt->m_devhdl;
14858 14953 sas_wwn = ptgt->m_sas_wwn;
14859 14954 devinfo = ptgt->m_deviceinfo;
14860 14955 phy = ptgt->m_phynum;
14861 14956 mutex_exit(&mpt->m_mutex);
14862 14957
14863 14958 /*
14864 14959 * generate compatible property with binding-set "mpt"
14865 14960 */
14866 14961 scsi_hba_nodename_compatible_get(inq, NULL, inq->inq_dtype, NULL,
14867 14962 &nodename, &compatible, &ncompatible);
14868 14963
14869 14964 /*
14870 14965 * if nodename can't be determined then print a message and skip it
14871 14966 */
14872 14967 if (nodename == NULL) {
14873 14968 mptsas_log(mpt, CE_WARN, "mptsas found no compatible driver "
14874 14969 "for target %d lun %d", target, lun);
14875 14970 return (DDI_FAILURE);
14876 14971 }
14877 14972
14878 14973 ndi_rtn = ndi_devi_alloc(pdip, nodename,
14879 14974 DEVI_SID_NODEID, lun_dip);
14880 14975
14881 14976 /*
14882 14977 * if lun alloc success, set props
14883 14978 */
14884 14979 if (ndi_rtn == NDI_SUCCESS) {
14885 14980
14886 14981 if (ndi_prop_update_int(DDI_DEV_T_NONE,
14887 14982 *lun_dip, LUN_PROP, lun) !=
14888 14983 DDI_PROP_SUCCESS) {
14889 14984 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14890 14985 "property for target %d lun %d (LUN_PROP)",
14891 14986 target, lun);
14892 14987 ndi_rtn = NDI_FAILURE;
14893 14988 goto phys_create_done;
14894 14989 }
14895 14990
14896 14991 lun64 = (int64_t)lun;
14897 14992 if (ndi_prop_update_int64(DDI_DEV_T_NONE,
14898 14993 *lun_dip, LUN64_PROP, lun64) !=
14899 14994 DDI_PROP_SUCCESS) {
14900 14995 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14901 14996 "property for target %d lun64 %d (LUN64_PROP)",
14902 14997 target, lun);
14903 14998 ndi_rtn = NDI_FAILURE;
14904 14999 goto phys_create_done;
14905 15000 }
14906 15001 if (ndi_prop_update_string_array(DDI_DEV_T_NONE,
14907 15002 *lun_dip, "compatible", compatible, ncompatible)
14908 15003 != DDI_PROP_SUCCESS) {
14909 15004 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14910 15005 "property for target %d lun %d (COMPATIBLE)",
14911 15006 target, lun);
14912 15007 ndi_rtn = NDI_FAILURE;
14913 15008 goto phys_create_done;
14914 15009 }
14915 15010
14916 15011 /*
14917 15012 * We need the SAS WWN for non-multipath devices, so
14918 15013 * we'll use the same property as that multipathing
14919 15014 * devices need to present for MPAPI. If we don't have
14920 15015 * a WWN (e.g. parallel SCSI), don't create the prop.
14921 15016 */
14922 15017 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP);
14923 15018 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
14924 15019 if (sas_wwn && ndi_prop_update_string(DDI_DEV_T_NONE,
14925 15020 *lun_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str)
14926 15021 != DDI_PROP_SUCCESS) {
14927 15022 mptsas_log(mpt, CE_WARN, "mptsas unable to "
14928 15023 "create property for SAS target %d lun %d "
14929 15024 "(target-port)", target, lun);
14930 15025 ndi_rtn = NDI_FAILURE;
14931 15026 goto phys_create_done;
14932 15027 }
14933 15028
14934 15029 be_sas_wwn = BE_64(sas_wwn);
14935 15030 if (sas_wwn && ndi_prop_update_byte_array(
14936 15031 DDI_DEV_T_NONE, *lun_dip, "port-wwn",
14937 15032 (uchar_t *)&be_sas_wwn, 8) != DDI_PROP_SUCCESS) {
14938 15033 mptsas_log(mpt, CE_WARN, "mptsas unable to "
14939 15034 "create property for SAS target %d lun %d "
14940 15035 "(port-wwn)", target, lun);
14941 15036 ndi_rtn = NDI_FAILURE;
14942 15037 goto phys_create_done;
14943 15038 } else if ((sas_wwn == 0) && (ndi_prop_update_int(
14944 15039 DDI_DEV_T_NONE, *lun_dip, "sata-phy", phy) !=
14945 15040 DDI_PROP_SUCCESS)) {
14946 15041 /*
14947 15042 * Direct attached SATA device without DeviceName
14948 15043 */
14949 15044 mptsas_log(mpt, CE_WARN, "mptsas unable to "
14950 15045 "create property for SAS target %d lun %d "
14951 15046 "(sata-phy)", target, lun);
14952 15047 ndi_rtn = NDI_FAILURE;
14953 15048 goto phys_create_done;
14954 15049 }
14955 15050
14956 15051 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
14957 15052 *lun_dip, SAS_PROP) != DDI_PROP_SUCCESS) {
14958 15053 mptsas_log(mpt, CE_WARN, "mptsas unable to"
14959 15054 "create property for SAS target %d lun %d"
14960 15055 " (SAS_PROP)", target, lun);
14961 15056 ndi_rtn = NDI_FAILURE;
14962 15057 goto phys_create_done;
14963 15058 }
14964 15059 if (guid && (ndi_prop_update_string(DDI_DEV_T_NONE,
14965 15060 *lun_dip, NDI_GUID, guid) != DDI_SUCCESS)) {
14966 15061 mptsas_log(mpt, CE_WARN, "mptsas unable "
14967 15062 "to create guid property for target %d "
14968 15063 "lun %d", target, lun);
14969 15064 ndi_rtn = NDI_FAILURE;
14970 15065 goto phys_create_done;
14971 15066 }
14972 15067
14973 15068 /*
14974 15069 * The following code is to set properties for SM-HBA support,
14975 15070 * it doesn't apply to RAID volumes
14976 15071 */
14977 15072 if (ptgt->m_phymask == 0)
14978 15073 goto phys_raid_lun;
14979 15074
14980 15075 mutex_enter(&mpt->m_mutex);
14981 15076
14982 15077 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14983 15078 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
14984 15079 (uint32_t)ptgt->m_devhdl;
14985 15080 rval = mptsas_get_sas_device_page0(mpt, page_address,
14986 15081 &dev_hdl, &dev_sas_wwn, &dev_info,
14987 15082 &physport, &phy_id, &pdev_hdl,
14988 15083 &bay_num, &enclosure);
14989 15084 if (rval != DDI_SUCCESS) {
14990 15085 mutex_exit(&mpt->m_mutex);
14991 15086 mptsas_log(mpt, CE_WARN, "mptsas unable to get"
14992 15087 "parent device for handle %d.", page_address);
14993 15088 ndi_rtn = NDI_FAILURE;
14994 15089 goto phys_create_done;
14995 15090 }
14996 15091
14997 15092 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14998 15093 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl;
14999 15094 rval = mptsas_get_sas_device_page0(mpt, page_address,
15000 15095 &dev_hdl, &pdev_sas_wwn, &pdev_info,
15001 15096 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure);
15002 15097 if (rval != DDI_SUCCESS) {
15003 15098 mutex_exit(&mpt->m_mutex);
15004 15099 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15005 15100 "device for handle %d.", page_address);
15006 15101 ndi_rtn = NDI_FAILURE;
15007 15102 goto phys_create_done;
15008 15103 }
15009 15104
15010 15105 mutex_exit(&mpt->m_mutex);
15011 15106
15012 15107 /*
15013 15108 * If this device direct attached to the controller
15014 15109 * set the attached-port to the base wwid
15015 15110 */
15016 15111 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
15017 15112 != DEVINFO_DIRECT_ATTACHED) {
15018 15113 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
15019 15114 pdev_sas_wwn);
15020 15115 } else {
15021 15116 /*
15022 15117 * Update the iport's attached-port to guid
15023 15118 */
15024 15119 if (sas_wwn == 0) {
15025 15120 (void) sprintf(wwn_str, "p%x", phy);
15026 15121 } else {
15027 15122 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
15028 15123 }
15029 15124 if (ddi_prop_update_string(DDI_DEV_T_NONE,
15030 15125 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
15031 15126 DDI_PROP_SUCCESS) {
15032 15127 mptsas_log(mpt, CE_WARN,
15033 15128 "mptsas unable to create "
15034 15129 "property for iport target-port"
15035 15130 " %s (sas_wwn)",
15036 15131 wwn_str);
15037 15132 ndi_rtn = NDI_FAILURE;
15038 15133 goto phys_create_done;
15039 15134 }
15040 15135
15041 15136 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
15042 15137 mpt->un.m_base_wwid);
15043 15138 }
15044 15139
15045 15140 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15046 15141 *lun_dip, SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) !=
15047 15142 DDI_PROP_SUCCESS) {
15048 15143 mptsas_log(mpt, CE_WARN,
15049 15144 "mptsas unable to create "
15050 15145 "property for iport attached-port %s (sas_wwn)",
15051 15146 attached_wwn_str);
15052 15147 ndi_rtn = NDI_FAILURE;
15053 15148 goto phys_create_done;
15054 15149 }
15055 15150
15056 15151 if (IS_SATA_DEVICE(dev_info)) {
15057 15152 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15058 15153 *lun_dip, MPTSAS_VARIANT, "sata") !=
15059 15154 DDI_PROP_SUCCESS) {
15060 15155 mptsas_log(mpt, CE_WARN,
15061 15156 "mptsas unable to create "
15062 15157 "property for device variant ");
15063 15158 ndi_rtn = NDI_FAILURE;
15064 15159 goto phys_create_done;
15065 15160 }
15066 15161 }
15067 15162
15068 15163 if (IS_ATAPI_DEVICE(dev_info)) {
15069 15164 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15070 15165 *lun_dip, MPTSAS_VARIANT, "atapi") !=
15071 15166 DDI_PROP_SUCCESS) {
15072 15167 mptsas_log(mpt, CE_WARN,
15073 15168 "mptsas unable to create "
15074 15169 "property for device variant ");
15075 15170 ndi_rtn = NDI_FAILURE;
15076 15171 goto phys_create_done;
15077 15172 }
15078 15173 }
15079 15174
15080 15175 phys_raid_lun:
15081 15176 /*
15082 15177 * if this is a SAS controller, and the target is a SATA
15083 15178 * drive, set the 'pm-capable' property for sd and if on
15084 15179 * an OPL platform, also check if this is an ATAPI
15085 15180 * device.
15086 15181 */
15087 15182 instance = ddi_get_instance(mpt->m_dip);
15088 15183 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
15089 15184 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
15090 15185 NDBG2(("mptsas%d: creating pm-capable property, "
15091 15186 "target %d", instance, target));
15092 15187
15093 15188 if ((ndi_prop_update_int(DDI_DEV_T_NONE,
15094 15189 *lun_dip, "pm-capable", 1)) !=
15095 15190 DDI_PROP_SUCCESS) {
15096 15191 mptsas_log(mpt, CE_WARN, "mptsas "
15097 15192 "failed to create pm-capable "
15098 15193 "property, target %d", target);
15099 15194 ndi_rtn = NDI_FAILURE;
15100 15195 goto phys_create_done;
15101 15196 }
15102 15197
15103 15198 }
15104 15199
15105 15200 if ((inq->inq_dtype == 0) || (inq->inq_dtype == 5)) {
15106 15201 /*
15107 15202 * add 'obp-path' properties for devinfo
15108 15203 */
15109 15204 bzero(wwn_str, sizeof (wwn_str));
15110 15205 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn);
15111 15206 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP);
15112 15207 if (guid) {
15113 15208 (void) snprintf(component, MAXPATHLEN,
15114 15209 "disk@w%s,%x", wwn_str, lun);
15115 15210 } else {
15116 15211 (void) snprintf(component, MAXPATHLEN,
15117 15212 "disk@p%x,%x", phy, lun);
15118 15213 }
15119 15214 if (ddi_pathname_obp_set(*lun_dip, component)
15120 15215 != DDI_SUCCESS) {
15121 15216 mptsas_log(mpt, CE_WARN, "mpt_sas driver "
15122 15217 "unable to set obp-path for SAS "
15123 15218 "object %s", component);
15124 15219 ndi_rtn = NDI_FAILURE;
15125 15220 goto phys_create_done;
15126 15221 }
15127 15222 }
15128 15223 /*
15129 15224 * Create the phy-num property for non-raid disk
15130 15225 */
15131 15226 if (ptgt->m_phymask != 0) {
15132 15227 if (ndi_prop_update_int(DDI_DEV_T_NONE,
15133 15228 *lun_dip, "phy-num", ptgt->m_phynum) !=
15134 15229 DDI_PROP_SUCCESS) {
15135 15230 mptsas_log(mpt, CE_WARN, "mptsas driver "
15136 15231 "failed to create phy-num property for "
15137 15232 "target %d", target);
15138 15233 ndi_rtn = NDI_FAILURE;
15139 15234 goto phys_create_done;
15140 15235 }
15141 15236 }
15142 15237 phys_create_done:
15143 15238 /*
15144 15239 * If props were setup ok, online the lun
15145 15240 */
15146 15241 if (ndi_rtn == NDI_SUCCESS) {
15147 15242 /*
15148 15243 * Try to online the new node
15149 15244 */
15150 15245 ndi_rtn = ndi_devi_online(*lun_dip, NDI_ONLINE_ATTACH);
15151 15246 }
15152 15247 if (ndi_rtn == NDI_SUCCESS) {
15153 15248 mutex_enter(&mpt->m_mutex);
15154 15249 if (mptsas_set_led_status(mpt, ptgt, 0) !=
15155 15250 DDI_SUCCESS) {
15156 15251 NDBG14(("mptsas: clear LED for tgt %x "
15157 15252 "failed", ptgt->m_slot_num));
15158 15253 }
15159 15254 mutex_exit(&mpt->m_mutex);
15160 15255 }
15161 15256
15162 15257 /*
15163 15258 * If success set rtn flag, else unwire alloc'd lun
15164 15259 */
15165 15260 if (ndi_rtn != NDI_SUCCESS) {
15166 15261 NDBG12(("mptsas driver unable to online "
15167 15262 "target %d lun %d", target, lun));
15168 15263 ndi_prop_remove_all(*lun_dip);
15169 15264 (void) ndi_devi_free(*lun_dip);
15170 15265 *lun_dip = NULL;
15171 15266 }
15172 15267 }
15173 15268
15174 15269 scsi_hba_nodename_compatible_free(nodename, compatible);
15175 15270
15176 15271 if (wwn_str != NULL) {
15177 15272 kmem_free(wwn_str, MPTSAS_WWN_STRLEN);
15178 15273 }
15179 15274 if (component != NULL) {
15180 15275 kmem_free(component, MAXPATHLEN);
15181 15276 }
15182 15277
15183 15278
15184 15279 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
15185 15280 }
15186 15281
15187 15282 static int
15188 15283 mptsas_probe_smp(dev_info_t *pdip, uint64_t wwn)
15189 15284 {
15190 15285 mptsas_t *mpt = DIP2MPT(pdip);
15191 15286 struct smp_device smp_sd;
15192 15287
15193 15288 /* XXX An HBA driver should not be allocating an smp_device. */
15194 15289 bzero(&smp_sd, sizeof (struct smp_device));
15195 15290 smp_sd.smp_sd_address.smp_a_hba_tran = mpt->m_smptran;
15196 15291 bcopy(&wwn, smp_sd.smp_sd_address.smp_a_wwn, SAS_WWN_BYTE_SIZE);
15197 15292
15198 15293 if (smp_probe(&smp_sd) != DDI_PROBE_SUCCESS)
15199 15294 return (NDI_FAILURE);
15200 15295 return (NDI_SUCCESS);
15201 15296 }
15202 15297
15203 15298 static int
15204 15299 mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, dev_info_t **smp_dip)
15205 15300 {
15206 15301 mptsas_t *mpt = DIP2MPT(pdip);
15207 15302 mptsas_smp_t *psmp = NULL;
15208 15303 int rval;
15209 15304 int phymask;
15210 15305
15211 15306 /*
15212 15307 * Get the physical port associated to the iport
15213 15308 * PHYMASK TODO
15214 15309 */
15215 15310 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
15216 15311 "phymask", 0);
15217 15312 /*
15218 15313 * Find the smp node in hash table with specified sas address and
15219 15314 * physical port
15220 15315 */
15221 15316 psmp = mptsas_wwid_to_psmp(mpt, phymask, sas_wwn);
15222 15317 if (psmp == NULL) {
15223 15318 return (DDI_FAILURE);
15224 15319 }
15225 15320
15226 15321 rval = mptsas_online_smp(pdip, psmp, smp_dip);
15227 15322
15228 15323 return (rval);
15229 15324 }
15230 15325
15231 15326 static int
15232 15327 mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
15233 15328 dev_info_t **smp_dip)
15234 15329 {
15235 15330 char wwn_str[MPTSAS_WWN_STRLEN];
15236 15331 char attached_wwn_str[MPTSAS_WWN_STRLEN];
15237 15332 int ndi_rtn = NDI_FAILURE;
15238 15333 int rval = 0;
15239 15334 mptsas_smp_t dev_info;
15240 15335 uint32_t page_address;
15241 15336 mptsas_t *mpt = DIP2MPT(pdip);
15242 15337 uint16_t dev_hdl;
15243 15338 uint64_t sas_wwn;
15244 15339 uint64_t smp_sas_wwn;
15245 15340 uint8_t physport;
15246 15341 uint8_t phy_id;
15247 15342 uint16_t pdev_hdl;
15248 15343 uint8_t numphys = 0;
15249 15344 uint16_t i = 0;
15250 15345 char phymask[MPTSAS_MAX_PHYS];
15251 15346 char *iport = NULL;
15252 15347 mptsas_phymask_t phy_mask = 0;
15253 15348 uint16_t attached_devhdl;
15254 15349 uint16_t bay_num, enclosure;
15255 15350
15256 15351 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_sasaddr);
15257 15352
15258 15353 /*
15259 15354 * Probe smp device, prevent the node of removed device from being
15260 15355 * configured succesfully
15261 15356 */
15262 15357 if (mptsas_probe_smp(pdip, smp_node->m_sasaddr) != NDI_SUCCESS) {
15263 15358 return (DDI_FAILURE);
15264 15359 }
15265 15360
15266 15361 if ((*smp_dip = mptsas_find_smp_child(pdip, wwn_str)) != NULL) {
15267 15362 return (DDI_SUCCESS);
15268 15363 }
15269 15364
15270 15365 ndi_rtn = ndi_devi_alloc(pdip, "smp", DEVI_SID_NODEID, smp_dip);
15271 15366
15272 15367 /*
15273 15368 * if lun alloc success, set props
15274 15369 */
15275 15370 if (ndi_rtn == NDI_SUCCESS) {
15276 15371 /*
15277 15372 * Set the flavor of the child to be SMP flavored
15278 15373 */
15279 15374 ndi_flavor_set(*smp_dip, SCSA_FLAVOR_SMP);
15280 15375
15281 15376 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15282 15377 *smp_dip, SMP_WWN, wwn_str) !=
15283 15378 DDI_PROP_SUCCESS) {
15284 15379 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15285 15380 "property for smp device %s (sas_wwn)",
15286 15381 wwn_str);
15287 15382 ndi_rtn = NDI_FAILURE;
15288 15383 goto smp_create_done;
15289 15384 }
15290 15385 (void) sprintf(wwn_str, "w%"PRIx64, smp_node->m_sasaddr);
15291 15386 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15292 15387 *smp_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str) !=
15293 15388 DDI_PROP_SUCCESS) {
15294 15389 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15295 15390 "property for iport target-port %s (sas_wwn)",
15296 15391 wwn_str);
15297 15392 ndi_rtn = NDI_FAILURE;
15298 15393 goto smp_create_done;
15299 15394 }
15300 15395
15301 15396 mutex_enter(&mpt->m_mutex);
15302 15397
15303 15398 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL &
15304 15399 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | smp_node->m_devhdl;
15305 15400 rval = mptsas_get_sas_expander_page0(mpt, page_address,
15306 15401 &dev_info);
15307 15402 if (rval != DDI_SUCCESS) {
15308 15403 mutex_exit(&mpt->m_mutex);
15309 15404 mptsas_log(mpt, CE_WARN,
15310 15405 "mptsas unable to get expander "
15311 15406 "parent device info for %x", page_address);
15312 15407 ndi_rtn = NDI_FAILURE;
15313 15408 goto smp_create_done;
15314 15409 }
15315 15410
15316 15411 smp_node->m_pdevhdl = dev_info.m_pdevhdl;
15317 15412 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15318 15413 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
15319 15414 (uint32_t)dev_info.m_pdevhdl;
15320 15415 rval = mptsas_get_sas_device_page0(mpt, page_address,
15321 15416 &dev_hdl, &sas_wwn, &smp_node->m_pdevinfo,
15322 15417 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure);
15323 15418 if (rval != DDI_SUCCESS) {
15324 15419 mutex_exit(&mpt->m_mutex);
15325 15420 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
15326 15421 "device info for %x", page_address);
15327 15422 ndi_rtn = NDI_FAILURE;
15328 15423 goto smp_create_done;
15329 15424 }
15330 15425
15331 15426 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15332 15427 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
15333 15428 (uint32_t)dev_info.m_devhdl;
15334 15429 rval = mptsas_get_sas_device_page0(mpt, page_address,
15335 15430 &dev_hdl, &smp_sas_wwn, &smp_node->m_deviceinfo,
15336 15431 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure);
15337 15432 if (rval != DDI_SUCCESS) {
15338 15433 mutex_exit(&mpt->m_mutex);
15339 15434 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
15340 15435 "device info for %x", page_address);
15341 15436 ndi_rtn = NDI_FAILURE;
15342 15437 goto smp_create_done;
15343 15438 }
15344 15439 mutex_exit(&mpt->m_mutex);
15345 15440
15346 15441 /*
15347 15442 * If this smp direct attached to the controller
15348 15443 * set the attached-port to the base wwid
15349 15444 */
15350 15445 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
15351 15446 != DEVINFO_DIRECT_ATTACHED) {
15352 15447 (void) sprintf(attached_wwn_str, "w%016"PRIx64,
15353 15448 sas_wwn);
15354 15449 } else {
15355 15450 (void) sprintf(attached_wwn_str, "w%016"PRIx64,
15356 15451 mpt->un.m_base_wwid);
15357 15452 }
15358 15453
15359 15454 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15360 15455 *smp_dip, SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwn_str) !=
15361 15456 DDI_PROP_SUCCESS) {
15362 15457 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15363 15458 "property for smp attached-port %s (sas_wwn)",
15364 15459 attached_wwn_str);
15365 15460 ndi_rtn = NDI_FAILURE;
15366 15461 goto smp_create_done;
15367 15462 }
15368 15463
15369 15464 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
15370 15465 *smp_dip, SMP_PROP) != DDI_PROP_SUCCESS) {
15371 15466 mptsas_log(mpt, CE_WARN, "mptsas unable to "
15372 15467 "create property for SMP %s (SMP_PROP) ",
15373 15468 wwn_str);
15374 15469 ndi_rtn = NDI_FAILURE;
15375 15470 goto smp_create_done;
15376 15471 }
15377 15472
15378 15473 /*
15379 15474 * check the smp to see whether it direct
15380 15475 * attached to the controller
15381 15476 */
15382 15477 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
15383 15478 != DEVINFO_DIRECT_ATTACHED) {
15384 15479 goto smp_create_done;
15385 15480 }
15386 15481 numphys = ddi_prop_get_int(DDI_DEV_T_ANY, pdip,
15387 15482 DDI_PROP_DONTPASS, MPTSAS_NUM_PHYS, -1);
15388 15483 if (numphys > 0) {
15389 15484 goto smp_create_done;
15390 15485 }
15391 15486 /*
15392 15487 * this iport is an old iport, we need to
15393 15488 * reconfig the props for it.
15394 15489 */
15395 15490 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip,
15396 15491 MPTSAS_VIRTUAL_PORT, 0) !=
15397 15492 DDI_PROP_SUCCESS) {
15398 15493 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
15399 15494 MPTSAS_VIRTUAL_PORT);
15400 15495 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
15401 15496 "prop update failed");
15402 15497 goto smp_create_done;
15403 15498 }
15404 15499
15405 15500 mutex_enter(&mpt->m_mutex);
15406 15501 numphys = 0;
15407 15502 iport = ddi_get_name_addr(pdip);
15408 15503 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
15409 15504 bzero(phymask, sizeof (phymask));
15410 15505 (void) sprintf(phymask,
15411 15506 "%x", mpt->m_phy_info[i].phy_mask);
15412 15507 if (strcmp(phymask, iport) == 0) {
15413 15508 phy_mask = mpt->m_phy_info[i].phy_mask;
15414 15509 break;
15415 15510 }
15416 15511 }
15417 15512
15418 15513 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
15419 15514 if ((phy_mask >> i) & 0x01) {
15420 15515 numphys++;
15421 15516 }
15422 15517 }
15423 15518 /*
15424 15519 * Update PHY info for smhba
15425 15520 */
15426 15521 if (mptsas_smhba_phy_init(mpt)) {
15427 15522 mutex_exit(&mpt->m_mutex);
15428 15523 mptsas_log(mpt, CE_WARN, "mptsas phy update "
15429 15524 "failed");
15430 15525 goto smp_create_done;
15431 15526 }
15432 15527 mutex_exit(&mpt->m_mutex);
15433 15528
15434 15529 mptsas_smhba_set_phy_props(mpt, iport, pdip,
15435 15530 numphys, &attached_devhdl);
15436 15531
15437 15532 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip,
15438 15533 MPTSAS_NUM_PHYS, numphys) !=
15439 15534 DDI_PROP_SUCCESS) {
15440 15535 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
15441 15536 MPTSAS_NUM_PHYS);
15442 15537 mptsas_log(mpt, CE_WARN, "mptsas update "
15443 15538 "num phys props failed");
15444 15539 goto smp_create_done;
15445 15540 }
15446 15541 /*
15447 15542 * Add parent's props for SMHBA support
15448 15543 */
15449 15544 if (ddi_prop_update_string(DDI_DEV_T_NONE, pdip,
15450 15545 SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
15451 15546 DDI_PROP_SUCCESS) {
15452 15547 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
15453 15548 SCSI_ADDR_PROP_ATTACHED_PORT);
15454 15549 mptsas_log(mpt, CE_WARN, "mptsas update iport"
15455 15550 "attached-port failed");
15456 15551 goto smp_create_done;
15457 15552 }
15458 15553
15459 15554 smp_create_done:
15460 15555 /*
15461 15556 * If props were setup ok, online the lun
15462 15557 */
15463 15558 if (ndi_rtn == NDI_SUCCESS) {
15464 15559 /*
15465 15560 * Try to online the new node
15466 15561 */
15467 15562 ndi_rtn = ndi_devi_online(*smp_dip, NDI_ONLINE_ATTACH);
15468 15563 }
15469 15564
15470 15565 /*
15471 15566 * If success set rtn flag, else unwire alloc'd lun
15472 15567 */
15473 15568 if (ndi_rtn != NDI_SUCCESS) {
15474 15569 NDBG12(("mptsas unable to online "
15475 15570 "SMP target %s", wwn_str));
15476 15571 ndi_prop_remove_all(*smp_dip);
15477 15572 (void) ndi_devi_free(*smp_dip);
15478 15573 }
15479 15574 }
15480 15575
15481 15576 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
15482 15577 }
15483 15578
15484 15579 /* smp transport routine */
15485 15580 static int mptsas_smp_start(struct smp_pkt *smp_pkt)
15486 15581 {
15487 15582 uint64_t wwn;
15488 15583 Mpi2SmpPassthroughRequest_t req;
15489 15584 Mpi2SmpPassthroughReply_t rep;
15490 15585 uint32_t direction = 0;
15491 15586 mptsas_t *mpt;
15492 15587 int ret;
15493 15588 uint64_t tmp64;
15494 15589
15495 15590 mpt = (mptsas_t *)smp_pkt->smp_pkt_address->
15496 15591 smp_a_hba_tran->smp_tran_hba_private;
15497 15592
15498 15593 bcopy(smp_pkt->smp_pkt_address->smp_a_wwn, &wwn, SAS_WWN_BYTE_SIZE);
15499 15594 /*
15500 15595 * Need to compose a SMP request message
15501 15596 * and call mptsas_do_passthru() function
15502 15597 */
15503 15598 bzero(&req, sizeof (req));
15504 15599 bzero(&rep, sizeof (rep));
15505 15600 req.PassthroughFlags = 0;
15506 15601 req.PhysicalPort = 0xff;
15507 15602 req.ChainOffset = 0;
15508 15603 req.Function = MPI2_FUNCTION_SMP_PASSTHROUGH;
15509 15604
15510 15605 if ((smp_pkt->smp_pkt_reqsize & 0xffff0000ul) != 0) {
15511 15606 smp_pkt->smp_pkt_reason = ERANGE;
15512 15607 return (DDI_FAILURE);
15513 15608 }
15514 15609 req.RequestDataLength = LE_16((uint16_t)(smp_pkt->smp_pkt_reqsize - 4));
15515 15610
15516 15611 req.MsgFlags = 0;
15517 15612 tmp64 = LE_64(wwn);
15518 15613 bcopy(&tmp64, &req.SASAddress, SAS_WWN_BYTE_SIZE);
15519 15614 if (smp_pkt->smp_pkt_rspsize > 0) {
15520 15615 direction |= MPTSAS_PASS_THRU_DIRECTION_READ;
15521 15616 }
15522 15617 if (smp_pkt->smp_pkt_reqsize > 0) {
15523 15618 direction |= MPTSAS_PASS_THRU_DIRECTION_WRITE;
15524 15619 }
15525 15620
15526 15621 mutex_enter(&mpt->m_mutex);
15527 15622 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep,
15528 15623 (uint8_t *)smp_pkt->smp_pkt_rsp,
15529 15624 offsetof(Mpi2SmpPassthroughRequest_t, SGL), sizeof (rep),
15530 15625 smp_pkt->smp_pkt_rspsize - 4, direction,
15531 15626 (uint8_t *)smp_pkt->smp_pkt_req, smp_pkt->smp_pkt_reqsize - 4,
15532 15627 smp_pkt->smp_pkt_timeout, FKIOCTL);
15533 15628 mutex_exit(&mpt->m_mutex);
15534 15629 if (ret != 0) {
15535 15630 cmn_err(CE_WARN, "smp_start do passthru error %d", ret);
15536 15631 smp_pkt->smp_pkt_reason = (uchar_t)(ret);
15537 15632 return (DDI_FAILURE);
15538 15633 }
15539 15634 /* do passthrough success, check the smp status */
15540 15635 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
15541 15636 switch (LE_16(rep.IOCStatus)) {
15542 15637 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
15543 15638 smp_pkt->smp_pkt_reason = ENODEV;
15544 15639 break;
15545 15640 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
15546 15641 smp_pkt->smp_pkt_reason = EOVERFLOW;
15547 15642 break;
15548 15643 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
15549 15644 smp_pkt->smp_pkt_reason = EIO;
15550 15645 break;
15551 15646 default:
15552 15647 mptsas_log(mpt, CE_NOTE, "smp_start: get unknown ioc"
15553 15648 "status:%x", LE_16(rep.IOCStatus));
15554 15649 smp_pkt->smp_pkt_reason = EIO;
15555 15650 break;
15556 15651 }
15557 15652 return (DDI_FAILURE);
15558 15653 }
15559 15654 if (rep.SASStatus != MPI2_SASSTATUS_SUCCESS) {
15560 15655 mptsas_log(mpt, CE_NOTE, "smp_start: get error SAS status:%x",
15561 15656 rep.SASStatus);
15562 15657 smp_pkt->smp_pkt_reason = EIO;
15563 15658 return (DDI_FAILURE);
15564 15659 }
15565 15660
15566 15661 return (DDI_SUCCESS);
15567 15662 }
15568 15663
15569 15664 /*
15570 15665 * If we didn't get a match, we need to get sas page0 for each device, and
15571 15666 * untill we get a match. If failed, return NULL
15572 15667 */
15573 15668 static mptsas_target_t *
15574 15669 mptsas_phy_to_tgt(mptsas_t *mpt, int phymask, uint8_t phy)
15575 15670 {
15576 15671 int i, j = 0;
15577 15672 int rval = 0;
15578 15673 uint16_t cur_handle;
15579 15674 uint32_t page_address;
15580 15675 mptsas_target_t *ptgt = NULL;
15581 15676
15582 15677 /*
15583 15678 * PHY named device must be direct attached and attaches to
15584 15679 * narrow port, if the iport is not parent of the device which
15585 15680 * we are looking for.
15586 15681 */
15587 15682 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
15588 15683 if ((1 << i) & phymask)
15589 15684 j++;
15590 15685 }
15591 15686
15592 15687 if (j > 1)
15593 15688 return (NULL);
15594 15689
15595 15690 /*
15596 15691 * Must be a narrow port and single device attached to the narrow port
15597 15692 * So the physical port num of device which is equal to the iport's
15598 15693 * port num is the device what we are looking for.
15599 15694 */
15600 15695
15601 15696 if (mpt->m_phy_info[phy].phy_mask != phymask)
15602 15697 return (NULL);
15603 15698
15604 15699 mutex_enter(&mpt->m_mutex);
15605 15700
15606 15701 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
15607 15702 MPTSAS_HASH_FIRST);
15608 15703 while (ptgt != NULL) {
15609 15704 if ((ptgt->m_sas_wwn == 0) && (ptgt->m_phynum == phy)) {
15610 15705 mutex_exit(&mpt->m_mutex);
15611 15706 return (ptgt);
15612 15707 }
15613 15708
15614 15709 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
15615 15710 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
15616 15711 }
15617 15712
15618 15713 if (mpt->m_done_traverse_dev) {
15619 15714 mutex_exit(&mpt->m_mutex);
15620 15715 return (NULL);
15621 15716 }
15622 15717
15623 15718 /* If didn't get a match, come here */
15624 15719 cur_handle = mpt->m_dev_handle;
15625 15720 for (; ; ) {
15626 15721 ptgt = NULL;
15627 15722 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
15628 15723 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)cur_handle;
15629 15724 rval = mptsas_get_target_device_info(mpt, page_address,
15630 15725 &cur_handle, &ptgt);
15631 15726 if ((rval == DEV_INFO_FAIL_PAGE0) ||
15632 15727 (rval == DEV_INFO_FAIL_ALLOC)) {
15633 15728 break;
15634 15729 }
15635 15730 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) ||
15636 15731 (rval == DEV_INFO_PHYS_DISK)) {
15637 15732 continue;
15638 15733 }
15639 15734 mpt->m_dev_handle = cur_handle;
15640 15735
15641 15736 if ((ptgt->m_sas_wwn == 0) && (ptgt->m_phynum == phy)) {
15642 15737 break;
15643 15738 }
15644 15739 }
15645 15740
15646 15741 mutex_exit(&mpt->m_mutex);
15647 15742 return (ptgt);
15648 15743 }
15649 15744
15650 15745 /*
15651 15746 * The ptgt->m_sas_wwn contains the wwid for each disk.
15652 15747 * For Raid volumes, we need to check m_raidvol[x].m_raidwwid
15653 15748 * If we didn't get a match, we need to get sas page0 for each device, and
15654 15749 * untill we get a match
15655 15750 * If failed, return NULL
15656 15751 */
15657 15752 static mptsas_target_t *
15658 15753 mptsas_wwid_to_ptgt(mptsas_t *mpt, int phymask, uint64_t wwid)
15659 15754 {
15660 15755 int rval = 0;
15661 15756 uint16_t cur_handle;
15662 15757 uint32_t page_address;
15663 15758 mptsas_target_t *tmp_tgt = NULL;
15664 15759
15665 15760 mutex_enter(&mpt->m_mutex);
15666 15761 tmp_tgt = (struct mptsas_target *)mptsas_hash_search(
15667 15762 &mpt->m_active->m_tgttbl, wwid, phymask);
15668 15763 if (tmp_tgt != NULL) {
15669 15764 mutex_exit(&mpt->m_mutex);
15670 15765 return (tmp_tgt);
15671 15766 }
15672 15767
15673 15768 if (phymask == 0) {
15674 15769 /*
15675 15770 * It's IR volume
15676 15771 */
15677 15772 rval = mptsas_get_raid_info(mpt);
15678 15773 if (rval) {
15679 15774 tmp_tgt = (struct mptsas_target *)mptsas_hash_search(
15680 15775 &mpt->m_active->m_tgttbl, wwid, phymask);
15681 15776 }
15682 15777 mutex_exit(&mpt->m_mutex);
15683 15778 return (tmp_tgt);
15684 15779 }
15685 15780
15686 15781 if (mpt->m_done_traverse_dev) {
15687 15782 mutex_exit(&mpt->m_mutex);
15688 15783 return (NULL);
15689 15784 }
15690 15785
15691 15786 /* If didn't get a match, come here */
15692 15787 cur_handle = mpt->m_dev_handle;
15693 15788 for (; ; ) {
15694 15789 tmp_tgt = NULL;
15695 15790 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
15696 15791 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | cur_handle;
15697 15792 rval = mptsas_get_target_device_info(mpt, page_address,
15698 15793 &cur_handle, &tmp_tgt);
15699 15794 if ((rval == DEV_INFO_FAIL_PAGE0) ||
15700 15795 (rval == DEV_INFO_FAIL_ALLOC)) {
15701 15796 tmp_tgt = NULL;
15702 15797 break;
15703 15798 }
15704 15799 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) ||
15705 15800 (rval == DEV_INFO_PHYS_DISK)) {
15706 15801 continue;
15707 15802 }
15708 15803 mpt->m_dev_handle = cur_handle;
15709 15804 if ((tmp_tgt->m_sas_wwn) && (tmp_tgt->m_sas_wwn == wwid) &&
15710 15805 (tmp_tgt->m_phymask == phymask)) {
15711 15806 break;
15712 15807 }
15713 15808 }
15714 15809
15715 15810 mutex_exit(&mpt->m_mutex);
15716 15811 return (tmp_tgt);
15717 15812 }
15718 15813
15719 15814 static mptsas_smp_t *
15720 15815 mptsas_wwid_to_psmp(mptsas_t *mpt, int phymask, uint64_t wwid)
15721 15816 {
15722 15817 int rval = 0;
15723 15818 uint16_t cur_handle;
15724 15819 uint32_t page_address;
15725 15820 mptsas_smp_t smp_node, *psmp = NULL;
15726 15821
15727 15822 mutex_enter(&mpt->m_mutex);
15728 15823 psmp = (struct mptsas_smp *)mptsas_hash_search(&mpt->m_active->m_smptbl,
15729 15824 wwid, phymask);
15730 15825 if (psmp != NULL) {
15731 15826 mutex_exit(&mpt->m_mutex);
15732 15827 return (psmp);
15733 15828 }
15734 15829
15735 15830 if (mpt->m_done_traverse_smp) {
15736 15831 mutex_exit(&mpt->m_mutex);
15737 15832 return (NULL);
15738 15833 }
15739 15834
15740 15835 /* If didn't get a match, come here */
15741 15836 cur_handle = mpt->m_smp_devhdl;
15742 15837 for (; ; ) {
15743 15838 psmp = NULL;
15744 15839 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL &
15745 15840 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)cur_handle;
15746 15841 rval = mptsas_get_sas_expander_page0(mpt, page_address,
15747 15842 &smp_node);
15748 15843 if (rval != DDI_SUCCESS) {
15749 15844 break;
15750 15845 }
15751 15846 mpt->m_smp_devhdl = cur_handle = smp_node.m_devhdl;
15752 15847 psmp = mptsas_smp_alloc(&mpt->m_active->m_smptbl, &smp_node);
15753 15848 ASSERT(psmp);
15754 15849 if ((psmp->m_sasaddr) && (psmp->m_sasaddr == wwid) &&
15755 15850 (psmp->m_phymask == phymask)) {
15756 15851 break;
15757 15852 }
15758 15853 }
15759 15854
15760 15855 mutex_exit(&mpt->m_mutex);
15761 15856 return (psmp);
15762 15857 }
15763 15858
15764 15859 /* helper functions using hash */
15765 15860
15766 15861 /*
15767 15862 * Can't have duplicate entries for same devhdl,
15768 15863 * if there are invalid entries, the devhdl should be set to 0xffff
15769 15864 */
15770 15865 static void *
15771 15866 mptsas_search_by_devhdl(mptsas_hash_table_t *hashtab, uint16_t devhdl)
15772 15867 {
15773 15868 mptsas_hash_data_t *data;
15774 15869
15775 15870 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_FIRST);
15776 15871 while (data != NULL) {
15777 15872 if (data->devhdl == devhdl) {
15778 15873 break;
15779 15874 }
15780 15875 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_NEXT);
15781 15876 }
15782 15877 return (data);
15783 15878 }
15784 15879
15785 15880 mptsas_target_t *
15786 15881 mptsas_tgt_alloc(mptsas_hash_table_t *hashtab, uint16_t devhdl, uint64_t wwid,
15787 15882 uint32_t devinfo, mptsas_phymask_t phymask, uint8_t phynum, mptsas_t *mpt)
15788 15883 {
15789 15884 mptsas_target_t *tmp_tgt = NULL;
15790 15885
15791 15886 tmp_tgt = mptsas_hash_search(hashtab, wwid, phymask);
15792 15887 if (tmp_tgt != NULL) {
15793 15888 NDBG20(("Hash item already exist"));
15794 15889 tmp_tgt->m_deviceinfo = devinfo;
15795 15890 tmp_tgt->m_devhdl = devhdl;
15796 15891 return (tmp_tgt);
15797 15892 }
15798 15893 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target), KM_SLEEP);
15799 15894 if (tmp_tgt == NULL) {
15800 15895 cmn_err(CE_WARN, "Fatal, allocated tgt failed");
15801 15896 return (NULL);
15802 15897 }
15803 15898 tmp_tgt->m_devhdl = devhdl;
15804 15899 tmp_tgt->m_sas_wwn = wwid;
15805 15900 tmp_tgt->m_deviceinfo = devinfo;
15806 15901 tmp_tgt->m_phymask = phymask;
15807 15902 tmp_tgt->m_phynum = phynum;
15808 15903 /* Initialized the tgt structure */
15809 15904 tmp_tgt->m_qfull_retries = QFULL_RETRIES;
15810 15905 tmp_tgt->m_qfull_retry_interval =
15811 15906 drv_usectohz(QFULL_RETRY_INTERVAL * 1000);
15812 15907 tmp_tgt->m_t_throttle = MAX_THROTTLE;
15813 15908 mutex_init(&tmp_tgt->m_tgt_intr_mutex, NULL, MUTEX_DRIVER,
15814 15909 DDI_INTR_PRI(mpt->m_intr_pri));
15815 15910
15816 15911 mptsas_hash_add(hashtab, tmp_tgt);
15817 15912
15818 15913 return (tmp_tgt);
15819 15914 }
15820 15915
15821 15916 static void
15822 15917 mptsas_tgt_free(mptsas_hash_table_t *hashtab, uint64_t wwid,
15823 15918 mptsas_phymask_t phymask)
15824 15919 {
15825 15920 mptsas_target_t *tmp_tgt;
15826 15921 tmp_tgt = mptsas_hash_rem(hashtab, wwid, phymask);
15827 15922 if (tmp_tgt == NULL) {
15828 15923 cmn_err(CE_WARN, "Tgt not found, nothing to free");
15829 15924 } else {
15830 15925 mutex_destroy(&tmp_tgt->m_tgt_intr_mutex);
15831 15926 kmem_free(tmp_tgt, sizeof (struct mptsas_target));
15832 15927 }
15833 15928 }
15834 15929
15835 15930 /*
15836 15931 * Return the entry in the hash table
15837 15932 */
15838 15933 static mptsas_smp_t *
15839 15934 mptsas_smp_alloc(mptsas_hash_table_t *hashtab, mptsas_smp_t *data)
15840 15935 {
15841 15936 uint64_t key1 = data->m_sasaddr;
15842 15937 mptsas_phymask_t key2 = data->m_phymask;
15843 15938 mptsas_smp_t *ret_data;
15844 15939
15845 15940 ret_data = mptsas_hash_search(hashtab, key1, key2);
15846 15941 if (ret_data != NULL) {
15847 15942 bcopy(data, ret_data, sizeof (mptsas_smp_t));
15848 15943 return (ret_data);
15849 15944 }
15850 15945
15851 15946 ret_data = kmem_alloc(sizeof (mptsas_smp_t), KM_SLEEP);
15852 15947 bcopy(data, ret_data, sizeof (mptsas_smp_t));
15853 15948 mptsas_hash_add(hashtab, ret_data);
15854 15949 return (ret_data);
15855 15950 }
15856 15951
15857 15952 static void
15858 15953 mptsas_smp_free(mptsas_hash_table_t *hashtab, uint64_t wwid,
15859 15954 mptsas_phymask_t phymask)
15860 15955 {
15861 15956 mptsas_smp_t *tmp_smp;
15862 15957 tmp_smp = mptsas_hash_rem(hashtab, wwid, phymask);
15863 15958 if (tmp_smp == NULL) {
15864 15959 cmn_err(CE_WARN, "Smp element not found, nothing to free");
15865 15960 } else {
15866 15961 kmem_free(tmp_smp, sizeof (struct mptsas_smp));
15867 15962 }
15868 15963 }
15869 15964
15870 15965 /*
15871 15966 * Hash operation functions
15872 15967 * key1 is the sas_wwn, key2 is the phymask
15873 15968 */
15874 15969 static void
15875 15970 mptsas_hash_init(mptsas_hash_table_t *hashtab)
15876 15971 {
15877 15972 if (hashtab == NULL) {
15878 15973 return;
15879 15974 }
15880 15975 bzero(hashtab->head, sizeof (mptsas_hash_node_t) *
15881 15976 MPTSAS_HASH_ARRAY_SIZE);
15882 15977 hashtab->cur = NULL;
15883 15978 hashtab->line = 0;
15884 15979 }
15885 15980
15886 15981 static void
15887 15982 mptsas_hash_uninit(mptsas_hash_table_t *hashtab, size_t datalen)
15888 15983 {
15889 15984 uint16_t line = 0;
15890 15985 mptsas_hash_node_t *cur = NULL, *last = NULL;
15891 15986
15892 15987 if (hashtab == NULL) {
15893 15988 return;
15894 15989 }
15895 15990 for (line = 0; line < MPTSAS_HASH_ARRAY_SIZE; line++) {
15896 15991 cur = hashtab->head[line];
15897 15992 while (cur != NULL) {
15898 15993 last = cur;
15899 15994 cur = cur->next;
15900 15995 kmem_free(last->data, datalen);
15901 15996 kmem_free(last, sizeof (mptsas_hash_node_t));
15902 15997 }
15903 15998 }
15904 15999 }
15905 16000
15906 16001 /*
15907 16002 * You must guarantee the element doesn't exist in the hash table
15908 16003 * before you call mptsas_hash_add()
15909 16004 */
15910 16005 static void
15911 16006 mptsas_hash_add(mptsas_hash_table_t *hashtab, void *data)
15912 16007 {
15913 16008 uint64_t key1 = ((mptsas_hash_data_t *)data)->key1;
15914 16009 mptsas_phymask_t key2 = ((mptsas_hash_data_t *)data)->key2;
15915 16010 mptsas_hash_node_t **head = NULL;
15916 16011 mptsas_hash_node_t *node = NULL;
15917 16012
15918 16013 if (hashtab == NULL) {
15919 16014 return;
15920 16015 }
15921 16016 ASSERT(mptsas_hash_search(hashtab, key1, key2) == NULL);
15922 16017 node = kmem_zalloc(sizeof (mptsas_hash_node_t), KM_NOSLEEP);
15923 16018 node->data = data;
15924 16019
15925 16020 head = &(hashtab->head[key1 % MPTSAS_HASH_ARRAY_SIZE]);
15926 16021 if (*head == NULL) {
15927 16022 *head = node;
15928 16023 } else {
15929 16024 node->next = *head;
15930 16025 *head = node;
15931 16026 }
15932 16027 }
15933 16028
15934 16029 static void *
15935 16030 mptsas_hash_rem(mptsas_hash_table_t *hashtab, uint64_t key1,
15936 16031 mptsas_phymask_t key2)
15937 16032 {
15938 16033 mptsas_hash_node_t **head = NULL;
15939 16034 mptsas_hash_node_t *last = NULL, *cur = NULL;
15940 16035 mptsas_hash_data_t *data;
15941 16036 if (hashtab == NULL) {
15942 16037 return (NULL);
15943 16038 }
15944 16039 head = &(hashtab->head[key1 % MPTSAS_HASH_ARRAY_SIZE]);
15945 16040 cur = *head;
15946 16041 while (cur != NULL) {
15947 16042 data = cur->data;
15948 16043 if ((data->key1 == key1) && (data->key2 == key2)) {
15949 16044 if (last == NULL) {
15950 16045 (*head) = cur->next;
15951 16046 } else {
15952 16047 last->next = cur->next;
15953 16048 }
15954 16049 kmem_free(cur, sizeof (mptsas_hash_node_t));
15955 16050 return (data);
15956 16051 } else {
15957 16052 last = cur;
15958 16053 cur = cur->next;
15959 16054 }
15960 16055 }
15961 16056 return (NULL);
15962 16057 }
15963 16058
15964 16059 static void *
15965 16060 mptsas_hash_search(mptsas_hash_table_t *hashtab, uint64_t key1,
15966 16061 mptsas_phymask_t key2)
15967 16062 {
15968 16063 mptsas_hash_node_t *cur = NULL;
15969 16064 mptsas_hash_data_t *data;
15970 16065 if (hashtab == NULL) {
15971 16066 return (NULL);
15972 16067 }
15973 16068 cur = hashtab->head[key1 % MPTSAS_HASH_ARRAY_SIZE];
15974 16069 while (cur != NULL) {
15975 16070 data = cur->data;
15976 16071 if ((data->key1 == key1) && (data->key2 == key2)) {
15977 16072 return (data);
15978 16073 } else {
15979 16074 cur = cur->next;
15980 16075 }
15981 16076 }
15982 16077 return (NULL);
15983 16078 }
15984 16079
15985 16080 static void *
15986 16081 mptsas_hash_traverse(mptsas_hash_table_t *hashtab, int pos)
15987 16082 {
15988 16083 mptsas_hash_node_t *this = NULL;
15989 16084
15990 16085 if (hashtab == NULL) {
15991 16086 return (NULL);
15992 16087 }
15993 16088
15994 16089 if (pos == MPTSAS_HASH_FIRST) {
15995 16090 hashtab->line = 0;
15996 16091 hashtab->cur = NULL;
15997 16092 this = hashtab->head[0];
15998 16093 } else {
15999 16094 if (hashtab->cur == NULL) {
16000 16095 return (NULL);
16001 16096 } else {
16002 16097 this = hashtab->cur->next;
16003 16098 }
16004 16099 }
16005 16100
16006 16101 while (this == NULL) {
16007 16102 hashtab->line++;
16008 16103 if (hashtab->line >= MPTSAS_HASH_ARRAY_SIZE) {
16009 16104 /* the traverse reaches the end */
16010 16105 hashtab->cur = NULL;
16011 16106 return (NULL);
16012 16107 } else {
16013 16108 this = hashtab->head[hashtab->line];
16014 16109 }
16015 16110 }
16016 16111 hashtab->cur = this;
16017 16112 return (this->data);
16018 16113 }
16019 16114
16020 16115 /*
16021 16116 * Functions for SGPIO LED support
16022 16117 */
16023 16118 static dev_info_t *
16024 16119 mptsas_get_dip_from_dev(dev_t dev, mptsas_phymask_t *phymask)
16025 16120 {
16026 16121 dev_info_t *dip;
16027 16122 int prop;
16028 16123 dip = e_ddi_hold_devi_by_dev(dev, 0);
16029 16124 if (dip == NULL)
16030 16125 return (dip);
16031 16126 prop = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
16032 16127 "phymask", 0);
16033 16128 *phymask = (mptsas_phymask_t)prop;
16034 16129 ddi_release_devi(dip);
16035 16130 return (dip);
16036 16131 }
16037 16132 static mptsas_target_t *
16038 16133 mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr, mptsas_phymask_t phymask)
16039 16134 {
16040 16135 uint8_t phynum;
16041 16136 uint64_t wwn;
16042 16137 int lun;
16043 16138 mptsas_target_t *ptgt = NULL;
16044 16139
16045 16140 if (mptsas_parse_address(addr, &wwn, &phynum, &lun) != DDI_SUCCESS) {
16046 16141 return (NULL);
16047 16142 }
16048 16143 if (addr[0] == 'w') {
16049 16144 ptgt = mptsas_wwid_to_ptgt(mpt, (int)phymask, wwn);
16050 16145 } else {
16051 16146 ptgt = mptsas_phy_to_tgt(mpt, (int)phymask, phynum);
16052 16147 }
16053 16148 return (ptgt);
16054 16149 }
16055 16150
16056 16151 #ifdef MPTSAS_GET_LED
16057 16152 static int
16058 16153 mptsas_get_led_status(mptsas_t *mpt, mptsas_target_t *ptgt,
16059 16154 uint32_t *slotstatus)
16060 16155 {
16061 16156 return (mptsas_send_sep(mpt, ptgt, slotstatus,
16062 16157 MPI2_SEP_REQ_ACTION_READ_STATUS));
16063 16158 }
16064 16159 #endif
16065 16160 static int
16066 16161 mptsas_set_led_status(mptsas_t *mpt, mptsas_target_t *ptgt, uint32_t slotstatus)
16067 16162 {
16068 16163 NDBG14(("mptsas_ioctl: set LED status %x for slot %x",
16069 16164 slotstatus, ptgt->m_slot_num));
16070 16165 return (mptsas_send_sep(mpt, ptgt, &slotstatus,
16071 16166 MPI2_SEP_REQ_ACTION_WRITE_STATUS));
16072 16167 }
16073 16168 /*
16074 16169 * send sep request, use enclosure/slot addressing
16075 16170 */
16076 16171 static int mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt,
16077 16172 uint32_t *status, uint8_t act)
16078 16173 {
16079 16174 Mpi2SepRequest_t req;
16080 16175 Mpi2SepReply_t rep;
16081 16176 int ret;
16082 16177
16083 16178 ASSERT(mutex_owned(&mpt->m_mutex));
16084 16179
16085 16180 bzero(&req, sizeof (req));
16086 16181 bzero(&rep, sizeof (rep));
16087 16182
16088 16183 /* Do nothing for RAID volumes */
16089 16184 if (ptgt->m_phymask == 0) {
16090 16185 NDBG14(("mptsas_send_sep: Skip RAID volumes"));
16091 16186 return (DDI_FAILURE);
16092 16187 }
16093 16188
16094 16189 req.Function = MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR;
16095 16190 req.Action = act;
16096 16191 req.Flags = MPI2_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS;
16097 16192 req.EnclosureHandle = LE_16(ptgt->m_enclosure);
16098 16193 req.Slot = LE_16(ptgt->m_slot_num);
16099 16194 if (act == MPI2_SEP_REQ_ACTION_WRITE_STATUS) {
16100 16195 req.SlotStatus = LE_32(*status);
16101 16196 }
16102 16197 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL,
16103 16198 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL);
16104 16199 if (ret != 0) {
16105 16200 mptsas_log(mpt, CE_NOTE, "mptsas_send_sep: passthru SEP "
16106 16201 "Processor Request message error %d", ret);
16107 16202 return (DDI_FAILURE);
16108 16203 }
16109 16204 /* do passthrough success, check the ioc status */
16110 16205 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
16111 16206 if ((LE_16(rep.IOCStatus) & MPI2_IOCSTATUS_MASK) ==
16112 16207 MPI2_IOCSTATUS_INVALID_FIELD) {
16113 16208 mptsas_log(mpt, CE_NOTE, "send sep act %x: Not "
16114 16209 "supported action, loginfo %x", act,
16115 16210 LE_32(rep.IOCLogInfo));
16116 16211 return (DDI_FAILURE);
16117 16212 }
16118 16213 mptsas_log(mpt, CE_NOTE, "send_sep act %x: ioc "
16119 16214 "status:%x", act, LE_16(rep.IOCStatus));
16120 16215 return (DDI_FAILURE);
16121 16216 }
16122 16217 if (act != MPI2_SEP_REQ_ACTION_WRITE_STATUS) {
16123 16218 *status = LE_32(rep.SlotStatus);
16124 16219 }
16125 16220
16126 16221 return (DDI_SUCCESS);
16127 16222 }
16128 16223
16129 16224 int
16130 16225 mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr,
16131 16226 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp,
16132 16227 uint32_t alloc_size, ddi_dma_cookie_t *cookiep)
16133 16228 {
16134 16229 ddi_dma_cookie_t new_cookie;
16135 16230 size_t alloc_len;
16136 16231 uint_t ncookie;
16137 16232
16138 16233 if (cookiep == NULL)
16139 16234 cookiep = &new_cookie;
16140 16235
16141 16236 if (ddi_dma_alloc_handle(mpt->m_dip, &dma_attr, DDI_DMA_SLEEP,
16142 16237 NULL, dma_hdp) != DDI_SUCCESS) {
16143 16238 dma_hdp = NULL;
16144 16239 return (FALSE);
16145 16240 }
16146 16241
16147 16242 if (ddi_dma_mem_alloc(*dma_hdp, alloc_size, &mpt->m_dev_acc_attr,
16148 16243 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, dma_memp, &alloc_len,
16149 16244 acc_hdp) != DDI_SUCCESS) {
16150 16245 ddi_dma_free_handle(dma_hdp);
16151 16246 dma_hdp = NULL;
16152 16247 return (FALSE);
16153 16248 }
16154 16249
16155 16250 if (ddi_dma_addr_bind_handle(*dma_hdp, NULL, *dma_memp, alloc_len,
16156 16251 (DDI_DMA_RDWR | DDI_DMA_CONSISTENT), DDI_DMA_SLEEP, NULL,
16157 16252 cookiep, &ncookie) != DDI_DMA_MAPPED) {
16158 16253 (void) ddi_dma_mem_free(acc_hdp);
16159 16254 ddi_dma_free_handle(dma_hdp);
16160 16255 dma_hdp = NULL;
16161 16256 return (FALSE);
16162 16257 }
16163 16258
16164 16259 return (TRUE);
16165 16260 }
16166 16261
16167 16262 void
16168 16263 mptsas_dma_addr_destroy(ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp)
16169 16264 {
16170 16265 if (*dma_hdp == NULL)
16171 16266 return;
16172 16267
16173 16268 (void) ddi_dma_unbind_handle(*dma_hdp);
16174 16269 (void) ddi_dma_mem_free(acc_hdp);
16175 16270 ddi_dma_free_handle(dma_hdp);
16176 16271 dma_hdp = NULL;
16177 16272 }
16178 16273
16179 16274 static int
16180 16275 mptsas_outstanding_cmds_n(mptsas_t *mpt)
16181 16276 {
16182 16277 int n = 0, i;
16183 16278 for (i = 0; i < mpt->m_slot_freeq_pair_n; i++) {
16184 16279 mutex_enter(&mpt->m_slot_freeq_pairp[i].
16185 16280 m_slot_allocq.s.m_fq_mutex);
16186 16281 mutex_enter(&mpt->m_slot_freeq_pairp[i].
16187 16282 m_slot_releq.s.m_fq_mutex);
16188 16283 n += (mpt->m_slot_freeq_pairp[i].m_slot_allocq.s.m_fq_n_init -
16189 16284 mpt->m_slot_freeq_pairp[i].m_slot_allocq.s.m_fq_n -
16190 16285 mpt->m_slot_freeq_pairp[i].m_slot_releq.s.m_fq_n);
16191 16286 mutex_exit(&mpt->m_slot_freeq_pairp[i].
16192 16287 m_slot_releq.s.m_fq_mutex);
16193 16288 mutex_exit(&mpt->m_slot_freeq_pairp[i].
16194 16289 m_slot_allocq.s.m_fq_mutex);
16195 16290 }
16196 16291 if (mpt->m_max_requests - 2 < n)
16197 16292 panic("mptsas: free slot allocq and releq crazy");
16198 16293 return (n);
16199 16294 }
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