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--- old/usr/src/lib/libdisasm/sparc/dis_sparc_fmt.c
+++ new/usr/src/lib/libdisasm/common/dis_sparc_fmt.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
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20 20 */
21 21
22 22 /*
23 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
24 24 * Use is subject to license terms.
25 25 */
26 26
27 27 /*
28 28 * Copyright 2009 Jason King. All rights reserved.
29 29 * Use is subject to license terms.
30 + * Copyright 2012 Joshua M. Clulow <josh@sysmgr.org>
30 31 */
31 32
32 33
33 34 #include <sys/byteorder.h>
34 35 #include <stdarg.h>
35 36
36 37 #if !defined(DIS_STANDALONE)
37 38 #include <stdio.h>
38 39 #endif /* DIS_STANDALONE */
39 40
40 41 #include "libdisasm.h"
41 42 #include "libdisasm_impl.h"
42 43 #include "dis_sparc.h"
43 44 #include "dis_sparc_fmt.h"
44 45
45 46 extern char *strncpy(char *, const char *, size_t);
46 47 extern size_t strlen(const char *);
47 48 extern int strcmp(const char *, const char *);
48 49 extern int strncmp(const char *, const char *, size_t);
49 50 extern size_t strlcat(char *, const char *, size_t);
50 51 extern size_t strlcpy(char *, const char *, size_t);
51 52 extern int snprintf(char *, size_t, const char *, ...);
52 53 extern int vsnprintf(char *, size_t, const char *, va_list);
53 54
54 55 /*
55 56 * This file has the functions that do all the dirty work of outputting the
56 57 * disassembled instruction
57 58 *
58 59 * All the non-static functions follow the format_fcn (in dis_sparc.h):
59 60 * Input:
60 61 * disassembler handle/context
61 62 * instruction to disassemble
62 63 * instruction definition pointer (inst_t *)
63 64 * index in the table of the instruction
64 65 * Return:
65 66 * 0 Success
66 67 * !0 Invalid instruction
67 68 *
68 69 * Generally, instructions found in the same table use the same output format
69 70 * or have a few minor differences (which are described in the 'flags' field
70 71 * of the instruction definition. In some cases, certain instructions differ
71 72 * radically enough from those in the same table, that their own format
72 73 * function is used.
73 74 *
74 75 * Typically each table has a unique format function defined in this file. In
75 76 * some cases (such as branches) a common one for all the tables is used.
76 77 *
77 78 * When adding support for new instructions, it is largely a judgement call
78 79 * as to when a new format function is defined.
79 80 */
80 81
81 82 /* The various instruction formats of a sparc instruction */
82 83
83 84 #if defined(_BIT_FIELDS_HTOL)
84 85 typedef struct format1 {
85 86 uint32_t op:2;
86 87 uint32_t disp30:30;
87 88 } format1_t;
88 89 #elif defined(_BIT_FIELDS_LTOH)
89 90 typedef struct format1 {
90 91 uint32_t disp30:30;
91 92 uint32_t op:2;
92 93 } format1_t;
93 94 #else
94 95 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
95 96 #endif
96 97
97 98 #if defined(_BIT_FIELDS_HTOL)
98 99 typedef struct format2 {
99 100 uint32_t op:2;
100 101 uint32_t rd:5;
101 102 uint32_t op2:3;
102 103 uint32_t imm22:22;
103 104 } format2_t;
104 105 #elif defined(_BIT_FIELDS_LTOH)
105 106 typedef struct format2 {
106 107 uint32_t imm22:22;
107 108 uint32_t op2:3;
108 109 uint32_t rd:5;
109 110 uint32_t op:2;
110 111 } format2_t;
111 112 #else
112 113 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
113 114 #endif
114 115
115 116 #if defined(_BIT_FIELDS_HTOL)
116 117 typedef struct format2a {
117 118 uint32_t op:2;
118 119 uint32_t a:1;
119 120 uint32_t cond:4;
120 121 uint32_t op2:3;
121 122 uint32_t disp22:22;
122 123 } format2a_t;
123 124 #elif defined(_BIT_FIELDS_LTOH)
124 125 typedef struct format2a {
125 126 uint32_t disp22:22;
126 127 uint32_t op2:3;
127 128 uint32_t cond:4;
128 129 uint32_t a:1;
129 130 uint32_t op:2;
130 131 } format2a_t;
131 132 #else
132 133 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
133 134 #endif
134 135
135 136 #if defined(_BIT_FIELDS_HTOL)
136 137 typedef struct format2b {
137 138 uint32_t op:2;
138 139 uint32_t a:1;
139 140 uint32_t cond:4;
140 141 uint32_t op2:3;
141 142 uint32_t cc:2;
142 143 uint32_t p:1;
143 144 uint32_t disp19:19;
144 145 } format2b_t;
145 146 #elif defined(_BIT_FIELDS_LTOH)
146 147 typedef struct format2b {
147 148 uint32_t disp19:19;
148 149 uint32_t p:1;
149 150 uint32_t cc:2;
150 151 uint32_t op2:3;
151 152 uint32_t cond:4;
152 153 uint32_t a:1;
153 154 uint32_t op:2;
154 155 } format2b_t;
155 156 #else
156 157 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
157 158 #endif
158 159
159 160 #if defined(_BIT_FIELDS_HTOL)
160 161 typedef struct format2c {
161 162 uint32_t op:2;
162 163 uint32_t a:1;
163 164 uint32_t cond:4;
164 165 uint32_t op2:3;
165 166 uint32_t d16hi:2;
166 167 uint32_t p:1;
167 168 uint32_t rs1:5;
168 169 uint32_t d16lo:14;
169 170 } format2c_t;
170 171 #elif defined(_BIT_FIELDS_LTOH)
171 172 typedef struct format2c {
172 173 uint32_t d16lo:14;
173 174 uint32_t rs1:5;
174 175 uint32_t p:1;
175 176 uint32_t d16hi:2;
176 177 uint32_t op2:3;
177 178 uint32_t cond:4;
178 179 uint32_t a:1;
179 180 uint32_t op:2;
180 181 } format2c_t;
181 182 #else
182 183 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
183 184 #endif
184 185
185 186 #if defined(_BIT_FIELDS_HTOL)
186 187 typedef struct format3 {
187 188 uint32_t op:2;
188 189 uint32_t rd:5;
189 190 uint32_t op3:6;
190 191 uint32_t rs1:5;
191 192 uint32_t i:1;
192 193 uint32_t asi:8;
193 194 uint32_t rs2:5;
194 195 } format3_t;
195 196 #elif defined(_BIT_FIELDS_LTOH)
196 197 typedef struct format3 {
197 198 uint32_t rs2:5;
198 199 uint32_t asi:8;
199 200 uint32_t i:1;
200 201 uint32_t rs1:5;
201 202 uint32_t op3:6;
202 203 uint32_t rd:5;
203 204 uint32_t op:2;
204 205 } format3_t;
205 206 #else
206 207 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
207 208 #endif
208 209
209 210 #if defined(_BIT_FIELDS_HTOL)
210 211 typedef struct format3a {
211 212 uint32_t op:2;
212 213 uint32_t rd:5;
213 214 uint32_t op3:6;
214 215 uint32_t rs1:5;
215 216 uint32_t i:1;
216 217 uint32_t simm13:13;
217 218 } format3a_t;
218 219 #elif defined(_BIT_FIELDS_LTOH)
219 220 typedef struct format3a {
220 221 uint32_t simm13:13;
221 222 uint32_t i:1;
222 223 uint32_t rs1:5;
223 224 uint32_t op3:6;
224 225 uint32_t rd:5;
225 226 uint32_t op:2;
226 227 } format3a_t;
227 228 #else
228 229 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
229 230 #endif
230 231
231 232 #if defined(_BIT_FIELDS_HTOL)
232 233 typedef struct format3b {
233 234 uint32_t op:2;
234 235 uint32_t rd:5;
235 236 uint32_t op3:6;
236 237 uint32_t rs1:5;
237 238 uint32_t i:1;
238 239 uint32_t x:1;
239 240 uint32_t undef:6;
240 241 uint32_t shcnt:6;
241 242 } format3b_t;
242 243 #elif defined(_BIT_FIELDS_LTOH)
243 244 typedef struct format3b {
244 245 uint32_t shcnt:6;
245 246 uint32_t undef:6;
246 247 uint32_t x:1;
247 248 uint32_t i:1;
248 249 uint32_t rs1:5;
249 250 uint32_t op3:6;
250 251 uint32_t rd:5;
251 252 uint32_t op:2;
252 253 } format3b_t;
253 254 #else
254 255 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
255 256 #endif
256 257
257 258 #if defined(_BIT_FIELDS_HTOL)
258 259 typedef struct format3c {
259 260 uint32_t op:2;
260 261 uint32_t rd:5;
261 262 uint32_t op3:6;
262 263 uint32_t cc2:1;
263 264 uint32_t cond:4;
264 265 uint32_t i:1;
265 266 uint32_t cc:2;
266 267 uint32_t simm11:11;
267 268 } format3c_t;
268 269 #elif defined(_BIT_FIELDS_LTOH)
269 270 typedef struct format3c {
270 271 uint32_t simm11:11;
271 272 uint32_t cc:2;
272 273 uint32_t i:1;
273 274 uint32_t cond:4;
274 275 uint32_t cc2:1;
275 276 uint32_t op3:6;
276 277 uint32_t rd:5;
277 278 uint32_t op:2;
278 279 } format3c_t;
279 280 #else
280 281 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
281 282 #endif
282 283
283 284 #if defined(_BIT_FIELDS_HTOL)
284 285 typedef struct format3d {
285 286 uint32_t op:2;
286 287 uint32_t rd:5;
287 288 uint32_t op3:6;
288 289 uint32_t rs1:5;
289 290 uint32_t i:1;
290 291 uint32_t rcond:3;
291 292 uint32_t simm10:10;
292 293 } format3d_t;
293 294 #elif defined(_BIT_FIELDS_LTOH)
294 295 typedef struct format3d {
295 296 uint32_t simm10:10;
296 297 uint32_t rcond:3;
297 298 uint32_t i:1;
298 299 uint32_t rs1:5;
299 300 uint32_t op3:6;
300 301 uint32_t rd:5;
301 302 uint32_t op:2;
302 303 } format3d_t;
303 304 #else
304 305 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
305 306 #endif
306 307
307 308 #if defined(_BIT_FIELDS_HTOL)
308 309 typedef struct formatcp {
309 310 uint32_t op:2;
310 311 uint32_t rd:5;
311 312 uint32_t op3:6;
312 313 uint32_t rs1:5;
313 314 uint32_t opc:9;
314 315 uint32_t rs2:5;
315 316 } formatcp_t;
316 317 #elif defined(_BIT_FIELDS_LTOH)
317 318 typedef struct formatcp {
318 319 uint32_t rs2:5;
319 320 uint32_t opc:9;
320 321 uint32_t rs1:5;
321 322 uint32_t op3:6;
322 323 uint32_t rd:5;
323 324 uint32_t op:2;
324 325 } formatcp_t;
325 326 #else
326 327 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
327 328 #endif
328 329
329 330 #if defined(_BIT_FIELDS_HTOL)
330 331 typedef struct formattcc {
331 332 uint32_t op:2;
332 333 uint32_t undef:1;
333 334 uint32_t cond:4;
334 335 uint32_t op3:6;
335 336 uint32_t rs1:5;
336 337 uint32_t i:1;
337 338 uint32_t cc:2;
338 339 uint32_t undef2:3;
339 340 uint32_t immtrap:8;
340 341 } formattcc_t;
341 342 #elif defined(_BIT_FIELDS_LTOH)
342 343 typedef struct formattcc {
343 344 uint32_t immtrap:8;
344 345 uint32_t undef2:3;
345 346 uint32_t cc:2;
346 347 uint32_t i:1;
347 348 uint32_t rs1:5;
348 349 uint32_t op3:6;
349 350 uint32_t cond:4;
350 351 uint32_t undef:1;
351 352 uint32_t op:2;
352 353 } formattcc_t;
353 354 #else
354 355 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
355 356 #endif
356 357
357 358 #if defined(_BIT_FIELDS_HTOL)
358 359 typedef struct formattcc2 {
359 360 uint32_t op:2;
360 361 uint32_t undef:1;
361 362 uint32_t cond:4;
362 363 uint32_t op3:6;
363 364 uint32_t rs1:5;
364 365 uint32_t i:1;
365 366 uint32_t cc:2;
366 367 uint32_t undef2:6;
367 368 uint32_t rs2:5;
368 369 } formattcc2_t;
369 370 #elif defined(_BIT_FIELDS_LTOH)
370 371 typedef struct formattcc2 {
371 372 uint32_t rs2:5;
372 373 uint32_t undef2:6;
373 374 uint32_t cc:2;
374 375 uint32_t i:1;
375 376 uint32_t rs1:5;
376 377 uint32_t op3:6;
377 378 uint32_t cond:4;
378 379 uint32_t undef:1;
379 380 uint32_t op:2;
380 381 } formattcc2_t;
381 382 #else
382 383 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
383 384 #endif
384 385
385 386 #if defined(_BIT_FIELDS_HTOL)
386 387 typedef struct formatmbr {
387 388 uint32_t op:2;
388 389 uint32_t rd:5;
389 390 uint32_t op3:6;
390 391 uint32_t rs1:5;
391 392 uint32_t i:1;
392 393 uint32_t undef:6;
393 394 uint32_t cmask:3;
394 395 uint32_t mmask:4;
395 396 } formatmbr_t;
396 397 #elif defined(_BIT_FIELDS_LTOH)
397 398 typedef struct formatmbr {
398 399 uint32_t mmask:4;
399 400 uint32_t cmask:3;
400 401 uint32_t undef:6;
401 402 uint32_t i:1;
402 403 uint32_t rs1:5;
403 404 uint32_t op3:6;
404 405 uint32_t rd:5;
405 406 uint32_t op:2;
406 407 } formatmbr_t;
407 408 #else
408 409 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
409 410 #endif
410 411
411 412 #if defined(_BIT_FIELDS_HTOL)
412 413 typedef struct formatfcmp {
413 414 uint32_t op:2;
414 415 uint32_t undef:3;
415 416 uint32_t cc:2;
416 417 uint32_t op3:6;
417 418 uint32_t rs1:5;
418 419 uint32_t opf:9;
419 420 uint32_t rs2:5;
420 421 } formatfcmp_t;
421 422 #elif defined(_BIT_FIELDS_LTOH)
422 423 typedef struct formatfcmp {
423 424 uint32_t rs2:5;
424 425 uint32_t opf:9;
425 426 uint32_t rs1:5;
426 427 uint32_t op3:6;
427 428 uint32_t cc:2;
428 429 uint32_t undef:3;
429 430 uint32_t op:2;
430 431 } formatfcmp_t;
431 432 #else
432 433 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
433 434 #endif
434 435
435 436 #if defined(_BIT_FIELDS_HTOL)
436 437 typedef struct formatfmov {
437 438 uint32_t op:2;
438 439 uint32_t rd:5;
439 440 uint32_t op3:6;
440 441 uint32_t undef:1;
441 442 uint32_t cond:4;
442 443 uint32_t cc:3;
443 444 uint32_t opf:6;
444 445 uint32_t rs2:5;
445 446 } formatfmov_t;
446 447 #elif defined(_BIT_FIELDS_LTOH)
447 448 typedef struct formatfmov {
448 449 uint32_t rs2:5;
449 450 uint32_t opf:6;
450 451 uint32_t cc:3;
451 452 uint32_t cond:4;
452 453 uint32_t undef:1;
453 454 uint32_t op3:6;
454 455 uint32_t rd:5;
455 456 uint32_t op:2;
456 457 } formatfmov_t;
457 458 #else
458 459 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
459 460 #endif
460 461
461 462 #if defined(_BIT_FIELDS_HTOL)
462 463 typedef struct formatfused {
463 464 uint32_t op:2;
464 465 uint32_t rd:5;
465 466 uint32_t op3:6;
466 467 uint32_t rs1:5;
467 468 uint32_t rs3:5;
468 469 uint32_t op5:4;
469 470 uint32_t rs2:5;
470 471 } formatfused_t;
471 472 #elif defined(_BIT_FIELDS_LTOH)
472 473 typedef struct formatfused {
473 474 uint32_t rs2:5;
474 475 uint32_t op5:4;
475 476 uint32_t rs3:5;
476 477 uint32_t rs1:5;
477 478 uint32_t op3:6;
478 479 uint32_t rd:5;
479 480 uint32_t op:2;
480 481 } formatfused_t;
481 482 #else
482 483 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
483 484 #endif
484 485
485 486 typedef union ifmt {
486 487 uint32_t i;
487 488 format1_t f1;
488 489 format2_t f2;
489 490 format2a_t f2a;
490 491 format2b_t f2b;
491 492 format2c_t f2c;
492 493 format3_t f3;
493 494 format3a_t f3a;
494 495 format3b_t f3b;
495 496 format3c_t f3c;
496 497 format3d_t f3d;
497 498 formatcp_t fcp;
498 499 formattcc_t ftcc;
499 500 formattcc2_t ftcc2;
500 501 formatfcmp_t fcmp;
501 502 formatmbr_t fmb;
502 503 formatfmov_t fmv;
503 504 formatfused_t fused;
504 505 } ifmt_t;
505 506
506 507 /* integer register names */
507 508 static const char *reg_names[32] = {
508 509 "%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7",
509 510 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7",
510 511 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7",
511 512 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7"
512 513 };
513 514
514 515 /* floating point register names */
515 516 static const char *freg_names[32] = {
516 517 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
517 518 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
518 519 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
519 520 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"
520 521 };
521 522
522 523 /* double precision register names */
523 524 static const char *fdreg_names[32] = {
524 525 "%d0", "%d32", "%d2", "%d34", "%d4", "%d36", "%d6", "%d38",
525 526 "%d8", "%d40", "%d10", "%d42", "%d12", "%d44", "%d14", "%d46",
526 527 "%d16", "%d48", "%d18", "%d50", "%d20", "%d52", "%d22", "%d54",
527 528 "%d24", "%d56", "%d26", "%d58", "%d28", "%d60", "%d30", "%d62"
528 529 };
529 530
530 531 static const char *compat_fdreg_names[32] = {
531 532 "%f0", "%f32", "%f2", "%f34", "%f4", "%f36", "%f6", "%f38",
532 533 "%f8", "%f40", "%f10", "%f42", "%f12", "%f44", "%f14", "%f46",
533 534 "%f16", "%f48", "%f18", "%f50", "%f20", "%f52", "%f22", "%f54",
534 535 "%f24", "%f56", "%f26", "%f58", "%f28", "%f60", "%f30", "%f62"
535 536 };
536 537
537 538
538 539 static const char *fqreg_names[32] = {
539 540 "%q0", "%q32", "%f2", "%f3", "%f4", "%q4", "%q36", "%f6",
540 541 "%f7", "%q8", "%q40", "%f10", "%f11", "%q12", "%q44", "%f14",
541 542 "%f15", "%q16", "%q48", "%f18", "%f19", "%q20", "%q52", "%f22",
542 543 "%f23", "%q24", "%q56", "%f26", "%f27", "%q28", "%q60", "%f30",
543 544 };
544 545
545 546
546 547 /* coprocessor register names -- sparcv8 only */
547 548 static const char *cpreg_names[32] = {
548 549 "%c0", "%c1", "%c2", "%c3", "%c4", "%c5", "%c6", "%c7",
549 550 "%c8", "%c9", "%c10", "%c11", "%c12", "%c13", "%c14", "%c15",
550 551 "%c16", "%c17", "%c18", "%c19", "%c20", "%c21", "%c22", "%c23",
551 552 "%c24", "%c25", "%c26", "%c27", "%c28", "%c29", "%c30", "%c31",
552 553 };
553 554
554 555 /* floating point condition code names */
555 556 static const char *fcc_names[4] = {
556 557 "%fcc0", "%fcc1", "%fcc2", "%fcc3"
557 558 };
558 559
559 560 /* condition code names */
560 561 static const char *icc_names[4] = {
561 562 "%icc", NULL, "%xcc", NULL
562 563 };
563 564
564 565 /* bitmask values for membar */
565 566 static const char *membar_mmask[4] = {
566 567 "#LoadLoad", "#StoreLoad", "#LoadStore", "#StoreStore"
567 568 };
568 569
569 570 static const char *membar_cmask[3] = {
570 571 "#Lookaside", "#MemIssue", "#Sync"
571 572 };
572 573
573 574 /* v8 ancillary state register names */
574 575 static const char *asr_names[32] = {
575 576 "%y", "%asr1", "%asr2", "%asr3",
576 577 "%asr4", "%asr5", "%asr6", "%asr7",
577 578 "%asr8", "%asr9", "%asr10", "%asr11",
578 579 "%asr12", "%asr13", "%asr14", "%asr15",
579 580 NULL, NULL, NULL, NULL,
580 581 NULL, NULL, NULL, NULL,
581 582 NULL, NULL, NULL, NULL,
582 583 NULL, NULL, NULL, NULL
583 584 };
584 585 static const uint32_t asr_rdmask = 0x0000ffffL;
585 586 static const uint32_t asr_wrmask = 0x0000ffffL;
586 587
587 588 static const char *v9_asr_names[32] = {
588 589 "%y", NULL, "%ccr", "%asi",
589 590 "%tick", "%pc", "%fprs", NULL,
590 591 NULL, NULL, NULL, NULL,
591 592 NULL, NULL, NULL, NULL,
592 593 "%pcr", "%pic", "%dcr", "%gsr",
593 594 "%softint_set", "%softint_clr", "%softint", "%tick_cmpr",
594 595 "%stick", "%stick_cmpr", NULL, NULL,
595 596 NULL, NULL, NULL, NULL
596 597 };
597 598 /*
598 599 * on v9, only certain registers are valid for read or writing
599 600 * these are bitmasks corresponding to which registers are valid in which
600 601 * case. Any access to %dcr is illegal.
601 602 */
602 603 static const uint32_t v9_asr_rdmask = 0x03cb007d;
603 604 static const uint32_t v9_asr_wrmask = 0x03fb004d;
604 605
605 606 /* privledged register names on v9 */
606 607 /* TODO: compat - NULL to %priv_nn */
607 608 static const char *v9_privreg_names[32] = {
608 609 "%tpc", "%tnpc", "%tstate", "%tt",
609 610 "%tick", "%tba", "%pstate", "%tl",
610 611 "%pil", "%cwp", "%cansave", "%canrestore",
611 612 "%cleanwin", "%otherwin", "%wstate", "%fq",
612 613 "%gl", NULL, NULL, NULL,
613 614 NULL, NULL, NULL, NULL,
614 615 NULL, NULL, NULL, NULL,
615 616 NULL, NULL, NULL, "%ver"
616 617 };
617 618
618 619 /* hyper privileged register names on v9 */
619 620 static const char *v9_hprivreg_names[32] = {
620 621 "%hpstate", "%htstate", NULL, "%hintp",
621 622 NULL, "%htba", "%hver", NULL,
622 623 NULL, NULL, NULL, NULL,
623 624 NULL, NULL, NULL, NULL,
624 625 NULL, NULL, NULL, NULL,
625 626 NULL, NULL, NULL, NULL,
626 627 NULL, NULL, NULL, NULL,
627 628 NULL, NULL, NULL, "%hstick_cmpr"
628 629 };
629 630
630 631 static const uint32_t v9_pr_rdmask = 0x80017fff;
631 632 static const uint32_t v9_pr_wrmask = 0x00017fff;
632 633 static const uint32_t v9_hpr_rdmask = 0x8000006b;
633 634 static const uint32_t v9_hpr_wrmask = 0x8000006b;
634 635
635 636 static const char *prefetch_str[32] = {
636 637 "#n_reads", "#one_read",
637 638 "#n_writes", "#one_write",
638 639 "#page", NULL, NULL, NULL,
639 640 NULL, NULL, NULL, NULL,
640 641 NULL, NULL, NULL, NULL,
641 642 NULL, "#unified", NULL, NULL,
642 643 "#n_reads_strong", "#one_read_strong",
643 644 "#n_writes_strong", "#one_write_strong",
644 645 NULL, NULL, NULL, NULL,
645 646 NULL, NULL, NULL, NULL
646 647 };
647 648
648 649 static void prt_field(const char *, uint32_t, int);
649 650
650 651 static const char *get_regname(dis_handle_t *, int, uint32_t);
651 652 static int32_t sign_extend(int32_t, int32_t);
652 653
653 654 static void prt_name(dis_handle_t *, const char *, int);
654 655
655 656 #define IMM_SIGNED 0x01 /* Is immediate value signed */
656 657 #define IMM_ADDR 0x02 /* Is immediate value part of an address */
657 658 static void prt_imm(dis_handle_t *, uint32_t, int);
658 659
659 660 static void prt_asi(dis_handle_t *, uint32_t);
660 661 static const char *get_asi_name(uint8_t);
661 662 static void prt_address(dis_handle_t *, uint32_t, int);
662 663 static void prt_aluargs(dis_handle_t *, uint32_t, uint32_t);
663 664 static void bprintf(dis_handle_t *, const char *, ...);
664 665
665 666 /*
666 667 * print out val (which is 'bitlen' bits long) in binary
667 668 */
668 669 #if defined(DIS_STANDALONE)
669 670 /* ARGSUSED */
670 671 void
671 672 prt_binary(uint32_t val, int bitlen)
672 673 {
673 674
674 675 }
675 676
676 677 #else
677 678
678 679 void
679 680 prt_binary(uint32_t val, int bitlen)
680 681 {
681 682 int i;
682 683
683 684 for (i = bitlen - 1; i >= 0; --i) {
684 685 (void) fprintf(stderr, ((val & (1L << i)) != 0) ? "1" : "0");
685 686
686 687 if (i % 4 == 0 && i != 0)
687 688 (void) fprintf(stderr, " ");
688 689 }
689 690 }
690 691 #endif /* DIS_STANDALONE */
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691 692
692 693
693 694 /*
694 695 * print out a call instruction
695 696 * format: call address <name>
696 697 */
697 698 /* ARGSUSED1 */
698 699 int
699 700 fmt_call(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
700 701 {
702 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
701 703 ifmt_t *f = (ifmt_t *)&instr;
702 704
703 705 int32_t disp;
704 706 size_t curlen;
705 707
706 708 int octal = ((dhp->dh_flags & DIS_OCTAL) != 0);
707 709
708 - if ((dhp->dh_debug & DIS_DEBUG_PRTFMT) != 0) {
710 + if ((dhx->dhx_debug & DIS_DEBUG_PRTFMT) != 0) {
709 711 prt_field("op", f->f1.op, 2);
710 712 prt_field("disp30", f->f1.disp30, 30);
711 713 }
712 714
713 715 disp = sign_extend(f->f1.disp30, 30) * 4;
714 716
715 717 prt_name(dhp, inp->in_data.in_def.in_name, 1);
716 718
717 719 bprintf(dhp, (octal != 0) ? "%s0%-11lo" : "%s0x%-10lx",
718 720 (disp < 0) ? "-" : "+",
719 721 (disp < 0) ? (-disp) : disp);
720 722
721 - (void) strlcat(dhp->dh_buf, " <", dhp->dh_buflen);
723 + (void) strlcat(dhx->dhx_buf, " <", dhx->dhx_buflen);
722 724
723 - curlen = strlen(dhp->dh_buf);
725 + curlen = strlen(dhx->dhx_buf);
724 726 dhp->dh_lookup(dhp->dh_data, dhp->dh_addr + (int64_t)disp,
725 - dhp->dh_buf + curlen, dhp->dh_buflen - curlen - 1, NULL,
727 + dhx->dhx_buf + curlen, dhx->dhx_buflen - curlen - 1, NULL,
726 728 NULL);
727 - (void) strlcat(dhp->dh_buf, ">", dhp->dh_buflen);
729 + (void) strlcat(dhx->dhx_buf, ">", dhx->dhx_buflen);
728 730
729 731
730 732 return (0);
731 733 }
732 734
733 735 int
734 736 fmt_sethi(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
735 737 {
738 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
736 739 ifmt_t *f = (ifmt_t *)&instr;
737 740
738 - if ((dhp->dh_debug & DIS_DEBUG_PRTFMT) != 0) {
741 + if ((dhx->dhx_debug & DIS_DEBUG_PRTFMT) != 0) {
739 742 prt_field("op", f->f2.op, 2);
740 743 prt_field("op2", f->f2.op2, 3);
741 744 prt_field("rd", f->f2.rd, 5);
742 745 prt_field("imm22", f->f2.imm22, 22);
743 746 }
744 747
745 748 if (idx == 0) {
746 749 /* unimp / illtrap */
747 750 prt_name(dhp, inp->in_data.in_def.in_name, 1);
748 751 prt_imm(dhp, f->f2.imm22, 0);
749 752 return (0);
750 753 }
751 754
752 755 if (f->f2.imm22 == 0 && f->f2.rd == 0) {
753 756 prt_name(dhp, "nop", 0);
754 757 return (0);
755 758 }
756 759
757 760 /* ?? Should we return -1 if rd == 0 && disp != 0 */
758 761
759 762 prt_name(dhp, inp->in_data.in_def.in_name, 1);
760 763
761 764 bprintf(dhp,
762 765 ((dhp->dh_flags & DIS_OCTAL) != 0) ?
763 766 "%%hi(0%lo), %s" : "%%hi(0x%lx), %s",
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764 767 f->f2.imm22 << 10,
765 768 reg_names[f->f2.rd]);
766 769
767 770 return (0);
768 771 }
769 772
770 773 /* ARGSUSED3 */
771 774 int
772 775 fmt_branch(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
773 776 {
777 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
774 778 const char *name = inp->in_data.in_def.in_name;
775 779 const char *r = NULL;
776 780 const char *annul = "";
777 781 const char *pred = "";
778 782
779 783 char buf[15];
780 784
781 785 ifmt_t *f = (ifmt_t *)&instr;
782 786
783 787 size_t curlen;
784 788 int32_t disp;
785 789 uint32_t flags = inp->in_data.in_def.in_flags;
786 790 int octal = ((dhp->dh_flags & DIS_OCTAL) != 0);
787 791
788 - if ((dhp->dh_debug & DIS_DEBUG_PRTFMT) != 0) {
792 + if ((dhx->dhx_debug & DIS_DEBUG_PRTFMT) != 0) {
789 793 prt_field("op", f->f2.op, 2);
790 794 prt_field("op2", f->f2.op2, 3);
791 795
792 796 switch (FLG_DISP_VAL(flags)) {
793 797 case DISP22:
794 798 prt_field("cond", f->f2a.cond, 4);
795 799 prt_field("a", f->f2a.a, 1);
796 800 prt_field("disp22", f->f2a.disp22, 22);
797 801 break;
798 802
799 803 case DISP19:
800 804 prt_field("cond", f->f2a.cond, 4);
801 805 prt_field("a", f->f2a.a, 1);
802 806 prt_field("p", f->f2b.p, 1);
803 807 prt_field("cc", f->f2b.cc, 2);
804 808 prt_field("disp19", f->f2b.disp19, 19);
805 809 break;
806 810
807 811 case DISP16:
808 812 prt_field("bit 28", ((instr & (1L << 28)) >> 28), 1);
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809 813 prt_field("rcond", f->f2c.cond, 3);
810 814 prt_field("p", f->f2c.p, 1);
811 815 prt_field("rs1", f->f2c.rs1, 5);
812 816 prt_field("d16hi", f->f2c.d16hi, 2);
813 817 prt_field("d16lo", f->f2c.d16lo, 14);
814 818 break;
815 819 }
816 820 }
817 821
818 822 if (f->f2b.op2 == 0x01 && idx == 0x00 && f->f2b.p == 1 &&
819 - f->f2b.cc == 0x02 && ((dhp->dh_debug & DIS_DEBUG_SYN_ALL) != 0)) {
823 + f->f2b.cc == 0x02 && ((dhx->dhx_debug & DIS_DEBUG_SYN_ALL) != 0)) {
820 824 name = "iprefetch";
821 825 flags = FLG_RS1(REG_NONE)|FLG_DISP(DISP19);
822 826 }
823 827
824 828
825 829 switch (FLG_DISP_VAL(flags)) {
826 830 case DISP22:
827 831 disp = sign_extend(f->f2a.disp22, 22);
828 832 break;
829 833
830 834 case DISP19:
831 835 disp = sign_extend(f->f2b.disp19, 19);
832 836 break;
833 837
834 838 case DISP16:
835 839 disp = sign_extend((f->f2c.d16hi << 14)|f->f2c.d16lo, 16);
836 840 break;
837 841
838 842 }
839 843
840 844 disp *= 4;
841 845
842 846 if ((FLG_RS1_VAL(flags) == REG_ICC) || (FLG_RS1_VAL(flags) == REG_FCC))
843 847 r = get_regname(dhp, FLG_RS1_VAL(flags), f->f2b.cc);
844 848 else
845 849 r = get_regname(dhp, FLG_RS1_VAL(flags), f->f2c.rs1);
846 850
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847 851 if (r == NULL)
848 852 return (-1);
849 853
850 854 if (f->f2a.a == 1)
851 855 annul = ",a";
852 856
853 857 if ((flags & FLG_PRED) != 0) {
854 858 if (f->f2b.p == 0) {
855 859 pred = ",pn";
856 860 } else {
857 - if ((dhp->dh_debug & DIS_DEBUG_COMPAT) != 0)
861 + if ((dhx->dhx_debug & DIS_DEBUG_COMPAT) != 0)
858 862 pred = ",pt";
859 863 }
860 864 }
861 865
862 866 (void) snprintf(buf, sizeof (buf), "%s%s%s", name, annul, pred);
863 867 prt_name(dhp, buf, 1);
864 868
865 869
866 870 switch (FLG_DISP_VAL(flags)) {
867 871 case DISP22:
868 872 bprintf(dhp,
869 873 (octal != 0) ? "%s0%-11lo <" : "%s0x%-10lx <",
870 874 (disp < 0) ? "-" : "+",
871 875 (disp < 0) ? (-disp) : disp);
872 876 break;
873 877
874 878 case DISP19:
875 879 bprintf(dhp,
876 880 (octal != 0) ? "%s, %s0%-5lo <" :
877 881 "%s, %s0x%-04lx <", r,
878 882 (disp < 0) ? "-" : "+",
879 883 (disp < 0) ? (-disp) : disp);
880 884 break;
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881 885
882 886 case DISP16:
883 887 bprintf(dhp,
884 888 (octal != 0) ? "%s, %s0%-6lo <" : "%s, %s0x%-5lx <",
885 889 r,
886 890 (disp < 0) ? "-" : "+",
887 891 (disp < 0) ? (-disp) : disp);
888 892 break;
889 893 }
890 894
891 - curlen = strlen(dhp->dh_buf);
895 + curlen = strlen(dhx->dhx_buf);
892 896 dhp->dh_lookup(dhp->dh_data, dhp->dh_addr + (int64_t)disp,
893 - dhp->dh_buf + curlen, dhp->dh_buflen - curlen - 1, NULL, NULL);
897 + dhx->dhx_buf + curlen, dhx->dhx_buflen - curlen - 1, NULL, NULL);
894 898
895 - (void) strlcat(dhp->dh_buf, ">", dhp->dh_buflen);
899 + (void) strlcat(dhx->dhx_buf, ">", dhx->dhx_buflen);
896 900
897 901 return (0);
898 902 }
899 903
900 904
901 905
902 906 /*
903 907 * print out the compare and swap instructions (casa/casxa)
904 908 * format: casa/casxa [%rs1] imm_asi, %rs2, %rd
905 909 * casa/casxa [%rs1] %asi, %rs2, %rd
906 910 *
907 911 * If DIS_DEBUG_SYN_ALL is set, synthetic instructions are emitted
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908 912 * when an immediate ASI value is given as follows:
909 913 *
910 914 * casa [%rs1]#ASI_P, %rs2, %rd -> cas [%rs1], %rs2, %rd
911 915 * casa [%rs1]#ASI_P_L, %rs2, %rd -> casl [%rs1], %rs2, %rd
912 916 * casxa [%rs1]#ASI_P, %rs2, %rd -> casx [%rs1], %rs2, %rd
913 917 * casxa [%rs1]#ASI_P_L, %rs2, %rd -> casxl [%rs1], %rs2, %rd
914 918 */
915 919 static int
916 920 fmt_cas(dis_handle_t *dhp, uint32_t instr, const char *name)
917 921 {
922 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
918 923 ifmt_t *f = (ifmt_t *)&instr;
919 924 const char *asistr = NULL;
920 925 int noasi = 0;
921 926
922 927 asistr = get_asi_name(f->f3.asi);
923 928
924 - if ((dhp->dh_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT)) != 0) {
929 + if ((dhx->dhx_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT)) != 0) {
925 930 if (f->f3.op3 == 0x3c && f->f3.i == 0) {
926 931 if (f->f3.asi == 0x80) {
927 932 noasi = 1;
928 933 name = "cas";
929 934 }
930 935
931 936 if (f->f3.asi == 0x88) {
932 937 noasi = 1;
933 938 name = "casl";
934 939 }
935 940 }
936 941
937 942 if (f->f3.op3 == 0x3e && f->f3.i == 0) {
938 943 if (f->f3.asi == 0x80) {
939 944 noasi = 1;
940 945 name = "casx";
941 946 }
942 947
943 948 if (f->f3.asi == 0x88) {
944 949 noasi = 1;
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945 950 name = "casxl";
946 951 }
947 952 }
948 953 }
949 954
950 955 prt_name(dhp, name, 1);
951 956
952 957 bprintf(dhp, "[%s]", reg_names[f->f3.rs1]);
953 958
954 959 if (noasi == 0) {
955 - (void) strlcat(dhp->dh_buf, " ", dhp->dh_buflen);
960 + (void) strlcat(dhx->dhx_buf, " ", dhx->dhx_buflen);
956 961 prt_asi(dhp, instr);
957 962 }
958 963
959 964 bprintf(dhp, ", %s, %s", reg_names[f->f3.rs2], reg_names[f->f3.rd]);
960 965
961 966 if (noasi == 0 && asistr != NULL)
962 967 bprintf(dhp, "\t<%s>", asistr);
963 968
964 969 return (0);
965 970 }
966 971
967 972 /*
968 973 * format a load/store instruction
969 974 * format: ldXX [%rs1 + %rs2], %rd load, i==0
970 975 * ldXX [%rs1 +/- nn], %rd load, i==1
971 976 * ldXX [%rs1 + %rs2] #XX, %rd load w/ imm_asi, i==0
972 977 * ldXX [%rs1 +/- nn] %asi, %rd load from asi[%asi], i==1
973 978 *
974 979 * stXX %rd, [%rs1 + %rs2] store, i==0
975 980 * stXX %rd, [%rs1 +/- nn] store, i==1
976 981 * stXX %rd, [%rs1 + %rs1] #XX store to imm_asi, i==0
977 982 * stXX %rd, [%rs1 +/-nn] %asi store to asi[%asi], i==1
978 983 *
979 984 * The register sets used for %rd are set in the instructions flags field
980 985 * The asi variants are used if FLG_ASI is set in the instructions flags field
981 986 *
982 987 * If DIS_DEBUG_SYNTH_ALL or DIS_DEBUG_COMPAT are set,
983 988 * When %rs1, %rs2 or nn are 0, they are not printed, i.e.
984 989 * [ %rs1 + 0x0 ], %rd -> [%rs1], %rd for example
985 990 *
986 991 * The following synthetic instructions are also implemented:
987 992 *
988 993 * stb %g0, [addr] -> clrb [addr] DIS_DEBUG_SYNTH_ALL
989 994 * sth %g0, [addr] -> crlh [addr] DIS_DEBUG_SYNTH_ALL
990 995 * stw %g0, [addr] -> clr [addr] DIS_DEBUG_SYNTH_ALL|DIS_DEBUG_COMPAT
991 996 * stx %g0, [addr] -> clrx [addr] DIS_DEBUG_SYNTH_ALL
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992 997 *
993 998 * If DIS_DEBUG_COMPAT is set, the following substitutions also take place
994 999 * lduw -> ld
995 1000 * ldtw -> ld
996 1001 * stuw -> st
997 1002 * sttw -> st
998 1003 */
999 1004 int
1000 1005 fmt_ls(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
1001 1006 {
1007 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
1002 1008 ifmt_t *f = (ifmt_t *)&instr;
1003 1009 const char *regstr = NULL;
1004 1010 const char *asistr = NULL;
1005 1011
1006 1012 const char *iname = inp->in_data.in_def.in_name;
1007 1013 uint32_t flags = inp->in_data.in_def.in_flags;
1008 1014
1009 - if ((dhp->dh_debug & DIS_DEBUG_PRTFMT) != 0) {
1015 + if ((dhx->dhx_debug & DIS_DEBUG_PRTFMT) != 0) {
1010 1016 prt_field("op", f->f3.op, 2);
1011 1017 prt_field("op3", f->f3.op3, 6);
1012 1018 prt_field("rs1", f->f3.rs1, 5);
1013 1019 prt_field("i", f->f3.i, 1);
1014 1020 if (f->f3.i != 0) {
1015 1021 prt_field("simm13", f->f3a.simm13, 13);
1016 1022 } else {
1017 1023 if ((flags & FLG_ASI) != 0)
1018 1024 prt_field("imm_asi", f->f3.asi, 8);
1019 1025 prt_field("rs2", f->f3.rs2, 5);
1020 1026 }
1021 1027 prt_field("rd", f->f3.rd, 5);
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1022 1028 }
1023 1029
1024 1030 if (idx == 0x2d || idx == 0x3d) {
1025 1031 /* prefetch / prefetcha */
1026 1032
1027 1033 prt_name(dhp, iname, 1);
1028 1034
1029 1035 prt_address(dhp, instr, 0);
1030 1036
1031 1037 if (idx == 0x3d) {
1032 - (void) strlcat(dhp->dh_buf, " ", dhp->dh_buflen);
1038 + (void) strlcat(dhx->dhx_buf, " ", dhx->dhx_buflen);
1033 1039 prt_asi(dhp, instr);
1034 1040 }
1035 1041
1036 - (void) strlcat(dhp->dh_buf, ", ", dhp->dh_buflen);
1042 + (void) strlcat(dhx->dhx_buf, ", ", dhx->dhx_buflen);
1037 1043
1038 1044 /* fcn field is the same as rd */
1039 1045 if (prefetch_str[f->f3.rd] != NULL)
1040 - (void) strlcat(dhp->dh_buf, prefetch_str[f->f3.rd],
1041 - dhp->dh_buflen);
1046 + (void) strlcat(dhx->dhx_buf, prefetch_str[f->f3.rd],
1047 + dhx->dhx_buflen);
1042 1048 else
1043 1049 prt_imm(dhp, f->f3.rd, 0);
1044 1050
1045 1051 if (idx == 0x3d && f->f3.i == 0) {
1046 1052 asistr = get_asi_name(f->f3.asi);
1047 1053 if (asistr != NULL)
1048 1054 bprintf(dhp, "\t<%s>", asistr);
1049 1055 }
1050 1056
1051 1057 return (0);
1052 1058 }
1053 1059
1054 1060 /* casa / casxa */
1055 1061 if (idx == 0x3c || idx == 0x3e)
1056 1062 return (fmt_cas(dhp, instr, iname));
1057 1063
1058 1064 /* synthetic instructions & special cases */
1059 1065 switch (idx) {
1060 1066 case 0x00:
1061 1067 /* ld */
1062 - if ((dhp->dh_debug & DIS_DEBUG_COMPAT) == 0)
1068 + if ((dhx->dhx_debug & DIS_DEBUG_COMPAT) == 0)
1063 1069 iname = "lduw";
1064 1070 break;
1065 1071
1066 1072 case 0x03:
1067 - if ((dhp->dh_debug & DIS_DEBUG_COMPAT) == 0)
1073 + if ((dhx->dhx_debug & DIS_DEBUG_COMPAT) == 0)
1068 1074 iname = "ldtw";
1069 1075 break;
1070 1076
1071 1077 case 0x04:
1072 1078 /* stw */
1073 - if ((dhp->dh_debug & DIS_DEBUG_COMPAT) == 0)
1079 + if ((dhx->dhx_debug & DIS_DEBUG_COMPAT) == 0)
1074 1080 iname = "stuw";
1075 1081
1076 1082 if ((dhp->dh_flags & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL))
1077 1083 == 0)
1078 1084 break;
1079 1085
1080 1086 if (f->f3.rd == 0) {
1081 1087 iname = "clr";
1082 1088 flags = FLG_RD(REG_NONE);
1083 1089 }
1084 1090 break;
1085 1091
1086 1092 case 0x05:
1087 1093 /* stb */
1088 1094 if ((dhp->dh_flags & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL))
1089 1095 == 0)
1090 1096 break;
1091 1097
1092 1098 if (f->f3.rd == 0) {
1093 1099 iname = "clrb";
1094 1100 flags = FLG_RD(REG_NONE);
1095 1101 }
1096 1102 break;
1097 1103
1098 1104 case 0x06:
1099 1105 /* sth */
1100 1106 if ((dhp->dh_flags & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL))
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1101 1107 == 0)
1102 1108 break;
1103 1109
1104 1110 if (f->f3.rd == 0) {
1105 1111 iname = "clrh";
1106 1112 flags = FLG_RD(REG_NONE);
1107 1113 }
1108 1114 break;
1109 1115
1110 1116 case 0x07:
1111 - if ((dhp->dh_debug & DIS_DEBUG_COMPAT) == 0)
1117 + if ((dhx->dhx_debug & DIS_DEBUG_COMPAT) == 0)
1112 1118 iname = "sttw";
1113 1119 break;
1114 1120
1115 1121 case 0x0e:
1116 1122 /* stx */
1117 1123
1118 1124 if ((dhp->dh_flags & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL))
1119 1125 == 0)
1120 1126 break;
1121 1127
1122 1128 if (f->f3.rd == 0) {
1123 1129 iname = "clrx";
1124 1130 flags = FLG_RD(REG_NONE);
1125 1131 }
1126 1132 break;
1127 1133
1128 1134 case 0x13:
1129 1135 /* ldtwa */
1130 - if (((dhp->dh_debug & DIS_DEBUG_COMPAT) == 0) &&
1136 + if (((dhx->dhx_debug & DIS_DEBUG_COMPAT) == 0) &&
1131 1137 ((dhp->dh_flags & (DIS_SPARC_V9|DIS_SPARC_V9_SGI)) != 0))
1132 1138 iname = "ldtwa";
1133 1139 break;
1134 1140
1135 1141 case 0x17:
1136 1142 /* sttwa */
1137 - if (((dhp->dh_debug & DIS_DEBUG_COMPAT) == 0) &&
1143 + if (((dhx->dhx_debug & DIS_DEBUG_COMPAT) == 0) &&
1138 1144 ((dhp->dh_flags & (DIS_SPARC_V9|DIS_SPARC_V9_SGI)) != 0))
1139 1145 iname = "sttwa";
1140 1146 break;
1141 1147
1142 1148 case 0x21:
1143 1149 case 0x25:
1144 1150 /*
1145 1151 * on sparcv8 it merely says that rd != 1 should generate an
1146 1152 * exception, on v9, it is illegal
1147 1153 */
1148 1154 if ((dhp->dh_flags & (DIS_SPARC_V9|DIS_SPARC_V9_SGI)) == 0)
1149 1155 break;
1150 1156
1151 1157 iname = (idx == 0x21) ? "ldx" : "stx";
1152 1158
1153 1159 if (f->f3.rd > 1)
1154 1160 return (-1);
1155 1161
1156 1162 break;
1157 1163
1158 1164 case 0x31:
1159 1165 /* stda */
1160 1166 switch (f->f3.asi) {
1161 1167 case 0xc0:
1162 1168 case 0xc1:
1163 1169 case 0xc8:
1164 1170 case 0xc9:
1165 1171 case 0xc2:
1166 1172 case 0xc3:
1167 1173 case 0xca:
1168 1174 case 0xcb:
1169 1175 case 0xc4:
1170 1176 case 0xc5:
1171 1177 case 0xcc:
1172 1178 case 0xcd:
1173 1179 /*
1174 1180 * store partial floating point, only valid w/
1175 1181 * vis
1176 1182 *
1177 1183 * Somewhat confusingly, it uses the same op
1178 1184 * code as 'stda' -- store double to alternate
1179 1185 * space. It is distinguised by specific
1180 1186 * imm_asi values (as seen above), and
1181 1187 * has a slightly different output syntax
1182 1188 */
1183 1189
1184 1190 if ((dhp->dh_flags & DIS_SPARC_V9_SGI) == 0)
1185 1191 break;
1186 1192 if (f->f3.i != 0)
1187 1193 break;
1188 1194 prt_name(dhp, iname, 1);
1189 1195 bprintf(dhp, "%s, %s, [%s] ",
1190 1196 get_regname(dhp, REG_FPD, f->f3.rd),
1191 1197 get_regname(dhp, REG_FPD, f->f3.rs2),
1192 1198 get_regname(dhp, REG_FPD, f->f3.rs1));
1193 1199 prt_asi(dhp, instr);
1194 1200 asistr = get_asi_name(f->f3.asi);
1195 1201 if (asistr != NULL)
1196 1202 bprintf(dhp, "\t<%s>", asistr);
1197 1203
1198 1204 return (0);
1199 1205
1200 1206 default:
1201 1207 break;
1202 1208 }
1203 1209
1204 1210 }
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1205 1211
1206 1212 regstr = get_regname(dhp, FLG_RD_VAL(flags), f->f3.rd);
1207 1213
1208 1214 if (f->f3.i == 0)
1209 1215 asistr = get_asi_name(f->f3.asi);
1210 1216
1211 1217 prt_name(dhp, iname, 1);
1212 1218
1213 1219 if ((flags & FLG_STORE) != 0) {
1214 1220 if (regstr[0] != '\0') {
1215 - (void) strlcat(dhp->dh_buf, regstr, dhp->dh_buflen);
1216 - (void) strlcat(dhp->dh_buf, ", ", dhp->dh_buflen);
1221 + (void) strlcat(dhx->dhx_buf, regstr, dhx->dhx_buflen);
1222 + (void) strlcat(dhx->dhx_buf, ", ", dhx->dhx_buflen);
1217 1223 }
1218 1224
1219 1225 prt_address(dhp, instr, 0);
1220 1226 if ((flags & FLG_ASI) != 0) {
1221 - (void) strlcat(dhp->dh_buf, " ", dhp->dh_buflen);
1227 + (void) strlcat(dhx->dhx_buf, " ", dhx->dhx_buflen);
1222 1228 prt_asi(dhp, instr);
1223 1229 }
1224 1230 } else {
1225 1231 prt_address(dhp, instr, 0);
1226 1232 if ((flags & FLG_ASI) != 0) {
1227 - (void) strlcat(dhp->dh_buf, " ", dhp->dh_buflen);
1233 + (void) strlcat(dhx->dhx_buf, " ", dhx->dhx_buflen);
1228 1234 prt_asi(dhp, instr);
1229 1235 }
1230 1236
1231 1237 if (regstr[0] != '\0') {
1232 - (void) strlcat(dhp->dh_buf, ", ", dhp->dh_buflen);
1233 - (void) strlcat(dhp->dh_buf, regstr, dhp->dh_buflen);
1238 + (void) strlcat(dhx->dhx_buf, ", ", dhx->dhx_buflen);
1239 + (void) strlcat(dhx->dhx_buf, regstr, dhx->dhx_buflen);
1234 1240 }
1235 1241 }
1236 1242
1237 1243 if ((flags & FLG_ASI) != 0 && asistr != NULL)
1238 1244 bprintf(dhp, "\t<%s>", asistr);
1239 1245
1240 1246 return (0);
1241 1247 }
1242 1248
1243 1249 static int
1244 1250 fmt_cpop(dis_handle_t *dhp, uint32_t instr, const inst_t *inp)
1245 1251 {
1252 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
1246 1253 ifmt_t *f = (ifmt_t *)&instr;
1247 1254 int flags = FLG_P1(REG_CP)|FLG_P2(REG_CP)|FLG_NOIMM|FLG_P3(REG_CP);
1248 1255
1249 - if ((dhp->dh_debug & DIS_DEBUG_PRTFMT) != 0) {
1256 + if ((dhx->dhx_debug & DIS_DEBUG_PRTFMT) != 0) {
1250 1257 prt_field("op", f->fcp.op, 2);
1251 1258 prt_field("op3", f->fcp.op3, 6);
1252 1259 prt_field("opc", f->fcp.opc, 9);
1253 1260 prt_field("rs1", f->fcp.rs1, 5);
1254 1261 prt_field("rs2", f->fcp.rs2, 5);
1255 1262 prt_field("rd", f->fcp.rd, 5);
1256 1263 }
1257 1264
1258 1265 prt_name(dhp, inp->in_data.in_def.in_name, 1);
1259 1266 prt_imm(dhp, f->fcp.opc, 0);
1260 1267
1261 - (void) strlcat(dhp->dh_buf, ", ", dhp->dh_buflen);
1268 + (void) strlcat(dhx->dhx_buf, ", ", dhx->dhx_buflen);
1262 1269 (void) prt_aluargs(dhp, instr, flags);
1263 1270
1264 1271 return (0);
1265 1272 }
1266 1273
1267 1274 static int
1268 1275 dis_fmt_rdwr(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
1269 1276 {
1277 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
1270 1278 const char *psr_str = "%psr";
1271 1279 const char *wim_str = "%wim";
1272 1280 const char *tbr_str = "%tbr";
1273 1281
1274 1282 const char *name = inp->in_data.in_def.in_name;
1275 1283 const char *regstr = NULL;
1276 1284
1277 1285 ifmt_t *f = (ifmt_t *)&instr;
1278 1286
1279 1287 int rd = (idx < 0x30);
1280 1288 int v9 = (dhp->dh_flags & (DIS_SPARC_V9|DIS_SPARC_V9_SGI));
1281 1289 int ridx = f->f3.rs1;
1282 1290 int i, first;
1283 1291 int pr_rs1 = 1;
1284 1292 int pr_rs2 = 1;
1285 1293
1286 1294 int use_mask = 1;
1287 1295 uint32_t mask;
1288 1296
1289 1297 if (rd == 0)
1290 1298 ridx = f->f3.rd;
1291 1299
1292 1300 switch (idx) {
1293 1301 case 0x28:
1294 1302 /* rd */
1295 1303
1296 1304 /* stbar */
1297 1305 if ((f->f3.rd == 0) && (f->f3.rs1 == 15) && (f->f3.i == 0)) {
1298 1306 prt_name(dhp, "stbar", 0);
1299 1307 return (0);
1300 1308 }
1301 1309
1302 1310 /* membar */
1303 1311 if ((v9 != 0) && (f->f3.rd == 0) && (f->f3.rs1 == 15) &&
1304 1312 (f->f3.i == 1) && ((f->i & (1L << 12)) == 0)) {
1305 1313
1306 1314 prt_name(dhp, "membar",
1307 1315 ((f->fmb.cmask != 0) || (f->fmb.mmask != 0)));
1308 1316
1309 1317 first = 0;
1310 1318
1311 1319 for (i = 0; i < 4; ++i) {
1312 1320 if ((f->fmb.cmask & (1L << i)) != 0) {
1313 1321 bprintf(dhp, "%s%s",
1314 1322 (first != 0) ? "|" : "",
1315 1323 membar_cmask[i]);
1316 1324 first = 1;
1317 1325 }
1318 1326 }
1319 1327
1320 1328 for (i = 0; i < 5; ++i) {
1321 1329 if ((f->fmb.mmask & (1L << i)) != 0) {
1322 1330 bprintf(dhp, "%s%s",
1323 1331 (first != 0) ? "|" : "",
1324 1332 membar_mmask[i]);
1325 1333 first = 1;
1326 1334 }
1327 1335 }
1328 1336
1329 1337 return (0);
1330 1338 }
1331 1339
1332 1340 if (v9 != 0) {
1333 1341 regstr = v9_asr_names[ridx];
1334 1342 mask = v9_asr_rdmask;
1335 1343 } else {
1336 1344 regstr = asr_names[ridx];
1337 1345 mask = asr_rdmask;
1338 1346 }
1339 1347 break;
1340 1348
1341 1349 case 0x29:
1342 1350 if (v9 != 0) {
1343 1351 regstr = v9_hprivreg_names[ridx];
1344 1352 mask = v9_hpr_rdmask;
1345 1353 } else {
1346 1354 regstr = psr_str;
1347 1355 use_mask = 0;
1348 1356 }
1349 1357 break;
1350 1358
1351 1359 case 0x2a:
1352 1360 if (v9 != 0) {
1353 1361 regstr = v9_privreg_names[ridx];
1354 1362 mask = v9_pr_rdmask;
1355 1363 } else {
1356 1364 regstr = wim_str;
1357 1365 use_mask = 0;
1358 1366 }
1359 1367 break;
1360 1368
1361 1369 case 0x2b:
1362 1370 if (v9 != 0) {
1363 1371 /* flushw */
1364 1372 prt_name(dhp, name, 0);
1365 1373 return (0);
1366 1374 }
1367 1375
1368 1376 regstr = tbr_str;
1369 1377 use_mask = 0;
1370 1378 break;
1371 1379
1372 1380 case 0x30:
1373 1381 if (v9 != 0) {
1374 1382 regstr = v9_asr_names[ridx];
1375 1383 mask = v9_asr_wrmask;
1376 1384 } else {
1377 1385 regstr = asr_names[ridx];
1378 1386 mask = asr_wrmask;
1379 1387 }
1380 1388
1381 1389 /*
1382 1390 * sir is shoehorned in here, per Ultrasparc 2007
1383 1391 * hyperprivileged edition, section 7.88, all of
1384 1392 * these must be true to distinguish from WRasr
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1385 1393 */
1386 1394 if (v9 != 0 && f->f3.rd == 15 && f->f3.rs1 == 0 &&
1387 1395 f->f3.i == 1) {
1388 1396 prt_name(dhp, "sir", 1);
1389 1397 prt_imm(dhp, sign_extend(f->f3a.simm13, 13),
1390 1398 IMM_SIGNED);
1391 1399 return (0);
1392 1400 }
1393 1401
1394 1402 /* synth: mov */
1395 - if ((dhp->dh_debug & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL))
1403 + if ((dhx->dhx_debug & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL))
1396 1404 == 0)
1397 1405 break;
1398 1406
1399 1407 if (v9 == 0) {
1400 1408 if (f->f3.rs1 == 0) {
1401 1409 name = "mov";
1402 1410 pr_rs1 = 0;
1403 1411 }
1404 1412
1405 1413 if ((f->f3.i == 0 && f->f3.rs2 == 0) ||
1406 1414 (f->f3.i == 1 && f->f3a.simm13 == 0)) {
1407 1415 name = "mov";
1408 1416 pr_rs2 = 0;
1409 1417 }
1410 1418 }
1411 1419
1412 1420 if (pr_rs1 == 0)
1413 1421 pr_rs2 = 1;
1414 1422
1415 1423 break;
1416 1424
1417 1425 case 0x31:
1418 1426 /*
1419 1427 * NOTE: due to the presence of an overlay entry for another
1420 1428 * table, this case only happens when doing v8 instructions
1421 1429 * only
1422 1430 */
1423 1431 regstr = psr_str;
1424 1432 use_mask = 0;
1425 1433 break;
1426 1434
1427 1435 case 0x32:
1428 1436 if (v9 != 0) {
1429 1437 regstr = v9_privreg_names[ridx];
1430 1438 mask = v9_pr_wrmask;
1431 1439 } else {
1432 1440 regstr = wim_str;
1433 1441 use_mask = 0;
1434 1442 }
1435 1443 break;
1436 1444
1437 1445 case 0x33:
1438 1446 if (v9 != 0) {
1439 1447 regstr = v9_hprivreg_names[ridx];
1440 1448 mask = v9_hpr_wrmask;
1441 1449 } else {
1442 1450 regstr = tbr_str;
1443 1451 use_mask = 0;
1444 1452 }
1445 1453 break;
1446 1454 }
1447 1455
1448 1456 if (regstr == NULL)
1449 1457 return (-1);
1450 1458
1451 1459 if (use_mask != 0 && ((1L << ridx) & mask) == 0)
1452 1460 return (-1);
1453 1461
1454 1462 prt_name(dhp, name, 1);
1455 1463
1456 1464 if (rd != 0) {
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1457 1465 bprintf(dhp, "%s, %s", regstr, reg_names[f->f3.rd]);
1458 1466 } else {
1459 1467 if (pr_rs1 == 1)
1460 1468 bprintf(dhp, "%s, ", reg_names[f->f3.rs1]);
1461 1469
1462 1470 if (pr_rs2 != 0) {
1463 1471 if (f->f3.i == 1)
1464 1472 prt_imm(dhp, sign_extend(f->f3a.simm13, 13),
1465 1473 IMM_SIGNED);
1466 1474 else
1467 - (void) strlcat(dhp->dh_buf,
1468 - reg_names[f->f3.rs2], dhp->dh_buflen);
1469 - (void) strlcat(dhp->dh_buf, ", ", dhp->dh_buflen);
1475 + (void) strlcat(dhx->dhx_buf,
1476 + reg_names[f->f3.rs2], dhx->dhx_buflen);
1477 + (void) strlcat(dhx->dhx_buf, ", ", dhx->dhx_buflen);
1470 1478 }
1471 1479
1472 - (void) strlcat(dhp->dh_buf, regstr, dhp->dh_buflen);
1480 + (void) strlcat(dhx->dhx_buf, regstr, dhx->dhx_buflen);
1473 1481 }
1474 1482
1475 1483 return (0);
1476 1484 }
1477 1485
1478 1486 /* ARGSUSED3 */
1479 1487 int
1480 1488 fmt_trap(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
1481 1489 {
1490 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
1482 1491 ifmt_t *f = (ifmt_t *)&instr;
1483 1492
1484 1493 int v9 = ((dhp->dh_flags & (DIS_SPARC_V9|DIS_SPARC_V9_SGI)) != 0);
1485 1494 int p_rs1, p_t;
1486 1495
1487 1496 if (f->ftcc.undef != 0)
1488 1497 return (-1);
1489 1498
1490 1499 if (icc_names[f->ftcc.cc] == NULL)
1491 1500 return (-1);
1492 1501
1493 1502 if (f->ftcc.i == 1 && f->ftcc.undef2 != 0)
1494 1503 return (-1);
1495 1504
1496 1505 if (f->ftcc2.i == 0 && f->ftcc2.undef2 != 0)
1497 1506 return (-1);
1498 1507
1499 1508 p_rs1 = ((f->ftcc.rs1 != 0) ||
1500 - ((dhp->dh_debug & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL)) == 0));
1509 + ((dhx->dhx_debug & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL)) == 0));
1501 1510
1502 1511 if (f->ftcc.i == 0) {
1503 1512 p_t = (f->f3.rs2 != 0 || p_rs1 == 0);
1504 1513
1505 1514 bprintf(dhp, "%-9s %s%s%s%s%s", inp->in_data.in_def.in_name,
1506 1515 (v9 != 0) ? icc_names[f->ftcc2.cc] : "",
1507 1516 (v9 != 0) ? ", " : "",
1508 1517 (p_rs1 != 0) ? reg_names[f->ftcc2.rs1] : "",
1509 1518 (p_rs1 != 0) ? " + " : "",
1510 1519 (p_t != 0) ? reg_names[f->f3.rs2] : "");
1511 1520 } else {
1512 1521 bprintf(dhp, "%-9s %s%s%s%s0x%x", inp->in_data.in_def.in_name,
1513 1522 (v9 != 0) ? icc_names[f->ftcc2.cc] : "",
1514 1523 (v9 != 0) ? ", " : "",
1515 1524 (p_rs1 != 0) ? reg_names[f->ftcc2.rs1] : "",
1516 1525 (p_rs1 != 0) ? " + " : "",
1517 1526 f->ftcc.immtrap);
1518 1527 }
1519 1528 return (0);
1520 1529 }
1521 1530
1522 1531 static int
1523 1532 prt_shift(dis_handle_t *dhp, uint32_t instr, const inst_t *inp)
1524 1533 {
1525 1534 char name[5];
1526 1535 uint32_t cnt;
1527 1536
1528 1537 ifmt_t *f = (ifmt_t *)&instr;
1529 1538 int octal = ((dhp->dh_flags & DIS_OCTAL) != 0);
1530 1539
1531 1540 name[0] = '\0';
1532 1541 (void) strlcat(name, inp->in_data.in_def.in_name, sizeof (name));
1533 1542
1534 1543 if (f->f3b.i == 1)
1535 1544 cnt = f->f3.rs2;
1536 1545
1537 1546 if (f->f3b.x == 1 && ((dhp->dh_flags & DIS_SPARC_V8) == 0)) {
1538 1547 cnt = f->f3b.shcnt;
1539 1548 (void) strlcat(name, "x", sizeof (name));
1540 1549 }
1541 1550
1542 1551 prt_name(dhp, name, 1);
1543 1552
1544 1553 if (f->f3b.i == 1)
1545 1554 bprintf(dhp, (octal != 0) ? "%s, 0%lo, %s" : "%s, 0x%lx, %s",
1546 1555 reg_names[f->f3.rs1], cnt, reg_names[f->f3.rd]);
1547 1556 else
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1548 1557 bprintf(dhp, "%s, %s, %s", reg_names[f->f3.rs1],
1549 1558 reg_names[f->f3.rs2], reg_names[f->f3.rd]);
1550 1559
1551 1560 return (0);
1552 1561 }
1553 1562
1554 1563 /* ARGSUSED3 */
1555 1564 static int
1556 1565 prt_jmpl(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
1557 1566 {
1567 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
1558 1568 const char *name = inp->in_data.in_def.in_name;
1559 1569 ifmt_t *f = (ifmt_t *)&instr;
1560 1570
1561 - if (f->f3.rd == 15 && ((dhp->dh_debug & DIS_DEBUG_COMPAT) == 0))
1571 + if (f->f3.rd == 15 && ((dhx->dhx_debug & DIS_DEBUG_COMPAT) == 0))
1562 1572 name = "call";
1563 1573
1564 1574 if (f->f3.rd == 0) {
1565 1575 if (f->f3.i == 1 && f->f3a.simm13 == 8) {
1566 1576 if (f->f3.rs1 == 15) {
1567 1577 prt_name(dhp, "retl", 0);
1568 1578 return (0);
1569 1579 }
1570 1580
1571 1581 if (f->f3.rs1 == 31) {
1572 1582 prt_name(dhp, "ret", 0);
1573 1583 return (0);
1574 1584 }
1575 1585 }
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1576 1586
1577 1587 name = "jmp";
1578 1588 }
1579 1589
1580 1590 prt_name(dhp, name, 1);
1581 1591 prt_address(dhp, instr, 1);
1582 1592
1583 1593 if (f->f3.rd == 0)
1584 1594 return (0);
1585 1595
1586 - if (f->f3.rd == 15 && ((dhp->dh_debug & DIS_DEBUG_COMPAT) == 0))
1596 + if (f->f3.rd == 15 && ((dhx->dhx_debug & DIS_DEBUG_COMPAT) == 0))
1587 1597 return (0);
1588 1598
1589 1599 bprintf(dhp, ", %s", reg_names[f->f3.rd]);
1590 1600
1591 1601 return (0);
1592 1602 }
1593 1603
1594 1604 int
1595 1605 fmt_alu(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
1596 1606 {
1607 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
1597 1608 ifmt_t *f = (ifmt_t *)&instr;
1598 1609
1599 1610 const char *name = inp->in_data.in_def.in_name;
1600 1611 int flags = inp->in_data.in_def.in_flags;
1601 1612 int arg = 0;
1602 1613
1603 - if ((dhp->dh_debug & DIS_DEBUG_PRTFMT) != 0) {
1614 + if ((dhx->dhx_debug & DIS_DEBUG_PRTFMT) != 0) {
1604 1615 prt_field("op", f->f3.op, 2);
1605 1616 prt_field("op3", f->f3.op3, 6);
1606 1617 prt_field("rs1", f->f3.rs1, 5);
1607 1618
1608 1619 switch (idx) {
1609 1620 /* TODO: more formats */
1610 1621
1611 1622 default:
1612 1623 if (f->f3.i == 0)
1613 1624 prt_field("rs2", f->f3.rs2, 5);
1614 1625 else
1615 1626 prt_field("simm13", f->f3a.simm13, 13);
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1616 1627
1617 1628 prt_field("rd", f->f3.rd, 5);
1618 1629 }
1619 1630
1620 1631 }
1621 1632
1622 1633 switch (idx) {
1623 1634 case 0x00:
1624 1635 /* add */
1625 1636
1626 - if ((dhp->dh_debug & DIS_DEBUG_SYN_ALL) == 0)
1637 + if ((dhx->dhx_debug & DIS_DEBUG_SYN_ALL) == 0)
1627 1638 break;
1628 1639
1629 1640 if (f->f3.rs1 == f->f3.rd && f->f3.i == 1 &&
1630 1641 f->f3a.simm13 == 1) {
1631 1642 name = "inc";
1632 1643 flags = FLG_P1(REG_NONE)|FLG_P2(REG_NONE)|FLG_NOIMM;
1633 1644 break;
1634 1645 }
1635 1646
1636 1647 if (f->f3.rs1 == f->f3.rd && f->f3.i == 1 &&
1637 1648 f->f3a.simm13 != 1) {
1638 1649 name = "inc";
1639 1650 flags = FLG_P1(REG_NONE);
1640 1651 break;
1641 1652 }
1642 1653 break;
1643 1654
1644 1655 case 0x02:
1645 1656 /* or */
1646 1657
1647 - if ((dhp->dh_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT))
1658 + if ((dhx->dhx_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT))
1648 1659 == 0)
1649 1660 break;
1650 1661
1651 - if ((dhp->dh_debug & DIS_DEBUG_SYN_ALL) != 0) {
1662 + if ((dhx->dhx_debug & DIS_DEBUG_SYN_ALL) != 0) {
1652 1663 if (f->f3.rs1 == f->f3.rd) {
1653 1664 name = "bset";
1654 1665 flags = FLG_P1(REG_NONE);
1655 1666 break;
1656 1667 }
1657 1668 }
1658 1669
1659 1670 if (((f->f3.i == 0 && f->f3.rs2 == 0) ||
1660 1671 (f->f3.i == 1 && f->f3a.simm13 == 0)) &&
1661 1672 (f->f3.rs1 == 0)) {
1662 1673 name = "clr";
1663 1674 flags = FLG_P1(REG_NONE)|FLG_P2(REG_NONE)|FLG_NOIMM;
1664 1675 break;
1665 1676 }
1666 1677
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1667 1678 if (f->f3.rs1 == 0) {
1668 1679 name = "mov";
1669 1680 flags = FLG_P1(REG_NONE);
1670 1681 break;
1671 1682 }
1672 1683 break;
1673 1684
1674 1685 case 0x04:
1675 1686 /* sub */
1676 1687
1677 - if ((dhp->dh_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT))
1688 + if ((dhx->dhx_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT))
1678 1689 == 0)
1679 1690 break;
1680 1691
1681 1692 if (f->f3.rs1 == 0 && f->f3.i == 0 && f->f3.rs2 == f->f3.rd) {
1682 1693 name = "neg";
1683 1694 flags = FLG_P1(REG_NONE)|FLG_P2(REG_NONE);
1684 1695 break;
1685 1696 }
1686 1697
1687 1698 if (f->f3.rs1 == 0 && f->f3.i == 0 && f->f3.rs2 != f->f3.rd) {
1688 1699 name = "neg";
1689 1700 flags = FLG_P1(REG_NONE);
1690 1701 break;
1691 1702 }
1692 1703
1693 - if ((dhp->dh_debug & DIS_DEBUG_SYN_ALL) == 0)
1704 + if ((dhx->dhx_debug & DIS_DEBUG_SYN_ALL) == 0)
1694 1705 break;
1695 1706
1696 1707 if (f->f3.rs1 == f->f3.rd && f->f3.i == 1 &&
1697 1708 f->f3a.simm13 == 1) {
1698 1709 name = "dec";
1699 1710 flags = FLG_P1(REG_NONE)|FLG_P2(REG_NONE)|FLG_NOIMM;
1700 1711 break;
1701 1712 }
1702 1713
1703 1714 if (f->f3.rs1 == f->f3.rd && f->f3.i == 1 &&
1704 1715 f->f3a.simm13 != 1) {
1705 1716 name = "dec";
1706 1717 flags = FLG_P1(REG_NONE);
1707 1718 break;
1708 1719 }
1709 1720 break;
1710 1721
1711 1722 case 0x07:
1712 1723 /* xnor */
1713 1724
1714 - if ((dhp->dh_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT))
1725 + if ((dhx->dhx_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT))
1715 1726 == 0)
1716 1727 break;
1717 1728
1718 1729 /*
1719 1730 * xnor -> not when you have:
1720 1731 * xnor %rs1, 0x0 or %g0, %rd
1721 1732 */
1722 1733 if ((f->f3.i == 0 && f->f3.rs2 != 0) ||
1723 1734 (f->f3.i == 1 && f->f3a.simm13 != 0))
1724 1735 break;
1725 1736
1726 1737 name = "not";
1727 1738
1728 1739 if (f->f3.rs1 == f->f3.rd)
1729 1740 flags = FLG_P1(REG_NONE)|FLG_P2(REG_NONE)|FLG_NOIMM|
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1730 1741 FLG_P3(REG_INT);
1731 1742 else
1732 1743 flags = FLG_P1(REG_INT)|FLG_P2(REG_NONE)|FLG_NOIMM|
1733 1744 FLG_P3(REG_INT);
1734 1745
1735 1746 break;
1736 1747
1737 1748 case 0x10:
1738 1749 /* addcc */
1739 1750
1740 - if ((dhp->dh_debug & DIS_DEBUG_SYN_ALL) == 0)
1751 + if ((dhx->dhx_debug & DIS_DEBUG_SYN_ALL) == 0)
1741 1752 break;
1742 1753
1743 1754 if (f->f3.rs1 == f->f3.rd && f->f3.i == 1 &&
1744 1755 f->f3a.simm13 == 1) {
1745 1756 name = "inccc";
1746 1757 flags = FLG_P1(REG_NONE)|FLG_P2(REG_NONE)|FLG_NOIMM;
1747 1758 break;
1748 1759 }
1749 1760
1750 1761 if (f->f3.rs1 == f->f3.rd && f->f3.i == 1 &&
1751 1762 f->f3a.simm13 != 1) {
1752 1763 name = "inccc";
1753 1764 flags = FLG_P1(REG_NONE);
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1754 1765 break;
1755 1766 }
1756 1767 break;
1757 1768
1758 1769 case 0x11:
1759 1770 /* andcc */
1760 1771
1761 1772 if (f->f3.rd != 0)
1762 1773 break;
1763 1774
1764 - if ((dhp->dh_debug & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL))
1775 + if ((dhx->dhx_debug & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL))
1765 1776 == 0)
1766 1777 break;
1767 1778
1768 - if (((dhp->dh_debug & DIS_DEBUG_COMPAT) != 0) &&
1779 + if (((dhx->dhx_debug & DIS_DEBUG_COMPAT) != 0) &&
1769 1780 ((dhp->dh_flags & (DIS_SPARC_V9|DIS_SPARC_V9_SGI)) == 0))
1770 1781 break;
1771 1782
1772 1783 name = "btst";
1773 1784 flags = FLG_P1(REG_NONE);
1774 1785 f->f3.rd = f->f3.rs1;
1775 1786 break;
1776 1787
1777 1788 case 0x12:
1778 1789 /* orcc */
1779 1790
1780 - if ((dhp->dh_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT))
1791 + if ((dhx->dhx_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT))
1781 1792 == 0)
1782 1793 break;
1783 1794
1784 1795 if (f->f3.rs1 == 0 && f->f3.rd == 0 && f->f3.i == 0) {
1785 1796 name = "tst";
1786 1797 flags = FLG_P1(REG_NONE)|FLG_P3(REG_NONE);
1787 1798 break;
1788 1799 }
1789 1800
1790 1801 if (f->f3.rs2 == 0 && f->f3.rd == 0 && f->f3.i == 0) {
1791 1802 name = "tst";
1792 1803 flags = FLG_P2(REG_NONE)|FLG_P3(REG_NONE);
1793 1804 break;
1794 1805 }
1795 1806
1796 1807 break;
1797 1808
1798 1809 case 0x14:
1799 1810 /* subcc */
1800 1811
1801 - if ((dhp->dh_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT))
1812 + if ((dhx->dhx_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT))
1802 1813 == 0)
1803 1814 break;
1804 1815
1805 1816 if (f->f3.rd == 0) {
1806 1817 name = "cmp";
1807 1818 flags = FLG_P3(REG_NONE);
1808 1819 break;
1809 1820 }
1810 1821
1811 - if ((dhp->dh_debug & DIS_DEBUG_COMPAT) != 0)
1822 + if ((dhx->dhx_debug & DIS_DEBUG_COMPAT) != 0)
1812 1823 break;
1813 1824
1814 1825 if (f->f3.rs1 == f->f3.rd && f->f3.i == 1 &&
1815 1826 f->f3a.simm13 == 1) {
1816 1827 name = "deccc";
1817 1828 flags = FLG_P1(REG_NONE)|FLG_P2(REG_NONE)|FLG_NOIMM;
1818 1829 break;
1819 1830 }
1820 1831
1821 1832 if (f->f3.rs1 == f->f3.rd && f->f3.i == 1 &&
1822 1833 f->f3a.simm13 != 1) {
1823 1834 name = "deccc";
1824 1835 flags = FLG_P1(REG_NONE);
1825 1836 break;
1826 1837 }
1827 1838
1828 1839 break;
1829 1840
1830 1841 case 0x25:
1831 1842 case 0x26:
1832 1843 case 0x27:
1833 1844 return (prt_shift(dhp, instr, inp));
1834 1845
1835 1846 case 0x28:
1836 1847 case 0x29:
1837 1848 case 0x2a:
1838 1849 case 0x2b:
1839 1850 case 0x30:
1840 1851 case 0x31:
1841 1852 case 0x32:
1842 1853 case 0x33:
1843 1854 return (dis_fmt_rdwr(dhp, instr, inp, idx));
1844 1855
1845 1856 case 0x36:
1846 1857 case 0x37:
1847 1858 /* NOTE: overlayed on v9 */
1848 1859 if ((dhp->dh_flags & DIS_SPARC_V8) != 0)
1849 1860 return (fmt_cpop(dhp, instr, inp));
1850 1861 break;
1851 1862
1852 1863 case 0x38:
1853 1864 /* jmpl */
1854 1865 return (prt_jmpl(dhp, instr, inp, idx));
1855 1866
1856 1867 case 0x39:
1857 1868 /* rett / return */
1858 1869 prt_name(dhp, name, 1);
1859 1870 prt_address(dhp, instr, 1);
1860 1871 return (0);
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1861 1872
1862 1873 case 0x3b:
1863 1874 /* flush */
1864 1875 prt_name(dhp, name, 1);
1865 1876 prt_address(dhp, instr, 0);
1866 1877 return (0);
1867 1878
1868 1879 case 0x3c:
1869 1880 case 0x3d:
1870 1881 /* save / restore */
1871 - if ((dhp->dh_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT))
1882 + if ((dhx->dhx_debug & (DIS_DEBUG_SYN_ALL|DIS_DEBUG_COMPAT))
1872 1883 == 0)
1873 1884 break;
1874 1885
1875 1886 if (f->f3.rs1 != 0 || f->f3.rs2 != 0 || f->f3.rd != 0)
1876 1887 break;
1877 1888
1878 - if (f->f3.i != 0 && ((dhp->dh_debug & DIS_DEBUG_COMPAT) != 0))
1889 + if (f->f3.i != 0 && ((dhx->dhx_debug & DIS_DEBUG_COMPAT) != 0))
1879 1890 break;
1880 1891
1881 1892 prt_name(dhp, name, 0);
1882 1893 return (0);
1883 1894 }
1884 1895
1885 1896 if (FLG_P1_VAL(flags) != REG_NONE || FLG_P2_VAL(flags) != REG_NONE ||
1886 1897 FLG_P3_VAL(flags) != REG_NONE)
1887 1898 arg = 1;
1888 1899
1889 1900 prt_name(dhp, name, (arg != 0));
1890 1901 prt_aluargs(dhp, instr, flags);
1891 1902
1892 1903 return (0);
1893 1904 }
1894 1905
1895 1906 /* ARGSUSED1 */
1896 1907 int
1897 1908 fmt_regwin(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
1898 1909 {
1899 1910 prt_name(dhp, inp->in_data.in_def.in_name, 0);
1900 1911 return (0);
1901 1912 }
1902 1913
1903 1914 /* ARGSUSED1 */
1904 1915 int
1905 1916 fmt_trap_ret(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
1906 1917 {
1907 1918 ifmt_t *f = (ifmt_t *)&instr;
1908 1919 prt_name(dhp, inp->in_data.in_def.in_name, 1);
1909 1920
1910 1921 if (f->f3.rd == 0xf) {
1911 1922 /* jpriv */
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1912 1923 prt_address(dhp, instr, 1);
1913 1924 }
1914 1925
1915 1926 return (0);
1916 1927 }
1917 1928
1918 1929 /* ARGSUSED3 */
1919 1930 int
1920 1931 fmt_movcc(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
1921 1932 {
1933 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
1922 1934 ifmt_t *f = (ifmt_t *)&instr;
1923 1935 const char **regs = NULL;
1924 1936
1925 - if ((dhp->dh_debug & DIS_DEBUG_PRTFMT) != 0) {
1937 + if ((dhx->dhx_debug & DIS_DEBUG_PRTFMT) != 0) {
1926 1938 prt_field("op", f->f3c.op, 2);
1927 1939 prt_field("op3", f->f3c.op3, 6);
1928 1940 prt_field("cond", f->f3c.cond, 4);
1929 1941 prt_field("cc2", f->f3c.cc2, 1);
1930 1942 prt_field("cc", f->f3c.cc, 2);
1931 1943 prt_field("i", f->f3c.i, 1);
1932 1944
1933 1945 if (f->f3c.i == 0)
1934 1946 prt_field("rs2", f->f3.rs2, 5);
1935 1947 else
1936 1948 prt_field("simm11", f->f3c.simm11, 11);
1937 1949
1938 1950 prt_field("rd", f->f3.rd, 5);
1939 1951 }
1940 1952
1941 1953 if (f->f3c.cc2 == 0) {
1942 1954 regs = fcc_names;
1943 1955 } else {
1944 1956 regs = icc_names;
1945 1957 if (regs[f->f3c.cc] == NULL)
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1946 1958 return (-1);
1947 1959 }
1948 1960
1949 1961 prt_name(dhp, inp->in_data.in_def.in_name, 1);
1950 1962
1951 1963 bprintf(dhp, "%s, ", regs[f->f3c.cc]);
1952 1964
1953 1965 if (f->f3c.i == 1)
1954 1966 prt_imm(dhp, sign_extend(f->f3c.simm11, 11), IMM_SIGNED);
1955 1967 else
1956 - (void) strlcat(dhp->dh_buf, reg_names[f->f3.rs2],
1957 - dhp->dh_buflen);
1968 + (void) strlcat(dhx->dhx_buf, reg_names[f->f3.rs2],
1969 + dhx->dhx_buflen);
1958 1970
1959 1971 bprintf(dhp, ", %s", reg_names[f->f3.rd]);
1960 1972
1961 1973 return (0);
1962 1974 }
1963 1975
1964 1976 /* ARGSUSED3 */
1965 1977 int
1966 1978 fmt_movr(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
1967 1979 {
1980 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
1968 1981 ifmt_t *f = (ifmt_t *)&instr;
1969 1982
1970 1983 prt_name(dhp, inp->in_data.in_def.in_name, 1);
1971 1984
1972 1985 bprintf(dhp, "%s, ", reg_names[f->f3d.rs1]);
1973 1986
1974 1987 if (f->f3d.i == 1)
1975 1988 prt_imm(dhp, sign_extend(f->f3d.simm10, 10), IMM_SIGNED);
1976 1989 else
1977 - (void) strlcat(dhp->dh_buf, reg_names[f->f3.rs2],
1978 - dhp->dh_buflen);
1990 + (void) strlcat(dhx->dhx_buf, reg_names[f->f3.rs2],
1991 + dhx->dhx_buflen);
1979 1992
1980 1993 bprintf(dhp, ", %s", reg_names[f->f3.rd]);
1981 1994
1982 1995 return (0);
1983 1996 }
1984 1997
1985 1998 /* ARGSUSED3 */
1986 1999 int
1987 2000 fmt_fpop1(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
1988 2001 {
2002 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
1989 2003 ifmt_t *f = (ifmt_t *)&instr;
1990 2004 int flags = inp->in_data.in_def.in_flags;
1991 2005
1992 2006 flags |= FLG_NOIMM;
1993 2007
1994 - if ((dhp->dh_debug & DIS_DEBUG_PRTFMT) != 0) {
2008 + if ((dhx->dhx_debug & DIS_DEBUG_PRTFMT) != 0) {
1995 2009 prt_field("op", f->f3.op, 2);
1996 2010 prt_field("op3", f->f3.op3, 6);
1997 2011 prt_field("opf", f->fcmp.opf, 9);
1998 2012 prt_field("rs1", f->f3.rs1, 5);
1999 2013 prt_field("rs2", f->f3.rs2, 5);
2000 2014 prt_field("rd", f->f3.rd, 5);
2001 2015 }
2002 2016
2003 2017 prt_name(dhp, inp->in_data.in_def.in_name, 1);
2004 2018 prt_aluargs(dhp, instr, flags);
2005 2019
2006 2020 return (0);
2007 2021 }
2008 2022
2009 2023 int
2010 2024 fmt_fpop2(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
2011 2025 {
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2012 2026 static const char *condstr_icc[16] = {
2013 2027 "n", "e", "le", "l", "leu", "lu", "neg", "vs",
2014 2028 "a", "nz", "g", "ge", "gu", "geu", "pos", "vc"
2015 2029 };
2016 2030
2017 2031 static const char *condstr_fcc[16] = {
2018 2032 "n", "nz", "lg", "ul", "l", "ug", "g", "u",
2019 2033 "a", "e", "ue", "ge", "uge", "le", "ule", "o"
2020 2034 };
2021 2035
2036 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
2022 2037 ifmt_t *f = (ifmt_t *)&instr;
2023 2038 const char *ccstr = "";
2024 2039 char name[15];
2025 2040
2026 2041 int flags = inp->in_data.in_def.in_flags;
2027 2042 int is_cmp = (idx == 0x51 || idx == 0x52 || idx == 0x53 ||
2028 2043 idx == 0x55 || idx == 0x56 || idx == 0x57);
2029 2044 int is_fmov = (idx & 0x3f);
2030 2045 int is_v9 = ((dhp->dh_flags & (DIS_SPARC_V9|DIS_SPARC_V9_SGI)) != 0);
2031 - int is_compat = ((dhp->dh_debug & DIS_DEBUG_COMPAT) != 0);
2046 + int is_compat = ((dhx->dhx_debug & DIS_DEBUG_COMPAT) != 0);
2032 2047
2033 2048 int p_cc = 0;
2034 2049
2035 2050 is_fmov = (is_fmov == 0x1 || is_fmov == 0x2 || is_fmov == 0x3);
2036 2051
2037 - if ((dhp->dh_debug & DIS_DEBUG_PRTFMT) != 0) {
2052 + if ((dhx->dhx_debug & DIS_DEBUG_PRTFMT) != 0) {
2038 2053 prt_field("op", f->f3.op, 2);
2039 2054 prt_field("op3", f->f3.op3, 6);
2040 2055 prt_field("opf", f->fcmp.opf, 9);
2041 2056
2042 2057 switch (idx & 0x3f) {
2043 2058 case 0x51:
2044 2059 case 0x52:
2045 2060 case 0x53:
2046 2061 case 0x55:
2047 2062 case 0x56:
2048 2063 case 0x57:
2049 2064 prt_field("cc", f->fcmp.cc, 2);
2050 2065 prt_field("rs1", f->f3.rs1, 5);
2051 2066 prt_field("rs2", f->f3.rs2, 5);
2052 2067 break;
2053 2068
2054 2069 case 0x01:
2055 2070 case 0x02:
2056 2071 case 0x03:
2057 2072 prt_field("opf_low", f->fmv.opf, 6);
2058 2073 prt_field("cond", f->fmv.cond, 4);
2059 2074 prt_field("opf_cc", f->fmv.cc, 3);
2060 2075 prt_field("rs2", f->fmv.rs2, 5);
2061 2076 break;
2062 2077
2063 2078 default:
2064 2079 prt_field("rs1", f->f3.rs1, 5);
2065 2080 prt_field("rs2", f->f3.rs2, 5);
2066 2081 prt_field("rd", f->f3.rd, 5);
2067 2082 }
2068 2083 }
2069 2084
2070 2085 name[0] = '\0';
2071 2086 (void) strlcat(name, inp->in_data.in_def.in_name, sizeof (name));
2072 2087
2073 2088 if (is_fmov != 0) {
2074 2089 (void) strlcat(name,
2075 2090 (f->fmv.cc < 4) ? condstr_fcc[f->fmv.cond]
2076 2091 : condstr_icc[f->fmv.cond],
2077 2092 sizeof (name));
2078 2093 }
2079 2094
2080 2095 prt_name(dhp, name, 1);
2081 2096
2082 2097 if (is_cmp != 0)
2083 2098 ccstr = fcc_names[f->fcmp.cc];
2084 2099
2085 2100 if (is_fmov != 0)
2086 2101 ccstr = (f->fmv.cc < 4) ? fcc_names[f->fmv.cc & 0x3]
2087 2102 : icc_names[f->fmv.cc & 0x3];
2088 2103
2089 2104 if (ccstr == NULL)
2090 2105 return (-1);
2091 2106
2092 2107 p_cc = (is_compat == 0 || is_v9 != 0 ||
2093 2108 (is_cmp != 0 && f->fcmp.cc != 0) ||
2094 2109 (is_fmov != 0 && f->fmv.cc != 0));
2095 2110
2096 2111 if (p_cc != 0)
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2097 2112 bprintf(dhp, "%s, ", ccstr);
2098 2113
2099 2114 prt_aluargs(dhp, instr, flags);
2100 2115
2101 2116 return (0);
2102 2117 }
2103 2118
2104 2119 int
2105 2120 fmt_vis(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
2106 2121 {
2122 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
2107 2123 ifmt_t *f = (ifmt_t *)&instr;
2108 2124 int flags = inp->in_data.in_def.in_flags;
2109 2125
2110 - if ((dhp->dh_debug & DIS_DEBUG_PRTFMT) != 0) {
2126 + if ((dhx->dhx_debug & DIS_DEBUG_PRTFMT) != 0) {
2111 2127 prt_field("op", f->f3.op, 2);
2112 2128 prt_field("op3", f->f3.op3, 6);
2113 2129 prt_field("opf", f->fcmp.opf, 9);
2114 2130
2115 2131 if (idx == 0x081) {
2116 2132 prt_field("mode", instr & 02L, 2);
2117 2133 } else {
2118 2134 prt_field("rs1", f->f3.rs1, 5);
2119 2135 prt_field("rs2", f->f3.rs2, 5);
2120 2136 prt_field("rd", f->f3.rd, 5);
2121 2137 }
2122 2138 }
2123 2139
2124 2140 prt_name(dhp, inp->in_data.in_def.in_name, 1);
2125 2141
2126 2142 if (idx == 0x081) {
2127 2143 /* siam */
2128 2144 bprintf(dhp, "%d", instr & 0x7L);
2129 2145 return (0);
2130 2146 }
2131 2147
2132 2148 prt_aluargs(dhp, instr, flags);
2133 2149
2134 2150 return (0);
2135 2151 }
2136 2152
2137 2153 /* ARGSUSED3 */
2138 2154 int
2139 2155 fmt_fused(dis_handle_t *dhp, uint32_t instr, const inst_t *inp, int idx)
2140 2156 {
2141 2157 ifmt_t *f = (ifmt_t *)&instr;
2142 2158 int flags = inp->in_data.in_def.in_flags;
2143 2159
2144 2160 prt_name(dhp, inp->in_data.in_def.in_name, 1);
2145 2161 bprintf(dhp, "%s, %s, %s, %s",
2146 2162 get_regname(dhp, FLG_P1_VAL(flags), f->fused.rs1),
2147 2163 get_regname(dhp, FLG_P1_VAL(flags), f->fused.rs2),
2148 2164 get_regname(dhp, FLG_P1_VAL(flags), f->fused.rs3),
2149 2165 get_regname(dhp, FLG_P1_VAL(flags), f->fused.rd));
2150 2166
2151 2167 return (0);
2152 2168 }
2153 2169 /*
2154 2170 * put name into the output buffer
2155 2171 * if add_space !=0, append a space after it
2156 2172 */
2157 2173 static void
2158 2174 prt_name(dis_handle_t *dhp, const char *name, int add_space)
2159 2175 {
2160 2176 bprintf(dhp, (add_space == 0) ? "%s" : "%-9s ", name);
2161 2177 }
2162 2178
2163 2179 /*
2164 2180 * For debugging, print out a field of the instruction
2165 2181 * field is the name of the field
2166 2182 * val is the value of the field
2167 2183 * len is the length of the field (in bits)
2168 2184 */
2169 2185 #if defined(DIS_STANDALONE)
2170 2186 /* ARGSUSED */
2171 2187 static void
2172 2188 prt_field(const char *field, uint32_t val, int len)
2173 2189 {
2174 2190
2175 2191 }
2176 2192
2177 2193 #else
2178 2194 static void
2179 2195 prt_field(const char *field, uint32_t val, int len)
2180 2196 {
2181 2197 (void) fprintf(stderr, "DISASM: %8s = 0x%-8x (", field, val);
2182 2198 prt_binary(val, len);
2183 2199 (void) fprintf(stderr, ")\n");
2184 2200 }
2185 2201 #endif /* DIS_STANDALONE */
2186 2202
2187 2203 /*
2188 2204 * sign extend a val (that is 'bits' bits in length) to a 32-bit signed
2189 2205 * integer
2190 2206 */
2191 2207 static int32_t
2192 2208 sign_extend(int32_t val, int32_t bits)
2193 2209 {
2194 2210 if ((val & (1L << (bits - 1))) == 0)
2195 2211 return (val);
2196 2212
2197 2213 return ((-1L << bits) | val);
2198 2214 }
2199 2215
2200 2216 /*
2201 2217 * print out an immediate (i.e. constant) value
2202 2218 * val is the value
2203 2219 * format indicates if it is:
2204 2220 * 0 Unsigned
2205 2221 * IMM_SIGNED A signed value (prepend +/- to the value)
2206 2222 * IMM_ADDR Part of an address expression (prepend +/- but with a space
2207 2223 * between the sign and the value for things like [%i1 + 0x55]
2208 2224 */
2209 2225 static void
2210 2226 prt_imm(dis_handle_t *dhp, uint32_t val, int format)
2211 2227 {
2212 2228 const char *fmtstr = NULL;
2213 2229 int32_t sv = (int32_t)val;
2214 2230 int octal = dhp->dh_flags & DIS_OCTAL;
2215 2231
2216 2232 switch (format) {
2217 2233 case IMM_ADDR:
2218 2234 if (sv < 0) {
2219 2235 sv = -sv;
2220 2236 fmtstr = (octal != 0) ? "- 0%lo" : "- 0x%lx";
2221 2237 } else {
2222 2238 fmtstr = (octal != 0) ? "+ 0%lo" : "+ 0x%lx";
2223 2239 }
2224 2240 break;
2225 2241
2226 2242 case IMM_SIGNED:
2227 2243 if (sv < 0) {
2228 2244 sv = -sv;
2229 2245 fmtstr = (octal != 0) ? "-0%lo" : "-0x%lx";
2230 2246 break;
2231 2247 }
2232 2248 /* fall through */
2233 2249
2234 2250 default:
2235 2251 fmtstr = (octal != 0) ? "0%lo" : "0x%lx";
2236 2252 }
2237 2253
2238 2254 bprintf(dhp, fmtstr, sv);
2239 2255 }
2240 2256
2241 2257 /*
2242 2258 * return the symbolic name of a register
2243 2259 * regset is one of the REG_* values indicating which type of register it is
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2244 2260 * such as integer, floating point, etc.
2245 2261 * idx is the numeric value of the register
2246 2262 *
2247 2263 * If regset is REG_NONE, an empty, but non-NULL string is returned
2248 2264 * NULL may be returned if the index indicates an invalid register value
2249 2265 * such as with the %icc/%xcc sets
2250 2266 */
2251 2267 static const char *
2252 2268 get_regname(dis_handle_t *dhp, int regset, uint32_t idx)
2253 2269 {
2270 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
2254 2271 const char *regname = NULL;
2255 2272
2256 2273 switch (regset) {
2257 2274 case REG_INT:
2258 2275 regname = reg_names[idx];
2259 2276 break;
2260 2277
2261 2278 case REG_FP:
2262 2279 regname = freg_names[idx];
2263 2280 break;
2264 2281
2265 2282 case REG_FPD:
2266 - if (((dhp->dh_debug & DIS_DEBUG_COMPAT) == 0) ||
2283 + if (((dhx->dhx_debug & DIS_DEBUG_COMPAT) == 0) ||
2267 2284 ((dhp->dh_flags & (DIS_SPARC_V9|DIS_SPARC_V9_SGI)) != 0))
2268 2285 regname = fdreg_names[idx];
2269 2286 else
2270 2287 regname = compat_fdreg_names[idx];
2271 2288
2272 2289 break;
2273 2290
2274 2291 case REG_FPQ:
2275 - if ((dhp->dh_debug & DIS_DEBUG_COMPAT) == 0)
2292 + if ((dhx->dhx_debug & DIS_DEBUG_COMPAT) == 0)
2276 2293 regname = fqreg_names[idx];
2277 2294 else
2278 2295 regname = freg_names[idx];
2279 2296
2280 2297 break;
2281 2298
2282 2299 case REG_CP:
2283 2300 regname = cpreg_names[idx];
2284 2301 break;
2285 2302
2286 2303 case REG_ICC:
2287 2304 regname = icc_names[idx];
2288 2305 break;
2289 2306
2290 2307 case REG_FCC:
2291 2308 regname = fcc_names[idx];
2292 2309 break;
2293 2310
2294 2311 case REG_FSR:
2295 2312 regname = "%fsr";
2296 2313 break;
2297 2314
2298 2315 case REG_CSR:
2299 2316 regname = "%csr";
2300 2317 break;
2301 2318
2302 2319 case REG_CQ:
2303 2320 regname = "%cq";
2304 2321 break;
2305 2322
2306 2323 case REG_NONE:
2307 2324 regname = "";
2308 2325 break;
2309 2326 }
2310 2327
2311 2328 return (regname);
2312 2329 }
2313 2330
2314 2331 /*
2315 2332 * output the asi value from the instruction
2316 2333 *
2317 2334 * TODO: investigate if this should perhaps have a mask -- are undefined ASI
2318 2335 * values for an instruction still disassembled??
2319 2336 */
2320 2337 static void
2321 2338 prt_asi(dis_handle_t *dhp, uint32_t instr)
2322 2339 {
2323 2340 ifmt_t *f = (ifmt_t *)&instr;
2324 2341 int octal = ((dhp->dh_flags & DIS_OCTAL) != 0);
2325 2342
2326 2343 if (f->f3.i != 0)
2327 2344 bprintf(dhp, "%%asi");
2328 2345 else
2329 2346 bprintf(dhp, (octal != 0) ? "0%03o" : "0x%02x", f->f3.asi);
2330 2347
2331 2348 }
2332 2349
2333 2350 /*
2334 2351 * put an address expression into the output buffer
2335 2352 *
2336 2353 * instr is the instruction to use
2337 2354 * if nobrackets != 0, [] are not added around the instruction
2338 2355 *
2339 2356 * Currently this option is set when printing out the address portion
2340 2357 * of a jmpl instruction, but otherwise 0 for load/stores
2341 2358 *
2342 2359 * If no debug flags are set, the full expression is output, even when
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2343 2360 * %g0 or 0x0 appears in the address
2344 2361 *
2345 2362 * If DIS_DEBUG_SYN_ALL or DIS_DEBUG_COMPAT are set, when %g0 or 0x0
2346 2363 * appear in the address, they are not output. If the wierd (and probably
2347 2364 * shouldn't happen) address of [%g0 + %g0] or [%g0 + 0x0] is encountered,
2348 2365 * [%g0] is output
2349 2366 */
2350 2367 static void
2351 2368 prt_address(dis_handle_t *dhp, uint32_t instr, int nobrackets)
2352 2369 {
2370 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
2353 2371 ifmt_t *f = (ifmt_t *)&instr;
2354 2372 int32_t simm13;
2355 2373 int octal = ((dhp->dh_flags & DIS_OCTAL) != 0);
2356 - int p1 = ((dhp->dh_debug & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL)) == 0);
2357 - int p2 = ((dhp->dh_debug & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL)) == 0);
2374 + int p1 = ((dhx->dhx_debug & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL)) == 0);
2375 + int p2 = ((dhx->dhx_debug & (DIS_DEBUG_COMPAT|DIS_DEBUG_SYN_ALL)) == 0);
2358 2376
2359 2377 if (f->f3a.i == 0) {
2360 2378 p1 |= ((f->f3a.rs1 != 0) || f->f3.rs2 == 0);
2361 2379 p2 |= (f->f3.rs2 != 0);
2362 2380
2363 2381 bprintf(dhp, "%s%s%s%s%s",
2364 2382 (nobrackets == 0) ? "[" : "",
2365 2383 (p1 != 0) ? reg_names[f->f3a.rs1] : "",
2366 2384 (p1 != 0 && p2 != 0) ? " + " : "",
2367 2385 (p2 != 0) ? reg_names[f->f3.rs2] : "",
2368 2386 (nobrackets == 0) ? "]" : "");
2369 2387 } else {
2370 2388 const char *sign;
2371 2389
2372 2390 simm13 = sign_extend(f->f3a.simm13, 13);
2373 2391 sign = (simm13 < 0) ? "-" : "+";
2374 2392
2375 2393 p1 |= (f->f3a.rs1 != 0);
2376 2394 p2 |= (p1 == 0 || simm13 != 0);
2377 2395
2378 2396 if (p1 == 0 && simm13 == 0)
2379 2397 p2 = 1;
2380 2398
2381 2399 if (p1 == 0 && simm13 >= 0)
2382 2400 sign = "";
2383 2401
2384 2402 if (p2 != 0)
2385 2403 bprintf(dhp,
2386 2404 (octal != 0) ? "%s%s%s%s%s0%lo%s" :
2387 2405 "%s%s%s%s%s0x%lx%s",
2388 2406 (nobrackets == 0) ? "[" : "",
2389 2407 (p1 != 0) ? reg_names[f->f3a.rs1] : "",
2390 2408 (p1 != 0) ? " " : "",
2391 2409 sign,
2392 2410 (p1 != 0) ? " " : "",
2393 2411 (simm13 < 0) ? -(simm13) : simm13,
2394 2412 (nobrackets == 0) ? "]" : "");
2395 2413 else
2396 2414 bprintf(dhp, "%s%s%s",
2397 2415 (nobrackets == 0) ? "[" : "",
2398 2416 reg_names[f->f3a.rs1],
2399 2417 (nobrackets == 0) ? "]" : "");
2400 2418 }
2401 2419 }
2402 2420
2403 2421 /*
2404 2422 * print out the arguments to an alu operation (add, sub, etc.)
2405 2423 * conatined in 'instr'
2406 2424 *
2407 2425 * alu instructions have the following format:
2408 2426 * %rs1, %rs2, %rd (i == 0)
2409 2427 * %rs1, 0xnnn, %rd (i == 1)
2410 2428 * ^ ^ ^
2411 2429 * | | |
2412 2430 * p1 p2 p3
2413 2431 *
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2414 2432 * flags indicates the register set to use for each position (p1, p2, p3)
2415 2433 * as well as if immediate values (i == 1) are allowed
2416 2434 *
2417 2435 * if flags indicates a specific position has REG_NONE set as it's register
2418 2436 * set, it is omitted from the output. This is primarly used for certain
2419 2437 * floating point operations
2420 2438 */
2421 2439 static void
2422 2440 prt_aluargs(dis_handle_t *dhp, uint32_t instr, uint32_t flags)
2423 2441 {
2442 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
2424 2443 ifmt_t *f = (ifmt_t *)&instr;
2425 2444 const char *r1, *r2, *r3;
2426 2445 int p1, p2, p3;
2427 2446 unsigned int opf = 0;
2428 2447
2429 2448 r1 = get_regname(dhp, FLG_P1_VAL(flags), f->f3.rs1);
2430 2449 r2 = get_regname(dhp, FLG_P2_VAL(flags), f->f3.rs2);
2431 2450 r3 = get_regname(dhp, FLG_P3_VAL(flags), f->f3.rd);
2432 2451
2433 2452 p1 = (FLG_P1_VAL(flags) != REG_NONE);
2434 2453 p2 = (((flags & FLG_NOIMM) == 0) || (FLG_P2_VAL(flags) != REG_NONE));
2435 2454 p3 = (FLG_RD_VAL(flags) != REG_NONE);
2436 2455
2437 2456 if (r1 == NULL || r1[0] == '\0')
2438 2457 p1 = 0;
2439 2458
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2440 2459 if (f->f3a.i == 0 && (r2 == NULL || r2[0] == '\0'))
2441 2460 p2 = 0;
2442 2461
2443 2462 if (r3 == NULL || r3[0] == '\0')
2444 2463 p3 = 0;
2445 2464
2446 2465 if ((f->fcmp.op == 2) && (f->fcmp.op3 == 0x36) && (f->fcmp.cc != 0))
2447 2466 opf = f->fcmp.opf;
2448 2467
2449 2468 if ((opf == 0x151) || (opf == 0x152)) {
2450 - (void) strlcat(dhp->dh_buf, r3, dhp->dh_buflen);
2451 - (void) strlcat(dhp->dh_buf, ", ", dhp->dh_buflen);
2469 + (void) strlcat(dhx->dhx_buf, r3, dhx->dhx_buflen);
2470 + (void) strlcat(dhx->dhx_buf, ", ", dhx->dhx_buflen);
2452 2471 p3 = 0;
2453 2472 }
2454 2473
2455 2474 if (p1 != 0) {
2456 - (void) strlcat(dhp->dh_buf, r1, dhp->dh_buflen);
2475 + (void) strlcat(dhx->dhx_buf, r1, dhx->dhx_buflen);
2457 2476 if (p2 != 0 || p3 != 0)
2458 - (void) strlcat(dhp->dh_buf, ", ", dhp->dh_buflen);
2477 + (void) strlcat(dhx->dhx_buf, ", ", dhx->dhx_buflen);
2459 2478 }
2460 2479
2461 2480 if (p2 != 0) {
2462 2481 if (f->f3.i == 0 || ((flags & FLG_NOIMM) != 0))
2463 - (void) strlcat(dhp->dh_buf, r2, dhp->dh_buflen);
2482 + (void) strlcat(dhx->dhx_buf, r2, dhx->dhx_buflen);
2464 2483 else
2465 2484 prt_imm(dhp, sign_extend(f->f3a.simm13, 13),
2466 2485 IMM_SIGNED);
2467 2486
2468 2487 if (p3 != 0)
2469 - (void) strlcat(dhp->dh_buf, ", ", dhp->dh_buflen);
2488 + (void) strlcat(dhx->dhx_buf, ", ", dhx->dhx_buflen);
2470 2489 }
2471 2490
2472 2491 if (p3 != 0)
2473 - (void) strlcat(dhp->dh_buf, r3, dhp->dh_buflen);
2492 + (void) strlcat(dhx->dhx_buf, r3, dhx->dhx_buflen);
2474 2493 }
2475 2494
2476 2495 static const char *
2477 2496 get_asi_name(uint8_t asi)
2478 2497 {
2479 2498 switch (asi) {
2480 2499 case 0x04:
2481 2500 return ("ASI_N");
2482 2501
2483 2502 case 0x0c:
2484 2503 return ("ASI_NL");
2485 2504
2486 2505 case 0x10:
2487 2506 return ("ASI_AIUP");
2488 2507
2489 2508 case 0x11:
2490 2509 return ("ASI_AIUS");
2491 2510
2492 2511 case 0x14:
2493 2512 return ("ASI_REAL");
2494 2513
2495 2514 case 0x15:
2496 2515 return ("ASI_REAL_IO");
2497 2516
2498 2517 case 0x16:
2499 2518 return ("ASI_BLK_AIUP");
2500 2519
2501 2520 case 0x17:
2502 2521 return ("ASI_BLK_AIUS");
2503 2522
2504 2523 case 0x18:
2505 2524 return ("ASI_AIUPL");
2506 2525
2507 2526 case 0x19:
2508 2527 return ("ASI_AIUSL");
2509 2528
2510 2529 case 0x1c:
2511 2530 return ("ASI_REAL_L");
2512 2531
2513 2532 case 0x1d:
2514 2533 return ("ASI_REAL_IO_L");
2515 2534
2516 2535 case 0x1e:
2517 2536 return ("ASI_BLK_AIUPL");
2518 2537
2519 2538 case 0x1f:
2520 2539 return ("ASI_BLK_AIUS_L");
2521 2540
2522 2541 case 0x20:
2523 2542 return ("ASI_SCRATCHPAD");
2524 2543
2525 2544 case 0x21:
2526 2545 return ("ASI_MMU_CONTEXTID");
2527 2546
2528 2547 case 0x22:
2529 2548 return ("ASI_TWINX_AIUP");
2530 2549
2531 2550 case 0x23:
2532 2551 return ("ASI_TWINX_AIUS");
2533 2552
2534 2553 case 0x25:
2535 2554 return ("ASI_QUEUE");
2536 2555
2537 2556 case 0x26:
2538 2557 return ("ASI_TWINX_R");
2539 2558
2540 2559 case 0x27:
2541 2560 return ("ASI_TWINX_N");
2542 2561
2543 2562 case 0x2a:
2544 2563 return ("ASI_LDTX_AIUPL");
2545 2564
2546 2565 case 0x2b:
2547 2566 return ("ASI_TWINX_AIUS_L");
2548 2567
2549 2568 case 0x2e:
2550 2569 return ("ASI_TWINX_REAL_L");
2551 2570
2552 2571 case 0x2f:
2553 2572 return ("ASI_TWINX_NL");
2554 2573
2555 2574 case 0x30:
2556 2575 return ("ASI_AIPP");
2557 2576
2558 2577 case 0x31:
2559 2578 return ("ASI_AIPS");
2560 2579
2561 2580 case 0x36:
2562 2581 return ("ASI_AIPN");
2563 2582
2564 2583 case 0x38:
2565 2584 return ("ASI_AIPP_L");
2566 2585
2567 2586 case 0x39:
2568 2587 return ("ASI_AIPS_L");
2569 2588
2570 2589 case 0x3e:
2571 2590 return ("ASI_AIPN_L");
2572 2591
2573 2592 case 0x41:
2574 2593 return ("ASI_CMT_SHARED");
2575 2594
2576 2595 case 0x4f:
2577 2596 return ("ASI_HYP_SCRATCHPAD");
2578 2597
2579 2598 case 0x50:
2580 2599 return ("ASI_IMMU");
2581 2600
2582 2601 case 0x52:
2583 2602 return ("ASI_MMU_REAL");
2584 2603
2585 2604 case 0x54:
2586 2605 return ("ASI_MMU");
2587 2606
2588 2607 case 0x55:
2589 2608 return ("ASI_ITLB_DATA_ACCESS_REG");
2590 2609
2591 2610 case 0x56:
2592 2611 return ("ASI_ITLB_TAG_READ_REG");
2593 2612
2594 2613 case 0x57:
2595 2614 return ("ASI_IMMU_DEMAP");
2596 2615
2597 2616 case 0x58:
2598 2617 return ("ASI_DMMU / ASI_UMMU");
2599 2618
2600 2619 case 0x5c:
2601 2620 return ("ASI_DTLB_DATA_IN_REG");
2602 2621
2603 2622 case 0x5d:
2604 2623 return ("ASI_DTLB_DATA_ACCESS_REG");
2605 2624
2606 2625 case 0x5e:
2607 2626 return ("ASI_DTLB_TAG_READ_REG");
2608 2627
2609 2628 case 0x5f:
2610 2629 return ("ASI_DMMU_DEMAP");
2611 2630
2612 2631 case 0x63:
2613 2632 return ("ASI_CMT_PER_STRAND / ASI_CMT_PER_CORE");
2614 2633
2615 2634 case 0x80:
2616 2635 return ("ASI_P");
2617 2636
2618 2637 case 0x81:
2619 2638 return ("ASI_S");
2620 2639
2621 2640 case 0x82:
2622 2641 return ("ASI_PNF");
2623 2642
2624 2643 case 0x83:
2625 2644 return ("ASI_SNF");
2626 2645
2627 2646 case 0x88:
2628 2647 return ("ASI_PL");
2629 2648
2630 2649 case 0x89:
2631 2650 return ("ASI_SL");
2632 2651
2633 2652 case 0x8a:
2634 2653 return ("ASI_PNFL");
2635 2654
2636 2655 case 0x8b:
2637 2656 return ("ASI_SNFL");
2638 2657
2639 2658 case 0xc0:
2640 2659 return ("ASI_PST8_P");
2641 2660
2642 2661 case 0xc1:
2643 2662 return ("ASI_PST8_S");
2644 2663
2645 2664 case 0xc2:
2646 2665 return ("ASI_PST16_P");
2647 2666
2648 2667 case 0xc3:
2649 2668 return ("ASI_PST16_S");
2650 2669
2651 2670 case 0xc4:
2652 2671 return ("ASI_PST32_P");
2653 2672
2654 2673 case 0xc5:
2655 2674 return ("ASI_PST32_S");
2656 2675
2657 2676 case 0xc8:
2658 2677 return ("ASI_PST8_PL");
2659 2678
2660 2679 case 0xc9:
2661 2680 return ("ASI_PST8_SL");
2662 2681
2663 2682 case 0xca:
2664 2683 return ("ASI_PST16_PL");
2665 2684
2666 2685 case 0xcb:
2667 2686 return ("ASI_PST16_SL");
2668 2687
2669 2688 case 0xcc:
2670 2689 return ("ASI_PST32_PL");
2671 2690
2672 2691 case 0xcd:
2673 2692 return ("ASI_PST32_SL");
2674 2693
2675 2694 case 0xd0:
2676 2695 return ("ASI_FL8_P");
2677 2696
2678 2697 case 0xd1:
2679 2698 return ("ASI_FL8_S");
2680 2699
2681 2700 case 0xd2:
2682 2701 return ("ASI_FL16_P");
2683 2702
2684 2703 case 0xd3:
2685 2704 return ("ASI_FL16_S");
2686 2705
2687 2706 case 0xd8:
2688 2707 return ("ASI_FL8_PL");
2689 2708
2690 2709 case 0xd9:
2691 2710 return ("ASI_FL8_SL");
2692 2711
2693 2712 case 0xda:
2694 2713 return ("ASI_FL16_PL");
2695 2714
2696 2715 case 0xdb:
2697 2716 return ("ASI_FL16_SL");
2698 2717
2699 2718 case 0xe0:
2700 2719 return ("ASI_BLK_COMMIT_P");
2701 2720
2702 2721 case 0xe1:
2703 2722 return ("ASI_BLK_SOMMIT_S");
2704 2723
2705 2724 case 0xe2:
2706 2725 return ("ASI_TWINX_P");
2707 2726
2708 2727 case 0xe3:
2709 2728 return ("ASI_TWINX_S");
2710 2729
2711 2730 case 0xea:
2712 2731 return ("ASI_TWINX_PL");
2713 2732
2714 2733 case 0xeb:
2715 2734 return ("ASI_TWINX_SL");
2716 2735
2717 2736 case 0xf0:
2718 2737 return ("ASI_BLK_P");
2719 2738
2720 2739 case 0xf1:
2721 2740 return ("ASI_BLK_S");
2722 2741
2723 2742 case 0xf8:
2724 2743 return ("ASI_BLK_PL");
2725 2744
2726 2745 case 0xf9:
2727 2746 return ("ASI_BLK_SL");
2728 2747
2729 2748 default:
2730 2749 return (NULL);
2731 2750 }
2732 2751 }
2733 2752
2734 2753 /*
|
↓ open down ↓ |
251 lines elided |
↑ open up ↑ |
2735 2754 * just a handy function that takes care of managing the buffer length
2736 2755 * w/ printf
2737 2756 */
2738 2757
2739 2758 /*
2740 2759 * PRINTF LIKE 1
2741 2760 */
2742 2761 static void
2743 2762 bprintf(dis_handle_t *dhp, const char *fmt, ...)
2744 2763 {
2764 + dis_handle_sparc_t *dhx = dhp->dh_arch_private;
2745 2765 size_t curlen;
2746 2766 va_list ap;
2747 2767
2748 - curlen = strlen(dhp->dh_buf);
2768 + curlen = strlen(dhx->dhx_buf);
2749 2769
2750 2770 va_start(ap, fmt);
2751 - (void) vsnprintf(dhp->dh_buf + curlen, dhp->dh_buflen - curlen, fmt,
2771 + (void) vsnprintf(dhx->dhx_buf + curlen, dhx->dhx_buflen - curlen, fmt,
2752 2772 ap);
2753 2773 va_end(ap);
2754 2774 }
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