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          --- old/usr/src/man/man7i/termiox.7i
          +++ new/usr/src/man/man7i/termiox.7i
   1      -'\" te
   2    1  .\"  Copyright 1989 AT&T
   3    2  .\" Copyright (C) 1999, Sun Microsystems, Inc. All Rights Reserved
   4      -.\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License").  You may not use this file except in compliance with the License.
   5      -.\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing.  See the License for the specific language governing permissions and limitations under the License.
   6      -.\" When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE.  If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner]
   7      -.TH TERMIOX 7I "April 9, 2016"
   8      -.SH NAME
   9      -termiox \- extended general terminal interface
  10      -.SH DESCRIPTION
  11      -.LP
  12      -The extended general terminal interface supplements the \fBtermio\fR(7I)
        3 +.\" Copyright (c) 2017, Joyent, Inc.
        4 +.\" The contents of this file are subject to the terms of the
        5 +.\" Common Development and Distribution License (the "License").
        6 +.\" You may not use this file except in compliance with the License.
        7 +.\"
        8 +.\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
        9 +.\" or http://www.opensolaris.org/os/licensing.
       10 +.\" See the License for the specific language governing permissions
       11 +.\" and limitations under the License.
       12 +.\"
       13 +.\" When distributing Covered Code, include this CDDL HEADER in each
       14 +.\" file and include the License file at usr/src/OPENSOLARIS.LICENSE.
       15 +.\" If applicable, add the following below this CDDL HEADER, with the
       16 +.\" fields enclosed by brackets "[]" replaced with your own identifying
       17 +.\" information: Portions Copyright [yyyy] [name of copyright owner]
       18 +.Dd October 29, 2017
       19 +.Dt TERMIOX 7I
       20 +.Os
       21 +.Sh NAME
       22 +.Nm termiox
       23 +.Nd extended general terminal interface
       24 +.Sh DESCRIPTION
       25 +The extended general terminal interface supplements the
       26 +.Xr termio 7I
  13   27  general terminal interface by adding support for asynchronous hardware flow
  14   28  control, isochronous flow control and clock modes, and local implementations of
  15      -additional asynchronous features. Some systems may not support all of these
  16      -capabilities because of either hardware or software limitations.  Other systems
  17      -may not permit certain functions to be disabled.  In these cases the
  18      -appropriate bits will be ignored.  See <\fBsys/termiox.h\fR> for your system to
  19      -find out which capabilities are supported.
  20      -.SS "Hardware Flow Control Modes"
  21      -.LP
  22      -Hardware flow control supplements the \fBtermio\fR(7I) \fBIXON\fR, \fBIXOFF\fR,
  23      -and \fBIXANY\fR character flow control. Character flow control occurs when one
       29 +additional asynchronous features.
       30 +Some systems may not support all of these
       31 +capabilities because of either hardware or software limitations.
       32 +Other systems may not permit certain functions to be disabled.
       33 +In these cases the appropriate bits will be ignored.
       34 +See
       35 +.In sys/termiox.h
       36 +for your system to find out which capabilities are supported.
       37 +.Ss "Hardware Flow Control Modes"
       38 +Hardware flow control supplements the
       39 +.Xr termio 7I
       40 +.Dv IXON ,
       41 +.Dv IXOFF ,
       42 +and
       43 +.Dv IXANY
       44 +character flow control.
       45 +Character flow control occurs when one
  24   46  device controls the data transfer of another device by the insertion of control
  25      -characters in the data stream between devices.  Hardware flow control occurs
       47 +characters in the data stream between devices.
       48 +Hardware flow control occurs
  26   49  when one device controls the data transfer of another device using electrical
  27      -control signals on wires (circuits) of the asynchronous interface. Isochronous
       50 +control signals on wires (circuits) of the asynchronous interface.
       51 +Isochronous
  28   52  hardware flow control occurs when one device controls the data transfer of
  29      -another device by  asserting or removing the transmit clock signals of that
  30      -device.  Character flow control and hardware flow control may be simultaneously
       53 +another device by asserting or removing the transmit clock signals of that
       54 +device.
       55 +Character flow control and hardware flow control may be simultaneously
  31   56  set.
  32      -.sp
  33      -.LP
       57 +.Pp
  34   58  In asynchronous, full duplex applications, the use of the Electronic Industries
  35   59  Association's EIA-232-D Request To Send (RTS) and Clear To Send (CTS) circuits
  36      -is the  preferred method of hardware flow control.  An interface to other
       60 +is the preferred method of hardware flow control.
       61 +An interface to other
  37   62  hardware flow control methods is included to provide a standard interface to
  38   63  these existing methods.
  39      -.sp
  40      -.LP
  41      -The EIA-232-D standard specified only unidirectional hardware flow control -
       64 +.Pp
       65 +The EIA-232-D standard specified only unidirectional hardware flow control \(em
  42   66  the Data Circuit-terminating Equipment or Data Communications Equipment (DCE)
  43      -indicates to the Data Terminal Equipment (DTE) to stop transmitting data.   The
  44      -\fBtermiox\fR interface allows both unidirectional and bidirectional hardware
       67 +indicates to the Data Terminal Equipment (DTE) to stop transmitting data.
       68 +The
       69 +.Nm
       70 +interface allows both unidirectional and bidirectional hardware
  45   71  flow control; when bidirectional flow control is enabled, either the DCE or DTE
  46   72  can indicate to each other to stop transmitting data across the interface.
  47      -Note: It is assumed that the asynchronous port is configured as a DTE.  If the
       73 +Note: It is assumed that the asynchronous port is configured as a DTE.
       74 +If the
  48   75  connected device is also a DTE and not a DCE, then DTE to DTE (for example,
  49   76  terminal or printer connected to computer) hardware flow control is possible by
  50   77  using a null modem to interconnect the appropriate data and control circuits.
  51      -.SS "Clock Modes"
  52      -.LP
       78 +.Ss "Clock Modes"
  53   79  Isochronous communication is a variation of asynchronous communication whereby
  54   80  two communicating devices may provide transmit and/or receive clock signals to
  55      -one another. Incoming clock signals can be taken from the baud rate generator
  56      -on the local isochronous port controller, from CCITT V.24 circuit 114,
  57      -Transmitter Signal Element Timing - DCE source (EIA-232-D pin 15), or  from
  58      -CCITT V.24 circuit 115, Receiver Signal Element Timing - DCE source  (EIA-232-D
  59      -pin 17). Outgoing clock signals can be sent on CCITT V.24 circuit 113,
  60      -Transmitter Signal Element Timing - DTE source (EIA-232-D  pin 24), on CCITT
  61      -V.24 circuit 128, Receiver Signal Element Timing - DTE source (no EIA-232-D
       81 +one another.
       82 +Incoming clock signals can be taken from the baud rate generator
       83 +on the local isochronous port controller, from CCITT V\.24 circuit 114,
       84 +Transmitter Signal Element Timing - DCE source (EIA-232-D pin 15), or from
       85 +CITT V\.24 circuit 115, Receiver Signal Element Timing - DCE source (EIA-232-D
       86 +pin 17).
       87 +Outgoing clock signals can be sent on CCITT V\.24 circuit 113,
       88 +Transmitter Signal Element Timing - DTE source (EIA-232-D pin 24), on CCITT
       89 +V\.24 circuit 128, Receiver Signal Element Timing - DTE source (no EIA-232-D
  62   90  pin), or not sent at all.
  63      -.sp
  64      -.LP
       91 +.Pp
  65   92  In terms of clock modes, traditional asynchronous communication is implemented
  66   93  simply by using the local baud rate generator as the incoming transmit and
  67   94  receive clock source and not outputting any clock signals.
  68      -.SS "Terminal Parameters"
  69      -.LP
  70      -The parameters that control the behavior of devices providing the \fBtermiox\fR
  71      -interface are specified by the \fBtermiox\fR structure defined in the
  72      -<\fBsys/termiox.h\fR> header.  Several \fBioctl\fR(2) system calls that fetch
       95 +.Ss "Terminal Parameters"
       96 +The parameters that control the behavior of devices providing the
       97 +.Nm
       98 +interface are specified by the
       99 +.Vt termiox
      100 +structure defined in the
      101 +.In sys/termiox.h
      102 +header.
      103 +Several
      104 +.Xr ioctl 2
      105 +system calls that fetch
  73  106  or change these parameters use this structure:
  74      -.sp
  75      -.in +2
  76      -.nf
      107 +.Bd -literal -offset 2n
  77  108  #define NFF     5
  78  109  struct termiox  {
  79  110          unsigned short  x_hflag;       /* hardware flow control modes */
  80  111          unsigned short  x_cflag;       /* clock modes */
  81  112          unsigned short  x_rflag[NFF];  /* reserved modes */
  82  113          unsigned short  x_sflag;       /* spare local modes */
  83  114  };
  84      -.fi
  85      -.in -2
  86      -
  87      -.sp
  88      -.LP
  89      -The \fBx_hflag\fR field describes hardware flow control modes:
  90      -.sp
  91      -
  92      -.sp
  93      -.TS
  94      -l l l
  95      -l l l .
  96      -RTSXOFF         0000001 T{
  97      -Enable RTS hardware flow control on input.
  98      -T}
  99      -CTSXON          0000002 T{
 100      -Enable CTS hardware flow control on output.
 101      -T}
 102      -DTRXOFF         0000004 T{
 103      -Enable DTR hardware flow control on input.
 104      -T}
 105      -CDXON           0000010 T{
 106      -Enable CD hardware flow control on output.
 107      -T}
 108      -ISXOFF          0000020 T{
 109      -Enable isochronous hardware flow control on input
 110      -T}
 111      -.TE
 112      -
 113      -.sp
 114      -.LP
      115 +.Ed
      116 +.Pp
      117 +The
      118 +.Fa x_hflag
      119 +field describes hardware flow control modes:
      120 +.Bl -column xxxxxxx xxxxxxx x
      121 +.It Dv RTSXOFF Ta 0000001 Ta "Enable RTS hardware flow control on input."
      122 +.It Dv CTSXON Ta 0000002 Ta "Enable CTS hardware flow control on output."
      123 +.It Dv DTRXOFF Ta 0000004 Ta "Enable DTR hardware flow control on input."
      124 +.It Dv CDXON Ta 0000010 Ta "Enable CD hardware flow control on output."
      125 +.It Dv ISXOFF Ta 0000020 Ta "Enable isochronous hardware flow control on input."
      126 +.El
      127 +.Pp
 115  128  The EIA-232-D DTR and CD circuits are used to establish a connection between
 116      -two systems. The RTS circuit is also used to establish a connection with a
 117      -modem. Thus, both DTR and RTS are activated when an asynchronous port is
 118      -opened. If DTR is used for hardware flow control, then RTS must be used for
 119      -connectivity. If CD is used for hardware flow control, then CTS must be used
 120      -for connectivity. Thus, RTS and DTR (or CTS and CD) cannot both be used for
 121      -hardware flow control at the same time. Other mutual exclusions may apply, such
 122      -as the simultaneous setting of the \fBtermio\fR(7I) \fBHUPCL\fR and the
 123      -\fBtermiox\fR \fBDTRXOFF\fR bits, which use the DTE ready line for different
 124      -functions.
 125      -.sp
 126      -.LP
      129 +two systems.
      130 +The RTS circuit is also used to establish a connection with a modem.
      131 +Thus, both DTR and RTS are activated when an asynchronous port is opened.
      132 +If DTR is used for hardware flow control, then RTS must be used for
      133 +connectivity.
      134 +If CD is used for hardware flow control, then CTS must be used
      135 +for connectivity.
      136 +Thus, RTS and DTR (or CTS and CD) cannot both be used for
      137 +hardware flow control at the same time.
      138 +Other mutual exclusions may apply, such as the simultaneous setting of the
      139 +.Xr termio 7I
      140 +.Dv HUPCL
      141 +and the
      142 +.Vt termiox
      143 +.Dv DTRXOFF
      144 +bits, which use the DTE ready line for different functions.
      145 +.Pp
 127  146  Variations of different hardware flow control methods may be selected by
 128      -setting the appropriate bits. For example, bidirectional RTS/CTS flow
 129      -control is selected by setting both the \fBRTSXOFF\fR and \fBCTSXON\fR bits and
 130      -bidirectional DTR/CTS flow control is selected by setting both the
 131      -\fBDTRXOFF\fR and \fBCTSXON\fR. Modem control or unidirectional CTS hardware
 132      -flow control is selected by setting only the \fBCTSXON\fR bit.
 133      -.sp
 134      -.LP
      147 +setting the appropriate bits.
      148 +For example, bidirectional RTS/CTS flow control is selected by setting both the
      149 +.Dv RTSXOFF
      150 +and
      151 +.Dv CTSXON
      152 +bits and bidirectional DTR/CTS flow control is selected by setting both the
      153 +.Dv DTRXOFF
      154 +and
      155 +.Dv CTSXON .
      156 +Modem control or unidirectional CTS hardware
      157 +flow control is selected by setting only the
      158 +.Dv CTSXON
      159 +bit.
      160 +.Pp
 135  161  As previously mentioned, it is assumed that the local asynchronous port (for
 136      -example, computer) is configured as a DTE.  If the connected device (for
 137      -example,  printer) is also a DTE, it is assumed that the device is connected to
 138      -the computer's asynchronous port using a null modem that swaps control circuits
 139      -(typically RTS and CTS).  The connected DTE drives RTS and the null modem swaps
 140      -RTS  and CTS so that the remote RTS is received as CTS by the local DTE.  In
 141      -the case that \fBCTSXON\fR is set for hardware flow control, printer's lowering
 142      -of its RTS would cause CTS seen by the computer to be lowered.  Output to the
 143      -printer is suspended until the printer's raising of its RTS, which would cause
 144      -CTS seen by the computer to be raised.
 145      -.sp
 146      -.LP
 147      -If \fBRTSXOFF\fR is set, the Request To Send (RTS) circuit (line) will be
      162 +example, computer) is configured as a DTE.
      163 +If the connected device (for example, printer) is also a DTE, it is assumed
      164 +that the device is connected to the computer's asynchronous port using a null
      165 +modem that swaps control circuits (typically RTS and CTS).
      166 +The connected DTE drives RTS and the null modem swaps
      167 +RTS and CTS so that the remote RTS is received as CTS by the local DTE.
      168 +In the case that
      169 +.Dv CTSXON
      170 +is set for hardware flow control, printer's lowering
      171 +of its RTS would cause CTS seen by the computer to be lowered.
      172 +Output to the printer is suspended until the printer's raising of its RTS,
      173 +which would cause CTS seen by the computer to be raised.
      174 +.Pp
      175 +If
      176 +.Dv RTSXOFF
      177 +is set, the Request To Send (RTS) circuit (line) will be
 148  178  raised, and if the asynchronous port needs to have its input stopped, it will
 149      -lower the Request To Send (RTS) line. If the RTS line is lowered, it is assumed
      179 +lower the Request To Send (RTS) line.
      180 +If the RTS line is lowered, it is assumed
 150  181  that the connected device will stop its output until RTS is raised.
 151      -.sp
 152      -.LP
 153      -If \fBCTSXON\fR is set, output will occur only if the Clear To Send (CTS)
 154      -circuit (line) is raised by the connected device. If the CTS line is lowered by
      182 +.Pp
      183 +If
      184 +.Dv CTSXON
      185 +is set, output will occur only if the Clear To Send (CTS)
      186 +circuit (line) is raised by the connected device.
      187 +If the CTS line is lowered by
 155  188  the connected device, output is suspended until CTS is raised.
 156      -.sp
 157      -.LP
 158      -If \fBDTRXOFF\fR is set, the DTE Ready (DTR) circuit (line) will be raised, and
      189 +.Pp
      190 +If
      191 +.Dv DTRXOFF
      192 +is set, the DTE Ready (DTR) circuit (line) will be raised, and
 159  193  if the asynchronous port needs to have its input stopped, it will lower the DTE
 160      -Ready (DTR) line. If the DTR line is lowered, it is assumed that the connected
      194 +Ready (DTR) line.
      195 +If the DTR line is lowered, it is assumed that the connected
 161  196  device will stop its output until DTR is raised.
 162      -.sp
 163      -.LP
 164      -If \fBCDXON\fR is set, output will occur only if the Received Line Signal
 165      -Detector (CD) circuit (line) is raised by the connected device. If the CD line
      197 +.Pp
      198 +If
      199 +.Dv CDXON
      200 +is set, output will occur only if the Received Line Signal
      201 +Detector (CD) circuit (line) is raised by the connected device.
      202 +If the CD line
 166  203  is lowered by the connected device, output is suspended until CD is raised.
 167      -.sp
 168      -.LP
 169      -If \fBISXOFF\fR is set, and if the isochronous port needs to have its input
 170      -stopped, it will stop the outgoing clock signal. It is assumed that the
 171      -connected device is using this clock signal to create its output. Transit and
 172      -receive clock sources are programmed using the \fBx_cflag\fR fields. If the
 173      -port is not programmed for external clock generation, \fBISXOFF\fR is ignored.
      204 +.Pp
      205 +If
      206 +.Dv ISXOFF
      207 +is set, and if the isochronous port needs to have its input
      208 +stopped, it will stop the outgoing clock signal.
      209 +It is assumed that the
      210 +connected device is using this clock signal to create its output.
      211 +Transit and receive clock sources are programmed using the
      212 +.Fa x_cflag
      213 +fields.
      214 +If the port is not programmed for external clock generation,
      215 +.Dv ISXOFF
      216 +is ignored.
 174  217  Output isochronous flow control is supported by appropriate clock source
 175      -programming using the \fBx_cflag\fR field and enabled at the remote connected
 176      -device.
 177      -.sp
 178      -.LP
 179      -The \fBx_cflag\fR field specifies the system treatment of clock modes.
 180      -.sp
 181      -
 182      -.sp
 183      -.TS
 184      -l l l
 185      -l l l .
 186      -\fBXMTCLK\fR    0000007 Transmit clock source:
 187      -\fBXCIBRG\fR    0000000         T{
 188      -Get transmit clock from internal baud rate generator.
 189      -T}
 190      -\fBXCTSET\fR    0000001         T{
 191      -Get transmit clock from transmitter signal element timing (DCE source) lead, CCITT V.24 circuit 114, EIA-232-D pin 15.
 192      -T}
 193      -\fBXCRSET\fR    0000002         T{
 194      -Get transmit clock from receiver signal element timing (DCE source) lead, CCITT V.24 circuit 115, EIA-232-D pin 17.
 195      -T}
 196      -\fBRCVCLK\fR    0000070         Receive clock source:
 197      -\fBRCIBRG\fR    0000000         T{
 198      -Get receive clock from internal baud rate generator.
 199      -T}
 200      -\fBRCTSET\fR    0000010         T{
 201      -Get receive clock from transmitter signal element timing (DCE source) lead, CCITT V.24 circuit 114, EIA-232-D pin 15.
 202      -T}
 203      -\fBRCRSET\fR    0000020         T{
 204      -Get receive clock from receiver signal element timing (DCE source) lead, CCITT V.24 circuit 115, EIA-232-D pin 17.
 205      -T}
 206      -\fBTSETCLK\fR   0000700         T{
 207      -Transmitter signal element timing (DTE source) lead, CCITT V.24 circuit 113, EIA-232-D pin 24, clock source:
 208      -T}
 209      -\fBTSETCOFF\fR  0000000         TSET clock not provided.
 210      -\fBTSETCRBRG\fR 0000100         T{
 211      -Output receive baud rate generator on circuit 113.
 212      -T}
 213      -\fBTSETCTBRG\fR 0000200         T{
 214      -Output transmit baud rate generator on circuit 113
 215      -T}
 216      -\fBTSETCTSET\fR 0000300         T{
 217      -Output transmitter signal element timing (DCE source) on circuit 113.
 218      -T}
 219      -\fBTSETCRSET\fR 0000400         T{
 220      -Output receiver signal element timing (DCE source) on circuit 113.
 221      -T}
 222      -\fBRSETCLK\fR   0007000         T{
 223      -Receiver signal element timing (DTE source) lead, CCITT V.24 circuit 128, no EIA-232-D pin, clock source:
 224      -T}
 225      -\fBRSETCOFF\fR  0000000         RSET clock not provided.
 226      -\fBRSETCRBRG\fR 0001000         T{
 227      -Output receive baud rate generator on circuit 128.
 228      -T}
 229      -\fBRSETCTBRG\fR 0002000         T{
 230      -Output transmit baud rate generator on circuit 128.
 231      -T}
 232      -\fBRSETCTSET\fR 0003000         T{
 233      -Output transmitter signal element timing (DCE source) on circuit 128.
 234      -T}
 235      -\fBRSETCRSET\fR 0004000         T{
 236      -Output receiver signal element timing (DCE) on circuit 128.
 237      -T}
 238      -.TE
 239      -
 240      -.sp
 241      -.LP
 242      -If the \fBXMTCLK\fR field has a value of \fBXCIBRG\fR the transmit clock is
 243      -taken from the hardware internal baud rate generator, as in normal asynchronous
 244      -transmission. If \fBXMTCLK\fR = \fBXCTSET\fR the transmit clock is taken from
 245      -the Transmitter Signal Element Timing (DCE source) circuit. If \fBXMTCLK\fR =
 246      -\fBXCRSET\fR the transmit clock is taken from the Receiver Signal Element
      218 +programming using the
      219 +.Fa x_cflag
      220 +field and enabled at the remote connected device.
      221 +.Pp
      222 +The
      223 +.Fa x_cflag
      224 +field specifies the system treatment of clock modes.
      225 +.Bl -column xxxxxxxxx xxxxxxxx l
      226 +.It Dv XMTCLK Ta 0000007 Ta "Transmit clock source:"
      227 +.It Dv XCIBRG Ta 0000000 Ta "Get transmit clock from internal baud rate generator."
      228 +.It Dv XCTSET Ta 0000001 Ta "Get transmit clock from transmitter signal element timing (DCE source) lead, CCITT V\.24 circuit 114, EIA-232-D pin 15."
      229 +.It Dv XCRSET Ta 0000002 Ta  Get transmit clock from receiver signal element timing (DCE source) lead, CCITT V\.4 circuit 115, EIA-232-D pin 17."
      230 +.It Dv RCVCLK Ta 0000070 Ta "Receive clock source:"
      231 +.It Dv RCIBRG Ta 0000000 Ta "Get receive clock from internal baud rate generator."
      232 +.It Dv RCTSET Ta 0000010 Ta "Get receive clock from transmitter signal element timing (DCE source) lead, CCITT V\.24 circuit 114, EIA-232-D pin 15."
      233 +.It Dv RCRSET Ta 0000020 Ta "Get receive clock from receiver signal element timing (DCE source) lead, CCITT V\.24 circuit 115, EIA-232-D pin 17."
      234 +.It Dv TSETCLK Ta 0000700 Ta "Transmitter signal element timing (DTE source) lead, CCITT V\.24 circuit 113, EIA-232-D pin 24, clock source:"
      235 +.It Dv TSETCOFF Ta 0000000 Ta "TSET clock not provided."
      236 +.It Dv TSETCRBRG Ta 0000100 Ta "Output receive baud rate generator on circuit 113."
      237 +.It Dv TSETCTBRG Ta 0000200 Ta "Output transmit baud rate generator on circuit 113"
      238 +.It Dv TSETCTSET Ta 0000300 Ta "Output transmitter signal element timing (DCE source) on circuit 113."
      239 +.It Dv TSETCRSET Ta 0000400 Ta "Output receiver signal element timing (DCE source) on circuit 113."
      240 +.It Dv RSETCLK Ta 0007000 Ta "Receiver signal element timing (DTE source) lead, CCITT V\.24 circuit 128, no EIA-232-D pin, clock source:"
      241 +.It Dv RSETCOFF Ta 0000000 Ta "RSET clock not provided."
      242 +.It Dv RSETCRBRG Ta 0001000 Ta "Output receive baud rate generator on circuit 128."
      243 +.It Dv RSETCTBRG Ta 0002000 Ta "Output transmit baud rate generator on circuit 128."
      244 +.It Dv RSETCTSET Ta 0003000 Ta "Output transmitter signal element timing (DCE source) on circuit 128."
      245 +.It Dv RSETCRSET Ta 0004000 Ta "Output receiver signal element timing (DCE) on circuit 128."
      246 +.El
      247 +.Pp
      248 +If the
      249 +.Fa XMTCLK
      250 +field has a value of
      251 +.Dv XCIBRG
      252 +the transmit clock is taken from the hardware internal baud rate generator, as
      253 +in normal asynchronous transmission.
      254 +If
      255 +.Fa XMTCLK
      256 +=
      257 +.Dv XCTSET
      258 +the transmit clock is taken from
      259 +the Transmitter Signal Element Timing (DCE source) circuit.
      260 +If
      261 +.Fa XMTCLK
      262 +=
      263 +.Dv XCRSET
      264 +the transmit clock is taken from the Receiver Signal Element
 247  265  Timing (DCE source) circuit.
 248      -.sp
 249      -.LP
 250      -If the \fBRCVCLK\fR field has a value of \fBRCIBRG\fR the receive clock is
      266 +.Pp
      267 +If the
      268 +.Fa RCVCLK
      269 +field has a value of
      270 +.Dv RCIBRG ,
      271 +the receive clock is
 251  272  taken from the hardware Internal Baud Rate Generator, as in normal asynchronous
 252      -transmission. If \fBRCVCLK\fR = \fBRCTSET\fR the receive clock is taken from
 253      -the Transmitter Signal Element Timing (DCE source) circuit. If \fBRCVCLK\fR =
 254      -\fBRCRSET\fR the receive clock is taken from the Receiver Signal Element Timing
      273 +transmission.
      274 +If
      275 +.Fa RCVCLK
      276 +=
      277 +.Dv RCTSET
      278 +the receive clock is taken from
      279 +the Transmitter Signal Element Timing (DCE source) circuit.
      280 +If
      281 +.Fa RCVCLK
      282 +=
      283 +.Dv RCRSET
      284 +the receive clock is taken from the Receiver Signal Element Timing
 255  285  (DCE source) circuit.
 256      -.sp
 257      -.LP
 258      -If the \fBTSETCLK\fR field has a value of \fBTSETCOFF\fR the Transmitter Signal
 259      -Element Timing (DTE source) circuit is not driven. If \fBTSETCLK\fR =
 260      -\fBTSETCRBRG\fR the Transmitter Signal Element Timing (DTE source) circuit is
 261      -driven by the Receive Baud Rate Generator. If \fBTSETCLK\fR = \fBTSETCTBRG\fR
      286 +.Pp
      287 +If the
      288 +.Fa TSETCLK
      289 +field has a value of
      290 +.Dv TSETCOFF
      291 +the Transmitter Signal Element Timing (DTE source) circuit is not driven.
      292 +If
      293 +.Fa TSETCLK
      294 +=
      295 +.Dv TSETCRBRG
      296 +the Transmitter Signal Element Timing (DTE source) circuit is
      297 +driven by the Receive Baud Rate Generator.
      298 +If
      299 +.Fa TSETCLK
      300 +=
      301 +.Dv TSETCTBRG
 262  302  the Transmitter Signal Element Timing (DTE source) circuit is driven by the
 263      -Transmit Baud Rate Generator. If \fBTSETCLK\fR = \fBTSETCTSET\fR the
 264      -Transmitter Signal Element Timing (DTE source) circuit is driven by the
 265      -Transmitter Signal Element Timing (DCE source). If \fBTSETCLK\fR =
 266      -\fBTSETCRBRG\fR the Transmitter Signal Element Timing (DTE source) circuit is
      303 +Transmit Baud Rate Generator.
      304 +If
      305 +.Fa TSETCLK
      306 +=
      307 +.Dv TSETCTSET
      308 +the Transmitter Signal Element Timing (DTE source) circuit is driven by the
      309 +Transmitter Signal Element Timing (DCE source).
      310 +If
      311 +.Fa TSETCLK
      312 +=
      313 +.Dv TSETCRBRG
      314 +the Transmitter Signal Element Timing (DTE source) circuit is
 267  315  driven by the Receiver Signal Element Timing (DCE source).
 268      -.sp
 269      -.LP
 270      -If the \fBRSETCLK\fR field has a value of \fBRSETCOFF\fR the Receiver Signal
 271      -Element Timing (DTE source) circuit is not driven. If \fBRSETCLK\fR =
 272      -\fBRSETCRBRG\fR the Receiver Signal Element Timing (DTE source) circuit is
 273      -driven by the Receive Baud Rate Generator.  If \fBRSETCLK\fR = \fBRSETCTBRG\fR
      316 +.Pp
      317 +If the
      318 +.Fa RSETCLK
      319 +field has a value of
      320 +.Dv RSETCOFF
      321 +the Receiver Signal Element Timing (DTE source) circuit is not driven.
      322 +If
      323 +.Fa RSETCLK
      324 +=
      325 +.Dv RSETCRBRG
      326 +the Receiver Signal Element Timing (DTE source) circuit is
      327 +driven by the Receive Baud Rate Generator.
      328 +If
      329 +.Fa RSETCLK
      330 +=
      331 +.Dv RSETCTBRG
 274  332  the Receiver Signal Element Timing (DTE source) circuit is driven by the
 275      -Transmit Baud Rate Generator. If \fBRSETCLK\fR = \fBRSETCTSET\fR the Receiver
      333 +Transmit Baud Rate Generator.
      334 +If
      335 +.Fa RSETCLK
      336 +=
      337 +.Dv RSETCTSET
      338 +the Receiver
 276  339  Signal Element Timing (DTE source) circuit is driven by the Transmitter Signal
 277      -Element Timing (DCE source). If \fBRSETCLK\fR = \fBRSETCRBRG\fR the Receiver
      340 +Element Timing (DCE source).
      341 +If
      342 +.Fa RSETCLK
      343 +=
      344 +.Dv RSETCRBRG
      345 +the Receiver
 278  346  Signal Element Timing (DTE source) circuit is driven by the Receiver Signal
 279  347  Element Timing (DCE source).
 280      -.sp
 281      -.LP
 282      -The \fBx_rflag\fR is reserved for future interface definitions and should not
 283      -be used by any implementations. The \fBx_sflag\fR may be used by local
      348 +.Pp
      349 +The
      350 +.Fa x_rflag
      351 +is reserved for future interface definitions and should not
      352 +be used by any implementations.
      353 +The
      354 +.Fa x_sflag
      355 +may be used by local
 284  356  implementations wishing to customize their terminal interface using the
 285      -\fBtermiox\fR ioctl system calls.
 286      -.SH IOCTLS
 287      -.LP
 288      -The  \fBioctl\fR(2) system calls have the form:
 289      -.sp
 290      -.in +2
 291      -.nf
 292      -\fBioctl\fR (\fIfildes, command, arg\fR) \fBstruct termiox *\fR \fIarg\fR;
 293      -.fi
 294      -.in -2
 295      -
 296      -.sp
 297      -.LP
      357 +.Nm
      358 +ioctl system calls.
      359 +.Sh IOCTLS
      360 +The
      361 +.Xr ioctl 2
      362 +system calls have the form:
      363 +.Bd -literal -offset 2n
      364 +struct termiox *arg;
      365 +ioctl(fildes, command, arg);
      366 +.Ed
      367 +.Pp
 298  368  The commands using this form are:
 299      -.sp
 300      -.ne 2
 301      -.na
 302      -\fB\fBTCGETX\fR\fR
 303      -.ad
 304      -.RS 11n
 305      -The argument is a pointer to a \fBtermiox\fR structure. The current terminal
 306      -parameters are fetched and stored into that structure.
 307      -.RE
 308      -
 309      -.sp
 310      -.ne 2
 311      -.na
 312      -\fB\fBTCSETX\fR\fR
 313      -.ad
 314      -.RS 11n
 315      -The argument is a pointer to a \fBtermiox\fR structure.  The current terminal
 316      -parameters are set from the values stored in that structure.  The change is
 317      -immediate.
 318      -.RE
 319      -
 320      -.sp
 321      -.ne 2
 322      -.na
 323      -\fB\fBTCSETXW\fR\fR
 324      -.ad
 325      -.RS 11n
 326      -The argument is a pointer to a \fBtermiox\fR structure.  The current terminal
 327      -parameters are set from the values stored in that structure.  The change occurs
 328      -after all characters queued for output have been transmitted. This form should
 329      -be used when changing parameters that will affect output.
 330      -.RE
 331      -
 332      -.sp
 333      -.ne 2
 334      -.na
 335      -\fB\fBTCSETXF\fR\fR
 336      -.ad
 337      -.RS 11n
 338      -The argument is a pointer to a \fBtermiox\fR structure.  The current terminal
 339      -parameters are set from the values stored in that structure.  The change occurs
      369 +.Bl -tag -width TCSETXW
      370 +.It Dv TCGETX
      371 +The argument is a pointer to a
      372 +.Vt termiox
      373 +structure.
      374 +The current terminal parameters are fetched and stored into that structure.
      375 +.It Dv TCSETX
      376 +The argument is a pointer to a
      377 +.Vt termiox
      378 +structure.
      379 +The current terminal parameters are set from the values stored in that structure.
      380 +The change is immediate.
      381 +.It Dv TCSETXW
      382 +The argument is a pointer to a
      383 +.Vt termiox
      384 +structure.
      385 +The current terminal parameters are set from the values stored in that structure.
      386 +The change occurs after all characters queued for output have been transmitted.
      387 +This form should be used when changing parameters that will affect output.
      388 +.It Dv TCSETXF
      389 +The argument is a pointer to a
      390 +.Vt termiox
      391 +structure.
      392 +The current terminal parameters are set from the values stored in that structure.
      393 +The change occurs
 340  394  after all characters queued for output have been transmitted; all characters
 341  395  queued for input are discarded and then the change occurs.
 342      -.RE
 343      -
 344      -.SH FILES
 345      -.LP
 346      -\fB/dev/*\fR
 347      -.SH SEE ALSO
 348      -.LP
 349      -\fBstty\fR(1), \fBioctl\fR(2), \fBtermio\fR(7I)
 350      -.SH NOTES
 351      -.LP
 352      -The  termiox(7I) system call is provided for compatibility with previous
 353      -releases and  its use is discouraged.  Instead, the  \fBtermio\fR(7I) system
 354      -call is recommended.  See \fBtermio\fR(7I) for usage information.
      396 +.El
      397 +.Sh FILES
      398 +.Pa /dev/*
      399 +.Sh SEE ALSO
      400 +.Xr stty 1 ,
      401 +.Xr ioctl 2 ,
      402 +.Xr termio 7I
      403 +.Sh NOTES
      404 +The
      405 +.Nm termiox Ns Pq 7I
      406 +system call is provided for compatibility with previous
      407 +releases and its use is discouraged.
      408 +Instead, the
      409 +.Xr termio 7I
      410 +system call is recommended.
      411 +See
      412 +.Xr termio 7I
      413 +for usage information.
    
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