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7 .TH TERMIOX 7I "April 9, 2016"
8 .SH NAME
9 termiox \- extended general terminal interface
10 .SH DESCRIPTION
11 .LP
12 The extended general terminal interface supplements the \fBtermio\fR(7I)
13 general terminal interface by adding support for asynchronous hardware flow
14 control, isochronous flow control and clock modes, and local implementations of
15 additional asynchronous features. Some systems may not support all of these
16 capabilities because of either hardware or software limitations. Other systems
17 may not permit certain functions to be disabled. In these cases the
18 appropriate bits will be ignored. See <\fBsys/termiox.h\fR> for your system to
19 find out which capabilities are supported.
20 .SS "Hardware Flow Control Modes"
21 .LP
22 Hardware flow control supplements the \fBtermio\fR(7I) \fBIXON\fR, \fBIXOFF\fR,
23 and \fBIXANY\fR character flow control. Character flow control occurs when one
24 device controls the data transfer of another device by the insertion of control
25 characters in the data stream between devices. Hardware flow control occurs
26 when one device controls the data transfer of another device using electrical
27 control signals on wires (circuits) of the asynchronous interface. Isochronous
28 hardware flow control occurs when one device controls the data transfer of
29 another device by asserting or removing the transmit clock signals of that
30 device. Character flow control and hardware flow control may be simultaneously
31 set.
32 .sp
33 .LP
34 In asynchronous, full duplex applications, the use of the Electronic Industries
35 Association's EIA-232-D Request To Send (RTS) and Clear To Send (CTS) circuits
36 is the preferred method of hardware flow control. An interface to other
37 hardware flow control methods is included to provide a standard interface to
38 these existing methods.
39 .sp
40 .LP
41 The EIA-232-D standard specified only unidirectional hardware flow control -
42 the Data Circuit-terminating Equipment or Data Communications Equipment (DCE)
43 indicates to the Data Terminal Equipment (DTE) to stop transmitting data. The
44 \fBtermiox\fR interface allows both unidirectional and bidirectional hardware
45 flow control; when bidirectional flow control is enabled, either the DCE or DTE
46 can indicate to each other to stop transmitting data across the interface.
47 Note: It is assumed that the asynchronous port is configured as a DTE. If the
48 connected device is also a DTE and not a DCE, then DTE to DTE (for example,
49 terminal or printer connected to computer) hardware flow control is possible by
50 using a null modem to interconnect the appropriate data and control circuits.
51 .SS "Clock Modes"
52 .LP
53 Isochronous communication is a variation of asynchronous communication whereby
54 two communicating devices may provide transmit and/or receive clock signals to
55 one another. Incoming clock signals can be taken from the baud rate generator
56 on the local isochronous port controller, from CCITT V.24 circuit 114,
57 Transmitter Signal Element Timing - DCE source (EIA-232-D pin 15), or from
58 CCITT V.24 circuit 115, Receiver Signal Element Timing - DCE source (EIA-232-D
59 pin 17). Outgoing clock signals can be sent on CCITT V.24 circuit 113,
60 Transmitter Signal Element Timing - DTE source (EIA-232-D pin 24), on CCITT
61 V.24 circuit 128, Receiver Signal Element Timing - DTE source (no EIA-232-D
62 pin), or not sent at all.
63 .sp
64 .LP
65 In terms of clock modes, traditional asynchronous communication is implemented
66 simply by using the local baud rate generator as the incoming transmit and
67 receive clock source and not outputting any clock signals.
68 .SS "Terminal Parameters"
69 .LP
70 The parameters that control the behavior of devices providing the \fBtermiox\fR
71 interface are specified by the \fBtermiox\fR structure defined in the
72 <\fBsys/termiox.h\fR> header. Several \fBioctl\fR(2) system calls that fetch
73 or change these parameters use this structure:
74 .sp
75 .in +2
76 .nf
77 #define NFF 5
78 struct termiox {
79 unsigned short x_hflag; /* hardware flow control modes */
80 unsigned short x_cflag; /* clock modes */
81 unsigned short x_rflag[NFF]; /* reserved modes */
82 unsigned short x_sflag; /* spare local modes */
83 };
84 .fi
85 .in -2
86
87 .sp
88 .LP
89 The \fBx_hflag\fR field describes hardware flow control modes:
90 .sp
91
92 .sp
93 .TS
94 l l l
95 l l l .
96 RTSXOFF 0000001 T{
97 Enable RTS hardware flow control on input.
98 T}
99 CTSXON 0000002 T{
100 Enable CTS hardware flow control on output.
101 T}
102 DTRXOFF 0000004 T{
103 Enable DTR hardware flow control on input.
104 T}
105 CDXON 0000010 T{
106 Enable CD hardware flow control on output.
107 T}
108 ISXOFF 0000020 T{
109 Enable isochronous hardware flow control on input
110 T}
111 .TE
112
113 .sp
114 .LP
115 The EIA-232-D DTR and CD circuits are used to establish a connection between
116 two systems. The RTS circuit is also used to establish a connection with a
117 modem. Thus, both DTR and RTS are activated when an asynchronous port is
118 opened. If DTR is used for hardware flow control, then RTS must be used for
119 connectivity. If CD is used for hardware flow control, then CTS must be used
120 for connectivity. Thus, RTS and DTR (or CTS and CD) cannot both be used for
121 hardware flow control at the same time. Other mutual exclusions may apply, such
122 as the simultaneous setting of the \fBtermio\fR(7I) \fBHUPCL\fR and the
123 \fBtermiox\fR \fBDTRXOFF\fR bits, which use the DTE ready line for different
124 functions.
125 .sp
126 .LP
127 Variations of different hardware flow control methods may be selected by
128 setting the appropriate bits. For example, bidirectional RTS/CTS flow
129 control is selected by setting both the \fBRTSXOFF\fR and \fBCTSXON\fR bits and
130 bidirectional DTR/CTS flow control is selected by setting both the
131 \fBDTRXOFF\fR and \fBCTSXON\fR. Modem control or unidirectional CTS hardware
132 flow control is selected by setting only the \fBCTSXON\fR bit.
133 .sp
134 .LP
135 As previously mentioned, it is assumed that the local asynchronous port (for
136 example, computer) is configured as a DTE. If the connected device (for
137 example, printer) is also a DTE, it is assumed that the device is connected to
138 the computer's asynchronous port using a null modem that swaps control circuits
139 (typically RTS and CTS). The connected DTE drives RTS and the null modem swaps
140 RTS and CTS so that the remote RTS is received as CTS by the local DTE. In
141 the case that \fBCTSXON\fR is set for hardware flow control, printer's lowering
142 of its RTS would cause CTS seen by the computer to be lowered. Output to the
143 printer is suspended until the printer's raising of its RTS, which would cause
144 CTS seen by the computer to be raised.
145 .sp
146 .LP
147 If \fBRTSXOFF\fR is set, the Request To Send (RTS) circuit (line) will be
148 raised, and if the asynchronous port needs to have its input stopped, it will
149 lower the Request To Send (RTS) line. If the RTS line is lowered, it is assumed
150 that the connected device will stop its output until RTS is raised.
151 .sp
152 .LP
153 If \fBCTSXON\fR is set, output will occur only if the Clear To Send (CTS)
154 circuit (line) is raised by the connected device. If the CTS line is lowered by
155 the connected device, output is suspended until CTS is raised.
156 .sp
157 .LP
158 If \fBDTRXOFF\fR is set, the DTE Ready (DTR) circuit (line) will be raised, and
159 if the asynchronous port needs to have its input stopped, it will lower the DTE
160 Ready (DTR) line. If the DTR line is lowered, it is assumed that the connected
161 device will stop its output until DTR is raised.
162 .sp
163 .LP
164 If \fBCDXON\fR is set, output will occur only if the Received Line Signal
165 Detector (CD) circuit (line) is raised by the connected device. If the CD line
166 is lowered by the connected device, output is suspended until CD is raised.
167 .sp
168 .LP
169 If \fBISXOFF\fR is set, and if the isochronous port needs to have its input
170 stopped, it will stop the outgoing clock signal. It is assumed that the
171 connected device is using this clock signal to create its output. Transit and
172 receive clock sources are programmed using the \fBx_cflag\fR fields. If the
173 port is not programmed for external clock generation, \fBISXOFF\fR is ignored.
174 Output isochronous flow control is supported by appropriate clock source
175 programming using the \fBx_cflag\fR field and enabled at the remote connected
176 device.
177 .sp
178 .LP
179 The \fBx_cflag\fR field specifies the system treatment of clock modes.
180 .sp
181
182 .sp
183 .TS
184 l l l
185 l l l .
186 \fBXMTCLK\fR 0000007 Transmit clock source:
187 \fBXCIBRG\fR 0000000 T{
188 Get transmit clock from internal baud rate generator.
189 T}
190 \fBXCTSET\fR 0000001 T{
191 Get transmit clock from transmitter signal element timing (DCE source) lead, CCITT V.24 circuit 114, EIA-232-D pin 15.
192 T}
193 \fBXCRSET\fR 0000002 T{
194 Get transmit clock from receiver signal element timing (DCE source) lead, CCITT V.24 circuit 115, EIA-232-D pin 17.
195 T}
196 \fBRCVCLK\fR 0000070 Receive clock source:
197 \fBRCIBRG\fR 0000000 T{
198 Get receive clock from internal baud rate generator.
199 T}
200 \fBRCTSET\fR 0000010 T{
201 Get receive clock from transmitter signal element timing (DCE source) lead, CCITT V.24 circuit 114, EIA-232-D pin 15.
202 T}
203 \fBRCRSET\fR 0000020 T{
204 Get receive clock from receiver signal element timing (DCE source) lead, CCITT V.24 circuit 115, EIA-232-D pin 17.
205 T}
206 \fBTSETCLK\fR 0000700 T{
207 Transmitter signal element timing (DTE source) lead, CCITT V.24 circuit 113, EIA-232-D pin 24, clock source:
208 T}
209 \fBTSETCOFF\fR 0000000 TSET clock not provided.
210 \fBTSETCRBRG\fR 0000100 T{
211 Output receive baud rate generator on circuit 113.
212 T}
213 \fBTSETCTBRG\fR 0000200 T{
214 Output transmit baud rate generator on circuit 113
215 T}
216 \fBTSETCTSET\fR 0000300 T{
217 Output transmitter signal element timing (DCE source) on circuit 113.
218 T}
219 \fBTSETCRSET\fR 0000400 T{
220 Output receiver signal element timing (DCE source) on circuit 113.
221 T}
222 \fBRSETCLK\fR 0007000 T{
223 Receiver signal element timing (DTE source) lead, CCITT V.24 circuit 128, no EIA-232-D pin, clock source:
224 T}
225 \fBRSETCOFF\fR 0000000 RSET clock not provided.
226 \fBRSETCRBRG\fR 0001000 T{
227 Output receive baud rate generator on circuit 128.
228 T}
229 \fBRSETCTBRG\fR 0002000 T{
230 Output transmit baud rate generator on circuit 128.
231 T}
232 \fBRSETCTSET\fR 0003000 T{
233 Output transmitter signal element timing (DCE source) on circuit 128.
234 T}
235 \fBRSETCRSET\fR 0004000 T{
236 Output receiver signal element timing (DCE) on circuit 128.
237 T}
238 .TE
239
240 .sp
241 .LP
242 If the \fBXMTCLK\fR field has a value of \fBXCIBRG\fR the transmit clock is
243 taken from the hardware internal baud rate generator, as in normal asynchronous
244 transmission. If \fBXMTCLK\fR = \fBXCTSET\fR the transmit clock is taken from
245 the Transmitter Signal Element Timing (DCE source) circuit. If \fBXMTCLK\fR =
246 \fBXCRSET\fR the transmit clock is taken from the Receiver Signal Element
247 Timing (DCE source) circuit.
248 .sp
249 .LP
250 If the \fBRCVCLK\fR field has a value of \fBRCIBRG\fR the receive clock is
251 taken from the hardware Internal Baud Rate Generator, as in normal asynchronous
252 transmission. If \fBRCVCLK\fR = \fBRCTSET\fR the receive clock is taken from
253 the Transmitter Signal Element Timing (DCE source) circuit. If \fBRCVCLK\fR =
254 \fBRCRSET\fR the receive clock is taken from the Receiver Signal Element Timing
255 (DCE source) circuit.
256 .sp
257 .LP
258 If the \fBTSETCLK\fR field has a value of \fBTSETCOFF\fR the Transmitter Signal
259 Element Timing (DTE source) circuit is not driven. If \fBTSETCLK\fR =
260 \fBTSETCRBRG\fR the Transmitter Signal Element Timing (DTE source) circuit is
261 driven by the Receive Baud Rate Generator. If \fBTSETCLK\fR = \fBTSETCTBRG\fR
262 the Transmitter Signal Element Timing (DTE source) circuit is driven by the
263 Transmit Baud Rate Generator. If \fBTSETCLK\fR = \fBTSETCTSET\fR the
264 Transmitter Signal Element Timing (DTE source) circuit is driven by the
265 Transmitter Signal Element Timing (DCE source). If \fBTSETCLK\fR =
266 \fBTSETCRBRG\fR the Transmitter Signal Element Timing (DTE source) circuit is
267 driven by the Receiver Signal Element Timing (DCE source).
268 .sp
269 .LP
270 If the \fBRSETCLK\fR field has a value of \fBRSETCOFF\fR the Receiver Signal
271 Element Timing (DTE source) circuit is not driven. If \fBRSETCLK\fR =
272 \fBRSETCRBRG\fR the Receiver Signal Element Timing (DTE source) circuit is
273 driven by the Receive Baud Rate Generator. If \fBRSETCLK\fR = \fBRSETCTBRG\fR
274 the Receiver Signal Element Timing (DTE source) circuit is driven by the
275 Transmit Baud Rate Generator. If \fBRSETCLK\fR = \fBRSETCTSET\fR the Receiver
276 Signal Element Timing (DTE source) circuit is driven by the Transmitter Signal
277 Element Timing (DCE source). If \fBRSETCLK\fR = \fBRSETCRBRG\fR the Receiver
278 Signal Element Timing (DTE source) circuit is driven by the Receiver Signal
279 Element Timing (DCE source).
280 .sp
281 .LP
282 The \fBx_rflag\fR is reserved for future interface definitions and should not
283 be used by any implementations. The \fBx_sflag\fR may be used by local
284 implementations wishing to customize their terminal interface using the
285 \fBtermiox\fR ioctl system calls.
286 .SH IOCTLS
287 .LP
288 The \fBioctl\fR(2) system calls have the form:
289 .sp
290 .in +2
291 .nf
292 \fBioctl\fR (\fIfildes, command, arg\fR) \fBstruct termiox *\fR \fIarg\fR;
293 .fi
294 .in -2
295
296 .sp
297 .LP
298 The commands using this form are:
299 .sp
300 .ne 2
301 .na
302 \fB\fBTCGETX\fR\fR
303 .ad
304 .RS 11n
305 The argument is a pointer to a \fBtermiox\fR structure. The current terminal
306 parameters are fetched and stored into that structure.
307 .RE
308
309 .sp
310 .ne 2
311 .na
312 \fB\fBTCSETX\fR\fR
313 .ad
314 .RS 11n
315 The argument is a pointer to a \fBtermiox\fR structure. The current terminal
316 parameters are set from the values stored in that structure. The change is
317 immediate.
318 .RE
319
320 .sp
321 .ne 2
322 .na
323 \fB\fBTCSETXW\fR\fR
324 .ad
325 .RS 11n
326 The argument is a pointer to a \fBtermiox\fR structure. The current terminal
327 parameters are set from the values stored in that structure. The change occurs
328 after all characters queued for output have been transmitted. This form should
329 be used when changing parameters that will affect output.
330 .RE
331
332 .sp
333 .ne 2
334 .na
335 \fB\fBTCSETXF\fR\fR
336 .ad
337 .RS 11n
338 The argument is a pointer to a \fBtermiox\fR structure. The current terminal
339 parameters are set from the values stored in that structure. The change occurs
340 after all characters queued for output have been transmitted; all characters
341 queued for input are discarded and then the change occurs.
342 .RE
343
344 .SH FILES
345 .LP
346 \fB/dev/*\fR
347 .SH SEE ALSO
348 .LP
349 \fBstty\fR(1), \fBioctl\fR(2), \fBtermio\fR(7I)
350 .SH NOTES
351 .LP
352 The termiox(7I) system call is provided for compatibility with previous
353 releases and its use is discouraged. Instead, the \fBtermio\fR(7I) system
354 call is recommended. See \fBtermio\fR(7I) for usage information.