191 * m_dr_flag is a flag for DR, make sure the member
192 * take the place of dr_flag of mptsas_hash_data.
193 */
194 uint8_t m_dr_flag; /* dr_flag */
195 uint16_t m_devhdl;
196 uint32_t m_deviceinfo;
197 uint8_t m_phynum;
198 uint32_t m_dups;
199 int32_t m_timeout;
200 int32_t m_timebase;
201 int32_t m_t_throttle;
202 int32_t m_t_ncmds;
203 int32_t m_reset_delay;
204 int32_t m_t_nwait;
205
206 uint16_t m_qfull_retry_interval;
207 uint8_t m_qfull_retries;
208 uint16_t m_enclosure;
209 uint16_t m_slot_num;
210 uint32_t m_tgt_unconfigured;
211
212 /*
213 * For the common case, the elements in this structure are
214 * protected by the per hba instance mutex. In order to make
215 * the key code path in ISR lockless, a separate mutex is
216 * introdeced to protect those shown in ISR.
217 */
218 kmutex_t m_tgt_intr_mutex;
219
220 } mptsas_target_t;
221
222 typedef struct mptsas_smp {
223 uint64_t m_sasaddr; /* hash key1 */
224 mptsas_phymask_t m_phymask; /* hash key2 */
225 uint8_t reserved1;
226 uint16_t m_devhdl;
227 uint32_t m_deviceinfo;
228 uint16_t m_pdevhdl;
229 uint32_t m_pdevinfo;
230 } mptsas_smp_t;
231
232 typedef struct mptsas_hash_data {
233 uint64_t key1;
234 mptsas_phymask_t key2;
235 uint8_t dr_flag;
236 uint16_t devhdl;
237 uint32_t device_info;
238 } mptsas_hash_data_t;
239
584 * state as we progress through reprogramming the HBA from target mode into
585 * initiator mode.
586 */
587
588 #define IOUC_READ_PAGE0 0x00000100
589 #define IOUC_READ_PAGE1 0x00000200
590 #define IOUC_WRITE_PAGE1 0x00000400
591 #define IOUC_DONE 0x00000800
592 #define DISCOVERY_IN_PROGRESS MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS
593 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG
594
595 /*
596 * Last allocated slot is used for TM requests. Since only m_max_requests
597 * frames are allocated, the last SMID will be m_max_requests - 1.
598 */
599 #define MPTSAS_SLOTS_SIZE(mpt) \
600 (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \
601 mpt->m_max_requests))
602 #define MPTSAS_TM_SLOT(mpt) (mpt->m_max_requests - 1)
603
604 typedef struct mptsas_slot_free_e {
605 processorid_t cpuid;
606 int slot;
607 list_node_t node;
608 } mptsas_slot_free_e_t;
609
610 /*
611 * each of the allocq and releaseq in all CPU groups resides in separate
612 * cacheline(64 bytes). Multiple mutex in the same cacheline is not good
613 * for performance.
614 */
615 typedef union mptsas_slot_freeq {
616 struct {
617 kmutex_t m_fq_mutex;
618 list_t m_fq_list;
619 int m_fq_n;
620 int m_fq_n_init;
621 } s;
622 char pad[64];
623 } mptsas_slot_freeq_t;
624
625 typedef struct mptsas_slot_freeq_pair {
626 mptsas_slot_freeq_t m_slot_allocq;
627 mptsas_slot_freeq_t m_slot_releq;
628 } mptsas_slot_freeq_pair_t;
629
630 /*
631 * Macro for phy_flags
632 */
633
634 typedef struct smhba_info {
635 kmutex_t phy_mutex;
636 uint8_t phy_id;
637 uint64_t sas_addr;
638 char path[8];
639 uint16_t owner_devhdl;
640 uint16_t attached_devhdl;
641 uint8_t attached_phy_identify;
642 uint32_t attached_phy_info;
643 uint8_t programmed_link_rate;
644 uint8_t hw_link_rate;
645 uint8_t change_count;
646 uint32_t phy_info;
647 uint8_t negotiated_link_rate;
648 uint8_t port_num;
649 kstat_t *phy_stats;
650 uint32_t invalid_dword_count;
675 mptsas_cmd_t *doneq;
676 mptsas_cmd_t **donetail;
677 kthread_t *threadp;
678 kcondvar_t cv;
679 ushort_t reserv1;
680 uint32_t reserv2;
681 kmutex_t mutex;
682 uint32_t flag;
683 uint32_t len;
684 mptsas_doneq_thread_arg_t arg;
685 } mptsas_doneq_thread_list_t;
686
687 typedef struct mptsas {
688 int m_instance;
689
690 struct mptsas *m_next;
691
692 scsi_hba_tran_t *m_tran;
693 smp_hba_tran_t *m_smptran;
694 kmutex_t m_mutex;
695 kcondvar_t m_cv;
696 kcondvar_t m_fw_cv;
697 kcondvar_t m_config_cv;
698 kcondvar_t m_fw_diag_cv;
699 dev_info_t *m_dip;
700
701 /*
702 * soft state flags
703 */
704 uint_t m_softstate;
705
706 struct mptsas_slots *m_active; /* outstanding cmds */
707
708 mptsas_cmd_t *m_waitq; /* cmd queue for active request */
709 mptsas_cmd_t **m_waitqtail; /* wait queue tail ptr */
710
711 mptsas_cmd_t *m_doneq; /* queue of completed commands */
712 mptsas_cmd_t **m_donetail; /* queue tail ptr */
713
714 kmutex_t m_passthru_mutex;
715 kcondvar_t m_passthru_cv;
716 /*
717 * variables for helper threads (fan-out interrupts)
718 */
719 mptsas_doneq_thread_list_t *m_doneq_thread_id;
720 uint32_t m_doneq_thread_n;
721 uint32_t m_doneq_thread_threshold;
722 uint32_t m_doneq_length_threshold;
723 uint32_t m_doneq_len;
724 kcondvar_t m_doneq_thread_cv;
725 kmutex_t m_doneq_mutex;
726
727 int m_ncmds; /* number of outstanding commands */
728 m_event_struct_t *m_ioc_event_cmdq; /* cmd queue for ioc event */
729 m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */
730
731 ddi_acc_handle_t m_datap; /* operating regs data access handle */
732
733 struct _MPI2_SYSTEM_INTERFACE_REGS *m_reg;
734
735 ushort_t m_devid; /* device id of chip. */
736 uchar_t m_revid; /* revision of chip. */
737 uint16_t m_svid; /* subsystem Vendor ID of chip */
738 uint16_t m_ssid; /* subsystem Device ID of chip */
739
740 uchar_t m_sync_offset; /* default offset for this chip. */
741
742 timeout_id_t m_quiesce_timeid;
743
744 ddi_dma_handle_t m_dma_req_frame_hdl;
745 ddi_acc_handle_t m_acc_req_frame_hdl;
746 ddi_dma_handle_t m_dma_reply_frame_hdl;
747 ddi_acc_handle_t m_acc_reply_frame_hdl;
748 ddi_dma_handle_t m_dma_free_queue_hdl;
749 ddi_acc_handle_t m_acc_free_queue_hdl;
750 ddi_dma_handle_t m_dma_post_queue_hdl;
751 ddi_acc_handle_t m_acc_post_queue_hdl;
752
753 /*
754 * Try the best to make the key code path in the ISR lockless.
755 * so avoid to use the per instance mutex m_mutex in the ISR. Introduce
756 * a separate mutex to protect the elements shown in ISR.
757 */
758 kmutex_t m_intr_mutex;
759
760 /*
761 * list of reset notification requests
762 */
763 struct scsi_reset_notify_entry *m_reset_notify_listf;
764
765 /*
766 * qfull handling
767 */
768 timeout_id_t m_restart_cmd_timeid;
769
770 /*
771 * scsi reset delay per bus
772 */
773 uint_t m_scsi_reset_delay;
774
775 int m_pm_idle_delay;
776
777 uchar_t m_polled_intr; /* intr was polled. */
778 uchar_t m_suspended; /* true if driver is suspended */
779
780 struct kmem_cache *m_kmem_cache;
832 uint16_t m_post_queue_depth;
833 uint16_t m_max_replies;
834 uint32_t m_free_index;
835 uint32_t m_post_index;
836 uint8_t m_reply_frame_size;
837 uint32_t m_ioc_capabilities;
838
839 /*
840 * indicates if the firmware was upload by the driver
841 * at boot time
842 */
843 ushort_t m_fwupload;
844
845 uint16_t m_productid;
846
847 /*
848 * per instance data structures for dma memory resources for
849 * MPI handshake protocol. only one handshake cmd can run at a time.
850 */
851 ddi_dma_handle_t m_hshk_dma_hdl;
852
853 ddi_acc_handle_t m_hshk_acc_hdl;
854
855 caddr_t m_hshk_memp;
856
857 size_t m_hshk_dma_size;
858
859 /* Firmware version on the card at boot time */
860 uint32_t m_fwversion;
861
862 /* MSI specific fields */
863 ddi_intr_handle_t *m_htable; /* For array of interrupts */
864 int m_intr_type; /* What type of interrupt */
865 int m_intr_cnt; /* # of intrs count returned */
866 size_t m_intr_size; /* Size of intr array */
867 uint_t m_intr_pri; /* Interrupt priority */
868 int m_intr_cap; /* Interrupt capabilities */
869 ddi_taskq_t *m_event_taskq;
870
871 /* SAS specific information */
872
873 union {
874 uint64_t m_base_wwid; /* Base WWID */
875 struct {
876 #ifdef _BIG_ENDIAN
907 uint32_t m_event_mask[4];
908 mptsas_event_entry_t m_events[MPTSAS_EVENT_QUEUE_SIZE];
909
910 /*
911 * FW diag Buffer List
912 */
913 mptsas_fw_diagnostic_buffer_t
914 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT];
915
916 /*
917 * Event Replay flag (MUR support)
918 */
919 uint8_t m_event_replay;
920
921 /*
922 * IR Capable flag
923 */
924 uint8_t m_ir_capable;
925
926 /*
927 * release and alloc queue for slot
928 */
929 int m_slot_freeq_pair_n;
930 mptsas_slot_freeq_pair_t *m_slot_freeq_pairp;
931 mptsas_slot_free_e_t *m_slot_free_ae;
932 #define MPI_ADDRESS_COALSCE_MAX 128
933 pMpi2ReplyDescriptorsUnion_t m_reply;
934
935 /*
936 * Is HBA processing a diag reset?
937 */
938 uint8_t m_in_reset;
939
940 /*
941 * per instance cmd data structures for task management cmds
942 */
943 m_event_struct_t m_event_task_mgmt; /* must be last */
944 /* ... scsi_pkt_size */
945 } mptsas_t;
946 #define MPTSAS_SIZE (sizeof (struct mptsas) - \
947 sizeof (struct scsi_pkt) + scsi_pkt_size())
948 /*
949 * Only one of below two conditions is satisfied, we
950 * think the target is associated to the iport and
951 * allow call into mptsas_probe_lun().
952 * 1. physicalsport == physport
953 * 2. (phymask & (1 << physport)) == 0
954 * The condition #2 is because LSI uses lowest PHY
955 * number as the value of physical port when auto port
|
191 * m_dr_flag is a flag for DR, make sure the member
192 * take the place of dr_flag of mptsas_hash_data.
193 */
194 uint8_t m_dr_flag; /* dr_flag */
195 uint16_t m_devhdl;
196 uint32_t m_deviceinfo;
197 uint8_t m_phynum;
198 uint32_t m_dups;
199 int32_t m_timeout;
200 int32_t m_timebase;
201 int32_t m_t_throttle;
202 int32_t m_t_ncmds;
203 int32_t m_reset_delay;
204 int32_t m_t_nwait;
205
206 uint16_t m_qfull_retry_interval;
207 uint8_t m_qfull_retries;
208 uint16_t m_enclosure;
209 uint16_t m_slot_num;
210 uint32_t m_tgt_unconfigured;
211 uint32_t m_timeout_interval;
212 uint8_t m_timeout_count;
213
214 } mptsas_target_t;
215
216 typedef struct mptsas_smp {
217 uint64_t m_sasaddr; /* hash key1 */
218 mptsas_phymask_t m_phymask; /* hash key2 */
219 uint8_t reserved1;
220 uint16_t m_devhdl;
221 uint32_t m_deviceinfo;
222 uint16_t m_pdevhdl;
223 uint32_t m_pdevinfo;
224 } mptsas_smp_t;
225
226 typedef struct mptsas_hash_data {
227 uint64_t key1;
228 mptsas_phymask_t key2;
229 uint8_t dr_flag;
230 uint16_t devhdl;
231 uint32_t device_info;
232 } mptsas_hash_data_t;
233
578 * state as we progress through reprogramming the HBA from target mode into
579 * initiator mode.
580 */
581
582 #define IOUC_READ_PAGE0 0x00000100
583 #define IOUC_READ_PAGE1 0x00000200
584 #define IOUC_WRITE_PAGE1 0x00000400
585 #define IOUC_DONE 0x00000800
586 #define DISCOVERY_IN_PROGRESS MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS
587 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG
588
589 /*
590 * Last allocated slot is used for TM requests. Since only m_max_requests
591 * frames are allocated, the last SMID will be m_max_requests - 1.
592 */
593 #define MPTSAS_SLOTS_SIZE(mpt) \
594 (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \
595 mpt->m_max_requests))
596 #define MPTSAS_TM_SLOT(mpt) (mpt->m_max_requests - 1)
597
598 /*
599 * Macro for phy_flags
600 */
601
602 typedef struct smhba_info {
603 kmutex_t phy_mutex;
604 uint8_t phy_id;
605 uint64_t sas_addr;
606 char path[8];
607 uint16_t owner_devhdl;
608 uint16_t attached_devhdl;
609 uint8_t attached_phy_identify;
610 uint32_t attached_phy_info;
611 uint8_t programmed_link_rate;
612 uint8_t hw_link_rate;
613 uint8_t change_count;
614 uint32_t phy_info;
615 uint8_t negotiated_link_rate;
616 uint8_t port_num;
617 kstat_t *phy_stats;
618 uint32_t invalid_dword_count;
643 mptsas_cmd_t *doneq;
644 mptsas_cmd_t **donetail;
645 kthread_t *threadp;
646 kcondvar_t cv;
647 ushort_t reserv1;
648 uint32_t reserv2;
649 kmutex_t mutex;
650 uint32_t flag;
651 uint32_t len;
652 mptsas_doneq_thread_arg_t arg;
653 } mptsas_doneq_thread_list_t;
654
655 typedef struct mptsas {
656 int m_instance;
657
658 struct mptsas *m_next;
659
660 scsi_hba_tran_t *m_tran;
661 smp_hba_tran_t *m_smptran;
662 kmutex_t m_mutex;
663 kmutex_t m_passthru_mutex;
664 kcondvar_t m_cv;
665 kcondvar_t m_passthru_cv;
666 kcondvar_t m_fw_cv;
667 kcondvar_t m_config_cv;
668 kcondvar_t m_fw_diag_cv;
669 dev_info_t *m_dip;
670
671 /*
672 * soft state flags
673 */
674 uint_t m_softstate;
675
676 struct mptsas_slots *m_active; /* outstanding cmds */
677
678 mptsas_cmd_t *m_waitq; /* cmd queue for active request */
679 mptsas_cmd_t **m_waitqtail; /* wait queue tail ptr */
680
681 kmutex_t m_tx_waitq_mutex;
682 mptsas_cmd_t *m_tx_waitq; /* TX cmd queue for active request */
683 mptsas_cmd_t **m_tx_waitqtail; /* tx_wait queue tail ptr */
684 int m_tx_draining; /* TX queue draining flag */
685
686 mptsas_cmd_t *m_doneq; /* queue of completed commands */
687 mptsas_cmd_t **m_donetail; /* queue tail ptr */
688
689 /*
690 * variables for helper threads (fan-out interrupts)
691 */
692 mptsas_doneq_thread_list_t *m_doneq_thread_id;
693 uint32_t m_doneq_thread_n;
694 uint32_t m_doneq_thread_threshold;
695 uint32_t m_doneq_length_threshold;
696 uint32_t m_doneq_len;
697 kcondvar_t m_doneq_thread_cv;
698 kmutex_t m_doneq_mutex;
699
700 int m_ncmds; /* number of outstanding commands */
701 m_event_struct_t *m_ioc_event_cmdq; /* cmd queue for ioc event */
702 m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */
703
704 ddi_acc_handle_t m_datap; /* operating regs data access handle */
705
706 struct _MPI2_SYSTEM_INTERFACE_REGS *m_reg;
707
708 ushort_t m_devid; /* device id of chip. */
709 uchar_t m_revid; /* revision of chip. */
710 uint16_t m_svid; /* subsystem Vendor ID of chip */
711 uint16_t m_ssid; /* subsystem Device ID of chip */
712
713 uchar_t m_sync_offset; /* default offset for this chip. */
714
715 timeout_id_t m_quiesce_timeid;
716
717 ddi_dma_handle_t m_dma_req_frame_hdl;
718 ddi_acc_handle_t m_acc_req_frame_hdl;
719 ddi_dma_handle_t m_dma_reply_frame_hdl;
720 ddi_acc_handle_t m_acc_reply_frame_hdl;
721 ddi_dma_handle_t m_dma_free_queue_hdl;
722 ddi_acc_handle_t m_acc_free_queue_hdl;
723 ddi_dma_handle_t m_dma_post_queue_hdl;
724 ddi_acc_handle_t m_acc_post_queue_hdl;
725
726 /*
727 * list of reset notification requests
728 */
729 struct scsi_reset_notify_entry *m_reset_notify_listf;
730
731 /*
732 * qfull handling
733 */
734 timeout_id_t m_restart_cmd_timeid;
735
736 /*
737 * scsi reset delay per bus
738 */
739 uint_t m_scsi_reset_delay;
740
741 int m_pm_idle_delay;
742
743 uchar_t m_polled_intr; /* intr was polled. */
744 uchar_t m_suspended; /* true if driver is suspended */
745
746 struct kmem_cache *m_kmem_cache;
798 uint16_t m_post_queue_depth;
799 uint16_t m_max_replies;
800 uint32_t m_free_index;
801 uint32_t m_post_index;
802 uint8_t m_reply_frame_size;
803 uint32_t m_ioc_capabilities;
804
805 /*
806 * indicates if the firmware was upload by the driver
807 * at boot time
808 */
809 ushort_t m_fwupload;
810
811 uint16_t m_productid;
812
813 /*
814 * per instance data structures for dma memory resources for
815 * MPI handshake protocol. only one handshake cmd can run at a time.
816 */
817 ddi_dma_handle_t m_hshk_dma_hdl;
818 ddi_acc_handle_t m_hshk_acc_hdl;
819 caddr_t m_hshk_memp;
820 size_t m_hshk_dma_size;
821
822 /* Firmware version on the card at boot time */
823 uint32_t m_fwversion;
824
825 /* MSI specific fields */
826 ddi_intr_handle_t *m_htable; /* For array of interrupts */
827 int m_intr_type; /* What type of interrupt */
828 int m_intr_cnt; /* # of intrs count returned */
829 size_t m_intr_size; /* Size of intr array */
830 uint_t m_intr_pri; /* Interrupt priority */
831 int m_intr_cap; /* Interrupt capabilities */
832 ddi_taskq_t *m_event_taskq;
833
834 /* SAS specific information */
835
836 union {
837 uint64_t m_base_wwid; /* Base WWID */
838 struct {
839 #ifdef _BIG_ENDIAN
870 uint32_t m_event_mask[4];
871 mptsas_event_entry_t m_events[MPTSAS_EVENT_QUEUE_SIZE];
872
873 /*
874 * FW diag Buffer List
875 */
876 mptsas_fw_diagnostic_buffer_t
877 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT];
878
879 /*
880 * Event Replay flag (MUR support)
881 */
882 uint8_t m_event_replay;
883
884 /*
885 * IR Capable flag
886 */
887 uint8_t m_ir_capable;
888
889 /*
890 * Is HBA processing a diag reset?
891 */
892 uint8_t m_in_reset;
893
894 /*
895 * per instance cmd data structures for task management cmds
896 */
897 m_event_struct_t m_event_task_mgmt; /* must be last */
898 /* ... scsi_pkt_size */
899 } mptsas_t;
900 #define MPTSAS_SIZE (sizeof (struct mptsas) - \
901 sizeof (struct scsi_pkt) + scsi_pkt_size())
902 /*
903 * Only one of below two conditions is satisfied, we
904 * think the target is associated to the iport and
905 * allow call into mptsas_probe_lun().
906 * 1. physicalsport == physport
907 * 2. (phymask & (1 << physport)) == 0
908 * The condition #2 is because LSI uses lowest PHY
909 * number as the value of physical port when auto port
|