Print this page
4233 mptsas topo change buffer overflow
| Split |
Close |
| Expand all |
| Collapse all |
--- old/usr/src/uts/common/io/scsi/adapters/mpt_sas/mptsas.c
+++ new/usr/src/uts/common/io/scsi/adapters/mpt_sas/mptsas.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
25 25 * Copyright (c) 2013, Joyent, Inc. All rights reserved.
26 26 */
27 27
28 28 /*
29 29 * Copyright (c) 2000 to 2010, LSI Corporation.
30 30 * All rights reserved.
31 31 *
32 32 * Redistribution and use in source and binary forms of all code within
33 33 * this file that is exclusively owned by LSI, with or without
34 34 * modification, is permitted provided that, in addition to the CDDL 1.0
35 35 * License requirements, the following conditions are met:
36 36 *
37 37 * Neither the name of the author nor the names of its contributors may be
38 38 * used to endorse or promote products derived from this software without
39 39 * specific prior written permission.
40 40 *
41 41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
42 42 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
43 43 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
44 44 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
45 45 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
46 46 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
47 47 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
48 48 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
49 49 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
50 50 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
51 51 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
52 52 * DAMAGE.
53 53 */
54 54
55 55 /*
56 56 * mptsas - This is a driver based on LSI Logic's MPT2.0 interface.
57 57 *
58 58 */
59 59
60 60 #if defined(lint) || defined(DEBUG)
61 61 #define MPTSAS_DEBUG
62 62 #endif
63 63
64 64 /*
65 65 * standard header files.
66 66 */
67 67 #include <sys/note.h>
68 68 #include <sys/scsi/scsi.h>
69 69 #include <sys/pci.h>
70 70 #include <sys/file.h>
71 71 #include <sys/policy.h>
72 72 #include <sys/model.h>
73 73 #include <sys/sysevent.h>
74 74 #include <sys/sysevent/eventdefs.h>
75 75 #include <sys/sysevent/dr.h>
76 76 #include <sys/sata/sata_defs.h>
77 77 #include <sys/scsi/generic/sas.h>
78 78 #include <sys/scsi/impl/scsi_sas.h>
79 79
80 80 #pragma pack(1)
81 81 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h>
82 82 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2.h>
83 83 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h>
84 84 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h>
85 85 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h>
86 86 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h>
87 87 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h>
88 88 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h>
89 89 #pragma pack()
90 90
91 91 /*
92 92 * private header files.
93 93 *
94 94 */
95 95 #include <sys/scsi/impl/scsi_reset_notify.h>
96 96 #include <sys/scsi/adapters/mpt_sas/mptsas_var.h>
97 97 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h>
98 98 #include <sys/scsi/adapters/mpt_sas/mptsas_smhba.h>
99 99 #include <sys/raidioctl.h>
100 100
101 101 #include <sys/fs/dv_node.h> /* devfs_clean */
102 102
103 103 /*
104 104 * FMA header files
105 105 */
106 106 #include <sys/ddifm.h>
107 107 #include <sys/fm/protocol.h>
108 108 #include <sys/fm/util.h>
109 109 #include <sys/fm/io/ddi.h>
110 110
111 111 /*
112 112 * autoconfiguration data and routines.
113 113 */
114 114 static int mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
115 115 static int mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd);
116 116 static int mptsas_power(dev_info_t *dip, int component, int level);
117 117
118 118 /*
119 119 * cb_ops function
120 120 */
121 121 static int mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode,
122 122 cred_t *credp, int *rval);
123 123 #ifdef __sparc
124 124 static int mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd);
125 125 #else /* __sparc */
126 126 static int mptsas_quiesce(dev_info_t *devi);
127 127 #endif /* __sparc */
128 128
129 129 /*
130 130 * Resource initilaization for hardware
131 131 */
132 132 static void mptsas_setup_cmd_reg(mptsas_t *mpt);
133 133 static void mptsas_disable_bus_master(mptsas_t *mpt);
134 134 static void mptsas_hba_fini(mptsas_t *mpt);
135 135 static void mptsas_cfg_fini(mptsas_t *mptsas_blkp);
136 136 static int mptsas_hba_setup(mptsas_t *mpt);
137 137 static void mptsas_hba_teardown(mptsas_t *mpt);
138 138 static int mptsas_config_space_init(mptsas_t *mpt);
139 139 static void mptsas_config_space_fini(mptsas_t *mpt);
140 140 static void mptsas_iport_register(mptsas_t *mpt);
141 141 static int mptsas_smp_setup(mptsas_t *mpt);
142 142 static void mptsas_smp_teardown(mptsas_t *mpt);
143 143 static int mptsas_cache_create(mptsas_t *mpt);
144 144 static void mptsas_cache_destroy(mptsas_t *mpt);
145 145 static int mptsas_alloc_request_frames(mptsas_t *mpt);
146 146 static int mptsas_alloc_reply_frames(mptsas_t *mpt);
147 147 static int mptsas_alloc_free_queue(mptsas_t *mpt);
148 148 static int mptsas_alloc_post_queue(mptsas_t *mpt);
149 149 static void mptsas_alloc_reply_args(mptsas_t *mpt);
150 150 static int mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd);
151 151 static void mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd);
152 152 static int mptsas_init_chip(mptsas_t *mpt, int first_time);
153 153
154 154 /*
155 155 * SCSA function prototypes
156 156 */
157 157 static int mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt);
158 158 static int mptsas_scsi_reset(struct scsi_address *ap, int level);
159 159 static int mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt);
160 160 static int mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly);
161 161 static int mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value,
162 162 int tgtonly);
163 163 static void mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt);
164 164 static struct scsi_pkt *mptsas_scsi_init_pkt(struct scsi_address *ap,
165 165 struct scsi_pkt *pkt, struct buf *bp, int cmdlen, int statuslen,
166 166 int tgtlen, int flags, int (*callback)(), caddr_t arg);
167 167 static void mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt);
168 168 static void mptsas_scsi_destroy_pkt(struct scsi_address *ap,
169 169 struct scsi_pkt *pkt);
170 170 static int mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
171 171 scsi_hba_tran_t *hba_tran, struct scsi_device *sd);
172 172 static void mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
173 173 scsi_hba_tran_t *hba_tran, struct scsi_device *sd);
174 174 static int mptsas_scsi_reset_notify(struct scsi_address *ap, int flag,
175 175 void (*callback)(caddr_t), caddr_t arg);
176 176 static int mptsas_get_name(struct scsi_device *sd, char *name, int len);
177 177 static int mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len);
178 178 static int mptsas_scsi_quiesce(dev_info_t *dip);
179 179 static int mptsas_scsi_unquiesce(dev_info_t *dip);
180 180 static int mptsas_bus_config(dev_info_t *pdip, uint_t flags,
181 181 ddi_bus_config_op_t op, void *arg, dev_info_t **childp);
182 182
183 183 /*
184 184 * SMP functions
185 185 */
186 186 static int mptsas_smp_start(struct smp_pkt *smp_pkt);
187 187
188 188 /*
189 189 * internal function prototypes.
190 190 */
191 191 static void mptsas_list_add(mptsas_t *mpt);
192 192 static void mptsas_list_del(mptsas_t *mpt);
193 193
194 194 static int mptsas_quiesce_bus(mptsas_t *mpt);
195 195 static int mptsas_unquiesce_bus(mptsas_t *mpt);
196 196
197 197 static int mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size);
198 198 static void mptsas_free_handshake_msg(mptsas_t *mpt);
199 199
200 200 static void mptsas_ncmds_checkdrain(void *arg);
201 201
202 202 static int mptsas_prepare_pkt(mptsas_cmd_t *cmd);
203 203 static int mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *sp);
204 204 static int mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *sp);
205 205 static void mptsas_accept_tx_waitq(mptsas_t *mpt);
206 206
207 207 static int mptsas_do_detach(dev_info_t *dev);
208 208 static int mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl);
209 209 static int mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun,
210 210 struct scsi_pkt *pkt);
211 211 static int mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp);
212 212
213 213 static void mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd);
214 214 static void mptsas_handle_event(void *args);
215 215 static int mptsas_handle_event_sync(void *args);
216 216 static void mptsas_handle_dr(void *args);
217 217 static void mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node,
218 218 dev_info_t *pdip);
219 219
220 220 static void mptsas_restart_cmd(void *);
221 221
222 222 static void mptsas_flush_hba(mptsas_t *mpt);
223 223 static void mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun,
224 224 uint8_t tasktype);
225 225 static void mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd,
226 226 uchar_t reason, uint_t stat);
227 227
228 228 static uint_t mptsas_intr(caddr_t arg1, caddr_t arg2);
229 229 static void mptsas_process_intr(mptsas_t *mpt,
230 230 pMpi2ReplyDescriptorsUnion_t reply_desc_union);
231 231 static void mptsas_handle_scsi_io_success(mptsas_t *mpt,
232 232 pMpi2ReplyDescriptorsUnion_t reply_desc);
233 233 static void mptsas_handle_address_reply(mptsas_t *mpt,
234 234 pMpi2ReplyDescriptorsUnion_t reply_desc);
235 235 static int mptsas_wait_intr(mptsas_t *mpt, int polltime);
236 236 static void mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd,
237 237 uint32_t *control, pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl);
238 238
239 239 static void mptsas_watch(void *arg);
240 240 static void mptsas_watchsubr(mptsas_t *mpt);
241 241 static void mptsas_cmd_timeout(mptsas_t *mpt, uint16_t devhdl);
242 242
243 243 static void mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd);
244 244 static int mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply,
245 245 uint8_t *data, uint32_t request_size, uint32_t reply_size,
246 246 uint32_t data_size, uint32_t direction, uint8_t *dataout,
247 247 uint32_t dataout_size, short timeout, int mode);
248 248 static int mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl);
249 249
250 250 static uint8_t mptsas_get_fw_diag_buffer_number(mptsas_t *mpt,
251 251 uint32_t unique_id);
252 252 static void mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd);
253 253 static int mptsas_post_fw_diag_buffer(mptsas_t *mpt,
254 254 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code);
255 255 static int mptsas_release_fw_diag_buffer(mptsas_t *mpt,
256 256 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code,
257 257 uint32_t diag_type);
258 258 static int mptsas_diag_register(mptsas_t *mpt,
259 259 mptsas_fw_diag_register_t *diag_register, uint32_t *return_code);
260 260 static int mptsas_diag_unregister(mptsas_t *mpt,
261 261 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code);
262 262 static int mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query,
263 263 uint32_t *return_code);
264 264 static int mptsas_diag_read_buffer(mptsas_t *mpt,
265 265 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf,
266 266 uint32_t *return_code, int ioctl_mode);
267 267 static int mptsas_diag_release(mptsas_t *mpt,
268 268 mptsas_fw_diag_release_t *diag_release, uint32_t *return_code);
269 269 static int mptsas_do_diag_action(mptsas_t *mpt, uint32_t action,
270 270 uint8_t *diag_action, uint32_t length, uint32_t *return_code,
271 271 int ioctl_mode);
272 272 static int mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *data,
273 273 int mode);
274 274
275 275 static int mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd,
276 276 int cmdlen, int tgtlen, int statuslen, int kf);
277 277 static void mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd);
278 278
279 279 static int mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags);
280 280 static void mptsas_kmem_cache_destructor(void *buf, void *cdrarg);
281 281
282 282 static int mptsas_cache_frames_constructor(void *buf, void *cdrarg,
283 283 int kmflags);
284 284 static void mptsas_cache_frames_destructor(void *buf, void *cdrarg);
285 285
286 286 static void mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply,
287 287 mptsas_cmd_t *cmd);
288 288 static void mptsas_check_task_mgt(mptsas_t *mpt,
289 289 pMpi2SCSIManagementReply_t reply, mptsas_cmd_t *cmd);
290 290 static int mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap,
291 291 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp,
292 292 int *resid);
293 293
294 294 static int mptsas_alloc_active_slots(mptsas_t *mpt, int flag);
295 295 static void mptsas_free_active_slots(mptsas_t *mpt);
296 296 static int mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
297 297
298 298 static void mptsas_restart_hba(mptsas_t *mpt);
299 299 static void mptsas_restart_waitq(mptsas_t *mpt);
300 300
301 301 static void mptsas_deliver_doneq_thread(mptsas_t *mpt);
302 302 static void mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd);
303 303 static void mptsas_doneq_mv(mptsas_t *mpt, uint64_t t);
304 304
305 305 static mptsas_cmd_t *mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t);
306 306 static void mptsas_doneq_empty(mptsas_t *mpt);
307 307 static void mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg);
308 308
309 309 static mptsas_cmd_t *mptsas_waitq_rm(mptsas_t *mpt);
310 310 static void mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd);
311 311 static mptsas_cmd_t *mptsas_tx_waitq_rm(mptsas_t *mpt);
312 312 static void mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd);
313 313
314 314
315 315 static void mptsas_start_watch_reset_delay();
316 316 static void mptsas_setup_bus_reset_delay(mptsas_t *mpt);
317 317 static void mptsas_watch_reset_delay(void *arg);
318 318 static int mptsas_watch_reset_delay_subr(mptsas_t *mpt);
319 319
320 320 /*
321 321 * helper functions
322 322 */
323 323 static void mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
324 324
325 325 static dev_info_t *mptsas_find_child(dev_info_t *pdip, char *name);
326 326 static dev_info_t *mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy);
327 327 static dev_info_t *mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr,
328 328 int lun);
329 329 static mdi_pathinfo_t *mptsas_find_path_addr(dev_info_t *pdip, uint64_t sasaddr,
330 330 int lun);
331 331 static mdi_pathinfo_t *mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy);
332 332 static dev_info_t *mptsas_find_smp_child(dev_info_t *pdip, char *str_wwn);
333 333
334 334 static int mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy,
335 335 int *lun);
336 336 static int mptsas_parse_smp_name(char *name, uint64_t *wwn);
337 337
338 338 static mptsas_target_t *mptsas_phy_to_tgt(mptsas_t *mpt, int phymask,
339 339 uint8_t phy);
340 340 static mptsas_target_t *mptsas_wwid_to_ptgt(mptsas_t *mpt, int phymask,
341 341 uint64_t wwid);
342 342 static mptsas_smp_t *mptsas_wwid_to_psmp(mptsas_t *mpt, int phymask,
343 343 uint64_t wwid);
344 344
345 345 static int mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun,
346 346 uchar_t page, unsigned char *buf, int len, int *rlen, uchar_t evpd);
347 347
348 348 static int mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address,
349 349 uint16_t *handle, mptsas_target_t **pptgt);
350 350 static void mptsas_update_phymask(mptsas_t *mpt);
351 351
352 352 static int mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt,
353 353 uint32_t *status, uint8_t cmd);
354 354 static dev_info_t *mptsas_get_dip_from_dev(dev_t dev,
355 355 mptsas_phymask_t *phymask);
356 356 static mptsas_target_t *mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr,
357 357 mptsas_phymask_t phymask);
358 358 static int mptsas_flush_led_status(mptsas_t *mpt, mptsas_target_t *ptgt);
359 359
360 360
361 361 /*
362 362 * Enumeration / DR functions
363 363 */
364 364 static void mptsas_config_all(dev_info_t *pdip);
365 365 static int mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun,
366 366 dev_info_t **lundip);
367 367 static int mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun,
368 368 dev_info_t **lundip);
369 369
370 370 static int mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt);
371 371 static int mptsas_offline_target(dev_info_t *pdip, char *name);
372 372
373 373 static int mptsas_config_raid(dev_info_t *pdip, uint16_t target,
374 374 dev_info_t **dip);
375 375
376 376 static int mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt);
377 377 static int mptsas_probe_lun(dev_info_t *pdip, int lun,
378 378 dev_info_t **dip, mptsas_target_t *ptgt);
379 379
380 380 static int mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq,
381 381 dev_info_t **dip, mptsas_target_t *ptgt, int lun);
382 382
383 383 static int mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *sd,
384 384 char *guid, dev_info_t **dip, mptsas_target_t *ptgt, int lun);
385 385 static int mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *sd,
386 386 char *guid, dev_info_t **dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt,
387 387 int lun);
388 388
389 389 static void mptsas_offline_missed_luns(dev_info_t *pdip,
390 390 uint16_t *repluns, int lun_cnt, mptsas_target_t *ptgt);
391 391 static int mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip,
392 392 mdi_pathinfo_t *rpip, uint_t flags);
393 393
394 394 static int mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn,
395 395 dev_info_t **smp_dip);
396 396 static int mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
397 397 uint_t flags);
398 398
399 399 static int mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data,
400 400 int mode, int *rval);
401 401 static int mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data,
402 402 int mode, int *rval);
403 403 static int mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data,
404 404 int mode, int *rval);
405 405 static void mptsas_record_event(void *args);
406 406 static int mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data,
407 407 int mode);
408 408
409 409 static void mptsas_hash_init(mptsas_hash_table_t *hashtab);
410 410 static void mptsas_hash_uninit(mptsas_hash_table_t *hashtab, size_t datalen);
411 411 static void mptsas_hash_add(mptsas_hash_table_t *hashtab, void *data);
412 412 static void * mptsas_hash_rem(mptsas_hash_table_t *hashtab, uint64_t key1,
413 413 mptsas_phymask_t key2);
414 414 static void * mptsas_hash_search(mptsas_hash_table_t *hashtab, uint64_t key1,
415 415 mptsas_phymask_t key2);
416 416 static void * mptsas_hash_traverse(mptsas_hash_table_t *hashtab, int pos);
417 417
418 418 mptsas_target_t *mptsas_tgt_alloc(mptsas_hash_table_t *, uint16_t, uint64_t,
419 419 uint32_t, mptsas_phymask_t, uint8_t);
420 420 static mptsas_smp_t *mptsas_smp_alloc(mptsas_hash_table_t *hashtab,
421 421 mptsas_smp_t *data);
422 422 static void mptsas_smp_free(mptsas_hash_table_t *hashtab, uint64_t wwid,
423 423 mptsas_phymask_t phymask);
424 424 static void mptsas_tgt_free(mptsas_hash_table_t *, uint64_t, mptsas_phymask_t);
425 425 static void * mptsas_search_by_devhdl(mptsas_hash_table_t *, uint16_t);
426 426 static int mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
427 427 dev_info_t **smp_dip);
428 428
429 429 /*
430 430 * Power management functions
431 431 */
432 432 static int mptsas_get_pci_cap(mptsas_t *mpt);
433 433 static int mptsas_init_pm(mptsas_t *mpt);
434 434
435 435 /*
436 436 * MPT MSI tunable:
437 437 *
438 438 * By default MSI is enabled on all supported platforms.
439 439 */
440 440 boolean_t mptsas_enable_msi = B_TRUE;
441 441 boolean_t mptsas_physical_bind_failed_page_83 = B_FALSE;
442 442
443 443 static int mptsas_register_intrs(mptsas_t *);
444 444 static void mptsas_unregister_intrs(mptsas_t *);
445 445 static int mptsas_add_intrs(mptsas_t *, int);
446 446 static void mptsas_rem_intrs(mptsas_t *);
447 447
448 448 /*
449 449 * FMA Prototypes
450 450 */
451 451 static void mptsas_fm_init(mptsas_t *mpt);
452 452 static void mptsas_fm_fini(mptsas_t *mpt);
453 453 static int mptsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *, const void *);
454 454
455 455 extern pri_t minclsyspri, maxclsyspri;
456 456
457 457 /*
458 458 * This device is created by the SCSI pseudo nexus driver (SCSI vHCI). It is
459 459 * under this device that the paths to a physical device are created when
460 460 * MPxIO is used.
461 461 */
462 462 extern dev_info_t *scsi_vhci_dip;
463 463
464 464 /*
465 465 * Tunable timeout value for Inquiry VPD page 0x83
466 466 * By default the value is 30 seconds.
467 467 */
468 468 int mptsas_inq83_retry_timeout = 30;
469 469
470 470 /*
471 471 * This is used to allocate memory for message frame storage, not for
472 472 * data I/O DMA. All message frames must be stored in the first 4G of
473 473 * physical memory.
474 474 */
475 475 ddi_dma_attr_t mptsas_dma_attrs = {
476 476 DMA_ATTR_V0, /* attribute layout version */
477 477 0x0ull, /* address low - should be 0 (longlong) */
478 478 0xffffffffull, /* address high - 32-bit max range */
479 479 0x00ffffffull, /* count max - max DMA object size */
480 480 4, /* allocation alignment requirements */
481 481 0x78, /* burstsizes - binary encoded values */
482 482 1, /* minxfer - gran. of DMA engine */
483 483 0x00ffffffull, /* maxxfer - gran. of DMA engine */
484 484 0xffffffffull, /* max segment size (DMA boundary) */
485 485 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */
486 486 512, /* granularity - device transfer size */
487 487 0 /* flags, set to 0 */
488 488 };
489 489
490 490 /*
491 491 * This is used for data I/O DMA memory allocation. (full 64-bit DMA
492 492 * physical addresses are supported.)
493 493 */
494 494 ddi_dma_attr_t mptsas_dma_attrs64 = {
495 495 DMA_ATTR_V0, /* attribute layout version */
496 496 0x0ull, /* address low - should be 0 (longlong) */
497 497 0xffffffffffffffffull, /* address high - 64-bit max */
498 498 0x00ffffffull, /* count max - max DMA object size */
499 499 4, /* allocation alignment requirements */
500 500 0x78, /* burstsizes - binary encoded values */
501 501 1, /* minxfer - gran. of DMA engine */
502 502 0x00ffffffull, /* maxxfer - gran. of DMA engine */
503 503 0xffffffffull, /* max segment size (DMA boundary) */
504 504 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */
505 505 512, /* granularity - device transfer size */
506 506 DDI_DMA_RELAXED_ORDERING /* flags, enable relaxed ordering */
507 507 };
508 508
509 509 ddi_device_acc_attr_t mptsas_dev_attr = {
510 510 DDI_DEVICE_ATTR_V1,
511 511 DDI_STRUCTURE_LE_ACC,
512 512 DDI_STRICTORDER_ACC,
513 513 DDI_DEFAULT_ACC
514 514 };
515 515
516 516 static struct cb_ops mptsas_cb_ops = {
517 517 scsi_hba_open, /* open */
518 518 scsi_hba_close, /* close */
519 519 nodev, /* strategy */
520 520 nodev, /* print */
521 521 nodev, /* dump */
522 522 nodev, /* read */
523 523 nodev, /* write */
524 524 mptsas_ioctl, /* ioctl */
525 525 nodev, /* devmap */
526 526 nodev, /* mmap */
527 527 nodev, /* segmap */
528 528 nochpoll, /* chpoll */
529 529 ddi_prop_op, /* cb_prop_op */
530 530 NULL, /* streamtab */
531 531 D_MP, /* cb_flag */
532 532 CB_REV, /* rev */
533 533 nodev, /* aread */
534 534 nodev /* awrite */
535 535 };
536 536
537 537 static struct dev_ops mptsas_ops = {
538 538 DEVO_REV, /* devo_rev, */
539 539 0, /* refcnt */
540 540 ddi_no_info, /* info */
541 541 nulldev, /* identify */
542 542 nulldev, /* probe */
543 543 mptsas_attach, /* attach */
544 544 mptsas_detach, /* detach */
545 545 #ifdef __sparc
546 546 mptsas_reset,
547 547 #else
548 548 nodev, /* reset */
549 549 #endif /* __sparc */
550 550 &mptsas_cb_ops, /* driver operations */
551 551 NULL, /* bus operations */
552 552 mptsas_power, /* power management */
553 553 #ifdef __sparc
554 554 ddi_quiesce_not_needed
555 555 #else
556 556 mptsas_quiesce /* quiesce */
557 557 #endif /* __sparc */
558 558 };
559 559
560 560
561 561 #define MPTSAS_MOD_STRING "MPTSAS HBA Driver 00.00.00.24"
562 562
563 563 static struct modldrv modldrv = {
564 564 &mod_driverops, /* Type of module. This one is a driver */
565 565 MPTSAS_MOD_STRING, /* Name of the module. */
566 566 &mptsas_ops, /* driver ops */
567 567 };
568 568
569 569 static struct modlinkage modlinkage = {
570 570 MODREV_1, &modldrv, NULL
571 571 };
572 572 #define TARGET_PROP "target"
573 573 #define LUN_PROP "lun"
574 574 #define LUN64_PROP "lun64"
575 575 #define SAS_PROP "sas-mpt"
576 576 #define MDI_GUID "wwn"
577 577 #define NDI_GUID "guid"
578 578 #define MPTSAS_DEV_GONE "mptsas_dev_gone"
579 579
580 580 /*
581 581 * Local static data
582 582 */
583 583 #if defined(MPTSAS_DEBUG)
584 584 uint32_t mptsas_debug_flags = 0;
585 585 #endif /* defined(MPTSAS_DEBUG) */
586 586 uint32_t mptsas_debug_resets = 0;
587 587
588 588 static kmutex_t mptsas_global_mutex;
589 589 static void *mptsas_state; /* soft state ptr */
590 590 static krwlock_t mptsas_global_rwlock;
591 591
592 592 static kmutex_t mptsas_log_mutex;
593 593 static char mptsas_log_buf[256];
594 594 _NOTE(MUTEX_PROTECTS_DATA(mptsas_log_mutex, mptsas_log_buf))
595 595
596 596 static mptsas_t *mptsas_head, *mptsas_tail;
597 597 static clock_t mptsas_scsi_watchdog_tick;
598 598 static clock_t mptsas_tick;
599 599 static timeout_id_t mptsas_reset_watch;
600 600 static timeout_id_t mptsas_timeout_id;
601 601 static int mptsas_timeouts_enabled = 0;
602 602 /*
603 603 * warlock directives
604 604 */
605 605 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", scsi_pkt \
606 606 mptsas_cmd NcrTableIndirect buf scsi_cdb scsi_status))
607 607 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", smp_pkt))
608 608 _NOTE(SCHEME_PROTECTS_DATA("stable data", scsi_device scsi_address))
609 609 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", mptsas_tgt_private))
610 610 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", scsi_hba_tran::tran_tgt_private))
611 611
612 612 /*
613 613 * SM - HBA statics
614 614 */
615 615 char *mptsas_driver_rev = MPTSAS_MOD_STRING;
616 616
617 617 #ifdef MPTSAS_DEBUG
618 618 void debug_enter(char *);
619 619 #endif
620 620
621 621 /*
622 622 * Notes:
623 623 * - scsi_hba_init(9F) initializes SCSI HBA modules
624 624 * - must call scsi_hba_fini(9F) if modload() fails
625 625 */
626 626 int
627 627 _init(void)
628 628 {
629 629 int status;
630 630 /* CONSTCOND */
631 631 ASSERT(NO_COMPETING_THREADS);
632 632
633 633 NDBG0(("_init"));
634 634
635 635 status = ddi_soft_state_init(&mptsas_state, MPTSAS_SIZE,
636 636 MPTSAS_INITIAL_SOFT_SPACE);
637 637 if (status != 0) {
638 638 return (status);
639 639 }
640 640
641 641 if ((status = scsi_hba_init(&modlinkage)) != 0) {
642 642 ddi_soft_state_fini(&mptsas_state);
643 643 return (status);
644 644 }
645 645
646 646 mutex_init(&mptsas_global_mutex, NULL, MUTEX_DRIVER, NULL);
647 647 rw_init(&mptsas_global_rwlock, NULL, RW_DRIVER, NULL);
648 648 mutex_init(&mptsas_log_mutex, NULL, MUTEX_DRIVER, NULL);
649 649
650 650 if ((status = mod_install(&modlinkage)) != 0) {
651 651 mutex_destroy(&mptsas_log_mutex);
652 652 rw_destroy(&mptsas_global_rwlock);
653 653 mutex_destroy(&mptsas_global_mutex);
654 654 ddi_soft_state_fini(&mptsas_state);
655 655 scsi_hba_fini(&modlinkage);
656 656 }
657 657
658 658 return (status);
659 659 }
660 660
661 661 /*
662 662 * Notes:
663 663 * - scsi_hba_fini(9F) uninitializes SCSI HBA modules
664 664 */
665 665 int
666 666 _fini(void)
667 667 {
668 668 int status;
669 669 /* CONSTCOND */
670 670 ASSERT(NO_COMPETING_THREADS);
671 671
672 672 NDBG0(("_fini"));
673 673
674 674 if ((status = mod_remove(&modlinkage)) == 0) {
675 675 ddi_soft_state_fini(&mptsas_state);
676 676 scsi_hba_fini(&modlinkage);
677 677 mutex_destroy(&mptsas_global_mutex);
678 678 rw_destroy(&mptsas_global_rwlock);
679 679 mutex_destroy(&mptsas_log_mutex);
680 680 }
681 681 return (status);
682 682 }
683 683
684 684 /*
685 685 * The loadable-module _info(9E) entry point
686 686 */
687 687 int
688 688 _info(struct modinfo *modinfop)
689 689 {
690 690 /* CONSTCOND */
691 691 ASSERT(NO_COMPETING_THREADS);
692 692 NDBG0(("mptsas _info"));
693 693
694 694 return (mod_info(&modlinkage, modinfop));
695 695 }
696 696
697 697
698 698 static int
699 699 mptsas_iport_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
700 700 {
701 701 dev_info_t *pdip;
702 702 mptsas_t *mpt;
703 703 scsi_hba_tran_t *hba_tran;
704 704 char *iport = NULL;
705 705 char phymask[MPTSAS_MAX_PHYS];
706 706 mptsas_phymask_t phy_mask = 0;
707 707 int dynamic_port = 0;
708 708 uint32_t page_address;
709 709 char initiator_wwnstr[MPTSAS_WWN_STRLEN];
710 710 int rval = DDI_FAILURE;
711 711 int i = 0;
712 712 uint8_t numphys = 0;
713 713 uint8_t phy_id;
714 714 uint8_t phy_port = 0;
715 715 uint16_t attached_devhdl = 0;
716 716 uint32_t dev_info;
717 717 uint64_t attached_sas_wwn;
718 718 uint16_t dev_hdl;
719 719 uint16_t pdev_hdl;
720 720 uint16_t bay_num, enclosure;
721 721 char attached_wwnstr[MPTSAS_WWN_STRLEN];
722 722
723 723 /* CONSTCOND */
724 724 ASSERT(NO_COMPETING_THREADS);
725 725
726 726 switch (cmd) {
727 727 case DDI_ATTACH:
728 728 break;
729 729
730 730 case DDI_RESUME:
731 731 /*
732 732 * If this a scsi-iport node, nothing to do here.
733 733 */
734 734 return (DDI_SUCCESS);
735 735
736 736 default:
737 737 return (DDI_FAILURE);
738 738 }
739 739
740 740 pdip = ddi_get_parent(dip);
741 741
742 742 if ((hba_tran = ndi_flavorv_get(pdip, SCSA_FLAVOR_SCSI_DEVICE)) ==
743 743 NULL) {
744 744 cmn_err(CE_WARN, "Failed attach iport because fail to "
745 745 "get tran vector for the HBA node");
746 746 return (DDI_FAILURE);
747 747 }
748 748
749 749 mpt = TRAN2MPT(hba_tran);
750 750 ASSERT(mpt != NULL);
751 751 if (mpt == NULL)
752 752 return (DDI_FAILURE);
753 753
754 754 if ((hba_tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) ==
755 755 NULL) {
756 756 mptsas_log(mpt, CE_WARN, "Failed attach iport because fail to "
757 757 "get tran vector for the iport node");
758 758 return (DDI_FAILURE);
759 759 }
760 760
761 761 /*
762 762 * Overwrite parent's tran_hba_private to iport's tran vector
763 763 */
764 764 hba_tran->tran_hba_private = mpt;
765 765
766 766 ddi_report_dev(dip);
767 767
768 768 /*
769 769 * Get SAS address for initiator port according dev_handle
770 770 */
771 771 iport = ddi_get_name_addr(dip);
772 772 if (iport && strncmp(iport, "v0", 2) == 0) {
773 773 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
774 774 MPTSAS_VIRTUAL_PORT, 1) !=
775 775 DDI_PROP_SUCCESS) {
776 776 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
777 777 MPTSAS_VIRTUAL_PORT);
778 778 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
779 779 "prop update failed");
780 780 return (DDI_FAILURE);
781 781 }
782 782 return (DDI_SUCCESS);
783 783 }
784 784
785 785 mutex_enter(&mpt->m_mutex);
786 786 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
787 787 bzero(phymask, sizeof (phymask));
788 788 (void) sprintf(phymask,
789 789 "%x", mpt->m_phy_info[i].phy_mask);
790 790 if (strcmp(phymask, iport) == 0) {
791 791 break;
792 792 }
793 793 }
794 794
795 795 if (i == MPTSAS_MAX_PHYS) {
796 796 mptsas_log(mpt, CE_WARN, "Failed attach port %s because port"
797 797 "seems not exist", iport);
798 798 mutex_exit(&mpt->m_mutex);
799 799 return (DDI_FAILURE);
800 800 }
801 801
802 802 phy_mask = mpt->m_phy_info[i].phy_mask;
803 803
804 804 if (mpt->m_phy_info[i].port_flags & AUTO_PORT_CONFIGURATION)
805 805 dynamic_port = 1;
806 806 else
807 807 dynamic_port = 0;
808 808
809 809 /*
810 810 * Update PHY info for smhba
811 811 */
812 812 if (mptsas_smhba_phy_init(mpt)) {
813 813 mutex_exit(&mpt->m_mutex);
814 814 mptsas_log(mpt, CE_WARN, "mptsas phy update "
815 815 "failed");
816 816 return (DDI_FAILURE);
817 817 }
818 818
819 819 mutex_exit(&mpt->m_mutex);
820 820
821 821 numphys = 0;
822 822 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
823 823 if ((phy_mask >> i) & 0x01) {
824 824 numphys++;
825 825 }
826 826 }
827 827
828 828 bzero(initiator_wwnstr, sizeof (initiator_wwnstr));
829 829 (void) sprintf(initiator_wwnstr, "w%016"PRIx64,
830 830 mpt->un.m_base_wwid);
831 831
832 832 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip,
833 833 SCSI_ADDR_PROP_INITIATOR_PORT, initiator_wwnstr) !=
834 834 DDI_PROP_SUCCESS) {
835 835 (void) ddi_prop_remove(DDI_DEV_T_NONE,
836 836 dip, SCSI_ADDR_PROP_INITIATOR_PORT);
837 837 mptsas_log(mpt, CE_WARN, "mptsas Initiator port "
838 838 "prop update failed");
839 839 return (DDI_FAILURE);
840 840 }
841 841 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
842 842 MPTSAS_NUM_PHYS, numphys) !=
843 843 DDI_PROP_SUCCESS) {
844 844 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, MPTSAS_NUM_PHYS);
845 845 return (DDI_FAILURE);
846 846 }
847 847
848 848 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
849 849 "phymask", phy_mask) !=
850 850 DDI_PROP_SUCCESS) {
851 851 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "phymask");
852 852 mptsas_log(mpt, CE_WARN, "mptsas phy mask "
853 853 "prop update failed");
854 854 return (DDI_FAILURE);
855 855 }
856 856
857 857 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
858 858 "dynamic-port", dynamic_port) !=
859 859 DDI_PROP_SUCCESS) {
860 860 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "dynamic-port");
861 861 mptsas_log(mpt, CE_WARN, "mptsas dynamic port "
862 862 "prop update failed");
863 863 return (DDI_FAILURE);
|
↓ open down ↓ |
863 lines elided |
↑ open up ↑ |
864 864 }
865 865 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
866 866 MPTSAS_VIRTUAL_PORT, 0) !=
867 867 DDI_PROP_SUCCESS) {
868 868 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
869 869 MPTSAS_VIRTUAL_PORT);
870 870 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
871 871 "prop update failed");
872 872 return (DDI_FAILURE);
873 873 }
874 - mptsas_smhba_set_phy_props(mpt,
875 - iport, dip, numphys, &attached_devhdl);
874 + mptsas_smhba_set_all_phy_props(mpt, dip, numphys, phy_mask,
875 + &attached_devhdl);
876 876
877 877 mutex_enter(&mpt->m_mutex);
878 878 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
879 879 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)attached_devhdl;
880 880 rval = mptsas_get_sas_device_page0(mpt, page_address, &dev_hdl,
881 881 &attached_sas_wwn, &dev_info, &phy_port, &phy_id,
882 882 &pdev_hdl, &bay_num, &enclosure);
883 883 if (rval != DDI_SUCCESS) {
884 884 mptsas_log(mpt, CE_WARN,
885 885 "Failed to get device page0 for handle:%d",
886 886 attached_devhdl);
887 887 mutex_exit(&mpt->m_mutex);
888 888 return (DDI_FAILURE);
889 889 }
890 890
891 891 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
892 892 bzero(phymask, sizeof (phymask));
893 893 (void) sprintf(phymask, "%x", mpt->m_phy_info[i].phy_mask);
894 894 if (strcmp(phymask, iport) == 0) {
895 895 (void) sprintf(&mpt->m_phy_info[i].smhba_info.path[0],
896 896 "%x",
897 897 mpt->m_phy_info[i].phy_mask);
898 898 }
899 899 }
900 900 mutex_exit(&mpt->m_mutex);
901 901
902 902 bzero(attached_wwnstr, sizeof (attached_wwnstr));
903 903 (void) sprintf(attached_wwnstr, "w%016"PRIx64,
904 904 attached_sas_wwn);
905 905 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip,
906 906 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
907 907 DDI_PROP_SUCCESS) {
908 908 (void) ddi_prop_remove(DDI_DEV_T_NONE,
909 909 dip, SCSI_ADDR_PROP_ATTACHED_PORT);
910 910 return (DDI_FAILURE);
911 911 }
912 912
913 913 /* Create kstats for each phy on this iport */
914 914
915 915 mptsas_create_phy_stats(mpt, iport, dip);
916 916
917 917 /*
918 918 * register sas hba iport with mdi (MPxIO/vhci)
919 919 */
920 920 if (mdi_phci_register(MDI_HCI_CLASS_SCSI,
921 921 dip, 0) == MDI_SUCCESS) {
922 922 mpt->m_mpxio_enable = TRUE;
923 923 }
924 924 return (DDI_SUCCESS);
925 925 }
926 926
927 927 /*
928 928 * Notes:
929 929 * Set up all device state and allocate data structures,
930 930 * mutexes, condition variables, etc. for device operation.
931 931 * Add interrupts needed.
932 932 * Return DDI_SUCCESS if device is ready, else return DDI_FAILURE.
933 933 */
934 934 static int
935 935 mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
936 936 {
937 937 mptsas_t *mpt = NULL;
938 938 int instance, i, j;
939 939 int doneq_thread_num;
940 940 char intr_added = 0;
941 941 char map_setup = 0;
942 942 char config_setup = 0;
943 943 char hba_attach_setup = 0;
944 944 char smp_attach_setup = 0;
945 945 char mutex_init_done = 0;
946 946 char event_taskq_create = 0;
947 947 char dr_taskq_create = 0;
948 948 char doneq_thread_create = 0;
949 949 scsi_hba_tran_t *hba_tran;
950 950 uint_t mem_bar = MEM_SPACE;
951 951 int rval = DDI_FAILURE;
952 952
953 953 /* CONSTCOND */
954 954 ASSERT(NO_COMPETING_THREADS);
955 955
956 956 if (scsi_hba_iport_unit_address(dip)) {
957 957 return (mptsas_iport_attach(dip, cmd));
958 958 }
959 959
960 960 switch (cmd) {
961 961 case DDI_ATTACH:
962 962 break;
963 963
964 964 case DDI_RESUME:
965 965 if ((hba_tran = ddi_get_driver_private(dip)) == NULL)
966 966 return (DDI_FAILURE);
967 967
968 968 mpt = TRAN2MPT(hba_tran);
969 969
970 970 if (!mpt) {
971 971 return (DDI_FAILURE);
972 972 }
973 973
974 974 /*
975 975 * Reset hardware and softc to "no outstanding commands"
976 976 * Note that a check condition can result on first command
977 977 * to a target.
978 978 */
979 979 mutex_enter(&mpt->m_mutex);
980 980
981 981 /*
982 982 * raise power.
983 983 */
984 984 if (mpt->m_options & MPTSAS_OPT_PM) {
985 985 mutex_exit(&mpt->m_mutex);
986 986 (void) pm_busy_component(dip, 0);
987 987 rval = pm_power_has_changed(dip, 0, PM_LEVEL_D0);
988 988 if (rval == DDI_SUCCESS) {
989 989 mutex_enter(&mpt->m_mutex);
990 990 } else {
991 991 /*
992 992 * The pm_raise_power() call above failed,
993 993 * and that can only occur if we were unable
994 994 * to reset the hardware. This is probably
995 995 * due to unhealty hardware, and because
996 996 * important filesystems(such as the root
997 997 * filesystem) could be on the attached disks,
998 998 * it would not be a good idea to continue,
999 999 * as we won't be entirely certain we are
1000 1000 * writing correct data. So we panic() here
1001 1001 * to not only prevent possible data corruption,
1002 1002 * but to give developers or end users a hope
1003 1003 * of identifying and correcting any problems.
1004 1004 */
1005 1005 fm_panic("mptsas could not reset hardware "
1006 1006 "during resume");
1007 1007 }
1008 1008 }
1009 1009
1010 1010 mpt->m_suspended = 0;
1011 1011
1012 1012 /*
1013 1013 * Reinitialize ioc
1014 1014 */
1015 1015 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1016 1016 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) {
1017 1017 mutex_exit(&mpt->m_mutex);
1018 1018 if (mpt->m_options & MPTSAS_OPT_PM) {
1019 1019 (void) pm_idle_component(dip, 0);
1020 1020 }
1021 1021 fm_panic("mptsas init chip fail during resume");
1022 1022 }
1023 1023 /*
1024 1024 * mptsas_update_driver_data needs interrupts so enable them
1025 1025 * first.
1026 1026 */
1027 1027 MPTSAS_ENABLE_INTR(mpt);
1028 1028 mptsas_update_driver_data(mpt);
1029 1029
1030 1030 /* start requests, if possible */
1031 1031 mptsas_restart_hba(mpt);
1032 1032
1033 1033 mutex_exit(&mpt->m_mutex);
1034 1034
1035 1035 /*
1036 1036 * Restart watch thread
1037 1037 */
1038 1038 mutex_enter(&mptsas_global_mutex);
1039 1039 if (mptsas_timeout_id == 0) {
1040 1040 mptsas_timeout_id = timeout(mptsas_watch, NULL,
1041 1041 mptsas_tick);
1042 1042 mptsas_timeouts_enabled = 1;
1043 1043 }
1044 1044 mutex_exit(&mptsas_global_mutex);
1045 1045
1046 1046 /* report idle status to pm framework */
1047 1047 if (mpt->m_options & MPTSAS_OPT_PM) {
1048 1048 (void) pm_idle_component(dip, 0);
1049 1049 }
1050 1050
1051 1051 return (DDI_SUCCESS);
1052 1052
1053 1053 default:
1054 1054 return (DDI_FAILURE);
1055 1055
1056 1056 }
1057 1057
1058 1058 instance = ddi_get_instance(dip);
1059 1059
1060 1060 /*
1061 1061 * Allocate softc information.
1062 1062 */
1063 1063 if (ddi_soft_state_zalloc(mptsas_state, instance) != DDI_SUCCESS) {
1064 1064 mptsas_log(NULL, CE_WARN,
1065 1065 "mptsas%d: cannot allocate soft state", instance);
1066 1066 goto fail;
1067 1067 }
1068 1068
1069 1069 mpt = ddi_get_soft_state(mptsas_state, instance);
1070 1070
1071 1071 if (mpt == NULL) {
1072 1072 mptsas_log(NULL, CE_WARN,
1073 1073 "mptsas%d: cannot get soft state", instance);
1074 1074 goto fail;
1075 1075 }
1076 1076
1077 1077 /* Indicate that we are 'sizeof (scsi_*(9S))' clean. */
1078 1078 scsi_size_clean(dip);
1079 1079
1080 1080 mpt->m_dip = dip;
1081 1081 mpt->m_instance = instance;
1082 1082
1083 1083 /* Make a per-instance copy of the structures */
1084 1084 mpt->m_io_dma_attr = mptsas_dma_attrs64;
1085 1085 mpt->m_msg_dma_attr = mptsas_dma_attrs;
1086 1086 mpt->m_reg_acc_attr = mptsas_dev_attr;
1087 1087 mpt->m_dev_acc_attr = mptsas_dev_attr;
1088 1088
1089 1089 /*
1090 1090 * Initialize FMA
1091 1091 */
1092 1092 mpt->m_fm_capabilities = ddi_getprop(DDI_DEV_T_ANY, mpt->m_dip,
1093 1093 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable",
1094 1094 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
1095 1095 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
1096 1096
1097 1097 mptsas_fm_init(mpt);
1098 1098
1099 1099 if (mptsas_alloc_handshake_msg(mpt,
1100 1100 sizeof (Mpi2SCSITaskManagementRequest_t)) == DDI_FAILURE) {
1101 1101 mptsas_log(mpt, CE_WARN, "cannot initialize handshake msg.");
1102 1102 goto fail;
1103 1103 }
1104 1104
1105 1105 /*
1106 1106 * Setup configuration space
1107 1107 */
1108 1108 if (mptsas_config_space_init(mpt) == FALSE) {
1109 1109 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init failed");
1110 1110 goto fail;
1111 1111 }
1112 1112 config_setup++;
1113 1113
1114 1114 if (ddi_regs_map_setup(dip, mem_bar, (caddr_t *)&mpt->m_reg,
1115 1115 0, 0, &mpt->m_reg_acc_attr, &mpt->m_datap) != DDI_SUCCESS) {
1116 1116 mptsas_log(mpt, CE_WARN, "map setup failed");
1117 1117 goto fail;
1118 1118 }
1119 1119 map_setup++;
1120 1120
1121 1121 /*
1122 1122 * A taskq is created for dealing with the event handler
1123 1123 */
1124 1124 if ((mpt->m_event_taskq = ddi_taskq_create(dip, "mptsas_event_taskq",
1125 1125 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
1126 1126 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create failed");
1127 1127 goto fail;
1128 1128 }
1129 1129 event_taskq_create++;
1130 1130
1131 1131 /*
1132 1132 * A taskq is created for dealing with dr events
1133 1133 */
1134 1134 if ((mpt->m_dr_taskq = ddi_taskq_create(dip,
1135 1135 "mptsas_dr_taskq",
1136 1136 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
1137 1137 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create for discovery "
1138 1138 "failed");
1139 1139 goto fail;
1140 1140 }
1141 1141 dr_taskq_create++;
1142 1142
1143 1143 mpt->m_doneq_thread_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1144 1144 0, "mptsas_doneq_thread_threshold_prop", 10);
1145 1145 mpt->m_doneq_length_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1146 1146 0, "mptsas_doneq_length_threshold_prop", 8);
1147 1147 mpt->m_doneq_thread_n = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1148 1148 0, "mptsas_doneq_thread_n_prop", 8);
1149 1149
1150 1150 if (mpt->m_doneq_thread_n) {
1151 1151 cv_init(&mpt->m_doneq_thread_cv, NULL, CV_DRIVER, NULL);
1152 1152 mutex_init(&mpt->m_doneq_mutex, NULL, MUTEX_DRIVER, NULL);
1153 1153
1154 1154 mutex_enter(&mpt->m_doneq_mutex);
1155 1155 mpt->m_doneq_thread_id =
1156 1156 kmem_zalloc(sizeof (mptsas_doneq_thread_list_t)
1157 1157 * mpt->m_doneq_thread_n, KM_SLEEP);
1158 1158
1159 1159 for (j = 0; j < mpt->m_doneq_thread_n; j++) {
1160 1160 cv_init(&mpt->m_doneq_thread_id[j].cv, NULL,
1161 1161 CV_DRIVER, NULL);
1162 1162 mutex_init(&mpt->m_doneq_thread_id[j].mutex, NULL,
1163 1163 MUTEX_DRIVER, NULL);
1164 1164 mutex_enter(&mpt->m_doneq_thread_id[j].mutex);
1165 1165 mpt->m_doneq_thread_id[j].flag |=
1166 1166 MPTSAS_DONEQ_THREAD_ACTIVE;
1167 1167 mpt->m_doneq_thread_id[j].arg.mpt = mpt;
1168 1168 mpt->m_doneq_thread_id[j].arg.t = j;
1169 1169 mpt->m_doneq_thread_id[j].threadp =
1170 1170 thread_create(NULL, 0, mptsas_doneq_thread,
1171 1171 &mpt->m_doneq_thread_id[j].arg,
1172 1172 0, &p0, TS_RUN, minclsyspri);
1173 1173 mpt->m_doneq_thread_id[j].donetail =
1174 1174 &mpt->m_doneq_thread_id[j].doneq;
1175 1175 mutex_exit(&mpt->m_doneq_thread_id[j].mutex);
1176 1176 }
1177 1177 mutex_exit(&mpt->m_doneq_mutex);
1178 1178 doneq_thread_create++;
1179 1179 }
1180 1180
1181 1181 /* Initialize mutex used in interrupt handler */
1182 1182 mutex_init(&mpt->m_mutex, NULL, MUTEX_DRIVER,
1183 1183 DDI_INTR_PRI(mpt->m_intr_pri));
1184 1184 mutex_init(&mpt->m_passthru_mutex, NULL, MUTEX_DRIVER, NULL);
1185 1185 mutex_init(&mpt->m_tx_waitq_mutex, NULL, MUTEX_DRIVER,
1186 1186 DDI_INTR_PRI(mpt->m_intr_pri));
1187 1187 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1188 1188 mutex_init(&mpt->m_phy_info[i].smhba_info.phy_mutex,
1189 1189 NULL, MUTEX_DRIVER,
1190 1190 DDI_INTR_PRI(mpt->m_intr_pri));
1191 1191 }
1192 1192
1193 1193 cv_init(&mpt->m_cv, NULL, CV_DRIVER, NULL);
1194 1194 cv_init(&mpt->m_passthru_cv, NULL, CV_DRIVER, NULL);
1195 1195 cv_init(&mpt->m_fw_cv, NULL, CV_DRIVER, NULL);
1196 1196 cv_init(&mpt->m_config_cv, NULL, CV_DRIVER, NULL);
1197 1197 cv_init(&mpt->m_fw_diag_cv, NULL, CV_DRIVER, NULL);
1198 1198 mutex_init_done++;
1199 1199
1200 1200 /*
1201 1201 * Disable hardware interrupt since we're not ready to
1202 1202 * handle it yet.
1203 1203 */
1204 1204 MPTSAS_DISABLE_INTR(mpt);
1205 1205 if (mptsas_register_intrs(mpt) == FALSE)
1206 1206 goto fail;
1207 1207 intr_added++;
1208 1208
1209 1209 mutex_enter(&mpt->m_mutex);
1210 1210 /*
1211 1211 * Initialize power management component
1212 1212 */
1213 1213 if (mpt->m_options & MPTSAS_OPT_PM) {
1214 1214 if (mptsas_init_pm(mpt)) {
1215 1215 mutex_exit(&mpt->m_mutex);
1216 1216 mptsas_log(mpt, CE_WARN, "mptsas pm initialization "
1217 1217 "failed");
1218 1218 goto fail;
1219 1219 }
1220 1220 }
1221 1221
1222 1222 /*
1223 1223 * Initialize chip using Message Unit Reset, if allowed
1224 1224 */
1225 1225 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1226 1226 if (mptsas_init_chip(mpt, TRUE) == DDI_FAILURE) {
1227 1227 mutex_exit(&mpt->m_mutex);
1228 1228 mptsas_log(mpt, CE_WARN, "mptsas chip initialization failed");
1229 1229 goto fail;
1230 1230 }
1231 1231
1232 1232 /*
1233 1233 * Fill in the phy_info structure and get the base WWID
1234 1234 */
1235 1235 if (mptsas_get_manufacture_page5(mpt) == DDI_FAILURE) {
1236 1236 mptsas_log(mpt, CE_WARN,
1237 1237 "mptsas_get_manufacture_page5 failed!");
1238 1238 goto fail;
1239 1239 }
1240 1240
1241 1241 if (mptsas_get_sas_io_unit_page_hndshk(mpt)) {
1242 1242 mptsas_log(mpt, CE_WARN,
1243 1243 "mptsas_get_sas_io_unit_page_hndshk failed!");
1244 1244 goto fail;
1245 1245 }
1246 1246
1247 1247 if (mptsas_get_manufacture_page0(mpt) == DDI_FAILURE) {
1248 1248 mptsas_log(mpt, CE_WARN,
1249 1249 "mptsas_get_manufacture_page0 failed!");
1250 1250 goto fail;
1251 1251 }
1252 1252
1253 1253 mutex_exit(&mpt->m_mutex);
1254 1254
1255 1255 /*
1256 1256 * Register the iport for multiple port HBA
1257 1257 */
1258 1258 mptsas_iport_register(mpt);
1259 1259
1260 1260 /*
1261 1261 * initialize SCSI HBA transport structure
1262 1262 */
1263 1263 if (mptsas_hba_setup(mpt) == FALSE)
1264 1264 goto fail;
1265 1265 hba_attach_setup++;
1266 1266
1267 1267 if (mptsas_smp_setup(mpt) == FALSE)
1268 1268 goto fail;
1269 1269 smp_attach_setup++;
1270 1270
1271 1271 if (mptsas_cache_create(mpt) == FALSE)
1272 1272 goto fail;
1273 1273
1274 1274 mpt->m_scsi_reset_delay = ddi_prop_get_int(DDI_DEV_T_ANY,
1275 1275 dip, 0, "scsi-reset-delay", SCSI_DEFAULT_RESET_DELAY);
1276 1276 if (mpt->m_scsi_reset_delay == 0) {
1277 1277 mptsas_log(mpt, CE_NOTE,
1278 1278 "scsi_reset_delay of 0 is not recommended,"
1279 1279 " resetting to SCSI_DEFAULT_RESET_DELAY\n");
1280 1280 mpt->m_scsi_reset_delay = SCSI_DEFAULT_RESET_DELAY;
1281 1281 }
1282 1282
1283 1283 /*
1284 1284 * Initialize the wait and done FIFO queue
1285 1285 */
1286 1286 mpt->m_donetail = &mpt->m_doneq;
1287 1287 mpt->m_waitqtail = &mpt->m_waitq;
1288 1288 mpt->m_tx_waitqtail = &mpt->m_tx_waitq;
1289 1289 mpt->m_tx_draining = 0;
1290 1290
1291 1291 /*
1292 1292 * ioc cmd queue initialize
1293 1293 */
1294 1294 mpt->m_ioc_event_cmdtail = &mpt->m_ioc_event_cmdq;
1295 1295 mpt->m_dev_handle = 0xFFFF;
1296 1296
1297 1297 MPTSAS_ENABLE_INTR(mpt);
1298 1298
1299 1299 /*
1300 1300 * enable event notification
1301 1301 */
1302 1302 mutex_enter(&mpt->m_mutex);
1303 1303 if (mptsas_ioc_enable_event_notification(mpt)) {
1304 1304 mutex_exit(&mpt->m_mutex);
1305 1305 goto fail;
1306 1306 }
1307 1307 mutex_exit(&mpt->m_mutex);
1308 1308
1309 1309 /*
1310 1310 * Initialize PHY info for smhba
1311 1311 */
1312 1312 if (mptsas_smhba_setup(mpt)) {
1313 1313 mptsas_log(mpt, CE_WARN, "mptsas phy initialization "
1314 1314 "failed");
1315 1315 goto fail;
1316 1316 }
1317 1317
1318 1318 /* Check all dma handles allocated in attach */
1319 1319 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl)
1320 1320 != DDI_SUCCESS) ||
1321 1321 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl)
1322 1322 != DDI_SUCCESS) ||
1323 1323 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl)
1324 1324 != DDI_SUCCESS) ||
1325 1325 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl)
1326 1326 != DDI_SUCCESS) ||
1327 1327 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl)
1328 1328 != DDI_SUCCESS)) {
1329 1329 goto fail;
1330 1330 }
1331 1331
1332 1332 /* Check all acc handles allocated in attach */
1333 1333 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) ||
1334 1334 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl)
1335 1335 != DDI_SUCCESS) ||
1336 1336 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl)
1337 1337 != DDI_SUCCESS) ||
1338 1338 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl)
1339 1339 != DDI_SUCCESS) ||
1340 1340 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl)
1341 1341 != DDI_SUCCESS) ||
1342 1342 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl)
1343 1343 != DDI_SUCCESS) ||
1344 1344 (mptsas_check_acc_handle(mpt->m_config_handle)
1345 1345 != DDI_SUCCESS)) {
1346 1346 goto fail;
1347 1347 }
1348 1348
1349 1349 /*
1350 1350 * After this point, we are not going to fail the attach.
1351 1351 */
1352 1352 /*
1353 1353 * used for mptsas_watch
1354 1354 */
1355 1355 mptsas_list_add(mpt);
1356 1356
1357 1357 mutex_enter(&mptsas_global_mutex);
1358 1358 if (mptsas_timeouts_enabled == 0) {
1359 1359 mptsas_scsi_watchdog_tick = ddi_prop_get_int(DDI_DEV_T_ANY,
1360 1360 dip, 0, "scsi-watchdog-tick", DEFAULT_WD_TICK);
1361 1361
1362 1362 mptsas_tick = mptsas_scsi_watchdog_tick *
1363 1363 drv_usectohz((clock_t)1000000);
1364 1364
1365 1365 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick);
1366 1366 mptsas_timeouts_enabled = 1;
1367 1367 }
1368 1368 mutex_exit(&mptsas_global_mutex);
1369 1369
1370 1370 /* Print message of HBA present */
1371 1371 ddi_report_dev(dip);
1372 1372
1373 1373 /* report idle status to pm framework */
1374 1374 if (mpt->m_options & MPTSAS_OPT_PM) {
1375 1375 (void) pm_idle_component(dip, 0);
1376 1376 }
1377 1377
1378 1378 return (DDI_SUCCESS);
1379 1379
1380 1380 fail:
1381 1381 mptsas_log(mpt, CE_WARN, "attach failed");
1382 1382 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE);
1383 1383 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST);
1384 1384 if (mpt) {
1385 1385 mutex_enter(&mptsas_global_mutex);
1386 1386
1387 1387 if (mptsas_timeout_id && (mptsas_head == NULL)) {
1388 1388 timeout_id_t tid = mptsas_timeout_id;
1389 1389 mptsas_timeouts_enabled = 0;
1390 1390 mptsas_timeout_id = 0;
1391 1391 mutex_exit(&mptsas_global_mutex);
1392 1392 (void) untimeout(tid);
1393 1393 mutex_enter(&mptsas_global_mutex);
1394 1394 }
1395 1395 mutex_exit(&mptsas_global_mutex);
1396 1396 /* deallocate in reverse order */
1397 1397 mptsas_cache_destroy(mpt);
1398 1398
1399 1399 if (smp_attach_setup) {
1400 1400 mptsas_smp_teardown(mpt);
1401 1401 }
1402 1402 if (hba_attach_setup) {
1403 1403 mptsas_hba_teardown(mpt);
1404 1404 }
1405 1405
1406 1406 if (mpt->m_active) {
1407 1407 mptsas_hash_uninit(&mpt->m_active->m_smptbl,
1408 1408 sizeof (mptsas_smp_t));
1409 1409 mptsas_hash_uninit(&mpt->m_active->m_tgttbl,
1410 1410 sizeof (mptsas_target_t));
1411 1411 mptsas_free_active_slots(mpt);
1412 1412 }
1413 1413 if (intr_added) {
1414 1414 mptsas_unregister_intrs(mpt);
1415 1415 }
1416 1416
1417 1417 if (doneq_thread_create) {
1418 1418 mutex_enter(&mpt->m_doneq_mutex);
1419 1419 doneq_thread_num = mpt->m_doneq_thread_n;
1420 1420 for (j = 0; j < mpt->m_doneq_thread_n; j++) {
1421 1421 mutex_enter(&mpt->m_doneq_thread_id[j].mutex);
1422 1422 mpt->m_doneq_thread_id[j].flag &=
1423 1423 (~MPTSAS_DONEQ_THREAD_ACTIVE);
1424 1424 cv_signal(&mpt->m_doneq_thread_id[j].cv);
1425 1425 mutex_exit(&mpt->m_doneq_thread_id[j].mutex);
1426 1426 }
1427 1427 while (mpt->m_doneq_thread_n) {
1428 1428 cv_wait(&mpt->m_doneq_thread_cv,
1429 1429 &mpt->m_doneq_mutex);
1430 1430 }
1431 1431 for (j = 0; j < doneq_thread_num; j++) {
1432 1432 cv_destroy(&mpt->m_doneq_thread_id[j].cv);
1433 1433 mutex_destroy(&mpt->m_doneq_thread_id[j].mutex);
1434 1434 }
1435 1435 kmem_free(mpt->m_doneq_thread_id,
1436 1436 sizeof (mptsas_doneq_thread_list_t)
1437 1437 * doneq_thread_num);
1438 1438 mutex_exit(&mpt->m_doneq_mutex);
1439 1439 cv_destroy(&mpt->m_doneq_thread_cv);
1440 1440 mutex_destroy(&mpt->m_doneq_mutex);
1441 1441 }
1442 1442 if (event_taskq_create) {
1443 1443 ddi_taskq_destroy(mpt->m_event_taskq);
1444 1444 }
1445 1445 if (dr_taskq_create) {
1446 1446 ddi_taskq_destroy(mpt->m_dr_taskq);
1447 1447 }
1448 1448 if (mutex_init_done) {
1449 1449 mutex_destroy(&mpt->m_tx_waitq_mutex);
1450 1450 mutex_destroy(&mpt->m_passthru_mutex);
1451 1451 mutex_destroy(&mpt->m_mutex);
1452 1452 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1453 1453 mutex_destroy(
1454 1454 &mpt->m_phy_info[i].smhba_info.phy_mutex);
1455 1455 }
1456 1456 cv_destroy(&mpt->m_cv);
1457 1457 cv_destroy(&mpt->m_passthru_cv);
1458 1458 cv_destroy(&mpt->m_fw_cv);
1459 1459 cv_destroy(&mpt->m_config_cv);
1460 1460 cv_destroy(&mpt->m_fw_diag_cv);
1461 1461 }
1462 1462
1463 1463 if (map_setup) {
1464 1464 mptsas_cfg_fini(mpt);
1465 1465 }
1466 1466 if (config_setup) {
1467 1467 mptsas_config_space_fini(mpt);
1468 1468 }
1469 1469 mptsas_free_handshake_msg(mpt);
1470 1470 mptsas_hba_fini(mpt);
1471 1471
1472 1472 mptsas_fm_fini(mpt);
1473 1473 ddi_soft_state_free(mptsas_state, instance);
1474 1474 ddi_prop_remove_all(dip);
1475 1475 }
1476 1476 return (DDI_FAILURE);
1477 1477 }
1478 1478
1479 1479 static int
1480 1480 mptsas_suspend(dev_info_t *devi)
1481 1481 {
1482 1482 mptsas_t *mpt, *g;
1483 1483 scsi_hba_tran_t *tran;
1484 1484
1485 1485 if (scsi_hba_iport_unit_address(devi)) {
1486 1486 return (DDI_SUCCESS);
1487 1487 }
1488 1488
1489 1489 if ((tran = ddi_get_driver_private(devi)) == NULL)
1490 1490 return (DDI_SUCCESS);
1491 1491
1492 1492 mpt = TRAN2MPT(tran);
1493 1493 if (!mpt) {
1494 1494 return (DDI_SUCCESS);
1495 1495 }
1496 1496
1497 1497 mutex_enter(&mpt->m_mutex);
1498 1498
1499 1499 if (mpt->m_suspended++) {
1500 1500 mutex_exit(&mpt->m_mutex);
1501 1501 return (DDI_SUCCESS);
1502 1502 }
1503 1503
1504 1504 /*
1505 1505 * Cancel timeout threads for this mpt
1506 1506 */
1507 1507 if (mpt->m_quiesce_timeid) {
1508 1508 timeout_id_t tid = mpt->m_quiesce_timeid;
1509 1509 mpt->m_quiesce_timeid = 0;
1510 1510 mutex_exit(&mpt->m_mutex);
1511 1511 (void) untimeout(tid);
1512 1512 mutex_enter(&mpt->m_mutex);
1513 1513 }
1514 1514
1515 1515 if (mpt->m_restart_cmd_timeid) {
1516 1516 timeout_id_t tid = mpt->m_restart_cmd_timeid;
1517 1517 mpt->m_restart_cmd_timeid = 0;
1518 1518 mutex_exit(&mpt->m_mutex);
1519 1519 (void) untimeout(tid);
1520 1520 mutex_enter(&mpt->m_mutex);
1521 1521 }
1522 1522
1523 1523 mutex_exit(&mpt->m_mutex);
1524 1524
1525 1525 (void) pm_idle_component(mpt->m_dip, 0);
1526 1526
1527 1527 /*
1528 1528 * Cancel watch threads if all mpts suspended
1529 1529 */
1530 1530 rw_enter(&mptsas_global_rwlock, RW_WRITER);
1531 1531 for (g = mptsas_head; g != NULL; g = g->m_next) {
1532 1532 if (!g->m_suspended)
1533 1533 break;
1534 1534 }
1535 1535 rw_exit(&mptsas_global_rwlock);
1536 1536
1537 1537 mutex_enter(&mptsas_global_mutex);
1538 1538 if (g == NULL) {
1539 1539 timeout_id_t tid;
1540 1540
1541 1541 mptsas_timeouts_enabled = 0;
1542 1542 if (mptsas_timeout_id) {
1543 1543 tid = mptsas_timeout_id;
1544 1544 mptsas_timeout_id = 0;
1545 1545 mutex_exit(&mptsas_global_mutex);
1546 1546 (void) untimeout(tid);
1547 1547 mutex_enter(&mptsas_global_mutex);
1548 1548 }
1549 1549 if (mptsas_reset_watch) {
1550 1550 tid = mptsas_reset_watch;
1551 1551 mptsas_reset_watch = 0;
1552 1552 mutex_exit(&mptsas_global_mutex);
1553 1553 (void) untimeout(tid);
1554 1554 mutex_enter(&mptsas_global_mutex);
1555 1555 }
1556 1556 }
1557 1557 mutex_exit(&mptsas_global_mutex);
1558 1558
1559 1559 mutex_enter(&mpt->m_mutex);
1560 1560
1561 1561 /*
1562 1562 * If this mpt is not in full power(PM_LEVEL_D0), just return.
1563 1563 */
1564 1564 if ((mpt->m_options & MPTSAS_OPT_PM) &&
1565 1565 (mpt->m_power_level != PM_LEVEL_D0)) {
1566 1566 mutex_exit(&mpt->m_mutex);
1567 1567 return (DDI_SUCCESS);
1568 1568 }
1569 1569
1570 1570 /* Disable HBA interrupts in hardware */
1571 1571 MPTSAS_DISABLE_INTR(mpt);
1572 1572 /*
1573 1573 * Send RAID action system shutdown to sync IR
1574 1574 */
1575 1575 mptsas_raid_action_system_shutdown(mpt);
1576 1576
1577 1577 mutex_exit(&mpt->m_mutex);
1578 1578
1579 1579 /* drain the taskq */
1580 1580 ddi_taskq_wait(mpt->m_event_taskq);
1581 1581 ddi_taskq_wait(mpt->m_dr_taskq);
1582 1582
1583 1583 return (DDI_SUCCESS);
1584 1584 }
1585 1585
1586 1586 #ifdef __sparc
1587 1587 /*ARGSUSED*/
1588 1588 static int
1589 1589 mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd)
1590 1590 {
1591 1591 mptsas_t *mpt;
1592 1592 scsi_hba_tran_t *tran;
1593 1593
1594 1594 /*
1595 1595 * If this call is for iport, just return.
1596 1596 */
1597 1597 if (scsi_hba_iport_unit_address(devi))
1598 1598 return (DDI_SUCCESS);
1599 1599
1600 1600 if ((tran = ddi_get_driver_private(devi)) == NULL)
1601 1601 return (DDI_SUCCESS);
1602 1602
1603 1603 if ((mpt = TRAN2MPT(tran)) == NULL)
1604 1604 return (DDI_SUCCESS);
1605 1605
1606 1606 /*
1607 1607 * Send RAID action system shutdown to sync IR. Disable HBA
1608 1608 * interrupts in hardware first.
1609 1609 */
1610 1610 MPTSAS_DISABLE_INTR(mpt);
1611 1611 mptsas_raid_action_system_shutdown(mpt);
1612 1612
1613 1613 return (DDI_SUCCESS);
1614 1614 }
1615 1615 #else /* __sparc */
1616 1616 /*
1617 1617 * quiesce(9E) entry point.
1618 1618 *
1619 1619 * This function is called when the system is single-threaded at high
1620 1620 * PIL with preemption disabled. Therefore, this function must not be
1621 1621 * blocked.
1622 1622 *
1623 1623 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
1624 1624 * DDI_FAILURE indicates an error condition and should almost never happen.
1625 1625 */
1626 1626 static int
1627 1627 mptsas_quiesce(dev_info_t *devi)
1628 1628 {
1629 1629 mptsas_t *mpt;
1630 1630 scsi_hba_tran_t *tran;
1631 1631
1632 1632 /*
1633 1633 * If this call is for iport, just return.
1634 1634 */
1635 1635 if (scsi_hba_iport_unit_address(devi))
1636 1636 return (DDI_SUCCESS);
1637 1637
1638 1638 if ((tran = ddi_get_driver_private(devi)) == NULL)
1639 1639 return (DDI_SUCCESS);
1640 1640
1641 1641 if ((mpt = TRAN2MPT(tran)) == NULL)
1642 1642 return (DDI_SUCCESS);
1643 1643
1644 1644 /* Disable HBA interrupts in hardware */
1645 1645 MPTSAS_DISABLE_INTR(mpt);
1646 1646 /* Send RAID action system shutdonw to sync IR */
1647 1647 mptsas_raid_action_system_shutdown(mpt);
1648 1648
1649 1649 return (DDI_SUCCESS);
1650 1650 }
1651 1651 #endif /* __sparc */
1652 1652
1653 1653 /*
1654 1654 * detach(9E). Remove all device allocations and system resources;
1655 1655 * disable device interrupts.
1656 1656 * Return DDI_SUCCESS if done; DDI_FAILURE if there's a problem.
1657 1657 */
1658 1658 static int
1659 1659 mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd)
1660 1660 {
1661 1661 /* CONSTCOND */
1662 1662 ASSERT(NO_COMPETING_THREADS);
1663 1663 NDBG0(("mptsas_detach: dip=0x%p cmd=0x%p", (void *)devi, (void *)cmd));
1664 1664
1665 1665 switch (cmd) {
1666 1666 case DDI_DETACH:
1667 1667 return (mptsas_do_detach(devi));
1668 1668
1669 1669 case DDI_SUSPEND:
1670 1670 return (mptsas_suspend(devi));
1671 1671
1672 1672 default:
1673 1673 return (DDI_FAILURE);
1674 1674 }
1675 1675 /* NOTREACHED */
1676 1676 }
1677 1677
1678 1678 static int
1679 1679 mptsas_do_detach(dev_info_t *dip)
1680 1680 {
1681 1681 mptsas_t *mpt;
1682 1682 scsi_hba_tran_t *tran;
1683 1683 int circ = 0;
1684 1684 int circ1 = 0;
1685 1685 mdi_pathinfo_t *pip = NULL;
1686 1686 int i;
1687 1687 int doneq_thread_num = 0;
1688 1688
1689 1689 NDBG0(("mptsas_do_detach: dip=0x%p", (void *)dip));
1690 1690
1691 1691 if ((tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == NULL)
1692 1692 return (DDI_FAILURE);
1693 1693
1694 1694 mpt = TRAN2MPT(tran);
1695 1695 if (!mpt) {
1696 1696 return (DDI_FAILURE);
1697 1697 }
1698 1698 /*
1699 1699 * Still have pathinfo child, should not detach mpt driver
1700 1700 */
1701 1701 if (scsi_hba_iport_unit_address(dip)) {
1702 1702 if (mpt->m_mpxio_enable) {
1703 1703 /*
1704 1704 * MPxIO enabled for the iport
1705 1705 */
1706 1706 ndi_devi_enter(scsi_vhci_dip, &circ1);
1707 1707 ndi_devi_enter(dip, &circ);
1708 1708 while (pip = mdi_get_next_client_path(dip, NULL)) {
1709 1709 if (mdi_pi_free(pip, 0) == MDI_SUCCESS) {
1710 1710 continue;
1711 1711 }
1712 1712 ndi_devi_exit(dip, circ);
1713 1713 ndi_devi_exit(scsi_vhci_dip, circ1);
1714 1714 NDBG12(("detach failed because of "
1715 1715 "outstanding path info"));
1716 1716 return (DDI_FAILURE);
1717 1717 }
1718 1718 ndi_devi_exit(dip, circ);
1719 1719 ndi_devi_exit(scsi_vhci_dip, circ1);
1720 1720 (void) mdi_phci_unregister(dip, 0);
1721 1721 }
1722 1722
1723 1723 ddi_prop_remove_all(dip);
1724 1724
1725 1725 return (DDI_SUCCESS);
1726 1726 }
1727 1727
1728 1728 /* Make sure power level is D0 before accessing registers */
1729 1729 if (mpt->m_options & MPTSAS_OPT_PM) {
1730 1730 (void) pm_busy_component(dip, 0);
1731 1731 if (mpt->m_power_level != PM_LEVEL_D0) {
1732 1732 if (pm_raise_power(dip, 0, PM_LEVEL_D0) !=
1733 1733 DDI_SUCCESS) {
1734 1734 mptsas_log(mpt, CE_WARN,
1735 1735 "mptsas%d: Raise power request failed.",
1736 1736 mpt->m_instance);
1737 1737 (void) pm_idle_component(dip, 0);
1738 1738 return (DDI_FAILURE);
1739 1739 }
1740 1740 }
1741 1741 }
1742 1742
1743 1743 /*
1744 1744 * Send RAID action system shutdown to sync IR. After action, send a
1745 1745 * Message Unit Reset. Since after that DMA resource will be freed,
1746 1746 * set ioc to READY state will avoid HBA initiated DMA operation.
1747 1747 */
1748 1748 mutex_enter(&mpt->m_mutex);
1749 1749 MPTSAS_DISABLE_INTR(mpt);
1750 1750 mptsas_raid_action_system_shutdown(mpt);
1751 1751 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1752 1752 (void) mptsas_ioc_reset(mpt, FALSE);
1753 1753 mutex_exit(&mpt->m_mutex);
1754 1754 mptsas_rem_intrs(mpt);
1755 1755 ddi_taskq_destroy(mpt->m_event_taskq);
1756 1756 ddi_taskq_destroy(mpt->m_dr_taskq);
1757 1757
1758 1758 if (mpt->m_doneq_thread_n) {
1759 1759 mutex_enter(&mpt->m_doneq_mutex);
1760 1760 doneq_thread_num = mpt->m_doneq_thread_n;
1761 1761 for (i = 0; i < mpt->m_doneq_thread_n; i++) {
1762 1762 mutex_enter(&mpt->m_doneq_thread_id[i].mutex);
1763 1763 mpt->m_doneq_thread_id[i].flag &=
1764 1764 (~MPTSAS_DONEQ_THREAD_ACTIVE);
1765 1765 cv_signal(&mpt->m_doneq_thread_id[i].cv);
1766 1766 mutex_exit(&mpt->m_doneq_thread_id[i].mutex);
1767 1767 }
1768 1768 while (mpt->m_doneq_thread_n) {
1769 1769 cv_wait(&mpt->m_doneq_thread_cv,
1770 1770 &mpt->m_doneq_mutex);
1771 1771 }
1772 1772 for (i = 0; i < doneq_thread_num; i++) {
1773 1773 cv_destroy(&mpt->m_doneq_thread_id[i].cv);
1774 1774 mutex_destroy(&mpt->m_doneq_thread_id[i].mutex);
1775 1775 }
1776 1776 kmem_free(mpt->m_doneq_thread_id,
1777 1777 sizeof (mptsas_doneq_thread_list_t)
1778 1778 * doneq_thread_num);
1779 1779 mutex_exit(&mpt->m_doneq_mutex);
1780 1780 cv_destroy(&mpt->m_doneq_thread_cv);
1781 1781 mutex_destroy(&mpt->m_doneq_mutex);
1782 1782 }
1783 1783
1784 1784 scsi_hba_reset_notify_tear_down(mpt->m_reset_notify_listf);
1785 1785
1786 1786 mptsas_list_del(mpt);
1787 1787
1788 1788 /*
1789 1789 * Cancel timeout threads for this mpt
1790 1790 */
1791 1791 mutex_enter(&mpt->m_mutex);
1792 1792 if (mpt->m_quiesce_timeid) {
1793 1793 timeout_id_t tid = mpt->m_quiesce_timeid;
1794 1794 mpt->m_quiesce_timeid = 0;
1795 1795 mutex_exit(&mpt->m_mutex);
1796 1796 (void) untimeout(tid);
1797 1797 mutex_enter(&mpt->m_mutex);
1798 1798 }
1799 1799
1800 1800 if (mpt->m_restart_cmd_timeid) {
1801 1801 timeout_id_t tid = mpt->m_restart_cmd_timeid;
1802 1802 mpt->m_restart_cmd_timeid = 0;
1803 1803 mutex_exit(&mpt->m_mutex);
1804 1804 (void) untimeout(tid);
1805 1805 mutex_enter(&mpt->m_mutex);
1806 1806 }
1807 1807
1808 1808 mutex_exit(&mpt->m_mutex);
1809 1809
1810 1810 /*
1811 1811 * last mpt? ... if active, CANCEL watch threads.
1812 1812 */
1813 1813 mutex_enter(&mptsas_global_mutex);
1814 1814 if (mptsas_head == NULL) {
1815 1815 timeout_id_t tid;
1816 1816 /*
1817 1817 * Clear mptsas_timeouts_enable so that the watch thread
1818 1818 * gets restarted on DDI_ATTACH
1819 1819 */
1820 1820 mptsas_timeouts_enabled = 0;
1821 1821 if (mptsas_timeout_id) {
1822 1822 tid = mptsas_timeout_id;
1823 1823 mptsas_timeout_id = 0;
1824 1824 mutex_exit(&mptsas_global_mutex);
1825 1825 (void) untimeout(tid);
1826 1826 mutex_enter(&mptsas_global_mutex);
1827 1827 }
1828 1828 if (mptsas_reset_watch) {
1829 1829 tid = mptsas_reset_watch;
1830 1830 mptsas_reset_watch = 0;
1831 1831 mutex_exit(&mptsas_global_mutex);
1832 1832 (void) untimeout(tid);
1833 1833 mutex_enter(&mptsas_global_mutex);
1834 1834 }
1835 1835 }
1836 1836 mutex_exit(&mptsas_global_mutex);
1837 1837
1838 1838 /*
1839 1839 * Delete Phy stats
1840 1840 */
1841 1841 mptsas_destroy_phy_stats(mpt);
1842 1842
1843 1843 /*
1844 1844 * Delete nt_active.
1845 1845 */
1846 1846 mutex_enter(&mpt->m_mutex);
1847 1847 mptsas_hash_uninit(&mpt->m_active->m_tgttbl, sizeof (mptsas_target_t));
1848 1848 mptsas_hash_uninit(&mpt->m_active->m_smptbl, sizeof (mptsas_smp_t));
1849 1849 mptsas_free_active_slots(mpt);
1850 1850 mutex_exit(&mpt->m_mutex);
1851 1851
1852 1852 /* deallocate everything that was allocated in mptsas_attach */
1853 1853 mptsas_cache_destroy(mpt);
1854 1854
1855 1855 mptsas_hba_fini(mpt);
1856 1856 mptsas_cfg_fini(mpt);
1857 1857
1858 1858 /* Lower the power informing PM Framework */
1859 1859 if (mpt->m_options & MPTSAS_OPT_PM) {
1860 1860 if (pm_lower_power(dip, 0, PM_LEVEL_D3) != DDI_SUCCESS)
1861 1861 mptsas_log(mpt, CE_WARN,
1862 1862 "!mptsas%d: Lower power request failed "
1863 1863 "during detach, ignoring.",
1864 1864 mpt->m_instance);
1865 1865 }
1866 1866
1867 1867 mutex_destroy(&mpt->m_tx_waitq_mutex);
1868 1868 mutex_destroy(&mpt->m_passthru_mutex);
1869 1869 mutex_destroy(&mpt->m_mutex);
1870 1870 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1871 1871 mutex_destroy(&mpt->m_phy_info[i].smhba_info.phy_mutex);
1872 1872 }
1873 1873 cv_destroy(&mpt->m_cv);
1874 1874 cv_destroy(&mpt->m_passthru_cv);
1875 1875 cv_destroy(&mpt->m_fw_cv);
1876 1876 cv_destroy(&mpt->m_config_cv);
1877 1877 cv_destroy(&mpt->m_fw_diag_cv);
1878 1878
1879 1879
1880 1880 mptsas_smp_teardown(mpt);
1881 1881 mptsas_hba_teardown(mpt);
1882 1882
1883 1883 mptsas_config_space_fini(mpt);
1884 1884
1885 1885 mptsas_free_handshake_msg(mpt);
1886 1886
1887 1887 mptsas_fm_fini(mpt);
1888 1888 ddi_soft_state_free(mptsas_state, ddi_get_instance(dip));
1889 1889 ddi_prop_remove_all(dip);
1890 1890
1891 1891 return (DDI_SUCCESS);
1892 1892 }
1893 1893
1894 1894 static void
1895 1895 mptsas_list_add(mptsas_t *mpt)
1896 1896 {
1897 1897 rw_enter(&mptsas_global_rwlock, RW_WRITER);
1898 1898
1899 1899 if (mptsas_head == NULL) {
1900 1900 mptsas_head = mpt;
1901 1901 } else {
1902 1902 mptsas_tail->m_next = mpt;
1903 1903 }
1904 1904 mptsas_tail = mpt;
1905 1905 rw_exit(&mptsas_global_rwlock);
1906 1906 }
1907 1907
1908 1908 static void
1909 1909 mptsas_list_del(mptsas_t *mpt)
1910 1910 {
1911 1911 mptsas_t *m;
1912 1912 /*
1913 1913 * Remove device instance from the global linked list
1914 1914 */
1915 1915 rw_enter(&mptsas_global_rwlock, RW_WRITER);
1916 1916 if (mptsas_head == mpt) {
1917 1917 m = mptsas_head = mpt->m_next;
1918 1918 } else {
1919 1919 for (m = mptsas_head; m != NULL; m = m->m_next) {
1920 1920 if (m->m_next == mpt) {
1921 1921 m->m_next = mpt->m_next;
1922 1922 break;
1923 1923 }
1924 1924 }
1925 1925 if (m == NULL) {
1926 1926 mptsas_log(mpt, CE_PANIC, "Not in softc list!");
1927 1927 }
1928 1928 }
1929 1929
1930 1930 if (mptsas_tail == mpt) {
1931 1931 mptsas_tail = m;
1932 1932 }
1933 1933 rw_exit(&mptsas_global_rwlock);
1934 1934 }
1935 1935
1936 1936 static int
1937 1937 mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size)
1938 1938 {
1939 1939 ddi_dma_attr_t task_dma_attrs;
1940 1940
1941 1941 task_dma_attrs = mpt->m_msg_dma_attr;
1942 1942 task_dma_attrs.dma_attr_sgllen = 1;
1943 1943 task_dma_attrs.dma_attr_granular = (uint32_t)(alloc_size);
1944 1944
1945 1945 /* allocate Task Management ddi_dma resources */
1946 1946 if (mptsas_dma_addr_create(mpt, task_dma_attrs,
1947 1947 &mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl, &mpt->m_hshk_memp,
1948 1948 alloc_size, NULL) == FALSE) {
1949 1949 return (DDI_FAILURE);
1950 1950 }
1951 1951 mpt->m_hshk_dma_size = alloc_size;
1952 1952
1953 1953 return (DDI_SUCCESS);
1954 1954 }
1955 1955
1956 1956 static void
1957 1957 mptsas_free_handshake_msg(mptsas_t *mpt)
1958 1958 {
1959 1959 mptsas_dma_addr_destroy(&mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl);
1960 1960 mpt->m_hshk_dma_size = 0;
1961 1961 }
1962 1962
1963 1963 static int
1964 1964 mptsas_hba_setup(mptsas_t *mpt)
1965 1965 {
1966 1966 scsi_hba_tran_t *hba_tran;
1967 1967 int tran_flags;
1968 1968
1969 1969 /* Allocate a transport structure */
1970 1970 hba_tran = mpt->m_tran = scsi_hba_tran_alloc(mpt->m_dip,
1971 1971 SCSI_HBA_CANSLEEP);
1972 1972 ASSERT(mpt->m_tran != NULL);
1973 1973
1974 1974 hba_tran->tran_hba_private = mpt;
1975 1975 hba_tran->tran_tgt_private = NULL;
1976 1976
1977 1977 hba_tran->tran_tgt_init = mptsas_scsi_tgt_init;
1978 1978 hba_tran->tran_tgt_free = mptsas_scsi_tgt_free;
1979 1979
1980 1980 hba_tran->tran_start = mptsas_scsi_start;
1981 1981 hba_tran->tran_reset = mptsas_scsi_reset;
1982 1982 hba_tran->tran_abort = mptsas_scsi_abort;
1983 1983 hba_tran->tran_getcap = mptsas_scsi_getcap;
1984 1984 hba_tran->tran_setcap = mptsas_scsi_setcap;
1985 1985 hba_tran->tran_init_pkt = mptsas_scsi_init_pkt;
1986 1986 hba_tran->tran_destroy_pkt = mptsas_scsi_destroy_pkt;
1987 1987
1988 1988 hba_tran->tran_dmafree = mptsas_scsi_dmafree;
1989 1989 hba_tran->tran_sync_pkt = mptsas_scsi_sync_pkt;
1990 1990 hba_tran->tran_reset_notify = mptsas_scsi_reset_notify;
1991 1991
1992 1992 hba_tran->tran_get_bus_addr = mptsas_get_bus_addr;
1993 1993 hba_tran->tran_get_name = mptsas_get_name;
1994 1994
1995 1995 hba_tran->tran_quiesce = mptsas_scsi_quiesce;
1996 1996 hba_tran->tran_unquiesce = mptsas_scsi_unquiesce;
1997 1997 hba_tran->tran_bus_reset = NULL;
1998 1998
1999 1999 hba_tran->tran_add_eventcall = NULL;
2000 2000 hba_tran->tran_get_eventcookie = NULL;
2001 2001 hba_tran->tran_post_event = NULL;
2002 2002 hba_tran->tran_remove_eventcall = NULL;
2003 2003
2004 2004 hba_tran->tran_bus_config = mptsas_bus_config;
2005 2005
2006 2006 hba_tran->tran_interconnect_type = INTERCONNECT_SAS;
2007 2007
2008 2008 /*
2009 2009 * All children of the HBA are iports. We need tran was cloned.
2010 2010 * So we pass the flags to SCSA. SCSI_HBA_TRAN_CLONE will be
2011 2011 * inherited to iport's tran vector.
2012 2012 */
2013 2013 tran_flags = (SCSI_HBA_HBA | SCSI_HBA_TRAN_CLONE);
2014 2014
2015 2015 if (scsi_hba_attach_setup(mpt->m_dip, &mpt->m_msg_dma_attr,
2016 2016 hba_tran, tran_flags) != DDI_SUCCESS) {
2017 2017 mptsas_log(mpt, CE_WARN, "hba attach setup failed");
2018 2018 scsi_hba_tran_free(hba_tran);
2019 2019 mpt->m_tran = NULL;
2020 2020 return (FALSE);
2021 2021 }
2022 2022 return (TRUE);
2023 2023 }
2024 2024
2025 2025 static void
2026 2026 mptsas_hba_teardown(mptsas_t *mpt)
2027 2027 {
2028 2028 (void) scsi_hba_detach(mpt->m_dip);
2029 2029 if (mpt->m_tran != NULL) {
2030 2030 scsi_hba_tran_free(mpt->m_tran);
2031 2031 mpt->m_tran = NULL;
2032 2032 }
2033 2033 }
2034 2034
2035 2035 static void
2036 2036 mptsas_iport_register(mptsas_t *mpt)
2037 2037 {
2038 2038 int i, j;
2039 2039 mptsas_phymask_t mask = 0x0;
2040 2040 /*
2041 2041 * initial value of mask is 0
2042 2042 */
2043 2043 mutex_enter(&mpt->m_mutex);
2044 2044 for (i = 0; i < mpt->m_num_phys; i++) {
2045 2045 mptsas_phymask_t phy_mask = 0x0;
2046 2046 char phy_mask_name[MPTSAS_MAX_PHYS];
2047 2047 uint8_t current_port;
2048 2048
2049 2049 if (mpt->m_phy_info[i].attached_devhdl == 0)
2050 2050 continue;
2051 2051
2052 2052 bzero(phy_mask_name, sizeof (phy_mask_name));
2053 2053
2054 2054 current_port = mpt->m_phy_info[i].port_num;
2055 2055
2056 2056 if ((mask & (1 << i)) != 0)
2057 2057 continue;
2058 2058
2059 2059 for (j = 0; j < mpt->m_num_phys; j++) {
2060 2060 if (mpt->m_phy_info[j].attached_devhdl &&
2061 2061 (mpt->m_phy_info[j].port_num == current_port)) {
2062 2062 phy_mask |= (1 << j);
2063 2063 }
2064 2064 }
2065 2065 mask = mask | phy_mask;
2066 2066
2067 2067 for (j = 0; j < mpt->m_num_phys; j++) {
2068 2068 if ((phy_mask >> j) & 0x01) {
2069 2069 mpt->m_phy_info[j].phy_mask = phy_mask;
2070 2070 }
2071 2071 }
2072 2072
2073 2073 (void) sprintf(phy_mask_name, "%x", phy_mask);
2074 2074
2075 2075 mutex_exit(&mpt->m_mutex);
2076 2076 /*
2077 2077 * register a iport
2078 2078 */
2079 2079 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name);
2080 2080 mutex_enter(&mpt->m_mutex);
2081 2081 }
2082 2082 mutex_exit(&mpt->m_mutex);
2083 2083 /*
2084 2084 * register a virtual port for RAID volume always
2085 2085 */
2086 2086 (void) scsi_hba_iport_register(mpt->m_dip, "v0");
2087 2087
2088 2088 }
2089 2089
2090 2090 static int
2091 2091 mptsas_smp_setup(mptsas_t *mpt)
2092 2092 {
2093 2093 mpt->m_smptran = smp_hba_tran_alloc(mpt->m_dip);
2094 2094 ASSERT(mpt->m_smptran != NULL);
2095 2095 mpt->m_smptran->smp_tran_hba_private = mpt;
2096 2096 mpt->m_smptran->smp_tran_start = mptsas_smp_start;
2097 2097 if (smp_hba_attach_setup(mpt->m_dip, mpt->m_smptran) != DDI_SUCCESS) {
2098 2098 mptsas_log(mpt, CE_WARN, "smp attach setup failed");
2099 2099 smp_hba_tran_free(mpt->m_smptran);
2100 2100 mpt->m_smptran = NULL;
2101 2101 return (FALSE);
2102 2102 }
2103 2103 /*
2104 2104 * Initialize smp hash table
2105 2105 */
2106 2106 mptsas_hash_init(&mpt->m_active->m_smptbl);
2107 2107 mpt->m_smp_devhdl = 0xFFFF;
2108 2108
2109 2109 return (TRUE);
2110 2110 }
2111 2111
2112 2112 static void
2113 2113 mptsas_smp_teardown(mptsas_t *mpt)
2114 2114 {
2115 2115 (void) smp_hba_detach(mpt->m_dip);
2116 2116 if (mpt->m_smptran != NULL) {
2117 2117 smp_hba_tran_free(mpt->m_smptran);
2118 2118 mpt->m_smptran = NULL;
2119 2119 }
2120 2120 mpt->m_smp_devhdl = 0;
2121 2121 }
2122 2122
2123 2123 static int
2124 2124 mptsas_cache_create(mptsas_t *mpt)
2125 2125 {
2126 2126 int instance = mpt->m_instance;
2127 2127 char buf[64];
2128 2128
2129 2129 /*
2130 2130 * create kmem cache for packets
2131 2131 */
2132 2132 (void) sprintf(buf, "mptsas%d_cache", instance);
2133 2133 mpt->m_kmem_cache = kmem_cache_create(buf,
2134 2134 sizeof (struct mptsas_cmd) + scsi_pkt_size(), 8,
2135 2135 mptsas_kmem_cache_constructor, mptsas_kmem_cache_destructor,
2136 2136 NULL, (void *)mpt, NULL, 0);
2137 2137
2138 2138 if (mpt->m_kmem_cache == NULL) {
2139 2139 mptsas_log(mpt, CE_WARN, "creating kmem cache failed");
2140 2140 return (FALSE);
2141 2141 }
2142 2142
2143 2143 /*
2144 2144 * create kmem cache for extra SGL frames if SGL cannot
2145 2145 * be accomodated into main request frame.
2146 2146 */
2147 2147 (void) sprintf(buf, "mptsas%d_cache_frames", instance);
2148 2148 mpt->m_cache_frames = kmem_cache_create(buf,
2149 2149 sizeof (mptsas_cache_frames_t), 8,
2150 2150 mptsas_cache_frames_constructor, mptsas_cache_frames_destructor,
2151 2151 NULL, (void *)mpt, NULL, 0);
2152 2152
2153 2153 if (mpt->m_cache_frames == NULL) {
2154 2154 mptsas_log(mpt, CE_WARN, "creating cache for frames failed");
2155 2155 return (FALSE);
2156 2156 }
2157 2157
2158 2158 return (TRUE);
2159 2159 }
2160 2160
2161 2161 static void
2162 2162 mptsas_cache_destroy(mptsas_t *mpt)
2163 2163 {
2164 2164 /* deallocate in reverse order */
2165 2165 if (mpt->m_cache_frames) {
2166 2166 kmem_cache_destroy(mpt->m_cache_frames);
2167 2167 mpt->m_cache_frames = NULL;
2168 2168 }
2169 2169 if (mpt->m_kmem_cache) {
2170 2170 kmem_cache_destroy(mpt->m_kmem_cache);
2171 2171 mpt->m_kmem_cache = NULL;
2172 2172 }
2173 2173 }
2174 2174
2175 2175 static int
2176 2176 mptsas_power(dev_info_t *dip, int component, int level)
2177 2177 {
2178 2178 #ifndef __lock_lint
2179 2179 _NOTE(ARGUNUSED(component))
2180 2180 #endif
2181 2181 mptsas_t *mpt;
2182 2182 int rval = DDI_SUCCESS;
2183 2183 int polls = 0;
2184 2184 uint32_t ioc_status;
2185 2185
2186 2186 if (scsi_hba_iport_unit_address(dip) != 0)
2187 2187 return (DDI_SUCCESS);
2188 2188
2189 2189 mpt = ddi_get_soft_state(mptsas_state, ddi_get_instance(dip));
2190 2190 if (mpt == NULL) {
2191 2191 return (DDI_FAILURE);
2192 2192 }
2193 2193
2194 2194 mutex_enter(&mpt->m_mutex);
2195 2195
2196 2196 /*
2197 2197 * If the device is busy, don't lower its power level
2198 2198 */
2199 2199 if (mpt->m_busy && (mpt->m_power_level > level)) {
2200 2200 mutex_exit(&mpt->m_mutex);
2201 2201 return (DDI_FAILURE);
2202 2202 }
2203 2203 switch (level) {
2204 2204 case PM_LEVEL_D0:
2205 2205 NDBG11(("mptsas%d: turning power ON.", mpt->m_instance));
2206 2206 MPTSAS_POWER_ON(mpt);
2207 2207 /*
2208 2208 * Wait up to 30 seconds for IOC to come out of reset.
2209 2209 */
2210 2210 while (((ioc_status = ddi_get32(mpt->m_datap,
2211 2211 &mpt->m_reg->Doorbell)) &
2212 2212 MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
2213 2213 if (polls++ > 3000) {
2214 2214 break;
2215 2215 }
2216 2216 delay(drv_usectohz(10000));
2217 2217 }
2218 2218 /*
2219 2219 * If IOC is not in operational state, try to hard reset it.
2220 2220 */
2221 2221 if ((ioc_status & MPI2_IOC_STATE_MASK) !=
2222 2222 MPI2_IOC_STATE_OPERATIONAL) {
2223 2223 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
2224 2224 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) {
2225 2225 mptsas_log(mpt, CE_WARN,
2226 2226 "mptsas_power: hard reset failed");
2227 2227 mutex_exit(&mpt->m_mutex);
2228 2228 return (DDI_FAILURE);
2229 2229 }
2230 2230 }
2231 2231 mpt->m_power_level = PM_LEVEL_D0;
2232 2232 break;
2233 2233 case PM_LEVEL_D3:
2234 2234 NDBG11(("mptsas%d: turning power OFF.", mpt->m_instance));
2235 2235 MPTSAS_POWER_OFF(mpt);
2236 2236 break;
2237 2237 default:
2238 2238 mptsas_log(mpt, CE_WARN, "mptsas%d: unknown power level <%x>.",
2239 2239 mpt->m_instance, level);
2240 2240 rval = DDI_FAILURE;
2241 2241 break;
2242 2242 }
2243 2243 mutex_exit(&mpt->m_mutex);
2244 2244 return (rval);
2245 2245 }
2246 2246
2247 2247 /*
2248 2248 * Initialize configuration space and figure out which
2249 2249 * chip and revison of the chip the mpt driver is using.
2250 2250 */
2251 2251 static int
2252 2252 mptsas_config_space_init(mptsas_t *mpt)
2253 2253 {
2254 2254 NDBG0(("mptsas_config_space_init"));
2255 2255
2256 2256 if (mpt->m_config_handle != NULL)
2257 2257 return (TRUE);
2258 2258
2259 2259 if (pci_config_setup(mpt->m_dip,
2260 2260 &mpt->m_config_handle) != DDI_SUCCESS) {
2261 2261 mptsas_log(mpt, CE_WARN, "cannot map configuration space.");
2262 2262 return (FALSE);
2263 2263 }
2264 2264
2265 2265 /*
2266 2266 * This is a workaround for a XMITS ASIC bug which does not
2267 2267 * drive the CBE upper bits.
2268 2268 */
2269 2269 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) &
2270 2270 PCI_STAT_PERROR) {
2271 2271 pci_config_put16(mpt->m_config_handle, PCI_CONF_STAT,
2272 2272 PCI_STAT_PERROR);
2273 2273 }
2274 2274
2275 2275 mptsas_setup_cmd_reg(mpt);
2276 2276
2277 2277 /*
2278 2278 * Get the chip device id:
2279 2279 */
2280 2280 mpt->m_devid = pci_config_get16(mpt->m_config_handle, PCI_CONF_DEVID);
2281 2281
2282 2282 /*
2283 2283 * Save the revision.
2284 2284 */
2285 2285 mpt->m_revid = pci_config_get8(mpt->m_config_handle, PCI_CONF_REVID);
2286 2286
2287 2287 /*
2288 2288 * Save the SubSystem Vendor and Device IDs
2289 2289 */
2290 2290 mpt->m_svid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBVENID);
2291 2291 mpt->m_ssid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBSYSID);
2292 2292
2293 2293 /*
2294 2294 * Set the latency timer to 0x40 as specified by the upa -> pci
2295 2295 * bridge chip design team. This may be done by the sparc pci
2296 2296 * bus nexus driver, but the driver should make sure the latency
2297 2297 * timer is correct for performance reasons.
2298 2298 */
2299 2299 pci_config_put8(mpt->m_config_handle, PCI_CONF_LATENCY_TIMER,
2300 2300 MPTSAS_LATENCY_TIMER);
2301 2301
2302 2302 (void) mptsas_get_pci_cap(mpt);
2303 2303 return (TRUE);
2304 2304 }
2305 2305
2306 2306 static void
2307 2307 mptsas_config_space_fini(mptsas_t *mpt)
2308 2308 {
2309 2309 if (mpt->m_config_handle != NULL) {
2310 2310 mptsas_disable_bus_master(mpt);
2311 2311 pci_config_teardown(&mpt->m_config_handle);
2312 2312 mpt->m_config_handle = NULL;
2313 2313 }
2314 2314 }
2315 2315
2316 2316 static void
2317 2317 mptsas_setup_cmd_reg(mptsas_t *mpt)
2318 2318 {
2319 2319 ushort_t cmdreg;
2320 2320
2321 2321 /*
2322 2322 * Set the command register to the needed values.
2323 2323 */
2324 2324 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM);
2325 2325 cmdreg |= (PCI_COMM_ME | PCI_COMM_SERR_ENABLE |
2326 2326 PCI_COMM_PARITY_DETECT | PCI_COMM_MAE);
2327 2327 cmdreg &= ~PCI_COMM_IO;
2328 2328 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg);
2329 2329 }
2330 2330
2331 2331 static void
2332 2332 mptsas_disable_bus_master(mptsas_t *mpt)
2333 2333 {
2334 2334 ushort_t cmdreg;
2335 2335
2336 2336 /*
2337 2337 * Clear the master enable bit in the PCI command register.
2338 2338 * This prevents any bus mastering activity like DMA.
2339 2339 */
2340 2340 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM);
2341 2341 cmdreg &= ~PCI_COMM_ME;
2342 2342 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg);
2343 2343 }
2344 2344
2345 2345 int
2346 2346 mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep)
2347 2347 {
2348 2348 ddi_dma_attr_t attrs;
2349 2349
2350 2350 attrs = mpt->m_io_dma_attr;
2351 2351 attrs.dma_attr_sgllen = 1;
2352 2352
2353 2353 ASSERT(dma_statep != NULL);
2354 2354
2355 2355 if (mptsas_dma_addr_create(mpt, attrs, &dma_statep->handle,
2356 2356 &dma_statep->accessp, &dma_statep->memp, dma_statep->size,
2357 2357 &dma_statep->cookie) == FALSE) {
2358 2358 return (DDI_FAILURE);
2359 2359 }
2360 2360
2361 2361 return (DDI_SUCCESS);
2362 2362 }
2363 2363
2364 2364 void
2365 2365 mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep)
2366 2366 {
2367 2367 ASSERT(dma_statep != NULL);
2368 2368 mptsas_dma_addr_destroy(&dma_statep->handle, &dma_statep->accessp);
2369 2369 dma_statep->size = 0;
2370 2370 }
2371 2371
2372 2372 int
2373 2373 mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)())
2374 2374 {
2375 2375 ddi_dma_attr_t attrs;
2376 2376 ddi_dma_handle_t dma_handle;
2377 2377 caddr_t memp;
2378 2378 ddi_acc_handle_t accessp;
2379 2379 int rval;
2380 2380
2381 2381 ASSERT(mutex_owned(&mpt->m_mutex));
2382 2382
2383 2383 attrs = mpt->m_msg_dma_attr;
2384 2384 attrs.dma_attr_sgllen = 1;
2385 2385 attrs.dma_attr_granular = size;
2386 2386
2387 2387 if (mptsas_dma_addr_create(mpt, attrs, &dma_handle,
2388 2388 &accessp, &memp, size, NULL) == FALSE) {
2389 2389 return (DDI_FAILURE);
2390 2390 }
2391 2391
2392 2392 rval = (*callback) (mpt, memp, var, accessp);
2393 2393
2394 2394 if ((mptsas_check_dma_handle(dma_handle) != DDI_SUCCESS) ||
2395 2395 (mptsas_check_acc_handle(accessp) != DDI_SUCCESS)) {
2396 2396 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
2397 2397 rval = DDI_FAILURE;
2398 2398 }
2399 2399
2400 2400 mptsas_dma_addr_destroy(&dma_handle, &accessp);
2401 2401 return (rval);
2402 2402
2403 2403 }
2404 2404
2405 2405 static int
2406 2406 mptsas_alloc_request_frames(mptsas_t *mpt)
2407 2407 {
2408 2408 ddi_dma_attr_t frame_dma_attrs;
2409 2409 caddr_t memp;
2410 2410 ddi_dma_cookie_t cookie;
2411 2411 size_t mem_size;
2412 2412
2413 2413 /*
2414 2414 * re-alloc when it has already alloced
2415 2415 */
2416 2416 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl,
2417 2417 &mpt->m_acc_req_frame_hdl);
2418 2418
2419 2419 /*
2420 2420 * The size of the request frame pool is:
2421 2421 * Number of Request Frames * Request Frame Size
2422 2422 */
2423 2423 mem_size = mpt->m_max_requests * mpt->m_req_frame_size;
2424 2424
2425 2425 /*
2426 2426 * set the DMA attributes. System Request Message Frames must be
2427 2427 * aligned on a 16-byte boundry.
2428 2428 */
2429 2429 frame_dma_attrs = mpt->m_msg_dma_attr;
2430 2430 frame_dma_attrs.dma_attr_align = 16;
2431 2431 frame_dma_attrs.dma_attr_sgllen = 1;
2432 2432
2433 2433 /*
2434 2434 * allocate the request frame pool.
2435 2435 */
2436 2436 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2437 2437 &mpt->m_dma_req_frame_hdl, &mpt->m_acc_req_frame_hdl, &memp,
2438 2438 mem_size, &cookie) == FALSE) {
2439 2439 return (DDI_FAILURE);
2440 2440 }
2441 2441
2442 2442 /*
2443 2443 * Store the request frame memory address. This chip uses this
2444 2444 * address to dma to and from the driver's frame. The second
2445 2445 * address is the address mpt uses to fill in the frame.
2446 2446 */
2447 2447 mpt->m_req_frame_dma_addr = cookie.dmac_laddress;
2448 2448 mpt->m_req_frame = memp;
2449 2449
2450 2450 /*
2451 2451 * Clear the request frame pool.
2452 2452 */
2453 2453 bzero(mpt->m_req_frame, mem_size);
2454 2454
2455 2455 return (DDI_SUCCESS);
2456 2456 }
2457 2457
2458 2458 static int
2459 2459 mptsas_alloc_reply_frames(mptsas_t *mpt)
2460 2460 {
2461 2461 ddi_dma_attr_t frame_dma_attrs;
2462 2462 caddr_t memp;
2463 2463 ddi_dma_cookie_t cookie;
2464 2464 size_t mem_size;
2465 2465
2466 2466 /*
2467 2467 * re-alloc when it has already alloced
2468 2468 */
2469 2469 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl,
2470 2470 &mpt->m_acc_reply_frame_hdl);
2471 2471
2472 2472 /*
2473 2473 * The size of the reply frame pool is:
2474 2474 * Number of Reply Frames * Reply Frame Size
2475 2475 */
2476 2476 mem_size = mpt->m_max_replies * mpt->m_reply_frame_size;
2477 2477
2478 2478 /*
2479 2479 * set the DMA attributes. System Reply Message Frames must be
2480 2480 * aligned on a 4-byte boundry. This is the default.
2481 2481 */
2482 2482 frame_dma_attrs = mpt->m_msg_dma_attr;
2483 2483 frame_dma_attrs.dma_attr_sgllen = 1;
2484 2484
2485 2485 /*
2486 2486 * allocate the reply frame pool
2487 2487 */
2488 2488 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2489 2489 &mpt->m_dma_reply_frame_hdl, &mpt->m_acc_reply_frame_hdl, &memp,
2490 2490 mem_size, &cookie) == FALSE) {
2491 2491 return (DDI_FAILURE);
2492 2492 }
2493 2493
2494 2494 /*
2495 2495 * Store the reply frame memory address. This chip uses this
2496 2496 * address to dma to and from the driver's frame. The second
2497 2497 * address is the address mpt uses to process the frame.
2498 2498 */
2499 2499 mpt->m_reply_frame_dma_addr = cookie.dmac_laddress;
2500 2500 mpt->m_reply_frame = memp;
2501 2501
2502 2502 /*
2503 2503 * Clear the reply frame pool.
2504 2504 */
2505 2505 bzero(mpt->m_reply_frame, mem_size);
2506 2506
2507 2507 return (DDI_SUCCESS);
2508 2508 }
2509 2509
2510 2510 static int
2511 2511 mptsas_alloc_free_queue(mptsas_t *mpt)
2512 2512 {
2513 2513 ddi_dma_attr_t frame_dma_attrs;
2514 2514 caddr_t memp;
2515 2515 ddi_dma_cookie_t cookie;
2516 2516 size_t mem_size;
2517 2517
2518 2518 /*
2519 2519 * re-alloc when it has already alloced
2520 2520 */
2521 2521 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl,
2522 2522 &mpt->m_acc_free_queue_hdl);
2523 2523
2524 2524 /*
2525 2525 * The reply free queue size is:
2526 2526 * Reply Free Queue Depth * 4
2527 2527 * The "4" is the size of one 32 bit address (low part of 64-bit
2528 2528 * address)
2529 2529 */
2530 2530 mem_size = mpt->m_free_queue_depth * 4;
2531 2531
2532 2532 /*
2533 2533 * set the DMA attributes The Reply Free Queue must be aligned on a
2534 2534 * 16-byte boundry.
2535 2535 */
2536 2536 frame_dma_attrs = mpt->m_msg_dma_attr;
2537 2537 frame_dma_attrs.dma_attr_align = 16;
2538 2538 frame_dma_attrs.dma_attr_sgllen = 1;
2539 2539
2540 2540 /*
2541 2541 * allocate the reply free queue
2542 2542 */
2543 2543 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2544 2544 &mpt->m_dma_free_queue_hdl, &mpt->m_acc_free_queue_hdl, &memp,
2545 2545 mem_size, &cookie) == FALSE) {
2546 2546 return (DDI_FAILURE);
2547 2547 }
2548 2548
2549 2549 /*
2550 2550 * Store the reply free queue memory address. This chip uses this
2551 2551 * address to read from the reply free queue. The second address
2552 2552 * is the address mpt uses to manage the queue.
2553 2553 */
2554 2554 mpt->m_free_queue_dma_addr = cookie.dmac_laddress;
2555 2555 mpt->m_free_queue = memp;
2556 2556
2557 2557 /*
2558 2558 * Clear the reply free queue memory.
2559 2559 */
2560 2560 bzero(mpt->m_free_queue, mem_size);
2561 2561
2562 2562 return (DDI_SUCCESS);
2563 2563 }
2564 2564
2565 2565 static int
2566 2566 mptsas_alloc_post_queue(mptsas_t *mpt)
2567 2567 {
2568 2568 ddi_dma_attr_t frame_dma_attrs;
2569 2569 caddr_t memp;
2570 2570 ddi_dma_cookie_t cookie;
2571 2571 size_t mem_size;
2572 2572
2573 2573 /*
2574 2574 * re-alloc when it has already alloced
2575 2575 */
2576 2576 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl,
2577 2577 &mpt->m_acc_post_queue_hdl);
2578 2578
2579 2579 /*
2580 2580 * The reply descriptor post queue size is:
2581 2581 * Reply Descriptor Post Queue Depth * 8
2582 2582 * The "8" is the size of each descriptor (8 bytes or 64 bits).
2583 2583 */
2584 2584 mem_size = mpt->m_post_queue_depth * 8;
2585 2585
2586 2586 /*
2587 2587 * set the DMA attributes. The Reply Descriptor Post Queue must be
2588 2588 * aligned on a 16-byte boundry.
2589 2589 */
2590 2590 frame_dma_attrs = mpt->m_msg_dma_attr;
2591 2591 frame_dma_attrs.dma_attr_align = 16;
2592 2592 frame_dma_attrs.dma_attr_sgllen = 1;
2593 2593
2594 2594 /*
2595 2595 * allocate the reply post queue
2596 2596 */
2597 2597 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2598 2598 &mpt->m_dma_post_queue_hdl, &mpt->m_acc_post_queue_hdl, &memp,
2599 2599 mem_size, &cookie) == FALSE) {
2600 2600 return (DDI_FAILURE);
2601 2601 }
2602 2602
2603 2603 /*
2604 2604 * Store the reply descriptor post queue memory address. This chip
2605 2605 * uses this address to write to the reply descriptor post queue. The
2606 2606 * second address is the address mpt uses to manage the queue.
2607 2607 */
2608 2608 mpt->m_post_queue_dma_addr = cookie.dmac_laddress;
2609 2609 mpt->m_post_queue = memp;
2610 2610
2611 2611 /*
2612 2612 * Clear the reply post queue memory.
2613 2613 */
2614 2614 bzero(mpt->m_post_queue, mem_size);
2615 2615
2616 2616 return (DDI_SUCCESS);
2617 2617 }
2618 2618
2619 2619 static void
2620 2620 mptsas_alloc_reply_args(mptsas_t *mpt)
2621 2621 {
2622 2622 if (mpt->m_replyh_args == NULL) {
2623 2623 mpt->m_replyh_args = kmem_zalloc(sizeof (m_replyh_arg_t) *
2624 2624 mpt->m_max_replies, KM_SLEEP);
2625 2625 }
2626 2626 }
2627 2627
2628 2628 static int
2629 2629 mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd)
2630 2630 {
2631 2631 mptsas_cache_frames_t *frames = NULL;
2632 2632 if (cmd->cmd_extra_frames == NULL) {
2633 2633 frames = kmem_cache_alloc(mpt->m_cache_frames, KM_NOSLEEP);
2634 2634 if (frames == NULL) {
2635 2635 return (DDI_FAILURE);
2636 2636 }
2637 2637 cmd->cmd_extra_frames = frames;
2638 2638 }
2639 2639 return (DDI_SUCCESS);
2640 2640 }
2641 2641
2642 2642 static void
2643 2643 mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd)
2644 2644 {
2645 2645 if (cmd->cmd_extra_frames) {
2646 2646 kmem_cache_free(mpt->m_cache_frames,
2647 2647 (void *)cmd->cmd_extra_frames);
2648 2648 cmd->cmd_extra_frames = NULL;
2649 2649 }
2650 2650 }
2651 2651
2652 2652 static void
2653 2653 mptsas_cfg_fini(mptsas_t *mpt)
2654 2654 {
2655 2655 NDBG0(("mptsas_cfg_fini"));
2656 2656 ddi_regs_map_free(&mpt->m_datap);
2657 2657 }
2658 2658
2659 2659 static void
2660 2660 mptsas_hba_fini(mptsas_t *mpt)
2661 2661 {
2662 2662 NDBG0(("mptsas_hba_fini"));
2663 2663
2664 2664 /*
2665 2665 * Free up any allocated memory
2666 2666 */
2667 2667 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl,
2668 2668 &mpt->m_acc_req_frame_hdl);
2669 2669
2670 2670 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl,
2671 2671 &mpt->m_acc_reply_frame_hdl);
2672 2672
2673 2673 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl,
2674 2674 &mpt->m_acc_free_queue_hdl);
2675 2675
2676 2676 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl,
2677 2677 &mpt->m_acc_post_queue_hdl);
2678 2678
2679 2679 if (mpt->m_replyh_args != NULL) {
2680 2680 kmem_free(mpt->m_replyh_args, sizeof (m_replyh_arg_t)
2681 2681 * mpt->m_max_replies);
2682 2682 }
2683 2683 }
2684 2684
2685 2685 static int
2686 2686 mptsas_name_child(dev_info_t *lun_dip, char *name, int len)
2687 2687 {
2688 2688 int lun = 0;
2689 2689 char *sas_wwn = NULL;
2690 2690 int phynum = -1;
2691 2691 int reallen = 0;
2692 2692
2693 2693 /* Get the target num */
2694 2694 lun = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, DDI_PROP_DONTPASS,
2695 2695 LUN_PROP, 0);
2696 2696
2697 2697 if ((phynum = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip,
2698 2698 DDI_PROP_DONTPASS, "sata-phy", -1)) != -1) {
2699 2699 /*
2700 2700 * Stick in the address of form "pPHY,LUN"
2701 2701 */
2702 2702 reallen = snprintf(name, len, "p%x,%x", phynum, lun);
2703 2703 } else if (ddi_prop_lookup_string(DDI_DEV_T_ANY, lun_dip,
2704 2704 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &sas_wwn)
2705 2705 == DDI_PROP_SUCCESS) {
2706 2706 /*
2707 2707 * Stick in the address of the form "wWWN,LUN"
2708 2708 */
2709 2709 reallen = snprintf(name, len, "%s,%x", sas_wwn, lun);
2710 2710 ddi_prop_free(sas_wwn);
2711 2711 } else {
2712 2712 return (DDI_FAILURE);
2713 2713 }
2714 2714
2715 2715 ASSERT(reallen < len);
2716 2716 if (reallen >= len) {
2717 2717 mptsas_log(0, CE_WARN, "!mptsas_get_name: name parameter "
2718 2718 "length too small, it needs to be %d bytes", reallen + 1);
2719 2719 }
2720 2720 return (DDI_SUCCESS);
2721 2721 }
2722 2722
2723 2723 /*
2724 2724 * tran_tgt_init(9E) - target device instance initialization
2725 2725 */
2726 2726 static int
2727 2727 mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
2728 2728 scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
2729 2729 {
2730 2730 #ifndef __lock_lint
2731 2731 _NOTE(ARGUNUSED(hba_tran))
2732 2732 #endif
2733 2733
2734 2734 /*
2735 2735 * At this point, the scsi_device structure already exists
2736 2736 * and has been initialized.
2737 2737 *
2738 2738 * Use this function to allocate target-private data structures,
2739 2739 * if needed by this HBA. Add revised flow-control and queue
2740 2740 * properties for child here, if desired and if you can tell they
2741 2741 * support tagged queueing by now.
2742 2742 */
2743 2743 mptsas_t *mpt;
2744 2744 int lun = sd->sd_address.a_lun;
2745 2745 mdi_pathinfo_t *pip = NULL;
2746 2746 mptsas_tgt_private_t *tgt_private = NULL;
2747 2747 mptsas_target_t *ptgt = NULL;
2748 2748 char *psas_wwn = NULL;
2749 2749 int phymask = 0;
2750 2750 uint64_t sas_wwn = 0;
2751 2751 mpt = SDEV2MPT(sd);
2752 2752
2753 2753 ASSERT(scsi_hba_iport_unit_address(hba_dip) != 0);
2754 2754
2755 2755 NDBG0(("mptsas_scsi_tgt_init: hbadip=0x%p tgtdip=0x%p lun=%d",
2756 2756 (void *)hba_dip, (void *)tgt_dip, lun));
2757 2757
2758 2758 if (ndi_dev_is_persistent_node(tgt_dip) == 0) {
2759 2759 (void) ndi_merge_node(tgt_dip, mptsas_name_child);
2760 2760 ddi_set_name_addr(tgt_dip, NULL);
2761 2761 return (DDI_FAILURE);
2762 2762 }
2763 2763 /*
2764 2764 * phymask is 0 means the virtual port for RAID
2765 2765 */
2766 2766 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, hba_dip, 0,
2767 2767 "phymask", 0);
2768 2768 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) {
2769 2769 if ((pip = (void *)(sd->sd_private)) == NULL) {
2770 2770 /*
2771 2771 * Very bad news if this occurs. Somehow scsi_vhci has
2772 2772 * lost the pathinfo node for this target.
2773 2773 */
2774 2774 return (DDI_NOT_WELL_FORMED);
2775 2775 }
2776 2776
2777 2777 if (mdi_prop_lookup_int(pip, LUN_PROP, &lun) !=
2778 2778 DDI_PROP_SUCCESS) {
2779 2779 mptsas_log(mpt, CE_WARN, "Get lun property failed\n");
2780 2780 return (DDI_FAILURE);
2781 2781 }
2782 2782
2783 2783 if (mdi_prop_lookup_string(pip, SCSI_ADDR_PROP_TARGET_PORT,
2784 2784 &psas_wwn) == MDI_SUCCESS) {
2785 2785 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) {
2786 2786 sas_wwn = 0;
2787 2787 }
2788 2788 (void) mdi_prop_free(psas_wwn);
2789 2789 }
2790 2790 } else {
2791 2791 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tgt_dip,
2792 2792 DDI_PROP_DONTPASS, LUN_PROP, 0);
2793 2793 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, tgt_dip,
2794 2794 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &psas_wwn) ==
2795 2795 DDI_PROP_SUCCESS) {
2796 2796 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) {
2797 2797 sas_wwn = 0;
2798 2798 }
2799 2799 ddi_prop_free(psas_wwn);
2800 2800 } else {
2801 2801 sas_wwn = 0;
2802 2802 }
2803 2803 }
2804 2804 ASSERT((sas_wwn != 0) || (phymask != 0));
2805 2805 mutex_enter(&mpt->m_mutex);
2806 2806 ptgt = mptsas_hash_search(&mpt->m_active->m_tgttbl, sas_wwn, phymask);
2807 2807 mutex_exit(&mpt->m_mutex);
2808 2808 if (ptgt == NULL) {
2809 2809 mptsas_log(mpt, CE_WARN, "!tgt_init: target doesn't exist or "
2810 2810 "gone already! phymask:%x, saswwn %"PRIx64, phymask,
2811 2811 sas_wwn);
2812 2812 return (DDI_FAILURE);
2813 2813 }
2814 2814 if (hba_tran->tran_tgt_private == NULL) {
2815 2815 tgt_private = kmem_zalloc(sizeof (mptsas_tgt_private_t),
2816 2816 KM_SLEEP);
2817 2817 tgt_private->t_lun = lun;
2818 2818 tgt_private->t_private = ptgt;
2819 2819 hba_tran->tran_tgt_private = tgt_private;
2820 2820 }
2821 2821
2822 2822 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) {
2823 2823 return (DDI_SUCCESS);
2824 2824 }
2825 2825 mutex_enter(&mpt->m_mutex);
2826 2826
2827 2827 if (ptgt->m_deviceinfo &
2828 2828 (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
2829 2829 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
2830 2830 uchar_t *inq89 = NULL;
2831 2831 int inq89_len = 0x238;
2832 2832 int reallen = 0;
2833 2833 int rval = 0;
2834 2834 struct sata_id *sid = NULL;
2835 2835 char model[SATA_ID_MODEL_LEN + 1];
2836 2836 char fw[SATA_ID_FW_LEN + 1];
2837 2837 char *vid, *pid;
2838 2838 int i;
2839 2839
2840 2840 mutex_exit(&mpt->m_mutex);
2841 2841 /*
2842 2842 * According SCSI/ATA Translation -2 (SAT-2) revision 01a
2843 2843 * chapter 12.4.2 VPD page 89h includes 512 bytes ATA IDENTIFY
2844 2844 * DEVICE data or ATA IDENTIFY PACKET DEVICE data.
2845 2845 */
2846 2846 inq89 = kmem_zalloc(inq89_len, KM_SLEEP);
2847 2847 rval = mptsas_inquiry(mpt, ptgt, 0, 0x89,
2848 2848 inq89, inq89_len, &reallen, 1);
2849 2849
2850 2850 if (rval != 0) {
2851 2851 if (inq89 != NULL) {
2852 2852 kmem_free(inq89, inq89_len);
2853 2853 }
2854 2854
2855 2855 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
2856 2856 "0x89 for SATA target:%x failed!", ptgt->m_devhdl);
2857 2857 return (DDI_SUCCESS);
2858 2858 }
2859 2859 sid = (void *)(&inq89[60]);
2860 2860
2861 2861 swab(sid->ai_model, model, SATA_ID_MODEL_LEN);
2862 2862 swab(sid->ai_fw, fw, SATA_ID_FW_LEN);
2863 2863
2864 2864 model[SATA_ID_MODEL_LEN] = 0;
2865 2865 fw[SATA_ID_FW_LEN] = 0;
2866 2866
2867 2867 /*
2868 2868 * split model into into vid/pid
2869 2869 */
2870 2870 for (i = 0, pid = model; i < SATA_ID_MODEL_LEN; i++, pid++)
2871 2871 if ((*pid == ' ') || (*pid == '\t'))
2872 2872 break;
2873 2873 if (i < SATA_ID_MODEL_LEN) {
2874 2874 vid = model;
2875 2875 /*
2876 2876 * terminate vid, establish pid
2877 2877 */
2878 2878 *pid++ = 0;
2879 2879 } else {
2880 2880 /*
2881 2881 * vid will stay "ATA ", the rule is same
2882 2882 * as sata framework implementation.
2883 2883 */
2884 2884 vid = NULL;
2885 2885 /*
2886 2886 * model is all pid
2887 2887 */
2888 2888 pid = model;
2889 2889 }
2890 2890
2891 2891 /*
2892 2892 * override SCSA "inquiry-*" properties
2893 2893 */
2894 2894 if (vid)
2895 2895 (void) scsi_device_prop_update_inqstring(sd,
2896 2896 INQUIRY_VENDOR_ID, vid, strlen(vid));
2897 2897 if (pid)
2898 2898 (void) scsi_device_prop_update_inqstring(sd,
2899 2899 INQUIRY_PRODUCT_ID, pid, strlen(pid));
2900 2900 (void) scsi_device_prop_update_inqstring(sd,
2901 2901 INQUIRY_REVISION_ID, fw, strlen(fw));
2902 2902
2903 2903 if (inq89 != NULL) {
2904 2904 kmem_free(inq89, inq89_len);
2905 2905 }
2906 2906 } else {
2907 2907 mutex_exit(&mpt->m_mutex);
2908 2908 }
2909 2909
2910 2910 return (DDI_SUCCESS);
2911 2911 }
2912 2912 /*
2913 2913 * tran_tgt_free(9E) - target device instance deallocation
2914 2914 */
2915 2915 static void
2916 2916 mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
2917 2917 scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
2918 2918 {
2919 2919 #ifndef __lock_lint
2920 2920 _NOTE(ARGUNUSED(hba_dip, tgt_dip, hba_tran, sd))
2921 2921 #endif
2922 2922
2923 2923 mptsas_tgt_private_t *tgt_private = hba_tran->tran_tgt_private;
2924 2924
2925 2925 if (tgt_private != NULL) {
2926 2926 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t));
2927 2927 hba_tran->tran_tgt_private = NULL;
2928 2928 }
2929 2929 }
2930 2930
2931 2931 /*
2932 2932 * scsi_pkt handling
2933 2933 *
2934 2934 * Visible to the external world via the transport structure.
2935 2935 */
2936 2936
2937 2937 /*
2938 2938 * Notes:
2939 2939 * - transport the command to the addressed SCSI target/lun device
2940 2940 * - normal operation is to schedule the command to be transported,
2941 2941 * and return TRAN_ACCEPT if this is successful.
2942 2942 * - if NO_INTR, tran_start must poll device for command completion
2943 2943 */
2944 2944 static int
2945 2945 mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt)
2946 2946 {
2947 2947 #ifndef __lock_lint
2948 2948 _NOTE(ARGUNUSED(ap))
2949 2949 #endif
2950 2950 mptsas_t *mpt = PKT2MPT(pkt);
2951 2951 mptsas_cmd_t *cmd = PKT2CMD(pkt);
2952 2952 int rval;
2953 2953 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
2954 2954
2955 2955 NDBG1(("mptsas_scsi_start: pkt=0x%p", (void *)pkt));
2956 2956 ASSERT(ptgt);
2957 2957 if (ptgt == NULL)
2958 2958 return (TRAN_FATAL_ERROR);
2959 2959
2960 2960 /*
2961 2961 * prepare the pkt before taking mutex.
2962 2962 */
2963 2963 rval = mptsas_prepare_pkt(cmd);
2964 2964 if (rval != TRAN_ACCEPT) {
2965 2965 return (rval);
2966 2966 }
2967 2967
2968 2968 /*
2969 2969 * Send the command to target/lun, however your HBA requires it.
2970 2970 * If busy, return TRAN_BUSY; if there's some other formatting error
2971 2971 * in the packet, return TRAN_BADPKT; otherwise, fall through to the
2972 2972 * return of TRAN_ACCEPT.
2973 2973 *
2974 2974 * Remember that access to shared resources, including the mptsas_t
2975 2975 * data structure and the HBA hardware registers, must be protected
2976 2976 * with mutexes, here and everywhere.
2977 2977 *
2978 2978 * Also remember that at interrupt time, you'll get an argument
2979 2979 * to the interrupt handler which is a pointer to your mptsas_t
2980 2980 * structure; you'll have to remember which commands are outstanding
2981 2981 * and which scsi_pkt is the currently-running command so the
2982 2982 * interrupt handler can refer to the pkt to set completion
2983 2983 * status, call the target driver back through pkt_comp, etc.
2984 2984 *
2985 2985 * If the instance lock is held by other thread, don't spin to wait
2986 2986 * for it. Instead, queue the cmd and next time when the instance lock
2987 2987 * is not held, accept all the queued cmd. A extra tx_waitq is
2988 2988 * introduced to protect the queue.
2989 2989 *
2990 2990 * The polled cmd will not be queud and accepted as usual.
2991 2991 *
2992 2992 * Under the tx_waitq mutex, record whether a thread is draining
2993 2993 * the tx_waitq. An IO requesting thread that finds the instance
2994 2994 * mutex contended appends to the tx_waitq and while holding the
2995 2995 * tx_wait mutex, if the draining flag is not set, sets it and then
2996 2996 * proceeds to spin for the instance mutex. This scheme ensures that
2997 2997 * the last cmd in a burst be processed.
2998 2998 *
2999 2999 * we enable this feature only when the helper threads are enabled,
3000 3000 * at which we think the loads are heavy.
3001 3001 *
3002 3002 * per instance mutex m_tx_waitq_mutex is introduced to protect the
3003 3003 * m_tx_waitqtail, m_tx_waitq, m_tx_draining.
3004 3004 */
3005 3005
3006 3006 if (mpt->m_doneq_thread_n) {
3007 3007 if (mutex_tryenter(&mpt->m_mutex) != 0) {
3008 3008 rval = mptsas_accept_txwq_and_pkt(mpt, cmd);
3009 3009 mutex_exit(&mpt->m_mutex);
3010 3010 } else if (cmd->cmd_pkt_flags & FLAG_NOINTR) {
3011 3011 mutex_enter(&mpt->m_mutex);
3012 3012 rval = mptsas_accept_txwq_and_pkt(mpt, cmd);
3013 3013 mutex_exit(&mpt->m_mutex);
3014 3014 } else {
3015 3015 mutex_enter(&mpt->m_tx_waitq_mutex);
3016 3016 /*
3017 3017 * ptgt->m_dr_flag is protected by m_mutex or
3018 3018 * m_tx_waitq_mutex. In this case, m_tx_waitq_mutex
3019 3019 * is acquired.
3020 3020 */
3021 3021 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3022 3022 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3023 3023 /*
3024 3024 * The command should be allowed to
3025 3025 * retry by returning TRAN_BUSY to
3026 3026 * to stall the I/O's which come from
3027 3027 * scsi_vhci since the device/path is
3028 3028 * in unstable state now.
3029 3029 */
3030 3030 mutex_exit(&mpt->m_tx_waitq_mutex);
3031 3031 return (TRAN_BUSY);
3032 3032 } else {
3033 3033 /*
3034 3034 * The device is offline, just fail the
3035 3035 * command by returning
3036 3036 * TRAN_FATAL_ERROR.
3037 3037 */
3038 3038 mutex_exit(&mpt->m_tx_waitq_mutex);
3039 3039 return (TRAN_FATAL_ERROR);
3040 3040 }
3041 3041 }
3042 3042 if (mpt->m_tx_draining) {
3043 3043 cmd->cmd_flags |= CFLAG_TXQ;
3044 3044 *mpt->m_tx_waitqtail = cmd;
3045 3045 mpt->m_tx_waitqtail = &cmd->cmd_linkp;
3046 3046 mutex_exit(&mpt->m_tx_waitq_mutex);
3047 3047 } else { /* drain the queue */
3048 3048 mpt->m_tx_draining = 1;
3049 3049 mutex_exit(&mpt->m_tx_waitq_mutex);
3050 3050 mutex_enter(&mpt->m_mutex);
3051 3051 rval = mptsas_accept_txwq_and_pkt(mpt, cmd);
3052 3052 mutex_exit(&mpt->m_mutex);
3053 3053 }
3054 3054 }
3055 3055 } else {
3056 3056 mutex_enter(&mpt->m_mutex);
3057 3057 /*
3058 3058 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex
3059 3059 * in this case, m_mutex is acquired.
3060 3060 */
3061 3061 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3062 3062 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3063 3063 /*
3064 3064 * commands should be allowed to retry by
3065 3065 * returning TRAN_BUSY to stall the I/O's
3066 3066 * which come from scsi_vhci since the device/
3067 3067 * path is in unstable state now.
3068 3068 */
3069 3069 mutex_exit(&mpt->m_mutex);
3070 3070 return (TRAN_BUSY);
3071 3071 } else {
3072 3072 /*
3073 3073 * The device is offline, just fail the
3074 3074 * command by returning TRAN_FATAL_ERROR.
3075 3075 */
3076 3076 mutex_exit(&mpt->m_mutex);
3077 3077 return (TRAN_FATAL_ERROR);
3078 3078 }
3079 3079 }
3080 3080 rval = mptsas_accept_pkt(mpt, cmd);
3081 3081 mutex_exit(&mpt->m_mutex);
3082 3082 }
3083 3083
3084 3084 return (rval);
3085 3085 }
3086 3086
3087 3087 /*
3088 3088 * Accept all the queued cmds(if any) before accept the current one.
3089 3089 */
3090 3090 static int
3091 3091 mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd)
3092 3092 {
3093 3093 int rval;
3094 3094 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3095 3095
3096 3096 ASSERT(mutex_owned(&mpt->m_mutex));
3097 3097 /*
3098 3098 * The call to mptsas_accept_tx_waitq() must always be performed
3099 3099 * because that is where mpt->m_tx_draining is cleared.
3100 3100 */
3101 3101 mutex_enter(&mpt->m_tx_waitq_mutex);
3102 3102 mptsas_accept_tx_waitq(mpt);
3103 3103 mutex_exit(&mpt->m_tx_waitq_mutex);
3104 3104 /*
3105 3105 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex
3106 3106 * in this case, m_mutex is acquired.
3107 3107 */
3108 3108 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3109 3109 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3110 3110 /*
3111 3111 * The command should be allowed to retry by returning
3112 3112 * TRAN_BUSY to stall the I/O's which come from
3113 3113 * scsi_vhci since the device/path is in unstable state
3114 3114 * now.
3115 3115 */
3116 3116 return (TRAN_BUSY);
3117 3117 } else {
3118 3118 /*
3119 3119 * The device is offline, just fail the command by
3120 3120 * return TRAN_FATAL_ERROR.
3121 3121 */
3122 3122 return (TRAN_FATAL_ERROR);
3123 3123 }
3124 3124 }
3125 3125 rval = mptsas_accept_pkt(mpt, cmd);
3126 3126
3127 3127 return (rval);
3128 3128 }
3129 3129
3130 3130 static int
3131 3131 mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd)
3132 3132 {
3133 3133 int rval = TRAN_ACCEPT;
3134 3134 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3135 3135
3136 3136 NDBG1(("mptsas_accept_pkt: cmd=0x%p", (void *)cmd));
3137 3137
3138 3138 ASSERT(mutex_owned(&mpt->m_mutex));
3139 3139
3140 3140 if ((cmd->cmd_flags & CFLAG_PREPARED) == 0) {
3141 3141 rval = mptsas_prepare_pkt(cmd);
3142 3142 if (rval != TRAN_ACCEPT) {
3143 3143 cmd->cmd_flags &= ~CFLAG_TRANFLAG;
3144 3144 return (rval);
3145 3145 }
3146 3146 }
3147 3147
3148 3148 /*
3149 3149 * reset the throttle if we were draining
3150 3150 */
3151 3151 if ((ptgt->m_t_ncmds == 0) &&
3152 3152 (ptgt->m_t_throttle == DRAIN_THROTTLE)) {
3153 3153 NDBG23(("reset throttle"));
3154 3154 ASSERT(ptgt->m_reset_delay == 0);
3155 3155 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
3156 3156 }
3157 3157
3158 3158 /*
3159 3159 * If HBA is being reset, the DevHandles are being re-initialized,
3160 3160 * which means that they could be invalid even if the target is still
3161 3161 * attached. Check if being reset and if DevHandle is being
3162 3162 * re-initialized. If this is the case, return BUSY so the I/O can be
3163 3163 * retried later.
3164 3164 */
3165 3165 if ((ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) && mpt->m_in_reset) {
3166 3166 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
3167 3167 if (cmd->cmd_flags & CFLAG_TXQ) {
3168 3168 mptsas_doneq_add(mpt, cmd);
3169 3169 mptsas_doneq_empty(mpt);
3170 3170 return (rval);
3171 3171 } else {
3172 3172 return (TRAN_BUSY);
3173 3173 }
3174 3174 }
3175 3175
3176 3176 /*
3177 3177 * If device handle has already been invalidated, just
3178 3178 * fail the command. In theory, command from scsi_vhci
3179 3179 * client is impossible send down command with invalid
3180 3180 * devhdl since devhdl is set after path offline, target
3181 3181 * driver is not suppose to select a offlined path.
3182 3182 */
3183 3183 if (ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) {
3184 3184 NDBG20(("rejecting command, it might because invalid devhdl "
3185 3185 "request."));
3186 3186 mptsas_set_pkt_reason(mpt, cmd, CMD_DEV_GONE, STAT_TERMINATED);
3187 3187 if (cmd->cmd_flags & CFLAG_TXQ) {
3188 3188 mptsas_doneq_add(mpt, cmd);
3189 3189 mptsas_doneq_empty(mpt);
3190 3190 return (rval);
3191 3191 } else {
3192 3192 return (TRAN_FATAL_ERROR);
3193 3193 }
3194 3194 }
3195 3195 /*
3196 3196 * The first case is the normal case. mpt gets a command from the
3197 3197 * target driver and starts it.
3198 3198 * Since SMID 0 is reserved and the TM slot is reserved, the actual max
3199 3199 * commands is m_max_requests - 2.
3200 3200 */
3201 3201 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) &&
3202 3202 (ptgt->m_t_throttle > HOLD_THROTTLE) &&
3203 3203 (ptgt->m_t_ncmds < ptgt->m_t_throttle) &&
3204 3204 (ptgt->m_reset_delay == 0) &&
3205 3205 (ptgt->m_t_nwait == 0) &&
3206 3206 ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0)) {
3207 3207 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
3208 3208 (void) mptsas_start_cmd(mpt, cmd);
3209 3209 } else {
3210 3210 mptsas_waitq_add(mpt, cmd);
3211 3211 }
3212 3212 } else {
3213 3213 /*
3214 3214 * Add this pkt to the work queue
3215 3215 */
3216 3216 mptsas_waitq_add(mpt, cmd);
3217 3217
3218 3218 if (cmd->cmd_pkt_flags & FLAG_NOINTR) {
3219 3219 (void) mptsas_poll(mpt, cmd, MPTSAS_POLL_TIME);
3220 3220
3221 3221 /*
3222 3222 * Only flush the doneq if this is not a TM
3223 3223 * cmd. For TM cmds the flushing of the
3224 3224 * doneq will be done in those routines.
3225 3225 */
3226 3226 if ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) {
3227 3227 mptsas_doneq_empty(mpt);
3228 3228 }
3229 3229 }
3230 3230 }
3231 3231 return (rval);
3232 3232 }
3233 3233
3234 3234 int
3235 3235 mptsas_save_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
3236 3236 {
3237 3237 mptsas_slots_t *slots;
3238 3238 int slot;
3239 3239 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3240 3240
3241 3241 ASSERT(mutex_owned(&mpt->m_mutex));
3242 3242 slots = mpt->m_active;
3243 3243
3244 3244 /*
3245 3245 * Account for reserved TM request slot and reserved SMID of 0.
3246 3246 */
3247 3247 ASSERT(slots->m_n_slots == (mpt->m_max_requests - 2));
3248 3248
3249 3249 /*
3250 3250 * m_tags is equivalent to the SMID when sending requests. Since the
3251 3251 * SMID cannot be 0, start out at one if rolling over past the size
3252 3252 * of the request queue depth. Also, don't use the last SMID, which is
3253 3253 * reserved for TM requests.
3254 3254 */
3255 3255 slot = (slots->m_tags)++;
3256 3256 if (slots->m_tags > slots->m_n_slots) {
3257 3257 slots->m_tags = 1;
3258 3258 }
3259 3259
3260 3260 alloc_tag:
3261 3261 /* Validate tag, should never fail. */
3262 3262 if (slots->m_slot[slot] == NULL) {
3263 3263 /*
3264 3264 * Make sure SMID is not using reserved value of 0
3265 3265 * and the TM request slot.
3266 3266 */
3267 3267 ASSERT((slot > 0) && (slot <= slots->m_n_slots));
3268 3268 cmd->cmd_slot = slot;
3269 3269 slots->m_slot[slot] = cmd;
3270 3270 mpt->m_ncmds++;
3271 3271
3272 3272 /*
3273 3273 * only increment per target ncmds if this is not a
3274 3274 * command that has no target associated with it (i.e. a
3275 3275 * event acknoledgment)
3276 3276 */
3277 3277 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
3278 3278 ptgt->m_t_ncmds++;
3279 3279 }
3280 3280 cmd->cmd_active_timeout = cmd->cmd_pkt->pkt_time;
3281 3281
3282 3282 /*
3283 3283 * If initial timout is less than or equal to one tick, bump
3284 3284 * the timeout by a tick so that command doesn't timeout before
3285 3285 * its allotted time.
3286 3286 */
3287 3287 if (cmd->cmd_active_timeout <= mptsas_scsi_watchdog_tick) {
3288 3288 cmd->cmd_active_timeout += mptsas_scsi_watchdog_tick;
3289 3289 }
3290 3290 return (TRUE);
3291 3291 } else {
3292 3292 int i;
3293 3293
3294 3294 /*
3295 3295 * If slot in use, scan until a free one is found. Don't use 0
3296 3296 * or final slot, which is reserved for TM requests.
3297 3297 */
3298 3298 for (i = 0; i < slots->m_n_slots; i++) {
3299 3299 slot = slots->m_tags;
3300 3300 if (++(slots->m_tags) > slots->m_n_slots) {
3301 3301 slots->m_tags = 1;
3302 3302 }
3303 3303 if (slots->m_slot[slot] == NULL) {
3304 3304 NDBG22(("found free slot %d", slot));
3305 3305 goto alloc_tag;
3306 3306 }
3307 3307 }
3308 3308 }
3309 3309 return (FALSE);
3310 3310 }
3311 3311
3312 3312 /*
3313 3313 * prepare the pkt:
3314 3314 * the pkt may have been resubmitted or just reused so
3315 3315 * initialize some fields and do some checks.
3316 3316 */
3317 3317 static int
3318 3318 mptsas_prepare_pkt(mptsas_cmd_t *cmd)
3319 3319 {
3320 3320 struct scsi_pkt *pkt = CMD2PKT(cmd);
3321 3321
3322 3322 NDBG1(("mptsas_prepare_pkt: cmd=0x%p", (void *)cmd));
3323 3323
3324 3324 /*
3325 3325 * Reinitialize some fields that need it; the packet may
3326 3326 * have been resubmitted
3327 3327 */
3328 3328 pkt->pkt_reason = CMD_CMPLT;
3329 3329 pkt->pkt_state = 0;
3330 3330 pkt->pkt_statistics = 0;
3331 3331 pkt->pkt_resid = 0;
3332 3332 cmd->cmd_age = 0;
3333 3333 cmd->cmd_pkt_flags = pkt->pkt_flags;
3334 3334
3335 3335 /*
3336 3336 * zero status byte.
3337 3337 */
3338 3338 *(pkt->pkt_scbp) = 0;
3339 3339
3340 3340 if (cmd->cmd_flags & CFLAG_DMAVALID) {
3341 3341 pkt->pkt_resid = cmd->cmd_dmacount;
3342 3342
3343 3343 /*
3344 3344 * consistent packets need to be sync'ed first
3345 3345 * (only for data going out)
3346 3346 */
3347 3347 if ((cmd->cmd_flags & CFLAG_CMDIOPB) &&
3348 3348 (cmd->cmd_flags & CFLAG_DMASEND)) {
3349 3349 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
3350 3350 DDI_DMA_SYNC_FORDEV);
3351 3351 }
3352 3352 }
3353 3353
3354 3354 cmd->cmd_flags =
3355 3355 (cmd->cmd_flags & ~(CFLAG_TRANFLAG)) |
3356 3356 CFLAG_PREPARED | CFLAG_IN_TRANSPORT;
3357 3357
3358 3358 return (TRAN_ACCEPT);
3359 3359 }
3360 3360
3361 3361 /*
3362 3362 * tran_init_pkt(9E) - allocate scsi_pkt(9S) for command
3363 3363 *
3364 3364 * One of three possibilities:
3365 3365 * - allocate scsi_pkt
3366 3366 * - allocate scsi_pkt and DMA resources
3367 3367 * - allocate DMA resources to an already-allocated pkt
3368 3368 */
3369 3369 static struct scsi_pkt *
3370 3370 mptsas_scsi_init_pkt(struct scsi_address *ap, struct scsi_pkt *pkt,
3371 3371 struct buf *bp, int cmdlen, int statuslen, int tgtlen, int flags,
3372 3372 int (*callback)(), caddr_t arg)
3373 3373 {
3374 3374 mptsas_cmd_t *cmd, *new_cmd;
3375 3375 mptsas_t *mpt = ADDR2MPT(ap);
3376 3376 int failure = 1;
3377 3377 uint_t oldcookiec;
3378 3378 mptsas_target_t *ptgt = NULL;
3379 3379 int rval;
3380 3380 mptsas_tgt_private_t *tgt_private;
3381 3381 int kf;
3382 3382
3383 3383 kf = (callback == SLEEP_FUNC)? KM_SLEEP: KM_NOSLEEP;
3384 3384
3385 3385 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->
3386 3386 tran_tgt_private;
3387 3387 ASSERT(tgt_private != NULL);
3388 3388 if (tgt_private == NULL) {
3389 3389 return (NULL);
3390 3390 }
3391 3391 ptgt = tgt_private->t_private;
3392 3392 ASSERT(ptgt != NULL);
3393 3393 if (ptgt == NULL)
3394 3394 return (NULL);
3395 3395 ap->a_target = ptgt->m_devhdl;
3396 3396 ap->a_lun = tgt_private->t_lun;
3397 3397
3398 3398 ASSERT(callback == NULL_FUNC || callback == SLEEP_FUNC);
3399 3399 #ifdef MPTSAS_TEST_EXTRN_ALLOC
3400 3400 statuslen *= 100; tgtlen *= 4;
3401 3401 #endif
3402 3402 NDBG3(("mptsas_scsi_init_pkt:\n"
3403 3403 "\ttgt=%d in=0x%p bp=0x%p clen=%d slen=%d tlen=%d flags=%x",
3404 3404 ap->a_target, (void *)pkt, (void *)bp,
3405 3405 cmdlen, statuslen, tgtlen, flags));
3406 3406
3407 3407 /*
3408 3408 * Allocate the new packet.
3409 3409 */
3410 3410 if (pkt == NULL) {
3411 3411 ddi_dma_handle_t save_dma_handle;
3412 3412 ddi_dma_handle_t save_arq_dma_handle;
3413 3413 struct buf *save_arq_bp;
3414 3414 ddi_dma_cookie_t save_arqcookie;
3415 3415
3416 3416 cmd = kmem_cache_alloc(mpt->m_kmem_cache, kf);
3417 3417
3418 3418 if (cmd) {
3419 3419 save_dma_handle = cmd->cmd_dmahandle;
3420 3420 save_arq_dma_handle = cmd->cmd_arqhandle;
3421 3421 save_arq_bp = cmd->cmd_arq_buf;
3422 3422 save_arqcookie = cmd->cmd_arqcookie;
3423 3423 bzero(cmd, sizeof (*cmd) + scsi_pkt_size());
3424 3424 cmd->cmd_dmahandle = save_dma_handle;
3425 3425 cmd->cmd_arqhandle = save_arq_dma_handle;
3426 3426 cmd->cmd_arq_buf = save_arq_bp;
3427 3427 cmd->cmd_arqcookie = save_arqcookie;
3428 3428
3429 3429 pkt = (void *)((uchar_t *)cmd +
3430 3430 sizeof (struct mptsas_cmd));
3431 3431 pkt->pkt_ha_private = (opaque_t)cmd;
3432 3432 pkt->pkt_address = *ap;
3433 3433 pkt->pkt_private = (opaque_t)cmd->cmd_pkt_private;
3434 3434 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb;
3435 3435 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb;
3436 3436 cmd->cmd_pkt = (struct scsi_pkt *)pkt;
3437 3437 cmd->cmd_cdblen = (uchar_t)cmdlen;
3438 3438 cmd->cmd_scblen = statuslen;
3439 3439 cmd->cmd_rqslen = SENSE_LENGTH;
3440 3440 cmd->cmd_tgt_addr = ptgt;
3441 3441 failure = 0;
3442 3442 }
3443 3443
3444 3444 if (failure || (cmdlen > sizeof (cmd->cmd_cdb)) ||
3445 3445 (tgtlen > PKT_PRIV_LEN) ||
3446 3446 (statuslen > EXTCMDS_STATUS_SIZE)) {
3447 3447 if (failure == 0) {
3448 3448 /*
3449 3449 * if extern alloc fails, all will be
3450 3450 * deallocated, including cmd
3451 3451 */
3452 3452 failure = mptsas_pkt_alloc_extern(mpt, cmd,
3453 3453 cmdlen, tgtlen, statuslen, kf);
3454 3454 }
3455 3455 if (failure) {
3456 3456 /*
3457 3457 * if extern allocation fails, it will
3458 3458 * deallocate the new pkt as well
3459 3459 */
3460 3460 return (NULL);
3461 3461 }
3462 3462 }
3463 3463 new_cmd = cmd;
3464 3464
3465 3465 } else {
3466 3466 cmd = PKT2CMD(pkt);
3467 3467 new_cmd = NULL;
3468 3468 }
3469 3469
3470 3470
3471 3471 /* grab cmd->cmd_cookiec here as oldcookiec */
3472 3472
3473 3473 oldcookiec = cmd->cmd_cookiec;
3474 3474
3475 3475 /*
3476 3476 * If the dma was broken up into PARTIAL transfers cmd_nwin will be
3477 3477 * greater than 0 and we'll need to grab the next dma window
3478 3478 */
3479 3479 /*
3480 3480 * SLM-not doing extra command frame right now; may add later
3481 3481 */
3482 3482
3483 3483 if (cmd->cmd_nwin > 0) {
3484 3484
3485 3485 /*
3486 3486 * Make sure we havn't gone past the the total number
3487 3487 * of windows
3488 3488 */
3489 3489 if (++cmd->cmd_winindex >= cmd->cmd_nwin) {
3490 3490 return (NULL);
3491 3491 }
3492 3492 if (ddi_dma_getwin(cmd->cmd_dmahandle, cmd->cmd_winindex,
3493 3493 &cmd->cmd_dma_offset, &cmd->cmd_dma_len,
3494 3494 &cmd->cmd_cookie, &cmd->cmd_cookiec) == DDI_FAILURE) {
3495 3495 return (NULL);
3496 3496 }
3497 3497 goto get_dma_cookies;
3498 3498 }
3499 3499
3500 3500
3501 3501 if (flags & PKT_XARQ) {
3502 3502 cmd->cmd_flags |= CFLAG_XARQ;
3503 3503 }
3504 3504
3505 3505 /*
3506 3506 * DMA resource allocation. This version assumes your
3507 3507 * HBA has some sort of bus-mastering or onboard DMA capability, with a
3508 3508 * scatter-gather list of length MPTSAS_MAX_DMA_SEGS, as given in the
3509 3509 * ddi_dma_attr_t structure and passed to scsi_impl_dmaget.
3510 3510 */
3511 3511 if (bp && (bp->b_bcount != 0) &&
3512 3512 (cmd->cmd_flags & CFLAG_DMAVALID) == 0) {
3513 3513
3514 3514 int cnt, dma_flags;
3515 3515 mptti_t *dmap; /* ptr to the S/G list */
3516 3516
3517 3517 /*
3518 3518 * Set up DMA memory and position to the next DMA segment.
3519 3519 */
3520 3520 ASSERT(cmd->cmd_dmahandle != NULL);
3521 3521
3522 3522 if (bp->b_flags & B_READ) {
3523 3523 dma_flags = DDI_DMA_READ;
3524 3524 cmd->cmd_flags &= ~CFLAG_DMASEND;
3525 3525 } else {
3526 3526 dma_flags = DDI_DMA_WRITE;
3527 3527 cmd->cmd_flags |= CFLAG_DMASEND;
3528 3528 }
3529 3529 if (flags & PKT_CONSISTENT) {
3530 3530 cmd->cmd_flags |= CFLAG_CMDIOPB;
3531 3531 dma_flags |= DDI_DMA_CONSISTENT;
3532 3532 }
3533 3533
3534 3534 if (flags & PKT_DMA_PARTIAL) {
3535 3535 dma_flags |= DDI_DMA_PARTIAL;
3536 3536 }
3537 3537
3538 3538 /*
3539 3539 * workaround for byte hole issue on psycho and
3540 3540 * schizo pre 2.1
3541 3541 */
3542 3542 if ((bp->b_flags & B_READ) && ((bp->b_flags &
3543 3543 (B_PAGEIO|B_REMAPPED)) != B_PAGEIO) &&
3544 3544 ((uintptr_t)bp->b_un.b_addr & 0x7)) {
3545 3545 dma_flags |= DDI_DMA_CONSISTENT;
3546 3546 }
3547 3547
3548 3548 rval = ddi_dma_buf_bind_handle(cmd->cmd_dmahandle, bp,
3549 3549 dma_flags, callback, arg,
3550 3550 &cmd->cmd_cookie, &cmd->cmd_cookiec);
3551 3551 if (rval == DDI_DMA_PARTIAL_MAP) {
3552 3552 (void) ddi_dma_numwin(cmd->cmd_dmahandle,
3553 3553 &cmd->cmd_nwin);
3554 3554 cmd->cmd_winindex = 0;
3555 3555 (void) ddi_dma_getwin(cmd->cmd_dmahandle,
3556 3556 cmd->cmd_winindex, &cmd->cmd_dma_offset,
3557 3557 &cmd->cmd_dma_len, &cmd->cmd_cookie,
3558 3558 &cmd->cmd_cookiec);
3559 3559 } else if (rval && (rval != DDI_DMA_MAPPED)) {
3560 3560 switch (rval) {
3561 3561 case DDI_DMA_NORESOURCES:
3562 3562 bioerror(bp, 0);
3563 3563 break;
3564 3564 case DDI_DMA_BADATTR:
3565 3565 case DDI_DMA_NOMAPPING:
3566 3566 bioerror(bp, EFAULT);
3567 3567 break;
3568 3568 case DDI_DMA_TOOBIG:
3569 3569 default:
3570 3570 bioerror(bp, EINVAL);
3571 3571 break;
3572 3572 }
3573 3573 cmd->cmd_flags &= ~CFLAG_DMAVALID;
3574 3574 if (new_cmd) {
3575 3575 mptsas_scsi_destroy_pkt(ap, pkt);
3576 3576 }
3577 3577 return ((struct scsi_pkt *)NULL);
3578 3578 }
3579 3579
3580 3580 get_dma_cookies:
3581 3581 cmd->cmd_flags |= CFLAG_DMAVALID;
3582 3582 ASSERT(cmd->cmd_cookiec > 0);
3583 3583
3584 3584 if (cmd->cmd_cookiec > MPTSAS_MAX_CMD_SEGS) {
3585 3585 mptsas_log(mpt, CE_NOTE, "large cookiec received %d\n",
3586 3586 cmd->cmd_cookiec);
3587 3587 bioerror(bp, EINVAL);
3588 3588 if (new_cmd) {
3589 3589 mptsas_scsi_destroy_pkt(ap, pkt);
3590 3590 }
3591 3591 return ((struct scsi_pkt *)NULL);
3592 3592 }
3593 3593
3594 3594 /*
3595 3595 * Allocate extra SGL buffer if needed.
3596 3596 */
3597 3597 if ((cmd->cmd_cookiec > MPTSAS_MAX_FRAME_SGES64(mpt)) &&
3598 3598 (cmd->cmd_extra_frames == NULL)) {
3599 3599 if (mptsas_alloc_extra_sgl_frame(mpt, cmd) ==
3600 3600 DDI_FAILURE) {
3601 3601 mptsas_log(mpt, CE_WARN, "MPT SGL mem alloc "
3602 3602 "failed");
3603 3603 bioerror(bp, ENOMEM);
3604 3604 if (new_cmd) {
3605 3605 mptsas_scsi_destroy_pkt(ap, pkt);
3606 3606 }
3607 3607 return ((struct scsi_pkt *)NULL);
3608 3608 }
3609 3609 }
3610 3610
3611 3611 /*
3612 3612 * Always use scatter-gather transfer
3613 3613 * Use the loop below to store physical addresses of
3614 3614 * DMA segments, from the DMA cookies, into your HBA's
3615 3615 * scatter-gather list.
3616 3616 * We need to ensure we have enough kmem alloc'd
3617 3617 * for the sg entries since we are no longer using an
3618 3618 * array inside mptsas_cmd_t.
3619 3619 *
3620 3620 * We check cmd->cmd_cookiec against oldcookiec so
3621 3621 * the scatter-gather list is correctly allocated
3622 3622 */
3623 3623
3624 3624 if (oldcookiec != cmd->cmd_cookiec) {
3625 3625 if (cmd->cmd_sg != (mptti_t *)NULL) {
3626 3626 kmem_free(cmd->cmd_sg, sizeof (mptti_t) *
3627 3627 oldcookiec);
3628 3628 cmd->cmd_sg = NULL;
3629 3629 }
3630 3630 }
3631 3631
3632 3632 if (cmd->cmd_sg == (mptti_t *)NULL) {
3633 3633 cmd->cmd_sg = kmem_alloc((size_t)(sizeof (mptti_t)*
3634 3634 cmd->cmd_cookiec), kf);
3635 3635
3636 3636 if (cmd->cmd_sg == (mptti_t *)NULL) {
3637 3637 mptsas_log(mpt, CE_WARN,
3638 3638 "unable to kmem_alloc enough memory "
3639 3639 "for scatter/gather list");
3640 3640 /*
3641 3641 * if we have an ENOMEM condition we need to behave
3642 3642 * the same way as the rest of this routine
3643 3643 */
3644 3644
3645 3645 bioerror(bp, ENOMEM);
3646 3646 if (new_cmd) {
3647 3647 mptsas_scsi_destroy_pkt(ap, pkt);
3648 3648 }
3649 3649 return ((struct scsi_pkt *)NULL);
3650 3650 }
3651 3651 }
3652 3652
3653 3653 dmap = cmd->cmd_sg;
3654 3654
3655 3655 ASSERT(cmd->cmd_cookie.dmac_size != 0);
3656 3656
3657 3657 /*
3658 3658 * store the first segment into the S/G list
3659 3659 */
3660 3660 dmap->count = cmd->cmd_cookie.dmac_size;
3661 3661 dmap->addr.address64.Low = (uint32_t)
3662 3662 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull);
3663 3663 dmap->addr.address64.High = (uint32_t)
3664 3664 (cmd->cmd_cookie.dmac_laddress >> 32);
3665 3665
3666 3666 /*
3667 3667 * dmacount counts the size of the dma for this window
3668 3668 * (if partial dma is being used). totaldmacount
3669 3669 * keeps track of the total amount of dma we have
3670 3670 * transferred for all the windows (needed to calculate
3671 3671 * the resid value below).
3672 3672 */
3673 3673 cmd->cmd_dmacount = cmd->cmd_cookie.dmac_size;
3674 3674 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size;
3675 3675
3676 3676 /*
3677 3677 * We already stored the first DMA scatter gather segment,
3678 3678 * start at 1 if we need to store more.
3679 3679 */
3680 3680 for (cnt = 1; cnt < cmd->cmd_cookiec; cnt++) {
3681 3681 /*
3682 3682 * Get next DMA cookie
3683 3683 */
3684 3684 ddi_dma_nextcookie(cmd->cmd_dmahandle,
3685 3685 &cmd->cmd_cookie);
3686 3686 dmap++;
3687 3687
3688 3688 cmd->cmd_dmacount += cmd->cmd_cookie.dmac_size;
3689 3689 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size;
3690 3690
3691 3691 /*
3692 3692 * store the segment parms into the S/G list
3693 3693 */
3694 3694 dmap->count = cmd->cmd_cookie.dmac_size;
3695 3695 dmap->addr.address64.Low = (uint32_t)
3696 3696 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull);
3697 3697 dmap->addr.address64.High = (uint32_t)
3698 3698 (cmd->cmd_cookie.dmac_laddress >> 32);
3699 3699 }
3700 3700
3701 3701 /*
3702 3702 * If this was partially allocated we set the resid
3703 3703 * the amount of data NOT transferred in this window
3704 3704 * If there is only one window, the resid will be 0
3705 3705 */
3706 3706 pkt->pkt_resid = (bp->b_bcount - cmd->cmd_totaldmacount);
3707 3707 NDBG16(("mptsas_dmaget: cmd_dmacount=%d.", cmd->cmd_dmacount));
3708 3708 }
3709 3709 return (pkt);
3710 3710 }
3711 3711
3712 3712 /*
3713 3713 * tran_destroy_pkt(9E) - scsi_pkt(9s) deallocation
3714 3714 *
3715 3715 * Notes:
3716 3716 * - also frees DMA resources if allocated
3717 3717 * - implicit DMA synchonization
3718 3718 */
3719 3719 static void
3720 3720 mptsas_scsi_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
3721 3721 {
3722 3722 mptsas_cmd_t *cmd = PKT2CMD(pkt);
3723 3723 mptsas_t *mpt = ADDR2MPT(ap);
3724 3724
3725 3725 NDBG3(("mptsas_scsi_destroy_pkt: target=%d pkt=0x%p",
3726 3726 ap->a_target, (void *)pkt));
3727 3727
3728 3728 if (cmd->cmd_flags & CFLAG_DMAVALID) {
3729 3729 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle);
3730 3730 cmd->cmd_flags &= ~CFLAG_DMAVALID;
3731 3731 }
3732 3732
3733 3733 if (cmd->cmd_sg) {
3734 3734 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * cmd->cmd_cookiec);
3735 3735 cmd->cmd_sg = NULL;
3736 3736 }
3737 3737
3738 3738 mptsas_free_extra_sgl_frame(mpt, cmd);
3739 3739
3740 3740 if ((cmd->cmd_flags &
3741 3741 (CFLAG_FREE | CFLAG_CDBEXTERN | CFLAG_PRIVEXTERN |
3742 3742 CFLAG_SCBEXTERN)) == 0) {
3743 3743 cmd->cmd_flags = CFLAG_FREE;
3744 3744 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd);
3745 3745 } else {
3746 3746 mptsas_pkt_destroy_extern(mpt, cmd);
3747 3747 }
3748 3748 }
3749 3749
3750 3750 /*
3751 3751 * kmem cache constructor and destructor:
3752 3752 * When constructing, we bzero the cmd and allocate the dma handle
3753 3753 * When destructing, just free the dma handle
3754 3754 */
3755 3755 static int
3756 3756 mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags)
3757 3757 {
3758 3758 mptsas_cmd_t *cmd = buf;
3759 3759 mptsas_t *mpt = cdrarg;
3760 3760 struct scsi_address ap;
3761 3761 uint_t cookiec;
3762 3762 ddi_dma_attr_t arq_dma_attr;
3763 3763 int (*callback)(caddr_t);
3764 3764
3765 3765 callback = (kmflags == KM_SLEEP)? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT;
3766 3766
3767 3767 NDBG4(("mptsas_kmem_cache_constructor"));
3768 3768
3769 3769 ap.a_hba_tran = mpt->m_tran;
3770 3770 ap.a_target = 0;
3771 3771 ap.a_lun = 0;
3772 3772
3773 3773 /*
3774 3774 * allocate a dma handle
3775 3775 */
3776 3776 if ((ddi_dma_alloc_handle(mpt->m_dip, &mpt->m_io_dma_attr, callback,
3777 3777 NULL, &cmd->cmd_dmahandle)) != DDI_SUCCESS) {
3778 3778 cmd->cmd_dmahandle = NULL;
3779 3779 return (-1);
3780 3780 }
3781 3781
3782 3782 cmd->cmd_arq_buf = scsi_alloc_consistent_buf(&ap, (struct buf *)NULL,
3783 3783 SENSE_LENGTH, B_READ, callback, NULL);
3784 3784 if (cmd->cmd_arq_buf == NULL) {
3785 3785 ddi_dma_free_handle(&cmd->cmd_dmahandle);
3786 3786 cmd->cmd_dmahandle = NULL;
3787 3787 return (-1);
3788 3788 }
3789 3789
3790 3790 /*
3791 3791 * allocate a arq handle
3792 3792 */
3793 3793 arq_dma_attr = mpt->m_msg_dma_attr;
3794 3794 arq_dma_attr.dma_attr_sgllen = 1;
3795 3795 if ((ddi_dma_alloc_handle(mpt->m_dip, &arq_dma_attr, callback,
3796 3796 NULL, &cmd->cmd_arqhandle)) != DDI_SUCCESS) {
3797 3797 ddi_dma_free_handle(&cmd->cmd_dmahandle);
3798 3798 scsi_free_consistent_buf(cmd->cmd_arq_buf);
3799 3799 cmd->cmd_dmahandle = NULL;
3800 3800 cmd->cmd_arqhandle = NULL;
3801 3801 return (-1);
3802 3802 }
3803 3803
3804 3804 if (ddi_dma_buf_bind_handle(cmd->cmd_arqhandle,
3805 3805 cmd->cmd_arq_buf, (DDI_DMA_READ | DDI_DMA_CONSISTENT),
3806 3806 callback, NULL, &cmd->cmd_arqcookie, &cookiec) != DDI_SUCCESS) {
3807 3807 ddi_dma_free_handle(&cmd->cmd_dmahandle);
3808 3808 ddi_dma_free_handle(&cmd->cmd_arqhandle);
3809 3809 scsi_free_consistent_buf(cmd->cmd_arq_buf);
3810 3810 cmd->cmd_dmahandle = NULL;
3811 3811 cmd->cmd_arqhandle = NULL;
3812 3812 cmd->cmd_arq_buf = NULL;
3813 3813 return (-1);
3814 3814 }
3815 3815
3816 3816 return (0);
3817 3817 }
3818 3818
3819 3819 static void
3820 3820 mptsas_kmem_cache_destructor(void *buf, void *cdrarg)
3821 3821 {
3822 3822 #ifndef __lock_lint
3823 3823 _NOTE(ARGUNUSED(cdrarg))
3824 3824 #endif
3825 3825 mptsas_cmd_t *cmd = buf;
3826 3826
3827 3827 NDBG4(("mptsas_kmem_cache_destructor"));
3828 3828
3829 3829 if (cmd->cmd_arqhandle) {
3830 3830 (void) ddi_dma_unbind_handle(cmd->cmd_arqhandle);
3831 3831 ddi_dma_free_handle(&cmd->cmd_arqhandle);
3832 3832 cmd->cmd_arqhandle = NULL;
3833 3833 }
3834 3834 if (cmd->cmd_arq_buf) {
3835 3835 scsi_free_consistent_buf(cmd->cmd_arq_buf);
3836 3836 cmd->cmd_arq_buf = NULL;
3837 3837 }
3838 3838 if (cmd->cmd_dmahandle) {
3839 3839 ddi_dma_free_handle(&cmd->cmd_dmahandle);
3840 3840 cmd->cmd_dmahandle = NULL;
3841 3841 }
3842 3842 }
3843 3843
3844 3844 static int
3845 3845 mptsas_cache_frames_constructor(void *buf, void *cdrarg, int kmflags)
3846 3846 {
3847 3847 mptsas_cache_frames_t *p = buf;
3848 3848 mptsas_t *mpt = cdrarg;
3849 3849 ddi_dma_attr_t frame_dma_attr;
3850 3850 size_t mem_size, alloc_len;
3851 3851 ddi_dma_cookie_t cookie;
3852 3852 uint_t ncookie;
3853 3853 int (*callback)(caddr_t) = (kmflags == KM_SLEEP)
3854 3854 ? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT;
3855 3855
3856 3856 frame_dma_attr = mpt->m_msg_dma_attr;
3857 3857 frame_dma_attr.dma_attr_align = 0x10;
3858 3858 frame_dma_attr.dma_attr_sgllen = 1;
3859 3859
3860 3860 if (ddi_dma_alloc_handle(mpt->m_dip, &frame_dma_attr, callback, NULL,
3861 3861 &p->m_dma_hdl) != DDI_SUCCESS) {
3862 3862 mptsas_log(mpt, CE_WARN, "Unable to allocate dma handle for"
3863 3863 " extra SGL.");
3864 3864 return (DDI_FAILURE);
3865 3865 }
3866 3866
3867 3867 mem_size = (mpt->m_max_request_frames - 1) * mpt->m_req_frame_size;
3868 3868
3869 3869 if (ddi_dma_mem_alloc(p->m_dma_hdl, mem_size, &mpt->m_dev_acc_attr,
3870 3870 DDI_DMA_CONSISTENT, callback, NULL, (caddr_t *)&p->m_frames_addr,
3871 3871 &alloc_len, &p->m_acc_hdl) != DDI_SUCCESS) {
3872 3872 ddi_dma_free_handle(&p->m_dma_hdl);
3873 3873 p->m_dma_hdl = NULL;
3874 3874 mptsas_log(mpt, CE_WARN, "Unable to allocate dma memory for"
3875 3875 " extra SGL.");
3876 3876 return (DDI_FAILURE);
3877 3877 }
3878 3878
3879 3879 if (ddi_dma_addr_bind_handle(p->m_dma_hdl, NULL, p->m_frames_addr,
3880 3880 alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, callback, NULL,
3881 3881 &cookie, &ncookie) != DDI_DMA_MAPPED) {
3882 3882 (void) ddi_dma_mem_free(&p->m_acc_hdl);
3883 3883 ddi_dma_free_handle(&p->m_dma_hdl);
3884 3884 p->m_dma_hdl = NULL;
3885 3885 mptsas_log(mpt, CE_WARN, "Unable to bind DMA resources for"
3886 3886 " extra SGL");
3887 3887 return (DDI_FAILURE);
3888 3888 }
3889 3889
3890 3890 /*
3891 3891 * Store the SGL memory address. This chip uses this
3892 3892 * address to dma to and from the driver. The second
3893 3893 * address is the address mpt uses to fill in the SGL.
3894 3894 */
3895 3895 p->m_phys_addr = cookie.dmac_address;
3896 3896
3897 3897 return (DDI_SUCCESS);
3898 3898 }
3899 3899
3900 3900 static void
3901 3901 mptsas_cache_frames_destructor(void *buf, void *cdrarg)
3902 3902 {
3903 3903 #ifndef __lock_lint
3904 3904 _NOTE(ARGUNUSED(cdrarg))
3905 3905 #endif
3906 3906 mptsas_cache_frames_t *p = buf;
3907 3907 if (p->m_dma_hdl != NULL) {
3908 3908 (void) ddi_dma_unbind_handle(p->m_dma_hdl);
3909 3909 (void) ddi_dma_mem_free(&p->m_acc_hdl);
3910 3910 ddi_dma_free_handle(&p->m_dma_hdl);
3911 3911 p->m_phys_addr = NULL;
3912 3912 p->m_frames_addr = NULL;
3913 3913 p->m_dma_hdl = NULL;
3914 3914 p->m_acc_hdl = NULL;
3915 3915 }
3916 3916
3917 3917 }
3918 3918
3919 3919 /*
3920 3920 * allocate and deallocate external pkt space (ie. not part of mptsas_cmd)
3921 3921 * for non-standard length cdb, pkt_private, status areas
3922 3922 * if allocation fails, then deallocate all external space and the pkt
3923 3923 */
3924 3924 /* ARGSUSED */
3925 3925 static int
3926 3926 mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd,
3927 3927 int cmdlen, int tgtlen, int statuslen, int kf)
3928 3928 {
3929 3929 caddr_t cdbp, scbp, tgt;
3930 3930 int (*callback)(caddr_t) = (kf == KM_SLEEP) ?
3931 3931 DDI_DMA_SLEEP : DDI_DMA_DONTWAIT;
3932 3932 struct scsi_address ap;
3933 3933 size_t senselength;
3934 3934 ddi_dma_attr_t ext_arq_dma_attr;
3935 3935 uint_t cookiec;
3936 3936
3937 3937 NDBG3(("mptsas_pkt_alloc_extern: "
3938 3938 "cmd=0x%p cmdlen=%d tgtlen=%d statuslen=%d kf=%x",
3939 3939 (void *)cmd, cmdlen, tgtlen, statuslen, kf));
3940 3940
3941 3941 tgt = cdbp = scbp = NULL;
3942 3942 cmd->cmd_scblen = statuslen;
3943 3943 cmd->cmd_privlen = (uchar_t)tgtlen;
3944 3944
3945 3945 if (cmdlen > sizeof (cmd->cmd_cdb)) {
3946 3946 if ((cdbp = kmem_zalloc((size_t)cmdlen, kf)) == NULL) {
3947 3947 goto fail;
3948 3948 }
3949 3949 cmd->cmd_pkt->pkt_cdbp = (opaque_t)cdbp;
3950 3950 cmd->cmd_flags |= CFLAG_CDBEXTERN;
3951 3951 }
3952 3952 if (tgtlen > PKT_PRIV_LEN) {
3953 3953 if ((tgt = kmem_zalloc((size_t)tgtlen, kf)) == NULL) {
3954 3954 goto fail;
3955 3955 }
3956 3956 cmd->cmd_flags |= CFLAG_PRIVEXTERN;
3957 3957 cmd->cmd_pkt->pkt_private = tgt;
3958 3958 }
3959 3959 if (statuslen > EXTCMDS_STATUS_SIZE) {
3960 3960 if ((scbp = kmem_zalloc((size_t)statuslen, kf)) == NULL) {
3961 3961 goto fail;
3962 3962 }
3963 3963 cmd->cmd_flags |= CFLAG_SCBEXTERN;
3964 3964 cmd->cmd_pkt->pkt_scbp = (opaque_t)scbp;
3965 3965
3966 3966 /* allocate sense data buf for DMA */
3967 3967
3968 3968 senselength = statuslen - MPTSAS_GET_ITEM_OFF(
3969 3969 struct scsi_arq_status, sts_sensedata);
3970 3970 cmd->cmd_rqslen = (uchar_t)senselength;
3971 3971
3972 3972 ap.a_hba_tran = mpt->m_tran;
3973 3973 ap.a_target = 0;
3974 3974 ap.a_lun = 0;
3975 3975
3976 3976 cmd->cmd_ext_arq_buf = scsi_alloc_consistent_buf(&ap,
3977 3977 (struct buf *)NULL, senselength, B_READ,
3978 3978 callback, NULL);
3979 3979
3980 3980 if (cmd->cmd_ext_arq_buf == NULL) {
3981 3981 goto fail;
3982 3982 }
3983 3983 /*
3984 3984 * allocate a extern arq handle and bind the buf
3985 3985 */
3986 3986 ext_arq_dma_attr = mpt->m_msg_dma_attr;
3987 3987 ext_arq_dma_attr.dma_attr_sgllen = 1;
3988 3988 if ((ddi_dma_alloc_handle(mpt->m_dip,
3989 3989 &ext_arq_dma_attr, callback,
3990 3990 NULL, &cmd->cmd_ext_arqhandle)) != DDI_SUCCESS) {
3991 3991 goto fail;
3992 3992 }
3993 3993
3994 3994 if (ddi_dma_buf_bind_handle(cmd->cmd_ext_arqhandle,
3995 3995 cmd->cmd_ext_arq_buf, (DDI_DMA_READ | DDI_DMA_CONSISTENT),
3996 3996 callback, NULL, &cmd->cmd_ext_arqcookie,
3997 3997 &cookiec)
3998 3998 != DDI_SUCCESS) {
3999 3999 goto fail;
4000 4000 }
4001 4001 cmd->cmd_flags |= CFLAG_EXTARQBUFVALID;
4002 4002 }
4003 4003 return (0);
4004 4004 fail:
4005 4005 mptsas_pkt_destroy_extern(mpt, cmd);
4006 4006 return (1);
4007 4007 }
4008 4008
4009 4009 /*
4010 4010 * deallocate external pkt space and deallocate the pkt
4011 4011 */
4012 4012 static void
4013 4013 mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd)
4014 4014 {
4015 4015 NDBG3(("mptsas_pkt_destroy_extern: cmd=0x%p", (void *)cmd));
4016 4016
4017 4017 if (cmd->cmd_flags & CFLAG_FREE) {
4018 4018 mptsas_log(mpt, CE_PANIC,
4019 4019 "mptsas_pkt_destroy_extern: freeing free packet");
4020 4020 _NOTE(NOT_REACHED)
4021 4021 /* NOTREACHED */
4022 4022 }
4023 4023 if (cmd->cmd_flags & CFLAG_CDBEXTERN) {
4024 4024 kmem_free(cmd->cmd_pkt->pkt_cdbp, (size_t)cmd->cmd_cdblen);
4025 4025 }
4026 4026 if (cmd->cmd_flags & CFLAG_SCBEXTERN) {
4027 4027 kmem_free(cmd->cmd_pkt->pkt_scbp, (size_t)cmd->cmd_scblen);
4028 4028 if (cmd->cmd_flags & CFLAG_EXTARQBUFVALID) {
4029 4029 (void) ddi_dma_unbind_handle(cmd->cmd_ext_arqhandle);
4030 4030 }
4031 4031 if (cmd->cmd_ext_arqhandle) {
4032 4032 ddi_dma_free_handle(&cmd->cmd_ext_arqhandle);
4033 4033 cmd->cmd_ext_arqhandle = NULL;
4034 4034 }
4035 4035 if (cmd->cmd_ext_arq_buf)
4036 4036 scsi_free_consistent_buf(cmd->cmd_ext_arq_buf);
4037 4037 }
4038 4038 if (cmd->cmd_flags & CFLAG_PRIVEXTERN) {
4039 4039 kmem_free(cmd->cmd_pkt->pkt_private, (size_t)cmd->cmd_privlen);
4040 4040 }
4041 4041 cmd->cmd_flags = CFLAG_FREE;
4042 4042 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd);
4043 4043 }
4044 4044
4045 4045 /*
4046 4046 * tran_sync_pkt(9E) - explicit DMA synchronization
4047 4047 */
4048 4048 /*ARGSUSED*/
4049 4049 static void
4050 4050 mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
4051 4051 {
4052 4052 mptsas_cmd_t *cmd = PKT2CMD(pkt);
4053 4053
4054 4054 NDBG3(("mptsas_scsi_sync_pkt: target=%d, pkt=0x%p",
4055 4055 ap->a_target, (void *)pkt));
4056 4056
4057 4057 if (cmd->cmd_dmahandle) {
4058 4058 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
4059 4059 (cmd->cmd_flags & CFLAG_DMASEND) ?
4060 4060 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU);
4061 4061 }
4062 4062 }
4063 4063
4064 4064 /*
4065 4065 * tran_dmafree(9E) - deallocate DMA resources allocated for command
4066 4066 */
4067 4067 /*ARGSUSED*/
4068 4068 static void
4069 4069 mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt)
4070 4070 {
4071 4071 mptsas_cmd_t *cmd = PKT2CMD(pkt);
4072 4072 mptsas_t *mpt = ADDR2MPT(ap);
4073 4073
4074 4074 NDBG3(("mptsas_scsi_dmafree: target=%d pkt=0x%p",
4075 4075 ap->a_target, (void *)pkt));
4076 4076
4077 4077 if (cmd->cmd_flags & CFLAG_DMAVALID) {
4078 4078 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle);
4079 4079 cmd->cmd_flags &= ~CFLAG_DMAVALID;
4080 4080 }
4081 4081
4082 4082 if (cmd->cmd_flags & CFLAG_EXTARQBUFVALID) {
4083 4083 (void) ddi_dma_unbind_handle(cmd->cmd_ext_arqhandle);
4084 4084 cmd->cmd_flags &= ~CFLAG_EXTARQBUFVALID;
4085 4085 }
4086 4086
4087 4087 mptsas_free_extra_sgl_frame(mpt, cmd);
4088 4088 }
4089 4089
4090 4090 static void
4091 4091 mptsas_pkt_comp(struct scsi_pkt *pkt, mptsas_cmd_t *cmd)
4092 4092 {
4093 4093 if ((cmd->cmd_flags & CFLAG_CMDIOPB) &&
4094 4094 (!(cmd->cmd_flags & CFLAG_DMASEND))) {
4095 4095 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
4096 4096 DDI_DMA_SYNC_FORCPU);
4097 4097 }
4098 4098 (*pkt->pkt_comp)(pkt);
4099 4099 }
4100 4100
4101 4101 static void
4102 4102 mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, uint32_t *control,
4103 4103 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl)
4104 4104 {
4105 4105 uint_t cookiec;
4106 4106 mptti_t *dmap;
4107 4107 uint32_t flags;
4108 4108 pMpi2SGESimple64_t sge;
4109 4109 pMpi2SGEChain64_t sgechain;
4110 4110 ASSERT(cmd->cmd_flags & CFLAG_DMAVALID);
4111 4111
4112 4112 /*
4113 4113 * Save the number of entries in the DMA
4114 4114 * Scatter/Gather list
4115 4115 */
4116 4116 cookiec = cmd->cmd_cookiec;
4117 4117
4118 4118 NDBG1(("mptsas_sge_setup: cookiec=%d", cookiec));
4119 4119
4120 4120 /*
4121 4121 * Set read/write bit in control.
4122 4122 */
4123 4123 if (cmd->cmd_flags & CFLAG_DMASEND) {
4124 4124 *control |= MPI2_SCSIIO_CONTROL_WRITE;
4125 4125 } else {
4126 4126 *control |= MPI2_SCSIIO_CONTROL_READ;
4127 4127 }
4128 4128
4129 4129 ddi_put32(acc_hdl, &frame->DataLength, cmd->cmd_dmacount);
4130 4130
4131 4131 /*
4132 4132 * We have 2 cases here. First where we can fit all the
4133 4133 * SG elements into the main frame, and the case
4134 4134 * where we can't.
4135 4135 * If we have more cookies than we can attach to a frame
4136 4136 * we will need to use a chain element to point
4137 4137 * a location of memory where the rest of the S/G
4138 4138 * elements reside.
4139 4139 */
4140 4140 if (cookiec <= MPTSAS_MAX_FRAME_SGES64(mpt)) {
4141 4141 dmap = cmd->cmd_sg;
4142 4142 sge = (pMpi2SGESimple64_t)(&frame->SGL);
4143 4143 while (cookiec--) {
4144 4144 ddi_put32(acc_hdl,
4145 4145 &sge->Address.Low, dmap->addr.address64.Low);
4146 4146 ddi_put32(acc_hdl,
4147 4147 &sge->Address.High, dmap->addr.address64.High);
4148 4148 ddi_put32(acc_hdl, &sge->FlagsLength,
4149 4149 dmap->count);
4150 4150 flags = ddi_get32(acc_hdl, &sge->FlagsLength);
4151 4151 flags |= ((uint32_t)
4152 4152 (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4153 4153 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4154 4154 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4155 4155 MPI2_SGE_FLAGS_SHIFT);
4156 4156
4157 4157 /*
4158 4158 * If this is the last cookie, we set the flags
4159 4159 * to indicate so
4160 4160 */
4161 4161 if (cookiec == 0) {
4162 4162 flags |=
4163 4163 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT
4164 4164 | MPI2_SGE_FLAGS_END_OF_BUFFER
4165 4165 | MPI2_SGE_FLAGS_END_OF_LIST) <<
4166 4166 MPI2_SGE_FLAGS_SHIFT);
4167 4167 }
4168 4168 if (cmd->cmd_flags & CFLAG_DMASEND) {
4169 4169 flags |= (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4170 4170 MPI2_SGE_FLAGS_SHIFT);
4171 4171 } else {
4172 4172 flags |= (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4173 4173 MPI2_SGE_FLAGS_SHIFT);
4174 4174 }
4175 4175 ddi_put32(acc_hdl, &sge->FlagsLength, flags);
4176 4176 dmap++;
4177 4177 sge++;
4178 4178 }
4179 4179 } else {
4180 4180 /*
4181 4181 * Hereby we start to deal with multiple frames.
4182 4182 * The process is as follows:
4183 4183 * 1. Determine how many frames are needed for SGL element
4184 4184 * storage; Note that all frames are stored in contiguous
4185 4185 * memory space and in 64-bit DMA mode each element is
4186 4186 * 3 double-words (12 bytes) long.
4187 4187 * 2. Fill up the main frame. We need to do this separately
4188 4188 * since it contains the SCSI IO request header and needs
4189 4189 * dedicated processing. Note that the last 4 double-words
4190 4190 * of the SCSI IO header is for SGL element storage
4191 4191 * (MPI2_SGE_IO_UNION).
4192 4192 * 3. Fill the chain element in the main frame, so the DMA
4193 4193 * engine can use the following frames.
4194 4194 * 4. Enter a loop to fill the remaining frames. Note that the
4195 4195 * last frame contains no chain element. The remaining
4196 4196 * frames go into the mpt SGL buffer allocated on the fly,
4197 4197 * not immediately following the main message frame, as in
4198 4198 * Gen1.
4199 4199 * Some restrictions:
4200 4200 * 1. For 64-bit DMA, the simple element and chain element
4201 4201 * are both of 3 double-words (12 bytes) in size, even
4202 4202 * though all frames are stored in the first 4G of mem
4203 4203 * range and the higher 32-bits of the address are always 0.
4204 4204 * 2. On some controllers (like the 1064/1068), a frame can
4205 4205 * hold SGL elements with the last 1 or 2 double-words
4206 4206 * (4 or 8 bytes) un-used. On these controllers, we should
4207 4207 * recognize that there's not enough room for another SGL
4208 4208 * element and move the sge pointer to the next frame.
4209 4209 */
4210 4210 int i, j, k, l, frames, sgemax;
4211 4211 int temp;
4212 4212 uint8_t chainflags;
4213 4213 uint16_t chainlength;
4214 4214 mptsas_cache_frames_t *p;
4215 4215
4216 4216 /*
4217 4217 * Sgemax is the number of SGE's that will fit
4218 4218 * each extra frame and frames is total
4219 4219 * number of frames we'll need. 1 sge entry per
4220 4220 * frame is reseverd for the chain element thus the -1 below.
4221 4221 */
4222 4222 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_SGE_SIMPLE64))
4223 4223 - 1);
4224 4224 temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax;
4225 4225
4226 4226 /*
4227 4227 * A little check to see if we need to round up the number
4228 4228 * of frames we need
4229 4229 */
4230 4230 if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp *
4231 4231 sgemax) > 1) {
4232 4232 frames = (temp + 1);
4233 4233 } else {
4234 4234 frames = temp;
4235 4235 }
4236 4236 dmap = cmd->cmd_sg;
4237 4237 sge = (pMpi2SGESimple64_t)(&frame->SGL);
4238 4238
4239 4239 /*
4240 4240 * First fill in the main frame
4241 4241 */
4242 4242 for (j = 1; j < MPTSAS_MAX_FRAME_SGES64(mpt); j++) {
4243 4243 ddi_put32(acc_hdl, &sge->Address.Low,
4244 4244 dmap->addr.address64.Low);
4245 4245 ddi_put32(acc_hdl, &sge->Address.High,
4246 4246 dmap->addr.address64.High);
4247 4247 ddi_put32(acc_hdl, &sge->FlagsLength, dmap->count);
4248 4248 flags = ddi_get32(acc_hdl, &sge->FlagsLength);
4249 4249 flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4250 4250 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4251 4251 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4252 4252 MPI2_SGE_FLAGS_SHIFT);
4253 4253
4254 4254 /*
4255 4255 * If this is the last SGE of this frame
4256 4256 * we set the end of list flag
4257 4257 */
4258 4258 if (j == (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) {
4259 4259 flags |= ((uint32_t)
4260 4260 (MPI2_SGE_FLAGS_LAST_ELEMENT) <<
4261 4261 MPI2_SGE_FLAGS_SHIFT);
4262 4262 }
4263 4263 if (cmd->cmd_flags & CFLAG_DMASEND) {
4264 4264 flags |=
4265 4265 (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4266 4266 MPI2_SGE_FLAGS_SHIFT);
4267 4267 } else {
4268 4268 flags |=
4269 4269 (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4270 4270 MPI2_SGE_FLAGS_SHIFT);
4271 4271 }
4272 4272 ddi_put32(acc_hdl, &sge->FlagsLength, flags);
4273 4273 dmap++;
4274 4274 sge++;
4275 4275 }
4276 4276
4277 4277 /*
4278 4278 * Fill in the chain element in the main frame.
4279 4279 * About calculation on ChainOffset:
4280 4280 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes)
4281 4281 * in the end reserved for SGL element storage
4282 4282 * (MPI2_SGE_IO_UNION); we should count it in our
4283 4283 * calculation. See its definition in the header file.
4284 4284 * 2. Constant j is the counter of the current SGL element
4285 4285 * that will be processed, and (j - 1) is the number of
4286 4286 * SGL elements that have been processed (stored in the
4287 4287 * main frame).
4288 4288 * 3. ChainOffset value should be in units of double-words (4
4289 4289 * bytes) so the last value should be divided by 4.
4290 4290 */
4291 4291 ddi_put8(acc_hdl, &frame->ChainOffset,
4292 4292 (sizeof (MPI2_SCSI_IO_REQUEST) -
4293 4293 sizeof (MPI2_SGE_IO_UNION) +
4294 4294 (j - 1) * sizeof (MPI2_SGE_SIMPLE64)) >> 2);
4295 4295 sgechain = (pMpi2SGEChain64_t)sge;
4296 4296 chainflags = (MPI2_SGE_FLAGS_CHAIN_ELEMENT |
4297 4297 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4298 4298 MPI2_SGE_FLAGS_64_BIT_ADDRESSING);
4299 4299 ddi_put8(acc_hdl, &sgechain->Flags, chainflags);
4300 4300
4301 4301 /*
4302 4302 * The size of the next frame is the accurate size of space
4303 4303 * (in bytes) used to store the SGL elements. j is the counter
4304 4304 * of SGL elements. (j - 1) is the number of SGL elements that
4305 4305 * have been processed (stored in frames).
4306 4306 */
4307 4307 if (frames >= 2) {
4308 4308 chainlength = mpt->m_req_frame_size /
4309 4309 sizeof (MPI2_SGE_SIMPLE64) *
4310 4310 sizeof (MPI2_SGE_SIMPLE64);
4311 4311 } else {
4312 4312 chainlength = ((cookiec - (j - 1)) *
4313 4313 sizeof (MPI2_SGE_SIMPLE64));
4314 4314 }
4315 4315
4316 4316 p = cmd->cmd_extra_frames;
4317 4317
4318 4318 ddi_put16(acc_hdl, &sgechain->Length, chainlength);
4319 4319 ddi_put32(acc_hdl, &sgechain->Address.Low,
4320 4320 p->m_phys_addr);
4321 4321 /* SGL is allocated in the first 4G mem range */
4322 4322 ddi_put32(acc_hdl, &sgechain->Address.High, 0);
4323 4323
4324 4324 /*
4325 4325 * If there are more than 2 frames left we have to
4326 4326 * fill in the next chain offset to the location of
4327 4327 * the chain element in the next frame.
4328 4328 * sgemax is the number of simple elements in an extra
4329 4329 * frame. Note that the value NextChainOffset should be
4330 4330 * in double-words (4 bytes).
4331 4331 */
4332 4332 if (frames >= 2) {
4333 4333 ddi_put8(acc_hdl, &sgechain->NextChainOffset,
4334 4334 (sgemax * sizeof (MPI2_SGE_SIMPLE64)) >> 2);
4335 4335 } else {
4336 4336 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 0);
4337 4337 }
4338 4338
4339 4339 /*
4340 4340 * Jump to next frame;
4341 4341 * Starting here, chain buffers go into the per command SGL.
4342 4342 * This buffer is allocated when chain buffers are needed.
4343 4343 */
4344 4344 sge = (pMpi2SGESimple64_t)p->m_frames_addr;
4345 4345 i = cookiec;
4346 4346
4347 4347 /*
4348 4348 * Start filling in frames with SGE's. If we
4349 4349 * reach the end of frame and still have SGE's
4350 4350 * to fill we need to add a chain element and
4351 4351 * use another frame. j will be our counter
4352 4352 * for what cookie we are at and i will be
4353 4353 * the total cookiec. k is the current frame
4354 4354 */
4355 4355 for (k = 1; k <= frames; k++) {
4356 4356 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) {
4357 4357
4358 4358 /*
4359 4359 * If we have reached the end of frame
4360 4360 * and we have more SGE's to fill in
4361 4361 * we have to fill the final entry
4362 4362 * with a chain element and then
4363 4363 * continue to the next frame
4364 4364 */
4365 4365 if ((l == (sgemax + 1)) && (k != frames)) {
4366 4366 sgechain = (pMpi2SGEChain64_t)sge;
4367 4367 j--;
4368 4368 chainflags = (
4369 4369 MPI2_SGE_FLAGS_CHAIN_ELEMENT |
4370 4370 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4371 4371 MPI2_SGE_FLAGS_64_BIT_ADDRESSING);
4372 4372 ddi_put8(p->m_acc_hdl,
4373 4373 &sgechain->Flags, chainflags);
4374 4374 /*
4375 4375 * k is the frame counter and (k + 1)
4376 4376 * is the number of the next frame.
4377 4377 * Note that frames are in contiguous
4378 4378 * memory space.
4379 4379 */
4380 4380 ddi_put32(p->m_acc_hdl,
4381 4381 &sgechain->Address.Low,
4382 4382 (p->m_phys_addr +
4383 4383 (mpt->m_req_frame_size * k)));
4384 4384 ddi_put32(p->m_acc_hdl,
4385 4385 &sgechain->Address.High, 0);
4386 4386
4387 4387 /*
4388 4388 * If there are more than 2 frames left
4389 4389 * we have to next chain offset to
4390 4390 * the location of the chain element
4391 4391 * in the next frame and fill in the
4392 4392 * length of the next chain
4393 4393 */
4394 4394 if ((frames - k) >= 2) {
4395 4395 ddi_put8(p->m_acc_hdl,
4396 4396 &sgechain->NextChainOffset,
4397 4397 (sgemax *
4398 4398 sizeof (MPI2_SGE_SIMPLE64))
4399 4399 >> 2);
4400 4400 ddi_put16(p->m_acc_hdl,
4401 4401 &sgechain->Length,
4402 4402 mpt->m_req_frame_size /
4403 4403 sizeof (MPI2_SGE_SIMPLE64) *
4404 4404 sizeof (MPI2_SGE_SIMPLE64));
4405 4405 } else {
4406 4406 /*
4407 4407 * This is the last frame. Set
4408 4408 * the NextChainOffset to 0 and
4409 4409 * Length is the total size of
4410 4410 * all remaining simple elements
4411 4411 */
4412 4412 ddi_put8(p->m_acc_hdl,
4413 4413 &sgechain->NextChainOffset,
4414 4414 0);
4415 4415 ddi_put16(p->m_acc_hdl,
4416 4416 &sgechain->Length,
4417 4417 (cookiec - j) *
4418 4418 sizeof (MPI2_SGE_SIMPLE64));
4419 4419 }
4420 4420
4421 4421 /* Jump to the next frame */
4422 4422 sge = (pMpi2SGESimple64_t)
4423 4423 ((char *)p->m_frames_addr +
4424 4424 (int)mpt->m_req_frame_size * k);
4425 4425
4426 4426 continue;
4427 4427 }
4428 4428
4429 4429 ddi_put32(p->m_acc_hdl,
4430 4430 &sge->Address.Low,
4431 4431 dmap->addr.address64.Low);
4432 4432 ddi_put32(p->m_acc_hdl,
4433 4433 &sge->Address.High,
4434 4434 dmap->addr.address64.High);
4435 4435 ddi_put32(p->m_acc_hdl,
4436 4436 &sge->FlagsLength, dmap->count);
4437 4437 flags = ddi_get32(p->m_acc_hdl,
4438 4438 &sge->FlagsLength);
4439 4439 flags |= ((uint32_t)(
4440 4440 MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4441 4441 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4442 4442 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4443 4443 MPI2_SGE_FLAGS_SHIFT);
4444 4444
4445 4445 /*
4446 4446 * If we are at the end of the frame and
4447 4447 * there is another frame to fill in
4448 4448 * we set the last simple element as last
4449 4449 * element
4450 4450 */
4451 4451 if ((l == sgemax) && (k != frames)) {
4452 4452 flags |= ((uint32_t)
4453 4453 (MPI2_SGE_FLAGS_LAST_ELEMENT) <<
4454 4454 MPI2_SGE_FLAGS_SHIFT);
4455 4455 }
4456 4456
4457 4457 /*
4458 4458 * If this is the final cookie we
4459 4459 * indicate it by setting the flags
4460 4460 */
4461 4461 if (j == i) {
4462 4462 flags |= ((uint32_t)
4463 4463 (MPI2_SGE_FLAGS_LAST_ELEMENT |
4464 4464 MPI2_SGE_FLAGS_END_OF_BUFFER |
4465 4465 MPI2_SGE_FLAGS_END_OF_LIST) <<
4466 4466 MPI2_SGE_FLAGS_SHIFT);
4467 4467 }
4468 4468 if (cmd->cmd_flags & CFLAG_DMASEND) {
4469 4469 flags |=
4470 4470 (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4471 4471 MPI2_SGE_FLAGS_SHIFT);
4472 4472 } else {
4473 4473 flags |=
4474 4474 (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4475 4475 MPI2_SGE_FLAGS_SHIFT);
4476 4476 }
4477 4477 ddi_put32(p->m_acc_hdl,
4478 4478 &sge->FlagsLength, flags);
4479 4479 dmap++;
4480 4480 sge++;
4481 4481 }
4482 4482 }
4483 4483
4484 4484 /*
4485 4485 * Sync DMA with the chain buffers that were just created
4486 4486 */
4487 4487 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
4488 4488 }
4489 4489 }
4490 4490
4491 4491 /*
4492 4492 * Interrupt handling
4493 4493 * Utility routine. Poll for status of a command sent to HBA
4494 4494 * without interrupts (a FLAG_NOINTR command).
4495 4495 */
4496 4496 int
4497 4497 mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime)
4498 4498 {
4499 4499 int rval = TRUE;
4500 4500
4501 4501 NDBG5(("mptsas_poll: cmd=0x%p", (void *)poll_cmd));
4502 4502
4503 4503 if ((poll_cmd->cmd_flags & CFLAG_TM_CMD) == 0) {
4504 4504 mptsas_restart_hba(mpt);
4505 4505 }
4506 4506
4507 4507 /*
4508 4508 * Wait, using drv_usecwait(), long enough for the command to
4509 4509 * reasonably return from the target if the target isn't
4510 4510 * "dead". A polled command may well be sent from scsi_poll, and
4511 4511 * there are retries built in to scsi_poll if the transport
4512 4512 * accepted the packet (TRAN_ACCEPT). scsi_poll waits 1 second
4513 4513 * and retries the transport up to scsi_poll_busycnt times
4514 4514 * (currently 60) if
4515 4515 * 1. pkt_reason is CMD_INCOMPLETE and pkt_state is 0, or
4516 4516 * 2. pkt_reason is CMD_CMPLT and *pkt_scbp has STATUS_BUSY
4517 4517 *
4518 4518 * limit the waiting to avoid a hang in the event that the
4519 4519 * cmd never gets started but we are still receiving interrupts
4520 4520 */
4521 4521 while (!(poll_cmd->cmd_flags & CFLAG_FINISHED)) {
4522 4522 if (mptsas_wait_intr(mpt, polltime) == FALSE) {
4523 4523 NDBG5(("mptsas_poll: command incomplete"));
4524 4524 rval = FALSE;
4525 4525 break;
4526 4526 }
4527 4527 }
4528 4528
4529 4529 if (rval == FALSE) {
4530 4530
4531 4531 /*
4532 4532 * this isn't supposed to happen, the hba must be wedged
4533 4533 * Mark this cmd as a timeout.
4534 4534 */
4535 4535 mptsas_set_pkt_reason(mpt, poll_cmd, CMD_TIMEOUT,
4536 4536 (STAT_TIMEOUT|STAT_ABORTED));
4537 4537
4538 4538 if (poll_cmd->cmd_queued == FALSE) {
4539 4539
4540 4540 NDBG5(("mptsas_poll: not on waitq"));
4541 4541
4542 4542 poll_cmd->cmd_pkt->pkt_state |=
4543 4543 (STATE_GOT_BUS|STATE_GOT_TARGET|STATE_SENT_CMD);
4544 4544 } else {
4545 4545
4546 4546 /* find and remove it from the waitq */
4547 4547 NDBG5(("mptsas_poll: delete from waitq"));
4548 4548 mptsas_waitq_delete(mpt, poll_cmd);
4549 4549 }
4550 4550
4551 4551 }
4552 4552 mptsas_fma_check(mpt, poll_cmd);
4553 4553 NDBG5(("mptsas_poll: done"));
4554 4554 return (rval);
4555 4555 }
4556 4556
4557 4557 /*
4558 4558 * Used for polling cmds and TM function
4559 4559 */
4560 4560 static int
4561 4561 mptsas_wait_intr(mptsas_t *mpt, int polltime)
4562 4562 {
4563 4563 int cnt;
4564 4564 pMpi2ReplyDescriptorsUnion_t reply_desc_union;
4565 4565 uint32_t int_mask;
4566 4566
4567 4567 NDBG5(("mptsas_wait_intr"));
4568 4568
4569 4569 mpt->m_polled_intr = 1;
4570 4570
4571 4571 /*
4572 4572 * Get the current interrupt mask and disable interrupts. When
4573 4573 * re-enabling ints, set mask to saved value.
4574 4574 */
4575 4575 int_mask = ddi_get32(mpt->m_datap, &mpt->m_reg->HostInterruptMask);
4576 4576 MPTSAS_DISABLE_INTR(mpt);
4577 4577
4578 4578 /*
4579 4579 * Keep polling for at least (polltime * 1000) seconds
4580 4580 */
4581 4581 for (cnt = 0; cnt < polltime; cnt++) {
4582 4582 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
4583 4583 DDI_DMA_SYNC_FORCPU);
4584 4584
4585 4585 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t)
4586 4586 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index);
4587 4587
4588 4588 if (ddi_get32(mpt->m_acc_post_queue_hdl,
4589 4589 &reply_desc_union->Words.Low) == 0xFFFFFFFF ||
4590 4590 ddi_get32(mpt->m_acc_post_queue_hdl,
4591 4591 &reply_desc_union->Words.High) == 0xFFFFFFFF) {
4592 4592 drv_usecwait(1000);
4593 4593 continue;
4594 4594 }
4595 4595
4596 4596 /*
4597 4597 * The reply is valid, process it according to its
4598 4598 * type.
4599 4599 */
4600 4600 mptsas_process_intr(mpt, reply_desc_union);
4601 4601
4602 4602 if (++mpt->m_post_index == mpt->m_post_queue_depth) {
4603 4603 mpt->m_post_index = 0;
4604 4604 }
4605 4605
4606 4606 /*
4607 4607 * Update the global reply index
4608 4608 */
4609 4609 ddi_put32(mpt->m_datap,
4610 4610 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index);
4611 4611 mpt->m_polled_intr = 0;
4612 4612
4613 4613 /*
4614 4614 * Re-enable interrupts and quit.
4615 4615 */
4616 4616 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask,
4617 4617 int_mask);
4618 4618 return (TRUE);
4619 4619
4620 4620 }
4621 4621
4622 4622 /*
4623 4623 * Clear polling flag, re-enable interrupts and quit.
4624 4624 */
4625 4625 mpt->m_polled_intr = 0;
4626 4626 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, int_mask);
4627 4627 return (FALSE);
4628 4628 }
4629 4629
4630 4630 static void
4631 4631 mptsas_handle_scsi_io_success(mptsas_t *mpt,
4632 4632 pMpi2ReplyDescriptorsUnion_t reply_desc)
4633 4633 {
4634 4634 pMpi2SCSIIOSuccessReplyDescriptor_t scsi_io_success;
4635 4635 uint16_t SMID;
4636 4636 mptsas_slots_t *slots = mpt->m_active;
4637 4637 mptsas_cmd_t *cmd = NULL;
4638 4638 struct scsi_pkt *pkt;
4639 4639
4640 4640 ASSERT(mutex_owned(&mpt->m_mutex));
4641 4641
4642 4642 scsi_io_success = (pMpi2SCSIIOSuccessReplyDescriptor_t)reply_desc;
4643 4643 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &scsi_io_success->SMID);
4644 4644
4645 4645 /*
4646 4646 * This is a success reply so just complete the IO. First, do a sanity
4647 4647 * check on the SMID. The final slot is used for TM requests, which
4648 4648 * would not come into this reply handler.
4649 4649 */
4650 4650 if ((SMID == 0) || (SMID > slots->m_n_slots)) {
4651 4651 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of %d\n",
4652 4652 SMID);
4653 4653 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
4654 4654 return;
4655 4655 }
4656 4656
4657 4657 cmd = slots->m_slot[SMID];
4658 4658
4659 4659 /*
4660 4660 * print warning and return if the slot is empty
4661 4661 */
4662 4662 if (cmd == NULL) {
4663 4663 mptsas_log(mpt, CE_WARN, "?NULL command for successful SCSI IO "
4664 4664 "in slot %d", SMID);
4665 4665 return;
4666 4666 }
4667 4667
4668 4668 pkt = CMD2PKT(cmd);
4669 4669 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | STATE_SENT_CMD |
4670 4670 STATE_GOT_STATUS);
4671 4671 if (cmd->cmd_flags & CFLAG_DMAVALID) {
4672 4672 pkt->pkt_state |= STATE_XFERRED_DATA;
4673 4673 }
4674 4674 pkt->pkt_resid = 0;
4675 4675
4676 4676 if (cmd->cmd_flags & CFLAG_PASSTHRU) {
4677 4677 cmd->cmd_flags |= CFLAG_FINISHED;
4678 4678 cv_broadcast(&mpt->m_passthru_cv);
4679 4679 return;
4680 4680 } else {
4681 4681 mptsas_remove_cmd(mpt, cmd);
4682 4682 }
4683 4683
4684 4684 if (cmd->cmd_flags & CFLAG_RETRY) {
4685 4685 /*
4686 4686 * The target returned QFULL or busy, do not add tihs
4687 4687 * pkt to the doneq since the hba will retry
4688 4688 * this cmd.
4689 4689 *
4690 4690 * The pkt has already been resubmitted in
4691 4691 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error().
4692 4692 * Remove this cmd_flag here.
4693 4693 */
4694 4694 cmd->cmd_flags &= ~CFLAG_RETRY;
4695 4695 } else {
4696 4696 mptsas_doneq_add(mpt, cmd);
4697 4697 }
4698 4698 }
4699 4699
4700 4700 static void
4701 4701 mptsas_handle_address_reply(mptsas_t *mpt,
4702 4702 pMpi2ReplyDescriptorsUnion_t reply_desc)
4703 4703 {
4704 4704 pMpi2AddressReplyDescriptor_t address_reply;
4705 4705 pMPI2DefaultReply_t reply;
4706 4706 mptsas_fw_diagnostic_buffer_t *pBuffer;
4707 4707 uint32_t reply_addr;
4708 4708 uint16_t SMID, iocstatus;
4709 4709 mptsas_slots_t *slots = mpt->m_active;
4710 4710 mptsas_cmd_t *cmd = NULL;
4711 4711 uint8_t function, buffer_type;
4712 4712 m_replyh_arg_t *args;
4713 4713 int reply_frame_no;
4714 4714
4715 4715 ASSERT(mutex_owned(&mpt->m_mutex));
4716 4716
4717 4717 address_reply = (pMpi2AddressReplyDescriptor_t)reply_desc;
4718 4718 reply_addr = ddi_get32(mpt->m_acc_post_queue_hdl,
4719 4719 &address_reply->ReplyFrameAddress);
4720 4720 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &address_reply->SMID);
4721 4721
4722 4722 /*
4723 4723 * If reply frame is not in the proper range we should ignore this
4724 4724 * message and exit the interrupt handler.
4725 4725 */
4726 4726 if ((reply_addr < mpt->m_reply_frame_dma_addr) ||
4727 4727 (reply_addr >= (mpt->m_reply_frame_dma_addr +
4728 4728 (mpt->m_reply_frame_size * mpt->m_max_replies))) ||
4729 4729 ((reply_addr - mpt->m_reply_frame_dma_addr) %
4730 4730 mpt->m_reply_frame_size != 0)) {
4731 4731 mptsas_log(mpt, CE_WARN, "?Received invalid reply frame "
4732 4732 "address 0x%x\n", reply_addr);
4733 4733 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
4734 4734 return;
4735 4735 }
4736 4736
4737 4737 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
4738 4738 DDI_DMA_SYNC_FORCPU);
4739 4739 reply = (pMPI2DefaultReply_t)(mpt->m_reply_frame + (reply_addr -
4740 4740 mpt->m_reply_frame_dma_addr));
4741 4741 function = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->Function);
4742 4742
4743 4743 /*
4744 4744 * don't get slot information and command for events since these values
4745 4745 * don't exist
4746 4746 */
4747 4747 if ((function != MPI2_FUNCTION_EVENT_NOTIFICATION) &&
4748 4748 (function != MPI2_FUNCTION_DIAG_BUFFER_POST)) {
4749 4749 /*
4750 4750 * This could be a TM reply, which use the last allocated SMID,
4751 4751 * so allow for that.
4752 4752 */
4753 4753 if ((SMID == 0) || (SMID > (slots->m_n_slots + 1))) {
4754 4754 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of "
4755 4755 "%d\n", SMID);
4756 4756 ddi_fm_service_impact(mpt->m_dip,
4757 4757 DDI_SERVICE_UNAFFECTED);
4758 4758 return;
4759 4759 }
4760 4760
4761 4761 cmd = slots->m_slot[SMID];
4762 4762
4763 4763 /*
4764 4764 * print warning and return if the slot is empty
4765 4765 */
4766 4766 if (cmd == NULL) {
4767 4767 mptsas_log(mpt, CE_WARN, "?NULL command for address "
4768 4768 "reply in slot %d", SMID);
4769 4769 return;
4770 4770 }
4771 4771 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
4772 4772 (cmd->cmd_flags & CFLAG_CONFIG) ||
4773 4773 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
4774 4774 cmd->cmd_rfm = reply_addr;
4775 4775 cmd->cmd_flags |= CFLAG_FINISHED;
4776 4776 cv_broadcast(&mpt->m_passthru_cv);
4777 4777 cv_broadcast(&mpt->m_config_cv);
4778 4778 cv_broadcast(&mpt->m_fw_diag_cv);
4779 4779 return;
4780 4780 } else if (!(cmd->cmd_flags & CFLAG_FW_CMD)) {
4781 4781 mptsas_remove_cmd(mpt, cmd);
4782 4782 }
4783 4783 NDBG31(("\t\tmptsas_process_intr: slot=%d", SMID));
4784 4784 }
4785 4785 /*
4786 4786 * Depending on the function, we need to handle
4787 4787 * the reply frame (and cmd) differently.
4788 4788 */
4789 4789 switch (function) {
4790 4790 case MPI2_FUNCTION_SCSI_IO_REQUEST:
4791 4791 mptsas_check_scsi_io_error(mpt, (pMpi2SCSIIOReply_t)reply, cmd);
4792 4792 break;
4793 4793 case MPI2_FUNCTION_SCSI_TASK_MGMT:
4794 4794 cmd->cmd_rfm = reply_addr;
4795 4795 mptsas_check_task_mgt(mpt, (pMpi2SCSIManagementReply_t)reply,
4796 4796 cmd);
4797 4797 break;
4798 4798 case MPI2_FUNCTION_FW_DOWNLOAD:
4799 4799 cmd->cmd_flags |= CFLAG_FINISHED;
4800 4800 cv_signal(&mpt->m_fw_cv);
4801 4801 break;
4802 4802 case MPI2_FUNCTION_EVENT_NOTIFICATION:
4803 4803 reply_frame_no = (reply_addr - mpt->m_reply_frame_dma_addr) /
4804 4804 mpt->m_reply_frame_size;
4805 4805 args = &mpt->m_replyh_args[reply_frame_no];
4806 4806 args->mpt = (void *)mpt;
4807 4807 args->rfm = reply_addr;
4808 4808
4809 4809 /*
4810 4810 * Record the event if its type is enabled in
4811 4811 * this mpt instance by ioctl.
4812 4812 */
4813 4813 mptsas_record_event(args);
4814 4814
4815 4815 /*
4816 4816 * Handle time critical events
4817 4817 * NOT_RESPONDING/ADDED only now
4818 4818 */
4819 4819 if (mptsas_handle_event_sync(args) == DDI_SUCCESS) {
4820 4820 /*
4821 4821 * Would not return main process,
4822 4822 * just let taskq resolve ack action
4823 4823 * and ack would be sent in taskq thread
4824 4824 */
4825 4825 NDBG20(("send mptsas_handle_event_sync success"));
4826 4826 }
4827 4827
4828 4828 if (mpt->m_in_reset) {
4829 4829 NDBG20(("dropping event received during reset"));
4830 4830 return;
4831 4831 }
4832 4832
4833 4833 if ((ddi_taskq_dispatch(mpt->m_event_taskq, mptsas_handle_event,
4834 4834 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) {
4835 4835 mptsas_log(mpt, CE_WARN, "No memory available"
4836 4836 "for dispatch taskq");
4837 4837 /*
4838 4838 * Return the reply frame to the free queue.
4839 4839 */
4840 4840 ddi_put32(mpt->m_acc_free_queue_hdl,
4841 4841 &((uint32_t *)(void *)
4842 4842 mpt->m_free_queue)[mpt->m_free_index], reply_addr);
4843 4843 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
4844 4844 DDI_DMA_SYNC_FORDEV);
4845 4845 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
4846 4846 mpt->m_free_index = 0;
4847 4847 }
4848 4848
4849 4849 ddi_put32(mpt->m_datap,
4850 4850 &mpt->m_reg->ReplyFreeHostIndex, mpt->m_free_index);
4851 4851 }
4852 4852 return;
4853 4853 case MPI2_FUNCTION_DIAG_BUFFER_POST:
4854 4854 /*
4855 4855 * If SMID is 0, this implies that the reply is due to a
4856 4856 * release function with a status that the buffer has been
4857 4857 * released. Set the buffer flags accordingly.
4858 4858 */
4859 4859 if (SMID == 0) {
4860 4860 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
4861 4861 &reply->IOCStatus);
4862 4862 buffer_type = ddi_get8(mpt->m_acc_reply_frame_hdl,
4863 4863 &(((pMpi2DiagBufferPostReply_t)reply)->BufferType));
4864 4864 if (iocstatus == MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED) {
4865 4865 pBuffer =
4866 4866 &mpt->m_fw_diag_buffer_list[buffer_type];
4867 4867 pBuffer->valid_data = TRUE;
4868 4868 pBuffer->owned_by_firmware = FALSE;
4869 4869 pBuffer->immediate = FALSE;
4870 4870 }
4871 4871 } else {
4872 4872 /*
4873 4873 * Normal handling of diag post reply with SMID.
4874 4874 */
4875 4875 cmd = slots->m_slot[SMID];
4876 4876
4877 4877 /*
4878 4878 * print warning and return if the slot is empty
4879 4879 */
4880 4880 if (cmd == NULL) {
4881 4881 mptsas_log(mpt, CE_WARN, "?NULL command for "
4882 4882 "address reply in slot %d", SMID);
4883 4883 return;
4884 4884 }
4885 4885 cmd->cmd_rfm = reply_addr;
4886 4886 cmd->cmd_flags |= CFLAG_FINISHED;
4887 4887 cv_broadcast(&mpt->m_fw_diag_cv);
4888 4888 }
4889 4889 return;
4890 4890 default:
4891 4891 mptsas_log(mpt, CE_WARN, "Unknown function 0x%x ", function);
4892 4892 break;
4893 4893 }
4894 4894
4895 4895 /*
4896 4896 * Return the reply frame to the free queue.
4897 4897 */
4898 4898 ddi_put32(mpt->m_acc_free_queue_hdl,
4899 4899 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
4900 4900 reply_addr);
4901 4901 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
4902 4902 DDI_DMA_SYNC_FORDEV);
4903 4903 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
4904 4904 mpt->m_free_index = 0;
4905 4905 }
4906 4906 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
4907 4907 mpt->m_free_index);
4908 4908
4909 4909 if (cmd->cmd_flags & CFLAG_FW_CMD)
4910 4910 return;
4911 4911
4912 4912 if (cmd->cmd_flags & CFLAG_RETRY) {
4913 4913 /*
4914 4914 * The target returned QFULL or busy, do not add tihs
4915 4915 * pkt to the doneq since the hba will retry
4916 4916 * this cmd.
4917 4917 *
4918 4918 * The pkt has already been resubmitted in
4919 4919 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error().
4920 4920 * Remove this cmd_flag here.
4921 4921 */
4922 4922 cmd->cmd_flags &= ~CFLAG_RETRY;
4923 4923 } else {
4924 4924 mptsas_doneq_add(mpt, cmd);
4925 4925 }
4926 4926 }
4927 4927
4928 4928 static void
4929 4929 mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply,
4930 4930 mptsas_cmd_t *cmd)
4931 4931 {
4932 4932 uint8_t scsi_status, scsi_state;
4933 4933 uint16_t ioc_status;
4934 4934 uint32_t xferred, sensecount, responsedata, loginfo = 0;
4935 4935 struct scsi_pkt *pkt;
4936 4936 struct scsi_arq_status *arqstat;
4937 4937 struct buf *bp;
4938 4938 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
4939 4939 uint8_t *sensedata = NULL;
4940 4940
4941 4941 if ((cmd->cmd_flags & (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) ==
4942 4942 (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) {
4943 4943 bp = cmd->cmd_ext_arq_buf;
4944 4944 } else {
4945 4945 bp = cmd->cmd_arq_buf;
4946 4946 }
4947 4947
4948 4948 scsi_status = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIStatus);
4949 4949 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus);
4950 4950 scsi_state = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIState);
4951 4951 xferred = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->TransferCount);
4952 4952 sensecount = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->SenseCount);
4953 4953 responsedata = ddi_get32(mpt->m_acc_reply_frame_hdl,
4954 4954 &reply->ResponseInfo);
4955 4955
4956 4956 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
4957 4957 loginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
4958 4958 &reply->IOCLogInfo);
4959 4959 mptsas_log(mpt, CE_NOTE,
4960 4960 "?Log info 0x%x received for target %d.\n"
4961 4961 "\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x",
4962 4962 loginfo, Tgt(cmd), scsi_status, ioc_status,
4963 4963 scsi_state);
4964 4964 }
4965 4965
4966 4966 NDBG31(("\t\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x",
4967 4967 scsi_status, ioc_status, scsi_state));
4968 4968
4969 4969 pkt = CMD2PKT(cmd);
4970 4970 *(pkt->pkt_scbp) = scsi_status;
4971 4971
4972 4972 if (loginfo == 0x31170000) {
4973 4973 /*
4974 4974 * if loginfo PL_LOGINFO_CODE_IO_DEVICE_MISSING_DELAY_RETRY
4975 4975 * 0x31170000 comes, that means the device missing delay
4976 4976 * is in progressing, the command need retry later.
4977 4977 */
4978 4978 *(pkt->pkt_scbp) = STATUS_BUSY;
4979 4979 return;
4980 4980 }
4981 4981
4982 4982 if ((scsi_state & MPI2_SCSI_STATE_NO_SCSI_STATUS) &&
4983 4983 ((ioc_status & MPI2_IOCSTATUS_MASK) ==
4984 4984 MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE)) {
4985 4985 pkt->pkt_reason = CMD_INCOMPLETE;
4986 4986 pkt->pkt_state |= STATE_GOT_BUS;
4987 4987 if (ptgt->m_reset_delay == 0) {
4988 4988 mptsas_set_throttle(mpt, ptgt,
4989 4989 DRAIN_THROTTLE);
4990 4990 }
4991 4991 return;
4992 4992 }
4993 4993
4994 4994 if (scsi_state & MPI2_SCSI_STATE_RESPONSE_INFO_VALID) {
4995 4995 responsedata &= 0x000000FF;
4996 4996 if (responsedata & MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF) {
4997 4997 mptsas_log(mpt, CE_NOTE, "Do not support the TLR\n");
4998 4998 pkt->pkt_reason = CMD_TLR_OFF;
4999 4999 return;
5000 5000 }
5001 5001 }
5002 5002
5003 5003
5004 5004 switch (scsi_status) {
5005 5005 case MPI2_SCSI_STATUS_CHECK_CONDITION:
5006 5006 pkt->pkt_resid = (cmd->cmd_dmacount - xferred);
5007 5007 arqstat = (void*)(pkt->pkt_scbp);
5008 5008 arqstat->sts_rqpkt_status = *((struct scsi_status *)
5009 5009 (pkt->pkt_scbp));
5010 5010 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET |
5011 5011 STATE_SENT_CMD | STATE_GOT_STATUS | STATE_ARQ_DONE);
5012 5012 if (cmd->cmd_flags & CFLAG_XARQ) {
5013 5013 pkt->pkt_state |= STATE_XARQ_DONE;
5014 5014 }
5015 5015 if (pkt->pkt_resid != cmd->cmd_dmacount) {
5016 5016 pkt->pkt_state |= STATE_XFERRED_DATA;
5017 5017 }
5018 5018 arqstat->sts_rqpkt_reason = pkt->pkt_reason;
5019 5019 arqstat->sts_rqpkt_state = pkt->pkt_state;
5020 5020 arqstat->sts_rqpkt_state |= STATE_XFERRED_DATA;
5021 5021 arqstat->sts_rqpkt_statistics = pkt->pkt_statistics;
5022 5022 sensedata = (uint8_t *)&arqstat->sts_sensedata;
5023 5023
5024 5024 bcopy((uchar_t *)bp->b_un.b_addr, sensedata,
5025 5025 ((cmd->cmd_rqslen >= sensecount) ? sensecount :
5026 5026 cmd->cmd_rqslen));
5027 5027 arqstat->sts_rqpkt_resid = (cmd->cmd_rqslen - sensecount);
5028 5028 cmd->cmd_flags |= CFLAG_CMDARQ;
5029 5029 /*
5030 5030 * Set proper status for pkt if autosense was valid
5031 5031 */
5032 5032 if (scsi_state & MPI2_SCSI_STATE_AUTOSENSE_VALID) {
5033 5033 struct scsi_status zero_status = { 0 };
5034 5034 arqstat->sts_rqpkt_status = zero_status;
5035 5035 }
5036 5036
5037 5037 /*
5038 5038 * ASC=0x47 is parity error
5039 5039 * ASC=0x48 is initiator detected error received
5040 5040 */
5041 5041 if ((scsi_sense_key(sensedata) == KEY_ABORTED_COMMAND) &&
5042 5042 ((scsi_sense_asc(sensedata) == 0x47) ||
5043 5043 (scsi_sense_asc(sensedata) == 0x48))) {
5044 5044 mptsas_log(mpt, CE_NOTE, "Aborted_command!");
5045 5045 }
5046 5046
5047 5047 /*
5048 5048 * ASC/ASCQ=0x3F/0x0E means report_luns data changed
5049 5049 * ASC/ASCQ=0x25/0x00 means invalid lun
5050 5050 */
5051 5051 if (((scsi_sense_key(sensedata) == KEY_UNIT_ATTENTION) &&
5052 5052 (scsi_sense_asc(sensedata) == 0x3F) &&
5053 5053 (scsi_sense_ascq(sensedata) == 0x0E)) ||
5054 5054 ((scsi_sense_key(sensedata) == KEY_ILLEGAL_REQUEST) &&
5055 5055 (scsi_sense_asc(sensedata) == 0x25) &&
5056 5056 (scsi_sense_ascq(sensedata) == 0x00))) {
5057 5057 mptsas_topo_change_list_t *topo_node = NULL;
5058 5058
5059 5059 topo_node = kmem_zalloc(
5060 5060 sizeof (mptsas_topo_change_list_t),
5061 5061 KM_NOSLEEP);
5062 5062 if (topo_node == NULL) {
5063 5063 mptsas_log(mpt, CE_NOTE, "No memory"
5064 5064 "resource for handle SAS dynamic"
5065 5065 "reconfigure.\n");
5066 5066 break;
5067 5067 }
5068 5068 topo_node->mpt = mpt;
5069 5069 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_TARGET;
5070 5070 topo_node->un.phymask = ptgt->m_phymask;
5071 5071 topo_node->devhdl = ptgt->m_devhdl;
5072 5072 topo_node->object = (void *)ptgt;
5073 5073 topo_node->flags = MPTSAS_TOPO_FLAG_LUN_ASSOCIATED;
5074 5074
5075 5075 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
5076 5076 mptsas_handle_dr,
5077 5077 (void *)topo_node,
5078 5078 DDI_NOSLEEP)) != DDI_SUCCESS) {
5079 5079 mptsas_log(mpt, CE_NOTE, "mptsas start taskq"
5080 5080 "for handle SAS dynamic reconfigure"
5081 5081 "failed. \n");
5082 5082 }
5083 5083 }
5084 5084 break;
5085 5085 case MPI2_SCSI_STATUS_GOOD:
5086 5086 switch (ioc_status & MPI2_IOCSTATUS_MASK) {
5087 5087 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
5088 5088 pkt->pkt_reason = CMD_DEV_GONE;
5089 5089 pkt->pkt_state |= STATE_GOT_BUS;
5090 5090 if (ptgt->m_reset_delay == 0) {
5091 5091 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5092 5092 }
5093 5093 NDBG31(("lost disk for target%d, command:%x",
5094 5094 Tgt(cmd), pkt->pkt_cdbp[0]));
5095 5095 break;
5096 5096 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
5097 5097 NDBG31(("data overrun: xferred=%d", xferred));
5098 5098 NDBG31(("dmacount=%d", cmd->cmd_dmacount));
5099 5099 pkt->pkt_reason = CMD_DATA_OVR;
5100 5100 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET
5101 5101 | STATE_SENT_CMD | STATE_GOT_STATUS
5102 5102 | STATE_XFERRED_DATA);
5103 5103 pkt->pkt_resid = 0;
5104 5104 break;
5105 5105 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
5106 5106 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
5107 5107 NDBG31(("data underrun: xferred=%d", xferred));
5108 5108 NDBG31(("dmacount=%d", cmd->cmd_dmacount));
5109 5109 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET
5110 5110 | STATE_SENT_CMD | STATE_GOT_STATUS);
5111 5111 pkt->pkt_resid = (cmd->cmd_dmacount - xferred);
5112 5112 if (pkt->pkt_resid != cmd->cmd_dmacount) {
5113 5113 pkt->pkt_state |= STATE_XFERRED_DATA;
5114 5114 }
5115 5115 break;
5116 5116 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
5117 5117 mptsas_set_pkt_reason(mpt,
5118 5118 cmd, CMD_RESET, STAT_BUS_RESET);
5119 5119 break;
5120 5120 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
5121 5121 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
5122 5122 mptsas_set_pkt_reason(mpt,
5123 5123 cmd, CMD_RESET, STAT_DEV_RESET);
5124 5124 break;
5125 5125 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
5126 5126 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
5127 5127 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET);
5128 5128 mptsas_set_pkt_reason(mpt,
5129 5129 cmd, CMD_TERMINATED, STAT_TERMINATED);
5130 5130 break;
5131 5131 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
5132 5132 case MPI2_IOCSTATUS_BUSY:
5133 5133 /*
5134 5134 * set throttles to drain
5135 5135 */
5136 5136 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
5137 5137 &mpt->m_active->m_tgttbl, MPTSAS_HASH_FIRST);
5138 5138 while (ptgt != NULL) {
5139 5139 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5140 5140
5141 5141 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
5142 5142 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
5143 5143 }
5144 5144
5145 5145 /*
5146 5146 * retry command
5147 5147 */
5148 5148 cmd->cmd_flags |= CFLAG_RETRY;
5149 5149 cmd->cmd_pkt_flags |= FLAG_HEAD;
5150 5150
5151 5151 (void) mptsas_accept_pkt(mpt, cmd);
5152 5152 break;
5153 5153 default:
5154 5154 mptsas_log(mpt, CE_WARN,
5155 5155 "unknown ioc_status = %x\n", ioc_status);
5156 5156 mptsas_log(mpt, CE_CONT, "scsi_state = %x, transfer "
5157 5157 "count = %x, scsi_status = %x", scsi_state,
5158 5158 xferred, scsi_status);
5159 5159 break;
5160 5160 }
5161 5161 break;
5162 5162 case MPI2_SCSI_STATUS_TASK_SET_FULL:
5163 5163 mptsas_handle_qfull(mpt, cmd);
5164 5164 break;
5165 5165 case MPI2_SCSI_STATUS_BUSY:
5166 5166 NDBG31(("scsi_status busy received"));
5167 5167 break;
5168 5168 case MPI2_SCSI_STATUS_RESERVATION_CONFLICT:
5169 5169 NDBG31(("scsi_status reservation conflict received"));
5170 5170 break;
5171 5171 default:
5172 5172 mptsas_log(mpt, CE_WARN, "scsi_status=%x, ioc_status=%x\n",
5173 5173 scsi_status, ioc_status);
5174 5174 mptsas_log(mpt, CE_WARN,
5175 5175 "mptsas_process_intr: invalid scsi status\n");
5176 5176 break;
5177 5177 }
5178 5178 }
5179 5179
5180 5180 static void
5181 5181 mptsas_check_task_mgt(mptsas_t *mpt, pMpi2SCSIManagementReply_t reply,
5182 5182 mptsas_cmd_t *cmd)
5183 5183 {
5184 5184 uint8_t task_type;
5185 5185 uint16_t ioc_status;
5186 5186 uint32_t log_info;
5187 5187 uint16_t dev_handle;
5188 5188 struct scsi_pkt *pkt = CMD2PKT(cmd);
5189 5189
5190 5190 task_type = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->TaskType);
5191 5191 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus);
5192 5192 log_info = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->IOCLogInfo);
5193 5193 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->DevHandle);
5194 5194
5195 5195 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5196 5196 mptsas_log(mpt, CE_WARN, "mptsas_check_task_mgt: Task 0x%x "
5197 5197 "failed. IOCStatus=0x%x IOCLogInfo=0x%x target=%d\n",
5198 5198 task_type, ioc_status, log_info, dev_handle);
5199 5199 pkt->pkt_reason = CMD_INCOMPLETE;
5200 5200 return;
5201 5201 }
5202 5202
5203 5203 switch (task_type) {
5204 5204 case MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK:
5205 5205 case MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET:
5206 5206 case MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK:
5207 5207 case MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA:
5208 5208 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET:
5209 5209 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_UNIT_ATTENTION:
5210 5210 break;
5211 5211 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
5212 5212 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
5213 5213 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
5214 5214 /*
5215 5215 * Check for invalid DevHandle of 0 in case application
5216 5216 * sends bad command. DevHandle of 0 could cause problems.
5217 5217 */
5218 5218 if (dev_handle == 0) {
5219 5219 mptsas_log(mpt, CE_WARN, "!Can't flush target with"
5220 5220 " DevHandle of 0.");
5221 5221 } else {
5222 5222 mptsas_flush_target(mpt, dev_handle, Lun(cmd),
5223 5223 task_type);
5224 5224 }
5225 5225 break;
5226 5226 default:
5227 5227 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.",
5228 5228 task_type);
5229 5229 mptsas_log(mpt, CE_WARN, "ioc status = %x", ioc_status);
5230 5230 break;
5231 5231 }
5232 5232 }
5233 5233
5234 5234 static void
5235 5235 mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg)
5236 5236 {
5237 5237 mptsas_t *mpt = arg->mpt;
5238 5238 uint64_t t = arg->t;
5239 5239 mptsas_cmd_t *cmd;
5240 5240 struct scsi_pkt *pkt;
5241 5241 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
5242 5242
5243 5243 mutex_enter(&item->mutex);
5244 5244 while (item->flag & MPTSAS_DONEQ_THREAD_ACTIVE) {
5245 5245 if (!item->doneq) {
5246 5246 cv_wait(&item->cv, &item->mutex);
5247 5247 }
5248 5248 pkt = NULL;
5249 5249 if ((cmd = mptsas_doneq_thread_rm(mpt, t)) != NULL) {
5250 5250 cmd->cmd_flags |= CFLAG_COMPLETED;
5251 5251 pkt = CMD2PKT(cmd);
5252 5252 }
5253 5253 mutex_exit(&item->mutex);
5254 5254 if (pkt) {
5255 5255 mptsas_pkt_comp(pkt, cmd);
5256 5256 }
5257 5257 mutex_enter(&item->mutex);
5258 5258 }
5259 5259 mutex_exit(&item->mutex);
5260 5260 mutex_enter(&mpt->m_doneq_mutex);
5261 5261 mpt->m_doneq_thread_n--;
5262 5262 cv_broadcast(&mpt->m_doneq_thread_cv);
5263 5263 mutex_exit(&mpt->m_doneq_mutex);
5264 5264 }
5265 5265
5266 5266
5267 5267 /*
5268 5268 * mpt interrupt handler.
5269 5269 */
5270 5270 static uint_t
5271 5271 mptsas_intr(caddr_t arg1, caddr_t arg2)
5272 5272 {
5273 5273 mptsas_t *mpt = (void *)arg1;
5274 5274 pMpi2ReplyDescriptorsUnion_t reply_desc_union;
5275 5275 uchar_t did_reply = FALSE;
5276 5276
5277 5277 NDBG1(("mptsas_intr: arg1 0x%p arg2 0x%p", (void *)arg1, (void *)arg2));
5278 5278
5279 5279 mutex_enter(&mpt->m_mutex);
5280 5280
5281 5281 /*
5282 5282 * If interrupts are shared by two channels then check whether this
5283 5283 * interrupt is genuinely for this channel by making sure first the
5284 5284 * chip is in high power state.
5285 5285 */
5286 5286 if ((mpt->m_options & MPTSAS_OPT_PM) &&
5287 5287 (mpt->m_power_level != PM_LEVEL_D0)) {
5288 5288 mutex_exit(&mpt->m_mutex);
5289 5289 return (DDI_INTR_UNCLAIMED);
5290 5290 }
5291 5291
5292 5292 /*
5293 5293 * If polling, interrupt was triggered by some shared interrupt because
5294 5294 * IOC interrupts are disabled during polling, so polling routine will
5295 5295 * handle any replies. Considering this, if polling is happening,
5296 5296 * return with interrupt unclaimed.
5297 5297 */
5298 5298 if (mpt->m_polled_intr) {
5299 5299 mutex_exit(&mpt->m_mutex);
5300 5300 mptsas_log(mpt, CE_WARN, "mpt_sas: Unclaimed interrupt");
5301 5301 return (DDI_INTR_UNCLAIMED);
5302 5302 }
5303 5303
5304 5304 /*
5305 5305 * Read the istat register.
5306 5306 */
5307 5307 if ((INTPENDING(mpt)) != 0) {
5308 5308 /*
5309 5309 * read fifo until empty.
5310 5310 */
5311 5311 #ifndef __lock_lint
5312 5312 _NOTE(CONSTCOND)
5313 5313 #endif
5314 5314 while (TRUE) {
5315 5315 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
5316 5316 DDI_DMA_SYNC_FORCPU);
5317 5317 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t)
5318 5318 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index);
5319 5319
5320 5320 if (ddi_get32(mpt->m_acc_post_queue_hdl,
5321 5321 &reply_desc_union->Words.Low) == 0xFFFFFFFF ||
5322 5322 ddi_get32(mpt->m_acc_post_queue_hdl,
5323 5323 &reply_desc_union->Words.High) == 0xFFFFFFFF) {
5324 5324 break;
5325 5325 }
5326 5326
5327 5327 /*
5328 5328 * The reply is valid, process it according to its
5329 5329 * type. Also, set a flag for updating the reply index
5330 5330 * after they've all been processed.
5331 5331 */
5332 5332 did_reply = TRUE;
5333 5333
5334 5334 mptsas_process_intr(mpt, reply_desc_union);
5335 5335
5336 5336 /*
5337 5337 * Increment post index and roll over if needed.
5338 5338 */
5339 5339 if (++mpt->m_post_index == mpt->m_post_queue_depth) {
5340 5340 mpt->m_post_index = 0;
5341 5341 }
5342 5342 }
5343 5343
5344 5344 /*
5345 5345 * Update the global reply index if at least one reply was
5346 5346 * processed.
5347 5347 */
5348 5348 if (did_reply) {
5349 5349 ddi_put32(mpt->m_datap,
5350 5350 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index);
5351 5351 }
5352 5352 } else {
5353 5353 mutex_exit(&mpt->m_mutex);
5354 5354 return (DDI_INTR_UNCLAIMED);
5355 5355 }
5356 5356 NDBG1(("mptsas_intr complete"));
5357 5357
5358 5358 /*
5359 5359 * If no helper threads are created, process the doneq in ISR. If
5360 5360 * helpers are created, use the doneq length as a metric to measure the
5361 5361 * load on the interrupt CPU. If it is long enough, which indicates the
5362 5362 * load is heavy, then we deliver the IO completions to the helpers.
5363 5363 * This measurement has some limitations, although it is simple and
5364 5364 * straightforward and works well for most of the cases at present.
5365 5365 */
5366 5366 if (!mpt->m_doneq_thread_n ||
5367 5367 (mpt->m_doneq_len <= mpt->m_doneq_length_threshold)) {
5368 5368 mptsas_doneq_empty(mpt);
5369 5369 } else {
5370 5370 mptsas_deliver_doneq_thread(mpt);
5371 5371 }
5372 5372
5373 5373 /*
5374 5374 * If there are queued cmd, start them now.
5375 5375 */
5376 5376 if (mpt->m_waitq != NULL) {
5377 5377 mptsas_restart_waitq(mpt);
5378 5378 }
5379 5379
5380 5380 mutex_exit(&mpt->m_mutex);
5381 5381 return (DDI_INTR_CLAIMED);
5382 5382 }
5383 5383
5384 5384 static void
5385 5385 mptsas_process_intr(mptsas_t *mpt,
5386 5386 pMpi2ReplyDescriptorsUnion_t reply_desc_union)
5387 5387 {
5388 5388 uint8_t reply_type;
5389 5389
5390 5390 ASSERT(mutex_owned(&mpt->m_mutex));
5391 5391
5392 5392 /*
5393 5393 * The reply is valid, process it according to its
5394 5394 * type. Also, set a flag for updated the reply index
5395 5395 * after they've all been processed.
5396 5396 */
5397 5397 reply_type = ddi_get8(mpt->m_acc_post_queue_hdl,
5398 5398 &reply_desc_union->Default.ReplyFlags);
5399 5399 reply_type &= MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
5400 5400 if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
5401 5401 mptsas_handle_scsi_io_success(mpt, reply_desc_union);
5402 5402 } else if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
5403 5403 mptsas_handle_address_reply(mpt, reply_desc_union);
5404 5404 } else {
5405 5405 mptsas_log(mpt, CE_WARN, "?Bad reply type %x", reply_type);
5406 5406 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
5407 5407 }
5408 5408
5409 5409 /*
5410 5410 * Clear the reply descriptor for re-use and increment
5411 5411 * index.
5412 5412 */
5413 5413 ddi_put64(mpt->m_acc_post_queue_hdl,
5414 5414 &((uint64_t *)(void *)mpt->m_post_queue)[mpt->m_post_index],
5415 5415 0xFFFFFFFFFFFFFFFF);
5416 5416 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
5417 5417 DDI_DMA_SYNC_FORDEV);
5418 5418 }
5419 5419
5420 5420 /*
5421 5421 * handle qfull condition
5422 5422 */
5423 5423 static void
5424 5424 mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd)
5425 5425 {
5426 5426 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
5427 5427
5428 5428 if ((++cmd->cmd_qfull_retries > ptgt->m_qfull_retries) ||
5429 5429 (ptgt->m_qfull_retries == 0)) {
5430 5430 /*
5431 5431 * We have exhausted the retries on QFULL, or,
5432 5432 * the target driver has indicated that it
5433 5433 * wants to handle QFULL itself by setting
5434 5434 * qfull-retries capability to 0. In either case
5435 5435 * we want the target driver's QFULL handling
5436 5436 * to kick in. We do this by having pkt_reason
5437 5437 * as CMD_CMPLT and pkt_scbp as STATUS_QFULL.
5438 5438 */
5439 5439 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5440 5440 } else {
5441 5441 if (ptgt->m_reset_delay == 0) {
5442 5442 ptgt->m_t_throttle =
5443 5443 max((ptgt->m_t_ncmds - 2), 0);
5444 5444 }
5445 5445
5446 5446 cmd->cmd_pkt_flags |= FLAG_HEAD;
5447 5447 cmd->cmd_flags &= ~(CFLAG_TRANFLAG);
5448 5448 cmd->cmd_flags |= CFLAG_RETRY;
5449 5449
5450 5450 (void) mptsas_accept_pkt(mpt, cmd);
5451 5451
5452 5452 /*
5453 5453 * when target gives queue full status with no commands
5454 5454 * outstanding (m_t_ncmds == 0), throttle is set to 0
5455 5455 * (HOLD_THROTTLE), and the queue full handling start
5456 5456 * (see psarc/1994/313); if there are commands outstanding,
5457 5457 * throttle is set to (m_t_ncmds - 2)
5458 5458 */
5459 5459 if (ptgt->m_t_throttle == HOLD_THROTTLE) {
5460 5460 /*
5461 5461 * By setting throttle to QFULL_THROTTLE, we
5462 5462 * avoid submitting new commands and in
5463 5463 * mptsas_restart_cmd find out slots which need
5464 5464 * their throttles to be cleared.
5465 5465 */
5466 5466 mptsas_set_throttle(mpt, ptgt, QFULL_THROTTLE);
5467 5467 if (mpt->m_restart_cmd_timeid == 0) {
5468 5468 mpt->m_restart_cmd_timeid =
5469 5469 timeout(mptsas_restart_cmd, mpt,
5470 5470 ptgt->m_qfull_retry_interval);
5471 5471 }
5472 5472 }
5473 5473 }
5474 5474 }
5475 5475
5476 5476 mptsas_phymask_t
5477 5477 mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport)
5478 5478 {
5479 5479 mptsas_phymask_t phy_mask = 0;
5480 5480 uint8_t i = 0;
5481 5481
5482 5482 NDBG20(("mptsas%d physport_to_phymask enter", mpt->m_instance));
5483 5483
5484 5484 ASSERT(mutex_owned(&mpt->m_mutex));
5485 5485
5486 5486 /*
5487 5487 * If physport is 0xFF, this is a RAID volume. Use phymask of 0.
5488 5488 */
5489 5489 if (physport == 0xFF) {
5490 5490 return (0);
5491 5491 }
5492 5492
5493 5493 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
5494 5494 if (mpt->m_phy_info[i].attached_devhdl &&
5495 5495 (mpt->m_phy_info[i].phy_mask != 0) &&
5496 5496 (mpt->m_phy_info[i].port_num == physport)) {
5497 5497 phy_mask = mpt->m_phy_info[i].phy_mask;
5498 5498 break;
5499 5499 }
5500 5500 }
5501 5501 NDBG20(("mptsas%d physport_to_phymask:physport :%x phymask :%x, ",
5502 5502 mpt->m_instance, physport, phy_mask));
5503 5503 return (phy_mask);
5504 5504 }
5505 5505
5506 5506 /*
5507 5507 * mpt free device handle after device gone, by use of passthrough
5508 5508 */
5509 5509 static int
5510 5510 mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl)
5511 5511 {
5512 5512 Mpi2SasIoUnitControlRequest_t req;
5513 5513 Mpi2SasIoUnitControlReply_t rep;
5514 5514 int ret;
5515 5515
5516 5516 ASSERT(mutex_owned(&mpt->m_mutex));
5517 5517
5518 5518 /*
5519 5519 * Need to compose a SAS IO Unit Control request message
5520 5520 * and call mptsas_do_passthru() function
5521 5521 */
5522 5522 bzero(&req, sizeof (req));
5523 5523 bzero(&rep, sizeof (rep));
5524 5524
5525 5525 req.Function = MPI2_FUNCTION_SAS_IO_UNIT_CONTROL;
5526 5526 req.Operation = MPI2_SAS_OP_REMOVE_DEVICE;
5527 5527 req.DevHandle = LE_16(devhdl);
5528 5528
5529 5529 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL,
5530 5530 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL);
5531 5531 if (ret != 0) {
5532 5532 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit "
5533 5533 "Control error %d", ret);
5534 5534 return (DDI_FAILURE);
5535 5535 }
5536 5536
5537 5537 /* do passthrough success, check the ioc status */
5538 5538 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
5539 5539 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit "
5540 5540 "Control IOCStatus %d", LE_16(rep.IOCStatus));
5541 5541 return (DDI_FAILURE);
5542 5542 }
5543 5543
5544 5544 return (DDI_SUCCESS);
5545 5545 }
5546 5546
5547 5547 static void
5548 5548 mptsas_update_phymask(mptsas_t *mpt)
5549 5549 {
5550 5550 mptsas_phymask_t mask = 0, phy_mask;
5551 5551 char *phy_mask_name;
5552 5552 uint8_t current_port;
5553 5553 int i, j;
5554 5554
5555 5555 NDBG20(("mptsas%d update phymask ", mpt->m_instance));
5556 5556
5557 5557 ASSERT(mutex_owned(&mpt->m_mutex));
5558 5558
5559 5559 (void) mptsas_get_sas_io_unit_page(mpt);
5560 5560
5561 5561 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
5562 5562
5563 5563 for (i = 0; i < mpt->m_num_phys; i++) {
5564 5564 phy_mask = 0x00;
5565 5565
5566 5566 if (mpt->m_phy_info[i].attached_devhdl == 0)
5567 5567 continue;
5568 5568
5569 5569 bzero(phy_mask_name, sizeof (phy_mask_name));
5570 5570
5571 5571 current_port = mpt->m_phy_info[i].port_num;
5572 5572
5573 5573 if ((mask & (1 << i)) != 0)
5574 5574 continue;
5575 5575
5576 5576 for (j = 0; j < mpt->m_num_phys; j++) {
5577 5577 if (mpt->m_phy_info[j].attached_devhdl &&
5578 5578 (mpt->m_phy_info[j].port_num == current_port)) {
5579 5579 phy_mask |= (1 << j);
5580 5580 }
5581 5581 }
5582 5582 mask = mask | phy_mask;
5583 5583
5584 5584 for (j = 0; j < mpt->m_num_phys; j++) {
5585 5585 if ((phy_mask >> j) & 0x01) {
5586 5586 mpt->m_phy_info[j].phy_mask = phy_mask;
5587 5587 }
5588 5588 }
5589 5589
5590 5590 (void) sprintf(phy_mask_name, "%x", phy_mask);
5591 5591
5592 5592 mutex_exit(&mpt->m_mutex);
5593 5593 /*
5594 5594 * register a iport, if the port has already been existed
5595 5595 * SCSA will do nothing and just return.
5596 5596 */
5597 5597 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name);
5598 5598 mutex_enter(&mpt->m_mutex);
5599 5599 }
5600 5600 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
5601 5601 NDBG20(("mptsas%d update phymask return", mpt->m_instance));
5602 5602 }
5603 5603
5604 5604 /*
5605 5605 * mptsas_handle_dr is a task handler for DR, the DR action includes:
5606 5606 * 1. Directly attched Device Added/Removed.
5607 5607 * 2. Expander Device Added/Removed.
5608 5608 * 3. Indirectly Attached Device Added/Expander.
5609 5609 * 4. LUNs of a existing device status change.
5610 5610 * 5. RAID volume created/deleted.
5611 5611 * 6. Member of RAID volume is released because of RAID deletion.
5612 5612 * 7. Physical disks are removed because of RAID creation.
5613 5613 */
5614 5614 static void
5615 5615 mptsas_handle_dr(void *args) {
5616 5616 mptsas_topo_change_list_t *topo_node = NULL;
5617 5617 mptsas_topo_change_list_t *save_node = NULL;
5618 5618 mptsas_t *mpt;
5619 5619 dev_info_t *parent = NULL;
5620 5620 mptsas_phymask_t phymask = 0;
5621 5621 char *phy_mask_name;
5622 5622 uint8_t flags = 0, physport = 0xff;
5623 5623 uint8_t port_update = 0;
5624 5624 uint_t event;
5625 5625
5626 5626 topo_node = (mptsas_topo_change_list_t *)args;
5627 5627
5628 5628 mpt = topo_node->mpt;
5629 5629 event = topo_node->event;
5630 5630 flags = topo_node->flags;
5631 5631
5632 5632 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
5633 5633
5634 5634 NDBG20(("mptsas%d handle_dr enter", mpt->m_instance));
5635 5635
5636 5636 switch (event) {
5637 5637 case MPTSAS_DR_EVENT_RECONFIG_TARGET:
5638 5638 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
5639 5639 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE) ||
5640 5640 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) {
5641 5641 /*
5642 5642 * Direct attached or expander attached device added
5643 5643 * into system or a Phys Disk that is being unhidden.
5644 5644 */
5645 5645 port_update = 1;
5646 5646 }
5647 5647 break;
5648 5648 case MPTSAS_DR_EVENT_RECONFIG_SMP:
5649 5649 /*
5650 5650 * New expander added into system, it must be the head
5651 5651 * of topo_change_list_t
5652 5652 */
5653 5653 port_update = 1;
5654 5654 break;
5655 5655 default:
5656 5656 port_update = 0;
5657 5657 break;
5658 5658 }
5659 5659 /*
5660 5660 * All cases port_update == 1 may cause initiator port form change
5661 5661 */
5662 5662 mutex_enter(&mpt->m_mutex);
5663 5663 if (mpt->m_port_chng && port_update) {
5664 5664 /*
5665 5665 * mpt->m_port_chng flag indicates some PHYs of initiator
5666 5666 * port have changed to online. So when expander added or
5667 5667 * directly attached device online event come, we force to
5668 5668 * update port information by issueing SAS IO Unit Page and
5669 5669 * update PHYMASKs.
5670 5670 */
5671 5671 (void) mptsas_update_phymask(mpt);
5672 5672 mpt->m_port_chng = 0;
5673 5673
5674 5674 }
5675 5675 mutex_exit(&mpt->m_mutex);
5676 5676 while (topo_node) {
5677 5677 phymask = 0;
5678 5678 if (parent == NULL) {
5679 5679 physport = topo_node->un.physport;
5680 5680 event = topo_node->event;
5681 5681 flags = topo_node->flags;
5682 5682 if (event & (MPTSAS_DR_EVENT_OFFLINE_TARGET |
5683 5683 MPTSAS_DR_EVENT_OFFLINE_SMP)) {
5684 5684 /*
5685 5685 * For all offline events, phymask is known
5686 5686 */
5687 5687 phymask = topo_node->un.phymask;
5688 5688 goto find_parent;
5689 5689 }
5690 5690 if (event & MPTSAS_TOPO_FLAG_REMOVE_HANDLE) {
5691 5691 goto handle_topo_change;
5692 5692 }
5693 5693 if (flags & MPTSAS_TOPO_FLAG_LUN_ASSOCIATED) {
5694 5694 phymask = topo_node->un.phymask;
5695 5695 goto find_parent;
5696 5696 }
5697 5697
5698 5698 if ((flags ==
5699 5699 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) &&
5700 5700 (event == MPTSAS_DR_EVENT_RECONFIG_TARGET)) {
5701 5701 /*
5702 5702 * There is no any field in IR_CONFIG_CHANGE
5703 5703 * event indicate physport/phynum, let's get
5704 5704 * parent after SAS Device Page0 request.
5705 5705 */
5706 5706 goto handle_topo_change;
5707 5707 }
5708 5708
5709 5709 mutex_enter(&mpt->m_mutex);
5710 5710 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
5711 5711 /*
5712 5712 * If the direct attached device added or a
5713 5713 * phys disk is being unhidden, argument
5714 5714 * physport actually is PHY#, so we have to get
5715 5715 * phymask according PHY#.
5716 5716 */
5717 5717 physport = mpt->m_phy_info[physport].port_num;
5718 5718 }
5719 5719
5720 5720 /*
5721 5721 * Translate physport to phymask so that we can search
5722 5722 * parent dip.
5723 5723 */
5724 5724 phymask = mptsas_physport_to_phymask(mpt,
5725 5725 physport);
5726 5726 mutex_exit(&mpt->m_mutex);
5727 5727
5728 5728 find_parent:
5729 5729 bzero(phy_mask_name, MPTSAS_MAX_PHYS);
5730 5730 /*
5731 5731 * For RAID topology change node, write the iport name
5732 5732 * as v0.
5733 5733 */
5734 5734 if (flags & MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
5735 5735 (void) sprintf(phy_mask_name, "v0");
5736 5736 } else {
5737 5737 /*
5738 5738 * phymask can bo 0 if the drive has been
5739 5739 * pulled by the time an add event is
5740 5740 * processed. If phymask is 0, just skip this
5741 5741 * event and continue.
5742 5742 */
5743 5743 if (phymask == 0) {
5744 5744 mutex_enter(&mpt->m_mutex);
5745 5745 save_node = topo_node;
5746 5746 topo_node = topo_node->next;
5747 5747 ASSERT(save_node);
5748 5748 kmem_free(save_node,
5749 5749 sizeof (mptsas_topo_change_list_t));
5750 5750 mutex_exit(&mpt->m_mutex);
5751 5751
5752 5752 parent = NULL;
5753 5753 continue;
5754 5754 }
5755 5755 (void) sprintf(phy_mask_name, "%x", phymask);
5756 5756 }
5757 5757 parent = scsi_hba_iport_find(mpt->m_dip,
5758 5758 phy_mask_name);
5759 5759 if (parent == NULL) {
5760 5760 mptsas_log(mpt, CE_WARN, "Failed to find an "
5761 5761 "iport, should not happen!");
5762 5762 goto out;
5763 5763 }
5764 5764
5765 5765 }
5766 5766 ASSERT(parent);
5767 5767 handle_topo_change:
5768 5768
5769 5769 mutex_enter(&mpt->m_mutex);
5770 5770 /*
5771 5771 * If HBA is being reset, don't perform operations depending
5772 5772 * on the IOC. We must free the topo list, however.
5773 5773 */
5774 5774 if (!mpt->m_in_reset)
5775 5775 mptsas_handle_topo_change(topo_node, parent);
5776 5776 else
5777 5777 NDBG20(("skipping topo change received during reset"));
5778 5778 save_node = topo_node;
5779 5779 topo_node = topo_node->next;
5780 5780 ASSERT(save_node);
5781 5781 kmem_free(save_node, sizeof (mptsas_topo_change_list_t));
5782 5782 mutex_exit(&mpt->m_mutex);
5783 5783
5784 5784 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
5785 5785 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) ||
5786 5786 (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED)) {
5787 5787 /*
5788 5788 * If direct attached device associated, make sure
5789 5789 * reset the parent before start the next one. But
5790 5790 * all devices associated with expander shares the
5791 5791 * parent. Also, reset parent if this is for RAID.
5792 5792 */
5793 5793 parent = NULL;
5794 5794 }
5795 5795 }
5796 5796 out:
5797 5797 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
5798 5798 }
5799 5799
5800 5800 static void
5801 5801 mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node,
5802 5802 dev_info_t *parent)
5803 5803 {
5804 5804 mptsas_target_t *ptgt = NULL;
5805 5805 mptsas_smp_t *psmp = NULL;
5806 5806 mptsas_t *mpt = (void *)topo_node->mpt;
5807 5807 uint16_t devhdl;
5808 5808 uint16_t attached_devhdl;
5809 5809 uint64_t sas_wwn = 0;
5810 5810 int rval = 0;
5811 5811 uint32_t page_address;
5812 5812 uint8_t phy, flags;
5813 5813 char *addr = NULL;
5814 5814 dev_info_t *lundip;
5815 5815 int circ = 0, circ1 = 0;
5816 5816 char attached_wwnstr[MPTSAS_WWN_STRLEN];
5817 5817
5818 5818 NDBG20(("mptsas%d handle_topo_change enter", mpt->m_instance));
5819 5819
5820 5820 ASSERT(mutex_owned(&mpt->m_mutex));
5821 5821
5822 5822 switch (topo_node->event) {
5823 5823 case MPTSAS_DR_EVENT_RECONFIG_TARGET:
5824 5824 {
5825 5825 char *phy_mask_name;
5826 5826 mptsas_phymask_t phymask = 0;
5827 5827
5828 5828 if (topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
5829 5829 /*
5830 5830 * Get latest RAID info.
5831 5831 */
5832 5832 (void) mptsas_get_raid_info(mpt);
5833 5833 ptgt = mptsas_search_by_devhdl(
5834 5834 &mpt->m_active->m_tgttbl, topo_node->devhdl);
5835 5835 if (ptgt == NULL)
5836 5836 break;
5837 5837 } else {
5838 5838 ptgt = (void *)topo_node->object;
5839 5839 }
5840 5840
5841 5841 if (ptgt == NULL) {
5842 5842 /*
5843 5843 * If a Phys Disk was deleted, RAID info needs to be
5844 5844 * updated to reflect the new topology.
5845 5845 */
5846 5846 (void) mptsas_get_raid_info(mpt);
5847 5847
5848 5848 /*
5849 5849 * Get sas device page 0 by DevHandle to make sure if
5850 5850 * SSP/SATA end device exist.
5851 5851 */
5852 5852 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
5853 5853 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
5854 5854 topo_node->devhdl;
5855 5855
5856 5856 rval = mptsas_get_target_device_info(mpt, page_address,
5857 5857 &devhdl, &ptgt);
5858 5858 if (rval == DEV_INFO_WRONG_DEVICE_TYPE) {
5859 5859 mptsas_log(mpt, CE_NOTE,
5860 5860 "mptsas_handle_topo_change: target %d is "
5861 5861 "not a SAS/SATA device. \n",
5862 5862 topo_node->devhdl);
5863 5863 } else if (rval == DEV_INFO_FAIL_ALLOC) {
5864 5864 mptsas_log(mpt, CE_NOTE,
5865 5865 "mptsas_handle_topo_change: could not "
5866 5866 "allocate memory. \n");
5867 5867 }
5868 5868 /*
5869 5869 * If rval is DEV_INFO_PHYS_DISK than there is nothing
5870 5870 * else to do, just leave.
5871 5871 */
5872 5872 if (rval != DEV_INFO_SUCCESS) {
5873 5873 return;
5874 5874 }
5875 5875 }
5876 5876
5877 5877 ASSERT(ptgt->m_devhdl == topo_node->devhdl);
5878 5878
5879 5879 mutex_exit(&mpt->m_mutex);
5880 5880 flags = topo_node->flags;
5881 5881
5882 5882 if (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) {
5883 5883 phymask = ptgt->m_phymask;
5884 5884 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
5885 5885 (void) sprintf(phy_mask_name, "%x", phymask);
5886 5886 parent = scsi_hba_iport_find(mpt->m_dip,
5887 5887 phy_mask_name);
5888 5888 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
5889 5889 if (parent == NULL) {
5890 5890 mptsas_log(mpt, CE_WARN, "Failed to find a "
5891 5891 "iport for PD, should not happen!");
5892 5892 mutex_enter(&mpt->m_mutex);
5893 5893 break;
5894 5894 }
5895 5895 }
5896 5896
5897 5897 if (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
5898 5898 ndi_devi_enter(parent, &circ1);
5899 5899 (void) mptsas_config_raid(parent, topo_node->devhdl,
5900 5900 &lundip);
5901 5901 ndi_devi_exit(parent, circ1);
5902 5902 } else {
5903 5903 /*
5904 5904 * hold nexus for bus configure
5905 5905 */
5906 5906 ndi_devi_enter(scsi_vhci_dip, &circ);
5907 5907 ndi_devi_enter(parent, &circ1);
5908 5908 rval = mptsas_config_target(parent, ptgt);
5909 5909 /*
5910 5910 * release nexus for bus configure
5911 5911 */
5912 5912 ndi_devi_exit(parent, circ1);
5913 5913 ndi_devi_exit(scsi_vhci_dip, circ);
5914 5914
5915 5915 /*
5916 5916 * Add parent's props for SMHBA support
5917 5917 */
5918 5918 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
5919 5919 bzero(attached_wwnstr,
5920 5920 sizeof (attached_wwnstr));
5921 5921 (void) sprintf(attached_wwnstr, "w%016"PRIx64,
5922 5922 ptgt->m_sas_wwn);
5923 5923 if (ddi_prop_update_string(DDI_DEV_T_NONE,
5924 5924 parent,
5925 5925 SCSI_ADDR_PROP_ATTACHED_PORT,
5926 5926 attached_wwnstr)
5927 5927 != DDI_PROP_SUCCESS) {
5928 5928 (void) ddi_prop_remove(DDI_DEV_T_NONE,
5929 5929 parent,
5930 5930 SCSI_ADDR_PROP_ATTACHED_PORT);
5931 5931 mptsas_log(mpt, CE_WARN, "Failed to"
5932 5932 "attached-port props");
5933 5933 return;
5934 5934 }
5935 5935 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
5936 5936 MPTSAS_NUM_PHYS, 1) !=
5937 5937 DDI_PROP_SUCCESS) {
5938 5938 (void) ddi_prop_remove(DDI_DEV_T_NONE,
5939 5939 parent, MPTSAS_NUM_PHYS);
5940 5940 mptsas_log(mpt, CE_WARN, "Failed to"
5941 5941 " create num-phys props");
5942 5942 return;
5943 5943 }
5944 5944
5945 5945 /*
|
↓ open down ↓ |
5060 lines elided |
↑ open up ↑ |
5946 5946 * Update PHY info for smhba
5947 5947 */
5948 5948 mutex_enter(&mpt->m_mutex);
5949 5949 if (mptsas_smhba_phy_init(mpt)) {
5950 5950 mutex_exit(&mpt->m_mutex);
5951 5951 mptsas_log(mpt, CE_WARN, "mptsas phy"
5952 5952 " update failed");
5953 5953 return;
5954 5954 }
5955 5955 mutex_exit(&mpt->m_mutex);
5956 - mptsas_smhba_set_phy_props(mpt,
5957 - ddi_get_name_addr(parent), parent,
5958 - 1, &attached_devhdl);
5956 +
5957 + /*
5958 + * topo_node->un.physport is really the PHY#
5959 + * for direct attached devices
5960 + */
5961 + mptsas_smhba_set_one_phy_props(mpt, parent,
5962 + topo_node->un.physport, &attached_devhdl);
5963 +
5959 5964 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
5960 5965 MPTSAS_VIRTUAL_PORT, 0) !=
5961 5966 DDI_PROP_SUCCESS) {
5962 5967 (void) ddi_prop_remove(DDI_DEV_T_NONE,
5963 5968 parent, MPTSAS_VIRTUAL_PORT);
5964 5969 mptsas_log(mpt, CE_WARN,
5965 5970 "mptsas virtual-port"
5966 5971 "port prop update failed");
5967 5972 return;
5968 5973 }
5969 5974 }
5970 5975 }
5971 5976 mutex_enter(&mpt->m_mutex);
5972 5977
5973 5978 NDBG20(("mptsas%d handle_topo_change to online devhdl:%x, "
5974 5979 "phymask:%x.", mpt->m_instance, ptgt->m_devhdl,
5975 5980 ptgt->m_phymask));
5976 5981 break;
5977 5982 }
5978 5983 case MPTSAS_DR_EVENT_OFFLINE_TARGET:
5979 5984 {
5980 5985 mptsas_hash_table_t *tgttbl = &mpt->m_active->m_tgttbl;
5981 5986 devhdl = topo_node->devhdl;
5982 5987 ptgt = mptsas_search_by_devhdl(tgttbl, devhdl);
5983 5988 if (ptgt == NULL)
5984 5989 break;
5985 5990
5986 5991 sas_wwn = ptgt->m_sas_wwn;
5987 5992 phy = ptgt->m_phynum;
5988 5993
5989 5994 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
5990 5995
5991 5996 if (sas_wwn) {
5992 5997 (void) sprintf(addr, "w%016"PRIx64, sas_wwn);
5993 5998 } else {
5994 5999 (void) sprintf(addr, "p%x", phy);
5995 6000 }
5996 6001 ASSERT(ptgt->m_devhdl == devhdl);
5997 6002
5998 6003 if ((topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) ||
5999 6004 (topo_node->flags ==
6000 6005 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) {
6001 6006 /*
6002 6007 * Get latest RAID info if RAID volume status changes
6003 6008 * or Phys Disk status changes
6004 6009 */
6005 6010 (void) mptsas_get_raid_info(mpt);
6006 6011 }
6007 6012 /*
6008 6013 * Abort all outstanding command on the device
6009 6014 */
6010 6015 rval = mptsas_do_scsi_reset(mpt, devhdl);
6011 6016 if (rval) {
6012 6017 NDBG20(("mptsas%d handle_topo_change to reset target "
6013 6018 "before offline devhdl:%x, phymask:%x, rval:%x",
6014 6019 mpt->m_instance, ptgt->m_devhdl, ptgt->m_phymask,
6015 6020 rval));
6016 6021 }
6017 6022
6018 6023 mutex_exit(&mpt->m_mutex);
6019 6024
6020 6025 ndi_devi_enter(scsi_vhci_dip, &circ);
6021 6026 ndi_devi_enter(parent, &circ1);
6022 6027 rval = mptsas_offline_target(parent, addr);
6023 6028 ndi_devi_exit(parent, circ1);
6024 6029 ndi_devi_exit(scsi_vhci_dip, circ);
6025 6030 NDBG20(("mptsas%d handle_topo_change to offline devhdl:%x, "
6026 6031 "phymask:%x, rval:%x", mpt->m_instance,
6027 6032 ptgt->m_devhdl, ptgt->m_phymask, rval));
6028 6033
6029 6034 kmem_free(addr, SCSI_MAXNAMELEN);
6030 6035
6031 6036 /*
6032 6037 * Clear parent's props for SMHBA support
6033 6038 */
6034 6039 flags = topo_node->flags;
6035 6040 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6036 6041 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6037 6042 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent,
6038 6043 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
6039 6044 DDI_PROP_SUCCESS) {
6040 6045 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6041 6046 SCSI_ADDR_PROP_ATTACHED_PORT);
6042 6047 mptsas_log(mpt, CE_WARN, "mptsas attached port "
6043 6048 "prop update failed");
6044 6049 break;
6045 6050 }
6046 6051 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6047 6052 MPTSAS_NUM_PHYS, 0) !=
6048 6053 DDI_PROP_SUCCESS) {
6049 6054 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6050 6055 MPTSAS_NUM_PHYS);
6051 6056 mptsas_log(mpt, CE_WARN, "mptsas num phys "
6052 6057 "prop update failed");
6053 6058 break;
6054 6059 }
6055 6060 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6056 6061 MPTSAS_VIRTUAL_PORT, 1) !=
6057 6062 DDI_PROP_SUCCESS) {
6058 6063 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6059 6064 MPTSAS_VIRTUAL_PORT);
6060 6065 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
6061 6066 "prop update failed");
6062 6067 break;
6063 6068 }
6064 6069 }
6065 6070
6066 6071 mutex_enter(&mpt->m_mutex);
6067 6072 ptgt->m_led_status = 0;
6068 6073 (void) mptsas_flush_led_status(mpt, ptgt);
6069 6074 if (rval == DDI_SUCCESS) {
6070 6075 mptsas_tgt_free(&mpt->m_active->m_tgttbl,
6071 6076 ptgt->m_sas_wwn, ptgt->m_phymask);
6072 6077 ptgt = NULL;
6073 6078 } else {
6074 6079 /*
6075 6080 * clean DR_INTRANSITION flag to allow I/O down to
6076 6081 * PHCI driver since failover finished.
6077 6082 * Invalidate the devhdl
6078 6083 */
6079 6084 ptgt->m_devhdl = MPTSAS_INVALID_DEVHDL;
6080 6085 ptgt->m_tgt_unconfigured = 0;
6081 6086 mutex_enter(&mpt->m_tx_waitq_mutex);
6082 6087 ptgt->m_dr_flag = MPTSAS_DR_INACTIVE;
6083 6088 mutex_exit(&mpt->m_tx_waitq_mutex);
6084 6089 }
6085 6090
6086 6091 /*
6087 6092 * Send SAS IO Unit Control to free the dev handle
6088 6093 */
6089 6094 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6090 6095 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE)) {
6091 6096 rval = mptsas_free_devhdl(mpt, devhdl);
6092 6097
6093 6098 NDBG20(("mptsas%d handle_topo_change to remove "
6094 6099 "devhdl:%x, rval:%x", mpt->m_instance, devhdl,
6095 6100 rval));
6096 6101 }
6097 6102
6098 6103 break;
6099 6104 }
6100 6105 case MPTSAS_TOPO_FLAG_REMOVE_HANDLE:
6101 6106 {
6102 6107 devhdl = topo_node->devhdl;
6103 6108 /*
6104 6109 * If this is the remove handle event, do a reset first.
6105 6110 */
6106 6111 if (topo_node->event == MPTSAS_TOPO_FLAG_REMOVE_HANDLE) {
6107 6112 rval = mptsas_do_scsi_reset(mpt, devhdl);
6108 6113 if (rval) {
6109 6114 NDBG20(("mpt%d reset target before remove "
6110 6115 "devhdl:%x, rval:%x", mpt->m_instance,
6111 6116 devhdl, rval));
6112 6117 }
6113 6118 }
6114 6119
6115 6120 /*
6116 6121 * Send SAS IO Unit Control to free the dev handle
6117 6122 */
6118 6123 rval = mptsas_free_devhdl(mpt, devhdl);
6119 6124 NDBG20(("mptsas%d handle_topo_change to remove "
6120 6125 "devhdl:%x, rval:%x", mpt->m_instance, devhdl,
6121 6126 rval));
6122 6127 break;
6123 6128 }
6124 6129 case MPTSAS_DR_EVENT_RECONFIG_SMP:
6125 6130 {
6126 6131 mptsas_smp_t smp;
6127 6132 dev_info_t *smpdip;
6128 6133 mptsas_hash_table_t *smptbl = &mpt->m_active->m_smptbl;
6129 6134
6130 6135 devhdl = topo_node->devhdl;
6131 6136
6132 6137 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL &
6133 6138 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)devhdl;
6134 6139 rval = mptsas_get_sas_expander_page0(mpt, page_address, &smp);
6135 6140 if (rval != DDI_SUCCESS) {
6136 6141 mptsas_log(mpt, CE_WARN, "failed to online smp, "
6137 6142 "handle %x", devhdl);
6138 6143 return;
6139 6144 }
6140 6145
6141 6146 psmp = mptsas_smp_alloc(smptbl, &smp);
6142 6147 if (psmp == NULL) {
6143 6148 return;
6144 6149 }
6145 6150
6146 6151 mutex_exit(&mpt->m_mutex);
6147 6152 ndi_devi_enter(parent, &circ1);
6148 6153 (void) mptsas_online_smp(parent, psmp, &smpdip);
6149 6154 ndi_devi_exit(parent, circ1);
6150 6155
6151 6156 mutex_enter(&mpt->m_mutex);
6152 6157 break;
6153 6158 }
6154 6159 case MPTSAS_DR_EVENT_OFFLINE_SMP:
6155 6160 {
6156 6161 mptsas_hash_table_t *smptbl = &mpt->m_active->m_smptbl;
6157 6162 devhdl = topo_node->devhdl;
6158 6163 uint32_t dev_info;
6159 6164
6160 6165 psmp = mptsas_search_by_devhdl(smptbl, devhdl);
6161 6166 if (psmp == NULL)
6162 6167 break;
6163 6168 /*
6164 6169 * The mptsas_smp_t data is released only if the dip is offlined
6165 6170 * successfully.
6166 6171 */
6167 6172 mutex_exit(&mpt->m_mutex);
6168 6173
6169 6174 ndi_devi_enter(parent, &circ1);
6170 6175 rval = mptsas_offline_smp(parent, psmp, NDI_DEVI_REMOVE);
6171 6176 ndi_devi_exit(parent, circ1);
6172 6177
6173 6178 dev_info = psmp->m_deviceinfo;
6174 6179 if ((dev_info & DEVINFO_DIRECT_ATTACHED) ==
6175 6180 DEVINFO_DIRECT_ATTACHED) {
6176 6181 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6177 6182 MPTSAS_VIRTUAL_PORT, 1) !=
6178 6183 DDI_PROP_SUCCESS) {
6179 6184 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6180 6185 MPTSAS_VIRTUAL_PORT);
6181 6186 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
6182 6187 "prop update failed");
6183 6188 return;
6184 6189 }
6185 6190 /*
6186 6191 * Check whether the smp connected to the iport,
6187 6192 */
6188 6193 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6189 6194 MPTSAS_NUM_PHYS, 0) !=
6190 6195 DDI_PROP_SUCCESS) {
6191 6196 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6192 6197 MPTSAS_NUM_PHYS);
6193 6198 mptsas_log(mpt, CE_WARN, "mptsas num phys"
6194 6199 "prop update failed");
6195 6200 return;
6196 6201 }
6197 6202 /*
6198 6203 * Clear parent's attached-port props
6199 6204 */
6200 6205 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6201 6206 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent,
6202 6207 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
6203 6208 DDI_PROP_SUCCESS) {
6204 6209 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6205 6210 SCSI_ADDR_PROP_ATTACHED_PORT);
6206 6211 mptsas_log(mpt, CE_WARN, "mptsas attached port "
6207 6212 "prop update failed");
6208 6213 return;
6209 6214 }
6210 6215 }
6211 6216
6212 6217 mutex_enter(&mpt->m_mutex);
6213 6218 NDBG20(("mptsas%d handle_topo_change to remove devhdl:%x, "
6214 6219 "rval:%x", mpt->m_instance, psmp->m_devhdl, rval));
6215 6220 if (rval == DDI_SUCCESS) {
6216 6221 mptsas_smp_free(smptbl, psmp->m_sasaddr,
6217 6222 psmp->m_phymask);
6218 6223 } else {
6219 6224 psmp->m_devhdl = MPTSAS_INVALID_DEVHDL;
6220 6225 }
6221 6226
6222 6227 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6223 6228
6224 6229 break;
6225 6230 }
6226 6231 default:
6227 6232 return;
6228 6233 }
6229 6234 }
6230 6235
6231 6236 /*
6232 6237 * Record the event if its type is enabled in mpt instance by ioctl.
6233 6238 */
6234 6239 static void
6235 6240 mptsas_record_event(void *args)
6236 6241 {
6237 6242 m_replyh_arg_t *replyh_arg;
6238 6243 pMpi2EventNotificationReply_t eventreply;
6239 6244 uint32_t event, rfm;
6240 6245 mptsas_t *mpt;
6241 6246 int i, j;
6242 6247 uint16_t event_data_len;
6243 6248 boolean_t sendAEN = FALSE;
6244 6249
6245 6250 replyh_arg = (m_replyh_arg_t *)args;
6246 6251 rfm = replyh_arg->rfm;
6247 6252 mpt = replyh_arg->mpt;
6248 6253
6249 6254 eventreply = (pMpi2EventNotificationReply_t)
6250 6255 (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr));
6251 6256 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
6252 6257
6253 6258
6254 6259 /*
6255 6260 * Generate a system event to let anyone who cares know that a
6256 6261 * LOG_ENTRY_ADDED event has occurred. This is sent no matter what the
6257 6262 * event mask is set to.
6258 6263 */
6259 6264 if (event == MPI2_EVENT_LOG_ENTRY_ADDED) {
6260 6265 sendAEN = TRUE;
6261 6266 }
6262 6267
6263 6268 /*
6264 6269 * Record the event only if it is not masked. Determine which dword
6265 6270 * and bit of event mask to test.
6266 6271 */
6267 6272 i = (uint8_t)(event / 32);
6268 6273 j = (uint8_t)(event % 32);
6269 6274 if ((i < 4) && ((1 << j) & mpt->m_event_mask[i])) {
6270 6275 i = mpt->m_event_index;
6271 6276 mpt->m_events[i].Type = event;
6272 6277 mpt->m_events[i].Number = ++mpt->m_event_number;
6273 6278 bzero(mpt->m_events[i].Data, MPTSAS_MAX_EVENT_DATA_LENGTH * 4);
6274 6279 event_data_len = ddi_get16(mpt->m_acc_reply_frame_hdl,
6275 6280 &eventreply->EventDataLength);
6276 6281
6277 6282 if (event_data_len > 0) {
6278 6283 /*
6279 6284 * Limit data to size in m_event entry
6280 6285 */
6281 6286 if (event_data_len > MPTSAS_MAX_EVENT_DATA_LENGTH) {
6282 6287 event_data_len = MPTSAS_MAX_EVENT_DATA_LENGTH;
6283 6288 }
6284 6289 for (j = 0; j < event_data_len; j++) {
6285 6290 mpt->m_events[i].Data[j] =
6286 6291 ddi_get32(mpt->m_acc_reply_frame_hdl,
6287 6292 &(eventreply->EventData[j]));
6288 6293 }
6289 6294
6290 6295 /*
6291 6296 * check for index wrap-around
6292 6297 */
6293 6298 if (++i == MPTSAS_EVENT_QUEUE_SIZE) {
6294 6299 i = 0;
6295 6300 }
6296 6301 mpt->m_event_index = (uint8_t)i;
6297 6302
6298 6303 /*
6299 6304 * Set flag to send the event.
6300 6305 */
6301 6306 sendAEN = TRUE;
6302 6307 }
6303 6308 }
6304 6309
6305 6310 /*
6306 6311 * Generate a system event if flag is set to let anyone who cares know
6307 6312 * that an event has occurred.
6308 6313 */
6309 6314 if (sendAEN) {
6310 6315 (void) ddi_log_sysevent(mpt->m_dip, DDI_VENDOR_LSI, "MPT_SAS",
6311 6316 "SAS", NULL, NULL, DDI_NOSLEEP);
6312 6317 }
6313 6318 }
6314 6319
6315 6320 #define SMP_RESET_IN_PROGRESS MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS
6316 6321 /*
6317 6322 * handle sync events from ioc in interrupt
6318 6323 * return value:
6319 6324 * DDI_SUCCESS: The event is handled by this func
6320 6325 * DDI_FAILURE: Event is not handled
6321 6326 */
6322 6327 static int
6323 6328 mptsas_handle_event_sync(void *args)
6324 6329 {
6325 6330 m_replyh_arg_t *replyh_arg;
6326 6331 pMpi2EventNotificationReply_t eventreply;
6327 6332 uint32_t event, rfm;
6328 6333 mptsas_t *mpt;
6329 6334 uint_t iocstatus;
6330 6335
6331 6336 replyh_arg = (m_replyh_arg_t *)args;
6332 6337 rfm = replyh_arg->rfm;
6333 6338 mpt = replyh_arg->mpt;
6334 6339
6335 6340 ASSERT(mutex_owned(&mpt->m_mutex));
6336 6341
6337 6342 eventreply = (pMpi2EventNotificationReply_t)
6338 6343 (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr));
6339 6344 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
6340 6345
6341 6346 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
6342 6347 &eventreply->IOCStatus)) {
6343 6348 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
6344 6349 mptsas_log(mpt, CE_WARN,
6345 6350 "!mptsas_handle_event_sync: IOCStatus=0x%x, "
6346 6351 "IOCLogInfo=0x%x", iocstatus,
6347 6352 ddi_get32(mpt->m_acc_reply_frame_hdl,
6348 6353 &eventreply->IOCLogInfo));
6349 6354 } else {
6350 6355 mptsas_log(mpt, CE_WARN,
6351 6356 "mptsas_handle_event_sync: IOCStatus=0x%x, "
6352 6357 "IOCLogInfo=0x%x", iocstatus,
6353 6358 ddi_get32(mpt->m_acc_reply_frame_hdl,
6354 6359 &eventreply->IOCLogInfo));
6355 6360 }
6356 6361 }
6357 6362
6358 6363 /*
6359 6364 * figure out what kind of event we got and handle accordingly
6360 6365 */
6361 6366 switch (event) {
6362 6367 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
6363 6368 {
6364 6369 pMpi2EventDataSasTopologyChangeList_t sas_topo_change_list;
6365 6370 uint8_t num_entries, expstatus, phy;
6366 6371 uint8_t phystatus, physport, state, i;
6367 6372 uint8_t start_phy_num, link_rate;
6368 6373 uint16_t dev_handle, reason_code;
6369 6374 uint16_t enc_handle, expd_handle;
6370 6375 char string[80], curr[80], prev[80];
6371 6376 mptsas_topo_change_list_t *topo_head = NULL;
6372 6377 mptsas_topo_change_list_t *topo_tail = NULL;
6373 6378 mptsas_topo_change_list_t *topo_node = NULL;
6374 6379 mptsas_target_t *ptgt;
6375 6380 mptsas_smp_t *psmp;
6376 6381 mptsas_hash_table_t *tgttbl, *smptbl;
6377 6382 uint8_t flags = 0, exp_flag;
6378 6383 smhba_info_t *pSmhba = NULL;
6379 6384
6380 6385 NDBG20(("mptsas_handle_event_sync: SAS topology change"));
6381 6386
6382 6387 tgttbl = &mpt->m_active->m_tgttbl;
6383 6388 smptbl = &mpt->m_active->m_smptbl;
6384 6389
6385 6390 sas_topo_change_list = (pMpi2EventDataSasTopologyChangeList_t)
6386 6391 eventreply->EventData;
6387 6392
6388 6393 enc_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6389 6394 &sas_topo_change_list->EnclosureHandle);
6390 6395 expd_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6391 6396 &sas_topo_change_list->ExpanderDevHandle);
6392 6397 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl,
6393 6398 &sas_topo_change_list->NumEntries);
6394 6399 start_phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl,
6395 6400 &sas_topo_change_list->StartPhyNum);
6396 6401 expstatus = ddi_get8(mpt->m_acc_reply_frame_hdl,
6397 6402 &sas_topo_change_list->ExpStatus);
6398 6403 physport = ddi_get8(mpt->m_acc_reply_frame_hdl,
6399 6404 &sas_topo_change_list->PhysicalPort);
6400 6405
6401 6406 string[0] = 0;
6402 6407 if (expd_handle) {
6403 6408 flags = MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED;
6404 6409 switch (expstatus) {
6405 6410 case MPI2_EVENT_SAS_TOPO_ES_ADDED:
6406 6411 (void) sprintf(string, " added");
6407 6412 /*
6408 6413 * New expander device added
6409 6414 */
6410 6415 mpt->m_port_chng = 1;
6411 6416 topo_node = kmem_zalloc(
6412 6417 sizeof (mptsas_topo_change_list_t),
6413 6418 KM_SLEEP);
6414 6419 topo_node->mpt = mpt;
6415 6420 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_SMP;
6416 6421 topo_node->un.physport = physport;
6417 6422 topo_node->devhdl = expd_handle;
6418 6423 topo_node->flags = flags;
6419 6424 topo_node->object = NULL;
6420 6425 if (topo_head == NULL) {
6421 6426 topo_head = topo_tail = topo_node;
6422 6427 } else {
6423 6428 topo_tail->next = topo_node;
6424 6429 topo_tail = topo_node;
6425 6430 }
6426 6431 break;
6427 6432 case MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING:
6428 6433 (void) sprintf(string, " not responding, "
6429 6434 "removed");
6430 6435 psmp = mptsas_search_by_devhdl(smptbl,
6431 6436 expd_handle);
6432 6437 if (psmp == NULL)
6433 6438 break;
6434 6439
6435 6440 topo_node = kmem_zalloc(
6436 6441 sizeof (mptsas_topo_change_list_t),
6437 6442 KM_SLEEP);
6438 6443 topo_node->mpt = mpt;
6439 6444 topo_node->un.phymask = psmp->m_phymask;
6440 6445 topo_node->event = MPTSAS_DR_EVENT_OFFLINE_SMP;
6441 6446 topo_node->devhdl = expd_handle;
6442 6447 topo_node->flags = flags;
6443 6448 topo_node->object = NULL;
6444 6449 if (topo_head == NULL) {
6445 6450 topo_head = topo_tail = topo_node;
6446 6451 } else {
6447 6452 topo_tail->next = topo_node;
6448 6453 topo_tail = topo_node;
6449 6454 }
6450 6455 break;
6451 6456 case MPI2_EVENT_SAS_TOPO_ES_RESPONDING:
6452 6457 break;
6453 6458 case MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING:
6454 6459 (void) sprintf(string, " not responding, "
6455 6460 "delaying removal");
6456 6461 break;
6457 6462 default:
6458 6463 break;
6459 6464 }
6460 6465 } else {
6461 6466 flags = MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE;
6462 6467 }
6463 6468
6464 6469 NDBG20(("SAS TOPOLOGY CHANGE for enclosure %x expander %x%s\n",
6465 6470 enc_handle, expd_handle, string));
6466 6471 for (i = 0; i < num_entries; i++) {
6467 6472 phy = i + start_phy_num;
6468 6473 phystatus = ddi_get8(mpt->m_acc_reply_frame_hdl,
6469 6474 &sas_topo_change_list->PHY[i].PhyStatus);
6470 6475 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6471 6476 &sas_topo_change_list->PHY[i].AttachedDevHandle);
6472 6477 reason_code = phystatus & MPI2_EVENT_SAS_TOPO_RC_MASK;
6473 6478 /*
6474 6479 * Filter out processing of Phy Vacant Status unless
6475 6480 * the reason code is "Not Responding". Process all
6476 6481 * other combinations of Phy Status and Reason Codes.
6477 6482 */
6478 6483 if ((phystatus &
6479 6484 MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT) &&
6480 6485 (reason_code !=
6481 6486 MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING)) {
6482 6487 continue;
6483 6488 }
6484 6489 curr[0] = 0;
6485 6490 prev[0] = 0;
6486 6491 string[0] = 0;
6487 6492 switch (reason_code) {
6488 6493 case MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED:
6489 6494 {
6490 6495 NDBG20(("mptsas%d phy %d physical_port %d "
6491 6496 "dev_handle %d added", mpt->m_instance, phy,
6492 6497 physport, dev_handle));
6493 6498 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl,
6494 6499 &sas_topo_change_list->PHY[i].LinkRate);
6495 6500 state = (link_rate &
6496 6501 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >>
6497 6502 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT;
6498 6503 switch (state) {
6499 6504 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
6500 6505 (void) sprintf(curr, "is disabled");
6501 6506 break;
6502 6507 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
6503 6508 (void) sprintf(curr, "is offline, "
6504 6509 "failed speed negotiation");
6505 6510 break;
6506 6511 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
6507 6512 (void) sprintf(curr, "SATA OOB "
6508 6513 "complete");
6509 6514 break;
6510 6515 case SMP_RESET_IN_PROGRESS:
6511 6516 (void) sprintf(curr, "SMP reset in "
6512 6517 "progress");
6513 6518 break;
6514 6519 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
6515 6520 (void) sprintf(curr, "is online at "
6516 6521 "1.5 Gbps");
6517 6522 break;
6518 6523 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
6519 6524 (void) sprintf(curr, "is online at 3.0 "
6520 6525 "Gbps");
6521 6526 break;
6522 6527 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
6523 6528 (void) sprintf(curr, "is online at 6.0 "
6524 6529 "Gbps");
6525 6530 break;
6526 6531 default:
6527 6532 (void) sprintf(curr, "state is "
6528 6533 "unknown");
6529 6534 break;
6530 6535 }
6531 6536 /*
6532 6537 * New target device added into the system.
6533 6538 * Set association flag according to if an
6534 6539 * expander is used or not.
6535 6540 */
6536 6541 exp_flag =
6537 6542 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE;
6538 6543 if (flags ==
6539 6544 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) {
6540 6545 flags = exp_flag;
6541 6546 }
6542 6547 topo_node = kmem_zalloc(
6543 6548 sizeof (mptsas_topo_change_list_t),
6544 6549 KM_SLEEP);
6545 6550 topo_node->mpt = mpt;
6546 6551 topo_node->event =
6547 6552 MPTSAS_DR_EVENT_RECONFIG_TARGET;
6548 6553 if (expd_handle == 0) {
6549 6554 /*
6550 6555 * Per MPI 2, if expander dev handle
6551 6556 * is 0, it's a directly attached
6552 6557 * device. So driver use PHY to decide
6553 6558 * which iport is associated
6554 6559 */
6555 6560 physport = phy;
6556 6561 mpt->m_port_chng = 1;
6557 6562 }
6558 6563 topo_node->un.physport = physport;
6559 6564 topo_node->devhdl = dev_handle;
6560 6565 topo_node->flags = flags;
6561 6566 topo_node->object = NULL;
6562 6567 if (topo_head == NULL) {
6563 6568 topo_head = topo_tail = topo_node;
6564 6569 } else {
6565 6570 topo_tail->next = topo_node;
6566 6571 topo_tail = topo_node;
6567 6572 }
6568 6573 break;
6569 6574 }
6570 6575 case MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING:
6571 6576 {
6572 6577 NDBG20(("mptsas%d phy %d physical_port %d "
6573 6578 "dev_handle %d removed", mpt->m_instance,
6574 6579 phy, physport, dev_handle));
6575 6580 /*
6576 6581 * Set association flag according to if an
6577 6582 * expander is used or not.
6578 6583 */
6579 6584 exp_flag =
6580 6585 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE;
6581 6586 if (flags ==
6582 6587 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) {
6583 6588 flags = exp_flag;
6584 6589 }
6585 6590 /*
6586 6591 * Target device is removed from the system
6587 6592 * Before the device is really offline from
6588 6593 * from system.
6589 6594 */
6590 6595 ptgt = mptsas_search_by_devhdl(tgttbl,
6591 6596 dev_handle);
6592 6597 /*
6593 6598 * If ptgt is NULL here, it means that the
6594 6599 * DevHandle is not in the hash table. This is
6595 6600 * reasonable sometimes. For example, if a
6596 6601 * disk was pulled, then added, then pulled
6597 6602 * again, the disk will not have been put into
6598 6603 * the hash table because the add event will
6599 6604 * have an invalid phymask. BUT, this does not
6600 6605 * mean that the DevHandle is invalid. The
6601 6606 * controller will still have a valid DevHandle
6602 6607 * that must be removed. To do this, use the
6603 6608 * MPTSAS_TOPO_FLAG_REMOVE_HANDLE event.
6604 6609 */
6605 6610 if (ptgt == NULL) {
6606 6611 topo_node = kmem_zalloc(
6607 6612 sizeof (mptsas_topo_change_list_t),
6608 6613 KM_SLEEP);
6609 6614 topo_node->mpt = mpt;
6610 6615 topo_node->un.phymask = 0;
6611 6616 topo_node->event =
6612 6617 MPTSAS_TOPO_FLAG_REMOVE_HANDLE;
6613 6618 topo_node->devhdl = dev_handle;
6614 6619 topo_node->flags = flags;
6615 6620 topo_node->object = NULL;
6616 6621 if (topo_head == NULL) {
6617 6622 topo_head = topo_tail =
6618 6623 topo_node;
6619 6624 } else {
6620 6625 topo_tail->next = topo_node;
6621 6626 topo_tail = topo_node;
6622 6627 }
6623 6628 break;
6624 6629 }
6625 6630
6626 6631 /*
6627 6632 * Update DR flag immediately avoid I/O failure
6628 6633 * before failover finish. Pay attention to the
6629 6634 * mutex protect, we need grab m_tx_waitq_mutex
6630 6635 * during set m_dr_flag because we won't add
6631 6636 * the following command into waitq, instead,
6632 6637 * we need return TRAN_BUSY in the tran_start
6633 6638 * context.
6634 6639 */
6635 6640 mutex_enter(&mpt->m_tx_waitq_mutex);
6636 6641 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
6637 6642 mutex_exit(&mpt->m_tx_waitq_mutex);
6638 6643
6639 6644 topo_node = kmem_zalloc(
6640 6645 sizeof (mptsas_topo_change_list_t),
6641 6646 KM_SLEEP);
6642 6647 topo_node->mpt = mpt;
6643 6648 topo_node->un.phymask = ptgt->m_phymask;
6644 6649 topo_node->event =
6645 6650 MPTSAS_DR_EVENT_OFFLINE_TARGET;
6646 6651 topo_node->devhdl = dev_handle;
6647 6652 topo_node->flags = flags;
6648 6653 topo_node->object = NULL;
6649 6654 if (topo_head == NULL) {
6650 6655 topo_head = topo_tail = topo_node;
6651 6656 } else {
6652 6657 topo_tail->next = topo_node;
6653 6658 topo_tail = topo_node;
6654 6659 }
6655 6660 break;
6656 6661 }
6657 6662 case MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED:
6658 6663 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl,
6659 6664 &sas_topo_change_list->PHY[i].LinkRate);
6660 6665 state = (link_rate &
6661 6666 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >>
6662 6667 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT;
6663 6668 pSmhba = &mpt->m_phy_info[i].smhba_info;
6664 6669 pSmhba->negotiated_link_rate = state;
6665 6670 switch (state) {
6666 6671 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
6667 6672 (void) sprintf(curr, "is disabled");
6668 6673 mptsas_smhba_log_sysevent(mpt,
6669 6674 ESC_SAS_PHY_EVENT,
6670 6675 SAS_PHY_REMOVE,
6671 6676 &mpt->m_phy_info[i].smhba_info);
6672 6677 mpt->m_phy_info[i].smhba_info.
6673 6678 negotiated_link_rate
6674 6679 = 0x1;
6675 6680 break;
6676 6681 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
6677 6682 (void) sprintf(curr, "is offline, "
6678 6683 "failed speed negotiation");
6679 6684 mptsas_smhba_log_sysevent(mpt,
6680 6685 ESC_SAS_PHY_EVENT,
6681 6686 SAS_PHY_OFFLINE,
6682 6687 &mpt->m_phy_info[i].smhba_info);
6683 6688 break;
6684 6689 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
6685 6690 (void) sprintf(curr, "SATA OOB "
6686 6691 "complete");
6687 6692 break;
6688 6693 case SMP_RESET_IN_PROGRESS:
6689 6694 (void) sprintf(curr, "SMP reset in "
6690 6695 "progress");
6691 6696 break;
6692 6697 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
6693 6698 (void) sprintf(curr, "is online at "
6694 6699 "1.5 Gbps");
6695 6700 if ((expd_handle == 0) &&
6696 6701 (enc_handle == 1)) {
6697 6702 mpt->m_port_chng = 1;
6698 6703 }
6699 6704 mptsas_smhba_log_sysevent(mpt,
6700 6705 ESC_SAS_PHY_EVENT,
6701 6706 SAS_PHY_ONLINE,
6702 6707 &mpt->m_phy_info[i].smhba_info);
6703 6708 break;
6704 6709 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
6705 6710 (void) sprintf(curr, "is online at 3.0 "
6706 6711 "Gbps");
6707 6712 if ((expd_handle == 0) &&
6708 6713 (enc_handle == 1)) {
6709 6714 mpt->m_port_chng = 1;
6710 6715 }
6711 6716 mptsas_smhba_log_sysevent(mpt,
6712 6717 ESC_SAS_PHY_EVENT,
6713 6718 SAS_PHY_ONLINE,
6714 6719 &mpt->m_phy_info[i].smhba_info);
6715 6720 break;
6716 6721 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
6717 6722 (void) sprintf(curr, "is online at "
6718 6723 "6.0 Gbps");
6719 6724 if ((expd_handle == 0) &&
6720 6725 (enc_handle == 1)) {
6721 6726 mpt->m_port_chng = 1;
6722 6727 }
6723 6728 mptsas_smhba_log_sysevent(mpt,
6724 6729 ESC_SAS_PHY_EVENT,
6725 6730 SAS_PHY_ONLINE,
6726 6731 &mpt->m_phy_info[i].smhba_info);
6727 6732 break;
6728 6733 default:
6729 6734 (void) sprintf(curr, "state is "
6730 6735 "unknown");
6731 6736 break;
6732 6737 }
6733 6738
6734 6739 state = (link_rate &
6735 6740 MPI2_EVENT_SAS_TOPO_LR_PREV_MASK) >>
6736 6741 MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT;
6737 6742 switch (state) {
6738 6743 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
6739 6744 (void) sprintf(prev, ", was disabled");
6740 6745 break;
6741 6746 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
6742 6747 (void) sprintf(prev, ", was offline, "
6743 6748 "failed speed negotiation");
6744 6749 break;
6745 6750 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
6746 6751 (void) sprintf(prev, ", was SATA OOB "
6747 6752 "complete");
6748 6753 break;
6749 6754 case SMP_RESET_IN_PROGRESS:
6750 6755 (void) sprintf(prev, ", was SMP reset "
6751 6756 "in progress");
6752 6757 break;
6753 6758 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
6754 6759 (void) sprintf(prev, ", was online at "
6755 6760 "1.5 Gbps");
6756 6761 break;
6757 6762 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
6758 6763 (void) sprintf(prev, ", was online at "
6759 6764 "3.0 Gbps");
6760 6765 break;
6761 6766 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
6762 6767 (void) sprintf(prev, ", was online at "
6763 6768 "6.0 Gbps");
6764 6769 break;
6765 6770 default:
6766 6771 break;
6767 6772 }
6768 6773 (void) sprintf(&string[strlen(string)], "link "
6769 6774 "changed, ");
6770 6775 break;
6771 6776 case MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE:
6772 6777 continue;
6773 6778 case MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING:
6774 6779 (void) sprintf(&string[strlen(string)],
6775 6780 "target not responding, delaying "
6776 6781 "removal");
6777 6782 break;
6778 6783 }
6779 6784 NDBG20(("mptsas%d phy %d DevHandle %x, %s%s%s\n",
6780 6785 mpt->m_instance, phy, dev_handle, string, curr,
6781 6786 prev));
6782 6787 }
6783 6788 if (topo_head != NULL) {
6784 6789 /*
6785 6790 * Launch DR taskq to handle topology change
6786 6791 */
6787 6792 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
6788 6793 mptsas_handle_dr, (void *)topo_head,
6789 6794 DDI_NOSLEEP)) != DDI_SUCCESS) {
6790 6795 mptsas_log(mpt, CE_NOTE, "mptsas start taskq "
6791 6796 "for handle SAS DR event failed. \n");
6792 6797 }
6793 6798 }
6794 6799 break;
6795 6800 }
6796 6801 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
6797 6802 {
6798 6803 Mpi2EventDataIrConfigChangeList_t *irChangeList;
6799 6804 mptsas_topo_change_list_t *topo_head = NULL;
6800 6805 mptsas_topo_change_list_t *topo_tail = NULL;
6801 6806 mptsas_topo_change_list_t *topo_node = NULL;
6802 6807 mptsas_target_t *ptgt;
6803 6808 mptsas_hash_table_t *tgttbl;
6804 6809 uint8_t num_entries, i, reason;
6805 6810 uint16_t volhandle, diskhandle;
6806 6811
6807 6812 irChangeList = (pMpi2EventDataIrConfigChangeList_t)
6808 6813 eventreply->EventData;
6809 6814 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl,
6810 6815 &irChangeList->NumElements);
6811 6816
6812 6817 tgttbl = &mpt->m_active->m_tgttbl;
6813 6818
6814 6819 NDBG20(("mptsas%d IR_CONFIGURATION_CHANGE_LIST event received",
6815 6820 mpt->m_instance));
6816 6821
6817 6822 for (i = 0; i < num_entries; i++) {
6818 6823 reason = ddi_get8(mpt->m_acc_reply_frame_hdl,
6819 6824 &irChangeList->ConfigElement[i].ReasonCode);
6820 6825 volhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6821 6826 &irChangeList->ConfigElement[i].VolDevHandle);
6822 6827 diskhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6823 6828 &irChangeList->ConfigElement[i].PhysDiskDevHandle);
6824 6829
6825 6830 switch (reason) {
6826 6831 case MPI2_EVENT_IR_CHANGE_RC_ADDED:
6827 6832 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED:
6828 6833 {
6829 6834 NDBG20(("mptsas %d volume added\n",
6830 6835 mpt->m_instance));
6831 6836
6832 6837 topo_node = kmem_zalloc(
6833 6838 sizeof (mptsas_topo_change_list_t),
6834 6839 KM_SLEEP);
6835 6840
6836 6841 topo_node->mpt = mpt;
6837 6842 topo_node->event =
6838 6843 MPTSAS_DR_EVENT_RECONFIG_TARGET;
6839 6844 topo_node->un.physport = 0xff;
6840 6845 topo_node->devhdl = volhandle;
6841 6846 topo_node->flags =
6842 6847 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED;
6843 6848 topo_node->object = NULL;
6844 6849 if (topo_head == NULL) {
6845 6850 topo_head = topo_tail = topo_node;
6846 6851 } else {
6847 6852 topo_tail->next = topo_node;
6848 6853 topo_tail = topo_node;
6849 6854 }
6850 6855 break;
6851 6856 }
6852 6857 case MPI2_EVENT_IR_CHANGE_RC_REMOVED:
6853 6858 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED:
6854 6859 {
6855 6860 NDBG20(("mptsas %d volume deleted\n",
6856 6861 mpt->m_instance));
6857 6862 ptgt = mptsas_search_by_devhdl(tgttbl,
6858 6863 volhandle);
6859 6864 if (ptgt == NULL)
6860 6865 break;
6861 6866
6862 6867 /*
6863 6868 * Clear any flags related to volume
6864 6869 */
6865 6870 (void) mptsas_delete_volume(mpt, volhandle);
6866 6871
6867 6872 /*
6868 6873 * Update DR flag immediately avoid I/O failure
6869 6874 */
6870 6875 mutex_enter(&mpt->m_tx_waitq_mutex);
6871 6876 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
6872 6877 mutex_exit(&mpt->m_tx_waitq_mutex);
6873 6878
6874 6879 topo_node = kmem_zalloc(
6875 6880 sizeof (mptsas_topo_change_list_t),
6876 6881 KM_SLEEP);
6877 6882 topo_node->mpt = mpt;
6878 6883 topo_node->un.phymask = ptgt->m_phymask;
6879 6884 topo_node->event =
6880 6885 MPTSAS_DR_EVENT_OFFLINE_TARGET;
6881 6886 topo_node->devhdl = volhandle;
6882 6887 topo_node->flags =
6883 6888 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED;
6884 6889 topo_node->object = (void *)ptgt;
6885 6890 if (topo_head == NULL) {
6886 6891 topo_head = topo_tail = topo_node;
6887 6892 } else {
6888 6893 topo_tail->next = topo_node;
6889 6894 topo_tail = topo_node;
6890 6895 }
6891 6896 break;
6892 6897 }
6893 6898 case MPI2_EVENT_IR_CHANGE_RC_PD_CREATED:
6894 6899 case MPI2_EVENT_IR_CHANGE_RC_HIDE:
6895 6900 {
6896 6901 ptgt = mptsas_search_by_devhdl(tgttbl,
6897 6902 diskhandle);
6898 6903 if (ptgt == NULL)
6899 6904 break;
6900 6905
6901 6906 /*
6902 6907 * Update DR flag immediately avoid I/O failure
6903 6908 */
6904 6909 mutex_enter(&mpt->m_tx_waitq_mutex);
6905 6910 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
6906 6911 mutex_exit(&mpt->m_tx_waitq_mutex);
6907 6912
6908 6913 topo_node = kmem_zalloc(
6909 6914 sizeof (mptsas_topo_change_list_t),
6910 6915 KM_SLEEP);
6911 6916 topo_node->mpt = mpt;
6912 6917 topo_node->un.phymask = ptgt->m_phymask;
6913 6918 topo_node->event =
6914 6919 MPTSAS_DR_EVENT_OFFLINE_TARGET;
6915 6920 topo_node->devhdl = diskhandle;
6916 6921 topo_node->flags =
6917 6922 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED;
6918 6923 topo_node->object = (void *)ptgt;
6919 6924 if (topo_head == NULL) {
6920 6925 topo_head = topo_tail = topo_node;
6921 6926 } else {
6922 6927 topo_tail->next = topo_node;
6923 6928 topo_tail = topo_node;
6924 6929 }
6925 6930 break;
6926 6931 }
6927 6932 case MPI2_EVENT_IR_CHANGE_RC_UNHIDE:
6928 6933 case MPI2_EVENT_IR_CHANGE_RC_PD_DELETED:
6929 6934 {
6930 6935 /*
6931 6936 * The physical drive is released by a IR
6932 6937 * volume. But we cannot get the the physport
6933 6938 * or phynum from the event data, so we only
6934 6939 * can get the physport/phynum after SAS
6935 6940 * Device Page0 request for the devhdl.
6936 6941 */
6937 6942 topo_node = kmem_zalloc(
6938 6943 sizeof (mptsas_topo_change_list_t),
6939 6944 KM_SLEEP);
6940 6945 topo_node->mpt = mpt;
6941 6946 topo_node->un.phymask = 0;
6942 6947 topo_node->event =
6943 6948 MPTSAS_DR_EVENT_RECONFIG_TARGET;
6944 6949 topo_node->devhdl = diskhandle;
6945 6950 topo_node->flags =
6946 6951 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED;
6947 6952 topo_node->object = NULL;
6948 6953 mpt->m_port_chng = 1;
6949 6954 if (topo_head == NULL) {
6950 6955 topo_head = topo_tail = topo_node;
6951 6956 } else {
6952 6957 topo_tail->next = topo_node;
6953 6958 topo_tail = topo_node;
6954 6959 }
6955 6960 break;
6956 6961 }
6957 6962 default:
6958 6963 break;
6959 6964 }
6960 6965 }
6961 6966
6962 6967 if (topo_head != NULL) {
6963 6968 /*
6964 6969 * Launch DR taskq to handle topology change
6965 6970 */
6966 6971 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
6967 6972 mptsas_handle_dr, (void *)topo_head,
6968 6973 DDI_NOSLEEP)) != DDI_SUCCESS) {
6969 6974 mptsas_log(mpt, CE_NOTE, "mptsas start taskq "
6970 6975 "for handle SAS DR event failed. \n");
6971 6976 }
6972 6977 }
6973 6978 break;
6974 6979 }
6975 6980 default:
6976 6981 return (DDI_FAILURE);
6977 6982 }
6978 6983
6979 6984 return (DDI_SUCCESS);
6980 6985 }
6981 6986
6982 6987 /*
6983 6988 * handle events from ioc
6984 6989 */
6985 6990 static void
6986 6991 mptsas_handle_event(void *args)
6987 6992 {
6988 6993 m_replyh_arg_t *replyh_arg;
6989 6994 pMpi2EventNotificationReply_t eventreply;
6990 6995 uint32_t event, iocloginfo, rfm;
6991 6996 uint32_t status;
6992 6997 uint8_t port;
6993 6998 mptsas_t *mpt;
6994 6999 uint_t iocstatus;
6995 7000
6996 7001 replyh_arg = (m_replyh_arg_t *)args;
6997 7002 rfm = replyh_arg->rfm;
6998 7003 mpt = replyh_arg->mpt;
6999 7004
7000 7005 mutex_enter(&mpt->m_mutex);
7001 7006 /*
7002 7007 * If HBA is being reset, drop incoming event.
7003 7008 */
7004 7009 if (mpt->m_in_reset) {
7005 7010 NDBG20(("dropping event received prior to reset"));
7006 7011 mutex_exit(&mpt->m_mutex);
7007 7012 return;
7008 7013 }
7009 7014
7010 7015 eventreply = (pMpi2EventNotificationReply_t)
7011 7016 (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr));
7012 7017 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
7013 7018
7014 7019 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
7015 7020 &eventreply->IOCStatus)) {
7016 7021 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
7017 7022 mptsas_log(mpt, CE_WARN,
7018 7023 "!mptsas_handle_event: IOCStatus=0x%x, "
7019 7024 "IOCLogInfo=0x%x", iocstatus,
7020 7025 ddi_get32(mpt->m_acc_reply_frame_hdl,
7021 7026 &eventreply->IOCLogInfo));
7022 7027 } else {
7023 7028 mptsas_log(mpt, CE_WARN,
7024 7029 "mptsas_handle_event: IOCStatus=0x%x, "
7025 7030 "IOCLogInfo=0x%x", iocstatus,
7026 7031 ddi_get32(mpt->m_acc_reply_frame_hdl,
7027 7032 &eventreply->IOCLogInfo));
7028 7033 }
7029 7034 }
7030 7035
7031 7036 /*
7032 7037 * figure out what kind of event we got and handle accordingly
7033 7038 */
7034 7039 switch (event) {
7035 7040 case MPI2_EVENT_LOG_ENTRY_ADDED:
7036 7041 break;
7037 7042 case MPI2_EVENT_LOG_DATA:
7038 7043 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
7039 7044 &eventreply->IOCLogInfo);
7040 7045 NDBG20(("mptsas %d log info %x received.\n", mpt->m_instance,
7041 7046 iocloginfo));
7042 7047 break;
7043 7048 case MPI2_EVENT_STATE_CHANGE:
7044 7049 NDBG20(("mptsas%d state change.", mpt->m_instance));
7045 7050 break;
7046 7051 case MPI2_EVENT_HARD_RESET_RECEIVED:
7047 7052 NDBG20(("mptsas%d event change.", mpt->m_instance));
7048 7053 break;
7049 7054 case MPI2_EVENT_SAS_DISCOVERY:
7050 7055 {
7051 7056 MPI2_EVENT_DATA_SAS_DISCOVERY *sasdiscovery;
7052 7057 char string[80];
7053 7058 uint8_t rc;
7054 7059
7055 7060 sasdiscovery =
7056 7061 (pMpi2EventDataSasDiscovery_t)eventreply->EventData;
7057 7062
7058 7063 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7059 7064 &sasdiscovery->ReasonCode);
7060 7065 port = ddi_get8(mpt->m_acc_reply_frame_hdl,
7061 7066 &sasdiscovery->PhysicalPort);
7062 7067 status = ddi_get32(mpt->m_acc_reply_frame_hdl,
7063 7068 &sasdiscovery->DiscoveryStatus);
7064 7069
7065 7070 string[0] = 0;
7066 7071 switch (rc) {
7067 7072 case MPI2_EVENT_SAS_DISC_RC_STARTED:
7068 7073 (void) sprintf(string, "STARTING");
7069 7074 break;
7070 7075 case MPI2_EVENT_SAS_DISC_RC_COMPLETED:
7071 7076 (void) sprintf(string, "COMPLETED");
7072 7077 break;
7073 7078 default:
7074 7079 (void) sprintf(string, "UNKNOWN");
7075 7080 break;
7076 7081 }
7077 7082
7078 7083 NDBG20(("SAS DISCOVERY is %s for port %d, status %x", string,
7079 7084 port, status));
7080 7085
7081 7086 break;
7082 7087 }
7083 7088 case MPI2_EVENT_EVENT_CHANGE:
7084 7089 NDBG20(("mptsas%d event change.", mpt->m_instance));
7085 7090 break;
7086 7091 case MPI2_EVENT_TASK_SET_FULL:
7087 7092 {
7088 7093 pMpi2EventDataTaskSetFull_t taskfull;
7089 7094
7090 7095 taskfull = (pMpi2EventDataTaskSetFull_t)eventreply->EventData;
7091 7096
7092 7097 NDBG20(("TASK_SET_FULL received for mptsas%d, depth %d\n",
7093 7098 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl,
7094 7099 &taskfull->CurrentDepth)));
7095 7100 break;
7096 7101 }
7097 7102 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
7098 7103 {
7099 7104 /*
7100 7105 * SAS TOPOLOGY CHANGE LIST Event has already been handled
7101 7106 * in mptsas_handle_event_sync() of interrupt context
7102 7107 */
7103 7108 break;
7104 7109 }
7105 7110 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
7106 7111 {
7107 7112 pMpi2EventDataSasEnclDevStatusChange_t encstatus;
7108 7113 uint8_t rc;
7109 7114 char string[80];
7110 7115
7111 7116 encstatus = (pMpi2EventDataSasEnclDevStatusChange_t)
7112 7117 eventreply->EventData;
7113 7118
7114 7119 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7115 7120 &encstatus->ReasonCode);
7116 7121 switch (rc) {
7117 7122 case MPI2_EVENT_SAS_ENCL_RC_ADDED:
7118 7123 (void) sprintf(string, "added");
7119 7124 break;
7120 7125 case MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING:
7121 7126 (void) sprintf(string, ", not responding");
7122 7127 break;
7123 7128 default:
7124 7129 break;
7125 7130 }
7126 7131 NDBG20(("mptsas%d ENCLOSURE STATUS CHANGE for enclosure %x%s\n",
7127 7132 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl,
7128 7133 &encstatus->EnclosureHandle), string));
7129 7134 break;
7130 7135 }
7131 7136
7132 7137 /*
7133 7138 * MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE is handled by
7134 7139 * mptsas_handle_event_sync,in here just send ack message.
7135 7140 */
7136 7141 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
7137 7142 {
7138 7143 pMpi2EventDataSasDeviceStatusChange_t statuschange;
7139 7144 uint8_t rc;
7140 7145 uint16_t devhdl;
7141 7146 uint64_t wwn = 0;
7142 7147 uint32_t wwn_lo, wwn_hi;
7143 7148
7144 7149 statuschange = (pMpi2EventDataSasDeviceStatusChange_t)
7145 7150 eventreply->EventData;
7146 7151 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7147 7152 &statuschange->ReasonCode);
7148 7153 wwn_lo = ddi_get32(mpt->m_acc_reply_frame_hdl,
7149 7154 (uint32_t *)(void *)&statuschange->SASAddress);
7150 7155 wwn_hi = ddi_get32(mpt->m_acc_reply_frame_hdl,
7151 7156 (uint32_t *)(void *)&statuschange->SASAddress + 1);
7152 7157 wwn = ((uint64_t)wwn_hi << 32) | wwn_lo;
7153 7158 devhdl = ddi_get16(mpt->m_acc_reply_frame_hdl,
7154 7159 &statuschange->DevHandle);
7155 7160
7156 7161 NDBG13(("MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE wwn is %"PRIx64,
7157 7162 wwn));
7158 7163
7159 7164 switch (rc) {
7160 7165 case MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA:
7161 7166 NDBG20(("SMART data received, ASC/ASCQ = %02x/%02x",
7162 7167 ddi_get8(mpt->m_acc_reply_frame_hdl,
7163 7168 &statuschange->ASC),
7164 7169 ddi_get8(mpt->m_acc_reply_frame_hdl,
7165 7170 &statuschange->ASCQ)));
7166 7171 break;
7167 7172
7168 7173 case MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED:
7169 7174 NDBG20(("Device not supported"));
7170 7175 break;
7171 7176
7172 7177 case MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET:
7173 7178 NDBG20(("IOC internally generated the Target Reset "
7174 7179 "for devhdl:%x", devhdl));
7175 7180 break;
7176 7181
7177 7182 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET:
7178 7183 NDBG20(("IOC's internally generated Target Reset "
7179 7184 "completed for devhdl:%x", devhdl));
7180 7185 break;
7181 7186
7182 7187 case MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL:
7183 7188 NDBG20(("IOC internally generated Abort Task"));
7184 7189 break;
7185 7190
7186 7191 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL:
7187 7192 NDBG20(("IOC's internally generated Abort Task "
7188 7193 "completed"));
7189 7194 break;
7190 7195
7191 7196 case MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL:
7192 7197 NDBG20(("IOC internally generated Abort Task Set"));
7193 7198 break;
7194 7199
7195 7200 case MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL:
7196 7201 NDBG20(("IOC internally generated Clear Task Set"));
7197 7202 break;
7198 7203
7199 7204 case MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL:
7200 7205 NDBG20(("IOC internally generated Query Task"));
7201 7206 break;
7202 7207
7203 7208 case MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION:
7204 7209 NDBG20(("Device sent an Asynchronous Notification"));
7205 7210 break;
7206 7211
7207 7212 default:
7208 7213 break;
7209 7214 }
7210 7215 break;
7211 7216 }
7212 7217 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
7213 7218 {
7214 7219 /*
7215 7220 * IR TOPOLOGY CHANGE LIST Event has already been handled
7216 7221 * in mpt_handle_event_sync() of interrupt context
7217 7222 */
7218 7223 break;
7219 7224 }
7220 7225 case MPI2_EVENT_IR_OPERATION_STATUS:
7221 7226 {
7222 7227 Mpi2EventDataIrOperationStatus_t *irOpStatus;
7223 7228 char reason_str[80];
7224 7229 uint8_t rc, percent;
7225 7230 uint16_t handle;
7226 7231
7227 7232 irOpStatus = (pMpi2EventDataIrOperationStatus_t)
7228 7233 eventreply->EventData;
7229 7234 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7230 7235 &irOpStatus->RAIDOperation);
7231 7236 percent = ddi_get8(mpt->m_acc_reply_frame_hdl,
7232 7237 &irOpStatus->PercentComplete);
7233 7238 handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7234 7239 &irOpStatus->VolDevHandle);
7235 7240
7236 7241 switch (rc) {
7237 7242 case MPI2_EVENT_IR_RAIDOP_RESYNC:
7238 7243 (void) sprintf(reason_str, "resync");
7239 7244 break;
7240 7245 case MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION:
7241 7246 (void) sprintf(reason_str, "online capacity "
7242 7247 "expansion");
7243 7248 break;
7244 7249 case MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK:
7245 7250 (void) sprintf(reason_str, "consistency check");
7246 7251 break;
7247 7252 default:
7248 7253 (void) sprintf(reason_str, "unknown reason %x",
7249 7254 rc);
7250 7255 }
7251 7256
7252 7257 NDBG20(("mptsas%d raid operational status: (%s)"
7253 7258 "\thandle(0x%04x), percent complete(%d)\n",
7254 7259 mpt->m_instance, reason_str, handle, percent));
7255 7260 break;
7256 7261 }
7257 7262 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
7258 7263 {
7259 7264 pMpi2EventDataSasBroadcastPrimitive_t sas_broadcast;
7260 7265 uint8_t phy_num;
7261 7266 uint8_t primitive;
7262 7267
7263 7268 sas_broadcast = (pMpi2EventDataSasBroadcastPrimitive_t)
7264 7269 eventreply->EventData;
7265 7270
7266 7271 phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl,
7267 7272 &sas_broadcast->PhyNum);
7268 7273 primitive = ddi_get8(mpt->m_acc_reply_frame_hdl,
7269 7274 &sas_broadcast->Primitive);
7270 7275
7271 7276 switch (primitive) {
7272 7277 case MPI2_EVENT_PRIMITIVE_CHANGE:
7273 7278 mptsas_smhba_log_sysevent(mpt,
7274 7279 ESC_SAS_HBA_PORT_BROADCAST,
7275 7280 SAS_PORT_BROADCAST_CHANGE,
7276 7281 &mpt->m_phy_info[phy_num].smhba_info);
7277 7282 break;
7278 7283 case MPI2_EVENT_PRIMITIVE_SES:
7279 7284 mptsas_smhba_log_sysevent(mpt,
7280 7285 ESC_SAS_HBA_PORT_BROADCAST,
7281 7286 SAS_PORT_BROADCAST_SES,
7282 7287 &mpt->m_phy_info[phy_num].smhba_info);
7283 7288 break;
7284 7289 case MPI2_EVENT_PRIMITIVE_EXPANDER:
7285 7290 mptsas_smhba_log_sysevent(mpt,
7286 7291 ESC_SAS_HBA_PORT_BROADCAST,
7287 7292 SAS_PORT_BROADCAST_D01_4,
7288 7293 &mpt->m_phy_info[phy_num].smhba_info);
7289 7294 break;
7290 7295 case MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT:
7291 7296 mptsas_smhba_log_sysevent(mpt,
7292 7297 ESC_SAS_HBA_PORT_BROADCAST,
7293 7298 SAS_PORT_BROADCAST_D04_7,
7294 7299 &mpt->m_phy_info[phy_num].smhba_info);
7295 7300 break;
7296 7301 case MPI2_EVENT_PRIMITIVE_RESERVED3:
7297 7302 mptsas_smhba_log_sysevent(mpt,
7298 7303 ESC_SAS_HBA_PORT_BROADCAST,
7299 7304 SAS_PORT_BROADCAST_D16_7,
7300 7305 &mpt->m_phy_info[phy_num].smhba_info);
7301 7306 break;
7302 7307 case MPI2_EVENT_PRIMITIVE_RESERVED4:
7303 7308 mptsas_smhba_log_sysevent(mpt,
7304 7309 ESC_SAS_HBA_PORT_BROADCAST,
7305 7310 SAS_PORT_BROADCAST_D29_7,
7306 7311 &mpt->m_phy_info[phy_num].smhba_info);
7307 7312 break;
7308 7313 case MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED:
7309 7314 mptsas_smhba_log_sysevent(mpt,
7310 7315 ESC_SAS_HBA_PORT_BROADCAST,
7311 7316 SAS_PORT_BROADCAST_D24_0,
7312 7317 &mpt->m_phy_info[phy_num].smhba_info);
7313 7318 break;
7314 7319 case MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED:
7315 7320 mptsas_smhba_log_sysevent(mpt,
7316 7321 ESC_SAS_HBA_PORT_BROADCAST,
7317 7322 SAS_PORT_BROADCAST_D27_4,
7318 7323 &mpt->m_phy_info[phy_num].smhba_info);
7319 7324 break;
7320 7325 default:
7321 7326 NDBG20(("mptsas%d: unknown BROADCAST PRIMITIVE"
7322 7327 " %x received",
7323 7328 mpt->m_instance, primitive));
7324 7329 break;
7325 7330 }
7326 7331 NDBG20(("mptsas%d sas broadcast primitive: "
7327 7332 "\tprimitive(0x%04x), phy(%d) complete\n",
7328 7333 mpt->m_instance, primitive, phy_num));
7329 7334 break;
7330 7335 }
7331 7336 case MPI2_EVENT_IR_VOLUME:
7332 7337 {
7333 7338 Mpi2EventDataIrVolume_t *irVolume;
7334 7339 uint16_t devhandle;
7335 7340 uint32_t state;
7336 7341 int config, vol;
7337 7342 mptsas_slots_t *slots = mpt->m_active;
7338 7343 uint8_t found = FALSE;
7339 7344
7340 7345 irVolume = (pMpi2EventDataIrVolume_t)eventreply->EventData;
7341 7346 state = ddi_get32(mpt->m_acc_reply_frame_hdl,
7342 7347 &irVolume->NewValue);
7343 7348 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7344 7349 &irVolume->VolDevHandle);
7345 7350
7346 7351 NDBG20(("EVENT_IR_VOLUME event is received"));
7347 7352
7348 7353 /*
7349 7354 * Get latest RAID info and then find the DevHandle for this
7350 7355 * event in the configuration. If the DevHandle is not found
7351 7356 * just exit the event.
7352 7357 */
7353 7358 (void) mptsas_get_raid_info(mpt);
7354 7359 for (config = 0; (config < slots->m_num_raid_configs) &&
7355 7360 (!found); config++) {
7356 7361 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) {
7357 7362 if (slots->m_raidconfig[config].m_raidvol[vol].
7358 7363 m_raidhandle == devhandle) {
7359 7364 found = TRUE;
7360 7365 break;
7361 7366 }
7362 7367 }
7363 7368 }
7364 7369 if (!found) {
7365 7370 break;
7366 7371 }
7367 7372
7368 7373 switch (irVolume->ReasonCode) {
7369 7374 case MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED:
7370 7375 {
7371 7376 uint32_t i;
7372 7377 slots->m_raidconfig[config].m_raidvol[vol].m_settings =
7373 7378 state;
7374 7379
7375 7380 i = state & MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING;
7376 7381 mptsas_log(mpt, CE_NOTE, " Volume %d settings changed"
7377 7382 ", auto-config of hot-swap drives is %s"
7378 7383 ", write caching is %s"
7379 7384 ", hot-spare pool mask is %02x\n",
7380 7385 vol, state &
7381 7386 MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE
7382 7387 ? "disabled" : "enabled",
7383 7388 i == MPI2_RAIDVOL0_SETTING_UNCHANGED
7384 7389 ? "controlled by member disks" :
7385 7390 i == MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING
7386 7391 ? "disabled" :
7387 7392 i == MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING
7388 7393 ? "enabled" :
7389 7394 "incorrectly set",
7390 7395 (state >> 16) & 0xff);
7391 7396 break;
7392 7397 }
7393 7398 case MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED:
7394 7399 {
7395 7400 slots->m_raidconfig[config].m_raidvol[vol].m_state =
7396 7401 (uint8_t)state;
7397 7402
7398 7403 mptsas_log(mpt, CE_NOTE,
7399 7404 "Volume %d is now %s\n", vol,
7400 7405 state == MPI2_RAID_VOL_STATE_OPTIMAL
7401 7406 ? "optimal" :
7402 7407 state == MPI2_RAID_VOL_STATE_DEGRADED
7403 7408 ? "degraded" :
7404 7409 state == MPI2_RAID_VOL_STATE_ONLINE
7405 7410 ? "online" :
7406 7411 state == MPI2_RAID_VOL_STATE_INITIALIZING
7407 7412 ? "initializing" :
7408 7413 state == MPI2_RAID_VOL_STATE_FAILED
7409 7414 ? "failed" :
7410 7415 state == MPI2_RAID_VOL_STATE_MISSING
7411 7416 ? "missing" :
7412 7417 "state unknown");
7413 7418 break;
7414 7419 }
7415 7420 case MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED:
7416 7421 {
7417 7422 slots->m_raidconfig[config].m_raidvol[vol].
7418 7423 m_statusflags = state;
7419 7424
7420 7425 mptsas_log(mpt, CE_NOTE,
7421 7426 " Volume %d is now %s%s%s%s%s%s%s%s%s\n",
7422 7427 vol,
7423 7428 state & MPI2_RAIDVOL0_STATUS_FLAG_ENABLED
7424 7429 ? ", enabled" : ", disabled",
7425 7430 state & MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED
7426 7431 ? ", quiesced" : "",
7427 7432 state & MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE
7428 7433 ? ", inactive" : ", active",
7429 7434 state &
7430 7435 MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL
7431 7436 ? ", bad block table is full" : "",
7432 7437 state &
7433 7438 MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS
7434 7439 ? ", resync in progress" : "",
7435 7440 state & MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT
7436 7441 ? ", background initialization in progress" : "",
7437 7442 state &
7438 7443 MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION
7439 7444 ? ", capacity expansion in progress" : "",
7440 7445 state &
7441 7446 MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK
7442 7447 ? ", consistency check in progress" : "",
7443 7448 state & MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB
7444 7449 ? ", data scrub in progress" : "");
7445 7450 break;
7446 7451 }
7447 7452 default:
7448 7453 break;
7449 7454 }
7450 7455 break;
7451 7456 }
7452 7457 case MPI2_EVENT_IR_PHYSICAL_DISK:
7453 7458 {
7454 7459 Mpi2EventDataIrPhysicalDisk_t *irPhysDisk;
7455 7460 uint16_t devhandle, enchandle, slot;
7456 7461 uint32_t status, state;
7457 7462 uint8_t physdisknum, reason;
7458 7463
7459 7464 irPhysDisk = (Mpi2EventDataIrPhysicalDisk_t *)
7460 7465 eventreply->EventData;
7461 7466 physdisknum = ddi_get8(mpt->m_acc_reply_frame_hdl,
7462 7467 &irPhysDisk->PhysDiskNum);
7463 7468 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7464 7469 &irPhysDisk->PhysDiskDevHandle);
7465 7470 enchandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7466 7471 &irPhysDisk->EnclosureHandle);
7467 7472 slot = ddi_get16(mpt->m_acc_reply_frame_hdl,
7468 7473 &irPhysDisk->Slot);
7469 7474 state = ddi_get32(mpt->m_acc_reply_frame_hdl,
7470 7475 &irPhysDisk->NewValue);
7471 7476 reason = ddi_get8(mpt->m_acc_reply_frame_hdl,
7472 7477 &irPhysDisk->ReasonCode);
7473 7478
7474 7479 NDBG20(("EVENT_IR_PHYSICAL_DISK event is received"));
7475 7480
7476 7481 switch (reason) {
7477 7482 case MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED:
7478 7483 mptsas_log(mpt, CE_NOTE,
7479 7484 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
7480 7485 "for enclosure with handle 0x%x is now in hot "
7481 7486 "spare pool %d",
7482 7487 physdisknum, devhandle, slot, enchandle,
7483 7488 (state >> 16) & 0xff);
7484 7489 break;
7485 7490
7486 7491 case MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED:
7487 7492 status = state;
7488 7493 mptsas_log(mpt, CE_NOTE,
7489 7494 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
7490 7495 "for enclosure with handle 0x%x is now "
7491 7496 "%s%s%s%s%s\n", physdisknum, devhandle, slot,
7492 7497 enchandle,
7493 7498 status & MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME
7494 7499 ? ", inactive" : ", active",
7495 7500 status & MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC
7496 7501 ? ", out of sync" : "",
7497 7502 status & MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED
7498 7503 ? ", quiesced" : "",
7499 7504 status &
7500 7505 MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED
7501 7506 ? ", write cache enabled" : "",
7502 7507 status & MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET
7503 7508 ? ", capacity expansion target" : "");
7504 7509 break;
7505 7510
7506 7511 case MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED:
7507 7512 mptsas_log(mpt, CE_NOTE,
7508 7513 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
7509 7514 "for enclosure with handle 0x%x is now %s\n",
7510 7515 physdisknum, devhandle, slot, enchandle,
7511 7516 state == MPI2_RAID_PD_STATE_OPTIMAL
7512 7517 ? "optimal" :
7513 7518 state == MPI2_RAID_PD_STATE_REBUILDING
7514 7519 ? "rebuilding" :
7515 7520 state == MPI2_RAID_PD_STATE_DEGRADED
7516 7521 ? "degraded" :
7517 7522 state == MPI2_RAID_PD_STATE_HOT_SPARE
7518 7523 ? "a hot spare" :
7519 7524 state == MPI2_RAID_PD_STATE_ONLINE
7520 7525 ? "online" :
7521 7526 state == MPI2_RAID_PD_STATE_OFFLINE
7522 7527 ? "offline" :
7523 7528 state == MPI2_RAID_PD_STATE_NOT_COMPATIBLE
7524 7529 ? "not compatible" :
7525 7530 state == MPI2_RAID_PD_STATE_NOT_CONFIGURED
7526 7531 ? "not configured" :
7527 7532 "state unknown");
7528 7533 break;
7529 7534 }
7530 7535 break;
7531 7536 }
7532 7537 default:
7533 7538 NDBG20(("mptsas%d: unknown event %x received",
7534 7539 mpt->m_instance, event));
7535 7540 break;
7536 7541 }
7537 7542
7538 7543 /*
7539 7544 * Return the reply frame to the free queue.
7540 7545 */
7541 7546 ddi_put32(mpt->m_acc_free_queue_hdl,
7542 7547 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], rfm);
7543 7548 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
7544 7549 DDI_DMA_SYNC_FORDEV);
7545 7550 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
7546 7551 mpt->m_free_index = 0;
7547 7552 }
7548 7553 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
7549 7554 mpt->m_free_index);
7550 7555 mutex_exit(&mpt->m_mutex);
7551 7556 }
7552 7557
7553 7558 /*
7554 7559 * invoked from timeout() to restart qfull cmds with throttle == 0
7555 7560 */
7556 7561 static void
7557 7562 mptsas_restart_cmd(void *arg)
7558 7563 {
7559 7564 mptsas_t *mpt = arg;
7560 7565 mptsas_target_t *ptgt = NULL;
7561 7566
7562 7567 mutex_enter(&mpt->m_mutex);
7563 7568
7564 7569 mpt->m_restart_cmd_timeid = 0;
7565 7570
7566 7571 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
7567 7572 MPTSAS_HASH_FIRST);
7568 7573 while (ptgt != NULL) {
7569 7574 if (ptgt->m_reset_delay == 0) {
7570 7575 if (ptgt->m_t_throttle == QFULL_THROTTLE) {
7571 7576 mptsas_set_throttle(mpt, ptgt,
7572 7577 MAX_THROTTLE);
7573 7578 }
7574 7579 }
7575 7580
7576 7581 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
7577 7582 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
7578 7583 }
7579 7584 mptsas_restart_hba(mpt);
7580 7585 mutex_exit(&mpt->m_mutex);
7581 7586 }
7582 7587
7583 7588 void
7584 7589 mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
7585 7590 {
7586 7591 int slot;
7587 7592 mptsas_slots_t *slots = mpt->m_active;
7588 7593 int t;
7589 7594 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
7590 7595
7591 7596 ASSERT(cmd != NULL);
7592 7597 ASSERT(cmd->cmd_queued == FALSE);
7593 7598
7594 7599 /*
7595 7600 * Task Management cmds are removed in their own routines. Also,
7596 7601 * we don't want to modify timeout based on TM cmds.
7597 7602 */
7598 7603 if (cmd->cmd_flags & CFLAG_TM_CMD) {
7599 7604 return;
7600 7605 }
7601 7606
7602 7607 t = Tgt(cmd);
7603 7608 slot = cmd->cmd_slot;
7604 7609
7605 7610 /*
7606 7611 * remove the cmd.
7607 7612 */
7608 7613 if (cmd == slots->m_slot[slot]) {
7609 7614 NDBG31(("mptsas_remove_cmd: removing cmd=0x%p", (void *)cmd));
7610 7615 slots->m_slot[slot] = NULL;
7611 7616 mpt->m_ncmds--;
7612 7617
7613 7618 /*
7614 7619 * only decrement per target ncmds if command
7615 7620 * has a target associated with it.
7616 7621 */
7617 7622 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
7618 7623 ptgt->m_t_ncmds--;
7619 7624 /*
7620 7625 * reset throttle if we just ran an untagged command
7621 7626 * to a tagged target
7622 7627 */
7623 7628 if ((ptgt->m_t_ncmds == 0) &&
7624 7629 ((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0)) {
7625 7630 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
7626 7631 }
7627 7632 }
7628 7633
7629 7634 }
7630 7635
7631 7636 /*
7632 7637 * This is all we need to do for ioc commands.
7633 7638 */
7634 7639 if (cmd->cmd_flags & CFLAG_CMDIOC) {
7635 7640 mptsas_return_to_pool(mpt, cmd);
7636 7641 return;
7637 7642 }
7638 7643
7639 7644 /*
7640 7645 * Figure out what to set tag Q timeout for...
7641 7646 *
7642 7647 * Optimize: If we have duplicate's of same timeout
7643 7648 * we're using, then we'll use it again until we run
7644 7649 * out of duplicates. This should be the normal case
7645 7650 * for block and raw I/O.
7646 7651 * If no duplicates, we have to scan through tag que and
7647 7652 * find the longest timeout value and use it. This is
7648 7653 * going to take a while...
7649 7654 * Add 1 to m_n_slots to account for TM request.
7650 7655 */
7651 7656 if (cmd->cmd_pkt->pkt_time == ptgt->m_timebase) {
7652 7657 if (--(ptgt->m_dups) == 0) {
7653 7658 if (ptgt->m_t_ncmds) {
7654 7659 mptsas_cmd_t *ssp;
7655 7660 uint_t n = 0;
7656 7661 ushort_t nslots = (slots->m_n_slots + 1);
7657 7662 ushort_t i;
7658 7663 /*
7659 7664 * This crude check assumes we don't do
7660 7665 * this too often which seems reasonable
7661 7666 * for block and raw I/O.
7662 7667 */
7663 7668 for (i = 0; i < nslots; i++) {
7664 7669 ssp = slots->m_slot[i];
7665 7670 if (ssp && (Tgt(ssp) == t) &&
7666 7671 (ssp->cmd_pkt->pkt_time > n)) {
7667 7672 n = ssp->cmd_pkt->pkt_time;
7668 7673 ptgt->m_dups = 1;
7669 7674 } else if (ssp && (Tgt(ssp) == t) &&
7670 7675 (ssp->cmd_pkt->pkt_time == n)) {
7671 7676 ptgt->m_dups++;
7672 7677 }
7673 7678 }
7674 7679 ptgt->m_timebase = n;
7675 7680 } else {
7676 7681 ptgt->m_dups = 0;
7677 7682 ptgt->m_timebase = 0;
7678 7683 }
7679 7684 }
7680 7685 }
7681 7686 ptgt->m_timeout = ptgt->m_timebase;
7682 7687
7683 7688 ASSERT(cmd != slots->m_slot[cmd->cmd_slot]);
7684 7689 }
7685 7690
7686 7691 /*
7687 7692 * accept all cmds on the tx_waitq if any and then
7688 7693 * start a fresh request from the top of the device queue.
7689 7694 *
7690 7695 * since there are always cmds queued on the tx_waitq, and rare cmds on
7691 7696 * the instance waitq, so this function should not be invoked in the ISR,
7692 7697 * the mptsas_restart_waitq() is invoked in the ISR instead. otherwise, the
7693 7698 * burden belongs to the IO dispatch CPUs is moved the interrupt CPU.
7694 7699 */
7695 7700 static void
7696 7701 mptsas_restart_hba(mptsas_t *mpt)
7697 7702 {
7698 7703 ASSERT(mutex_owned(&mpt->m_mutex));
7699 7704
7700 7705 mutex_enter(&mpt->m_tx_waitq_mutex);
7701 7706 if (mpt->m_tx_waitq) {
7702 7707 mptsas_accept_tx_waitq(mpt);
7703 7708 }
7704 7709 mutex_exit(&mpt->m_tx_waitq_mutex);
7705 7710 mptsas_restart_waitq(mpt);
7706 7711 }
7707 7712
7708 7713 /*
7709 7714 * start a fresh request from the top of the device queue
7710 7715 */
7711 7716 static void
7712 7717 mptsas_restart_waitq(mptsas_t *mpt)
7713 7718 {
7714 7719 mptsas_cmd_t *cmd, *next_cmd;
7715 7720 mptsas_target_t *ptgt = NULL;
7716 7721
7717 7722 NDBG1(("mptsas_restart_waitq: mpt=0x%p", (void *)mpt));
7718 7723
7719 7724 ASSERT(mutex_owned(&mpt->m_mutex));
7720 7725
7721 7726 /*
7722 7727 * If there is a reset delay, don't start any cmds. Otherwise, start
7723 7728 * as many cmds as possible.
7724 7729 * Since SMID 0 is reserved and the TM slot is reserved, the actual max
7725 7730 * commands is m_max_requests - 2.
7726 7731 */
7727 7732 cmd = mpt->m_waitq;
7728 7733
7729 7734 while (cmd != NULL) {
7730 7735 next_cmd = cmd->cmd_linkp;
7731 7736 if (cmd->cmd_flags & CFLAG_PASSTHRU) {
7732 7737 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
7733 7738 /*
7734 7739 * passthru command get slot need
7735 7740 * set CFLAG_PREPARED.
7736 7741 */
7737 7742 cmd->cmd_flags |= CFLAG_PREPARED;
7738 7743 mptsas_waitq_delete(mpt, cmd);
7739 7744 mptsas_start_passthru(mpt, cmd);
7740 7745 }
7741 7746 cmd = next_cmd;
7742 7747 continue;
7743 7748 }
7744 7749 if (cmd->cmd_flags & CFLAG_CONFIG) {
7745 7750 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
7746 7751 /*
7747 7752 * Send the config page request and delete it
7748 7753 * from the waitq.
7749 7754 */
7750 7755 cmd->cmd_flags |= CFLAG_PREPARED;
7751 7756 mptsas_waitq_delete(mpt, cmd);
7752 7757 mptsas_start_config_page_access(mpt, cmd);
7753 7758 }
7754 7759 cmd = next_cmd;
7755 7760 continue;
7756 7761 }
7757 7762 if (cmd->cmd_flags & CFLAG_FW_DIAG) {
7758 7763 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
7759 7764 /*
7760 7765 * Send the FW Diag request and delete if from
7761 7766 * the waitq.
7762 7767 */
7763 7768 cmd->cmd_flags |= CFLAG_PREPARED;
7764 7769 mptsas_waitq_delete(mpt, cmd);
7765 7770 mptsas_start_diag(mpt, cmd);
7766 7771 }
7767 7772 cmd = next_cmd;
7768 7773 continue;
7769 7774 }
7770 7775
7771 7776 ptgt = cmd->cmd_tgt_addr;
7772 7777 if (ptgt && (ptgt->m_t_throttle == DRAIN_THROTTLE) &&
7773 7778 (ptgt->m_t_ncmds == 0)) {
7774 7779 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
7775 7780 }
7776 7781 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) &&
7777 7782 (ptgt && (ptgt->m_reset_delay == 0)) &&
7778 7783 (ptgt && (ptgt->m_t_ncmds <
7779 7784 ptgt->m_t_throttle))) {
7780 7785 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
7781 7786 mptsas_waitq_delete(mpt, cmd);
7782 7787 (void) mptsas_start_cmd(mpt, cmd);
7783 7788 }
7784 7789 }
7785 7790 cmd = next_cmd;
7786 7791 }
7787 7792 }
7788 7793 /*
7789 7794 * Cmds are queued if tran_start() doesn't get the m_mutexlock(no wait).
7790 7795 * Accept all those queued cmds before new cmd is accept so that the
7791 7796 * cmds are sent in order.
7792 7797 */
7793 7798 static void
7794 7799 mptsas_accept_tx_waitq(mptsas_t *mpt)
7795 7800 {
7796 7801 mptsas_cmd_t *cmd;
7797 7802
7798 7803 ASSERT(mutex_owned(&mpt->m_mutex));
7799 7804 ASSERT(mutex_owned(&mpt->m_tx_waitq_mutex));
7800 7805
7801 7806 /*
7802 7807 * A Bus Reset could occur at any time and flush the tx_waitq,
7803 7808 * so we cannot count on the tx_waitq to contain even one cmd.
7804 7809 * And when the m_tx_waitq_mutex is released and run
7805 7810 * mptsas_accept_pkt(), the tx_waitq may be flushed.
7806 7811 */
7807 7812 cmd = mpt->m_tx_waitq;
7808 7813 for (;;) {
7809 7814 if ((cmd = mpt->m_tx_waitq) == NULL) {
7810 7815 mpt->m_tx_draining = 0;
7811 7816 break;
7812 7817 }
7813 7818 if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL) {
7814 7819 mpt->m_tx_waitqtail = &mpt->m_tx_waitq;
7815 7820 }
7816 7821 cmd->cmd_linkp = NULL;
7817 7822 mutex_exit(&mpt->m_tx_waitq_mutex);
7818 7823 if (mptsas_accept_pkt(mpt, cmd) != TRAN_ACCEPT)
7819 7824 cmn_err(CE_WARN, "mpt: mptsas_accept_tx_waitq: failed "
7820 7825 "to accept cmd on queue\n");
7821 7826 mutex_enter(&mpt->m_tx_waitq_mutex);
7822 7827 }
7823 7828 }
7824 7829
7825 7830
7826 7831 /*
7827 7832 * mpt tag type lookup
7828 7833 */
7829 7834 static char mptsas_tag_lookup[] =
7830 7835 {0, MSG_HEAD_QTAG, MSG_ORDERED_QTAG, 0, MSG_SIMPLE_QTAG};
7831 7836
7832 7837 static int
7833 7838 mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
7834 7839 {
7835 7840 struct scsi_pkt *pkt = CMD2PKT(cmd);
7836 7841 uint32_t control = 0;
7837 7842 int n;
7838 7843 caddr_t mem;
7839 7844 pMpi2SCSIIORequest_t io_request;
7840 7845 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl;
7841 7846 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl;
7842 7847 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
7843 7848 uint16_t SMID, io_flags = 0;
7844 7849 uint32_t request_desc_low, request_desc_high;
7845 7850
7846 7851 NDBG1(("mptsas_start_cmd: cmd=0x%p", (void *)cmd));
7847 7852
7848 7853 /*
7849 7854 * Set SMID and increment index. Rollover to 1 instead of 0 if index
7850 7855 * is at the max. 0 is an invalid SMID, so we call the first index 1.
7851 7856 */
7852 7857 SMID = cmd->cmd_slot;
7853 7858
7854 7859 /*
7855 7860 * It is possible for back to back device reset to
7856 7861 * happen before the reset delay has expired. That's
7857 7862 * ok, just let the device reset go out on the bus.
7858 7863 */
7859 7864 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
7860 7865 ASSERT(ptgt->m_reset_delay == 0);
7861 7866 }
7862 7867
7863 7868 /*
7864 7869 * if a non-tagged cmd is submitted to an active tagged target
7865 7870 * then drain before submitting this cmd; SCSI-2 allows RQSENSE
7866 7871 * to be untagged
7867 7872 */
7868 7873 if (((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0) &&
7869 7874 (ptgt->m_t_ncmds > 1) &&
7870 7875 ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) &&
7871 7876 (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE)) {
7872 7877 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
7873 7878 NDBG23(("target=%d, untagged cmd, start draining\n",
7874 7879 ptgt->m_devhdl));
7875 7880
7876 7881 if (ptgt->m_reset_delay == 0) {
7877 7882 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
7878 7883 }
7879 7884
7880 7885 mptsas_remove_cmd(mpt, cmd);
7881 7886 cmd->cmd_pkt_flags |= FLAG_HEAD;
7882 7887 mptsas_waitq_add(mpt, cmd);
7883 7888 }
7884 7889 return (DDI_FAILURE);
7885 7890 }
7886 7891
7887 7892 /*
7888 7893 * Set correct tag bits.
7889 7894 */
7890 7895 if (cmd->cmd_pkt_flags & FLAG_TAGMASK) {
7891 7896 switch (mptsas_tag_lookup[((cmd->cmd_pkt_flags &
7892 7897 FLAG_TAGMASK) >> 12)]) {
7893 7898 case MSG_SIMPLE_QTAG:
7894 7899 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
7895 7900 break;
7896 7901 case MSG_HEAD_QTAG:
7897 7902 control |= MPI2_SCSIIO_CONTROL_HEADOFQ;
7898 7903 break;
7899 7904 case MSG_ORDERED_QTAG:
7900 7905 control |= MPI2_SCSIIO_CONTROL_ORDEREDQ;
7901 7906 break;
7902 7907 default:
7903 7908 mptsas_log(mpt, CE_WARN, "mpt: Invalid tag type\n");
7904 7909 break;
7905 7910 }
7906 7911 } else {
7907 7912 if (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE) {
7908 7913 ptgt->m_t_throttle = 1;
7909 7914 }
7910 7915 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
7911 7916 }
7912 7917
7913 7918 if (cmd->cmd_pkt_flags & FLAG_TLR) {
7914 7919 control |= MPI2_SCSIIO_CONTROL_TLR_ON;
7915 7920 }
7916 7921
7917 7922 mem = mpt->m_req_frame + (mpt->m_req_frame_size * SMID);
7918 7923 io_request = (pMpi2SCSIIORequest_t)mem;
7919 7924
7920 7925 bzero(io_request, sizeof (Mpi2SCSIIORequest_t));
7921 7926 ddi_put8(acc_hdl, &io_request->SGLOffset0, offsetof
7922 7927 (MPI2_SCSI_IO_REQUEST, SGL) / 4);
7923 7928 mptsas_init_std_hdr(acc_hdl, io_request, ptgt->m_devhdl, Lun(cmd), 0,
7924 7929 MPI2_FUNCTION_SCSI_IO_REQUEST);
7925 7930
7926 7931 (void) ddi_rep_put8(acc_hdl, (uint8_t *)pkt->pkt_cdbp,
7927 7932 io_request->CDB.CDB32, cmd->cmd_cdblen, DDI_DEV_AUTOINCR);
7928 7933
7929 7934 io_flags = cmd->cmd_cdblen;
7930 7935 ddi_put16(acc_hdl, &io_request->IoFlags, io_flags);
7931 7936 /*
7932 7937 * setup the Scatter/Gather DMA list for this request
7933 7938 */
7934 7939 if (cmd->cmd_cookiec > 0) {
7935 7940 mptsas_sge_setup(mpt, cmd, &control, io_request, acc_hdl);
7936 7941 } else {
7937 7942 ddi_put32(acc_hdl, &io_request->SGL.MpiSimple.FlagsLength,
7938 7943 ((uint32_t)MPI2_SGE_FLAGS_LAST_ELEMENT |
7939 7944 MPI2_SGE_FLAGS_END_OF_BUFFER |
7940 7945 MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
7941 7946 MPI2_SGE_FLAGS_END_OF_LIST) << MPI2_SGE_FLAGS_SHIFT);
7942 7947 }
7943 7948
7944 7949 /*
7945 7950 * save ARQ information
7946 7951 */
7947 7952 ddi_put8(acc_hdl, &io_request->SenseBufferLength, cmd->cmd_rqslen);
7948 7953 if ((cmd->cmd_flags & (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) ==
7949 7954 (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) {
7950 7955 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress,
7951 7956 cmd->cmd_ext_arqcookie.dmac_address);
7952 7957 } else {
7953 7958 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress,
7954 7959 cmd->cmd_arqcookie.dmac_address);
7955 7960 }
7956 7961
7957 7962 ddi_put32(acc_hdl, &io_request->Control, control);
7958 7963
7959 7964 NDBG31(("starting message=0x%p, with cmd=0x%p",
7960 7965 (void *)(uintptr_t)mpt->m_req_frame_dma_addr, (void *)cmd));
7961 7966
7962 7967 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
7963 7968
7964 7969 /*
7965 7970 * Build request descriptor and write it to the request desc post reg.
7966 7971 */
7967 7972 request_desc_low = (SMID << 16) + MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
7968 7973 request_desc_high = ptgt->m_devhdl << 16;
7969 7974 MPTSAS_START_CMD(mpt, request_desc_low, request_desc_high);
7970 7975
7971 7976 /*
7972 7977 * Start timeout.
7973 7978 */
7974 7979 #ifdef MPTSAS_TEST
7975 7980 /*
7976 7981 * Temporarily set timebase = 0; needed for
7977 7982 * timeout torture test.
7978 7983 */
7979 7984 if (mptsas_test_timeouts) {
7980 7985 ptgt->m_timebase = 0;
7981 7986 }
7982 7987 #endif
7983 7988 n = pkt->pkt_time - ptgt->m_timebase;
7984 7989
7985 7990 if (n == 0) {
7986 7991 (ptgt->m_dups)++;
7987 7992 ptgt->m_timeout = ptgt->m_timebase;
7988 7993 } else if (n > 0) {
7989 7994 ptgt->m_timeout =
7990 7995 ptgt->m_timebase = pkt->pkt_time;
7991 7996 ptgt->m_dups = 1;
7992 7997 } else if (n < 0) {
7993 7998 ptgt->m_timeout = ptgt->m_timebase;
7994 7999 }
7995 8000 #ifdef MPTSAS_TEST
7996 8001 /*
7997 8002 * Set back to a number higher than
7998 8003 * mptsas_scsi_watchdog_tick
7999 8004 * so timeouts will happen in mptsas_watchsubr
8000 8005 */
8001 8006 if (mptsas_test_timeouts) {
8002 8007 ptgt->m_timebase = 60;
8003 8008 }
8004 8009 #endif
8005 8010
8006 8011 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) ||
8007 8012 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) {
8008 8013 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8009 8014 return (DDI_FAILURE);
8010 8015 }
8011 8016 return (DDI_SUCCESS);
8012 8017 }
8013 8018
8014 8019 /*
8015 8020 * Select a helper thread to handle current doneq
8016 8021 */
8017 8022 static void
8018 8023 mptsas_deliver_doneq_thread(mptsas_t *mpt)
8019 8024 {
8020 8025 uint64_t t, i;
8021 8026 uint32_t min = 0xffffffff;
8022 8027 mptsas_doneq_thread_list_t *item;
8023 8028
8024 8029 for (i = 0; i < mpt->m_doneq_thread_n; i++) {
8025 8030 item = &mpt->m_doneq_thread_id[i];
8026 8031 /*
8027 8032 * If the completed command on help thread[i] less than
8028 8033 * doneq_thread_threshold, then pick the thread[i]. Otherwise
8029 8034 * pick a thread which has least completed command.
8030 8035 */
8031 8036
8032 8037 mutex_enter(&item->mutex);
8033 8038 if (item->len < mpt->m_doneq_thread_threshold) {
8034 8039 t = i;
8035 8040 mutex_exit(&item->mutex);
8036 8041 break;
8037 8042 }
8038 8043 if (item->len < min) {
8039 8044 min = item->len;
8040 8045 t = i;
8041 8046 }
8042 8047 mutex_exit(&item->mutex);
8043 8048 }
8044 8049 mutex_enter(&mpt->m_doneq_thread_id[t].mutex);
8045 8050 mptsas_doneq_mv(mpt, t);
8046 8051 cv_signal(&mpt->m_doneq_thread_id[t].cv);
8047 8052 mutex_exit(&mpt->m_doneq_thread_id[t].mutex);
8048 8053 }
8049 8054
8050 8055 /*
8051 8056 * move the current global doneq to the doneq of thead[t]
8052 8057 */
8053 8058 static void
8054 8059 mptsas_doneq_mv(mptsas_t *mpt, uint64_t t)
8055 8060 {
8056 8061 mptsas_cmd_t *cmd;
8057 8062 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
8058 8063
8059 8064 ASSERT(mutex_owned(&item->mutex));
8060 8065 while ((cmd = mpt->m_doneq) != NULL) {
8061 8066 if ((mpt->m_doneq = cmd->cmd_linkp) == NULL) {
8062 8067 mpt->m_donetail = &mpt->m_doneq;
8063 8068 }
8064 8069 cmd->cmd_linkp = NULL;
8065 8070 *item->donetail = cmd;
8066 8071 item->donetail = &cmd->cmd_linkp;
8067 8072 mpt->m_doneq_len--;
8068 8073 item->len++;
8069 8074 }
8070 8075 }
8071 8076
8072 8077 void
8073 8078 mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd)
8074 8079 {
8075 8080 struct scsi_pkt *pkt = CMD2PKT(cmd);
8076 8081
8077 8082 /* Check all acc and dma handles */
8078 8083 if ((mptsas_check_acc_handle(mpt->m_datap) !=
8079 8084 DDI_SUCCESS) ||
8080 8085 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
8081 8086 DDI_SUCCESS) ||
8082 8087 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) !=
8083 8088 DDI_SUCCESS) ||
8084 8089 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) !=
8085 8090 DDI_SUCCESS) ||
8086 8091 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) !=
8087 8092 DDI_SUCCESS) ||
8088 8093 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) !=
8089 8094 DDI_SUCCESS) ||
8090 8095 (mptsas_check_acc_handle(mpt->m_config_handle) !=
8091 8096 DDI_SUCCESS)) {
8092 8097 ddi_fm_service_impact(mpt->m_dip,
8093 8098 DDI_SERVICE_UNAFFECTED);
8094 8099 ddi_fm_acc_err_clear(mpt->m_config_handle,
8095 8100 DDI_FME_VER0);
8096 8101 pkt->pkt_reason = CMD_TRAN_ERR;
8097 8102 pkt->pkt_statistics = 0;
8098 8103 }
8099 8104 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
8100 8105 DDI_SUCCESS) ||
8101 8106 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) !=
8102 8107 DDI_SUCCESS) ||
8103 8108 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) !=
8104 8109 DDI_SUCCESS) ||
8105 8110 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) !=
8106 8111 DDI_SUCCESS) ||
8107 8112 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) !=
8108 8113 DDI_SUCCESS)) {
8109 8114 ddi_fm_service_impact(mpt->m_dip,
8110 8115 DDI_SERVICE_UNAFFECTED);
8111 8116 pkt->pkt_reason = CMD_TRAN_ERR;
8112 8117 pkt->pkt_statistics = 0;
8113 8118 }
8114 8119 if (cmd->cmd_dmahandle &&
8115 8120 (mptsas_check_dma_handle(cmd->cmd_dmahandle) != DDI_SUCCESS)) {
8116 8121 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8117 8122 pkt->pkt_reason = CMD_TRAN_ERR;
8118 8123 pkt->pkt_statistics = 0;
8119 8124 }
8120 8125 if ((cmd->cmd_extra_frames &&
8121 8126 ((mptsas_check_dma_handle(cmd->cmd_extra_frames->m_dma_hdl) !=
8122 8127 DDI_SUCCESS) ||
8123 8128 (mptsas_check_acc_handle(cmd->cmd_extra_frames->m_acc_hdl) !=
8124 8129 DDI_SUCCESS)))) {
8125 8130 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8126 8131 pkt->pkt_reason = CMD_TRAN_ERR;
8127 8132 pkt->pkt_statistics = 0;
8128 8133 }
8129 8134 if (cmd->cmd_arqhandle &&
8130 8135 (mptsas_check_dma_handle(cmd->cmd_arqhandle) != DDI_SUCCESS)) {
8131 8136 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8132 8137 pkt->pkt_reason = CMD_TRAN_ERR;
8133 8138 pkt->pkt_statistics = 0;
8134 8139 }
8135 8140 if (cmd->cmd_ext_arqhandle &&
8136 8141 (mptsas_check_dma_handle(cmd->cmd_ext_arqhandle) != DDI_SUCCESS)) {
8137 8142 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8138 8143 pkt->pkt_reason = CMD_TRAN_ERR;
8139 8144 pkt->pkt_statistics = 0;
8140 8145 }
8141 8146 }
8142 8147
8143 8148 /*
8144 8149 * These routines manipulate the queue of commands that
8145 8150 * are waiting for their completion routines to be called.
8146 8151 * The queue is usually in FIFO order but on an MP system
8147 8152 * it's possible for the completion routines to get out
8148 8153 * of order. If that's a problem you need to add a global
8149 8154 * mutex around the code that calls the completion routine
8150 8155 * in the interrupt handler.
8151 8156 */
8152 8157 static void
8153 8158 mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd)
8154 8159 {
8155 8160 struct scsi_pkt *pkt = CMD2PKT(cmd);
8156 8161
8157 8162 NDBG31(("mptsas_doneq_add: cmd=0x%p", (void *)cmd));
8158 8163
8159 8164 ASSERT((cmd->cmd_flags & CFLAG_COMPLETED) == 0);
8160 8165 cmd->cmd_linkp = NULL;
8161 8166 cmd->cmd_flags |= CFLAG_FINISHED;
8162 8167 cmd->cmd_flags &= ~CFLAG_IN_TRANSPORT;
8163 8168
8164 8169 mptsas_fma_check(mpt, cmd);
8165 8170
8166 8171 /*
8167 8172 * only add scsi pkts that have completion routines to
8168 8173 * the doneq. no intr cmds do not have callbacks.
8169 8174 */
8170 8175 if (pkt && (pkt->pkt_comp)) {
8171 8176 *mpt->m_donetail = cmd;
8172 8177 mpt->m_donetail = &cmd->cmd_linkp;
8173 8178 mpt->m_doneq_len++;
8174 8179 }
8175 8180 }
8176 8181
8177 8182 static mptsas_cmd_t *
8178 8183 mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t)
8179 8184 {
8180 8185 mptsas_cmd_t *cmd;
8181 8186 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
8182 8187
8183 8188 /* pop one off the done queue */
8184 8189 if ((cmd = item->doneq) != NULL) {
8185 8190 /* if the queue is now empty fix the tail pointer */
8186 8191 NDBG31(("mptsas_doneq_thread_rm: cmd=0x%p", (void *)cmd));
8187 8192 if ((item->doneq = cmd->cmd_linkp) == NULL) {
8188 8193 item->donetail = &item->doneq;
8189 8194 }
8190 8195 cmd->cmd_linkp = NULL;
8191 8196 item->len--;
8192 8197 }
8193 8198 return (cmd);
8194 8199 }
8195 8200
8196 8201 static void
8197 8202 mptsas_doneq_empty(mptsas_t *mpt)
8198 8203 {
8199 8204 if (mpt->m_doneq && !mpt->m_in_callback) {
8200 8205 mptsas_cmd_t *cmd, *next;
8201 8206 struct scsi_pkt *pkt;
8202 8207
8203 8208 mpt->m_in_callback = 1;
8204 8209 cmd = mpt->m_doneq;
8205 8210 mpt->m_doneq = NULL;
8206 8211 mpt->m_donetail = &mpt->m_doneq;
8207 8212 mpt->m_doneq_len = 0;
8208 8213
8209 8214 mutex_exit(&mpt->m_mutex);
8210 8215 /*
8211 8216 * run the completion routines of all the
8212 8217 * completed commands
8213 8218 */
8214 8219 while (cmd != NULL) {
8215 8220 next = cmd->cmd_linkp;
8216 8221 cmd->cmd_linkp = NULL;
8217 8222 /* run this command's completion routine */
8218 8223 cmd->cmd_flags |= CFLAG_COMPLETED;
8219 8224 pkt = CMD2PKT(cmd);
8220 8225 mptsas_pkt_comp(pkt, cmd);
8221 8226 cmd = next;
8222 8227 }
8223 8228 mutex_enter(&mpt->m_mutex);
8224 8229 mpt->m_in_callback = 0;
8225 8230 }
8226 8231 }
8227 8232
8228 8233 /*
8229 8234 * These routines manipulate the target's queue of pending requests
8230 8235 */
8231 8236 void
8232 8237 mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd)
8233 8238 {
8234 8239 NDBG7(("mptsas_waitq_add: cmd=0x%p", (void *)cmd));
8235 8240 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8236 8241 cmd->cmd_queued = TRUE;
8237 8242 if (ptgt)
8238 8243 ptgt->m_t_nwait++;
8239 8244 if (cmd->cmd_pkt_flags & FLAG_HEAD) {
8240 8245 if ((cmd->cmd_linkp = mpt->m_waitq) == NULL) {
8241 8246 mpt->m_waitqtail = &cmd->cmd_linkp;
8242 8247 }
8243 8248 mpt->m_waitq = cmd;
8244 8249 } else {
8245 8250 cmd->cmd_linkp = NULL;
8246 8251 *(mpt->m_waitqtail) = cmd;
8247 8252 mpt->m_waitqtail = &cmd->cmd_linkp;
8248 8253 }
8249 8254 }
8250 8255
8251 8256 static mptsas_cmd_t *
8252 8257 mptsas_waitq_rm(mptsas_t *mpt)
8253 8258 {
8254 8259 mptsas_cmd_t *cmd;
8255 8260 mptsas_target_t *ptgt;
8256 8261 NDBG7(("mptsas_waitq_rm"));
8257 8262
8258 8263 MPTSAS_WAITQ_RM(mpt, cmd);
8259 8264
8260 8265 NDBG7(("mptsas_waitq_rm: cmd=0x%p", (void *)cmd));
8261 8266 if (cmd) {
8262 8267 ptgt = cmd->cmd_tgt_addr;
8263 8268 if (ptgt) {
8264 8269 ptgt->m_t_nwait--;
8265 8270 ASSERT(ptgt->m_t_nwait >= 0);
8266 8271 }
8267 8272 }
8268 8273 return (cmd);
8269 8274 }
8270 8275
8271 8276 /*
8272 8277 * remove specified cmd from the middle of the wait queue.
8273 8278 */
8274 8279 static void
8275 8280 mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd)
8276 8281 {
8277 8282 mptsas_cmd_t *prevp = mpt->m_waitq;
8278 8283 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8279 8284
8280 8285 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
8281 8286 (void *)mpt, (void *)cmd));
8282 8287 if (ptgt) {
8283 8288 ptgt->m_t_nwait--;
8284 8289 ASSERT(ptgt->m_t_nwait >= 0);
8285 8290 }
8286 8291
8287 8292 if (prevp == cmd) {
8288 8293 if ((mpt->m_waitq = cmd->cmd_linkp) == NULL)
8289 8294 mpt->m_waitqtail = &mpt->m_waitq;
8290 8295
8291 8296 cmd->cmd_linkp = NULL;
8292 8297 cmd->cmd_queued = FALSE;
8293 8298 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
8294 8299 (void *)mpt, (void *)cmd));
8295 8300 return;
8296 8301 }
8297 8302
8298 8303 while (prevp != NULL) {
8299 8304 if (prevp->cmd_linkp == cmd) {
8300 8305 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL)
8301 8306 mpt->m_waitqtail = &prevp->cmd_linkp;
8302 8307
8303 8308 cmd->cmd_linkp = NULL;
8304 8309 cmd->cmd_queued = FALSE;
8305 8310 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
8306 8311 (void *)mpt, (void *)cmd));
8307 8312 return;
8308 8313 }
8309 8314 prevp = prevp->cmd_linkp;
8310 8315 }
8311 8316 cmn_err(CE_PANIC, "mpt: mptsas_waitq_delete: queue botch");
8312 8317 }
8313 8318
8314 8319 static mptsas_cmd_t *
8315 8320 mptsas_tx_waitq_rm(mptsas_t *mpt)
8316 8321 {
8317 8322 mptsas_cmd_t *cmd;
8318 8323 NDBG7(("mptsas_tx_waitq_rm"));
8319 8324
8320 8325 MPTSAS_TX_WAITQ_RM(mpt, cmd);
8321 8326
8322 8327 NDBG7(("mptsas_tx_waitq_rm: cmd=0x%p", (void *)cmd));
8323 8328
8324 8329 return (cmd);
8325 8330 }
8326 8331
8327 8332 /*
8328 8333 * remove specified cmd from the middle of the tx_waitq.
8329 8334 */
8330 8335 static void
8331 8336 mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd)
8332 8337 {
8333 8338 mptsas_cmd_t *prevp = mpt->m_tx_waitq;
8334 8339
8335 8340 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p",
8336 8341 (void *)mpt, (void *)cmd));
8337 8342
8338 8343 if (prevp == cmd) {
8339 8344 if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL)
8340 8345 mpt->m_tx_waitqtail = &mpt->m_tx_waitq;
8341 8346
8342 8347 cmd->cmd_linkp = NULL;
8343 8348 cmd->cmd_queued = FALSE;
8344 8349 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p",
8345 8350 (void *)mpt, (void *)cmd));
8346 8351 return;
8347 8352 }
8348 8353
8349 8354 while (prevp != NULL) {
8350 8355 if (prevp->cmd_linkp == cmd) {
8351 8356 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL)
8352 8357 mpt->m_tx_waitqtail = &prevp->cmd_linkp;
8353 8358
8354 8359 cmd->cmd_linkp = NULL;
8355 8360 cmd->cmd_queued = FALSE;
8356 8361 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p",
8357 8362 (void *)mpt, (void *)cmd));
8358 8363 return;
8359 8364 }
8360 8365 prevp = prevp->cmd_linkp;
8361 8366 }
8362 8367 cmn_err(CE_PANIC, "mpt: mptsas_tx_waitq_delete: queue botch");
8363 8368 }
8364 8369
8365 8370 /*
8366 8371 * device and bus reset handling
8367 8372 *
8368 8373 * Notes:
8369 8374 * - RESET_ALL: reset the controller
8370 8375 * - RESET_TARGET: reset the target specified in scsi_address
8371 8376 */
8372 8377 static int
8373 8378 mptsas_scsi_reset(struct scsi_address *ap, int level)
8374 8379 {
8375 8380 mptsas_t *mpt = ADDR2MPT(ap);
8376 8381 int rval;
8377 8382 mptsas_tgt_private_t *tgt_private;
8378 8383 mptsas_target_t *ptgt = NULL;
8379 8384
8380 8385 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->tran_tgt_private;
8381 8386 ptgt = tgt_private->t_private;
8382 8387 if (ptgt == NULL) {
8383 8388 return (FALSE);
8384 8389 }
8385 8390 NDBG22(("mptsas_scsi_reset: target=%d level=%d", ptgt->m_devhdl,
8386 8391 level));
8387 8392
8388 8393 mutex_enter(&mpt->m_mutex);
8389 8394 /*
8390 8395 * if we are not in panic set up a reset delay for this target
8391 8396 */
8392 8397 if (!ddi_in_panic()) {
8393 8398 mptsas_setup_bus_reset_delay(mpt);
8394 8399 } else {
8395 8400 drv_usecwait(mpt->m_scsi_reset_delay * 1000);
8396 8401 }
8397 8402 rval = mptsas_do_scsi_reset(mpt, ptgt->m_devhdl);
8398 8403 mutex_exit(&mpt->m_mutex);
8399 8404
8400 8405 /*
8401 8406 * The transport layer expect to only see TRUE and
8402 8407 * FALSE. Therefore, we will adjust the return value
8403 8408 * if mptsas_do_scsi_reset returns FAILED.
8404 8409 */
8405 8410 if (rval == FAILED)
8406 8411 rval = FALSE;
8407 8412 return (rval);
8408 8413 }
8409 8414
8410 8415 static int
8411 8416 mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl)
8412 8417 {
8413 8418 int rval = FALSE;
8414 8419 uint8_t config, disk;
8415 8420 mptsas_slots_t *slots = mpt->m_active;
8416 8421
8417 8422 ASSERT(mutex_owned(&mpt->m_mutex));
8418 8423
8419 8424 if (mptsas_debug_resets) {
8420 8425 mptsas_log(mpt, CE_WARN, "mptsas_do_scsi_reset: target=%d",
8421 8426 devhdl);
8422 8427 }
8423 8428
8424 8429 /*
8425 8430 * Issue a Target Reset message to the target specified but not to a
8426 8431 * disk making up a raid volume. Just look through the RAID config
8427 8432 * Phys Disk list of DevHandles. If the target's DevHandle is in this
8428 8433 * list, then don't reset this target.
8429 8434 */
8430 8435 for (config = 0; config < slots->m_num_raid_configs; config++) {
8431 8436 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) {
8432 8437 if (devhdl == slots->m_raidconfig[config].
8433 8438 m_physdisk_devhdl[disk]) {
8434 8439 return (TRUE);
8435 8440 }
8436 8441 }
8437 8442 }
8438 8443
8439 8444 rval = mptsas_ioc_task_management(mpt,
8440 8445 MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, devhdl, 0, NULL, 0, 0);
8441 8446
8442 8447 mptsas_doneq_empty(mpt);
8443 8448 return (rval);
8444 8449 }
8445 8450
8446 8451 static int
8447 8452 mptsas_scsi_reset_notify(struct scsi_address *ap, int flag,
8448 8453 void (*callback)(caddr_t), caddr_t arg)
8449 8454 {
8450 8455 mptsas_t *mpt = ADDR2MPT(ap);
8451 8456
8452 8457 NDBG22(("mptsas_scsi_reset_notify: tgt=%d", ap->a_target));
8453 8458
8454 8459 return (scsi_hba_reset_notify_setup(ap, flag, callback, arg,
8455 8460 &mpt->m_mutex, &mpt->m_reset_notify_listf));
8456 8461 }
8457 8462
8458 8463 static int
8459 8464 mptsas_get_name(struct scsi_device *sd, char *name, int len)
8460 8465 {
8461 8466 dev_info_t *lun_dip = NULL;
8462 8467
8463 8468 ASSERT(sd != NULL);
8464 8469 ASSERT(name != NULL);
8465 8470 lun_dip = sd->sd_dev;
8466 8471 ASSERT(lun_dip != NULL);
8467 8472
8468 8473 if (mptsas_name_child(lun_dip, name, len) == DDI_SUCCESS) {
8469 8474 return (1);
8470 8475 } else {
8471 8476 return (0);
8472 8477 }
8473 8478 }
8474 8479
8475 8480 static int
8476 8481 mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len)
8477 8482 {
8478 8483 return (mptsas_get_name(sd, name, len));
8479 8484 }
8480 8485
8481 8486 void
8482 8487 mptsas_set_throttle(mptsas_t *mpt, mptsas_target_t *ptgt, int what)
8483 8488 {
8484 8489
8485 8490 NDBG25(("mptsas_set_throttle: throttle=%x", what));
8486 8491
8487 8492 /*
8488 8493 * if the bus is draining/quiesced, no changes to the throttles
8489 8494 * are allowed. Not allowing change of throttles during draining
8490 8495 * limits error recovery but will reduce draining time
8491 8496 *
8492 8497 * all throttles should have been set to HOLD_THROTTLE
8493 8498 */
8494 8499 if (mpt->m_softstate & (MPTSAS_SS_QUIESCED | MPTSAS_SS_DRAINING)) {
8495 8500 return;
8496 8501 }
8497 8502
8498 8503 if (what == HOLD_THROTTLE) {
8499 8504 ptgt->m_t_throttle = HOLD_THROTTLE;
8500 8505 } else if (ptgt->m_reset_delay == 0) {
8501 8506 ptgt->m_t_throttle = what;
8502 8507 }
8503 8508 }
8504 8509
8505 8510 /*
8506 8511 * Clean up from a device reset.
8507 8512 * For the case of target reset, this function clears the waitq of all
8508 8513 * commands for a particular target. For the case of abort task set, this
8509 8514 * function clears the waitq of all commonds for a particular target/lun.
8510 8515 */
8511 8516 static void
8512 8517 mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, uint8_t tasktype)
8513 8518 {
8514 8519 mptsas_slots_t *slots = mpt->m_active;
8515 8520 mptsas_cmd_t *cmd, *next_cmd;
8516 8521 int slot;
8517 8522 uchar_t reason;
8518 8523 uint_t stat;
8519 8524
8520 8525 NDBG25(("mptsas_flush_target: target=%d lun=%d", target, lun));
8521 8526
8522 8527 /*
8523 8528 * Make sure the I/O Controller has flushed all cmds
8524 8529 * that are associated with this target for a target reset
8525 8530 * and target/lun for abort task set.
8526 8531 * Account for TM requests, which use the last SMID.
8527 8532 */
8528 8533 for (slot = 0; slot <= mpt->m_active->m_n_slots; slot++) {
8529 8534 if ((cmd = slots->m_slot[slot]) == NULL)
8530 8535 continue;
8531 8536 reason = CMD_RESET;
8532 8537 stat = STAT_DEV_RESET;
8533 8538 switch (tasktype) {
8534 8539 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
8535 8540 if (Tgt(cmd) == target) {
8536 8541 NDBG25(("mptsas_flush_target discovered non-"
8537 8542 "NULL cmd in slot %d, tasktype 0x%x", slot,
8538 8543 tasktype));
8539 8544 mptsas_dump_cmd(mpt, cmd);
8540 8545 mptsas_remove_cmd(mpt, cmd);
8541 8546 mptsas_set_pkt_reason(mpt, cmd, reason, stat);
8542 8547 mptsas_doneq_add(mpt, cmd);
8543 8548 }
8544 8549 break;
8545 8550 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
8546 8551 reason = CMD_ABORTED;
8547 8552 stat = STAT_ABORTED;
8548 8553 /*FALLTHROUGH*/
8549 8554 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
8550 8555 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
8551 8556
8552 8557 NDBG25(("mptsas_flush_target discovered non-"
8553 8558 "NULL cmd in slot %d, tasktype 0x%x", slot,
8554 8559 tasktype));
8555 8560 mptsas_dump_cmd(mpt, cmd);
8556 8561 mptsas_remove_cmd(mpt, cmd);
8557 8562 mptsas_set_pkt_reason(mpt, cmd, reason,
8558 8563 stat);
8559 8564 mptsas_doneq_add(mpt, cmd);
8560 8565 }
8561 8566 break;
8562 8567 default:
8563 8568 break;
8564 8569 }
8565 8570 }
8566 8571
8567 8572 /*
8568 8573 * Flush the waitq and tx_waitq of this target's cmds
8569 8574 */
8570 8575 cmd = mpt->m_waitq;
8571 8576
8572 8577 reason = CMD_RESET;
8573 8578 stat = STAT_DEV_RESET;
8574 8579
8575 8580 switch (tasktype) {
8576 8581 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
8577 8582 while (cmd != NULL) {
8578 8583 next_cmd = cmd->cmd_linkp;
8579 8584 if (Tgt(cmd) == target) {
8580 8585 mptsas_waitq_delete(mpt, cmd);
8581 8586 mptsas_set_pkt_reason(mpt, cmd,
8582 8587 reason, stat);
8583 8588 mptsas_doneq_add(mpt, cmd);
8584 8589 }
8585 8590 cmd = next_cmd;
8586 8591 }
8587 8592 mutex_enter(&mpt->m_tx_waitq_mutex);
8588 8593 cmd = mpt->m_tx_waitq;
8589 8594 while (cmd != NULL) {
8590 8595 next_cmd = cmd->cmd_linkp;
8591 8596 if (Tgt(cmd) == target) {
8592 8597 mptsas_tx_waitq_delete(mpt, cmd);
8593 8598 mutex_exit(&mpt->m_tx_waitq_mutex);
8594 8599 mptsas_set_pkt_reason(mpt, cmd,
8595 8600 reason, stat);
8596 8601 mptsas_doneq_add(mpt, cmd);
8597 8602 mutex_enter(&mpt->m_tx_waitq_mutex);
8598 8603 }
8599 8604 cmd = next_cmd;
8600 8605 }
8601 8606 mutex_exit(&mpt->m_tx_waitq_mutex);
8602 8607 break;
8603 8608 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
8604 8609 reason = CMD_ABORTED;
8605 8610 stat = STAT_ABORTED;
8606 8611 /*FALLTHROUGH*/
8607 8612 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
8608 8613 while (cmd != NULL) {
8609 8614 next_cmd = cmd->cmd_linkp;
8610 8615 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
8611 8616 mptsas_waitq_delete(mpt, cmd);
8612 8617 mptsas_set_pkt_reason(mpt, cmd,
8613 8618 reason, stat);
8614 8619 mptsas_doneq_add(mpt, cmd);
8615 8620 }
8616 8621 cmd = next_cmd;
8617 8622 }
8618 8623 mutex_enter(&mpt->m_tx_waitq_mutex);
8619 8624 cmd = mpt->m_tx_waitq;
8620 8625 while (cmd != NULL) {
8621 8626 next_cmd = cmd->cmd_linkp;
8622 8627 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
8623 8628 mptsas_tx_waitq_delete(mpt, cmd);
8624 8629 mutex_exit(&mpt->m_tx_waitq_mutex);
8625 8630 mptsas_set_pkt_reason(mpt, cmd,
8626 8631 reason, stat);
8627 8632 mptsas_doneq_add(mpt, cmd);
8628 8633 mutex_enter(&mpt->m_tx_waitq_mutex);
8629 8634 }
8630 8635 cmd = next_cmd;
8631 8636 }
8632 8637 mutex_exit(&mpt->m_tx_waitq_mutex);
8633 8638 break;
8634 8639 default:
8635 8640 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.",
8636 8641 tasktype);
8637 8642 break;
8638 8643 }
8639 8644 }
8640 8645
8641 8646 /*
8642 8647 * Clean up hba state, abort all outstanding command and commands in waitq
8643 8648 * reset timeout of all targets.
8644 8649 */
8645 8650 static void
8646 8651 mptsas_flush_hba(mptsas_t *mpt)
8647 8652 {
8648 8653 mptsas_slots_t *slots = mpt->m_active;
8649 8654 mptsas_cmd_t *cmd;
8650 8655 int slot;
8651 8656
8652 8657 NDBG25(("mptsas_flush_hba"));
8653 8658
8654 8659 /*
8655 8660 * The I/O Controller should have already sent back
8656 8661 * all commands via the scsi I/O reply frame. Make
8657 8662 * sure all commands have been flushed.
8658 8663 * Account for TM request, which use the last SMID.
8659 8664 */
8660 8665 for (slot = 0; slot <= mpt->m_active->m_n_slots; slot++) {
8661 8666 if ((cmd = slots->m_slot[slot]) == NULL)
8662 8667 continue;
8663 8668
8664 8669 if (cmd->cmd_flags & CFLAG_CMDIOC) {
8665 8670 /*
8666 8671 * Need to make sure to tell everyone that might be
8667 8672 * waiting on this command that it's going to fail. If
8668 8673 * we get here, this command will never timeout because
8669 8674 * the active command table is going to be re-allocated,
8670 8675 * so there will be nothing to check against a time out.
8671 8676 * Instead, mark the command as failed due to reset.
8672 8677 */
8673 8678 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET,
8674 8679 STAT_BUS_RESET);
8675 8680 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
8676 8681 (cmd->cmd_flags & CFLAG_CONFIG) ||
8677 8682 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
8678 8683 cmd->cmd_flags |= CFLAG_FINISHED;
8679 8684 cv_broadcast(&mpt->m_passthru_cv);
8680 8685 cv_broadcast(&mpt->m_config_cv);
8681 8686 cv_broadcast(&mpt->m_fw_diag_cv);
8682 8687 }
8683 8688 continue;
8684 8689 }
8685 8690
8686 8691 NDBG25(("mptsas_flush_hba discovered non-NULL cmd in slot %d",
8687 8692 slot));
8688 8693 mptsas_dump_cmd(mpt, cmd);
8689 8694
8690 8695 mptsas_remove_cmd(mpt, cmd);
8691 8696 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
8692 8697 mptsas_doneq_add(mpt, cmd);
8693 8698 }
8694 8699
8695 8700 /*
8696 8701 * Flush the waitq.
8697 8702 */
8698 8703 while ((cmd = mptsas_waitq_rm(mpt)) != NULL) {
8699 8704 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
8700 8705 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
8701 8706 (cmd->cmd_flags & CFLAG_CONFIG) ||
8702 8707 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
8703 8708 cmd->cmd_flags |= CFLAG_FINISHED;
8704 8709 cv_broadcast(&mpt->m_passthru_cv);
8705 8710 cv_broadcast(&mpt->m_config_cv);
8706 8711 cv_broadcast(&mpt->m_fw_diag_cv);
8707 8712 } else {
8708 8713 mptsas_doneq_add(mpt, cmd);
8709 8714 }
8710 8715 }
8711 8716
8712 8717 /*
8713 8718 * Flush the tx_waitq
8714 8719 */
8715 8720 mutex_enter(&mpt->m_tx_waitq_mutex);
8716 8721 while ((cmd = mptsas_tx_waitq_rm(mpt)) != NULL) {
8717 8722 mutex_exit(&mpt->m_tx_waitq_mutex);
8718 8723 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
8719 8724 mptsas_doneq_add(mpt, cmd);
8720 8725 mutex_enter(&mpt->m_tx_waitq_mutex);
8721 8726 }
8722 8727 mutex_exit(&mpt->m_tx_waitq_mutex);
8723 8728
8724 8729 /*
8725 8730 * Drain the taskqs prior to reallocating resources.
8726 8731 */
8727 8732 mutex_exit(&mpt->m_mutex);
8728 8733 ddi_taskq_wait(mpt->m_event_taskq);
8729 8734 ddi_taskq_wait(mpt->m_dr_taskq);
8730 8735 mutex_enter(&mpt->m_mutex);
8731 8736 }
8732 8737
8733 8738 /*
8734 8739 * set pkt_reason and OR in pkt_statistics flag
8735 8740 */
8736 8741 static void
8737 8742 mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, uchar_t reason,
8738 8743 uint_t stat)
8739 8744 {
8740 8745 #ifndef __lock_lint
8741 8746 _NOTE(ARGUNUSED(mpt))
8742 8747 #endif
8743 8748
8744 8749 NDBG25(("mptsas_set_pkt_reason: cmd=0x%p reason=%x stat=%x",
8745 8750 (void *)cmd, reason, stat));
8746 8751
8747 8752 if (cmd) {
8748 8753 if (cmd->cmd_pkt->pkt_reason == CMD_CMPLT) {
8749 8754 cmd->cmd_pkt->pkt_reason = reason;
8750 8755 }
8751 8756 cmd->cmd_pkt->pkt_statistics |= stat;
8752 8757 }
8753 8758 }
8754 8759
8755 8760 static void
8756 8761 mptsas_start_watch_reset_delay()
8757 8762 {
8758 8763 NDBG22(("mptsas_start_watch_reset_delay"));
8759 8764
8760 8765 mutex_enter(&mptsas_global_mutex);
8761 8766 if (mptsas_reset_watch == NULL && mptsas_timeouts_enabled) {
8762 8767 mptsas_reset_watch = timeout(mptsas_watch_reset_delay, NULL,
8763 8768 drv_usectohz((clock_t)
8764 8769 MPTSAS_WATCH_RESET_DELAY_TICK * 1000));
8765 8770 ASSERT(mptsas_reset_watch != NULL);
8766 8771 }
8767 8772 mutex_exit(&mptsas_global_mutex);
8768 8773 }
8769 8774
8770 8775 static void
8771 8776 mptsas_setup_bus_reset_delay(mptsas_t *mpt)
8772 8777 {
8773 8778 mptsas_target_t *ptgt = NULL;
8774 8779
8775 8780 NDBG22(("mptsas_setup_bus_reset_delay"));
8776 8781 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
8777 8782 MPTSAS_HASH_FIRST);
8778 8783 while (ptgt != NULL) {
8779 8784 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
8780 8785 ptgt->m_reset_delay = mpt->m_scsi_reset_delay;
8781 8786
8782 8787 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
8783 8788 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
8784 8789 }
8785 8790
8786 8791 mptsas_start_watch_reset_delay();
8787 8792 }
8788 8793
8789 8794 /*
8790 8795 * mptsas_watch_reset_delay(_subr) is invoked by timeout() and checks every
8791 8796 * mpt instance for active reset delays
8792 8797 */
8793 8798 static void
8794 8799 mptsas_watch_reset_delay(void *arg)
8795 8800 {
8796 8801 #ifndef __lock_lint
8797 8802 _NOTE(ARGUNUSED(arg))
8798 8803 #endif
8799 8804
8800 8805 mptsas_t *mpt;
8801 8806 int not_done = 0;
8802 8807
8803 8808 NDBG22(("mptsas_watch_reset_delay"));
8804 8809
8805 8810 mutex_enter(&mptsas_global_mutex);
8806 8811 mptsas_reset_watch = 0;
8807 8812 mutex_exit(&mptsas_global_mutex);
8808 8813 rw_enter(&mptsas_global_rwlock, RW_READER);
8809 8814 for (mpt = mptsas_head; mpt != NULL; mpt = mpt->m_next) {
8810 8815 if (mpt->m_tran == 0) {
8811 8816 continue;
8812 8817 }
8813 8818 mutex_enter(&mpt->m_mutex);
8814 8819 not_done += mptsas_watch_reset_delay_subr(mpt);
8815 8820 mutex_exit(&mpt->m_mutex);
8816 8821 }
8817 8822 rw_exit(&mptsas_global_rwlock);
8818 8823
8819 8824 if (not_done) {
8820 8825 mptsas_start_watch_reset_delay();
8821 8826 }
8822 8827 }
8823 8828
8824 8829 static int
8825 8830 mptsas_watch_reset_delay_subr(mptsas_t *mpt)
8826 8831 {
8827 8832 int done = 0;
8828 8833 int restart = 0;
8829 8834 mptsas_target_t *ptgt = NULL;
8830 8835
8831 8836 NDBG22(("mptsas_watch_reset_delay_subr: mpt=0x%p", (void *)mpt));
8832 8837
8833 8838 ASSERT(mutex_owned(&mpt->m_mutex));
8834 8839
8835 8840 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
8836 8841 MPTSAS_HASH_FIRST);
8837 8842 while (ptgt != NULL) {
8838 8843 if (ptgt->m_reset_delay != 0) {
8839 8844 ptgt->m_reset_delay -=
8840 8845 MPTSAS_WATCH_RESET_DELAY_TICK;
8841 8846 if (ptgt->m_reset_delay <= 0) {
8842 8847 ptgt->m_reset_delay = 0;
8843 8848 mptsas_set_throttle(mpt, ptgt,
8844 8849 MAX_THROTTLE);
8845 8850 restart++;
8846 8851 } else {
8847 8852 done = -1;
8848 8853 }
8849 8854 }
8850 8855
8851 8856 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
8852 8857 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
8853 8858 }
8854 8859
8855 8860 if (restart > 0) {
8856 8861 mptsas_restart_hba(mpt);
8857 8862 }
8858 8863 return (done);
8859 8864 }
8860 8865
8861 8866 #ifdef MPTSAS_TEST
8862 8867 static void
8863 8868 mptsas_test_reset(mptsas_t *mpt, int target)
8864 8869 {
8865 8870 mptsas_target_t *ptgt = NULL;
8866 8871
8867 8872 if (mptsas_rtest == target) {
8868 8873 if (mptsas_do_scsi_reset(mpt, target) == TRUE) {
8869 8874 mptsas_rtest = -1;
8870 8875 }
8871 8876 if (mptsas_rtest == -1) {
8872 8877 NDBG22(("mptsas_test_reset success"));
8873 8878 }
8874 8879 }
8875 8880 }
8876 8881 #endif
8877 8882
8878 8883 /*
8879 8884 * abort handling:
8880 8885 *
8881 8886 * Notes:
8882 8887 * - if pkt is not NULL, abort just that command
8883 8888 * - if pkt is NULL, abort all outstanding commands for target
8884 8889 */
8885 8890 static int
8886 8891 mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt)
8887 8892 {
8888 8893 mptsas_t *mpt = ADDR2MPT(ap);
8889 8894 int rval;
8890 8895 mptsas_tgt_private_t *tgt_private;
8891 8896 int target, lun;
8892 8897
8893 8898 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->
8894 8899 tran_tgt_private;
8895 8900 ASSERT(tgt_private != NULL);
8896 8901 target = tgt_private->t_private->m_devhdl;
8897 8902 lun = tgt_private->t_lun;
8898 8903
8899 8904 NDBG23(("mptsas_scsi_abort: target=%d.%d", target, lun));
8900 8905
8901 8906 mutex_enter(&mpt->m_mutex);
8902 8907 rval = mptsas_do_scsi_abort(mpt, target, lun, pkt);
8903 8908 mutex_exit(&mpt->m_mutex);
8904 8909 return (rval);
8905 8910 }
8906 8911
8907 8912 static int
8908 8913 mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, struct scsi_pkt *pkt)
8909 8914 {
8910 8915 mptsas_cmd_t *sp = NULL;
8911 8916 mptsas_slots_t *slots = mpt->m_active;
8912 8917 int rval = FALSE;
8913 8918
8914 8919 ASSERT(mutex_owned(&mpt->m_mutex));
8915 8920
8916 8921 /*
8917 8922 * Abort the command pkt on the target/lun in ap. If pkt is
8918 8923 * NULL, abort all outstanding commands on that target/lun.
8919 8924 * If you can abort them, return 1, else return 0.
8920 8925 * Each packet that's aborted should be sent back to the target
8921 8926 * driver through the callback routine, with pkt_reason set to
8922 8927 * CMD_ABORTED.
8923 8928 *
8924 8929 * abort cmd pkt on HBA hardware; clean out of outstanding
8925 8930 * command lists, etc.
8926 8931 */
8927 8932 if (pkt != NULL) {
8928 8933 /* abort the specified packet */
8929 8934 sp = PKT2CMD(pkt);
8930 8935
8931 8936 if (sp->cmd_queued) {
8932 8937 NDBG23(("mptsas_do_scsi_abort: queued sp=0x%p aborted",
8933 8938 (void *)sp));
8934 8939 mptsas_waitq_delete(mpt, sp);
8935 8940 mptsas_set_pkt_reason(mpt, sp, CMD_ABORTED,
8936 8941 STAT_ABORTED);
8937 8942 mptsas_doneq_add(mpt, sp);
8938 8943 rval = TRUE;
8939 8944 goto done;
8940 8945 }
8941 8946
8942 8947 /*
8943 8948 * Have mpt firmware abort this command
8944 8949 */
8945 8950
8946 8951 if (slots->m_slot[sp->cmd_slot] != NULL) {
8947 8952 rval = mptsas_ioc_task_management(mpt,
8948 8953 MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK, target,
8949 8954 lun, NULL, 0, 0);
8950 8955
8951 8956 /*
8952 8957 * The transport layer expects only TRUE and FALSE.
8953 8958 * Therefore, if mptsas_ioc_task_management returns
8954 8959 * FAILED we will return FALSE.
8955 8960 */
8956 8961 if (rval == FAILED)
8957 8962 rval = FALSE;
8958 8963 goto done;
8959 8964 }
8960 8965 }
8961 8966
8962 8967 /*
8963 8968 * If pkt is NULL then abort task set
8964 8969 */
8965 8970 rval = mptsas_ioc_task_management(mpt,
8966 8971 MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET, target, lun, NULL, 0, 0);
8967 8972
8968 8973 /*
8969 8974 * The transport layer expects only TRUE and FALSE.
8970 8975 * Therefore, if mptsas_ioc_task_management returns
8971 8976 * FAILED we will return FALSE.
8972 8977 */
8973 8978 if (rval == FAILED)
8974 8979 rval = FALSE;
8975 8980
8976 8981 #ifdef MPTSAS_TEST
8977 8982 if (rval && mptsas_test_stop) {
8978 8983 debug_enter("mptsas_do_scsi_abort");
8979 8984 }
8980 8985 #endif
8981 8986
8982 8987 done:
8983 8988 mptsas_doneq_empty(mpt);
8984 8989 return (rval);
8985 8990 }
8986 8991
8987 8992 /*
8988 8993 * capability handling:
8989 8994 * (*tran_getcap). Get the capability named, and return its value.
8990 8995 */
8991 8996 static int
8992 8997 mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly)
8993 8998 {
8994 8999 mptsas_t *mpt = ADDR2MPT(ap);
8995 9000 int ckey;
8996 9001 int rval = FALSE;
8997 9002
8998 9003 NDBG24(("mptsas_scsi_getcap: target=%d, cap=%s tgtonly=%x",
8999 9004 ap->a_target, cap, tgtonly));
9000 9005
9001 9006 mutex_enter(&mpt->m_mutex);
9002 9007
9003 9008 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) {
9004 9009 mutex_exit(&mpt->m_mutex);
9005 9010 return (UNDEFINED);
9006 9011 }
9007 9012
9008 9013 switch (ckey) {
9009 9014 case SCSI_CAP_DMA_MAX:
9010 9015 rval = (int)mpt->m_msg_dma_attr.dma_attr_maxxfer;
9011 9016 break;
9012 9017 case SCSI_CAP_ARQ:
9013 9018 rval = TRUE;
9014 9019 break;
9015 9020 case SCSI_CAP_MSG_OUT:
9016 9021 case SCSI_CAP_PARITY:
9017 9022 case SCSI_CAP_UNTAGGED_QING:
9018 9023 rval = TRUE;
9019 9024 break;
9020 9025 case SCSI_CAP_TAGGED_QING:
9021 9026 rval = TRUE;
9022 9027 break;
9023 9028 case SCSI_CAP_RESET_NOTIFICATION:
9024 9029 rval = TRUE;
9025 9030 break;
9026 9031 case SCSI_CAP_LINKED_CMDS:
9027 9032 rval = FALSE;
9028 9033 break;
9029 9034 case SCSI_CAP_QFULL_RETRIES:
9030 9035 rval = ((mptsas_tgt_private_t *)(ap->a_hba_tran->
9031 9036 tran_tgt_private))->t_private->m_qfull_retries;
9032 9037 break;
9033 9038 case SCSI_CAP_QFULL_RETRY_INTERVAL:
9034 9039 rval = drv_hztousec(((mptsas_tgt_private_t *)
9035 9040 (ap->a_hba_tran->tran_tgt_private))->
9036 9041 t_private->m_qfull_retry_interval) / 1000;
9037 9042 break;
9038 9043 case SCSI_CAP_CDB_LEN:
9039 9044 rval = CDB_GROUP4;
9040 9045 break;
9041 9046 case SCSI_CAP_INTERCONNECT_TYPE:
9042 9047 rval = INTERCONNECT_SAS;
9043 9048 break;
9044 9049 case SCSI_CAP_TRAN_LAYER_RETRIES:
9045 9050 if (mpt->m_ioc_capabilities &
9046 9051 MPI2_IOCFACTS_CAPABILITY_TLR)
9047 9052 rval = TRUE;
9048 9053 else
9049 9054 rval = FALSE;
9050 9055 break;
9051 9056 default:
9052 9057 rval = UNDEFINED;
9053 9058 break;
9054 9059 }
9055 9060
9056 9061 NDBG24(("mptsas_scsi_getcap: %s, rval=%x", cap, rval));
9057 9062
9058 9063 mutex_exit(&mpt->m_mutex);
9059 9064 return (rval);
9060 9065 }
9061 9066
9062 9067 /*
9063 9068 * (*tran_setcap). Set the capability named to the value given.
9064 9069 */
9065 9070 static int
9066 9071 mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, int tgtonly)
9067 9072 {
9068 9073 mptsas_t *mpt = ADDR2MPT(ap);
9069 9074 int ckey;
9070 9075 int rval = FALSE;
9071 9076
9072 9077 NDBG24(("mptsas_scsi_setcap: target=%d, cap=%s value=%x tgtonly=%x",
9073 9078 ap->a_target, cap, value, tgtonly));
9074 9079
9075 9080 if (!tgtonly) {
9076 9081 return (rval);
9077 9082 }
9078 9083
9079 9084 mutex_enter(&mpt->m_mutex);
9080 9085
9081 9086 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) {
9082 9087 mutex_exit(&mpt->m_mutex);
9083 9088 return (UNDEFINED);
9084 9089 }
9085 9090
9086 9091 switch (ckey) {
9087 9092 case SCSI_CAP_DMA_MAX:
9088 9093 case SCSI_CAP_MSG_OUT:
9089 9094 case SCSI_CAP_PARITY:
9090 9095 case SCSI_CAP_INITIATOR_ID:
9091 9096 case SCSI_CAP_LINKED_CMDS:
9092 9097 case SCSI_CAP_UNTAGGED_QING:
9093 9098 case SCSI_CAP_RESET_NOTIFICATION:
9094 9099 /*
9095 9100 * None of these are settable via
9096 9101 * the capability interface.
9097 9102 */
9098 9103 break;
9099 9104 case SCSI_CAP_ARQ:
9100 9105 /*
9101 9106 * We cannot turn off arq so return false if asked to
9102 9107 */
9103 9108 if (value) {
9104 9109 rval = TRUE;
9105 9110 } else {
9106 9111 rval = FALSE;
9107 9112 }
9108 9113 break;
9109 9114 case SCSI_CAP_TAGGED_QING:
9110 9115 mptsas_set_throttle(mpt, ((mptsas_tgt_private_t *)
9111 9116 (ap->a_hba_tran->tran_tgt_private))->t_private,
9112 9117 MAX_THROTTLE);
9113 9118 rval = TRUE;
9114 9119 break;
9115 9120 case SCSI_CAP_QFULL_RETRIES:
9116 9121 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))->
9117 9122 t_private->m_qfull_retries = (uchar_t)value;
9118 9123 rval = TRUE;
9119 9124 break;
9120 9125 case SCSI_CAP_QFULL_RETRY_INTERVAL:
9121 9126 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))->
9122 9127 t_private->m_qfull_retry_interval =
9123 9128 drv_usectohz(value * 1000);
9124 9129 rval = TRUE;
9125 9130 break;
9126 9131 default:
9127 9132 rval = UNDEFINED;
9128 9133 break;
9129 9134 }
9130 9135 mutex_exit(&mpt->m_mutex);
9131 9136 return (rval);
9132 9137 }
9133 9138
9134 9139 /*
9135 9140 * Utility routine for mptsas_ifsetcap/ifgetcap
9136 9141 */
9137 9142 /*ARGSUSED*/
9138 9143 static int
9139 9144 mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp)
9140 9145 {
9141 9146 NDBG24(("mptsas_scsi_capchk: cap=%s", cap));
9142 9147
9143 9148 if (!cap)
9144 9149 return (FALSE);
9145 9150
9146 9151 *cidxp = scsi_hba_lookup_capstr(cap);
9147 9152 return (TRUE);
9148 9153 }
9149 9154
9150 9155 static int
9151 9156 mptsas_alloc_active_slots(mptsas_t *mpt, int flag)
9152 9157 {
9153 9158 mptsas_slots_t *old_active = mpt->m_active;
9154 9159 mptsas_slots_t *new_active;
9155 9160 size_t size;
9156 9161 int rval = -1, i;
9157 9162
9158 9163 /*
9159 9164 * if there are active commands, then we cannot
9160 9165 * change size of active slots array.
9161 9166 */
9162 9167 ASSERT(mpt->m_ncmds == 0);
9163 9168
9164 9169 size = MPTSAS_SLOTS_SIZE(mpt);
9165 9170 new_active = kmem_zalloc(size, flag);
9166 9171 if (new_active == NULL) {
9167 9172 NDBG1(("new active alloc failed"));
9168 9173 return (rval);
9169 9174 }
9170 9175 /*
9171 9176 * Since SMID 0 is reserved and the TM slot is reserved, the
9172 9177 * number of slots that can be used at any one time is
9173 9178 * m_max_requests - 2.
9174 9179 */
9175 9180 new_active->m_n_slots = (mpt->m_max_requests - 2);
9176 9181 new_active->m_size = size;
9177 9182 new_active->m_tags = 1;
9178 9183 if (old_active) {
9179 9184 new_active->m_tgttbl = old_active->m_tgttbl;
9180 9185 new_active->m_smptbl = old_active->m_smptbl;
9181 9186 new_active->m_num_raid_configs =
9182 9187 old_active->m_num_raid_configs;
9183 9188 for (i = 0; i < new_active->m_num_raid_configs; i++) {
9184 9189 new_active->m_raidconfig[i] =
9185 9190 old_active->m_raidconfig[i];
9186 9191 }
9187 9192 mptsas_free_active_slots(mpt);
9188 9193 }
9189 9194 mpt->m_active = new_active;
9190 9195 rval = 0;
9191 9196
9192 9197 return (rval);
9193 9198 }
9194 9199
9195 9200 static void
9196 9201 mptsas_free_active_slots(mptsas_t *mpt)
9197 9202 {
9198 9203 mptsas_slots_t *active = mpt->m_active;
9199 9204 size_t size;
9200 9205
9201 9206 if (active == NULL)
9202 9207 return;
9203 9208 size = active->m_size;
9204 9209 kmem_free(active, size);
9205 9210 mpt->m_active = NULL;
9206 9211 }
9207 9212
9208 9213 /*
9209 9214 * Error logging, printing, and debug print routines.
9210 9215 */
9211 9216 static char *mptsas_label = "mpt_sas";
9212 9217
9213 9218 /*PRINTFLIKE3*/
9214 9219 void
9215 9220 mptsas_log(mptsas_t *mpt, int level, char *fmt, ...)
9216 9221 {
9217 9222 dev_info_t *dev;
9218 9223 va_list ap;
9219 9224
9220 9225 if (mpt) {
9221 9226 dev = mpt->m_dip;
9222 9227 } else {
9223 9228 dev = 0;
9224 9229 }
9225 9230
9226 9231 mutex_enter(&mptsas_log_mutex);
9227 9232
9228 9233 va_start(ap, fmt);
9229 9234 (void) vsprintf(mptsas_log_buf, fmt, ap);
9230 9235 va_end(ap);
9231 9236
9232 9237 if (level == CE_CONT) {
9233 9238 scsi_log(dev, mptsas_label, level, "%s\n", mptsas_log_buf);
9234 9239 } else {
9235 9240 scsi_log(dev, mptsas_label, level, "%s", mptsas_log_buf);
9236 9241 }
9237 9242
9238 9243 mutex_exit(&mptsas_log_mutex);
9239 9244 }
9240 9245
9241 9246 #ifdef MPTSAS_DEBUG
9242 9247 /*PRINTFLIKE1*/
9243 9248 void
9244 9249 mptsas_printf(char *fmt, ...)
9245 9250 {
9246 9251 dev_info_t *dev = 0;
9247 9252 va_list ap;
9248 9253
9249 9254 mutex_enter(&mptsas_log_mutex);
9250 9255
9251 9256 va_start(ap, fmt);
9252 9257 (void) vsprintf(mptsas_log_buf, fmt, ap);
9253 9258 va_end(ap);
9254 9259
9255 9260 #ifdef PROM_PRINTF
9256 9261 prom_printf("%s:\t%s\n", mptsas_label, mptsas_log_buf);
9257 9262 #else
9258 9263 scsi_log(dev, mptsas_label, SCSI_DEBUG, "%s\n", mptsas_log_buf);
9259 9264 #endif
9260 9265 mutex_exit(&mptsas_log_mutex);
9261 9266 }
9262 9267 #endif
9263 9268
9264 9269 /*
9265 9270 * timeout handling
9266 9271 */
9267 9272 static void
9268 9273 mptsas_watch(void *arg)
9269 9274 {
9270 9275 #ifndef __lock_lint
9271 9276 _NOTE(ARGUNUSED(arg))
9272 9277 #endif
9273 9278
9274 9279 mptsas_t *mpt;
9275 9280 uint32_t doorbell;
9276 9281
9277 9282 NDBG30(("mptsas_watch"));
9278 9283
9279 9284 rw_enter(&mptsas_global_rwlock, RW_READER);
9280 9285 for (mpt = mptsas_head; mpt != (mptsas_t *)NULL; mpt = mpt->m_next) {
9281 9286
9282 9287 mutex_enter(&mpt->m_mutex);
9283 9288
9284 9289 /* Skip device if not powered on */
9285 9290 if (mpt->m_options & MPTSAS_OPT_PM) {
9286 9291 if (mpt->m_power_level == PM_LEVEL_D0) {
9287 9292 (void) pm_busy_component(mpt->m_dip, 0);
9288 9293 mpt->m_busy = 1;
9289 9294 } else {
9290 9295 mutex_exit(&mpt->m_mutex);
9291 9296 continue;
9292 9297 }
9293 9298 }
9294 9299
9295 9300 /*
9296 9301 * Check if controller is in a FAULT state. If so, reset it.
9297 9302 */
9298 9303 doorbell = ddi_get32(mpt->m_datap, &mpt->m_reg->Doorbell);
9299 9304 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
9300 9305 doorbell &= MPI2_DOORBELL_DATA_MASK;
9301 9306 mptsas_log(mpt, CE_WARN, "MPT Firmware Fault, "
9302 9307 "code: %04x", doorbell);
9303 9308 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
9304 9309 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
9305 9310 mptsas_log(mpt, CE_WARN, "Reset failed"
9306 9311 "after fault was detected");
9307 9312 }
9308 9313 }
9309 9314
9310 9315 /*
9311 9316 * For now, always call mptsas_watchsubr.
9312 9317 */
9313 9318 mptsas_watchsubr(mpt);
9314 9319
9315 9320 if (mpt->m_options & MPTSAS_OPT_PM) {
9316 9321 mpt->m_busy = 0;
9317 9322 (void) pm_idle_component(mpt->m_dip, 0);
9318 9323 }
9319 9324
9320 9325 mutex_exit(&mpt->m_mutex);
9321 9326 }
9322 9327 rw_exit(&mptsas_global_rwlock);
9323 9328
9324 9329 mutex_enter(&mptsas_global_mutex);
9325 9330 if (mptsas_timeouts_enabled)
9326 9331 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick);
9327 9332 mutex_exit(&mptsas_global_mutex);
9328 9333 }
9329 9334
9330 9335 static void
9331 9336 mptsas_watchsubr(mptsas_t *mpt)
9332 9337 {
9333 9338 int i;
9334 9339 mptsas_cmd_t *cmd;
9335 9340 mptsas_target_t *ptgt = NULL;
9336 9341
9337 9342 NDBG30(("mptsas_watchsubr: mpt=0x%p", (void *)mpt));
9338 9343
9339 9344 #ifdef MPTSAS_TEST
9340 9345 if (mptsas_enable_untagged) {
9341 9346 mptsas_test_untagged++;
9342 9347 }
9343 9348 #endif
9344 9349
9345 9350 /*
9346 9351 * Check for commands stuck in active slot
9347 9352 * Account for TM requests, which use the last SMID.
9348 9353 */
9349 9354 for (i = 0; i <= mpt->m_active->m_n_slots; i++) {
9350 9355 if ((cmd = mpt->m_active->m_slot[i]) != NULL) {
9351 9356 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
9352 9357 cmd->cmd_active_timeout -=
9353 9358 mptsas_scsi_watchdog_tick;
9354 9359 if (cmd->cmd_active_timeout <= 0) {
9355 9360 /*
9356 9361 * There seems to be a command stuck
9357 9362 * in the active slot. Drain throttle.
9358 9363 */
9359 9364 mptsas_set_throttle(mpt,
9360 9365 cmd->cmd_tgt_addr,
9361 9366 DRAIN_THROTTLE);
9362 9367 }
9363 9368 }
9364 9369 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
9365 9370 (cmd->cmd_flags & CFLAG_CONFIG) ||
9366 9371 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
9367 9372 cmd->cmd_active_timeout -=
9368 9373 mptsas_scsi_watchdog_tick;
9369 9374 if (cmd->cmd_active_timeout <= 0) {
9370 9375 /*
9371 9376 * passthrough command timeout
9372 9377 */
9373 9378 cmd->cmd_flags |= (CFLAG_FINISHED |
9374 9379 CFLAG_TIMEOUT);
9375 9380 cv_broadcast(&mpt->m_passthru_cv);
9376 9381 cv_broadcast(&mpt->m_config_cv);
9377 9382 cv_broadcast(&mpt->m_fw_diag_cv);
9378 9383 }
9379 9384 }
9380 9385 }
9381 9386 }
9382 9387
9383 9388 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
9384 9389 MPTSAS_HASH_FIRST);
9385 9390 while (ptgt != NULL) {
9386 9391 /*
9387 9392 * If we were draining due to a qfull condition,
9388 9393 * go back to full throttle.
9389 9394 */
9390 9395 if ((ptgt->m_t_throttle < MAX_THROTTLE) &&
9391 9396 (ptgt->m_t_throttle > HOLD_THROTTLE) &&
9392 9397 (ptgt->m_t_ncmds < ptgt->m_t_throttle)) {
9393 9398 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
9394 9399 mptsas_restart_hba(mpt);
9395 9400 }
9396 9401
9397 9402 if ((ptgt->m_t_ncmds > 0) &&
9398 9403 (ptgt->m_timebase)) {
9399 9404
9400 9405 if (ptgt->m_timebase <=
9401 9406 mptsas_scsi_watchdog_tick) {
9402 9407 ptgt->m_timebase +=
9403 9408 mptsas_scsi_watchdog_tick;
9404 9409 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9405 9410 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9406 9411 continue;
9407 9412 }
9408 9413
9409 9414 ptgt->m_timeout -= mptsas_scsi_watchdog_tick;
9410 9415
9411 9416 if (ptgt->m_timeout < 0) {
9412 9417 mptsas_cmd_timeout(mpt, ptgt->m_devhdl);
9413 9418 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9414 9419 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9415 9420 continue;
9416 9421 }
9417 9422
9418 9423 if ((ptgt->m_timeout) <=
9419 9424 mptsas_scsi_watchdog_tick) {
9420 9425 NDBG23(("pending timeout"));
9421 9426 mptsas_set_throttle(mpt, ptgt,
9422 9427 DRAIN_THROTTLE);
9423 9428 }
9424 9429 }
9425 9430
9426 9431 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9427 9432 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9428 9433 }
9429 9434 }
9430 9435
9431 9436 /*
9432 9437 * timeout recovery
9433 9438 */
9434 9439 static void
9435 9440 mptsas_cmd_timeout(mptsas_t *mpt, uint16_t devhdl)
9436 9441 {
9437 9442
9438 9443 NDBG29(("mptsas_cmd_timeout: target=%d", devhdl));
9439 9444 mptsas_log(mpt, CE_WARN, "Disconnected command timeout for "
9440 9445 "Target %d", devhdl);
9441 9446
9442 9447 /*
9443 9448 * If the current target is not the target passed in,
9444 9449 * try to reset that target.
9445 9450 */
9446 9451 NDBG29(("mptsas_cmd_timeout: device reset"));
9447 9452 if (mptsas_do_scsi_reset(mpt, devhdl) != TRUE) {
9448 9453 mptsas_log(mpt, CE_WARN, "Target %d reset for command timeout "
9449 9454 "recovery failed!", devhdl);
9450 9455 }
9451 9456 }
9452 9457
9453 9458 /*
9454 9459 * Device / Hotplug control
9455 9460 */
9456 9461 static int
9457 9462 mptsas_scsi_quiesce(dev_info_t *dip)
9458 9463 {
9459 9464 mptsas_t *mpt;
9460 9465 scsi_hba_tran_t *tran;
9461 9466
9462 9467 tran = ddi_get_driver_private(dip);
9463 9468 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL)
9464 9469 return (-1);
9465 9470
9466 9471 return (mptsas_quiesce_bus(mpt));
9467 9472 }
9468 9473
9469 9474 static int
9470 9475 mptsas_scsi_unquiesce(dev_info_t *dip)
9471 9476 {
9472 9477 mptsas_t *mpt;
9473 9478 scsi_hba_tran_t *tran;
9474 9479
9475 9480 tran = ddi_get_driver_private(dip);
9476 9481 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL)
9477 9482 return (-1);
9478 9483
9479 9484 return (mptsas_unquiesce_bus(mpt));
9480 9485 }
9481 9486
9482 9487 static int
9483 9488 mptsas_quiesce_bus(mptsas_t *mpt)
9484 9489 {
9485 9490 mptsas_target_t *ptgt = NULL;
9486 9491
9487 9492 NDBG28(("mptsas_quiesce_bus"));
9488 9493 mutex_enter(&mpt->m_mutex);
9489 9494
9490 9495 /* Set all the throttles to zero */
9491 9496 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
9492 9497 MPTSAS_HASH_FIRST);
9493 9498 while (ptgt != NULL) {
9494 9499 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
9495 9500
9496 9501 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9497 9502 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9498 9503 }
9499 9504
9500 9505 /* If there are any outstanding commands in the queue */
9501 9506 if (mpt->m_ncmds) {
9502 9507 mpt->m_softstate |= MPTSAS_SS_DRAINING;
9503 9508 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain,
9504 9509 mpt, (MPTSAS_QUIESCE_TIMEOUT * drv_usectohz(1000000)));
9505 9510 if (cv_wait_sig(&mpt->m_cv, &mpt->m_mutex) == 0) {
9506 9511 /*
9507 9512 * Quiesce has been interrupted
9508 9513 */
9509 9514 mpt->m_softstate &= ~MPTSAS_SS_DRAINING;
9510 9515 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9511 9516 &mpt->m_active->m_tgttbl, MPTSAS_HASH_FIRST);
9512 9517 while (ptgt != NULL) {
9513 9518 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
9514 9519
9515 9520 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9516 9521 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9517 9522 }
9518 9523 mptsas_restart_hba(mpt);
9519 9524 if (mpt->m_quiesce_timeid != 0) {
9520 9525 timeout_id_t tid = mpt->m_quiesce_timeid;
9521 9526 mpt->m_quiesce_timeid = 0;
9522 9527 mutex_exit(&mpt->m_mutex);
9523 9528 (void) untimeout(tid);
9524 9529 return (-1);
9525 9530 }
9526 9531 mutex_exit(&mpt->m_mutex);
9527 9532 return (-1);
9528 9533 } else {
9529 9534 /* Bus has been quiesced */
9530 9535 ASSERT(mpt->m_quiesce_timeid == 0);
9531 9536 mpt->m_softstate &= ~MPTSAS_SS_DRAINING;
9532 9537 mpt->m_softstate |= MPTSAS_SS_QUIESCED;
9533 9538 mutex_exit(&mpt->m_mutex);
9534 9539 return (0);
9535 9540 }
9536 9541 }
9537 9542 /* Bus was not busy - QUIESCED */
9538 9543 mutex_exit(&mpt->m_mutex);
9539 9544
9540 9545 return (0);
9541 9546 }
9542 9547
9543 9548 static int
9544 9549 mptsas_unquiesce_bus(mptsas_t *mpt)
9545 9550 {
9546 9551 mptsas_target_t *ptgt = NULL;
9547 9552
9548 9553 NDBG28(("mptsas_unquiesce_bus"));
9549 9554 mutex_enter(&mpt->m_mutex);
9550 9555 mpt->m_softstate &= ~MPTSAS_SS_QUIESCED;
9551 9556 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
9552 9557 MPTSAS_HASH_FIRST);
9553 9558 while (ptgt != NULL) {
9554 9559 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
9555 9560
9556 9561 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9557 9562 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9558 9563 }
9559 9564 mptsas_restart_hba(mpt);
9560 9565 mutex_exit(&mpt->m_mutex);
9561 9566 return (0);
9562 9567 }
9563 9568
9564 9569 static void
9565 9570 mptsas_ncmds_checkdrain(void *arg)
9566 9571 {
9567 9572 mptsas_t *mpt = arg;
9568 9573 mptsas_target_t *ptgt = NULL;
9569 9574
9570 9575 mutex_enter(&mpt->m_mutex);
9571 9576 if (mpt->m_softstate & MPTSAS_SS_DRAINING) {
9572 9577 mpt->m_quiesce_timeid = 0;
9573 9578 if (mpt->m_ncmds == 0) {
9574 9579 /* Command queue has been drained */
9575 9580 cv_signal(&mpt->m_cv);
9576 9581 } else {
9577 9582 /*
9578 9583 * The throttle may have been reset because
9579 9584 * of a SCSI bus reset
9580 9585 */
9581 9586 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9582 9587 &mpt->m_active->m_tgttbl, MPTSAS_HASH_FIRST);
9583 9588 while (ptgt != NULL) {
9584 9589 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
9585 9590
9586 9591 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9587 9592 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9588 9593 }
9589 9594
9590 9595 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain,
9591 9596 mpt, (MPTSAS_QUIESCE_TIMEOUT *
9592 9597 drv_usectohz(1000000)));
9593 9598 }
9594 9599 }
9595 9600 mutex_exit(&mpt->m_mutex);
9596 9601 }
9597 9602
9598 9603 /*ARGSUSED*/
9599 9604 static void
9600 9605 mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
9601 9606 {
9602 9607 int i;
9603 9608 uint8_t *cp = (uchar_t *)cmd->cmd_pkt->pkt_cdbp;
9604 9609 char buf[128];
9605 9610
9606 9611 buf[0] = '\0';
9607 9612 NDBG25(("?Cmd (0x%p) dump for Target %d Lun %d:\n", (void *)cmd,
9608 9613 Tgt(cmd), Lun(cmd)));
9609 9614 (void) sprintf(&buf[0], "\tcdb=[");
9610 9615 for (i = 0; i < (int)cmd->cmd_cdblen; i++) {
9611 9616 (void) sprintf(&buf[strlen(buf)], " 0x%x", *cp++);
9612 9617 }
9613 9618 (void) sprintf(&buf[strlen(buf)], " ]");
9614 9619 NDBG25(("?%s\n", buf));
9615 9620 NDBG25(("?pkt_flags=0x%x pkt_statistics=0x%x pkt_state=0x%x\n",
9616 9621 cmd->cmd_pkt->pkt_flags, cmd->cmd_pkt->pkt_statistics,
9617 9622 cmd->cmd_pkt->pkt_state));
9618 9623 NDBG25(("?pkt_scbp=0x%x cmd_flags=0x%x\n", cmd->cmd_pkt->pkt_scbp ?
9619 9624 *(cmd->cmd_pkt->pkt_scbp) : 0, cmd->cmd_flags));
9620 9625 }
9621 9626
9622 9627 static void
9623 9628 mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd)
9624 9629 {
9625 9630 caddr_t memp;
9626 9631 pMPI2RequestHeader_t request_hdrp;
9627 9632 struct scsi_pkt *pkt = cmd->cmd_pkt;
9628 9633 mptsas_pt_request_t *pt = pkt->pkt_ha_private;
9629 9634 uint32_t request_size, data_size, dataout_size;
9630 9635 uint32_t direction;
9631 9636 ddi_dma_cookie_t data_cookie;
9632 9637 ddi_dma_cookie_t dataout_cookie;
9633 9638 uint32_t request_desc_low, request_desc_high = 0;
9634 9639 uint32_t i, sense_bufp;
9635 9640 uint8_t desc_type;
9636 9641 uint8_t *request, function;
9637 9642 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl;
9638 9643 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl;
9639 9644
9640 9645 desc_type = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
9641 9646
9642 9647 request = pt->request;
9643 9648 direction = pt->direction;
9644 9649 request_size = pt->request_size;
9645 9650 data_size = pt->data_size;
9646 9651 dataout_size = pt->dataout_size;
9647 9652 data_cookie = pt->data_cookie;
9648 9653 dataout_cookie = pt->dataout_cookie;
9649 9654
9650 9655 /*
9651 9656 * Store the passthrough message in memory location
9652 9657 * corresponding to our slot number
9653 9658 */
9654 9659 memp = mpt->m_req_frame + (mpt->m_req_frame_size * cmd->cmd_slot);
9655 9660 request_hdrp = (pMPI2RequestHeader_t)memp;
9656 9661 bzero(memp, mpt->m_req_frame_size);
9657 9662
9658 9663 for (i = 0; i < request_size; i++) {
9659 9664 bcopy(request + i, memp + i, 1);
9660 9665 }
9661 9666
9662 9667 if (data_size || dataout_size) {
9663 9668 pMpi2SGESimple64_t sgep;
9664 9669 uint32_t sge_flags;
9665 9670
9666 9671 sgep = (pMpi2SGESimple64_t)((uint8_t *)request_hdrp +
9667 9672 request_size);
9668 9673 if (dataout_size) {
9669 9674
9670 9675 sge_flags = dataout_size |
9671 9676 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
9672 9677 MPI2_SGE_FLAGS_END_OF_BUFFER |
9673 9678 MPI2_SGE_FLAGS_HOST_TO_IOC |
9674 9679 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
9675 9680 MPI2_SGE_FLAGS_SHIFT);
9676 9681 ddi_put32(acc_hdl, &sgep->FlagsLength, sge_flags);
9677 9682 ddi_put32(acc_hdl, &sgep->Address.Low,
9678 9683 (uint32_t)(dataout_cookie.dmac_laddress &
9679 9684 0xffffffffull));
9680 9685 ddi_put32(acc_hdl, &sgep->Address.High,
9681 9686 (uint32_t)(dataout_cookie.dmac_laddress
9682 9687 >> 32));
9683 9688 sgep++;
9684 9689 }
9685 9690 sge_flags = data_size;
9686 9691 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
9687 9692 MPI2_SGE_FLAGS_LAST_ELEMENT |
9688 9693 MPI2_SGE_FLAGS_END_OF_BUFFER |
9689 9694 MPI2_SGE_FLAGS_END_OF_LIST |
9690 9695 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
9691 9696 MPI2_SGE_FLAGS_SHIFT);
9692 9697 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) {
9693 9698 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) <<
9694 9699 MPI2_SGE_FLAGS_SHIFT);
9695 9700 } else {
9696 9701 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) <<
9697 9702 MPI2_SGE_FLAGS_SHIFT);
9698 9703 }
9699 9704 ddi_put32(acc_hdl, &sgep->FlagsLength,
9700 9705 sge_flags);
9701 9706 ddi_put32(acc_hdl, &sgep->Address.Low,
9702 9707 (uint32_t)(data_cookie.dmac_laddress &
9703 9708 0xffffffffull));
9704 9709 ddi_put32(acc_hdl, &sgep->Address.High,
9705 9710 (uint32_t)(data_cookie.dmac_laddress >> 32));
9706 9711 }
9707 9712
9708 9713 function = request_hdrp->Function;
9709 9714 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
9710 9715 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
9711 9716 pMpi2SCSIIORequest_t scsi_io_req;
9712 9717
9713 9718 scsi_io_req = (pMpi2SCSIIORequest_t)request_hdrp;
9714 9719 /*
9715 9720 * Put SGE for data and data_out buffer at the end of
9716 9721 * scsi_io_request message header.(64 bytes in total)
9717 9722 * Following above SGEs, the residual space will be
9718 9723 * used by sense data.
9719 9724 */
9720 9725 ddi_put8(acc_hdl,
9721 9726 &scsi_io_req->SenseBufferLength,
9722 9727 (uint8_t)(request_size - 64));
9723 9728
9724 9729 sense_bufp = mpt->m_req_frame_dma_addr +
9725 9730 (mpt->m_req_frame_size * cmd->cmd_slot);
9726 9731 sense_bufp += 64;
9727 9732 ddi_put32(acc_hdl,
9728 9733 &scsi_io_req->SenseBufferLowAddress, sense_bufp);
9729 9734
9730 9735 /*
9731 9736 * Set SGLOffset0 value
9732 9737 */
9733 9738 ddi_put8(acc_hdl, &scsi_io_req->SGLOffset0,
9734 9739 offsetof(MPI2_SCSI_IO_REQUEST, SGL) / 4);
9735 9740
9736 9741 /*
9737 9742 * Setup descriptor info. RAID passthrough must use the
9738 9743 * default request descriptor which is already set, so if this
9739 9744 * is a SCSI IO request, change the descriptor to SCSI IO.
9740 9745 */
9741 9746 if (function == MPI2_FUNCTION_SCSI_IO_REQUEST) {
9742 9747 desc_type = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
9743 9748 request_desc_high = (ddi_get16(acc_hdl,
9744 9749 &scsi_io_req->DevHandle) << 16);
9745 9750 }
9746 9751 }
9747 9752
9748 9753 /*
9749 9754 * We must wait till the message has been completed before
9750 9755 * beginning the next message so we wait for this one to
9751 9756 * finish.
9752 9757 */
9753 9758 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
9754 9759 request_desc_low = (cmd->cmd_slot << 16) + desc_type;
9755 9760 cmd->cmd_rfm = NULL;
9756 9761 MPTSAS_START_CMD(mpt, request_desc_low, request_desc_high);
9757 9762 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) ||
9758 9763 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) {
9759 9764 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
9760 9765 }
9761 9766 }
9762 9767
9763 9768
9764 9769
9765 9770 static int
9766 9771 mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply,
9767 9772 uint8_t *data, uint32_t request_size, uint32_t reply_size,
9768 9773 uint32_t data_size, uint32_t direction, uint8_t *dataout,
9769 9774 uint32_t dataout_size, short timeout, int mode)
9770 9775 {
9771 9776 mptsas_pt_request_t pt;
9772 9777 mptsas_dma_alloc_state_t data_dma_state;
9773 9778 mptsas_dma_alloc_state_t dataout_dma_state;
9774 9779 caddr_t memp;
9775 9780 mptsas_cmd_t *cmd = NULL;
9776 9781 struct scsi_pkt *pkt;
9777 9782 uint32_t reply_len = 0, sense_len = 0;
9778 9783 pMPI2RequestHeader_t request_hdrp;
9779 9784 pMPI2RequestHeader_t request_msg;
9780 9785 pMPI2DefaultReply_t reply_msg;
9781 9786 Mpi2SCSIIOReply_t rep_msg;
9782 9787 int i, status = 0, pt_flags = 0, rv = 0;
9783 9788 int rvalue;
9784 9789 uint8_t function;
9785 9790
9786 9791 ASSERT(mutex_owned(&mpt->m_mutex));
9787 9792
9788 9793 reply_msg = (pMPI2DefaultReply_t)(&rep_msg);
9789 9794 bzero(reply_msg, sizeof (MPI2_DEFAULT_REPLY));
9790 9795 request_msg = kmem_zalloc(request_size, KM_SLEEP);
9791 9796
9792 9797 mutex_exit(&mpt->m_mutex);
9793 9798 /*
9794 9799 * copy in the request buffer since it could be used by
9795 9800 * another thread when the pt request into waitq
9796 9801 */
9797 9802 if (ddi_copyin(request, request_msg, request_size, mode)) {
9798 9803 mutex_enter(&mpt->m_mutex);
9799 9804 status = EFAULT;
9800 9805 mptsas_log(mpt, CE_WARN, "failed to copy request data");
9801 9806 goto out;
9802 9807 }
9803 9808 mutex_enter(&mpt->m_mutex);
9804 9809
9805 9810 function = request_msg->Function;
9806 9811 if (function == MPI2_FUNCTION_SCSI_TASK_MGMT) {
9807 9812 pMpi2SCSITaskManagementRequest_t task;
9808 9813 task = (pMpi2SCSITaskManagementRequest_t)request_msg;
9809 9814 mptsas_setup_bus_reset_delay(mpt);
9810 9815 rv = mptsas_ioc_task_management(mpt, task->TaskType,
9811 9816 task->DevHandle, (int)task->LUN[1], reply, reply_size,
9812 9817 mode);
9813 9818
9814 9819 if (rv != TRUE) {
9815 9820 status = EIO;
9816 9821 mptsas_log(mpt, CE_WARN, "task management failed");
9817 9822 }
9818 9823 goto out;
9819 9824 }
9820 9825
9821 9826 if (data_size != 0) {
9822 9827 data_dma_state.size = data_size;
9823 9828 if (mptsas_dma_alloc(mpt, &data_dma_state) != DDI_SUCCESS) {
9824 9829 status = ENOMEM;
9825 9830 mptsas_log(mpt, CE_WARN, "failed to alloc DMA "
9826 9831 "resource");
9827 9832 goto out;
9828 9833 }
9829 9834 pt_flags |= MPTSAS_DATA_ALLOCATED;
9830 9835 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) {
9831 9836 mutex_exit(&mpt->m_mutex);
9832 9837 for (i = 0; i < data_size; i++) {
9833 9838 if (ddi_copyin(data + i, (uint8_t *)
9834 9839 data_dma_state.memp + i, 1, mode)) {
9835 9840 mutex_enter(&mpt->m_mutex);
9836 9841 status = EFAULT;
9837 9842 mptsas_log(mpt, CE_WARN, "failed to "
9838 9843 "copy read data");
9839 9844 goto out;
9840 9845 }
9841 9846 }
9842 9847 mutex_enter(&mpt->m_mutex);
9843 9848 }
9844 9849 }
9845 9850
9846 9851 if (dataout_size != 0) {
9847 9852 dataout_dma_state.size = dataout_size;
9848 9853 if (mptsas_dma_alloc(mpt, &dataout_dma_state) != DDI_SUCCESS) {
9849 9854 status = ENOMEM;
9850 9855 mptsas_log(mpt, CE_WARN, "failed to alloc DMA "
9851 9856 "resource");
9852 9857 goto out;
9853 9858 }
9854 9859 pt_flags |= MPTSAS_DATAOUT_ALLOCATED;
9855 9860 mutex_exit(&mpt->m_mutex);
9856 9861 for (i = 0; i < dataout_size; i++) {
9857 9862 if (ddi_copyin(dataout + i, (uint8_t *)
9858 9863 dataout_dma_state.memp + i, 1, mode)) {
9859 9864 mutex_enter(&mpt->m_mutex);
9860 9865 mptsas_log(mpt, CE_WARN, "failed to copy out"
9861 9866 " data");
9862 9867 status = EFAULT;
9863 9868 goto out;
9864 9869 }
9865 9870 }
9866 9871 mutex_enter(&mpt->m_mutex);
9867 9872 }
9868 9873
9869 9874 if ((rvalue = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
9870 9875 status = EAGAIN;
9871 9876 mptsas_log(mpt, CE_NOTE, "event ack command pool is full");
9872 9877 goto out;
9873 9878 }
9874 9879 pt_flags |= MPTSAS_REQUEST_POOL_CMD;
9875 9880
9876 9881 bzero((caddr_t)cmd, sizeof (*cmd));
9877 9882 bzero((caddr_t)pkt, scsi_pkt_size());
9878 9883 bzero((caddr_t)&pt, sizeof (pt));
9879 9884
9880 9885 cmd->ioc_cmd_slot = (uint32_t)(rvalue);
9881 9886
9882 9887 pt.request = (uint8_t *)request_msg;
9883 9888 pt.direction = direction;
9884 9889 pt.request_size = request_size;
9885 9890 pt.data_size = data_size;
9886 9891 pt.dataout_size = dataout_size;
9887 9892 pt.data_cookie = data_dma_state.cookie;
9888 9893 pt.dataout_cookie = dataout_dma_state.cookie;
9889 9894
9890 9895 /*
9891 9896 * Form a blank cmd/pkt to store the acknowledgement message
9892 9897 */
9893 9898 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb[0];
9894 9899 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb;
9895 9900 pkt->pkt_ha_private = (opaque_t)&pt;
9896 9901 pkt->pkt_flags = FLAG_HEAD;
9897 9902 pkt->pkt_time = timeout;
9898 9903 cmd->cmd_pkt = pkt;
9899 9904 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_PASSTHRU;
9900 9905
9901 9906 /*
9902 9907 * Save the command in a slot
9903 9908 */
9904 9909 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
9905 9910 /*
9906 9911 * Once passthru command get slot, set cmd_flags
9907 9912 * CFLAG_PREPARED.
9908 9913 */
9909 9914 cmd->cmd_flags |= CFLAG_PREPARED;
9910 9915 mptsas_start_passthru(mpt, cmd);
9911 9916 } else {
9912 9917 mptsas_waitq_add(mpt, cmd);
9913 9918 }
9914 9919
9915 9920 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
9916 9921 cv_wait(&mpt->m_passthru_cv, &mpt->m_mutex);
9917 9922 }
9918 9923
9919 9924 if (cmd->cmd_flags & CFLAG_PREPARED) {
9920 9925 memp = mpt->m_req_frame + (mpt->m_req_frame_size *
9921 9926 cmd->cmd_slot);
9922 9927 request_hdrp = (pMPI2RequestHeader_t)memp;
9923 9928 }
9924 9929
9925 9930 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
9926 9931 status = ETIMEDOUT;
9927 9932 mptsas_log(mpt, CE_WARN, "passthrough command timeout");
9928 9933 pt_flags |= MPTSAS_CMD_TIMEOUT;
9929 9934 goto out;
9930 9935 }
9931 9936
9932 9937 if (cmd->cmd_rfm) {
9933 9938 /*
9934 9939 * cmd_rfm is zero means the command reply is a CONTEXT
9935 9940 * reply and no PCI Write to post the free reply SMFA
9936 9941 * because no reply message frame is used.
9937 9942 * cmd_rfm is non-zero means the reply is a ADDRESS
9938 9943 * reply and reply message frame is used.
9939 9944 */
9940 9945 pt_flags |= MPTSAS_ADDRESS_REPLY;
9941 9946 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
9942 9947 DDI_DMA_SYNC_FORCPU);
9943 9948 reply_msg = (pMPI2DefaultReply_t)
9944 9949 (mpt->m_reply_frame + (cmd->cmd_rfm -
9945 9950 mpt->m_reply_frame_dma_addr));
9946 9951 }
9947 9952
9948 9953 mptsas_fma_check(mpt, cmd);
9949 9954 if (pkt->pkt_reason == CMD_TRAN_ERR) {
9950 9955 status = EAGAIN;
9951 9956 mptsas_log(mpt, CE_WARN, "passthru fma error");
9952 9957 goto out;
9953 9958 }
9954 9959 if (pkt->pkt_reason == CMD_RESET) {
9955 9960 status = EAGAIN;
9956 9961 mptsas_log(mpt, CE_WARN, "ioc reset abort passthru");
9957 9962 goto out;
9958 9963 }
9959 9964
9960 9965 if (pkt->pkt_reason == CMD_INCOMPLETE) {
9961 9966 status = EIO;
9962 9967 mptsas_log(mpt, CE_WARN, "passthrough command incomplete");
9963 9968 goto out;
9964 9969 }
9965 9970
9966 9971 mutex_exit(&mpt->m_mutex);
9967 9972 if (cmd->cmd_flags & CFLAG_PREPARED) {
9968 9973 function = request_hdrp->Function;
9969 9974 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
9970 9975 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
9971 9976 reply_len = sizeof (MPI2_SCSI_IO_REPLY);
9972 9977 sense_len = reply_size - reply_len;
9973 9978 } else {
9974 9979 reply_len = reply_size;
9975 9980 sense_len = 0;
9976 9981 }
9977 9982
9978 9983 for (i = 0; i < reply_len; i++) {
9979 9984 if (ddi_copyout((uint8_t *)reply_msg + i, reply + i, 1,
9980 9985 mode)) {
9981 9986 mutex_enter(&mpt->m_mutex);
9982 9987 status = EFAULT;
9983 9988 mptsas_log(mpt, CE_WARN, "failed to copy out "
9984 9989 "reply data");
9985 9990 goto out;
9986 9991 }
9987 9992 }
9988 9993 for (i = 0; i < sense_len; i++) {
9989 9994 if (ddi_copyout((uint8_t *)request_hdrp + 64 + i,
9990 9995 reply + reply_len + i, 1, mode)) {
9991 9996 mutex_enter(&mpt->m_mutex);
9992 9997 status = EFAULT;
9993 9998 mptsas_log(mpt, CE_WARN, "failed to copy out "
9994 9999 "sense data");
9995 10000 goto out;
9996 10001 }
9997 10002 }
9998 10003 }
9999 10004
10000 10005 if (data_size) {
10001 10006 if (direction != MPTSAS_PASS_THRU_DIRECTION_WRITE) {
10002 10007 (void) ddi_dma_sync(data_dma_state.handle, 0, 0,
10003 10008 DDI_DMA_SYNC_FORCPU);
10004 10009 for (i = 0; i < data_size; i++) {
10005 10010 if (ddi_copyout((uint8_t *)(
10006 10011 data_dma_state.memp + i), data + i, 1,
10007 10012 mode)) {
10008 10013 mutex_enter(&mpt->m_mutex);
10009 10014 status = EFAULT;
10010 10015 mptsas_log(mpt, CE_WARN, "failed to "
10011 10016 "copy out the reply data");
10012 10017 goto out;
10013 10018 }
10014 10019 }
10015 10020 }
10016 10021 }
10017 10022 mutex_enter(&mpt->m_mutex);
10018 10023 out:
10019 10024 /*
10020 10025 * Put the reply frame back on the free queue, increment the free
10021 10026 * index, and write the new index to the free index register. But only
10022 10027 * if this reply is an ADDRESS reply.
10023 10028 */
10024 10029 if (pt_flags & MPTSAS_ADDRESS_REPLY) {
10025 10030 ddi_put32(mpt->m_acc_free_queue_hdl,
10026 10031 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
10027 10032 cmd->cmd_rfm);
10028 10033 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
10029 10034 DDI_DMA_SYNC_FORDEV);
10030 10035 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
10031 10036 mpt->m_free_index = 0;
10032 10037 }
10033 10038 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
10034 10039 mpt->m_free_index);
10035 10040 }
10036 10041 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
10037 10042 mptsas_remove_cmd(mpt, cmd);
10038 10043 pt_flags &= (~MPTSAS_REQUEST_POOL_CMD);
10039 10044 }
10040 10045 if (pt_flags & MPTSAS_REQUEST_POOL_CMD)
10041 10046 mptsas_return_to_pool(mpt, cmd);
10042 10047 if (pt_flags & MPTSAS_DATA_ALLOCATED) {
10043 10048 if (mptsas_check_dma_handle(data_dma_state.handle) !=
10044 10049 DDI_SUCCESS) {
10045 10050 ddi_fm_service_impact(mpt->m_dip,
10046 10051 DDI_SERVICE_UNAFFECTED);
10047 10052 status = EFAULT;
10048 10053 }
10049 10054 mptsas_dma_free(&data_dma_state);
10050 10055 }
10051 10056 if (pt_flags & MPTSAS_DATAOUT_ALLOCATED) {
10052 10057 if (mptsas_check_dma_handle(dataout_dma_state.handle) !=
10053 10058 DDI_SUCCESS) {
10054 10059 ddi_fm_service_impact(mpt->m_dip,
10055 10060 DDI_SERVICE_UNAFFECTED);
10056 10061 status = EFAULT;
10057 10062 }
10058 10063 mptsas_dma_free(&dataout_dma_state);
10059 10064 }
10060 10065 if (pt_flags & MPTSAS_CMD_TIMEOUT) {
10061 10066 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
10062 10067 mptsas_log(mpt, CE_WARN, "mptsas_restart_ioc failed");
10063 10068 }
10064 10069 }
10065 10070 if (request_msg)
10066 10071 kmem_free(request_msg, request_size);
10067 10072
10068 10073 return (status);
10069 10074 }
10070 10075
10071 10076 static int
10072 10077 mptsas_pass_thru(mptsas_t *mpt, mptsas_pass_thru_t *data, int mode)
10073 10078 {
10074 10079 /*
10075 10080 * If timeout is 0, set timeout to default of 60 seconds.
10076 10081 */
10077 10082 if (data->Timeout == 0) {
10078 10083 data->Timeout = MPTSAS_PASS_THRU_TIME_DEFAULT;
10079 10084 }
10080 10085
10081 10086 if (((data->DataSize == 0) &&
10082 10087 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_NONE)) ||
10083 10088 ((data->DataSize != 0) &&
10084 10089 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_READ) ||
10085 10090 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_WRITE) ||
10086 10091 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) &&
10087 10092 (data->DataOutSize != 0))))) {
10088 10093 if (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) {
10089 10094 data->DataDirection = MPTSAS_PASS_THRU_DIRECTION_READ;
10090 10095 } else {
10091 10096 data->DataOutSize = 0;
10092 10097 }
10093 10098 /*
10094 10099 * Send passthru request messages
10095 10100 */
10096 10101 return (mptsas_do_passthru(mpt,
10097 10102 (uint8_t *)((uintptr_t)data->PtrRequest),
10098 10103 (uint8_t *)((uintptr_t)data->PtrReply),
10099 10104 (uint8_t *)((uintptr_t)data->PtrData),
10100 10105 data->RequestSize, data->ReplySize,
10101 10106 data->DataSize, data->DataDirection,
10102 10107 (uint8_t *)((uintptr_t)data->PtrDataOut),
10103 10108 data->DataOutSize, data->Timeout, mode));
10104 10109 } else {
10105 10110 return (EINVAL);
10106 10111 }
10107 10112 }
10108 10113
10109 10114 static uint8_t
10110 10115 mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, uint32_t unique_id)
10111 10116 {
10112 10117 uint8_t index;
10113 10118
10114 10119 for (index = 0; index < MPI2_DIAG_BUF_TYPE_COUNT; index++) {
10115 10120 if (mpt->m_fw_diag_buffer_list[index].unique_id == unique_id) {
10116 10121 return (index);
10117 10122 }
10118 10123 }
10119 10124
10120 10125 return (MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND);
10121 10126 }
10122 10127
10123 10128 static void
10124 10129 mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd)
10125 10130 {
10126 10131 pMpi2DiagBufferPostRequest_t pDiag_post_msg;
10127 10132 pMpi2DiagReleaseRequest_t pDiag_release_msg;
10128 10133 struct scsi_pkt *pkt = cmd->cmd_pkt;
10129 10134 mptsas_diag_request_t *diag = pkt->pkt_ha_private;
10130 10135 uint32_t request_desc_low, i;
10131 10136
10132 10137 ASSERT(mutex_owned(&mpt->m_mutex));
10133 10138
10134 10139 /*
10135 10140 * Form the diag message depending on the post or release function.
10136 10141 */
10137 10142 if (diag->function == MPI2_FUNCTION_DIAG_BUFFER_POST) {
10138 10143 pDiag_post_msg = (pMpi2DiagBufferPostRequest_t)
10139 10144 (mpt->m_req_frame + (mpt->m_req_frame_size *
10140 10145 cmd->cmd_slot));
10141 10146 bzero(pDiag_post_msg, mpt->m_req_frame_size);
10142 10147 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->Function,
10143 10148 diag->function);
10144 10149 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->BufferType,
10145 10150 diag->pBuffer->buffer_type);
10146 10151 ddi_put8(mpt->m_acc_req_frame_hdl,
10147 10152 &pDiag_post_msg->ExtendedType,
10148 10153 diag->pBuffer->extended_type);
10149 10154 ddi_put32(mpt->m_acc_req_frame_hdl,
10150 10155 &pDiag_post_msg->BufferLength,
10151 10156 diag->pBuffer->buffer_data.size);
10152 10157 for (i = 0; i < (sizeof (pDiag_post_msg->ProductSpecific) / 4);
10153 10158 i++) {
10154 10159 ddi_put32(mpt->m_acc_req_frame_hdl,
10155 10160 &pDiag_post_msg->ProductSpecific[i],
10156 10161 diag->pBuffer->product_specific[i]);
10157 10162 }
10158 10163 ddi_put32(mpt->m_acc_req_frame_hdl,
10159 10164 &pDiag_post_msg->BufferAddress.Low,
10160 10165 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress
10161 10166 & 0xffffffffull));
10162 10167 ddi_put32(mpt->m_acc_req_frame_hdl,
10163 10168 &pDiag_post_msg->BufferAddress.High,
10164 10169 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress
10165 10170 >> 32));
10166 10171 } else {
10167 10172 pDiag_release_msg = (pMpi2DiagReleaseRequest_t)
10168 10173 (mpt->m_req_frame + (mpt->m_req_frame_size *
10169 10174 cmd->cmd_slot));
10170 10175 bzero(pDiag_release_msg, mpt->m_req_frame_size);
10171 10176 ddi_put8(mpt->m_acc_req_frame_hdl,
10172 10177 &pDiag_release_msg->Function, diag->function);
10173 10178 ddi_put8(mpt->m_acc_req_frame_hdl,
10174 10179 &pDiag_release_msg->BufferType,
10175 10180 diag->pBuffer->buffer_type);
10176 10181 }
10177 10182
10178 10183 /*
10179 10184 * Send the message
10180 10185 */
10181 10186 (void) ddi_dma_sync(mpt->m_dma_req_frame_hdl, 0, 0,
10182 10187 DDI_DMA_SYNC_FORDEV);
10183 10188 request_desc_low = (cmd->cmd_slot << 16) +
10184 10189 MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
10185 10190 cmd->cmd_rfm = NULL;
10186 10191 MPTSAS_START_CMD(mpt, request_desc_low, 0);
10187 10192 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
10188 10193 DDI_SUCCESS) ||
10189 10194 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
10190 10195 DDI_SUCCESS)) {
10191 10196 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
10192 10197 }
10193 10198 }
10194 10199
10195 10200 static int
10196 10201 mptsas_post_fw_diag_buffer(mptsas_t *mpt,
10197 10202 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code)
10198 10203 {
10199 10204 mptsas_diag_request_t diag;
10200 10205 int status, slot_num, post_flags = 0;
10201 10206 mptsas_cmd_t *cmd = NULL;
10202 10207 struct scsi_pkt *pkt;
10203 10208 pMpi2DiagBufferPostReply_t reply;
10204 10209 uint16_t iocstatus;
10205 10210 uint32_t iocloginfo, transfer_length;
10206 10211
10207 10212 /*
10208 10213 * If buffer is not enabled, just leave.
10209 10214 */
10210 10215 *return_code = MPTSAS_FW_DIAG_ERROR_POST_FAILED;
10211 10216 if (!pBuffer->enabled) {
10212 10217 status = DDI_FAILURE;
10213 10218 goto out;
10214 10219 }
10215 10220
10216 10221 /*
10217 10222 * Clear some flags initially.
10218 10223 */
10219 10224 pBuffer->force_release = FALSE;
10220 10225 pBuffer->valid_data = FALSE;
10221 10226 pBuffer->owned_by_firmware = FALSE;
10222 10227
10223 10228 /*
10224 10229 * Get a cmd buffer from the cmd buffer pool
10225 10230 */
10226 10231 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
10227 10232 status = DDI_FAILURE;
10228 10233 mptsas_log(mpt, CE_NOTE, "command pool is full: Post FW Diag");
10229 10234 goto out;
10230 10235 }
10231 10236 post_flags |= MPTSAS_REQUEST_POOL_CMD;
10232 10237
10233 10238 bzero((caddr_t)cmd, sizeof (*cmd));
10234 10239 bzero((caddr_t)pkt, scsi_pkt_size());
10235 10240
10236 10241 cmd->ioc_cmd_slot = (uint32_t)(slot_num);
10237 10242
10238 10243 diag.pBuffer = pBuffer;
10239 10244 diag.function = MPI2_FUNCTION_DIAG_BUFFER_POST;
10240 10245
10241 10246 /*
10242 10247 * Form a blank cmd/pkt to store the acknowledgement message
10243 10248 */
10244 10249 pkt->pkt_ha_private = (opaque_t)&diag;
10245 10250 pkt->pkt_flags = FLAG_HEAD;
10246 10251 pkt->pkt_time = 60;
10247 10252 cmd->cmd_pkt = pkt;
10248 10253 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG;
10249 10254
10250 10255 /*
10251 10256 * Save the command in a slot
10252 10257 */
10253 10258 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
10254 10259 /*
10255 10260 * Once passthru command get slot, set cmd_flags
10256 10261 * CFLAG_PREPARED.
10257 10262 */
10258 10263 cmd->cmd_flags |= CFLAG_PREPARED;
10259 10264 mptsas_start_diag(mpt, cmd);
10260 10265 } else {
10261 10266 mptsas_waitq_add(mpt, cmd);
10262 10267 }
10263 10268
10264 10269 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
10265 10270 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex);
10266 10271 }
10267 10272
10268 10273 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
10269 10274 status = DDI_FAILURE;
10270 10275 mptsas_log(mpt, CE_WARN, "Post FW Diag command timeout");
10271 10276 goto out;
10272 10277 }
10273 10278
10274 10279 /*
10275 10280 * cmd_rfm points to the reply message if a reply was given. Check the
10276 10281 * IOCStatus to make sure everything went OK with the FW diag request
10277 10282 * and set buffer flags.
10278 10283 */
10279 10284 if (cmd->cmd_rfm) {
10280 10285 post_flags |= MPTSAS_ADDRESS_REPLY;
10281 10286 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
10282 10287 DDI_DMA_SYNC_FORCPU);
10283 10288 reply = (pMpi2DiagBufferPostReply_t)(mpt->m_reply_frame +
10284 10289 (cmd->cmd_rfm - mpt->m_reply_frame_dma_addr));
10285 10290
10286 10291 /*
10287 10292 * Get the reply message data
10288 10293 */
10289 10294 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
10290 10295 &reply->IOCStatus);
10291 10296 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
10292 10297 &reply->IOCLogInfo);
10293 10298 transfer_length = ddi_get32(mpt->m_acc_reply_frame_hdl,
10294 10299 &reply->TransferLength);
10295 10300
10296 10301 /*
10297 10302 * If post failed quit.
10298 10303 */
10299 10304 if (iocstatus != MPI2_IOCSTATUS_SUCCESS) {
10300 10305 status = DDI_FAILURE;
10301 10306 NDBG13(("post FW Diag Buffer failed: IOCStatus=0x%x, "
10302 10307 "IOCLogInfo=0x%x, TransferLength=0x%x", iocstatus,
10303 10308 iocloginfo, transfer_length));
10304 10309 goto out;
10305 10310 }
10306 10311
10307 10312 /*
10308 10313 * Post was successful.
10309 10314 */
10310 10315 pBuffer->valid_data = TRUE;
10311 10316 pBuffer->owned_by_firmware = TRUE;
10312 10317 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
10313 10318 status = DDI_SUCCESS;
10314 10319 }
10315 10320
10316 10321 out:
10317 10322 /*
10318 10323 * Put the reply frame back on the free queue, increment the free
10319 10324 * index, and write the new index to the free index register. But only
10320 10325 * if this reply is an ADDRESS reply.
10321 10326 */
10322 10327 if (post_flags & MPTSAS_ADDRESS_REPLY) {
10323 10328 ddi_put32(mpt->m_acc_free_queue_hdl,
10324 10329 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
10325 10330 cmd->cmd_rfm);
10326 10331 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
10327 10332 DDI_DMA_SYNC_FORDEV);
10328 10333 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
10329 10334 mpt->m_free_index = 0;
10330 10335 }
10331 10336 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
10332 10337 mpt->m_free_index);
10333 10338 }
10334 10339 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
10335 10340 mptsas_remove_cmd(mpt, cmd);
10336 10341 post_flags &= (~MPTSAS_REQUEST_POOL_CMD);
10337 10342 }
10338 10343 if (post_flags & MPTSAS_REQUEST_POOL_CMD) {
10339 10344 mptsas_return_to_pool(mpt, cmd);
10340 10345 }
10341 10346
10342 10347 return (status);
10343 10348 }
10344 10349
10345 10350 static int
10346 10351 mptsas_release_fw_diag_buffer(mptsas_t *mpt,
10347 10352 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code,
10348 10353 uint32_t diag_type)
10349 10354 {
10350 10355 mptsas_diag_request_t diag;
10351 10356 int status, slot_num, rel_flags = 0;
10352 10357 mptsas_cmd_t *cmd = NULL;
10353 10358 struct scsi_pkt *pkt;
10354 10359 pMpi2DiagReleaseReply_t reply;
10355 10360 uint16_t iocstatus;
10356 10361 uint32_t iocloginfo;
10357 10362
10358 10363 /*
10359 10364 * If buffer is not enabled, just leave.
10360 10365 */
10361 10366 *return_code = MPTSAS_FW_DIAG_ERROR_RELEASE_FAILED;
10362 10367 if (!pBuffer->enabled) {
10363 10368 mptsas_log(mpt, CE_NOTE, "This buffer type is not supported "
10364 10369 "by the IOC");
10365 10370 status = DDI_FAILURE;
10366 10371 goto out;
10367 10372 }
10368 10373
10369 10374 /*
10370 10375 * Clear some flags initially.
10371 10376 */
10372 10377 pBuffer->force_release = FALSE;
10373 10378 pBuffer->valid_data = FALSE;
10374 10379 pBuffer->owned_by_firmware = FALSE;
10375 10380
10376 10381 /*
10377 10382 * Get a cmd buffer from the cmd buffer pool
10378 10383 */
10379 10384 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
10380 10385 status = DDI_FAILURE;
10381 10386 mptsas_log(mpt, CE_NOTE, "command pool is full: Release FW "
10382 10387 "Diag");
10383 10388 goto out;
10384 10389 }
10385 10390 rel_flags |= MPTSAS_REQUEST_POOL_CMD;
10386 10391
10387 10392 bzero((caddr_t)cmd, sizeof (*cmd));
10388 10393 bzero((caddr_t)pkt, scsi_pkt_size());
10389 10394
10390 10395 cmd->ioc_cmd_slot = (uint32_t)(slot_num);
10391 10396
10392 10397 diag.pBuffer = pBuffer;
10393 10398 diag.function = MPI2_FUNCTION_DIAG_RELEASE;
10394 10399
10395 10400 /*
10396 10401 * Form a blank cmd/pkt to store the acknowledgement message
10397 10402 */
10398 10403 pkt->pkt_ha_private = (opaque_t)&diag;
10399 10404 pkt->pkt_flags = FLAG_HEAD;
10400 10405 pkt->pkt_time = 60;
10401 10406 cmd->cmd_pkt = pkt;
10402 10407 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG;
10403 10408
10404 10409 /*
10405 10410 * Save the command in a slot
10406 10411 */
10407 10412 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
10408 10413 /*
10409 10414 * Once passthru command get slot, set cmd_flags
10410 10415 * CFLAG_PREPARED.
10411 10416 */
10412 10417 cmd->cmd_flags |= CFLAG_PREPARED;
10413 10418 mptsas_start_diag(mpt, cmd);
10414 10419 } else {
10415 10420 mptsas_waitq_add(mpt, cmd);
10416 10421 }
10417 10422
10418 10423 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
10419 10424 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex);
10420 10425 }
10421 10426
10422 10427 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
10423 10428 status = DDI_FAILURE;
10424 10429 mptsas_log(mpt, CE_WARN, "Release FW Diag command timeout");
10425 10430 goto out;
10426 10431 }
10427 10432
10428 10433 /*
10429 10434 * cmd_rfm points to the reply message if a reply was given. Check the
10430 10435 * IOCStatus to make sure everything went OK with the FW diag request
10431 10436 * and set buffer flags.
10432 10437 */
10433 10438 if (cmd->cmd_rfm) {
10434 10439 rel_flags |= MPTSAS_ADDRESS_REPLY;
10435 10440 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
10436 10441 DDI_DMA_SYNC_FORCPU);
10437 10442 reply = (pMpi2DiagReleaseReply_t)(mpt->m_reply_frame +
10438 10443 (cmd->cmd_rfm - mpt->m_reply_frame_dma_addr));
10439 10444
10440 10445 /*
10441 10446 * Get the reply message data
10442 10447 */
10443 10448 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
10444 10449 &reply->IOCStatus);
10445 10450 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
10446 10451 &reply->IOCLogInfo);
10447 10452
10448 10453 /*
10449 10454 * If release failed quit.
10450 10455 */
10451 10456 if ((iocstatus != MPI2_IOCSTATUS_SUCCESS) ||
10452 10457 pBuffer->owned_by_firmware) {
10453 10458 status = DDI_FAILURE;
10454 10459 NDBG13(("release FW Diag Buffer failed: "
10455 10460 "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus,
10456 10461 iocloginfo));
10457 10462 goto out;
10458 10463 }
10459 10464
10460 10465 /*
10461 10466 * Release was successful.
10462 10467 */
10463 10468 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
10464 10469 status = DDI_SUCCESS;
10465 10470
10466 10471 /*
10467 10472 * If this was for an UNREGISTER diag type command, clear the
10468 10473 * unique ID.
10469 10474 */
10470 10475 if (diag_type == MPTSAS_FW_DIAG_TYPE_UNREGISTER) {
10471 10476 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID;
10472 10477 }
10473 10478 }
10474 10479
10475 10480 out:
10476 10481 /*
10477 10482 * Put the reply frame back on the free queue, increment the free
10478 10483 * index, and write the new index to the free index register. But only
10479 10484 * if this reply is an ADDRESS reply.
10480 10485 */
10481 10486 if (rel_flags & MPTSAS_ADDRESS_REPLY) {
10482 10487 ddi_put32(mpt->m_acc_free_queue_hdl,
10483 10488 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
10484 10489 cmd->cmd_rfm);
10485 10490 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
10486 10491 DDI_DMA_SYNC_FORDEV);
10487 10492 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
10488 10493 mpt->m_free_index = 0;
10489 10494 }
10490 10495 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
10491 10496 mpt->m_free_index);
10492 10497 }
10493 10498 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
10494 10499 mptsas_remove_cmd(mpt, cmd);
10495 10500 rel_flags &= (~MPTSAS_REQUEST_POOL_CMD);
10496 10501 }
10497 10502 if (rel_flags & MPTSAS_REQUEST_POOL_CMD) {
10498 10503 mptsas_return_to_pool(mpt, cmd);
10499 10504 }
10500 10505
10501 10506 return (status);
10502 10507 }
10503 10508
10504 10509 static int
10505 10510 mptsas_diag_register(mptsas_t *mpt, mptsas_fw_diag_register_t *diag_register,
10506 10511 uint32_t *return_code)
10507 10512 {
10508 10513 mptsas_fw_diagnostic_buffer_t *pBuffer;
10509 10514 uint8_t extended_type, buffer_type, i;
10510 10515 uint32_t buffer_size;
10511 10516 uint32_t unique_id;
10512 10517 int status;
10513 10518
10514 10519 ASSERT(mutex_owned(&mpt->m_mutex));
10515 10520
10516 10521 extended_type = diag_register->ExtendedType;
10517 10522 buffer_type = diag_register->BufferType;
10518 10523 buffer_size = diag_register->RequestedBufferSize;
10519 10524 unique_id = diag_register->UniqueId;
10520 10525
10521 10526 /*
10522 10527 * Check for valid buffer type
10523 10528 */
10524 10529 if (buffer_type >= MPI2_DIAG_BUF_TYPE_COUNT) {
10525 10530 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10526 10531 return (DDI_FAILURE);
10527 10532 }
10528 10533
10529 10534 /*
10530 10535 * Get the current buffer and look up the unique ID. The unique ID
10531 10536 * should not be found. If it is, the ID is already in use.
10532 10537 */
10533 10538 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
10534 10539 pBuffer = &mpt->m_fw_diag_buffer_list[buffer_type];
10535 10540 if (i != MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
10536 10541 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10537 10542 return (DDI_FAILURE);
10538 10543 }
10539 10544
10540 10545 /*
10541 10546 * The buffer's unique ID should not be registered yet, and the given
10542 10547 * unique ID cannot be 0.
10543 10548 */
10544 10549 if ((pBuffer->unique_id != MPTSAS_FW_DIAG_INVALID_UID) ||
10545 10550 (unique_id == MPTSAS_FW_DIAG_INVALID_UID)) {
10546 10551 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10547 10552 return (DDI_FAILURE);
10548 10553 }
10549 10554
10550 10555 /*
10551 10556 * If this buffer is already posted as immediate, just change owner.
10552 10557 */
10553 10558 if (pBuffer->immediate && pBuffer->owned_by_firmware &&
10554 10559 (pBuffer->unique_id == MPTSAS_FW_DIAG_INVALID_UID)) {
10555 10560 pBuffer->immediate = FALSE;
10556 10561 pBuffer->unique_id = unique_id;
10557 10562 return (DDI_SUCCESS);
10558 10563 }
10559 10564
10560 10565 /*
10561 10566 * Post a new buffer after checking if it's enabled. The DMA buffer
10562 10567 * that is allocated will be contiguous (sgl_len = 1).
10563 10568 */
10564 10569 if (!pBuffer->enabled) {
10565 10570 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER;
10566 10571 return (DDI_FAILURE);
10567 10572 }
10568 10573 bzero(&pBuffer->buffer_data, sizeof (mptsas_dma_alloc_state_t));
10569 10574 pBuffer->buffer_data.size = buffer_size;
10570 10575 if (mptsas_dma_alloc(mpt, &pBuffer->buffer_data) != DDI_SUCCESS) {
10571 10576 mptsas_log(mpt, CE_WARN, "failed to alloc DMA resource for "
10572 10577 "diag buffer: size = %d bytes", buffer_size);
10573 10578 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER;
10574 10579 return (DDI_FAILURE);
10575 10580 }
10576 10581
10577 10582 /*
10578 10583 * Copy the given info to the diag buffer and post the buffer.
10579 10584 */
10580 10585 pBuffer->buffer_type = buffer_type;
10581 10586 pBuffer->immediate = FALSE;
10582 10587 if (buffer_type == MPI2_DIAG_BUF_TYPE_TRACE) {
10583 10588 for (i = 0; i < (sizeof (pBuffer->product_specific) / 4);
10584 10589 i++) {
10585 10590 pBuffer->product_specific[i] =
10586 10591 diag_register->ProductSpecific[i];
10587 10592 }
10588 10593 }
10589 10594 pBuffer->extended_type = extended_type;
10590 10595 pBuffer->unique_id = unique_id;
10591 10596 status = mptsas_post_fw_diag_buffer(mpt, pBuffer, return_code);
10592 10597
10593 10598 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) !=
10594 10599 DDI_SUCCESS) {
10595 10600 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed in "
10596 10601 "mptsas_diag_register.");
10597 10602 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
10598 10603 status = DDI_FAILURE;
10599 10604 }
10600 10605
10601 10606 /*
10602 10607 * In case there was a failure, free the DMA buffer.
10603 10608 */
10604 10609 if (status == DDI_FAILURE) {
10605 10610 mptsas_dma_free(&pBuffer->buffer_data);
10606 10611 }
10607 10612
10608 10613 return (status);
10609 10614 }
10610 10615
10611 10616 static int
10612 10617 mptsas_diag_unregister(mptsas_t *mpt,
10613 10618 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code)
10614 10619 {
10615 10620 mptsas_fw_diagnostic_buffer_t *pBuffer;
10616 10621 uint8_t i;
10617 10622 uint32_t unique_id;
10618 10623 int status;
10619 10624
10620 10625 ASSERT(mutex_owned(&mpt->m_mutex));
10621 10626
10622 10627 unique_id = diag_unregister->UniqueId;
10623 10628
10624 10629 /*
10625 10630 * Get the current buffer and look up the unique ID. The unique ID
10626 10631 * should be there.
10627 10632 */
10628 10633 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
10629 10634 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
10630 10635 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10631 10636 return (DDI_FAILURE);
10632 10637 }
10633 10638
10634 10639 pBuffer = &mpt->m_fw_diag_buffer_list[i];
10635 10640
10636 10641 /*
10637 10642 * Try to release the buffer from FW before freeing it. If release
10638 10643 * fails, don't free the DMA buffer in case FW tries to access it
10639 10644 * later. If buffer is not owned by firmware, can't release it.
10640 10645 */
10641 10646 if (!pBuffer->owned_by_firmware) {
10642 10647 status = DDI_SUCCESS;
10643 10648 } else {
10644 10649 status = mptsas_release_fw_diag_buffer(mpt, pBuffer,
10645 10650 return_code, MPTSAS_FW_DIAG_TYPE_UNREGISTER);
10646 10651 }
10647 10652
10648 10653 /*
10649 10654 * At this point, return the current status no matter what happens with
10650 10655 * the DMA buffer.
10651 10656 */
10652 10657 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID;
10653 10658 if (status == DDI_SUCCESS) {
10654 10659 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) !=
10655 10660 DDI_SUCCESS) {
10656 10661 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed "
10657 10662 "in mptsas_diag_unregister.");
10658 10663 ddi_fm_service_impact(mpt->m_dip,
10659 10664 DDI_SERVICE_UNAFFECTED);
10660 10665 }
10661 10666 mptsas_dma_free(&pBuffer->buffer_data);
10662 10667 }
10663 10668
10664 10669 return (status);
10665 10670 }
10666 10671
10667 10672 static int
10668 10673 mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query,
10669 10674 uint32_t *return_code)
10670 10675 {
10671 10676 mptsas_fw_diagnostic_buffer_t *pBuffer;
10672 10677 uint8_t i;
10673 10678 uint32_t unique_id;
10674 10679
10675 10680 ASSERT(mutex_owned(&mpt->m_mutex));
10676 10681
10677 10682 unique_id = diag_query->UniqueId;
10678 10683
10679 10684 /*
10680 10685 * If ID is valid, query on ID.
10681 10686 * If ID is invalid, query on buffer type.
10682 10687 */
10683 10688 if (unique_id == MPTSAS_FW_DIAG_INVALID_UID) {
10684 10689 i = diag_query->BufferType;
10685 10690 if (i >= MPI2_DIAG_BUF_TYPE_COUNT) {
10686 10691 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10687 10692 return (DDI_FAILURE);
10688 10693 }
10689 10694 } else {
10690 10695 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
10691 10696 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
10692 10697 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10693 10698 return (DDI_FAILURE);
10694 10699 }
10695 10700 }
10696 10701
10697 10702 /*
10698 10703 * Fill query structure with the diag buffer info.
10699 10704 */
10700 10705 pBuffer = &mpt->m_fw_diag_buffer_list[i];
10701 10706 diag_query->BufferType = pBuffer->buffer_type;
10702 10707 diag_query->ExtendedType = pBuffer->extended_type;
10703 10708 if (diag_query->BufferType == MPI2_DIAG_BUF_TYPE_TRACE) {
10704 10709 for (i = 0; i < (sizeof (diag_query->ProductSpecific) / 4);
10705 10710 i++) {
10706 10711 diag_query->ProductSpecific[i] =
10707 10712 pBuffer->product_specific[i];
10708 10713 }
10709 10714 }
10710 10715 diag_query->TotalBufferSize = pBuffer->buffer_data.size;
10711 10716 diag_query->DriverAddedBufferSize = 0;
10712 10717 diag_query->UniqueId = pBuffer->unique_id;
10713 10718 diag_query->ApplicationFlags = 0;
10714 10719 diag_query->DiagnosticFlags = 0;
10715 10720
10716 10721 /*
10717 10722 * Set/Clear application flags
10718 10723 */
10719 10724 if (pBuffer->immediate) {
10720 10725 diag_query->ApplicationFlags &= ~MPTSAS_FW_DIAG_FLAG_APP_OWNED;
10721 10726 } else {
10722 10727 diag_query->ApplicationFlags |= MPTSAS_FW_DIAG_FLAG_APP_OWNED;
10723 10728 }
10724 10729 if (pBuffer->valid_data || pBuffer->owned_by_firmware) {
10725 10730 diag_query->ApplicationFlags |=
10726 10731 MPTSAS_FW_DIAG_FLAG_BUFFER_VALID;
10727 10732 } else {
10728 10733 diag_query->ApplicationFlags &=
10729 10734 ~MPTSAS_FW_DIAG_FLAG_BUFFER_VALID;
10730 10735 }
10731 10736 if (pBuffer->owned_by_firmware) {
10732 10737 diag_query->ApplicationFlags |=
10733 10738 MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS;
10734 10739 } else {
10735 10740 diag_query->ApplicationFlags &=
10736 10741 ~MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS;
10737 10742 }
10738 10743
10739 10744 return (DDI_SUCCESS);
10740 10745 }
10741 10746
10742 10747 static int
10743 10748 mptsas_diag_read_buffer(mptsas_t *mpt,
10744 10749 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf,
10745 10750 uint32_t *return_code, int ioctl_mode)
10746 10751 {
10747 10752 mptsas_fw_diagnostic_buffer_t *pBuffer;
10748 10753 uint8_t i, *pData;
10749 10754 uint32_t unique_id, byte;
10750 10755 int status;
10751 10756
10752 10757 ASSERT(mutex_owned(&mpt->m_mutex));
10753 10758
10754 10759 unique_id = diag_read_buffer->UniqueId;
10755 10760
10756 10761 /*
10757 10762 * Get the current buffer and look up the unique ID. The unique ID
10758 10763 * should be there.
10759 10764 */
10760 10765 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
10761 10766 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
10762 10767 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10763 10768 return (DDI_FAILURE);
10764 10769 }
10765 10770
10766 10771 pBuffer = &mpt->m_fw_diag_buffer_list[i];
10767 10772
10768 10773 /*
10769 10774 * Make sure requested read is within limits
10770 10775 */
10771 10776 if (diag_read_buffer->StartingOffset + diag_read_buffer->BytesToRead >
10772 10777 pBuffer->buffer_data.size) {
10773 10778 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10774 10779 return (DDI_FAILURE);
10775 10780 }
10776 10781
10777 10782 /*
10778 10783 * Copy the requested data from DMA to the diag_read_buffer. The DMA
10779 10784 * buffer that was allocated is one contiguous buffer.
10780 10785 */
10781 10786 pData = (uint8_t *)(pBuffer->buffer_data.memp +
10782 10787 diag_read_buffer->StartingOffset);
10783 10788 (void) ddi_dma_sync(pBuffer->buffer_data.handle, 0, 0,
10784 10789 DDI_DMA_SYNC_FORCPU);
10785 10790 for (byte = 0; byte < diag_read_buffer->BytesToRead; byte++) {
10786 10791 if (ddi_copyout(pData + byte, ioctl_buf + byte, 1, ioctl_mode)
10787 10792 != 0) {
10788 10793 return (DDI_FAILURE);
10789 10794 }
10790 10795 }
10791 10796 diag_read_buffer->Status = 0;
10792 10797
10793 10798 /*
10794 10799 * Set or clear the Force Release flag.
10795 10800 */
10796 10801 if (pBuffer->force_release) {
10797 10802 diag_read_buffer->Flags |= MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE;
10798 10803 } else {
10799 10804 diag_read_buffer->Flags &= ~MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE;
10800 10805 }
10801 10806
10802 10807 /*
10803 10808 * If buffer is to be reregistered, make sure it's not already owned by
10804 10809 * firmware first.
10805 10810 */
10806 10811 status = DDI_SUCCESS;
10807 10812 if (!pBuffer->owned_by_firmware) {
10808 10813 if (diag_read_buffer->Flags & MPTSAS_FW_DIAG_FLAG_REREGISTER) {
10809 10814 status = mptsas_post_fw_diag_buffer(mpt, pBuffer,
10810 10815 return_code);
10811 10816 }
10812 10817 }
10813 10818
10814 10819 return (status);
10815 10820 }
10816 10821
10817 10822 static int
10818 10823 mptsas_diag_release(mptsas_t *mpt, mptsas_fw_diag_release_t *diag_release,
10819 10824 uint32_t *return_code)
10820 10825 {
10821 10826 mptsas_fw_diagnostic_buffer_t *pBuffer;
10822 10827 uint8_t i;
10823 10828 uint32_t unique_id;
10824 10829 int status;
10825 10830
10826 10831 ASSERT(mutex_owned(&mpt->m_mutex));
10827 10832
10828 10833 unique_id = diag_release->UniqueId;
10829 10834
10830 10835 /*
10831 10836 * Get the current buffer and look up the unique ID. The unique ID
10832 10837 * should be there.
10833 10838 */
10834 10839 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
10835 10840 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
10836 10841 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10837 10842 return (DDI_FAILURE);
10838 10843 }
10839 10844
10840 10845 pBuffer = &mpt->m_fw_diag_buffer_list[i];
10841 10846
10842 10847 /*
10843 10848 * If buffer is not owned by firmware, it's already been released.
10844 10849 */
10845 10850 if (!pBuffer->owned_by_firmware) {
10846 10851 *return_code = MPTSAS_FW_DIAG_ERROR_ALREADY_RELEASED;
10847 10852 return (DDI_FAILURE);
10848 10853 }
10849 10854
10850 10855 /*
10851 10856 * Release the buffer.
10852 10857 */
10853 10858 status = mptsas_release_fw_diag_buffer(mpt, pBuffer, return_code,
10854 10859 MPTSAS_FW_DIAG_TYPE_RELEASE);
10855 10860 return (status);
10856 10861 }
10857 10862
10858 10863 static int
10859 10864 mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, uint8_t *diag_action,
10860 10865 uint32_t length, uint32_t *return_code, int ioctl_mode)
10861 10866 {
10862 10867 mptsas_fw_diag_register_t diag_register;
10863 10868 mptsas_fw_diag_unregister_t diag_unregister;
10864 10869 mptsas_fw_diag_query_t diag_query;
10865 10870 mptsas_diag_read_buffer_t diag_read_buffer;
10866 10871 mptsas_fw_diag_release_t diag_release;
10867 10872 int status = DDI_SUCCESS;
10868 10873 uint32_t original_return_code, read_buf_len;
10869 10874
10870 10875 ASSERT(mutex_owned(&mpt->m_mutex));
10871 10876
10872 10877 original_return_code = *return_code;
10873 10878 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
10874 10879
10875 10880 switch (action) {
10876 10881 case MPTSAS_FW_DIAG_TYPE_REGISTER:
10877 10882 if (!length) {
10878 10883 *return_code =
10879 10884 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10880 10885 status = DDI_FAILURE;
10881 10886 break;
10882 10887 }
10883 10888 if (ddi_copyin(diag_action, &diag_register,
10884 10889 sizeof (diag_register), ioctl_mode) != 0) {
10885 10890 return (DDI_FAILURE);
10886 10891 }
10887 10892 status = mptsas_diag_register(mpt, &diag_register,
10888 10893 return_code);
10889 10894 break;
10890 10895
10891 10896 case MPTSAS_FW_DIAG_TYPE_UNREGISTER:
10892 10897 if (length < sizeof (diag_unregister)) {
10893 10898 *return_code =
10894 10899 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10895 10900 status = DDI_FAILURE;
10896 10901 break;
10897 10902 }
10898 10903 if (ddi_copyin(diag_action, &diag_unregister,
10899 10904 sizeof (diag_unregister), ioctl_mode) != 0) {
10900 10905 return (DDI_FAILURE);
10901 10906 }
10902 10907 status = mptsas_diag_unregister(mpt, &diag_unregister,
10903 10908 return_code);
10904 10909 break;
10905 10910
10906 10911 case MPTSAS_FW_DIAG_TYPE_QUERY:
10907 10912 if (length < sizeof (diag_query)) {
10908 10913 *return_code =
10909 10914 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10910 10915 status = DDI_FAILURE;
10911 10916 break;
10912 10917 }
10913 10918 if (ddi_copyin(diag_action, &diag_query,
10914 10919 sizeof (diag_query), ioctl_mode) != 0) {
10915 10920 return (DDI_FAILURE);
10916 10921 }
10917 10922 status = mptsas_diag_query(mpt, &diag_query,
10918 10923 return_code);
10919 10924 if (status == DDI_SUCCESS) {
10920 10925 if (ddi_copyout(&diag_query, diag_action,
10921 10926 sizeof (diag_query), ioctl_mode) != 0) {
10922 10927 return (DDI_FAILURE);
10923 10928 }
10924 10929 }
10925 10930 break;
10926 10931
10927 10932 case MPTSAS_FW_DIAG_TYPE_READ_BUFFER:
10928 10933 if (ddi_copyin(diag_action, &diag_read_buffer,
10929 10934 sizeof (diag_read_buffer) - 4, ioctl_mode) != 0) {
10930 10935 return (DDI_FAILURE);
10931 10936 }
10932 10937 read_buf_len = sizeof (diag_read_buffer) -
10933 10938 sizeof (diag_read_buffer.DataBuffer) +
10934 10939 diag_read_buffer.BytesToRead;
10935 10940 if (length < read_buf_len) {
10936 10941 *return_code =
10937 10942 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10938 10943 status = DDI_FAILURE;
10939 10944 break;
10940 10945 }
10941 10946 status = mptsas_diag_read_buffer(mpt,
10942 10947 &diag_read_buffer, diag_action +
10943 10948 sizeof (diag_read_buffer) - 4, return_code,
10944 10949 ioctl_mode);
10945 10950 if (status == DDI_SUCCESS) {
10946 10951 if (ddi_copyout(&diag_read_buffer, diag_action,
10947 10952 sizeof (diag_read_buffer) - 4, ioctl_mode)
10948 10953 != 0) {
10949 10954 return (DDI_FAILURE);
10950 10955 }
10951 10956 }
10952 10957 break;
10953 10958
10954 10959 case MPTSAS_FW_DIAG_TYPE_RELEASE:
10955 10960 if (length < sizeof (diag_release)) {
10956 10961 *return_code =
10957 10962 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10958 10963 status = DDI_FAILURE;
10959 10964 break;
10960 10965 }
10961 10966 if (ddi_copyin(diag_action, &diag_release,
10962 10967 sizeof (diag_release), ioctl_mode) != 0) {
10963 10968 return (DDI_FAILURE);
10964 10969 }
10965 10970 status = mptsas_diag_release(mpt, &diag_release,
10966 10971 return_code);
10967 10972 break;
10968 10973
10969 10974 default:
10970 10975 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10971 10976 status = DDI_FAILURE;
10972 10977 break;
10973 10978 }
10974 10979
10975 10980 if ((status == DDI_FAILURE) &&
10976 10981 (original_return_code == MPTSAS_FW_DIAG_NEW) &&
10977 10982 (*return_code != MPTSAS_FW_DIAG_ERROR_SUCCESS)) {
10978 10983 status = DDI_SUCCESS;
10979 10984 }
10980 10985
10981 10986 return (status);
10982 10987 }
10983 10988
10984 10989 static int
10985 10990 mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *user_data, int mode)
10986 10991 {
10987 10992 int status;
10988 10993 mptsas_diag_action_t driver_data;
10989 10994
10990 10995 ASSERT(mutex_owned(&mpt->m_mutex));
10991 10996
10992 10997 /*
10993 10998 * Copy the user data to a driver data buffer.
10994 10999 */
10995 11000 if (ddi_copyin(user_data, &driver_data, sizeof (mptsas_diag_action_t),
10996 11001 mode) == 0) {
10997 11002 /*
10998 11003 * Send diag action request if Action is valid
10999 11004 */
11000 11005 if (driver_data.Action == MPTSAS_FW_DIAG_TYPE_REGISTER ||
11001 11006 driver_data.Action == MPTSAS_FW_DIAG_TYPE_UNREGISTER ||
11002 11007 driver_data.Action == MPTSAS_FW_DIAG_TYPE_QUERY ||
11003 11008 driver_data.Action == MPTSAS_FW_DIAG_TYPE_READ_BUFFER ||
11004 11009 driver_data.Action == MPTSAS_FW_DIAG_TYPE_RELEASE) {
11005 11010 status = mptsas_do_diag_action(mpt, driver_data.Action,
11006 11011 (void *)(uintptr_t)driver_data.PtrDiagAction,
11007 11012 driver_data.Length, &driver_data.ReturnCode,
11008 11013 mode);
11009 11014 if (status == DDI_SUCCESS) {
11010 11015 if (ddi_copyout(&driver_data.ReturnCode,
11011 11016 &user_data->ReturnCode,
11012 11017 sizeof (user_data->ReturnCode), mode)
11013 11018 != 0) {
11014 11019 status = EFAULT;
11015 11020 } else {
11016 11021 status = 0;
11017 11022 }
11018 11023 } else {
11019 11024 status = EIO;
11020 11025 }
11021 11026 } else {
11022 11027 status = EINVAL;
11023 11028 }
11024 11029 } else {
11025 11030 status = EFAULT;
11026 11031 }
11027 11032
11028 11033 return (status);
11029 11034 }
11030 11035
11031 11036 /*
11032 11037 * This routine handles the "event query" ioctl.
11033 11038 */
11034 11039 static int
11035 11040 mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, int mode,
11036 11041 int *rval)
11037 11042 {
11038 11043 int status;
11039 11044 mptsas_event_query_t driverdata;
11040 11045 uint8_t i;
11041 11046
11042 11047 driverdata.Entries = MPTSAS_EVENT_QUEUE_SIZE;
11043 11048
11044 11049 mutex_enter(&mpt->m_mutex);
11045 11050 for (i = 0; i < 4; i++) {
11046 11051 driverdata.Types[i] = mpt->m_event_mask[i];
11047 11052 }
11048 11053 mutex_exit(&mpt->m_mutex);
11049 11054
11050 11055 if (ddi_copyout(&driverdata, data, sizeof (driverdata), mode) != 0) {
11051 11056 status = EFAULT;
11052 11057 } else {
11053 11058 *rval = MPTIOCTL_STATUS_GOOD;
11054 11059 status = 0;
11055 11060 }
11056 11061
11057 11062 return (status);
11058 11063 }
11059 11064
11060 11065 /*
11061 11066 * This routine handles the "event enable" ioctl.
11062 11067 */
11063 11068 static int
11064 11069 mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, int mode,
11065 11070 int *rval)
11066 11071 {
11067 11072 int status;
11068 11073 mptsas_event_enable_t driverdata;
11069 11074 uint8_t i;
11070 11075
11071 11076 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) {
11072 11077 mutex_enter(&mpt->m_mutex);
11073 11078 for (i = 0; i < 4; i++) {
11074 11079 mpt->m_event_mask[i] = driverdata.Types[i];
11075 11080 }
11076 11081 mutex_exit(&mpt->m_mutex);
11077 11082
11078 11083 *rval = MPTIOCTL_STATUS_GOOD;
11079 11084 status = 0;
11080 11085 } else {
11081 11086 status = EFAULT;
11082 11087 }
11083 11088 return (status);
11084 11089 }
11085 11090
11086 11091 /*
11087 11092 * This routine handles the "event report" ioctl.
11088 11093 */
11089 11094 static int
11090 11095 mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, int mode,
11091 11096 int *rval)
11092 11097 {
11093 11098 int status;
11094 11099 mptsas_event_report_t driverdata;
11095 11100
11096 11101 mutex_enter(&mpt->m_mutex);
11097 11102
11098 11103 if (ddi_copyin(&data->Size, &driverdata.Size, sizeof (driverdata.Size),
11099 11104 mode) == 0) {
11100 11105 if (driverdata.Size >= sizeof (mpt->m_events)) {
11101 11106 if (ddi_copyout(mpt->m_events, data->Events,
11102 11107 sizeof (mpt->m_events), mode) != 0) {
11103 11108 status = EFAULT;
11104 11109 } else {
11105 11110 if (driverdata.Size > sizeof (mpt->m_events)) {
11106 11111 driverdata.Size =
11107 11112 sizeof (mpt->m_events);
11108 11113 if (ddi_copyout(&driverdata.Size,
11109 11114 &data->Size,
11110 11115 sizeof (driverdata.Size),
11111 11116 mode) != 0) {
11112 11117 status = EFAULT;
11113 11118 } else {
11114 11119 *rval = MPTIOCTL_STATUS_GOOD;
11115 11120 status = 0;
11116 11121 }
11117 11122 } else {
11118 11123 *rval = MPTIOCTL_STATUS_GOOD;
11119 11124 status = 0;
11120 11125 }
11121 11126 }
11122 11127 } else {
11123 11128 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT;
11124 11129 status = 0;
11125 11130 }
11126 11131 } else {
11127 11132 status = EFAULT;
11128 11133 }
11129 11134
11130 11135 mutex_exit(&mpt->m_mutex);
11131 11136 return (status);
11132 11137 }
11133 11138
11134 11139 static void
11135 11140 mptsas_lookup_pci_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data)
11136 11141 {
11137 11142 int *reg_data;
11138 11143 uint_t reglen;
11139 11144
11140 11145 /*
11141 11146 * Lookup the 'reg' property and extract the other data
11142 11147 */
11143 11148 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip,
11144 11149 DDI_PROP_DONTPASS, "reg", ®_data, ®len) ==
11145 11150 DDI_PROP_SUCCESS) {
11146 11151 /*
11147 11152 * Extract the PCI data from the 'reg' property first DWORD.
11148 11153 * The entry looks like the following:
11149 11154 * First DWORD:
11150 11155 * Bits 0 - 7 8-bit Register number
11151 11156 * Bits 8 - 10 3-bit Function number
11152 11157 * Bits 11 - 15 5-bit Device number
11153 11158 * Bits 16 - 23 8-bit Bus number
11154 11159 * Bits 24 - 25 2-bit Address Space type identifier
11155 11160 *
11156 11161 */
11157 11162 adapter_data->PciInformation.u.bits.BusNumber =
11158 11163 (reg_data[0] & 0x00FF0000) >> 16;
11159 11164 adapter_data->PciInformation.u.bits.DeviceNumber =
11160 11165 (reg_data[0] & 0x0000F800) >> 11;
11161 11166 adapter_data->PciInformation.u.bits.FunctionNumber =
11162 11167 (reg_data[0] & 0x00000700) >> 8;
11163 11168 ddi_prop_free((void *)reg_data);
11164 11169 } else {
11165 11170 /*
11166 11171 * If we can't determine the PCI data then we fill in FF's for
11167 11172 * the data to indicate this.
11168 11173 */
11169 11174 adapter_data->PCIDeviceHwId = 0xFFFFFFFF;
11170 11175 adapter_data->MpiPortNumber = 0xFFFFFFFF;
11171 11176 adapter_data->PciInformation.u.AsDWORD = 0xFFFFFFFF;
11172 11177 }
11173 11178
11174 11179 /*
11175 11180 * Saved in the mpt->m_fwversion
11176 11181 */
11177 11182 adapter_data->MpiFirmwareVersion = mpt->m_fwversion;
11178 11183 }
11179 11184
11180 11185 static void
11181 11186 mptsas_read_adapter_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data)
11182 11187 {
11183 11188 char *driver_verstr = MPTSAS_MOD_STRING;
11184 11189
11185 11190 mptsas_lookup_pci_data(mpt, adapter_data);
11186 11191 adapter_data->AdapterType = MPTIOCTL_ADAPTER_TYPE_SAS2;
11187 11192 adapter_data->PCIDeviceHwId = (uint32_t)mpt->m_devid;
11188 11193 adapter_data->PCIDeviceHwRev = (uint32_t)mpt->m_revid;
11189 11194 adapter_data->SubSystemId = (uint32_t)mpt->m_ssid;
11190 11195 adapter_data->SubsystemVendorId = (uint32_t)mpt->m_svid;
11191 11196 (void) strcpy((char *)&adapter_data->DriverVersion[0], driver_verstr);
11192 11197 adapter_data->BiosVersion = 0;
11193 11198 (void) mptsas_get_bios_page3(mpt, &adapter_data->BiosVersion);
11194 11199 }
11195 11200
11196 11201 static void
11197 11202 mptsas_read_pci_info(mptsas_t *mpt, mptsas_pci_info_t *pci_info)
11198 11203 {
11199 11204 int *reg_data, i;
11200 11205 uint_t reglen;
11201 11206
11202 11207 /*
11203 11208 * Lookup the 'reg' property and extract the other data
11204 11209 */
11205 11210 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip,
11206 11211 DDI_PROP_DONTPASS, "reg", ®_data, ®len) ==
11207 11212 DDI_PROP_SUCCESS) {
11208 11213 /*
11209 11214 * Extract the PCI data from the 'reg' property first DWORD.
11210 11215 * The entry looks like the following:
11211 11216 * First DWORD:
11212 11217 * Bits 8 - 10 3-bit Function number
11213 11218 * Bits 11 - 15 5-bit Device number
11214 11219 * Bits 16 - 23 8-bit Bus number
11215 11220 */
11216 11221 pci_info->BusNumber = (reg_data[0] & 0x00FF0000) >> 16;
11217 11222 pci_info->DeviceNumber = (reg_data[0] & 0x0000F800) >> 11;
11218 11223 pci_info->FunctionNumber = (reg_data[0] & 0x00000700) >> 8;
11219 11224 ddi_prop_free((void *)reg_data);
11220 11225 } else {
11221 11226 /*
11222 11227 * If we can't determine the PCI info then we fill in FF's for
11223 11228 * the data to indicate this.
11224 11229 */
11225 11230 pci_info->BusNumber = 0xFFFFFFFF;
11226 11231 pci_info->DeviceNumber = 0xFF;
11227 11232 pci_info->FunctionNumber = 0xFF;
11228 11233 }
11229 11234
11230 11235 /*
11231 11236 * Now get the interrupt vector and the pci header. The vector can
11232 11237 * only be 0 right now. The header is the first 256 bytes of config
11233 11238 * space.
11234 11239 */
11235 11240 pci_info->InterruptVector = 0;
11236 11241 for (i = 0; i < sizeof (pci_info->PciHeader); i++) {
11237 11242 pci_info->PciHeader[i] = pci_config_get8(mpt->m_config_handle,
11238 11243 i);
11239 11244 }
11240 11245 }
11241 11246
11242 11247 static int
11243 11248 mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, int mode)
11244 11249 {
11245 11250 int status = 0;
11246 11251 mptsas_reg_access_t driverdata;
11247 11252
11248 11253 mutex_enter(&mpt->m_mutex);
11249 11254 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) {
11250 11255 switch (driverdata.Command) {
11251 11256 /*
11252 11257 * IO access is not supported.
11253 11258 */
11254 11259 case REG_IO_READ:
11255 11260 case REG_IO_WRITE:
11256 11261 mptsas_log(mpt, CE_WARN, "IO access is not "
11257 11262 "supported. Use memory access.");
11258 11263 status = EINVAL;
11259 11264 break;
11260 11265
11261 11266 case REG_MEM_READ:
11262 11267 driverdata.RegData = ddi_get32(mpt->m_datap,
11263 11268 (uint32_t *)(void *)mpt->m_reg +
11264 11269 driverdata.RegOffset);
11265 11270 if (ddi_copyout(&driverdata.RegData,
11266 11271 &data->RegData,
11267 11272 sizeof (driverdata.RegData), mode) != 0) {
11268 11273 mptsas_log(mpt, CE_WARN, "Register "
11269 11274 "Read Failed");
11270 11275 status = EFAULT;
11271 11276 }
11272 11277 break;
11273 11278
11274 11279 case REG_MEM_WRITE:
11275 11280 ddi_put32(mpt->m_datap,
11276 11281 (uint32_t *)(void *)mpt->m_reg +
11277 11282 driverdata.RegOffset,
11278 11283 driverdata.RegData);
11279 11284 break;
11280 11285
11281 11286 default:
11282 11287 status = EINVAL;
11283 11288 break;
11284 11289 }
11285 11290 } else {
11286 11291 status = EFAULT;
11287 11292 }
11288 11293
11289 11294 mutex_exit(&mpt->m_mutex);
11290 11295 return (status);
11291 11296 }
11292 11297
11293 11298 static int
11294 11299 led_control(mptsas_t *mpt, intptr_t data, int mode)
11295 11300 {
11296 11301 int ret = 0;
11297 11302 mptsas_led_control_t lc;
11298 11303 mptsas_target_t *ptgt;
11299 11304
11300 11305 if (ddi_copyin((void *)data, &lc, sizeof (lc), mode) != 0) {
11301 11306 return (EFAULT);
11302 11307 }
11303 11308
11304 11309 if ((lc.Command != MPTSAS_LEDCTL_FLAG_SET &&
11305 11310 lc.Command != MPTSAS_LEDCTL_FLAG_GET) ||
11306 11311 lc.Led < MPTSAS_LEDCTL_LED_MIN ||
11307 11312 lc.Led > MPTSAS_LEDCTL_LED_MAX ||
11308 11313 (lc.Command == MPTSAS_LEDCTL_FLAG_SET && lc.LedStatus != 0 &&
11309 11314 lc.LedStatus != 1)) {
11310 11315 return (EINVAL);
11311 11316 }
11312 11317
11313 11318 if ((lc.Command == MPTSAS_LEDCTL_FLAG_SET && (mode & FWRITE) == 0) ||
11314 11319 (lc.Command == MPTSAS_LEDCTL_FLAG_GET && (mode & FREAD) == 0))
11315 11320 return (EACCES);
11316 11321
11317 11322 /* Locate the target we're interrogating... */
11318 11323 mutex_enter(&mpt->m_mutex);
11319 11324 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
11320 11325 MPTSAS_HASH_FIRST);
11321 11326 while (ptgt != NULL) {
11322 11327 if (ptgt->m_enclosure == lc.Enclosure &&
11323 11328 ptgt->m_slot_num == lc.Slot) {
11324 11329 break;
11325 11330 }
11326 11331 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
11327 11332 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
11328 11333 }
11329 11334 if (ptgt == NULL) {
11330 11335 /* We could not find a target for that enclosure/slot. */
11331 11336 mutex_exit(&mpt->m_mutex);
11332 11337 return (ENOENT);
11333 11338 }
11334 11339
11335 11340 if (lc.Command == MPTSAS_LEDCTL_FLAG_SET) {
11336 11341 /* Update our internal LED state. */
11337 11342 ptgt->m_led_status &= ~(1 << (lc.Led - 1));
11338 11343 ptgt->m_led_status |= lc.LedStatus << (lc.Led - 1);
11339 11344
11340 11345 /* Flush it to the controller. */
11341 11346 ret = mptsas_flush_led_status(mpt, ptgt);
11342 11347 mutex_exit(&mpt->m_mutex);
11343 11348 return (ret);
11344 11349 }
11345 11350
11346 11351 /* Return our internal LED state. */
11347 11352 lc.LedStatus = (ptgt->m_led_status >> (lc.Led - 1)) & 1;
11348 11353 mutex_exit(&mpt->m_mutex);
11349 11354
11350 11355 if (ddi_copyout(&lc, (void *)data, sizeof (lc), mode) != 0) {
11351 11356 return (EFAULT);
11352 11357 }
11353 11358
11354 11359 return (0);
11355 11360 }
11356 11361
11357 11362 static int
11358 11363 get_disk_info(mptsas_t *mpt, intptr_t data, int mode)
11359 11364 {
11360 11365 uint16_t i = 0;
11361 11366 uint16_t count = 0;
11362 11367 int ret = 0;
11363 11368 mptsas_target_t *ptgt;
11364 11369 mptsas_disk_info_t *di;
11365 11370 STRUCT_DECL(mptsas_get_disk_info, gdi);
11366 11371
11367 11372 if ((mode & FREAD) == 0)
11368 11373 return (EACCES);
11369 11374
11370 11375 STRUCT_INIT(gdi, get_udatamodel());
11371 11376
11372 11377 if (ddi_copyin((void *)data, STRUCT_BUF(gdi), STRUCT_SIZE(gdi),
11373 11378 mode) != 0) {
11374 11379 return (EFAULT);
11375 11380 }
11376 11381
11377 11382 /* Find out how many targets there are. */
11378 11383 mutex_enter(&mpt->m_mutex);
11379 11384 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
11380 11385 MPTSAS_HASH_FIRST);
11381 11386 while (ptgt != NULL) {
11382 11387 count++;
11383 11388 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
11384 11389 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
11385 11390 }
11386 11391 mutex_exit(&mpt->m_mutex);
11387 11392
11388 11393 /*
11389 11394 * If we haven't been asked to copy out information on each target,
11390 11395 * then just return the count.
11391 11396 */
11392 11397 STRUCT_FSET(gdi, DiskCount, count);
11393 11398 if (STRUCT_FGETP(gdi, PtrDiskInfoArray) == NULL)
11394 11399 goto copy_out;
11395 11400
11396 11401 /*
11397 11402 * If we haven't been given a large enough buffer to copy out into,
11398 11403 * let the caller know.
11399 11404 */
11400 11405 if (STRUCT_FGET(gdi, DiskInfoArraySize) <
11401 11406 count * sizeof (mptsas_disk_info_t)) {
11402 11407 ret = ENOSPC;
11403 11408 goto copy_out;
11404 11409 }
11405 11410
11406 11411 di = kmem_zalloc(count * sizeof (mptsas_disk_info_t), KM_SLEEP);
11407 11412
11408 11413 mutex_enter(&mpt->m_mutex);
11409 11414 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
11410 11415 MPTSAS_HASH_FIRST);
11411 11416 while (ptgt != NULL) {
11412 11417 if (i >= count) {
11413 11418 /*
11414 11419 * The number of targets changed while we weren't
11415 11420 * looking, so give up.
11416 11421 */
11417 11422 mutex_exit(&mpt->m_mutex);
11418 11423 kmem_free(di, count * sizeof (mptsas_disk_info_t));
11419 11424 return (EAGAIN);
11420 11425 }
11421 11426 di[i].Instance = mpt->m_instance;
11422 11427 di[i].Enclosure = ptgt->m_enclosure;
11423 11428 di[i].Slot = ptgt->m_slot_num;
11424 11429 di[i].SasAddress = ptgt->m_sas_wwn;
11425 11430
11426 11431 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
11427 11432 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
11428 11433 i++;
11429 11434 }
11430 11435 mutex_exit(&mpt->m_mutex);
11431 11436 STRUCT_FSET(gdi, DiskCount, i);
11432 11437
11433 11438 /* Copy out the disk information to the caller. */
11434 11439 if (ddi_copyout((void *)di, STRUCT_FGETP(gdi, PtrDiskInfoArray),
11435 11440 i * sizeof (mptsas_disk_info_t), mode) != 0) {
11436 11441 ret = EFAULT;
11437 11442 }
11438 11443
11439 11444 kmem_free(di, count * sizeof (mptsas_disk_info_t));
11440 11445
11441 11446 copy_out:
11442 11447 if (ddi_copyout(STRUCT_BUF(gdi), (void *)data, STRUCT_SIZE(gdi),
11443 11448 mode) != 0) {
11444 11449 ret = EFAULT;
11445 11450 }
11446 11451
11447 11452 return (ret);
11448 11453 }
11449 11454
11450 11455 static int
11451 11456 mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, cred_t *credp,
11452 11457 int *rval)
11453 11458 {
11454 11459 int status = 0;
11455 11460 mptsas_t *mpt;
11456 11461 mptsas_update_flash_t flashdata;
11457 11462 mptsas_pass_thru_t passthru_data;
11458 11463 mptsas_adapter_data_t adapter_data;
11459 11464 mptsas_pci_info_t pci_info;
11460 11465 int copylen;
11461 11466
11462 11467 int iport_flag = 0;
11463 11468 dev_info_t *dip = NULL;
11464 11469 mptsas_phymask_t phymask = 0;
11465 11470 struct devctl_iocdata *dcp = NULL;
11466 11471 char *addr = NULL;
11467 11472 mptsas_target_t *ptgt = NULL;
11468 11473
11469 11474 *rval = MPTIOCTL_STATUS_GOOD;
11470 11475 if (secpolicy_sys_config(credp, B_FALSE) != 0) {
11471 11476 return (EPERM);
11472 11477 }
11473 11478
11474 11479 mpt = ddi_get_soft_state(mptsas_state, MINOR2INST(getminor(dev)));
11475 11480 if (mpt == NULL) {
11476 11481 /*
11477 11482 * Called from iport node, get the states
11478 11483 */
11479 11484 iport_flag = 1;
11480 11485 dip = mptsas_get_dip_from_dev(dev, &phymask);
11481 11486 if (dip == NULL) {
11482 11487 return (ENXIO);
11483 11488 }
11484 11489 mpt = DIP2MPT(dip);
11485 11490 }
11486 11491 /* Make sure power level is D0 before accessing registers */
11487 11492 mutex_enter(&mpt->m_mutex);
11488 11493 if (mpt->m_options & MPTSAS_OPT_PM) {
11489 11494 (void) pm_busy_component(mpt->m_dip, 0);
11490 11495 if (mpt->m_power_level != PM_LEVEL_D0) {
11491 11496 mutex_exit(&mpt->m_mutex);
11492 11497 if (pm_raise_power(mpt->m_dip, 0, PM_LEVEL_D0) !=
11493 11498 DDI_SUCCESS) {
11494 11499 mptsas_log(mpt, CE_WARN,
11495 11500 "mptsas%d: mptsas_ioctl: Raise power "
11496 11501 "request failed.", mpt->m_instance);
11497 11502 (void) pm_idle_component(mpt->m_dip, 0);
11498 11503 return (ENXIO);
11499 11504 }
11500 11505 } else {
11501 11506 mutex_exit(&mpt->m_mutex);
11502 11507 }
11503 11508 } else {
11504 11509 mutex_exit(&mpt->m_mutex);
11505 11510 }
11506 11511
11507 11512 if (iport_flag) {
11508 11513 status = scsi_hba_ioctl(dev, cmd, data, mode, credp, rval);
11509 11514 if (status != 0) {
11510 11515 goto out;
11511 11516 }
11512 11517 /*
11513 11518 * The following code control the OK2RM LED, it doesn't affect
11514 11519 * the ioctl return status.
11515 11520 */
11516 11521 if ((cmd == DEVCTL_DEVICE_ONLINE) ||
11517 11522 (cmd == DEVCTL_DEVICE_OFFLINE)) {
11518 11523 if (ndi_dc_allochdl((void *)data, &dcp) !=
11519 11524 NDI_SUCCESS) {
11520 11525 goto out;
11521 11526 }
11522 11527 addr = ndi_dc_getaddr(dcp);
11523 11528 ptgt = mptsas_addr_to_ptgt(mpt, addr, phymask);
11524 11529 if (ptgt == NULL) {
11525 11530 NDBG14(("mptsas_ioctl led control: tgt %s not "
11526 11531 "found", addr));
11527 11532 ndi_dc_freehdl(dcp);
11528 11533 goto out;
11529 11534 }
11530 11535 mutex_enter(&mpt->m_mutex);
11531 11536 if (cmd == DEVCTL_DEVICE_ONLINE) {
11532 11537 ptgt->m_tgt_unconfigured = 0;
11533 11538 } else if (cmd == DEVCTL_DEVICE_OFFLINE) {
11534 11539 ptgt->m_tgt_unconfigured = 1;
11535 11540 }
11536 11541 if (cmd == DEVCTL_DEVICE_OFFLINE) {
11537 11542 ptgt->m_led_status |=
11538 11543 (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1));
11539 11544 } else {
11540 11545 ptgt->m_led_status &=
11541 11546 ~(1 << (MPTSAS_LEDCTL_LED_OK2RM - 1));
11542 11547 }
11543 11548 (void) mptsas_flush_led_status(mpt, ptgt);
11544 11549 mutex_exit(&mpt->m_mutex);
11545 11550 ndi_dc_freehdl(dcp);
11546 11551 }
11547 11552 goto out;
11548 11553 }
11549 11554 switch (cmd) {
11550 11555 case MPTIOCTL_GET_DISK_INFO:
11551 11556 status = get_disk_info(mpt, data, mode);
11552 11557 break;
11553 11558 case MPTIOCTL_LED_CONTROL:
11554 11559 status = led_control(mpt, data, mode);
11555 11560 break;
11556 11561 case MPTIOCTL_UPDATE_FLASH:
11557 11562 if (ddi_copyin((void *)data, &flashdata,
11558 11563 sizeof (struct mptsas_update_flash), mode)) {
11559 11564 status = EFAULT;
11560 11565 break;
11561 11566 }
11562 11567
11563 11568 mutex_enter(&mpt->m_mutex);
11564 11569 if (mptsas_update_flash(mpt,
11565 11570 (caddr_t)(long)flashdata.PtrBuffer,
11566 11571 flashdata.ImageSize, flashdata.ImageType, mode)) {
11567 11572 status = EFAULT;
11568 11573 }
11569 11574
11570 11575 /*
11571 11576 * Reset the chip to start using the new
11572 11577 * firmware. Reset if failed also.
11573 11578 */
11574 11579 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
11575 11580 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) {
11576 11581 status = EFAULT;
11577 11582 }
11578 11583 mutex_exit(&mpt->m_mutex);
11579 11584 break;
11580 11585 case MPTIOCTL_PASS_THRU:
11581 11586 /*
11582 11587 * The user has requested to pass through a command to
11583 11588 * be executed by the MPT firmware. Call our routine
11584 11589 * which does this. Only allow one passthru IOCTL at
11585 11590 * one time. Other threads will block on
11586 11591 * m_passthru_mutex, which is of adaptive variant.
11587 11592 */
11588 11593 if (ddi_copyin((void *)data, &passthru_data,
11589 11594 sizeof (mptsas_pass_thru_t), mode)) {
11590 11595 status = EFAULT;
11591 11596 break;
11592 11597 }
11593 11598 mutex_enter(&mpt->m_passthru_mutex);
11594 11599 mutex_enter(&mpt->m_mutex);
11595 11600 status = mptsas_pass_thru(mpt, &passthru_data, mode);
11596 11601 mutex_exit(&mpt->m_mutex);
11597 11602 mutex_exit(&mpt->m_passthru_mutex);
11598 11603
11599 11604 break;
11600 11605 case MPTIOCTL_GET_ADAPTER_DATA:
11601 11606 /*
11602 11607 * The user has requested to read adapter data. Call
11603 11608 * our routine which does this.
11604 11609 */
11605 11610 bzero(&adapter_data, sizeof (mptsas_adapter_data_t));
11606 11611 if (ddi_copyin((void *)data, (void *)&adapter_data,
11607 11612 sizeof (mptsas_adapter_data_t), mode)) {
11608 11613 status = EFAULT;
11609 11614 break;
11610 11615 }
11611 11616 if (adapter_data.StructureLength >=
11612 11617 sizeof (mptsas_adapter_data_t)) {
11613 11618 adapter_data.StructureLength = (uint32_t)
11614 11619 sizeof (mptsas_adapter_data_t);
11615 11620 copylen = sizeof (mptsas_adapter_data_t);
11616 11621 mutex_enter(&mpt->m_mutex);
11617 11622 mptsas_read_adapter_data(mpt, &adapter_data);
11618 11623 mutex_exit(&mpt->m_mutex);
11619 11624 } else {
11620 11625 adapter_data.StructureLength = (uint32_t)
11621 11626 sizeof (mptsas_adapter_data_t);
11622 11627 copylen = sizeof (adapter_data.StructureLength);
11623 11628 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT;
11624 11629 }
11625 11630 if (ddi_copyout((void *)(&adapter_data), (void *)data,
11626 11631 copylen, mode) != 0) {
11627 11632 status = EFAULT;
11628 11633 }
11629 11634 break;
11630 11635 case MPTIOCTL_GET_PCI_INFO:
11631 11636 /*
11632 11637 * The user has requested to read pci info. Call
11633 11638 * our routine which does this.
11634 11639 */
11635 11640 bzero(&pci_info, sizeof (mptsas_pci_info_t));
11636 11641 mutex_enter(&mpt->m_mutex);
11637 11642 mptsas_read_pci_info(mpt, &pci_info);
11638 11643 mutex_exit(&mpt->m_mutex);
11639 11644 if (ddi_copyout((void *)(&pci_info), (void *)data,
11640 11645 sizeof (mptsas_pci_info_t), mode) != 0) {
11641 11646 status = EFAULT;
11642 11647 }
11643 11648 break;
11644 11649 case MPTIOCTL_RESET_ADAPTER:
11645 11650 mutex_enter(&mpt->m_mutex);
11646 11651 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
11647 11652 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
11648 11653 mptsas_log(mpt, CE_WARN, "reset adapter IOCTL "
11649 11654 "failed");
11650 11655 status = EFAULT;
11651 11656 }
11652 11657 mutex_exit(&mpt->m_mutex);
11653 11658 break;
11654 11659 case MPTIOCTL_DIAG_ACTION:
11655 11660 /*
11656 11661 * The user has done a diag buffer action. Call our
11657 11662 * routine which does this. Only allow one diag action
11658 11663 * at one time.
11659 11664 */
11660 11665 mutex_enter(&mpt->m_mutex);
11661 11666 if (mpt->m_diag_action_in_progress) {
11662 11667 mutex_exit(&mpt->m_mutex);
11663 11668 return (EBUSY);
11664 11669 }
11665 11670 mpt->m_diag_action_in_progress = 1;
11666 11671 status = mptsas_diag_action(mpt,
11667 11672 (mptsas_diag_action_t *)data, mode);
11668 11673 mpt->m_diag_action_in_progress = 0;
11669 11674 mutex_exit(&mpt->m_mutex);
11670 11675 break;
11671 11676 case MPTIOCTL_EVENT_QUERY:
11672 11677 /*
11673 11678 * The user has done an event query. Call our routine
11674 11679 * which does this.
11675 11680 */
11676 11681 status = mptsas_event_query(mpt,
11677 11682 (mptsas_event_query_t *)data, mode, rval);
11678 11683 break;
11679 11684 case MPTIOCTL_EVENT_ENABLE:
11680 11685 /*
11681 11686 * The user has done an event enable. Call our routine
11682 11687 * which does this.
11683 11688 */
11684 11689 status = mptsas_event_enable(mpt,
11685 11690 (mptsas_event_enable_t *)data, mode, rval);
11686 11691 break;
11687 11692 case MPTIOCTL_EVENT_REPORT:
11688 11693 /*
11689 11694 * The user has done an event report. Call our routine
11690 11695 * which does this.
11691 11696 */
11692 11697 status = mptsas_event_report(mpt,
11693 11698 (mptsas_event_report_t *)data, mode, rval);
11694 11699 break;
11695 11700 case MPTIOCTL_REG_ACCESS:
11696 11701 /*
11697 11702 * The user has requested register access. Call our
11698 11703 * routine which does this.
11699 11704 */
11700 11705 status = mptsas_reg_access(mpt,
11701 11706 (mptsas_reg_access_t *)data, mode);
11702 11707 break;
11703 11708 default:
11704 11709 status = scsi_hba_ioctl(dev, cmd, data, mode, credp,
11705 11710 rval);
11706 11711 break;
11707 11712 }
11708 11713
11709 11714 out:
11710 11715 return (status);
11711 11716 }
11712 11717
11713 11718 int
11714 11719 mptsas_restart_ioc(mptsas_t *mpt)
11715 11720 {
11716 11721 int rval = DDI_SUCCESS;
11717 11722 mptsas_target_t *ptgt = NULL;
11718 11723
11719 11724 ASSERT(mutex_owned(&mpt->m_mutex));
11720 11725
11721 11726 /*
11722 11727 * Set a flag telling I/O path that we're processing a reset. This is
11723 11728 * needed because after the reset is complete, the hash table still
11724 11729 * needs to be rebuilt. If I/Os are started before the hash table is
11725 11730 * rebuilt, I/O errors will occur. This flag allows I/Os to be marked
11726 11731 * so that they can be retried.
11727 11732 */
11728 11733 mpt->m_in_reset = TRUE;
11729 11734
11730 11735 /*
11731 11736 * Set all throttles to HOLD
11732 11737 */
11733 11738 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
11734 11739 MPTSAS_HASH_FIRST);
11735 11740 while (ptgt != NULL) {
11736 11741 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
11737 11742
11738 11743 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
11739 11744 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
11740 11745 }
11741 11746
11742 11747 /*
11743 11748 * Disable interrupts
11744 11749 */
11745 11750 MPTSAS_DISABLE_INTR(mpt);
11746 11751
11747 11752 /*
11748 11753 * Abort all commands: outstanding commands, commands in waitq and
11749 11754 * tx_waitq.
11750 11755 */
11751 11756 mptsas_flush_hba(mpt);
11752 11757
11753 11758 /*
11754 11759 * Reinitialize the chip.
11755 11760 */
11756 11761 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) {
11757 11762 rval = DDI_FAILURE;
11758 11763 }
11759 11764
11760 11765 /*
11761 11766 * Enable interrupts again
11762 11767 */
11763 11768 MPTSAS_ENABLE_INTR(mpt);
11764 11769
11765 11770 /*
11766 11771 * If mptsas_init_chip was successful, update the driver data.
11767 11772 */
11768 11773 if (rval == DDI_SUCCESS) {
11769 11774 mptsas_update_driver_data(mpt);
11770 11775 }
11771 11776
11772 11777 /*
11773 11778 * Reset the throttles
11774 11779 */
11775 11780 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
11776 11781 MPTSAS_HASH_FIRST);
11777 11782 while (ptgt != NULL) {
11778 11783 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
11779 11784
11780 11785 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
11781 11786 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
11782 11787 }
11783 11788
11784 11789 mptsas_doneq_empty(mpt);
11785 11790 mptsas_restart_hba(mpt);
11786 11791
11787 11792 if (rval != DDI_SUCCESS) {
11788 11793 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE);
11789 11794 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST);
11790 11795 }
11791 11796
11792 11797 /*
11793 11798 * Clear the reset flag so that I/Os can continue.
11794 11799 */
11795 11800 mpt->m_in_reset = FALSE;
11796 11801
11797 11802 return (rval);
11798 11803 }
11799 11804
11800 11805 static int
11801 11806 mptsas_init_chip(mptsas_t *mpt, int first_time)
11802 11807 {
11803 11808 ddi_dma_cookie_t cookie;
11804 11809 uint32_t i;
11805 11810 int rval;
11806 11811
11807 11812 /*
11808 11813 * Check to see if the firmware image is valid
11809 11814 */
11810 11815 if (ddi_get32(mpt->m_datap, &mpt->m_reg->HostDiagnostic) &
11811 11816 MPI2_DIAG_FLASH_BAD_SIG) {
11812 11817 mptsas_log(mpt, CE_WARN, "mptsas bad flash signature!");
11813 11818 goto fail;
11814 11819 }
11815 11820
11816 11821 /*
11817 11822 * Reset the chip
11818 11823 */
11819 11824 rval = mptsas_ioc_reset(mpt, first_time);
11820 11825 if (rval == MPTSAS_RESET_FAIL) {
11821 11826 mptsas_log(mpt, CE_WARN, "hard reset failed!");
11822 11827 goto fail;
11823 11828 }
11824 11829
11825 11830 if ((rval == MPTSAS_SUCCESS_MUR) && (!first_time)) {
11826 11831 goto mur;
11827 11832 }
11828 11833 /*
11829 11834 * Setup configuration space
11830 11835 */
11831 11836 if (mptsas_config_space_init(mpt) == FALSE) {
11832 11837 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init "
11833 11838 "failed!");
11834 11839 goto fail;
11835 11840 }
11836 11841
11837 11842 /*
11838 11843 * IOC facts can change after a diag reset so all buffers that are
11839 11844 * based on these numbers must be de-allocated and re-allocated. Get
11840 11845 * new IOC facts each time chip is initialized.
11841 11846 */
11842 11847 if (mptsas_ioc_get_facts(mpt) == DDI_FAILURE) {
11843 11848 mptsas_log(mpt, CE_WARN, "mptsas_ioc_get_facts failed");
11844 11849 goto fail;
11845 11850 }
11846 11851
11847 11852 if (mptsas_alloc_active_slots(mpt, KM_SLEEP)) {
11848 11853 goto fail;
11849 11854 }
11850 11855 /*
11851 11856 * Allocate request message frames, reply free queue, reply descriptor
11852 11857 * post queue, and reply message frames using latest IOC facts.
11853 11858 */
11854 11859 if (mptsas_alloc_request_frames(mpt) == DDI_FAILURE) {
11855 11860 mptsas_log(mpt, CE_WARN, "mptsas_alloc_request_frames failed");
11856 11861 goto fail;
11857 11862 }
11858 11863 if (mptsas_alloc_free_queue(mpt) == DDI_FAILURE) {
11859 11864 mptsas_log(mpt, CE_WARN, "mptsas_alloc_free_queue failed!");
11860 11865 goto fail;
11861 11866 }
11862 11867 if (mptsas_alloc_post_queue(mpt) == DDI_FAILURE) {
11863 11868 mptsas_log(mpt, CE_WARN, "mptsas_alloc_post_queue failed!");
11864 11869 goto fail;
11865 11870 }
11866 11871 if (mptsas_alloc_reply_frames(mpt) == DDI_FAILURE) {
11867 11872 mptsas_log(mpt, CE_WARN, "mptsas_alloc_reply_frames failed!");
11868 11873 goto fail;
11869 11874 }
11870 11875
11871 11876 mur:
11872 11877 /*
11873 11878 * Re-Initialize ioc to operational state
11874 11879 */
11875 11880 if (mptsas_ioc_init(mpt) == DDI_FAILURE) {
11876 11881 mptsas_log(mpt, CE_WARN, "mptsas_ioc_init failed");
11877 11882 goto fail;
11878 11883 }
11879 11884
11880 11885 mptsas_alloc_reply_args(mpt);
11881 11886
11882 11887 /*
11883 11888 * Initialize reply post index. Reply free index is initialized after
11884 11889 * the next loop.
11885 11890 */
11886 11891 mpt->m_post_index = 0;
11887 11892
11888 11893 /*
11889 11894 * Initialize the Reply Free Queue with the physical addresses of our
11890 11895 * reply frames.
11891 11896 */
11892 11897 cookie.dmac_address = mpt->m_reply_frame_dma_addr;
11893 11898 for (i = 0; i < mpt->m_max_replies; i++) {
11894 11899 ddi_put32(mpt->m_acc_free_queue_hdl,
11895 11900 &((uint32_t *)(void *)mpt->m_free_queue)[i],
11896 11901 cookie.dmac_address);
11897 11902 cookie.dmac_address += mpt->m_reply_frame_size;
11898 11903 }
11899 11904 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
11900 11905 DDI_DMA_SYNC_FORDEV);
11901 11906
11902 11907 /*
11903 11908 * Initialize the reply free index to one past the last frame on the
11904 11909 * queue. This will signify that the queue is empty to start with.
11905 11910 */
11906 11911 mpt->m_free_index = i;
11907 11912 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, i);
11908 11913
11909 11914 /*
11910 11915 * Initialize the reply post queue to 0xFFFFFFFF,0xFFFFFFFF's.
11911 11916 */
11912 11917 for (i = 0; i < mpt->m_post_queue_depth; i++) {
11913 11918 ddi_put64(mpt->m_acc_post_queue_hdl,
11914 11919 &((uint64_t *)(void *)mpt->m_post_queue)[i],
11915 11920 0xFFFFFFFFFFFFFFFF);
11916 11921 }
11917 11922 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
11918 11923 DDI_DMA_SYNC_FORDEV);
11919 11924
11920 11925 /*
11921 11926 * Enable ports
11922 11927 */
11923 11928 if (mptsas_ioc_enable_port(mpt) == DDI_FAILURE) {
11924 11929 mptsas_log(mpt, CE_WARN, "mptsas_ioc_enable_port failed");
11925 11930 goto fail;
11926 11931 }
11927 11932
11928 11933 /*
11929 11934 * enable events
11930 11935 */
11931 11936 if (mptsas_ioc_enable_event_notification(mpt)) {
11932 11937 goto fail;
11933 11938 }
11934 11939
11935 11940 /*
11936 11941 * We need checks in attach and these.
11937 11942 * chip_init is called in mult. places
11938 11943 */
11939 11944
11940 11945 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
11941 11946 DDI_SUCCESS) ||
11942 11947 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) !=
11943 11948 DDI_SUCCESS) ||
11944 11949 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) !=
11945 11950 DDI_SUCCESS) ||
11946 11951 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) !=
11947 11952 DDI_SUCCESS) ||
11948 11953 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) !=
11949 11954 DDI_SUCCESS)) {
11950 11955 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
11951 11956 goto fail;
11952 11957 }
11953 11958
11954 11959 /* Check all acc handles */
11955 11960 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) ||
11956 11961 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
11957 11962 DDI_SUCCESS) ||
11958 11963 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) !=
11959 11964 DDI_SUCCESS) ||
11960 11965 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) !=
11961 11966 DDI_SUCCESS) ||
11962 11967 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) !=
11963 11968 DDI_SUCCESS) ||
11964 11969 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) !=
11965 11970 DDI_SUCCESS) ||
11966 11971 (mptsas_check_acc_handle(mpt->m_config_handle) !=
11967 11972 DDI_SUCCESS)) {
11968 11973 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
11969 11974 goto fail;
11970 11975 }
11971 11976
11972 11977 return (DDI_SUCCESS);
11973 11978
11974 11979 fail:
11975 11980 return (DDI_FAILURE);
11976 11981 }
11977 11982
11978 11983 static int
11979 11984 mptsas_get_pci_cap(mptsas_t *mpt)
11980 11985 {
11981 11986 ushort_t caps_ptr, cap, cap_count;
11982 11987
11983 11988 if (mpt->m_config_handle == NULL)
11984 11989 return (FALSE);
11985 11990 /*
11986 11991 * Check if capabilities list is supported and if so,
11987 11992 * get initial capabilities pointer and clear bits 0,1.
11988 11993 */
11989 11994 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT)
11990 11995 & PCI_STAT_CAP) {
11991 11996 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle,
11992 11997 PCI_CONF_CAP_PTR), 4);
11993 11998 } else {
11994 11999 caps_ptr = PCI_CAP_NEXT_PTR_NULL;
11995 12000 }
11996 12001
11997 12002 /*
11998 12003 * Walk capabilities if supported.
11999 12004 */
12000 12005 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) {
12001 12006
12002 12007 /*
12003 12008 * Check that we haven't exceeded the maximum number of
12004 12009 * capabilities and that the pointer is in a valid range.
12005 12010 */
12006 12011 if (++cap_count > 48) {
12007 12012 mptsas_log(mpt, CE_WARN,
12008 12013 "too many device capabilities.\n");
12009 12014 break;
12010 12015 }
12011 12016 if (caps_ptr < 64) {
12012 12017 mptsas_log(mpt, CE_WARN,
12013 12018 "capabilities pointer 0x%x out of range.\n",
12014 12019 caps_ptr);
12015 12020 break;
12016 12021 }
12017 12022
12018 12023 /*
12019 12024 * Get next capability and check that it is valid.
12020 12025 * For now, we only support power management.
12021 12026 */
12022 12027 cap = pci_config_get8(mpt->m_config_handle, caps_ptr);
12023 12028 switch (cap) {
12024 12029 case PCI_CAP_ID_PM:
12025 12030 mptsas_log(mpt, CE_NOTE,
12026 12031 "?mptsas%d supports power management.\n",
12027 12032 mpt->m_instance);
12028 12033 mpt->m_options |= MPTSAS_OPT_PM;
12029 12034
12030 12035 /* Save PMCSR offset */
12031 12036 mpt->m_pmcsr_offset = caps_ptr + PCI_PMCSR;
12032 12037 break;
12033 12038 /*
12034 12039 * The following capabilities are valid. Any others
12035 12040 * will cause a message to be logged.
12036 12041 */
12037 12042 case PCI_CAP_ID_VPD:
12038 12043 case PCI_CAP_ID_MSI:
12039 12044 case PCI_CAP_ID_PCIX:
12040 12045 case PCI_CAP_ID_PCI_E:
12041 12046 case PCI_CAP_ID_MSI_X:
12042 12047 break;
12043 12048 default:
12044 12049 mptsas_log(mpt, CE_NOTE,
12045 12050 "?mptsas%d unrecognized capability "
12046 12051 "0x%x.\n", mpt->m_instance, cap);
12047 12052 break;
12048 12053 }
12049 12054
12050 12055 /*
12051 12056 * Get next capabilities pointer and clear bits 0,1.
12052 12057 */
12053 12058 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle,
12054 12059 (caps_ptr + PCI_CAP_NEXT_PTR)), 4);
12055 12060 }
12056 12061 return (TRUE);
12057 12062 }
12058 12063
12059 12064 static int
12060 12065 mptsas_init_pm(mptsas_t *mpt)
12061 12066 {
12062 12067 char pmc_name[16];
12063 12068 char *pmc[] = {
12064 12069 NULL,
12065 12070 "0=Off (PCI D3 State)",
12066 12071 "3=On (PCI D0 State)",
12067 12072 NULL
12068 12073 };
12069 12074 uint16_t pmcsr_stat;
12070 12075
12071 12076 if (mptsas_get_pci_cap(mpt) == FALSE) {
12072 12077 return (DDI_FAILURE);
12073 12078 }
12074 12079 /*
12075 12080 * If PCI's capability does not support PM, then don't need
12076 12081 * to registe the pm-components
12077 12082 */
12078 12083 if (!(mpt->m_options & MPTSAS_OPT_PM))
12079 12084 return (DDI_SUCCESS);
12080 12085 /*
12081 12086 * If power management is supported by this chip, create
12082 12087 * pm-components property for the power management framework
12083 12088 */
12084 12089 (void) sprintf(pmc_name, "NAME=mptsas%d", mpt->m_instance);
12085 12090 pmc[0] = pmc_name;
12086 12091 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, mpt->m_dip,
12087 12092 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) {
12088 12093 mpt->m_options &= ~MPTSAS_OPT_PM;
12089 12094 mptsas_log(mpt, CE_WARN,
12090 12095 "mptsas%d: pm-component property creation failed.",
12091 12096 mpt->m_instance);
12092 12097 return (DDI_FAILURE);
12093 12098 }
12094 12099
12095 12100 /*
12096 12101 * Power on device.
12097 12102 */
12098 12103 (void) pm_busy_component(mpt->m_dip, 0);
12099 12104 pmcsr_stat = pci_config_get16(mpt->m_config_handle,
12100 12105 mpt->m_pmcsr_offset);
12101 12106 if ((pmcsr_stat & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_D0) {
12102 12107 mptsas_log(mpt, CE_WARN, "mptsas%d: Power up the device",
12103 12108 mpt->m_instance);
12104 12109 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset,
12105 12110 PCI_PMCSR_D0);
12106 12111 }
12107 12112 if (pm_power_has_changed(mpt->m_dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) {
12108 12113 mptsas_log(mpt, CE_WARN, "pm_power_has_changed failed");
12109 12114 return (DDI_FAILURE);
12110 12115 }
12111 12116 mpt->m_power_level = PM_LEVEL_D0;
12112 12117 /*
12113 12118 * Set pm idle delay.
12114 12119 */
12115 12120 mpt->m_pm_idle_delay = ddi_prop_get_int(DDI_DEV_T_ANY,
12116 12121 mpt->m_dip, 0, "mptsas-pm-idle-delay", MPTSAS_PM_IDLE_TIMEOUT);
12117 12122
12118 12123 return (DDI_SUCCESS);
12119 12124 }
12120 12125
12121 12126 static int
12122 12127 mptsas_register_intrs(mptsas_t *mpt)
12123 12128 {
12124 12129 dev_info_t *dip;
12125 12130 int intr_types;
12126 12131
12127 12132 dip = mpt->m_dip;
12128 12133
12129 12134 /* Get supported interrupt types */
12130 12135 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) {
12131 12136 mptsas_log(mpt, CE_WARN, "ddi_intr_get_supported_types "
12132 12137 "failed\n");
12133 12138 return (FALSE);
12134 12139 }
12135 12140
12136 12141 NDBG6(("ddi_intr_get_supported_types() returned: 0x%x", intr_types));
12137 12142
12138 12143 /*
12139 12144 * Try MSI, but fall back to FIXED
12140 12145 */
12141 12146 if (mptsas_enable_msi && (intr_types & DDI_INTR_TYPE_MSI)) {
12142 12147 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_MSI) == DDI_SUCCESS) {
12143 12148 NDBG0(("Using MSI interrupt type"));
12144 12149 mpt->m_intr_type = DDI_INTR_TYPE_MSI;
12145 12150 return (TRUE);
12146 12151 }
12147 12152 }
12148 12153 if (intr_types & DDI_INTR_TYPE_FIXED) {
12149 12154 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_FIXED) == DDI_SUCCESS) {
12150 12155 NDBG0(("Using FIXED interrupt type"));
12151 12156 mpt->m_intr_type = DDI_INTR_TYPE_FIXED;
12152 12157 return (TRUE);
12153 12158 } else {
12154 12159 NDBG0(("FIXED interrupt registration failed"));
12155 12160 return (FALSE);
12156 12161 }
12157 12162 }
12158 12163
12159 12164 return (FALSE);
12160 12165 }
12161 12166
12162 12167 static void
12163 12168 mptsas_unregister_intrs(mptsas_t *mpt)
12164 12169 {
12165 12170 mptsas_rem_intrs(mpt);
12166 12171 }
12167 12172
12168 12173 /*
12169 12174 * mptsas_add_intrs:
12170 12175 *
12171 12176 * Register FIXED or MSI interrupts.
12172 12177 */
12173 12178 static int
12174 12179 mptsas_add_intrs(mptsas_t *mpt, int intr_type)
12175 12180 {
12176 12181 dev_info_t *dip = mpt->m_dip;
12177 12182 int avail, actual, count = 0;
12178 12183 int i, flag, ret;
12179 12184
12180 12185 NDBG6(("mptsas_add_intrs:interrupt type 0x%x", intr_type));
12181 12186
12182 12187 /* Get number of interrupts */
12183 12188 ret = ddi_intr_get_nintrs(dip, intr_type, &count);
12184 12189 if ((ret != DDI_SUCCESS) || (count <= 0)) {
12185 12190 mptsas_log(mpt, CE_WARN, "ddi_intr_get_nintrs() failed, "
12186 12191 "ret %d count %d\n", ret, count);
12187 12192
12188 12193 return (DDI_FAILURE);
12189 12194 }
12190 12195
12191 12196 /* Get number of available interrupts */
12192 12197 ret = ddi_intr_get_navail(dip, intr_type, &avail);
12193 12198 if ((ret != DDI_SUCCESS) || (avail == 0)) {
12194 12199 mptsas_log(mpt, CE_WARN, "ddi_intr_get_navail() failed, "
12195 12200 "ret %d avail %d\n", ret, avail);
12196 12201
12197 12202 return (DDI_FAILURE);
12198 12203 }
12199 12204
12200 12205 if (avail < count) {
12201 12206 mptsas_log(mpt, CE_NOTE, "ddi_intr_get_nvail returned %d, "
12202 12207 "navail() returned %d", count, avail);
12203 12208 }
12204 12209
12205 12210 /* Mpt only have one interrupt routine */
12206 12211 if ((intr_type == DDI_INTR_TYPE_MSI) && (count > 1)) {
12207 12212 count = 1;
12208 12213 }
12209 12214
12210 12215 /* Allocate an array of interrupt handles */
12211 12216 mpt->m_intr_size = count * sizeof (ddi_intr_handle_t);
12212 12217 mpt->m_htable = kmem_alloc(mpt->m_intr_size, KM_SLEEP);
12213 12218
12214 12219 flag = DDI_INTR_ALLOC_NORMAL;
12215 12220
12216 12221 /* call ddi_intr_alloc() */
12217 12222 ret = ddi_intr_alloc(dip, mpt->m_htable, intr_type, 0,
12218 12223 count, &actual, flag);
12219 12224
12220 12225 if ((ret != DDI_SUCCESS) || (actual == 0)) {
12221 12226 mptsas_log(mpt, CE_WARN, "ddi_intr_alloc() failed, ret %d\n",
12222 12227 ret);
12223 12228 kmem_free(mpt->m_htable, mpt->m_intr_size);
12224 12229 return (DDI_FAILURE);
12225 12230 }
12226 12231
12227 12232 /* use interrupt count returned or abort? */
12228 12233 if (actual < count) {
12229 12234 mptsas_log(mpt, CE_NOTE, "Requested: %d, Received: %d\n",
12230 12235 count, actual);
12231 12236 }
12232 12237
12233 12238 mpt->m_intr_cnt = actual;
12234 12239
12235 12240 /*
12236 12241 * Get priority for first msi, assume remaining are all the same
12237 12242 */
12238 12243 if ((ret = ddi_intr_get_pri(mpt->m_htable[0],
12239 12244 &mpt->m_intr_pri)) != DDI_SUCCESS) {
12240 12245 mptsas_log(mpt, CE_WARN, "ddi_intr_get_pri() failed %d\n", ret);
12241 12246
12242 12247 /* Free already allocated intr */
12243 12248 for (i = 0; i < actual; i++) {
12244 12249 (void) ddi_intr_free(mpt->m_htable[i]);
12245 12250 }
12246 12251
12247 12252 kmem_free(mpt->m_htable, mpt->m_intr_size);
12248 12253 return (DDI_FAILURE);
12249 12254 }
12250 12255
12251 12256 /* Test for high level mutex */
12252 12257 if (mpt->m_intr_pri >= ddi_intr_get_hilevel_pri()) {
12253 12258 mptsas_log(mpt, CE_WARN, "mptsas_add_intrs: "
12254 12259 "Hi level interrupt not supported\n");
12255 12260
12256 12261 /* Free already allocated intr */
12257 12262 for (i = 0; i < actual; i++) {
12258 12263 (void) ddi_intr_free(mpt->m_htable[i]);
12259 12264 }
12260 12265
12261 12266 kmem_free(mpt->m_htable, mpt->m_intr_size);
12262 12267 return (DDI_FAILURE);
12263 12268 }
12264 12269
12265 12270 /* Call ddi_intr_add_handler() */
12266 12271 for (i = 0; i < actual; i++) {
12267 12272 if ((ret = ddi_intr_add_handler(mpt->m_htable[i], mptsas_intr,
12268 12273 (caddr_t)mpt, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) {
12269 12274 mptsas_log(mpt, CE_WARN, "ddi_intr_add_handler() "
12270 12275 "failed %d\n", ret);
12271 12276
12272 12277 /* Free already allocated intr */
12273 12278 for (i = 0; i < actual; i++) {
12274 12279 (void) ddi_intr_free(mpt->m_htable[i]);
12275 12280 }
12276 12281
12277 12282 kmem_free(mpt->m_htable, mpt->m_intr_size);
12278 12283 return (DDI_FAILURE);
12279 12284 }
12280 12285 }
12281 12286
12282 12287 if ((ret = ddi_intr_get_cap(mpt->m_htable[0], &mpt->m_intr_cap))
12283 12288 != DDI_SUCCESS) {
12284 12289 mptsas_log(mpt, CE_WARN, "ddi_intr_get_cap() failed %d\n", ret);
12285 12290
12286 12291 /* Free already allocated intr */
12287 12292 for (i = 0; i < actual; i++) {
12288 12293 (void) ddi_intr_free(mpt->m_htable[i]);
12289 12294 }
12290 12295
12291 12296 kmem_free(mpt->m_htable, mpt->m_intr_size);
12292 12297 return (DDI_FAILURE);
12293 12298 }
12294 12299
12295 12300 /*
12296 12301 * Enable interrupts
12297 12302 */
12298 12303 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) {
12299 12304 /* Call ddi_intr_block_enable() for MSI interrupts */
12300 12305 (void) ddi_intr_block_enable(mpt->m_htable, mpt->m_intr_cnt);
12301 12306 } else {
12302 12307 /* Call ddi_intr_enable for MSI or FIXED interrupts */
12303 12308 for (i = 0; i < mpt->m_intr_cnt; i++) {
12304 12309 (void) ddi_intr_enable(mpt->m_htable[i]);
12305 12310 }
12306 12311 }
12307 12312 return (DDI_SUCCESS);
12308 12313 }
12309 12314
12310 12315 /*
12311 12316 * mptsas_rem_intrs:
12312 12317 *
12313 12318 * Unregister FIXED or MSI interrupts
12314 12319 */
12315 12320 static void
12316 12321 mptsas_rem_intrs(mptsas_t *mpt)
12317 12322 {
12318 12323 int i;
12319 12324
12320 12325 NDBG6(("mptsas_rem_intrs"));
12321 12326
12322 12327 /* Disable all interrupts */
12323 12328 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) {
12324 12329 /* Call ddi_intr_block_disable() */
12325 12330 (void) ddi_intr_block_disable(mpt->m_htable, mpt->m_intr_cnt);
12326 12331 } else {
12327 12332 for (i = 0; i < mpt->m_intr_cnt; i++) {
12328 12333 (void) ddi_intr_disable(mpt->m_htable[i]);
12329 12334 }
12330 12335 }
12331 12336
12332 12337 /* Call ddi_intr_remove_handler() */
12333 12338 for (i = 0; i < mpt->m_intr_cnt; i++) {
12334 12339 (void) ddi_intr_remove_handler(mpt->m_htable[i]);
12335 12340 (void) ddi_intr_free(mpt->m_htable[i]);
12336 12341 }
12337 12342
12338 12343 kmem_free(mpt->m_htable, mpt->m_intr_size);
12339 12344 }
12340 12345
12341 12346 /*
12342 12347 * The IO fault service error handling callback function
12343 12348 */
12344 12349 /*ARGSUSED*/
12345 12350 static int
12346 12351 mptsas_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
12347 12352 {
12348 12353 /*
12349 12354 * as the driver can always deal with an error in any dma or
12350 12355 * access handle, we can just return the fme_status value.
12351 12356 */
12352 12357 pci_ereport_post(dip, err, NULL);
12353 12358 return (err->fme_status);
12354 12359 }
12355 12360
12356 12361 /*
12357 12362 * mptsas_fm_init - initialize fma capabilities and register with IO
12358 12363 * fault services.
12359 12364 */
12360 12365 static void
12361 12366 mptsas_fm_init(mptsas_t *mpt)
12362 12367 {
12363 12368 /*
12364 12369 * Need to change iblock to priority for new MSI intr
12365 12370 */
12366 12371 ddi_iblock_cookie_t fm_ibc;
12367 12372
12368 12373 /* Only register with IO Fault Services if we have some capability */
12369 12374 if (mpt->m_fm_capabilities) {
12370 12375 /* Adjust access and dma attributes for FMA */
12371 12376 mpt->m_reg_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC;
12372 12377 mpt->m_msg_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
12373 12378 mpt->m_io_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
12374 12379
12375 12380 /*
12376 12381 * Register capabilities with IO Fault Services.
12377 12382 * mpt->m_fm_capabilities will be updated to indicate
12378 12383 * capabilities actually supported (not requested.)
12379 12384 */
12380 12385 ddi_fm_init(mpt->m_dip, &mpt->m_fm_capabilities, &fm_ibc);
12381 12386
12382 12387 /*
12383 12388 * Initialize pci ereport capabilities if ereport
12384 12389 * capable (should always be.)
12385 12390 */
12386 12391 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) ||
12387 12392 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
12388 12393 pci_ereport_setup(mpt->m_dip);
12389 12394 }
12390 12395
12391 12396 /*
12392 12397 * Register error callback if error callback capable.
12393 12398 */
12394 12399 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
12395 12400 ddi_fm_handler_register(mpt->m_dip,
12396 12401 mptsas_fm_error_cb, (void *) mpt);
12397 12402 }
12398 12403 }
12399 12404 }
12400 12405
12401 12406 /*
12402 12407 * mptsas_fm_fini - Releases fma capabilities and un-registers with IO
12403 12408 * fault services.
12404 12409 *
12405 12410 */
12406 12411 static void
12407 12412 mptsas_fm_fini(mptsas_t *mpt)
12408 12413 {
12409 12414 /* Only unregister FMA capabilities if registered */
12410 12415 if (mpt->m_fm_capabilities) {
12411 12416
12412 12417 /*
12413 12418 * Un-register error callback if error callback capable.
12414 12419 */
12415 12420
12416 12421 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
12417 12422 ddi_fm_handler_unregister(mpt->m_dip);
12418 12423 }
12419 12424
12420 12425 /*
12421 12426 * Release any resources allocated by pci_ereport_setup()
12422 12427 */
12423 12428
12424 12429 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) ||
12425 12430 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
12426 12431 pci_ereport_teardown(mpt->m_dip);
12427 12432 }
12428 12433
12429 12434 /* Unregister from IO Fault Services */
12430 12435 ddi_fm_fini(mpt->m_dip);
12431 12436
12432 12437 /* Adjust access and dma attributes for FMA */
12433 12438 mpt->m_reg_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC;
12434 12439 mpt->m_msg_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
12435 12440 mpt->m_io_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
12436 12441
12437 12442 }
12438 12443 }
12439 12444
12440 12445 int
12441 12446 mptsas_check_acc_handle(ddi_acc_handle_t handle)
12442 12447 {
12443 12448 ddi_fm_error_t de;
12444 12449
12445 12450 if (handle == NULL)
12446 12451 return (DDI_FAILURE);
12447 12452 ddi_fm_acc_err_get(handle, &de, DDI_FME_VER0);
12448 12453 return (de.fme_status);
12449 12454 }
12450 12455
12451 12456 int
12452 12457 mptsas_check_dma_handle(ddi_dma_handle_t handle)
12453 12458 {
12454 12459 ddi_fm_error_t de;
12455 12460
12456 12461 if (handle == NULL)
12457 12462 return (DDI_FAILURE);
12458 12463 ddi_fm_dma_err_get(handle, &de, DDI_FME_VER0);
12459 12464 return (de.fme_status);
12460 12465 }
12461 12466
12462 12467 void
12463 12468 mptsas_fm_ereport(mptsas_t *mpt, char *detail)
12464 12469 {
12465 12470 uint64_t ena;
12466 12471 char buf[FM_MAX_CLASS];
12467 12472
12468 12473 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
12469 12474 ena = fm_ena_generate(0, FM_ENA_FMT1);
12470 12475 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities)) {
12471 12476 ddi_fm_ereport_post(mpt->m_dip, buf, ena, DDI_NOSLEEP,
12472 12477 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL);
12473 12478 }
12474 12479 }
12475 12480
12476 12481 static int
12477 12482 mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address,
12478 12483 uint16_t *dev_handle, mptsas_target_t **pptgt)
12479 12484 {
12480 12485 int rval;
12481 12486 uint32_t dev_info;
12482 12487 uint64_t sas_wwn;
12483 12488 mptsas_phymask_t phymask;
12484 12489 uint8_t physport, phynum, config, disk;
12485 12490 mptsas_slots_t *slots = mpt->m_active;
12486 12491 uint64_t devicename;
12487 12492 uint16_t pdev_hdl;
12488 12493 mptsas_target_t *tmp_tgt = NULL;
12489 12494 uint16_t bay_num, enclosure;
12490 12495
12491 12496 ASSERT(*pptgt == NULL);
12492 12497
12493 12498 rval = mptsas_get_sas_device_page0(mpt, page_address, dev_handle,
12494 12499 &sas_wwn, &dev_info, &physport, &phynum, &pdev_hdl,
12495 12500 &bay_num, &enclosure);
12496 12501 if (rval != DDI_SUCCESS) {
12497 12502 rval = DEV_INFO_FAIL_PAGE0;
12498 12503 return (rval);
12499 12504 }
12500 12505
12501 12506 if ((dev_info & (MPI2_SAS_DEVICE_INFO_SSP_TARGET |
12502 12507 MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
12503 12508 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) == NULL) {
12504 12509 rval = DEV_INFO_WRONG_DEVICE_TYPE;
12505 12510 return (rval);
12506 12511 }
12507 12512
12508 12513 /*
12509 12514 * Check if the dev handle is for a Phys Disk. If so, set return value
12510 12515 * and exit. Don't add Phys Disks to hash.
12511 12516 */
12512 12517 for (config = 0; config < slots->m_num_raid_configs; config++) {
12513 12518 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) {
12514 12519 if (*dev_handle == slots->m_raidconfig[config].
12515 12520 m_physdisk_devhdl[disk]) {
12516 12521 rval = DEV_INFO_PHYS_DISK;
12517 12522 return (rval);
12518 12523 }
12519 12524 }
12520 12525 }
12521 12526
12522 12527 /*
12523 12528 * Get SATA Device Name from SAS device page0 for
12524 12529 * sata device, if device name doesn't exist, set m_sas_wwn to
12525 12530 * 0 for direct attached SATA. For the device behind the expander
12526 12531 * we still can use STP address assigned by expander.
12527 12532 */
12528 12533 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
12529 12534 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
12530 12535 mutex_exit(&mpt->m_mutex);
12531 12536 /* alloc a tmp_tgt to send the cmd */
12532 12537 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target),
12533 12538 KM_SLEEP);
12534 12539 tmp_tgt->m_devhdl = *dev_handle;
12535 12540 tmp_tgt->m_deviceinfo = dev_info;
12536 12541 tmp_tgt->m_qfull_retries = QFULL_RETRIES;
12537 12542 tmp_tgt->m_qfull_retry_interval =
12538 12543 drv_usectohz(QFULL_RETRY_INTERVAL * 1000);
12539 12544 tmp_tgt->m_t_throttle = MAX_THROTTLE;
12540 12545 devicename = mptsas_get_sata_guid(mpt, tmp_tgt, 0);
12541 12546 kmem_free(tmp_tgt, sizeof (struct mptsas_target));
12542 12547 mutex_enter(&mpt->m_mutex);
12543 12548 if (devicename != 0 && (((devicename >> 56) & 0xf0) == 0x50)) {
12544 12549 sas_wwn = devicename;
12545 12550 } else if (dev_info & MPI2_SAS_DEVICE_INFO_DIRECT_ATTACH) {
12546 12551 sas_wwn = 0;
12547 12552 }
12548 12553 }
12549 12554
12550 12555 phymask = mptsas_physport_to_phymask(mpt, physport);
12551 12556 *pptgt = mptsas_tgt_alloc(&slots->m_tgttbl, *dev_handle, sas_wwn,
12552 12557 dev_info, phymask, phynum);
12553 12558 if (*pptgt == NULL) {
12554 12559 mptsas_log(mpt, CE_WARN, "Failed to allocated target"
12555 12560 "structure!");
12556 12561 rval = DEV_INFO_FAIL_ALLOC;
12557 12562 return (rval);
12558 12563 }
12559 12564 (*pptgt)->m_enclosure = enclosure;
12560 12565 (*pptgt)->m_slot_num = bay_num;
12561 12566 return (DEV_INFO_SUCCESS);
12562 12567 }
12563 12568
12564 12569 uint64_t
12565 12570 mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun)
12566 12571 {
12567 12572 uint64_t sata_guid = 0, *pwwn = NULL;
12568 12573 int target = ptgt->m_devhdl;
12569 12574 uchar_t *inq83 = NULL;
12570 12575 int inq83_len = 0xFF;
12571 12576 uchar_t *dblk = NULL;
12572 12577 int inq83_retry = 3;
12573 12578 int rval = DDI_FAILURE;
12574 12579
12575 12580 inq83 = kmem_zalloc(inq83_len, KM_SLEEP);
12576 12581
12577 12582 inq83_retry:
12578 12583 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83,
12579 12584 inq83_len, NULL, 1);
12580 12585 if (rval != DDI_SUCCESS) {
12581 12586 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
12582 12587 "0x83 for target:%x, lun:%x failed!", target, lun);
12583 12588 goto out;
12584 12589 }
12585 12590 /* According to SAT2, the first descriptor is logic unit name */
12586 12591 dblk = &inq83[4];
12587 12592 if ((dblk[1] & 0x30) != 0) {
12588 12593 mptsas_log(mpt, CE_WARN, "!Descriptor is not lun associated.");
12589 12594 goto out;
12590 12595 }
12591 12596 pwwn = (uint64_t *)(void *)(&dblk[4]);
12592 12597 if ((dblk[4] & 0xf0) == 0x50) {
12593 12598 sata_guid = BE_64(*pwwn);
12594 12599 goto out;
12595 12600 } else if (dblk[4] == 'A') {
12596 12601 NDBG20(("SATA drive has no NAA format GUID."));
12597 12602 goto out;
12598 12603 } else {
12599 12604 /* The data is not ready, wait and retry */
12600 12605 inq83_retry--;
12601 12606 if (inq83_retry <= 0) {
12602 12607 goto out;
12603 12608 }
12604 12609 NDBG20(("The GUID is not ready, retry..."));
12605 12610 delay(1 * drv_usectohz(1000000));
12606 12611 goto inq83_retry;
12607 12612 }
12608 12613 out:
12609 12614 kmem_free(inq83, inq83_len);
12610 12615 return (sata_guid);
12611 12616 }
12612 12617
12613 12618 static int
12614 12619 mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, uchar_t page,
12615 12620 unsigned char *buf, int len, int *reallen, uchar_t evpd)
12616 12621 {
12617 12622 uchar_t cdb[CDB_GROUP0];
12618 12623 struct scsi_address ap;
12619 12624 struct buf *data_bp = NULL;
12620 12625 int resid = 0;
12621 12626 int ret = DDI_FAILURE;
12622 12627
12623 12628 ASSERT(len <= 0xffff);
12624 12629
12625 12630 ap.a_target = MPTSAS_INVALID_DEVHDL;
12626 12631 ap.a_lun = (uchar_t)(lun);
12627 12632 ap.a_hba_tran = mpt->m_tran;
12628 12633
12629 12634 data_bp = scsi_alloc_consistent_buf(&ap,
12630 12635 (struct buf *)NULL, len, B_READ, NULL_FUNC, NULL);
12631 12636 if (data_bp == NULL) {
12632 12637 return (ret);
12633 12638 }
12634 12639 bzero(cdb, CDB_GROUP0);
12635 12640 cdb[0] = SCMD_INQUIRY;
12636 12641 cdb[1] = evpd;
12637 12642 cdb[2] = page;
12638 12643 cdb[3] = (len & 0xff00) >> 8;
12639 12644 cdb[4] = (len & 0x00ff);
12640 12645 cdb[5] = 0;
12641 12646
12642 12647 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP0, data_bp,
12643 12648 &resid);
12644 12649 if (ret == DDI_SUCCESS) {
12645 12650 if (reallen) {
12646 12651 *reallen = len - resid;
12647 12652 }
12648 12653 bcopy((caddr_t)data_bp->b_un.b_addr, buf, len);
12649 12654 }
12650 12655 if (data_bp) {
12651 12656 scsi_free_consistent_buf(data_bp);
12652 12657 }
12653 12658 return (ret);
12654 12659 }
12655 12660
12656 12661 static int
12657 12662 mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap,
12658 12663 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp,
12659 12664 int *resid)
12660 12665 {
12661 12666 struct scsi_pkt *pktp = NULL;
12662 12667 scsi_hba_tran_t *tran_clone = NULL;
12663 12668 mptsas_tgt_private_t *tgt_private = NULL;
12664 12669 int ret = DDI_FAILURE;
12665 12670
12666 12671 /*
12667 12672 * scsi_hba_tran_t->tran_tgt_private is used to pass the address
12668 12673 * information to scsi_init_pkt, allocate a scsi_hba_tran structure
12669 12674 * to simulate the cmds from sd
12670 12675 */
12671 12676 tran_clone = kmem_alloc(
12672 12677 sizeof (scsi_hba_tran_t), KM_SLEEP);
12673 12678 if (tran_clone == NULL) {
12674 12679 goto out;
12675 12680 }
12676 12681 bcopy((caddr_t)mpt->m_tran,
12677 12682 (caddr_t)tran_clone, sizeof (scsi_hba_tran_t));
12678 12683 tgt_private = kmem_alloc(
12679 12684 sizeof (mptsas_tgt_private_t), KM_SLEEP);
12680 12685 if (tgt_private == NULL) {
12681 12686 goto out;
12682 12687 }
12683 12688 tgt_private->t_lun = ap->a_lun;
12684 12689 tgt_private->t_private = ptgt;
12685 12690 tran_clone->tran_tgt_private = tgt_private;
12686 12691 ap->a_hba_tran = tran_clone;
12687 12692
12688 12693 pktp = scsi_init_pkt(ap, (struct scsi_pkt *)NULL,
12689 12694 data_bp, cdblen, sizeof (struct scsi_arq_status),
12690 12695 0, PKT_CONSISTENT, NULL, NULL);
12691 12696 if (pktp == NULL) {
12692 12697 goto out;
12693 12698 }
12694 12699 bcopy(cdb, pktp->pkt_cdbp, cdblen);
12695 12700 pktp->pkt_flags = FLAG_NOPARITY;
12696 12701 if (scsi_poll(pktp) < 0) {
12697 12702 goto out;
12698 12703 }
12699 12704 if (((struct scsi_status *)pktp->pkt_scbp)->sts_chk) {
12700 12705 goto out;
12701 12706 }
12702 12707 if (resid != NULL) {
12703 12708 *resid = pktp->pkt_resid;
12704 12709 }
12705 12710
12706 12711 ret = DDI_SUCCESS;
12707 12712 out:
12708 12713 if (pktp) {
12709 12714 scsi_destroy_pkt(pktp);
12710 12715 }
12711 12716 if (tran_clone) {
12712 12717 kmem_free(tran_clone, sizeof (scsi_hba_tran_t));
12713 12718 }
12714 12719 if (tgt_private) {
12715 12720 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t));
12716 12721 }
12717 12722 return (ret);
12718 12723 }
12719 12724 static int
12720 12725 mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, int *lun)
12721 12726 {
12722 12727 char *cp = NULL;
12723 12728 char *ptr = NULL;
12724 12729 size_t s = 0;
12725 12730 char *wwid_str = NULL;
12726 12731 char *lun_str = NULL;
12727 12732 long lunnum;
12728 12733 long phyid = -1;
12729 12734 int rc = DDI_FAILURE;
12730 12735
12731 12736 ptr = name;
12732 12737 ASSERT(ptr[0] == 'w' || ptr[0] == 'p');
12733 12738 ptr++;
12734 12739 if ((cp = strchr(ptr, ',')) == NULL) {
12735 12740 return (DDI_FAILURE);
12736 12741 }
12737 12742
12738 12743 wwid_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
12739 12744 s = (uintptr_t)cp - (uintptr_t)ptr;
12740 12745
12741 12746 bcopy(ptr, wwid_str, s);
12742 12747 wwid_str[s] = '\0';
12743 12748
12744 12749 ptr = ++cp;
12745 12750
12746 12751 if ((cp = strchr(ptr, '\0')) == NULL) {
12747 12752 goto out;
12748 12753 }
12749 12754 lun_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
12750 12755 s = (uintptr_t)cp - (uintptr_t)ptr;
12751 12756
12752 12757 bcopy(ptr, lun_str, s);
12753 12758 lun_str[s] = '\0';
12754 12759
12755 12760 if (name[0] == 'p') {
12756 12761 rc = ddi_strtol(wwid_str, NULL, 0x10, &phyid);
12757 12762 } else {
12758 12763 rc = scsi_wwnstr_to_wwn(wwid_str, wwid);
12759 12764 }
12760 12765 if (rc != DDI_SUCCESS)
12761 12766 goto out;
12762 12767
12763 12768 if (phyid != -1) {
12764 12769 ASSERT(phyid < MPTSAS_MAX_PHYS);
12765 12770 *phy = (uint8_t)phyid;
12766 12771 }
12767 12772 rc = ddi_strtol(lun_str, NULL, 0x10, &lunnum);
12768 12773 if (rc != 0)
12769 12774 goto out;
12770 12775
12771 12776 *lun = (int)lunnum;
12772 12777 rc = DDI_SUCCESS;
12773 12778 out:
12774 12779 if (wwid_str)
12775 12780 kmem_free(wwid_str, SCSI_MAXNAMELEN);
12776 12781 if (lun_str)
12777 12782 kmem_free(lun_str, SCSI_MAXNAMELEN);
12778 12783
12779 12784 return (rc);
12780 12785 }
12781 12786
12782 12787 /*
12783 12788 * mptsas_parse_smp_name() is to parse sas wwn string
12784 12789 * which format is "wWWN"
12785 12790 */
12786 12791 static int
12787 12792 mptsas_parse_smp_name(char *name, uint64_t *wwn)
12788 12793 {
12789 12794 char *ptr = name;
12790 12795
12791 12796 if (*ptr != 'w') {
12792 12797 return (DDI_FAILURE);
12793 12798 }
12794 12799
12795 12800 ptr++;
12796 12801 if (scsi_wwnstr_to_wwn(ptr, wwn)) {
12797 12802 return (DDI_FAILURE);
12798 12803 }
12799 12804 return (DDI_SUCCESS);
12800 12805 }
12801 12806
12802 12807 static int
12803 12808 mptsas_bus_config(dev_info_t *pdip, uint_t flag,
12804 12809 ddi_bus_config_op_t op, void *arg, dev_info_t **childp)
12805 12810 {
12806 12811 int ret = NDI_FAILURE;
12807 12812 int circ = 0;
12808 12813 int circ1 = 0;
12809 12814 mptsas_t *mpt;
12810 12815 char *ptr = NULL;
12811 12816 char *devnm = NULL;
12812 12817 uint64_t wwid = 0;
12813 12818 uint8_t phy = 0xFF;
12814 12819 int lun = 0;
12815 12820 uint_t mflags = flag;
12816 12821 int bconfig = TRUE;
12817 12822
12818 12823 if (scsi_hba_iport_unit_address(pdip) == 0) {
12819 12824 return (DDI_FAILURE);
12820 12825 }
12821 12826
12822 12827 mpt = DIP2MPT(pdip);
12823 12828 if (!mpt) {
12824 12829 return (DDI_FAILURE);
12825 12830 }
12826 12831 /*
12827 12832 * Hold the nexus across the bus_config
12828 12833 */
12829 12834 ndi_devi_enter(scsi_vhci_dip, &circ);
12830 12835 ndi_devi_enter(pdip, &circ1);
12831 12836 switch (op) {
12832 12837 case BUS_CONFIG_ONE:
12833 12838 /* parse wwid/target name out of name given */
12834 12839 if ((ptr = strchr((char *)arg, '@')) == NULL) {
12835 12840 ret = NDI_FAILURE;
12836 12841 break;
12837 12842 }
12838 12843 ptr++;
12839 12844 if (strncmp((char *)arg, "smp", 3) == 0) {
12840 12845 /*
12841 12846 * This is a SMP target device
12842 12847 */
12843 12848 ret = mptsas_parse_smp_name(ptr, &wwid);
12844 12849 if (ret != DDI_SUCCESS) {
12845 12850 ret = NDI_FAILURE;
12846 12851 break;
12847 12852 }
12848 12853 ret = mptsas_config_smp(pdip, wwid, childp);
12849 12854 } else if ((ptr[0] == 'w') || (ptr[0] == 'p')) {
12850 12855 /*
12851 12856 * OBP could pass down a non-canonical form
12852 12857 * bootpath without LUN part when LUN is 0.
12853 12858 * So driver need adjust the string.
12854 12859 */
12855 12860 if (strchr(ptr, ',') == NULL) {
12856 12861 devnm = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
12857 12862 (void) sprintf(devnm, "%s,0", (char *)arg);
12858 12863 ptr = strchr(devnm, '@');
12859 12864 ptr++;
12860 12865 }
12861 12866
12862 12867 /*
12863 12868 * The device path is wWWID format and the device
12864 12869 * is not SMP target device.
12865 12870 */
12866 12871 ret = mptsas_parse_address(ptr, &wwid, &phy, &lun);
12867 12872 if (ret != DDI_SUCCESS) {
12868 12873 ret = NDI_FAILURE;
12869 12874 break;
12870 12875 }
12871 12876 *childp = NULL;
12872 12877 if (ptr[0] == 'w') {
12873 12878 ret = mptsas_config_one_addr(pdip, wwid,
12874 12879 lun, childp);
12875 12880 } else if (ptr[0] == 'p') {
12876 12881 ret = mptsas_config_one_phy(pdip, phy, lun,
12877 12882 childp);
12878 12883 }
12879 12884
12880 12885 /*
12881 12886 * If this is CD/DVD device in OBP path, the
12882 12887 * ndi_busop_bus_config can be skipped as config one
12883 12888 * operation is done above.
12884 12889 */
12885 12890 if ((ret == NDI_SUCCESS) && (*childp != NULL) &&
12886 12891 (strcmp(ddi_node_name(*childp), "cdrom") == 0) &&
12887 12892 (strncmp((char *)arg, "disk", 4) == 0)) {
12888 12893 bconfig = FALSE;
12889 12894 ndi_hold_devi(*childp);
12890 12895 }
12891 12896 } else {
12892 12897 ret = NDI_FAILURE;
12893 12898 break;
12894 12899 }
12895 12900
12896 12901 /*
12897 12902 * DDI group instructed us to use this flag.
12898 12903 */
12899 12904 mflags |= NDI_MDI_FALLBACK;
12900 12905 break;
12901 12906 case BUS_CONFIG_DRIVER:
12902 12907 case BUS_CONFIG_ALL:
12903 12908 mptsas_config_all(pdip);
12904 12909 ret = NDI_SUCCESS;
12905 12910 break;
12906 12911 }
12907 12912
12908 12913 if ((ret == NDI_SUCCESS) && bconfig) {
12909 12914 ret = ndi_busop_bus_config(pdip, mflags, op,
12910 12915 (devnm == NULL) ? arg : devnm, childp, 0);
12911 12916 }
12912 12917
12913 12918 ndi_devi_exit(pdip, circ1);
12914 12919 ndi_devi_exit(scsi_vhci_dip, circ);
12915 12920 if (devnm != NULL)
12916 12921 kmem_free(devnm, SCSI_MAXNAMELEN);
12917 12922 return (ret);
12918 12923 }
12919 12924
12920 12925 static int
12921 12926 mptsas_probe_lun(dev_info_t *pdip, int lun, dev_info_t **dip,
12922 12927 mptsas_target_t *ptgt)
12923 12928 {
12924 12929 int rval = DDI_FAILURE;
12925 12930 struct scsi_inquiry *sd_inq = NULL;
12926 12931 mptsas_t *mpt = DIP2MPT(pdip);
12927 12932
12928 12933 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP);
12929 12934
12930 12935 rval = mptsas_inquiry(mpt, ptgt, lun, 0, (uchar_t *)sd_inq,
12931 12936 SUN_INQSIZE, 0, (uchar_t)0);
12932 12937
12933 12938 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) {
12934 12939 rval = mptsas_create_lun(pdip, sd_inq, dip, ptgt, lun);
12935 12940 } else {
12936 12941 rval = DDI_FAILURE;
12937 12942 }
12938 12943
12939 12944 kmem_free(sd_inq, SUN_INQSIZE);
12940 12945 return (rval);
12941 12946 }
12942 12947
12943 12948 static int
12944 12949 mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun,
12945 12950 dev_info_t **lundip)
12946 12951 {
12947 12952 int rval;
12948 12953 mptsas_t *mpt = DIP2MPT(pdip);
12949 12954 int phymask;
12950 12955 mptsas_target_t *ptgt = NULL;
12951 12956
12952 12957 /*
12953 12958 * Get the physical port associated to the iport
12954 12959 */
12955 12960 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
12956 12961 "phymask", 0);
12957 12962
12958 12963 ptgt = mptsas_wwid_to_ptgt(mpt, phymask, sasaddr);
12959 12964 if (ptgt == NULL) {
12960 12965 /*
12961 12966 * didn't match any device by searching
12962 12967 */
12963 12968 return (DDI_FAILURE);
12964 12969 }
12965 12970 /*
12966 12971 * If the LUN already exists and the status is online,
12967 12972 * we just return the pointer to dev_info_t directly.
12968 12973 * For the mdi_pathinfo node, we'll handle it in
12969 12974 * mptsas_create_virt_lun()
12970 12975 * TODO should be also in mptsas_handle_dr
12971 12976 */
12972 12977
12973 12978 *lundip = mptsas_find_child_addr(pdip, sasaddr, lun);
12974 12979 if (*lundip != NULL) {
12975 12980 /*
12976 12981 * TODO Another senario is, we hotplug the same disk
12977 12982 * on the same slot, the devhdl changed, is this
12978 12983 * possible?
12979 12984 * tgt_private->t_private != ptgt
12980 12985 */
12981 12986 if (sasaddr != ptgt->m_sas_wwn) {
12982 12987 /*
12983 12988 * The device has changed although the devhdl is the
12984 12989 * same (Enclosure mapping mode, change drive on the
12985 12990 * same slot)
12986 12991 */
12987 12992 return (DDI_FAILURE);
12988 12993 }
12989 12994 return (DDI_SUCCESS);
12990 12995 }
12991 12996
12992 12997 if (phymask == 0) {
12993 12998 /*
12994 12999 * Configure IR volume
12995 13000 */
12996 13001 rval = mptsas_config_raid(pdip, ptgt->m_devhdl, lundip);
12997 13002 return (rval);
12998 13003 }
12999 13004 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt);
13000 13005
13001 13006 return (rval);
13002 13007 }
13003 13008
13004 13009 static int
13005 13010 mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun,
13006 13011 dev_info_t **lundip)
13007 13012 {
13008 13013 int rval;
13009 13014 mptsas_t *mpt = DIP2MPT(pdip);
13010 13015 int phymask;
13011 13016 mptsas_target_t *ptgt = NULL;
13012 13017
13013 13018 /*
13014 13019 * Get the physical port associated to the iport
13015 13020 */
13016 13021 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
13017 13022 "phymask", 0);
13018 13023
13019 13024 ptgt = mptsas_phy_to_tgt(mpt, phymask, phy);
13020 13025 if (ptgt == NULL) {
13021 13026 /*
13022 13027 * didn't match any device by searching
13023 13028 */
13024 13029 return (DDI_FAILURE);
13025 13030 }
13026 13031
13027 13032 /*
13028 13033 * If the LUN already exists and the status is online,
13029 13034 * we just return the pointer to dev_info_t directly.
13030 13035 * For the mdi_pathinfo node, we'll handle it in
13031 13036 * mptsas_create_virt_lun().
13032 13037 */
13033 13038
13034 13039 *lundip = mptsas_find_child_phy(pdip, phy);
13035 13040 if (*lundip != NULL) {
13036 13041 return (DDI_SUCCESS);
13037 13042 }
13038 13043
13039 13044 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt);
13040 13045
13041 13046 return (rval);
13042 13047 }
13043 13048
13044 13049 static int
13045 13050 mptsas_retrieve_lundata(int lun_cnt, uint8_t *buf, uint16_t *lun_num,
13046 13051 uint8_t *lun_addr_type)
13047 13052 {
13048 13053 uint32_t lun_idx = 0;
13049 13054
13050 13055 ASSERT(lun_num != NULL);
13051 13056 ASSERT(lun_addr_type != NULL);
13052 13057
13053 13058 lun_idx = (lun_cnt + 1) * MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE;
13054 13059 /* determine report luns addressing type */
13055 13060 switch (buf[lun_idx] & MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) {
13056 13061 /*
13057 13062 * Vendors in the field have been found to be concatenating
13058 13063 * bus/target/lun to equal the complete lun value instead
13059 13064 * of switching to flat space addressing
13060 13065 */
13061 13066 /* 00b - peripheral device addressing method */
13062 13067 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL:
13063 13068 /* FALLTHRU */
13064 13069 /* 10b - logical unit addressing method */
13065 13070 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT:
13066 13071 /* FALLTHRU */
13067 13072 /* 01b - flat space addressing method */
13068 13073 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE:
13069 13074 /* byte0 bit0-5=msb lun byte1 bit0-7=lsb lun */
13070 13075 *lun_addr_type = (buf[lun_idx] &
13071 13076 MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) >> 6;
13072 13077 *lun_num = (buf[lun_idx] & 0x3F) << 8;
13073 13078 *lun_num |= buf[lun_idx + 1];
13074 13079 return (DDI_SUCCESS);
13075 13080 default:
13076 13081 return (DDI_FAILURE);
13077 13082 }
13078 13083 }
13079 13084
13080 13085 static int
13081 13086 mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt)
13082 13087 {
13083 13088 struct buf *repluns_bp = NULL;
13084 13089 struct scsi_address ap;
13085 13090 uchar_t cdb[CDB_GROUP5];
13086 13091 int ret = DDI_FAILURE;
13087 13092 int retry = 0;
13088 13093 int lun_list_len = 0;
13089 13094 uint16_t lun_num = 0;
13090 13095 uint8_t lun_addr_type = 0;
13091 13096 uint32_t lun_cnt = 0;
13092 13097 uint32_t lun_total = 0;
13093 13098 dev_info_t *cdip = NULL;
13094 13099 uint16_t *saved_repluns = NULL;
13095 13100 char *buffer = NULL;
13096 13101 int buf_len = 128;
13097 13102 mptsas_t *mpt = DIP2MPT(pdip);
13098 13103 uint64_t sas_wwn = 0;
13099 13104 uint8_t phy = 0xFF;
13100 13105 uint32_t dev_info = 0;
13101 13106
13102 13107 mutex_enter(&mpt->m_mutex);
13103 13108 sas_wwn = ptgt->m_sas_wwn;
13104 13109 phy = ptgt->m_phynum;
13105 13110 dev_info = ptgt->m_deviceinfo;
13106 13111 mutex_exit(&mpt->m_mutex);
13107 13112
13108 13113 if (sas_wwn == 0) {
13109 13114 /*
13110 13115 * It's a SATA without Device Name
13111 13116 * So don't try multi-LUNs
13112 13117 */
13113 13118 if (mptsas_find_child_phy(pdip, phy)) {
13114 13119 return (DDI_SUCCESS);
13115 13120 } else {
13116 13121 /*
13117 13122 * need configure and create node
13118 13123 */
13119 13124 return (DDI_FAILURE);
13120 13125 }
13121 13126 }
13122 13127
13123 13128 /*
13124 13129 * WWN (SAS address or Device Name exist)
13125 13130 */
13126 13131 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
13127 13132 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
13128 13133 /*
13129 13134 * SATA device with Device Name
13130 13135 * So don't try multi-LUNs
13131 13136 */
13132 13137 if (mptsas_find_child_addr(pdip, sas_wwn, 0)) {
13133 13138 return (DDI_SUCCESS);
13134 13139 } else {
13135 13140 return (DDI_FAILURE);
13136 13141 }
13137 13142 }
13138 13143
13139 13144 do {
13140 13145 ap.a_target = MPTSAS_INVALID_DEVHDL;
13141 13146 ap.a_lun = 0;
13142 13147 ap.a_hba_tran = mpt->m_tran;
13143 13148 repluns_bp = scsi_alloc_consistent_buf(&ap,
13144 13149 (struct buf *)NULL, buf_len, B_READ, NULL_FUNC, NULL);
13145 13150 if (repluns_bp == NULL) {
13146 13151 retry++;
13147 13152 continue;
13148 13153 }
13149 13154 bzero(cdb, CDB_GROUP5);
13150 13155 cdb[0] = SCMD_REPORT_LUNS;
13151 13156 cdb[6] = (buf_len & 0xff000000) >> 24;
13152 13157 cdb[7] = (buf_len & 0x00ff0000) >> 16;
13153 13158 cdb[8] = (buf_len & 0x0000ff00) >> 8;
13154 13159 cdb[9] = (buf_len & 0x000000ff);
13155 13160
13156 13161 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP5,
13157 13162 repluns_bp, NULL);
13158 13163 if (ret != DDI_SUCCESS) {
13159 13164 scsi_free_consistent_buf(repluns_bp);
13160 13165 retry++;
13161 13166 continue;
13162 13167 }
13163 13168 lun_list_len = BE_32(*(int *)((void *)(
13164 13169 repluns_bp->b_un.b_addr)));
13165 13170 if (buf_len >= lun_list_len + 8) {
13166 13171 ret = DDI_SUCCESS;
13167 13172 break;
13168 13173 }
13169 13174 scsi_free_consistent_buf(repluns_bp);
13170 13175 buf_len = lun_list_len + 8;
13171 13176
13172 13177 } while (retry < 3);
13173 13178
13174 13179 if (ret != DDI_SUCCESS)
13175 13180 return (ret);
13176 13181 buffer = (char *)repluns_bp->b_un.b_addr;
13177 13182 /*
13178 13183 * find out the number of luns returned by the SCSI ReportLun call
13179 13184 * and allocate buffer space
13180 13185 */
13181 13186 lun_total = lun_list_len / MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE;
13182 13187 saved_repluns = kmem_zalloc(sizeof (uint16_t) * lun_total, KM_SLEEP);
13183 13188 if (saved_repluns == NULL) {
13184 13189 scsi_free_consistent_buf(repluns_bp);
13185 13190 return (DDI_FAILURE);
13186 13191 }
13187 13192 for (lun_cnt = 0; lun_cnt < lun_total; lun_cnt++) {
13188 13193 if (mptsas_retrieve_lundata(lun_cnt, (uint8_t *)(buffer),
13189 13194 &lun_num, &lun_addr_type) != DDI_SUCCESS) {
13190 13195 continue;
13191 13196 }
13192 13197 saved_repluns[lun_cnt] = lun_num;
13193 13198 if (cdip = mptsas_find_child_addr(pdip, sas_wwn, lun_num))
13194 13199 ret = DDI_SUCCESS;
13195 13200 else
13196 13201 ret = mptsas_probe_lun(pdip, lun_num, &cdip,
13197 13202 ptgt);
13198 13203 if ((ret == DDI_SUCCESS) && (cdip != NULL)) {
13199 13204 (void) ndi_prop_remove(DDI_DEV_T_NONE, cdip,
13200 13205 MPTSAS_DEV_GONE);
13201 13206 }
13202 13207 }
13203 13208 mptsas_offline_missed_luns(pdip, saved_repluns, lun_total, ptgt);
13204 13209 kmem_free(saved_repluns, sizeof (uint16_t) * lun_total);
13205 13210 scsi_free_consistent_buf(repluns_bp);
13206 13211 return (DDI_SUCCESS);
13207 13212 }
13208 13213
13209 13214 static int
13210 13215 mptsas_config_raid(dev_info_t *pdip, uint16_t target, dev_info_t **dip)
13211 13216 {
13212 13217 int rval = DDI_FAILURE;
13213 13218 struct scsi_inquiry *sd_inq = NULL;
13214 13219 mptsas_t *mpt = DIP2MPT(pdip);
13215 13220 mptsas_target_t *ptgt = NULL;
13216 13221
13217 13222 mutex_enter(&mpt->m_mutex);
13218 13223 ptgt = mptsas_search_by_devhdl(&mpt->m_active->m_tgttbl, target);
13219 13224 mutex_exit(&mpt->m_mutex);
13220 13225 if (ptgt == NULL) {
13221 13226 mptsas_log(mpt, CE_WARN, "Volume with VolDevHandle of 0x%x "
13222 13227 "not found.", target);
13223 13228 return (rval);
13224 13229 }
13225 13230
13226 13231 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP);
13227 13232 rval = mptsas_inquiry(mpt, ptgt, 0, 0, (uchar_t *)sd_inq,
13228 13233 SUN_INQSIZE, 0, (uchar_t)0);
13229 13234
13230 13235 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) {
13231 13236 rval = mptsas_create_phys_lun(pdip, sd_inq, NULL, dip, ptgt,
13232 13237 0);
13233 13238 } else {
13234 13239 rval = DDI_FAILURE;
13235 13240 }
13236 13241
13237 13242 kmem_free(sd_inq, SUN_INQSIZE);
13238 13243 return (rval);
13239 13244 }
13240 13245
13241 13246 /*
13242 13247 * configure all RAID volumes for virtual iport
13243 13248 */
13244 13249 static void
13245 13250 mptsas_config_all_viport(dev_info_t *pdip)
13246 13251 {
13247 13252 mptsas_t *mpt = DIP2MPT(pdip);
13248 13253 int config, vol;
13249 13254 int target;
13250 13255 dev_info_t *lundip = NULL;
13251 13256 mptsas_slots_t *slots = mpt->m_active;
13252 13257
13253 13258 /*
13254 13259 * Get latest RAID info and search for any Volume DevHandles. If any
13255 13260 * are found, configure the volume.
13256 13261 */
13257 13262 mutex_enter(&mpt->m_mutex);
13258 13263 for (config = 0; config < slots->m_num_raid_configs; config++) {
13259 13264 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) {
13260 13265 if (slots->m_raidconfig[config].m_raidvol[vol].m_israid
13261 13266 == 1) {
13262 13267 target = slots->m_raidconfig[config].
13263 13268 m_raidvol[vol].m_raidhandle;
13264 13269 mutex_exit(&mpt->m_mutex);
13265 13270 (void) mptsas_config_raid(pdip, target,
13266 13271 &lundip);
13267 13272 mutex_enter(&mpt->m_mutex);
13268 13273 }
13269 13274 }
13270 13275 }
13271 13276 mutex_exit(&mpt->m_mutex);
13272 13277 }
13273 13278
13274 13279 static void
13275 13280 mptsas_offline_missed_luns(dev_info_t *pdip, uint16_t *repluns,
13276 13281 int lun_cnt, mptsas_target_t *ptgt)
13277 13282 {
13278 13283 dev_info_t *child = NULL, *savechild = NULL;
13279 13284 mdi_pathinfo_t *pip = NULL, *savepip = NULL;
13280 13285 uint64_t sas_wwn, wwid;
13281 13286 uint8_t phy;
13282 13287 int lun;
13283 13288 int i;
13284 13289 int find;
13285 13290 char *addr;
13286 13291 char *nodename;
13287 13292 mptsas_t *mpt = DIP2MPT(pdip);
13288 13293
13289 13294 mutex_enter(&mpt->m_mutex);
13290 13295 wwid = ptgt->m_sas_wwn;
13291 13296 mutex_exit(&mpt->m_mutex);
13292 13297
13293 13298 child = ddi_get_child(pdip);
13294 13299 while (child) {
13295 13300 find = 0;
13296 13301 savechild = child;
13297 13302 child = ddi_get_next_sibling(child);
13298 13303
13299 13304 nodename = ddi_node_name(savechild);
13300 13305 if (strcmp(nodename, "smp") == 0) {
13301 13306 continue;
13302 13307 }
13303 13308
13304 13309 addr = ddi_get_name_addr(savechild);
13305 13310 if (addr == NULL) {
13306 13311 continue;
13307 13312 }
13308 13313
13309 13314 if (mptsas_parse_address(addr, &sas_wwn, &phy, &lun) !=
13310 13315 DDI_SUCCESS) {
13311 13316 continue;
13312 13317 }
13313 13318
13314 13319 if (wwid == sas_wwn) {
13315 13320 for (i = 0; i < lun_cnt; i++) {
13316 13321 if (repluns[i] == lun) {
13317 13322 find = 1;
13318 13323 break;
13319 13324 }
13320 13325 }
13321 13326 } else {
13322 13327 continue;
13323 13328 }
13324 13329 if (find == 0) {
13325 13330 /*
13326 13331 * The lun has not been there already
13327 13332 */
13328 13333 (void) mptsas_offline_lun(pdip, savechild, NULL,
13329 13334 NDI_DEVI_REMOVE);
13330 13335 }
13331 13336 }
13332 13337
13333 13338 pip = mdi_get_next_client_path(pdip, NULL);
13334 13339 while (pip) {
13335 13340 find = 0;
13336 13341 savepip = pip;
13337 13342 addr = MDI_PI(pip)->pi_addr;
13338 13343
13339 13344 pip = mdi_get_next_client_path(pdip, pip);
13340 13345
13341 13346 if (addr == NULL) {
13342 13347 continue;
13343 13348 }
13344 13349
13345 13350 if (mptsas_parse_address(addr, &sas_wwn, &phy,
13346 13351 &lun) != DDI_SUCCESS) {
13347 13352 continue;
13348 13353 }
13349 13354
13350 13355 if (sas_wwn == wwid) {
13351 13356 for (i = 0; i < lun_cnt; i++) {
13352 13357 if (repluns[i] == lun) {
13353 13358 find = 1;
13354 13359 break;
13355 13360 }
13356 13361 }
13357 13362 } else {
13358 13363 continue;
13359 13364 }
13360 13365
13361 13366 if (find == 0) {
13362 13367 /*
13363 13368 * The lun has not been there already
13364 13369 */
13365 13370 (void) mptsas_offline_lun(pdip, NULL, savepip,
13366 13371 NDI_DEVI_REMOVE);
13367 13372 }
13368 13373 }
13369 13374 }
13370 13375
13371 13376 void
13372 13377 mptsas_update_hashtab(struct mptsas *mpt)
13373 13378 {
13374 13379 uint32_t page_address;
13375 13380 int rval = 0;
13376 13381 uint16_t dev_handle;
13377 13382 mptsas_target_t *ptgt = NULL;
13378 13383 mptsas_smp_t smp_node;
13379 13384
13380 13385 /*
13381 13386 * Get latest RAID info.
13382 13387 */
13383 13388 (void) mptsas_get_raid_info(mpt);
13384 13389
13385 13390 dev_handle = mpt->m_smp_devhdl;
13386 13391 for (; mpt->m_done_traverse_smp == 0; ) {
13387 13392 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL &
13388 13393 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)dev_handle;
13389 13394 if (mptsas_get_sas_expander_page0(mpt, page_address, &smp_node)
13390 13395 != DDI_SUCCESS) {
13391 13396 break;
13392 13397 }
13393 13398 mpt->m_smp_devhdl = dev_handle = smp_node.m_devhdl;
13394 13399 (void) mptsas_smp_alloc(&mpt->m_active->m_smptbl, &smp_node);
13395 13400 }
13396 13401
13397 13402 /*
13398 13403 * Config target devices
13399 13404 */
13400 13405 dev_handle = mpt->m_dev_handle;
13401 13406
13402 13407 /*
13403 13408 * Do loop to get sas device page 0 by GetNextHandle till the
13404 13409 * the last handle. If the sas device is a SATA/SSP target,
13405 13410 * we try to config it.
13406 13411 */
13407 13412 for (; mpt->m_done_traverse_dev == 0; ) {
13408 13413 ptgt = NULL;
13409 13414 page_address =
13410 13415 (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
13411 13416 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
13412 13417 (uint32_t)dev_handle;
13413 13418 rval = mptsas_get_target_device_info(mpt, page_address,
13414 13419 &dev_handle, &ptgt);
13415 13420 if ((rval == DEV_INFO_FAIL_PAGE0) ||
13416 13421 (rval == DEV_INFO_FAIL_ALLOC)) {
13417 13422 break;
13418 13423 }
13419 13424
13420 13425 mpt->m_dev_handle = dev_handle;
13421 13426 }
13422 13427
13423 13428 }
13424 13429
13425 13430 void
13426 13431 mptsas_invalid_hashtab(mptsas_hash_table_t *hashtab)
13427 13432 {
13428 13433 mptsas_hash_data_t *data;
13429 13434 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_FIRST);
13430 13435 while (data != NULL) {
13431 13436 data->devhdl = MPTSAS_INVALID_DEVHDL;
13432 13437 data->device_info = 0;
13433 13438 /*
13434 13439 * For tgttbl, clear dr_flag.
13435 13440 */
13436 13441 data->dr_flag = MPTSAS_DR_INACTIVE;
13437 13442 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_NEXT);
13438 13443 }
13439 13444 }
13440 13445
13441 13446 void
13442 13447 mptsas_update_driver_data(struct mptsas *mpt)
13443 13448 {
13444 13449 /*
13445 13450 * TODO after hard reset, update the driver data structures
13446 13451 * 1. update port/phymask mapping table mpt->m_phy_info
13447 13452 * 2. invalid all the entries in hash table
13448 13453 * m_devhdl = 0xffff and m_deviceinfo = 0
13449 13454 * 3. call sas_device_page/expander_page to update hash table
13450 13455 */
13451 13456 mptsas_update_phymask(mpt);
13452 13457 /*
13453 13458 * Invalid the existing entries
13454 13459 */
13455 13460 mptsas_invalid_hashtab(&mpt->m_active->m_tgttbl);
13456 13461 mptsas_invalid_hashtab(&mpt->m_active->m_smptbl);
13457 13462 mpt->m_done_traverse_dev = 0;
13458 13463 mpt->m_done_traverse_smp = 0;
13459 13464 mpt->m_dev_handle = mpt->m_smp_devhdl = MPTSAS_INVALID_DEVHDL;
13460 13465 mptsas_update_hashtab(mpt);
13461 13466 }
13462 13467
13463 13468 static void
13464 13469 mptsas_config_all(dev_info_t *pdip)
13465 13470 {
13466 13471 dev_info_t *smpdip = NULL;
13467 13472 mptsas_t *mpt = DIP2MPT(pdip);
13468 13473 int phymask = 0;
13469 13474 mptsas_phymask_t phy_mask;
13470 13475 mptsas_target_t *ptgt = NULL;
13471 13476 mptsas_smp_t *psmp;
13472 13477
13473 13478 /*
13474 13479 * Get the phymask associated to the iport
13475 13480 */
13476 13481 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
13477 13482 "phymask", 0);
13478 13483
13479 13484 /*
13480 13485 * Enumerate RAID volumes here (phymask == 0).
13481 13486 */
13482 13487 if (phymask == 0) {
13483 13488 mptsas_config_all_viport(pdip);
13484 13489 return;
13485 13490 }
13486 13491
13487 13492 mutex_enter(&mpt->m_mutex);
13488 13493
13489 13494 if (!mpt->m_done_traverse_dev || !mpt->m_done_traverse_smp) {
13490 13495 mptsas_update_hashtab(mpt);
13491 13496 }
13492 13497
13493 13498 psmp = (mptsas_smp_t *)mptsas_hash_traverse(&mpt->m_active->m_smptbl,
13494 13499 MPTSAS_HASH_FIRST);
13495 13500 while (psmp != NULL) {
13496 13501 phy_mask = psmp->m_phymask;
13497 13502 if (phy_mask == phymask) {
13498 13503 smpdip = NULL;
13499 13504 mutex_exit(&mpt->m_mutex);
13500 13505 (void) mptsas_online_smp(pdip, psmp, &smpdip);
13501 13506 mutex_enter(&mpt->m_mutex);
13502 13507 }
13503 13508 psmp = (mptsas_smp_t *)mptsas_hash_traverse(
13504 13509 &mpt->m_active->m_smptbl, MPTSAS_HASH_NEXT);
13505 13510 }
13506 13511
13507 13512 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
13508 13513 MPTSAS_HASH_FIRST);
13509 13514 while (ptgt != NULL) {
13510 13515 phy_mask = ptgt->m_phymask;
13511 13516 if (phy_mask == phymask) {
13512 13517 mutex_exit(&mpt->m_mutex);
13513 13518 (void) mptsas_config_target(pdip, ptgt);
13514 13519 mutex_enter(&mpt->m_mutex);
13515 13520 }
13516 13521
13517 13522 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
13518 13523 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
13519 13524 }
13520 13525 mutex_exit(&mpt->m_mutex);
13521 13526 }
13522 13527
13523 13528 static int
13524 13529 mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt)
13525 13530 {
13526 13531 int rval = DDI_FAILURE;
13527 13532 dev_info_t *tdip;
13528 13533
13529 13534 rval = mptsas_config_luns(pdip, ptgt);
13530 13535 if (rval != DDI_SUCCESS) {
13531 13536 /*
13532 13537 * The return value means the SCMD_REPORT_LUNS
13533 13538 * did not execute successfully. The target maybe
13534 13539 * doesn't support such command.
13535 13540 */
13536 13541 rval = mptsas_probe_lun(pdip, 0, &tdip, ptgt);
13537 13542 }
13538 13543 return (rval);
13539 13544 }
13540 13545
13541 13546 /*
13542 13547 * Return fail if not all the childs/paths are freed.
13543 13548 * if there is any path under the HBA, the return value will be always fail
13544 13549 * because we didn't call mdi_pi_free for path
13545 13550 */
13546 13551 static int
13547 13552 mptsas_offline_target(dev_info_t *pdip, char *name)
13548 13553 {
13549 13554 dev_info_t *child = NULL, *prechild = NULL;
13550 13555 mdi_pathinfo_t *pip = NULL, *savepip = NULL;
13551 13556 int tmp_rval, rval = DDI_SUCCESS;
13552 13557 char *addr, *cp;
13553 13558 size_t s;
13554 13559 mptsas_t *mpt = DIP2MPT(pdip);
13555 13560
13556 13561 child = ddi_get_child(pdip);
13557 13562 while (child) {
13558 13563 addr = ddi_get_name_addr(child);
13559 13564 prechild = child;
13560 13565 child = ddi_get_next_sibling(child);
13561 13566
13562 13567 if (addr == NULL) {
13563 13568 continue;
13564 13569 }
13565 13570 if ((cp = strchr(addr, ',')) == NULL) {
13566 13571 continue;
13567 13572 }
13568 13573
13569 13574 s = (uintptr_t)cp - (uintptr_t)addr;
13570 13575
13571 13576 if (strncmp(addr, name, s) != 0) {
13572 13577 continue;
13573 13578 }
13574 13579
13575 13580 tmp_rval = mptsas_offline_lun(pdip, prechild, NULL,
13576 13581 NDI_DEVI_REMOVE);
13577 13582 if (tmp_rval != DDI_SUCCESS) {
13578 13583 rval = DDI_FAILURE;
13579 13584 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
13580 13585 prechild, MPTSAS_DEV_GONE) !=
13581 13586 DDI_PROP_SUCCESS) {
13582 13587 mptsas_log(mpt, CE_WARN, "mptsas driver "
13583 13588 "unable to create property for "
13584 13589 "SAS %s (MPTSAS_DEV_GONE)", addr);
13585 13590 }
13586 13591 }
13587 13592 }
13588 13593
13589 13594 pip = mdi_get_next_client_path(pdip, NULL);
13590 13595 while (pip) {
13591 13596 addr = MDI_PI(pip)->pi_addr;
13592 13597 savepip = pip;
13593 13598 pip = mdi_get_next_client_path(pdip, pip);
13594 13599 if (addr == NULL) {
13595 13600 continue;
13596 13601 }
13597 13602
13598 13603 if ((cp = strchr(addr, ',')) == NULL) {
13599 13604 continue;
13600 13605 }
13601 13606
13602 13607 s = (uintptr_t)cp - (uintptr_t)addr;
13603 13608
13604 13609 if (strncmp(addr, name, s) != 0) {
13605 13610 continue;
13606 13611 }
13607 13612
13608 13613 (void) mptsas_offline_lun(pdip, NULL, savepip,
13609 13614 NDI_DEVI_REMOVE);
13610 13615 /*
13611 13616 * driver will not invoke mdi_pi_free, so path will not
13612 13617 * be freed forever, return DDI_FAILURE.
13613 13618 */
13614 13619 rval = DDI_FAILURE;
13615 13620 }
13616 13621 return (rval);
13617 13622 }
13618 13623
13619 13624 static int
13620 13625 mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip,
13621 13626 mdi_pathinfo_t *rpip, uint_t flags)
13622 13627 {
13623 13628 int rval = DDI_FAILURE;
13624 13629 char *devname;
13625 13630 dev_info_t *cdip, *parent;
13626 13631
13627 13632 if (rpip != NULL) {
13628 13633 parent = scsi_vhci_dip;
13629 13634 cdip = mdi_pi_get_client(rpip);
13630 13635 } else if (rdip != NULL) {
13631 13636 parent = pdip;
13632 13637 cdip = rdip;
13633 13638 } else {
13634 13639 return (DDI_FAILURE);
13635 13640 }
13636 13641
13637 13642 /*
13638 13643 * Make sure node is attached otherwise
13639 13644 * it won't have related cache nodes to
13640 13645 * clean up. i_ddi_devi_attached is
13641 13646 * similiar to i_ddi_node_state(cdip) >=
13642 13647 * DS_ATTACHED.
13643 13648 */
13644 13649 if (i_ddi_devi_attached(cdip)) {
13645 13650
13646 13651 /* Get full devname */
13647 13652 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP);
13648 13653 (void) ddi_deviname(cdip, devname);
13649 13654 /* Clean cache */
13650 13655 (void) devfs_clean(parent, devname + 1,
13651 13656 DV_CLEAN_FORCE);
13652 13657 kmem_free(devname, MAXNAMELEN + 1);
13653 13658 }
13654 13659 if (rpip != NULL) {
13655 13660 if (MDI_PI_IS_OFFLINE(rpip)) {
13656 13661 rval = DDI_SUCCESS;
13657 13662 } else {
13658 13663 rval = mdi_pi_offline(rpip, 0);
13659 13664 }
13660 13665 } else {
13661 13666 rval = ndi_devi_offline(cdip, flags);
13662 13667 }
13663 13668
13664 13669 return (rval);
13665 13670 }
13666 13671
13667 13672 static dev_info_t *
13668 13673 mptsas_find_smp_child(dev_info_t *parent, char *str_wwn)
13669 13674 {
13670 13675 dev_info_t *child = NULL;
13671 13676 char *smp_wwn = NULL;
13672 13677
13673 13678 child = ddi_get_child(parent);
13674 13679 while (child) {
13675 13680 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, child,
13676 13681 DDI_PROP_DONTPASS, SMP_WWN, &smp_wwn)
13677 13682 != DDI_SUCCESS) {
13678 13683 child = ddi_get_next_sibling(child);
13679 13684 continue;
13680 13685 }
13681 13686
13682 13687 if (strcmp(smp_wwn, str_wwn) == 0) {
13683 13688 ddi_prop_free(smp_wwn);
13684 13689 break;
13685 13690 }
13686 13691 child = ddi_get_next_sibling(child);
13687 13692 ddi_prop_free(smp_wwn);
13688 13693 }
13689 13694 return (child);
13690 13695 }
13691 13696
13692 13697 static int
13693 13698 mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, uint_t flags)
13694 13699 {
13695 13700 int rval = DDI_FAILURE;
13696 13701 char *devname;
13697 13702 char wwn_str[MPTSAS_WWN_STRLEN];
13698 13703 dev_info_t *cdip;
13699 13704
13700 13705 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_sasaddr);
13701 13706
13702 13707 cdip = mptsas_find_smp_child(pdip, wwn_str);
13703 13708
13704 13709 if (cdip == NULL)
13705 13710 return (DDI_SUCCESS);
13706 13711
13707 13712 /*
13708 13713 * Make sure node is attached otherwise
13709 13714 * it won't have related cache nodes to
13710 13715 * clean up. i_ddi_devi_attached is
13711 13716 * similiar to i_ddi_node_state(cdip) >=
13712 13717 * DS_ATTACHED.
13713 13718 */
13714 13719 if (i_ddi_devi_attached(cdip)) {
13715 13720
13716 13721 /* Get full devname */
13717 13722 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP);
13718 13723 (void) ddi_deviname(cdip, devname);
13719 13724 /* Clean cache */
13720 13725 (void) devfs_clean(pdip, devname + 1,
13721 13726 DV_CLEAN_FORCE);
13722 13727 kmem_free(devname, MAXNAMELEN + 1);
13723 13728 }
13724 13729
13725 13730 rval = ndi_devi_offline(cdip, flags);
13726 13731
13727 13732 return (rval);
13728 13733 }
13729 13734
13730 13735 static dev_info_t *
13731 13736 mptsas_find_child(dev_info_t *pdip, char *name)
13732 13737 {
13733 13738 dev_info_t *child = NULL;
13734 13739 char *rname = NULL;
13735 13740 int rval = DDI_FAILURE;
13736 13741
13737 13742 rname = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13738 13743
13739 13744 child = ddi_get_child(pdip);
13740 13745 while (child) {
13741 13746 rval = mptsas_name_child(child, rname, SCSI_MAXNAMELEN);
13742 13747 if (rval != DDI_SUCCESS) {
13743 13748 child = ddi_get_next_sibling(child);
13744 13749 bzero(rname, SCSI_MAXNAMELEN);
13745 13750 continue;
13746 13751 }
13747 13752
13748 13753 if (strcmp(rname, name) == 0) {
13749 13754 break;
13750 13755 }
13751 13756 child = ddi_get_next_sibling(child);
13752 13757 bzero(rname, SCSI_MAXNAMELEN);
13753 13758 }
13754 13759
13755 13760 kmem_free(rname, SCSI_MAXNAMELEN);
13756 13761
13757 13762 return (child);
13758 13763 }
13759 13764
13760 13765
13761 13766 static dev_info_t *
13762 13767 mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, int lun)
13763 13768 {
13764 13769 dev_info_t *child = NULL;
13765 13770 char *name = NULL;
13766 13771 char *addr = NULL;
13767 13772
13768 13773 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13769 13774 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13770 13775 (void) sprintf(name, "%016"PRIx64, sasaddr);
13771 13776 (void) sprintf(addr, "w%s,%x", name, lun);
13772 13777 child = mptsas_find_child(pdip, addr);
13773 13778 kmem_free(name, SCSI_MAXNAMELEN);
13774 13779 kmem_free(addr, SCSI_MAXNAMELEN);
13775 13780 return (child);
13776 13781 }
13777 13782
13778 13783 static dev_info_t *
13779 13784 mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy)
13780 13785 {
13781 13786 dev_info_t *child;
13782 13787 char *addr;
13783 13788
13784 13789 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13785 13790 (void) sprintf(addr, "p%x,0", phy);
13786 13791 child = mptsas_find_child(pdip, addr);
13787 13792 kmem_free(addr, SCSI_MAXNAMELEN);
13788 13793 return (child);
13789 13794 }
13790 13795
13791 13796 static mdi_pathinfo_t *
13792 13797 mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy)
13793 13798 {
13794 13799 mdi_pathinfo_t *path;
13795 13800 char *addr = NULL;
13796 13801
13797 13802 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13798 13803 (void) sprintf(addr, "p%x,0", phy);
13799 13804 path = mdi_pi_find(pdip, NULL, addr);
13800 13805 kmem_free(addr, SCSI_MAXNAMELEN);
13801 13806 return (path);
13802 13807 }
13803 13808
13804 13809 static mdi_pathinfo_t *
13805 13810 mptsas_find_path_addr(dev_info_t *parent, uint64_t sasaddr, int lun)
13806 13811 {
13807 13812 mdi_pathinfo_t *path;
13808 13813 char *name = NULL;
13809 13814 char *addr = NULL;
13810 13815
13811 13816 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13812 13817 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13813 13818 (void) sprintf(name, "%016"PRIx64, sasaddr);
13814 13819 (void) sprintf(addr, "w%s,%x", name, lun);
13815 13820 path = mdi_pi_find(parent, NULL, addr);
13816 13821 kmem_free(name, SCSI_MAXNAMELEN);
13817 13822 kmem_free(addr, SCSI_MAXNAMELEN);
13818 13823
13819 13824 return (path);
13820 13825 }
13821 13826
13822 13827 static int
13823 13828 mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq,
13824 13829 dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun)
13825 13830 {
13826 13831 int i = 0;
13827 13832 uchar_t *inq83 = NULL;
13828 13833 int inq83_len1 = 0xFF;
13829 13834 int inq83_len = 0;
13830 13835 int rval = DDI_FAILURE;
13831 13836 ddi_devid_t devid;
13832 13837 char *guid = NULL;
13833 13838 int target = ptgt->m_devhdl;
13834 13839 mdi_pathinfo_t *pip = NULL;
13835 13840 mptsas_t *mpt = DIP2MPT(pdip);
13836 13841
13837 13842 /*
13838 13843 * For DVD/CD ROM and tape devices and optical
13839 13844 * devices, we won't try to enumerate them under
13840 13845 * scsi_vhci, so no need to try page83
13841 13846 */
13842 13847 if (sd_inq && (sd_inq->inq_dtype == DTYPE_RODIRECT ||
13843 13848 sd_inq->inq_dtype == DTYPE_OPTICAL ||
13844 13849 sd_inq->inq_dtype == DTYPE_ESI))
13845 13850 goto create_lun;
13846 13851
13847 13852 /*
13848 13853 * The LCA returns good SCSI status, but corrupt page 83 data the first
13849 13854 * time it is queried. The solution is to keep trying to request page83
13850 13855 * and verify the GUID is not (DDI_NOT_WELL_FORMED) in
13851 13856 * mptsas_inq83_retry_timeout seconds. If the timeout expires, driver
13852 13857 * give up to get VPD page at this stage and fail the enumeration.
13853 13858 */
13854 13859
13855 13860 inq83 = kmem_zalloc(inq83_len1, KM_SLEEP);
13856 13861
13857 13862 for (i = 0; i < mptsas_inq83_retry_timeout; i++) {
13858 13863 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83,
13859 13864 inq83_len1, &inq83_len, 1);
13860 13865 if (rval != 0) {
13861 13866 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
13862 13867 "0x83 for target:%x, lun:%x failed!", target, lun);
13863 13868 if (mptsas_physical_bind_failed_page_83 != B_FALSE)
13864 13869 goto create_lun;
13865 13870 goto out;
13866 13871 }
13867 13872 /*
13868 13873 * create DEVID from inquiry data
13869 13874 */
13870 13875 if ((rval = ddi_devid_scsi_encode(
13871 13876 DEVID_SCSI_ENCODE_VERSION_LATEST, NULL, (uchar_t *)sd_inq,
13872 13877 sizeof (struct scsi_inquiry), NULL, 0, inq83,
13873 13878 (size_t)inq83_len, &devid)) == DDI_SUCCESS) {
13874 13879 /*
13875 13880 * extract GUID from DEVID
13876 13881 */
13877 13882 guid = ddi_devid_to_guid(devid);
13878 13883
13879 13884 /*
13880 13885 * Do not enable MPXIO if the strlen(guid) is greater
13881 13886 * than MPTSAS_MAX_GUID_LEN, this constrain would be
13882 13887 * handled by framework later.
13883 13888 */
13884 13889 if (guid && (strlen(guid) > MPTSAS_MAX_GUID_LEN)) {
13885 13890 ddi_devid_free_guid(guid);
13886 13891 guid = NULL;
13887 13892 if (mpt->m_mpxio_enable == TRUE) {
13888 13893 mptsas_log(mpt, CE_NOTE, "!Target:%x, "
13889 13894 "lun:%x doesn't have a valid GUID, "
13890 13895 "multipathing for this drive is "
13891 13896 "not enabled", target, lun);
13892 13897 }
13893 13898 }
13894 13899
13895 13900 /*
13896 13901 * devid no longer needed
13897 13902 */
13898 13903 ddi_devid_free(devid);
13899 13904 break;
13900 13905 } else if (rval == DDI_NOT_WELL_FORMED) {
13901 13906 /*
13902 13907 * return value of ddi_devid_scsi_encode equal to
13903 13908 * DDI_NOT_WELL_FORMED means DEVID_RETRY, it worth
13904 13909 * to retry inquiry page 0x83 and get GUID.
13905 13910 */
13906 13911 NDBG20(("Not well formed devid, retry..."));
13907 13912 delay(1 * drv_usectohz(1000000));
13908 13913 continue;
13909 13914 } else {
13910 13915 mptsas_log(mpt, CE_WARN, "!Encode devid failed for "
13911 13916 "path target:%x, lun:%x", target, lun);
13912 13917 rval = DDI_FAILURE;
13913 13918 goto create_lun;
13914 13919 }
13915 13920 }
13916 13921
13917 13922 if (i == mptsas_inq83_retry_timeout) {
13918 13923 mptsas_log(mpt, CE_WARN, "!Repeated page83 requests timeout "
13919 13924 "for path target:%x, lun:%x", target, lun);
13920 13925 }
13921 13926
13922 13927 rval = DDI_FAILURE;
13923 13928
13924 13929 create_lun:
13925 13930 if ((guid != NULL) && (mpt->m_mpxio_enable == TRUE)) {
13926 13931 rval = mptsas_create_virt_lun(pdip, sd_inq, guid, lun_dip, &pip,
13927 13932 ptgt, lun);
13928 13933 }
13929 13934 if (rval != DDI_SUCCESS) {
13930 13935 rval = mptsas_create_phys_lun(pdip, sd_inq, guid, lun_dip,
13931 13936 ptgt, lun);
13932 13937
13933 13938 }
13934 13939 out:
13935 13940 if (guid != NULL) {
13936 13941 /*
13937 13942 * guid no longer needed
13938 13943 */
13939 13944 ddi_devid_free_guid(guid);
13940 13945 }
13941 13946 if (inq83 != NULL)
13942 13947 kmem_free(inq83, inq83_len1);
13943 13948 return (rval);
13944 13949 }
13945 13950
13946 13951 static int
13947 13952 mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *inq, char *guid,
13948 13953 dev_info_t **lun_dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, int lun)
13949 13954 {
13950 13955 int target;
13951 13956 char *nodename = NULL;
13952 13957 char **compatible = NULL;
13953 13958 int ncompatible = 0;
13954 13959 int mdi_rtn = MDI_FAILURE;
13955 13960 int rval = DDI_FAILURE;
13956 13961 char *old_guid = NULL;
13957 13962 mptsas_t *mpt = DIP2MPT(pdip);
13958 13963 char *lun_addr = NULL;
13959 13964 char *wwn_str = NULL;
13960 13965 char *attached_wwn_str = NULL;
13961 13966 char *component = NULL;
13962 13967 uint8_t phy = 0xFF;
13963 13968 uint64_t sas_wwn;
13964 13969 int64_t lun64 = 0;
13965 13970 uint32_t devinfo;
13966 13971 uint16_t dev_hdl;
13967 13972 uint16_t pdev_hdl;
13968 13973 uint64_t dev_sas_wwn;
13969 13974 uint64_t pdev_sas_wwn;
13970 13975 uint32_t pdev_info;
13971 13976 uint8_t physport;
13972 13977 uint8_t phy_id;
13973 13978 uint32_t page_address;
13974 13979 uint16_t bay_num, enclosure;
13975 13980 char pdev_wwn_str[MPTSAS_WWN_STRLEN];
13976 13981 uint32_t dev_info;
13977 13982
13978 13983 mutex_enter(&mpt->m_mutex);
13979 13984 target = ptgt->m_devhdl;
13980 13985 sas_wwn = ptgt->m_sas_wwn;
13981 13986 devinfo = ptgt->m_deviceinfo;
13982 13987 phy = ptgt->m_phynum;
13983 13988 mutex_exit(&mpt->m_mutex);
13984 13989
13985 13990 if (sas_wwn) {
13986 13991 *pip = mptsas_find_path_addr(pdip, sas_wwn, lun);
13987 13992 } else {
13988 13993 *pip = mptsas_find_path_phy(pdip, phy);
13989 13994 }
13990 13995
13991 13996 if (*pip != NULL) {
13992 13997 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip;
13993 13998 ASSERT(*lun_dip != NULL);
13994 13999 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, *lun_dip,
13995 14000 (DDI_PROP_DONTPASS | DDI_PROP_NOTPROM),
13996 14001 MDI_CLIENT_GUID_PROP, &old_guid) == DDI_SUCCESS) {
13997 14002 if (strncmp(guid, old_guid, strlen(guid)) == 0) {
13998 14003 /*
13999 14004 * Same path back online again.
14000 14005 */
14001 14006 (void) ddi_prop_free(old_guid);
14002 14007 if ((!MDI_PI_IS_ONLINE(*pip)) &&
14003 14008 (!MDI_PI_IS_STANDBY(*pip)) &&
14004 14009 (ptgt->m_tgt_unconfigured == 0)) {
14005 14010 rval = mdi_pi_online(*pip, 0);
14006 14011 mutex_enter(&mpt->m_mutex);
14007 14012 ptgt->m_led_status = 0;
14008 14013 (void) mptsas_flush_led_status(mpt,
14009 14014 ptgt);
14010 14015 mutex_exit(&mpt->m_mutex);
14011 14016 } else {
14012 14017 rval = DDI_SUCCESS;
14013 14018 }
14014 14019 if (rval != DDI_SUCCESS) {
14015 14020 mptsas_log(mpt, CE_WARN, "path:target: "
14016 14021 "%x, lun:%x online failed!", target,
14017 14022 lun);
14018 14023 *pip = NULL;
14019 14024 *lun_dip = NULL;
14020 14025 }
14021 14026 return (rval);
14022 14027 } else {
14023 14028 /*
14024 14029 * The GUID of the LUN has changed which maybe
14025 14030 * because customer mapped another volume to the
14026 14031 * same LUN.
14027 14032 */
14028 14033 mptsas_log(mpt, CE_WARN, "The GUID of the "
14029 14034 "target:%x, lun:%x was changed, maybe "
14030 14035 "because someone mapped another volume "
14031 14036 "to the same LUN", target, lun);
14032 14037 (void) ddi_prop_free(old_guid);
14033 14038 if (!MDI_PI_IS_OFFLINE(*pip)) {
14034 14039 rval = mdi_pi_offline(*pip, 0);
14035 14040 if (rval != MDI_SUCCESS) {
14036 14041 mptsas_log(mpt, CE_WARN, "path:"
14037 14042 "target:%x, lun:%x offline "
14038 14043 "failed!", target, lun);
14039 14044 *pip = NULL;
14040 14045 *lun_dip = NULL;
14041 14046 return (DDI_FAILURE);
14042 14047 }
14043 14048 }
14044 14049 if (mdi_pi_free(*pip, 0) != MDI_SUCCESS) {
14045 14050 mptsas_log(mpt, CE_WARN, "path:target:"
14046 14051 "%x, lun:%x free failed!", target,
14047 14052 lun);
14048 14053 *pip = NULL;
14049 14054 *lun_dip = NULL;
14050 14055 return (DDI_FAILURE);
14051 14056 }
14052 14057 }
14053 14058 } else {
14054 14059 mptsas_log(mpt, CE_WARN, "Can't get client-guid "
14055 14060 "property for path:target:%x, lun:%x", target, lun);
14056 14061 *pip = NULL;
14057 14062 *lun_dip = NULL;
14058 14063 return (DDI_FAILURE);
14059 14064 }
14060 14065 }
14061 14066 scsi_hba_nodename_compatible_get(inq, NULL,
14062 14067 inq->inq_dtype, NULL, &nodename, &compatible, &ncompatible);
14063 14068
14064 14069 /*
14065 14070 * if nodename can't be determined then print a message and skip it
14066 14071 */
14067 14072 if (nodename == NULL) {
14068 14073 mptsas_log(mpt, CE_WARN, "mptsas driver found no compatible "
14069 14074 "driver for target%d lun %d dtype:0x%02x", target, lun,
14070 14075 inq->inq_dtype);
14071 14076 return (DDI_FAILURE);
14072 14077 }
14073 14078
14074 14079 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP);
14075 14080 /* The property is needed by MPAPI */
14076 14081 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn);
14077 14082
14078 14083 lun_addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14079 14084 if (guid) {
14080 14085 (void) sprintf(lun_addr, "w%s,%x", wwn_str, lun);
14081 14086 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
14082 14087 } else {
14083 14088 (void) sprintf(lun_addr, "p%x,%x", phy, lun);
14084 14089 (void) sprintf(wwn_str, "p%x", phy);
14085 14090 }
14086 14091
14087 14092 mdi_rtn = mdi_pi_alloc_compatible(pdip, nodename,
14088 14093 guid, lun_addr, compatible, ncompatible,
14089 14094 0, pip);
14090 14095 if (mdi_rtn == MDI_SUCCESS) {
14091 14096
14092 14097 if (mdi_prop_update_string(*pip, MDI_GUID,
14093 14098 guid) != DDI_SUCCESS) {
14094 14099 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14095 14100 "create prop for target %d lun %d (MDI_GUID)",
14096 14101 target, lun);
14097 14102 mdi_rtn = MDI_FAILURE;
14098 14103 goto virt_create_done;
14099 14104 }
14100 14105
14101 14106 if (mdi_prop_update_int(*pip, LUN_PROP,
14102 14107 lun) != DDI_SUCCESS) {
14103 14108 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14104 14109 "create prop for target %d lun %d (LUN_PROP)",
14105 14110 target, lun);
14106 14111 mdi_rtn = MDI_FAILURE;
14107 14112 goto virt_create_done;
14108 14113 }
14109 14114 lun64 = (int64_t)lun;
14110 14115 if (mdi_prop_update_int64(*pip, LUN64_PROP,
14111 14116 lun64) != DDI_SUCCESS) {
14112 14117 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14113 14118 "create prop for target %d (LUN64_PROP)",
14114 14119 target);
14115 14120 mdi_rtn = MDI_FAILURE;
14116 14121 goto virt_create_done;
14117 14122 }
14118 14123 if (mdi_prop_update_string_array(*pip, "compatible",
14119 14124 compatible, ncompatible) !=
14120 14125 DDI_PROP_SUCCESS) {
14121 14126 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14122 14127 "create prop for target %d lun %d (COMPATIBLE)",
14123 14128 target, lun);
14124 14129 mdi_rtn = MDI_FAILURE;
14125 14130 goto virt_create_done;
14126 14131 }
14127 14132 if (sas_wwn && (mdi_prop_update_string(*pip,
14128 14133 SCSI_ADDR_PROP_TARGET_PORT, wwn_str) != DDI_PROP_SUCCESS)) {
14129 14134 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14130 14135 "create prop for target %d lun %d "
14131 14136 "(target-port)", target, lun);
14132 14137 mdi_rtn = MDI_FAILURE;
14133 14138 goto virt_create_done;
14134 14139 } else if ((sas_wwn == 0) && (mdi_prop_update_int(*pip,
14135 14140 "sata-phy", phy) != DDI_PROP_SUCCESS)) {
14136 14141 /*
14137 14142 * Direct attached SATA device without DeviceName
14138 14143 */
14139 14144 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14140 14145 "create prop for SAS target %d lun %d "
14141 14146 "(sata-phy)", target, lun);
14142 14147 mdi_rtn = MDI_FAILURE;
14143 14148 goto virt_create_done;
14144 14149 }
14145 14150 mutex_enter(&mpt->m_mutex);
14146 14151
14147 14152 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14148 14153 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
14149 14154 (uint32_t)ptgt->m_devhdl;
14150 14155 rval = mptsas_get_sas_device_page0(mpt, page_address,
14151 14156 &dev_hdl, &dev_sas_wwn, &dev_info, &physport,
14152 14157 &phy_id, &pdev_hdl, &bay_num, &enclosure);
14153 14158 if (rval != DDI_SUCCESS) {
14154 14159 mutex_exit(&mpt->m_mutex);
14155 14160 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
14156 14161 "parent device for handle %d", page_address);
14157 14162 mdi_rtn = MDI_FAILURE;
14158 14163 goto virt_create_done;
14159 14164 }
14160 14165
14161 14166 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14162 14167 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl;
14163 14168 rval = mptsas_get_sas_device_page0(mpt, page_address,
14164 14169 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport,
14165 14170 &phy_id, &pdev_hdl, &bay_num, &enclosure);
14166 14171 if (rval != DDI_SUCCESS) {
14167 14172 mutex_exit(&mpt->m_mutex);
14168 14173 mptsas_log(mpt, CE_WARN, "mptsas unable to get"
14169 14174 "device info for handle %d", page_address);
14170 14175 mdi_rtn = MDI_FAILURE;
14171 14176 goto virt_create_done;
14172 14177 }
14173 14178
14174 14179 mutex_exit(&mpt->m_mutex);
14175 14180
14176 14181 /*
14177 14182 * If this device direct attached to the controller
14178 14183 * set the attached-port to the base wwid
14179 14184 */
14180 14185 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
14181 14186 != DEVINFO_DIRECT_ATTACHED) {
14182 14187 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
14183 14188 pdev_sas_wwn);
14184 14189 } else {
14185 14190 /*
14186 14191 * Update the iport's attached-port to guid
14187 14192 */
14188 14193 if (sas_wwn == 0) {
14189 14194 (void) sprintf(wwn_str, "p%x", phy);
14190 14195 } else {
14191 14196 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
14192 14197 }
14193 14198 if (ddi_prop_update_string(DDI_DEV_T_NONE,
14194 14199 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
14195 14200 DDI_PROP_SUCCESS) {
14196 14201 mptsas_log(mpt, CE_WARN,
14197 14202 "mptsas unable to create "
14198 14203 "property for iport target-port"
14199 14204 " %s (sas_wwn)",
14200 14205 wwn_str);
14201 14206 mdi_rtn = MDI_FAILURE;
14202 14207 goto virt_create_done;
14203 14208 }
14204 14209
14205 14210 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
14206 14211 mpt->un.m_base_wwid);
14207 14212 }
14208 14213
14209 14214 if (mdi_prop_update_string(*pip,
14210 14215 SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) !=
14211 14216 DDI_PROP_SUCCESS) {
14212 14217 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14213 14218 "property for iport attached-port %s (sas_wwn)",
14214 14219 attached_wwn_str);
14215 14220 mdi_rtn = MDI_FAILURE;
14216 14221 goto virt_create_done;
14217 14222 }
14218 14223
14219 14224
14220 14225 if (inq->inq_dtype == 0) {
14221 14226 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP);
14222 14227 /*
14223 14228 * set obp path for pathinfo
14224 14229 */
14225 14230 (void) snprintf(component, MAXPATHLEN,
14226 14231 "disk@%s", lun_addr);
14227 14232
14228 14233 if (mdi_pi_pathname_obp_set(*pip, component) !=
14229 14234 DDI_SUCCESS) {
14230 14235 mptsas_log(mpt, CE_WARN, "mpt_sas driver "
14231 14236 "unable to set obp-path for object %s",
14232 14237 component);
14233 14238 mdi_rtn = MDI_FAILURE;
14234 14239 goto virt_create_done;
14235 14240 }
14236 14241 }
14237 14242
14238 14243 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip;
14239 14244 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
14240 14245 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
14241 14246 if ((ndi_prop_update_int(DDI_DEV_T_NONE, *lun_dip,
14242 14247 "pm-capable", 1)) !=
14243 14248 DDI_PROP_SUCCESS) {
14244 14249 mptsas_log(mpt, CE_WARN, "mptsas driver"
14245 14250 "failed to create pm-capable "
14246 14251 "property, target %d", target);
14247 14252 mdi_rtn = MDI_FAILURE;
14248 14253 goto virt_create_done;
14249 14254 }
14250 14255 }
14251 14256 /*
14252 14257 * Create the phy-num property
14253 14258 */
14254 14259 if (mdi_prop_update_int(*pip, "phy-num",
14255 14260 ptgt->m_phynum) != DDI_SUCCESS) {
14256 14261 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14257 14262 "create phy-num property for target %d lun %d",
14258 14263 target, lun);
14259 14264 mdi_rtn = MDI_FAILURE;
14260 14265 goto virt_create_done;
14261 14266 }
14262 14267 NDBG20(("new path:%s onlining,", MDI_PI(*pip)->pi_addr));
14263 14268 mdi_rtn = mdi_pi_online(*pip, 0);
14264 14269 if (mdi_rtn == MDI_SUCCESS) {
14265 14270 mutex_enter(&mpt->m_mutex);
14266 14271 ptgt->m_led_status = 0;
14267 14272 (void) mptsas_flush_led_status(mpt, ptgt);
14268 14273 mutex_exit(&mpt->m_mutex);
14269 14274 }
14270 14275 if (mdi_rtn == MDI_NOT_SUPPORTED) {
14271 14276 mdi_rtn = MDI_FAILURE;
14272 14277 }
14273 14278 virt_create_done:
14274 14279 if (*pip && mdi_rtn != MDI_SUCCESS) {
14275 14280 (void) mdi_pi_free(*pip, 0);
14276 14281 *pip = NULL;
14277 14282 *lun_dip = NULL;
14278 14283 }
14279 14284 }
14280 14285
14281 14286 scsi_hba_nodename_compatible_free(nodename, compatible);
14282 14287 if (lun_addr != NULL) {
14283 14288 kmem_free(lun_addr, SCSI_MAXNAMELEN);
14284 14289 }
14285 14290 if (wwn_str != NULL) {
14286 14291 kmem_free(wwn_str, MPTSAS_WWN_STRLEN);
14287 14292 }
14288 14293 if (component != NULL) {
14289 14294 kmem_free(component, MAXPATHLEN);
14290 14295 }
14291 14296
14292 14297 return ((mdi_rtn == MDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
14293 14298 }
14294 14299
14295 14300 static int
14296 14301 mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *inq,
14297 14302 char *guid, dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun)
14298 14303 {
14299 14304 int target;
14300 14305 int rval;
14301 14306 int ndi_rtn = NDI_FAILURE;
14302 14307 uint64_t be_sas_wwn;
14303 14308 char *nodename = NULL;
14304 14309 char **compatible = NULL;
14305 14310 int ncompatible = 0;
14306 14311 int instance = 0;
14307 14312 mptsas_t *mpt = DIP2MPT(pdip);
14308 14313 char *wwn_str = NULL;
14309 14314 char *component = NULL;
14310 14315 char *attached_wwn_str = NULL;
14311 14316 uint8_t phy = 0xFF;
14312 14317 uint64_t sas_wwn;
14313 14318 uint32_t devinfo;
14314 14319 uint16_t dev_hdl;
14315 14320 uint16_t pdev_hdl;
14316 14321 uint64_t pdev_sas_wwn;
14317 14322 uint64_t dev_sas_wwn;
14318 14323 uint32_t pdev_info;
14319 14324 uint8_t physport;
14320 14325 uint8_t phy_id;
14321 14326 uint32_t page_address;
14322 14327 uint16_t bay_num, enclosure;
14323 14328 char pdev_wwn_str[MPTSAS_WWN_STRLEN];
14324 14329 uint32_t dev_info;
14325 14330 int64_t lun64 = 0;
14326 14331
14327 14332 mutex_enter(&mpt->m_mutex);
14328 14333 target = ptgt->m_devhdl;
14329 14334 sas_wwn = ptgt->m_sas_wwn;
14330 14335 devinfo = ptgt->m_deviceinfo;
14331 14336 phy = ptgt->m_phynum;
14332 14337 mutex_exit(&mpt->m_mutex);
14333 14338
14334 14339 /*
14335 14340 * generate compatible property with binding-set "mpt"
14336 14341 */
14337 14342 scsi_hba_nodename_compatible_get(inq, NULL, inq->inq_dtype, NULL,
14338 14343 &nodename, &compatible, &ncompatible);
14339 14344
14340 14345 /*
14341 14346 * if nodename can't be determined then print a message and skip it
14342 14347 */
14343 14348 if (nodename == NULL) {
14344 14349 mptsas_log(mpt, CE_WARN, "mptsas found no compatible driver "
14345 14350 "for target %d lun %d", target, lun);
14346 14351 return (DDI_FAILURE);
14347 14352 }
14348 14353
14349 14354 ndi_rtn = ndi_devi_alloc(pdip, nodename,
14350 14355 DEVI_SID_NODEID, lun_dip);
14351 14356
14352 14357 /*
14353 14358 * if lun alloc success, set props
14354 14359 */
14355 14360 if (ndi_rtn == NDI_SUCCESS) {
14356 14361
14357 14362 if (ndi_prop_update_int(DDI_DEV_T_NONE,
14358 14363 *lun_dip, LUN_PROP, lun) !=
14359 14364 DDI_PROP_SUCCESS) {
14360 14365 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14361 14366 "property for target %d lun %d (LUN_PROP)",
14362 14367 target, lun);
14363 14368 ndi_rtn = NDI_FAILURE;
14364 14369 goto phys_create_done;
14365 14370 }
14366 14371
14367 14372 lun64 = (int64_t)lun;
14368 14373 if (ndi_prop_update_int64(DDI_DEV_T_NONE,
14369 14374 *lun_dip, LUN64_PROP, lun64) !=
14370 14375 DDI_PROP_SUCCESS) {
14371 14376 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14372 14377 "property for target %d lun64 %d (LUN64_PROP)",
14373 14378 target, lun);
14374 14379 ndi_rtn = NDI_FAILURE;
14375 14380 goto phys_create_done;
14376 14381 }
14377 14382 if (ndi_prop_update_string_array(DDI_DEV_T_NONE,
14378 14383 *lun_dip, "compatible", compatible, ncompatible)
14379 14384 != DDI_PROP_SUCCESS) {
14380 14385 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14381 14386 "property for target %d lun %d (COMPATIBLE)",
14382 14387 target, lun);
14383 14388 ndi_rtn = NDI_FAILURE;
14384 14389 goto phys_create_done;
14385 14390 }
14386 14391
14387 14392 /*
14388 14393 * We need the SAS WWN for non-multipath devices, so
14389 14394 * we'll use the same property as that multipathing
14390 14395 * devices need to present for MPAPI. If we don't have
14391 14396 * a WWN (e.g. parallel SCSI), don't create the prop.
14392 14397 */
14393 14398 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP);
14394 14399 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
14395 14400 if (sas_wwn && ndi_prop_update_string(DDI_DEV_T_NONE,
14396 14401 *lun_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str)
14397 14402 != DDI_PROP_SUCCESS) {
14398 14403 mptsas_log(mpt, CE_WARN, "mptsas unable to "
14399 14404 "create property for SAS target %d lun %d "
14400 14405 "(target-port)", target, lun);
14401 14406 ndi_rtn = NDI_FAILURE;
14402 14407 goto phys_create_done;
14403 14408 }
14404 14409
14405 14410 be_sas_wwn = BE_64(sas_wwn);
14406 14411 if (sas_wwn && ndi_prop_update_byte_array(
14407 14412 DDI_DEV_T_NONE, *lun_dip, "port-wwn",
14408 14413 (uchar_t *)&be_sas_wwn, 8) != DDI_PROP_SUCCESS) {
14409 14414 mptsas_log(mpt, CE_WARN, "mptsas unable to "
14410 14415 "create property for SAS target %d lun %d "
14411 14416 "(port-wwn)", target, lun);
14412 14417 ndi_rtn = NDI_FAILURE;
14413 14418 goto phys_create_done;
14414 14419 } else if ((sas_wwn == 0) && (ndi_prop_update_int(
14415 14420 DDI_DEV_T_NONE, *lun_dip, "sata-phy", phy) !=
14416 14421 DDI_PROP_SUCCESS)) {
14417 14422 /*
14418 14423 * Direct attached SATA device without DeviceName
14419 14424 */
14420 14425 mptsas_log(mpt, CE_WARN, "mptsas unable to "
14421 14426 "create property for SAS target %d lun %d "
14422 14427 "(sata-phy)", target, lun);
14423 14428 ndi_rtn = NDI_FAILURE;
14424 14429 goto phys_create_done;
14425 14430 }
14426 14431
14427 14432 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
14428 14433 *lun_dip, SAS_PROP) != DDI_PROP_SUCCESS) {
14429 14434 mptsas_log(mpt, CE_WARN, "mptsas unable to"
14430 14435 "create property for SAS target %d lun %d"
14431 14436 " (SAS_PROP)", target, lun);
14432 14437 ndi_rtn = NDI_FAILURE;
14433 14438 goto phys_create_done;
14434 14439 }
14435 14440 if (guid && (ndi_prop_update_string(DDI_DEV_T_NONE,
14436 14441 *lun_dip, NDI_GUID, guid) != DDI_SUCCESS)) {
14437 14442 mptsas_log(mpt, CE_WARN, "mptsas unable "
14438 14443 "to create guid property for target %d "
14439 14444 "lun %d", target, lun);
14440 14445 ndi_rtn = NDI_FAILURE;
14441 14446 goto phys_create_done;
14442 14447 }
14443 14448
14444 14449 /*
14445 14450 * The following code is to set properties for SM-HBA support,
14446 14451 * it doesn't apply to RAID volumes
14447 14452 */
14448 14453 if (ptgt->m_phymask == 0)
14449 14454 goto phys_raid_lun;
14450 14455
14451 14456 mutex_enter(&mpt->m_mutex);
14452 14457
14453 14458 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14454 14459 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
14455 14460 (uint32_t)ptgt->m_devhdl;
14456 14461 rval = mptsas_get_sas_device_page0(mpt, page_address,
14457 14462 &dev_hdl, &dev_sas_wwn, &dev_info,
14458 14463 &physport, &phy_id, &pdev_hdl,
14459 14464 &bay_num, &enclosure);
14460 14465 if (rval != DDI_SUCCESS) {
14461 14466 mutex_exit(&mpt->m_mutex);
14462 14467 mptsas_log(mpt, CE_WARN, "mptsas unable to get"
14463 14468 "parent device for handle %d.", page_address);
14464 14469 ndi_rtn = NDI_FAILURE;
14465 14470 goto phys_create_done;
14466 14471 }
14467 14472
14468 14473 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14469 14474 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl;
14470 14475 rval = mptsas_get_sas_device_page0(mpt, page_address,
14471 14476 &dev_hdl, &pdev_sas_wwn, &pdev_info,
14472 14477 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure);
14473 14478 if (rval != DDI_SUCCESS) {
14474 14479 mutex_exit(&mpt->m_mutex);
14475 14480 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14476 14481 "device for handle %d.", page_address);
14477 14482 ndi_rtn = NDI_FAILURE;
14478 14483 goto phys_create_done;
14479 14484 }
14480 14485
14481 14486 mutex_exit(&mpt->m_mutex);
14482 14487
14483 14488 /*
14484 14489 * If this device direct attached to the controller
14485 14490 * set the attached-port to the base wwid
14486 14491 */
14487 14492 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
14488 14493 != DEVINFO_DIRECT_ATTACHED) {
14489 14494 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
14490 14495 pdev_sas_wwn);
14491 14496 } else {
14492 14497 /*
14493 14498 * Update the iport's attached-port to guid
14494 14499 */
14495 14500 if (sas_wwn == 0) {
14496 14501 (void) sprintf(wwn_str, "p%x", phy);
14497 14502 } else {
14498 14503 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
14499 14504 }
14500 14505 if (ddi_prop_update_string(DDI_DEV_T_NONE,
14501 14506 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
14502 14507 DDI_PROP_SUCCESS) {
14503 14508 mptsas_log(mpt, CE_WARN,
14504 14509 "mptsas unable to create "
14505 14510 "property for iport target-port"
14506 14511 " %s (sas_wwn)",
14507 14512 wwn_str);
14508 14513 ndi_rtn = NDI_FAILURE;
14509 14514 goto phys_create_done;
14510 14515 }
14511 14516
14512 14517 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
14513 14518 mpt->un.m_base_wwid);
14514 14519 }
14515 14520
14516 14521 if (ndi_prop_update_string(DDI_DEV_T_NONE,
14517 14522 *lun_dip, SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) !=
14518 14523 DDI_PROP_SUCCESS) {
14519 14524 mptsas_log(mpt, CE_WARN,
14520 14525 "mptsas unable to create "
14521 14526 "property for iport attached-port %s (sas_wwn)",
14522 14527 attached_wwn_str);
14523 14528 ndi_rtn = NDI_FAILURE;
14524 14529 goto phys_create_done;
14525 14530 }
14526 14531
14527 14532 if (IS_SATA_DEVICE(dev_info)) {
14528 14533 if (ndi_prop_update_string(DDI_DEV_T_NONE,
14529 14534 *lun_dip, MPTSAS_VARIANT, "sata") !=
14530 14535 DDI_PROP_SUCCESS) {
14531 14536 mptsas_log(mpt, CE_WARN,
14532 14537 "mptsas unable to create "
14533 14538 "property for device variant ");
14534 14539 ndi_rtn = NDI_FAILURE;
14535 14540 goto phys_create_done;
14536 14541 }
14537 14542 }
14538 14543
14539 14544 if (IS_ATAPI_DEVICE(dev_info)) {
14540 14545 if (ndi_prop_update_string(DDI_DEV_T_NONE,
14541 14546 *lun_dip, MPTSAS_VARIANT, "atapi") !=
14542 14547 DDI_PROP_SUCCESS) {
14543 14548 mptsas_log(mpt, CE_WARN,
14544 14549 "mptsas unable to create "
14545 14550 "property for device variant ");
14546 14551 ndi_rtn = NDI_FAILURE;
14547 14552 goto phys_create_done;
14548 14553 }
14549 14554 }
14550 14555
14551 14556 phys_raid_lun:
14552 14557 /*
14553 14558 * if this is a SAS controller, and the target is a SATA
14554 14559 * drive, set the 'pm-capable' property for sd and if on
14555 14560 * an OPL platform, also check if this is an ATAPI
14556 14561 * device.
14557 14562 */
14558 14563 instance = ddi_get_instance(mpt->m_dip);
14559 14564 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
14560 14565 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
14561 14566 NDBG2(("mptsas%d: creating pm-capable property, "
14562 14567 "target %d", instance, target));
14563 14568
14564 14569 if ((ndi_prop_update_int(DDI_DEV_T_NONE,
14565 14570 *lun_dip, "pm-capable", 1)) !=
14566 14571 DDI_PROP_SUCCESS) {
14567 14572 mptsas_log(mpt, CE_WARN, "mptsas "
14568 14573 "failed to create pm-capable "
14569 14574 "property, target %d", target);
14570 14575 ndi_rtn = NDI_FAILURE;
14571 14576 goto phys_create_done;
14572 14577 }
14573 14578
14574 14579 }
14575 14580
14576 14581 if ((inq->inq_dtype == 0) || (inq->inq_dtype == 5)) {
14577 14582 /*
14578 14583 * add 'obp-path' properties for devinfo
14579 14584 */
14580 14585 bzero(wwn_str, sizeof (wwn_str));
14581 14586 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn);
14582 14587 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP);
14583 14588 if (guid) {
14584 14589 (void) snprintf(component, MAXPATHLEN,
14585 14590 "disk@w%s,%x", wwn_str, lun);
14586 14591 } else {
14587 14592 (void) snprintf(component, MAXPATHLEN,
14588 14593 "disk@p%x,%x", phy, lun);
14589 14594 }
14590 14595 if (ddi_pathname_obp_set(*lun_dip, component)
14591 14596 != DDI_SUCCESS) {
14592 14597 mptsas_log(mpt, CE_WARN, "mpt_sas driver "
14593 14598 "unable to set obp-path for SAS "
14594 14599 "object %s", component);
14595 14600 ndi_rtn = NDI_FAILURE;
14596 14601 goto phys_create_done;
14597 14602 }
14598 14603 }
14599 14604 /*
14600 14605 * Create the phy-num property for non-raid disk
14601 14606 */
14602 14607 if (ptgt->m_phymask != 0) {
14603 14608 if (ndi_prop_update_int(DDI_DEV_T_NONE,
14604 14609 *lun_dip, "phy-num", ptgt->m_phynum) !=
14605 14610 DDI_PROP_SUCCESS) {
14606 14611 mptsas_log(mpt, CE_WARN, "mptsas driver "
14607 14612 "failed to create phy-num property for "
14608 14613 "target %d", target);
14609 14614 ndi_rtn = NDI_FAILURE;
14610 14615 goto phys_create_done;
14611 14616 }
14612 14617 }
14613 14618 phys_create_done:
14614 14619 /*
14615 14620 * If props were setup ok, online the lun
14616 14621 */
14617 14622 if (ndi_rtn == NDI_SUCCESS) {
14618 14623 /*
14619 14624 * Try to online the new node
14620 14625 */
14621 14626 ndi_rtn = ndi_devi_online(*lun_dip, NDI_ONLINE_ATTACH);
14622 14627 }
14623 14628 if (ndi_rtn == NDI_SUCCESS) {
14624 14629 mutex_enter(&mpt->m_mutex);
14625 14630 ptgt->m_led_status = 0;
14626 14631 (void) mptsas_flush_led_status(mpt, ptgt);
14627 14632 mutex_exit(&mpt->m_mutex);
14628 14633 }
14629 14634
14630 14635 /*
14631 14636 * If success set rtn flag, else unwire alloc'd lun
14632 14637 */
14633 14638 if (ndi_rtn != NDI_SUCCESS) {
14634 14639 NDBG12(("mptsas driver unable to online "
14635 14640 "target %d lun %d", target, lun));
14636 14641 ndi_prop_remove_all(*lun_dip);
14637 14642 (void) ndi_devi_free(*lun_dip);
14638 14643 *lun_dip = NULL;
14639 14644 }
14640 14645 }
14641 14646
14642 14647 scsi_hba_nodename_compatible_free(nodename, compatible);
14643 14648
14644 14649 if (wwn_str != NULL) {
14645 14650 kmem_free(wwn_str, MPTSAS_WWN_STRLEN);
14646 14651 }
14647 14652 if (component != NULL) {
14648 14653 kmem_free(component, MAXPATHLEN);
14649 14654 }
14650 14655
14651 14656
14652 14657 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
14653 14658 }
14654 14659
14655 14660 static int
14656 14661 mptsas_probe_smp(dev_info_t *pdip, uint64_t wwn)
14657 14662 {
14658 14663 mptsas_t *mpt = DIP2MPT(pdip);
14659 14664 struct smp_device smp_sd;
14660 14665
14661 14666 /* XXX An HBA driver should not be allocating an smp_device. */
14662 14667 bzero(&smp_sd, sizeof (struct smp_device));
14663 14668 smp_sd.smp_sd_address.smp_a_hba_tran = mpt->m_smptran;
14664 14669 bcopy(&wwn, smp_sd.smp_sd_address.smp_a_wwn, SAS_WWN_BYTE_SIZE);
14665 14670
14666 14671 if (smp_probe(&smp_sd) != DDI_PROBE_SUCCESS)
14667 14672 return (NDI_FAILURE);
14668 14673 return (NDI_SUCCESS);
14669 14674 }
14670 14675
14671 14676 static int
14672 14677 mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, dev_info_t **smp_dip)
14673 14678 {
14674 14679 mptsas_t *mpt = DIP2MPT(pdip);
14675 14680 mptsas_smp_t *psmp = NULL;
14676 14681 int rval;
14677 14682 int phymask;
14678 14683
14679 14684 /*
14680 14685 * Get the physical port associated to the iport
14681 14686 * PHYMASK TODO
14682 14687 */
14683 14688 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
14684 14689 "phymask", 0);
14685 14690 /*
14686 14691 * Find the smp node in hash table with specified sas address and
14687 14692 * physical port
14688 14693 */
14689 14694 psmp = mptsas_wwid_to_psmp(mpt, phymask, sas_wwn);
14690 14695 if (psmp == NULL) {
14691 14696 return (DDI_FAILURE);
14692 14697 }
14693 14698
14694 14699 rval = mptsas_online_smp(pdip, psmp, smp_dip);
14695 14700
14696 14701 return (rval);
14697 14702 }
14698 14703
14699 14704 static int
14700 14705 mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
14701 14706 dev_info_t **smp_dip)
14702 14707 {
14703 14708 char wwn_str[MPTSAS_WWN_STRLEN];
14704 14709 char attached_wwn_str[MPTSAS_WWN_STRLEN];
14705 14710 int ndi_rtn = NDI_FAILURE;
14706 14711 int rval = 0;
14707 14712 mptsas_smp_t dev_info;
14708 14713 uint32_t page_address;
14709 14714 mptsas_t *mpt = DIP2MPT(pdip);
14710 14715 uint16_t dev_hdl;
14711 14716 uint64_t sas_wwn;
14712 14717 uint64_t smp_sas_wwn;
14713 14718 uint8_t physport;
14714 14719 uint8_t phy_id;
14715 14720 uint16_t pdev_hdl;
14716 14721 uint8_t numphys = 0;
14717 14722 uint16_t i = 0;
14718 14723 char phymask[MPTSAS_MAX_PHYS];
14719 14724 char *iport = NULL;
14720 14725 mptsas_phymask_t phy_mask = 0;
14721 14726 uint16_t attached_devhdl;
14722 14727 uint16_t bay_num, enclosure;
14723 14728
14724 14729 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_sasaddr);
14725 14730
14726 14731 /*
14727 14732 * Probe smp device, prevent the node of removed device from being
14728 14733 * configured succesfully
14729 14734 */
14730 14735 if (mptsas_probe_smp(pdip, smp_node->m_sasaddr) != NDI_SUCCESS) {
14731 14736 return (DDI_FAILURE);
14732 14737 }
14733 14738
14734 14739 if ((*smp_dip = mptsas_find_smp_child(pdip, wwn_str)) != NULL) {
14735 14740 return (DDI_SUCCESS);
14736 14741 }
14737 14742
14738 14743 ndi_rtn = ndi_devi_alloc(pdip, "smp", DEVI_SID_NODEID, smp_dip);
14739 14744
14740 14745 /*
14741 14746 * if lun alloc success, set props
14742 14747 */
14743 14748 if (ndi_rtn == NDI_SUCCESS) {
14744 14749 /*
14745 14750 * Set the flavor of the child to be SMP flavored
14746 14751 */
14747 14752 ndi_flavor_set(*smp_dip, SCSA_FLAVOR_SMP);
14748 14753
14749 14754 if (ndi_prop_update_string(DDI_DEV_T_NONE,
14750 14755 *smp_dip, SMP_WWN, wwn_str) !=
14751 14756 DDI_PROP_SUCCESS) {
14752 14757 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14753 14758 "property for smp device %s (sas_wwn)",
14754 14759 wwn_str);
14755 14760 ndi_rtn = NDI_FAILURE;
14756 14761 goto smp_create_done;
14757 14762 }
14758 14763 (void) sprintf(wwn_str, "w%"PRIx64, smp_node->m_sasaddr);
14759 14764 if (ndi_prop_update_string(DDI_DEV_T_NONE,
14760 14765 *smp_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str) !=
14761 14766 DDI_PROP_SUCCESS) {
14762 14767 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14763 14768 "property for iport target-port %s (sas_wwn)",
14764 14769 wwn_str);
14765 14770 ndi_rtn = NDI_FAILURE;
14766 14771 goto smp_create_done;
14767 14772 }
14768 14773
14769 14774 mutex_enter(&mpt->m_mutex);
14770 14775
14771 14776 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL &
14772 14777 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | smp_node->m_devhdl;
14773 14778 rval = mptsas_get_sas_expander_page0(mpt, page_address,
14774 14779 &dev_info);
14775 14780 if (rval != DDI_SUCCESS) {
14776 14781 mutex_exit(&mpt->m_mutex);
14777 14782 mptsas_log(mpt, CE_WARN,
14778 14783 "mptsas unable to get expander "
14779 14784 "parent device info for %x", page_address);
14780 14785 ndi_rtn = NDI_FAILURE;
14781 14786 goto smp_create_done;
14782 14787 }
14783 14788
14784 14789 smp_node->m_pdevhdl = dev_info.m_pdevhdl;
14785 14790 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14786 14791 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
14787 14792 (uint32_t)dev_info.m_pdevhdl;
14788 14793 rval = mptsas_get_sas_device_page0(mpt, page_address,
14789 14794 &dev_hdl, &sas_wwn, &smp_node->m_pdevinfo,
14790 14795 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure);
14791 14796 if (rval != DDI_SUCCESS) {
14792 14797 mutex_exit(&mpt->m_mutex);
14793 14798 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
14794 14799 "device info for %x", page_address);
14795 14800 ndi_rtn = NDI_FAILURE;
14796 14801 goto smp_create_done;
14797 14802 }
14798 14803
14799 14804 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14800 14805 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
14801 14806 (uint32_t)dev_info.m_devhdl;
14802 14807 rval = mptsas_get_sas_device_page0(mpt, page_address,
14803 14808 &dev_hdl, &smp_sas_wwn, &smp_node->m_deviceinfo,
14804 14809 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure);
14805 14810 if (rval != DDI_SUCCESS) {
14806 14811 mutex_exit(&mpt->m_mutex);
14807 14812 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
14808 14813 "device info for %x", page_address);
14809 14814 ndi_rtn = NDI_FAILURE;
14810 14815 goto smp_create_done;
14811 14816 }
14812 14817 mutex_exit(&mpt->m_mutex);
14813 14818
14814 14819 /*
14815 14820 * If this smp direct attached to the controller
14816 14821 * set the attached-port to the base wwid
14817 14822 */
14818 14823 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
14819 14824 != DEVINFO_DIRECT_ATTACHED) {
14820 14825 (void) sprintf(attached_wwn_str, "w%016"PRIx64,
14821 14826 sas_wwn);
14822 14827 } else {
14823 14828 (void) sprintf(attached_wwn_str, "w%016"PRIx64,
14824 14829 mpt->un.m_base_wwid);
14825 14830 }
14826 14831
14827 14832 if (ndi_prop_update_string(DDI_DEV_T_NONE,
14828 14833 *smp_dip, SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwn_str) !=
14829 14834 DDI_PROP_SUCCESS) {
14830 14835 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14831 14836 "property for smp attached-port %s (sas_wwn)",
14832 14837 attached_wwn_str);
14833 14838 ndi_rtn = NDI_FAILURE;
14834 14839 goto smp_create_done;
14835 14840 }
14836 14841
14837 14842 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
14838 14843 *smp_dip, SMP_PROP) != DDI_PROP_SUCCESS) {
14839 14844 mptsas_log(mpt, CE_WARN, "mptsas unable to "
14840 14845 "create property for SMP %s (SMP_PROP) ",
14841 14846 wwn_str);
14842 14847 ndi_rtn = NDI_FAILURE;
14843 14848 goto smp_create_done;
14844 14849 }
14845 14850
14846 14851 /*
14847 14852 * check the smp to see whether it direct
14848 14853 * attached to the controller
14849 14854 */
14850 14855 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
14851 14856 != DEVINFO_DIRECT_ATTACHED) {
14852 14857 goto smp_create_done;
14853 14858 }
14854 14859 numphys = ddi_prop_get_int(DDI_DEV_T_ANY, pdip,
14855 14860 DDI_PROP_DONTPASS, MPTSAS_NUM_PHYS, -1);
14856 14861 if (numphys > 0) {
14857 14862 goto smp_create_done;
14858 14863 }
14859 14864 /*
14860 14865 * this iport is an old iport, we need to
14861 14866 * reconfig the props for it.
14862 14867 */
14863 14868 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip,
14864 14869 MPTSAS_VIRTUAL_PORT, 0) !=
14865 14870 DDI_PROP_SUCCESS) {
14866 14871 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
14867 14872 MPTSAS_VIRTUAL_PORT);
14868 14873 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
14869 14874 "prop update failed");
14870 14875 goto smp_create_done;
14871 14876 }
14872 14877
14873 14878 mutex_enter(&mpt->m_mutex);
14874 14879 numphys = 0;
14875 14880 iport = ddi_get_name_addr(pdip);
14876 14881 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
14877 14882 bzero(phymask, sizeof (phymask));
14878 14883 (void) sprintf(phymask,
14879 14884 "%x", mpt->m_phy_info[i].phy_mask);
14880 14885 if (strcmp(phymask, iport) == 0) {
14881 14886 phy_mask = mpt->m_phy_info[i].phy_mask;
14882 14887 break;
14883 14888 }
14884 14889 }
14885 14890
14886 14891 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
14887 14892 if ((phy_mask >> i) & 0x01) {
14888 14893 numphys++;
14889 14894 }
14890 14895 }
14891 14896 /*
|
↓ open down ↓ |
8923 lines elided |
↑ open up ↑ |
14892 14897 * Update PHY info for smhba
14893 14898 */
14894 14899 if (mptsas_smhba_phy_init(mpt)) {
14895 14900 mutex_exit(&mpt->m_mutex);
14896 14901 mptsas_log(mpt, CE_WARN, "mptsas phy update "
14897 14902 "failed");
14898 14903 goto smp_create_done;
14899 14904 }
14900 14905 mutex_exit(&mpt->m_mutex);
14901 14906
14902 - mptsas_smhba_set_phy_props(mpt, iport, pdip,
14903 - numphys, &attached_devhdl);
14907 + mptsas_smhba_set_all_phy_props(mpt, pdip, numphys, phy_mask,
14908 + &attached_devhdl);
14904 14909
14905 14910 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip,
14906 14911 MPTSAS_NUM_PHYS, numphys) !=
14907 14912 DDI_PROP_SUCCESS) {
14908 14913 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
14909 14914 MPTSAS_NUM_PHYS);
14910 14915 mptsas_log(mpt, CE_WARN, "mptsas update "
14911 14916 "num phys props failed");
14912 14917 goto smp_create_done;
14913 14918 }
14914 14919 /*
14915 14920 * Add parent's props for SMHBA support
14916 14921 */
14917 14922 if (ddi_prop_update_string(DDI_DEV_T_NONE, pdip,
14918 14923 SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
14919 14924 DDI_PROP_SUCCESS) {
14920 14925 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
14921 14926 SCSI_ADDR_PROP_ATTACHED_PORT);
14922 14927 mptsas_log(mpt, CE_WARN, "mptsas update iport"
14923 14928 "attached-port failed");
14924 14929 goto smp_create_done;
14925 14930 }
14926 14931
14927 14932 smp_create_done:
14928 14933 /*
14929 14934 * If props were setup ok, online the lun
14930 14935 */
14931 14936 if (ndi_rtn == NDI_SUCCESS) {
14932 14937 /*
14933 14938 * Try to online the new node
14934 14939 */
14935 14940 ndi_rtn = ndi_devi_online(*smp_dip, NDI_ONLINE_ATTACH);
14936 14941 }
14937 14942
14938 14943 /*
14939 14944 * If success set rtn flag, else unwire alloc'd lun
14940 14945 */
14941 14946 if (ndi_rtn != NDI_SUCCESS) {
14942 14947 NDBG12(("mptsas unable to online "
14943 14948 "SMP target %s", wwn_str));
14944 14949 ndi_prop_remove_all(*smp_dip);
14945 14950 (void) ndi_devi_free(*smp_dip);
14946 14951 }
14947 14952 }
14948 14953
14949 14954 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
14950 14955 }
14951 14956
14952 14957 /* smp transport routine */
14953 14958 static int mptsas_smp_start(struct smp_pkt *smp_pkt)
14954 14959 {
14955 14960 uint64_t wwn;
14956 14961 Mpi2SmpPassthroughRequest_t req;
14957 14962 Mpi2SmpPassthroughReply_t rep;
14958 14963 uint32_t direction = 0;
14959 14964 mptsas_t *mpt;
14960 14965 int ret;
14961 14966 uint64_t tmp64;
14962 14967
14963 14968 mpt = (mptsas_t *)smp_pkt->smp_pkt_address->
14964 14969 smp_a_hba_tran->smp_tran_hba_private;
14965 14970
14966 14971 bcopy(smp_pkt->smp_pkt_address->smp_a_wwn, &wwn, SAS_WWN_BYTE_SIZE);
14967 14972 /*
14968 14973 * Need to compose a SMP request message
14969 14974 * and call mptsas_do_passthru() function
14970 14975 */
14971 14976 bzero(&req, sizeof (req));
14972 14977 bzero(&rep, sizeof (rep));
14973 14978 req.PassthroughFlags = 0;
14974 14979 req.PhysicalPort = 0xff;
14975 14980 req.ChainOffset = 0;
14976 14981 req.Function = MPI2_FUNCTION_SMP_PASSTHROUGH;
14977 14982
14978 14983 if ((smp_pkt->smp_pkt_reqsize & 0xffff0000ul) != 0) {
14979 14984 smp_pkt->smp_pkt_reason = ERANGE;
14980 14985 return (DDI_FAILURE);
14981 14986 }
14982 14987 req.RequestDataLength = LE_16((uint16_t)(smp_pkt->smp_pkt_reqsize - 4));
14983 14988
14984 14989 req.MsgFlags = 0;
14985 14990 tmp64 = LE_64(wwn);
14986 14991 bcopy(&tmp64, &req.SASAddress, SAS_WWN_BYTE_SIZE);
14987 14992 if (smp_pkt->smp_pkt_rspsize > 0) {
14988 14993 direction |= MPTSAS_PASS_THRU_DIRECTION_READ;
14989 14994 }
14990 14995 if (smp_pkt->smp_pkt_reqsize > 0) {
14991 14996 direction |= MPTSAS_PASS_THRU_DIRECTION_WRITE;
14992 14997 }
14993 14998
14994 14999 mutex_enter(&mpt->m_mutex);
14995 15000 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep,
14996 15001 (uint8_t *)smp_pkt->smp_pkt_rsp,
14997 15002 offsetof(Mpi2SmpPassthroughRequest_t, SGL), sizeof (rep),
14998 15003 smp_pkt->smp_pkt_rspsize - 4, direction,
14999 15004 (uint8_t *)smp_pkt->smp_pkt_req, smp_pkt->smp_pkt_reqsize - 4,
15000 15005 smp_pkt->smp_pkt_timeout, FKIOCTL);
15001 15006 mutex_exit(&mpt->m_mutex);
15002 15007 if (ret != 0) {
15003 15008 cmn_err(CE_WARN, "smp_start do passthru error %d", ret);
15004 15009 smp_pkt->smp_pkt_reason = (uchar_t)(ret);
15005 15010 return (DDI_FAILURE);
15006 15011 }
15007 15012 /* do passthrough success, check the smp status */
15008 15013 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
15009 15014 switch (LE_16(rep.IOCStatus)) {
15010 15015 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
15011 15016 smp_pkt->smp_pkt_reason = ENODEV;
15012 15017 break;
15013 15018 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
15014 15019 smp_pkt->smp_pkt_reason = EOVERFLOW;
15015 15020 break;
15016 15021 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
15017 15022 smp_pkt->smp_pkt_reason = EIO;
15018 15023 break;
15019 15024 default:
15020 15025 mptsas_log(mpt, CE_NOTE, "smp_start: get unknown ioc"
15021 15026 "status:%x", LE_16(rep.IOCStatus));
15022 15027 smp_pkt->smp_pkt_reason = EIO;
15023 15028 break;
15024 15029 }
15025 15030 return (DDI_FAILURE);
15026 15031 }
15027 15032 if (rep.SASStatus != MPI2_SASSTATUS_SUCCESS) {
15028 15033 mptsas_log(mpt, CE_NOTE, "smp_start: get error SAS status:%x",
15029 15034 rep.SASStatus);
15030 15035 smp_pkt->smp_pkt_reason = EIO;
15031 15036 return (DDI_FAILURE);
15032 15037 }
15033 15038
15034 15039 return (DDI_SUCCESS);
15035 15040 }
15036 15041
15037 15042 /*
15038 15043 * If we didn't get a match, we need to get sas page0 for each device, and
15039 15044 * untill we get a match. If failed, return NULL
15040 15045 */
15041 15046 static mptsas_target_t *
15042 15047 mptsas_phy_to_tgt(mptsas_t *mpt, int phymask, uint8_t phy)
15043 15048 {
15044 15049 int i, j = 0;
15045 15050 int rval = 0;
15046 15051 uint16_t cur_handle;
15047 15052 uint32_t page_address;
15048 15053 mptsas_target_t *ptgt = NULL;
15049 15054
15050 15055 /*
15051 15056 * PHY named device must be direct attached and attaches to
15052 15057 * narrow port, if the iport is not parent of the device which
15053 15058 * we are looking for.
15054 15059 */
15055 15060 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
15056 15061 if ((1 << i) & phymask)
15057 15062 j++;
15058 15063 }
15059 15064
15060 15065 if (j > 1)
15061 15066 return (NULL);
15062 15067
15063 15068 /*
15064 15069 * Must be a narrow port and single device attached to the narrow port
15065 15070 * So the physical port num of device which is equal to the iport's
15066 15071 * port num is the device what we are looking for.
15067 15072 */
15068 15073
15069 15074 if (mpt->m_phy_info[phy].phy_mask != phymask)
15070 15075 return (NULL);
15071 15076
15072 15077 mutex_enter(&mpt->m_mutex);
15073 15078
15074 15079 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
15075 15080 MPTSAS_HASH_FIRST);
15076 15081 while (ptgt != NULL) {
15077 15082 if ((ptgt->m_sas_wwn == 0) && (ptgt->m_phynum == phy)) {
15078 15083 mutex_exit(&mpt->m_mutex);
15079 15084 return (ptgt);
15080 15085 }
15081 15086
15082 15087 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
15083 15088 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
15084 15089 }
15085 15090
15086 15091 if (mpt->m_done_traverse_dev) {
15087 15092 mutex_exit(&mpt->m_mutex);
15088 15093 return (NULL);
15089 15094 }
15090 15095
15091 15096 /* If didn't get a match, come here */
15092 15097 cur_handle = mpt->m_dev_handle;
15093 15098 for (; ; ) {
15094 15099 ptgt = NULL;
15095 15100 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
15096 15101 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)cur_handle;
15097 15102 rval = mptsas_get_target_device_info(mpt, page_address,
15098 15103 &cur_handle, &ptgt);
15099 15104 if ((rval == DEV_INFO_FAIL_PAGE0) ||
15100 15105 (rval == DEV_INFO_FAIL_ALLOC)) {
15101 15106 break;
15102 15107 }
15103 15108 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) ||
15104 15109 (rval == DEV_INFO_PHYS_DISK)) {
15105 15110 continue;
15106 15111 }
15107 15112 mpt->m_dev_handle = cur_handle;
15108 15113
15109 15114 if ((ptgt->m_sas_wwn == 0) && (ptgt->m_phynum == phy)) {
15110 15115 break;
15111 15116 }
15112 15117 }
15113 15118
15114 15119 mutex_exit(&mpt->m_mutex);
15115 15120 return (ptgt);
15116 15121 }
15117 15122
15118 15123 /*
15119 15124 * The ptgt->m_sas_wwn contains the wwid for each disk.
15120 15125 * For Raid volumes, we need to check m_raidvol[x].m_raidwwid
15121 15126 * If we didn't get a match, we need to get sas page0 for each device, and
15122 15127 * untill we get a match
15123 15128 * If failed, return NULL
15124 15129 */
15125 15130 static mptsas_target_t *
15126 15131 mptsas_wwid_to_ptgt(mptsas_t *mpt, int phymask, uint64_t wwid)
15127 15132 {
15128 15133 int rval = 0;
15129 15134 uint16_t cur_handle;
15130 15135 uint32_t page_address;
15131 15136 mptsas_target_t *tmp_tgt = NULL;
15132 15137
15133 15138 mutex_enter(&mpt->m_mutex);
15134 15139 tmp_tgt = (struct mptsas_target *)mptsas_hash_search(
15135 15140 &mpt->m_active->m_tgttbl, wwid, phymask);
15136 15141 if (tmp_tgt != NULL) {
15137 15142 mutex_exit(&mpt->m_mutex);
15138 15143 return (tmp_tgt);
15139 15144 }
15140 15145
15141 15146 if (phymask == 0) {
15142 15147 /*
15143 15148 * It's IR volume
15144 15149 */
15145 15150 rval = mptsas_get_raid_info(mpt);
15146 15151 if (rval) {
15147 15152 tmp_tgt = (struct mptsas_target *)mptsas_hash_search(
15148 15153 &mpt->m_active->m_tgttbl, wwid, phymask);
15149 15154 }
15150 15155 mutex_exit(&mpt->m_mutex);
15151 15156 return (tmp_tgt);
15152 15157 }
15153 15158
15154 15159 if (mpt->m_done_traverse_dev) {
15155 15160 mutex_exit(&mpt->m_mutex);
15156 15161 return (NULL);
15157 15162 }
15158 15163
15159 15164 /* If didn't get a match, come here */
15160 15165 cur_handle = mpt->m_dev_handle;
15161 15166 for (; ; ) {
15162 15167 tmp_tgt = NULL;
15163 15168 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
15164 15169 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | cur_handle;
15165 15170 rval = mptsas_get_target_device_info(mpt, page_address,
15166 15171 &cur_handle, &tmp_tgt);
15167 15172 if ((rval == DEV_INFO_FAIL_PAGE0) ||
15168 15173 (rval == DEV_INFO_FAIL_ALLOC)) {
15169 15174 tmp_tgt = NULL;
15170 15175 break;
15171 15176 }
15172 15177 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) ||
15173 15178 (rval == DEV_INFO_PHYS_DISK)) {
15174 15179 continue;
15175 15180 }
15176 15181 mpt->m_dev_handle = cur_handle;
15177 15182 if ((tmp_tgt->m_sas_wwn) && (tmp_tgt->m_sas_wwn == wwid) &&
15178 15183 (tmp_tgt->m_phymask == phymask)) {
15179 15184 break;
15180 15185 }
15181 15186 }
15182 15187
15183 15188 mutex_exit(&mpt->m_mutex);
15184 15189 return (tmp_tgt);
15185 15190 }
15186 15191
15187 15192 static mptsas_smp_t *
15188 15193 mptsas_wwid_to_psmp(mptsas_t *mpt, int phymask, uint64_t wwid)
15189 15194 {
15190 15195 int rval = 0;
15191 15196 uint16_t cur_handle;
15192 15197 uint32_t page_address;
15193 15198 mptsas_smp_t smp_node, *psmp = NULL;
15194 15199
15195 15200 mutex_enter(&mpt->m_mutex);
15196 15201 psmp = (struct mptsas_smp *)mptsas_hash_search(&mpt->m_active->m_smptbl,
15197 15202 wwid, phymask);
15198 15203 if (psmp != NULL) {
15199 15204 mutex_exit(&mpt->m_mutex);
15200 15205 return (psmp);
15201 15206 }
15202 15207
15203 15208 if (mpt->m_done_traverse_smp) {
15204 15209 mutex_exit(&mpt->m_mutex);
15205 15210 return (NULL);
15206 15211 }
15207 15212
15208 15213 /* If didn't get a match, come here */
15209 15214 cur_handle = mpt->m_smp_devhdl;
15210 15215 for (; ; ) {
15211 15216 psmp = NULL;
15212 15217 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL &
15213 15218 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)cur_handle;
15214 15219 rval = mptsas_get_sas_expander_page0(mpt, page_address,
15215 15220 &smp_node);
15216 15221 if (rval != DDI_SUCCESS) {
15217 15222 break;
15218 15223 }
15219 15224 mpt->m_smp_devhdl = cur_handle = smp_node.m_devhdl;
15220 15225 psmp = mptsas_smp_alloc(&mpt->m_active->m_smptbl, &smp_node);
15221 15226 ASSERT(psmp);
15222 15227 if ((psmp->m_sasaddr) && (psmp->m_sasaddr == wwid) &&
15223 15228 (psmp->m_phymask == phymask)) {
15224 15229 break;
15225 15230 }
15226 15231 }
15227 15232
15228 15233 mutex_exit(&mpt->m_mutex);
15229 15234 return (psmp);
15230 15235 }
15231 15236
15232 15237 /* helper functions using hash */
15233 15238
15234 15239 /*
15235 15240 * Can't have duplicate entries for same devhdl,
15236 15241 * if there are invalid entries, the devhdl should be set to 0xffff
15237 15242 */
15238 15243 static void *
15239 15244 mptsas_search_by_devhdl(mptsas_hash_table_t *hashtab, uint16_t devhdl)
15240 15245 {
15241 15246 mptsas_hash_data_t *data;
15242 15247
15243 15248 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_FIRST);
15244 15249 while (data != NULL) {
15245 15250 if (data->devhdl == devhdl) {
15246 15251 break;
15247 15252 }
15248 15253 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_NEXT);
15249 15254 }
15250 15255 return (data);
15251 15256 }
15252 15257
15253 15258 mptsas_target_t *
15254 15259 mptsas_tgt_alloc(mptsas_hash_table_t *hashtab, uint16_t devhdl, uint64_t wwid,
15255 15260 uint32_t devinfo, mptsas_phymask_t phymask, uint8_t phynum)
15256 15261 {
15257 15262 mptsas_target_t *tmp_tgt = NULL;
15258 15263
15259 15264 tmp_tgt = mptsas_hash_search(hashtab, wwid, phymask);
15260 15265 if (tmp_tgt != NULL) {
15261 15266 NDBG20(("Hash item already exist"));
15262 15267 tmp_tgt->m_deviceinfo = devinfo;
15263 15268 tmp_tgt->m_devhdl = devhdl;
15264 15269 return (tmp_tgt);
15265 15270 }
15266 15271 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target), KM_SLEEP);
15267 15272 if (tmp_tgt == NULL) {
15268 15273 cmn_err(CE_WARN, "Fatal, allocated tgt failed");
15269 15274 return (NULL);
15270 15275 }
15271 15276 tmp_tgt->m_devhdl = devhdl;
15272 15277 tmp_tgt->m_sas_wwn = wwid;
15273 15278 tmp_tgt->m_deviceinfo = devinfo;
15274 15279 tmp_tgt->m_phymask = phymask;
15275 15280 tmp_tgt->m_phynum = phynum;
15276 15281 /* Initialized the tgt structure */
15277 15282 tmp_tgt->m_qfull_retries = QFULL_RETRIES;
15278 15283 tmp_tgt->m_qfull_retry_interval =
15279 15284 drv_usectohz(QFULL_RETRY_INTERVAL * 1000);
15280 15285 tmp_tgt->m_t_throttle = MAX_THROTTLE;
15281 15286
15282 15287 mptsas_hash_add(hashtab, tmp_tgt);
15283 15288
15284 15289 return (tmp_tgt);
15285 15290 }
15286 15291
15287 15292 static void
15288 15293 mptsas_tgt_free(mptsas_hash_table_t *hashtab, uint64_t wwid,
15289 15294 mptsas_phymask_t phymask)
15290 15295 {
15291 15296 mptsas_target_t *tmp_tgt;
15292 15297 tmp_tgt = mptsas_hash_rem(hashtab, wwid, phymask);
15293 15298 if (tmp_tgt == NULL) {
15294 15299 cmn_err(CE_WARN, "Tgt not found, nothing to free");
15295 15300 } else {
15296 15301 kmem_free(tmp_tgt, sizeof (struct mptsas_target));
15297 15302 }
15298 15303 }
15299 15304
15300 15305 /*
15301 15306 * Return the entry in the hash table
15302 15307 */
15303 15308 static mptsas_smp_t *
15304 15309 mptsas_smp_alloc(mptsas_hash_table_t *hashtab, mptsas_smp_t *data)
15305 15310 {
15306 15311 uint64_t key1 = data->m_sasaddr;
15307 15312 mptsas_phymask_t key2 = data->m_phymask;
15308 15313 mptsas_smp_t *ret_data;
15309 15314
15310 15315 ret_data = mptsas_hash_search(hashtab, key1, key2);
15311 15316 if (ret_data != NULL) {
15312 15317 bcopy(data, ret_data, sizeof (mptsas_smp_t));
15313 15318 return (ret_data);
15314 15319 }
15315 15320
15316 15321 ret_data = kmem_alloc(sizeof (mptsas_smp_t), KM_SLEEP);
15317 15322 bcopy(data, ret_data, sizeof (mptsas_smp_t));
15318 15323 mptsas_hash_add(hashtab, ret_data);
15319 15324 return (ret_data);
15320 15325 }
15321 15326
15322 15327 static void
15323 15328 mptsas_smp_free(mptsas_hash_table_t *hashtab, uint64_t wwid,
15324 15329 mptsas_phymask_t phymask)
15325 15330 {
15326 15331 mptsas_smp_t *tmp_smp;
15327 15332 tmp_smp = mptsas_hash_rem(hashtab, wwid, phymask);
15328 15333 if (tmp_smp == NULL) {
15329 15334 cmn_err(CE_WARN, "Smp element not found, nothing to free");
15330 15335 } else {
15331 15336 kmem_free(tmp_smp, sizeof (struct mptsas_smp));
15332 15337 }
15333 15338 }
15334 15339
15335 15340 /*
15336 15341 * Hash operation functions
15337 15342 * key1 is the sas_wwn, key2 is the phymask
15338 15343 */
15339 15344 static void
15340 15345 mptsas_hash_init(mptsas_hash_table_t *hashtab)
15341 15346 {
15342 15347 if (hashtab == NULL) {
15343 15348 return;
15344 15349 }
15345 15350 bzero(hashtab->head, sizeof (mptsas_hash_node_t) *
15346 15351 MPTSAS_HASH_ARRAY_SIZE);
15347 15352 hashtab->cur = NULL;
15348 15353 hashtab->line = 0;
15349 15354 }
15350 15355
15351 15356 static void
15352 15357 mptsas_hash_uninit(mptsas_hash_table_t *hashtab, size_t datalen)
15353 15358 {
15354 15359 uint16_t line = 0;
15355 15360 mptsas_hash_node_t *cur = NULL, *last = NULL;
15356 15361
15357 15362 if (hashtab == NULL) {
15358 15363 return;
15359 15364 }
15360 15365 for (line = 0; line < MPTSAS_HASH_ARRAY_SIZE; line++) {
15361 15366 cur = hashtab->head[line];
15362 15367 while (cur != NULL) {
15363 15368 last = cur;
15364 15369 cur = cur->next;
15365 15370 kmem_free(last->data, datalen);
15366 15371 kmem_free(last, sizeof (mptsas_hash_node_t));
15367 15372 }
15368 15373 }
15369 15374 }
15370 15375
15371 15376 /*
15372 15377 * You must guarantee the element doesn't exist in the hash table
15373 15378 * before you call mptsas_hash_add()
15374 15379 */
15375 15380 static void
15376 15381 mptsas_hash_add(mptsas_hash_table_t *hashtab, void *data)
15377 15382 {
15378 15383 uint64_t key1 = ((mptsas_hash_data_t *)data)->key1;
15379 15384 mptsas_phymask_t key2 = ((mptsas_hash_data_t *)data)->key2;
15380 15385 mptsas_hash_node_t **head = NULL;
15381 15386 mptsas_hash_node_t *node = NULL;
15382 15387
15383 15388 if (hashtab == NULL) {
15384 15389 return;
15385 15390 }
15386 15391 ASSERT(mptsas_hash_search(hashtab, key1, key2) == NULL);
15387 15392 node = kmem_zalloc(sizeof (mptsas_hash_node_t), KM_NOSLEEP);
15388 15393 node->data = data;
15389 15394
15390 15395 head = &(hashtab->head[key1 % MPTSAS_HASH_ARRAY_SIZE]);
15391 15396 if (*head == NULL) {
15392 15397 *head = node;
15393 15398 } else {
15394 15399 node->next = *head;
15395 15400 *head = node;
15396 15401 }
15397 15402 }
15398 15403
15399 15404 static void *
15400 15405 mptsas_hash_rem(mptsas_hash_table_t *hashtab, uint64_t key1,
15401 15406 mptsas_phymask_t key2)
15402 15407 {
15403 15408 mptsas_hash_node_t **head = NULL;
15404 15409 mptsas_hash_node_t *last = NULL, *cur = NULL;
15405 15410 mptsas_hash_data_t *data;
15406 15411 if (hashtab == NULL) {
15407 15412 return (NULL);
15408 15413 }
15409 15414 head = &(hashtab->head[key1 % MPTSAS_HASH_ARRAY_SIZE]);
15410 15415 cur = *head;
15411 15416 while (cur != NULL) {
15412 15417 data = cur->data;
15413 15418 if ((data->key1 == key1) && (data->key2 == key2)) {
15414 15419 if (last == NULL) {
15415 15420 (*head) = cur->next;
15416 15421 } else {
15417 15422 last->next = cur->next;
15418 15423 }
15419 15424 kmem_free(cur, sizeof (mptsas_hash_node_t));
15420 15425 return (data);
15421 15426 } else {
15422 15427 last = cur;
15423 15428 cur = cur->next;
15424 15429 }
15425 15430 }
15426 15431 return (NULL);
15427 15432 }
15428 15433
15429 15434 static void *
15430 15435 mptsas_hash_search(mptsas_hash_table_t *hashtab, uint64_t key1,
15431 15436 mptsas_phymask_t key2)
15432 15437 {
15433 15438 mptsas_hash_node_t *cur = NULL;
15434 15439 mptsas_hash_data_t *data;
15435 15440 if (hashtab == NULL) {
15436 15441 return (NULL);
15437 15442 }
15438 15443 cur = hashtab->head[key1 % MPTSAS_HASH_ARRAY_SIZE];
15439 15444 while (cur != NULL) {
15440 15445 data = cur->data;
15441 15446 if ((data->key1 == key1) && (data->key2 == key2)) {
15442 15447 return (data);
15443 15448 } else {
15444 15449 cur = cur->next;
15445 15450 }
15446 15451 }
15447 15452 return (NULL);
15448 15453 }
15449 15454
15450 15455 static void *
15451 15456 mptsas_hash_traverse(mptsas_hash_table_t *hashtab, int pos)
15452 15457 {
15453 15458 mptsas_hash_node_t *this = NULL;
15454 15459
15455 15460 if (hashtab == NULL) {
15456 15461 return (NULL);
15457 15462 }
15458 15463
15459 15464 if (pos == MPTSAS_HASH_FIRST) {
15460 15465 hashtab->line = 0;
15461 15466 hashtab->cur = NULL;
15462 15467 this = hashtab->head[0];
15463 15468 } else {
15464 15469 if (hashtab->cur == NULL) {
15465 15470 return (NULL);
15466 15471 } else {
15467 15472 this = hashtab->cur->next;
15468 15473 }
15469 15474 }
15470 15475
15471 15476 while (this == NULL) {
15472 15477 hashtab->line++;
15473 15478 if (hashtab->line >= MPTSAS_HASH_ARRAY_SIZE) {
15474 15479 /* the traverse reaches the end */
15475 15480 hashtab->cur = NULL;
15476 15481 return (NULL);
15477 15482 } else {
15478 15483 this = hashtab->head[hashtab->line];
15479 15484 }
15480 15485 }
15481 15486 hashtab->cur = this;
15482 15487 return (this->data);
15483 15488 }
15484 15489
15485 15490 /*
15486 15491 * Functions for SGPIO LED support
15487 15492 */
15488 15493 static dev_info_t *
15489 15494 mptsas_get_dip_from_dev(dev_t dev, mptsas_phymask_t *phymask)
15490 15495 {
15491 15496 dev_info_t *dip;
15492 15497 int prop;
15493 15498 dip = e_ddi_hold_devi_by_dev(dev, 0);
15494 15499 if (dip == NULL)
15495 15500 return (dip);
15496 15501 prop = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
15497 15502 "phymask", 0);
15498 15503 *phymask = (mptsas_phymask_t)prop;
15499 15504 ddi_release_devi(dip);
15500 15505 return (dip);
15501 15506 }
15502 15507 static mptsas_target_t *
15503 15508 mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr, mptsas_phymask_t phymask)
15504 15509 {
15505 15510 uint8_t phynum;
15506 15511 uint64_t wwn;
15507 15512 int lun;
15508 15513 mptsas_target_t *ptgt = NULL;
15509 15514
15510 15515 if (mptsas_parse_address(addr, &wwn, &phynum, &lun) != DDI_SUCCESS) {
15511 15516 return (NULL);
15512 15517 }
15513 15518 if (addr[0] == 'w') {
15514 15519 ptgt = mptsas_wwid_to_ptgt(mpt, (int)phymask, wwn);
15515 15520 } else {
15516 15521 ptgt = mptsas_phy_to_tgt(mpt, (int)phymask, phynum);
15517 15522 }
15518 15523 return (ptgt);
15519 15524 }
15520 15525
15521 15526 static int
15522 15527 mptsas_flush_led_status(mptsas_t *mpt, mptsas_target_t *ptgt)
15523 15528 {
15524 15529 uint32_t slotstatus = 0;
15525 15530
15526 15531 /* Build an MPI2 Slot Status based on our view of the world */
15527 15532 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_IDENT - 1)))
15528 15533 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST;
15529 15534 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_FAIL - 1)))
15530 15535 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT;
15531 15536 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1)))
15532 15537 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE;
15533 15538
15534 15539 /* Write it to the controller */
15535 15540 NDBG14(("mptsas_ioctl: set LED status %x for slot %x",
15536 15541 slotstatus, ptgt->m_slot_num));
15537 15542 return (mptsas_send_sep(mpt, ptgt, &slotstatus,
15538 15543 MPI2_SEP_REQ_ACTION_WRITE_STATUS));
15539 15544 }
15540 15545
15541 15546 /*
15542 15547 * send sep request, use enclosure/slot addressing
15543 15548 */
15544 15549 static int
15545 15550 mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt,
15546 15551 uint32_t *status, uint8_t act)
15547 15552 {
15548 15553 Mpi2SepRequest_t req;
15549 15554 Mpi2SepReply_t rep;
15550 15555 int ret;
15551 15556
15552 15557 ASSERT(mutex_owned(&mpt->m_mutex));
15553 15558
15554 15559 /*
15555 15560 * We only support SEP control of directly-attached targets, in which
15556 15561 * case the "SEP" we're talking to is a virtual one contained within
15557 15562 * the HBA itself. This is necessary because DA targets typically have
15558 15563 * no other mechanism for LED control. Targets for which a separate
15559 15564 * enclosure service processor exists should be controlled via ses(7d)
15560 15565 * or sgen(7d). Furthermore, since such requests can time out, they
15561 15566 * should be made in user context rather than in response to
15562 15567 * asynchronous fabric changes.
15563 15568 *
15564 15569 * In addition, we do not support this operation for RAID volumes,
15565 15570 * since there is no slot associated with them.
15566 15571 */
15567 15572 if (!(ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) ||
15568 15573 ptgt->m_phymask == 0) {
15569 15574 return (ENOTTY);
15570 15575 }
15571 15576
15572 15577 bzero(&req, sizeof (req));
15573 15578 bzero(&rep, sizeof (rep));
15574 15579
15575 15580 req.Function = MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR;
15576 15581 req.Action = act;
15577 15582 req.Flags = MPI2_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS;
15578 15583 req.EnclosureHandle = LE_16(ptgt->m_enclosure);
15579 15584 req.Slot = LE_16(ptgt->m_slot_num);
15580 15585 if (act == MPI2_SEP_REQ_ACTION_WRITE_STATUS) {
15581 15586 req.SlotStatus = LE_32(*status);
15582 15587 }
15583 15588 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL,
15584 15589 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL);
15585 15590 if (ret != 0) {
15586 15591 mptsas_log(mpt, CE_NOTE, "mptsas_send_sep: passthru SEP "
15587 15592 "Processor Request message error %d", ret);
15588 15593 return (ret);
15589 15594 }
15590 15595 /* do passthrough success, check the ioc status */
15591 15596 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
15592 15597 mptsas_log(mpt, CE_NOTE, "send_sep act %x: ioc "
15593 15598 "status:%x loginfo %x", act, LE_16(rep.IOCStatus),
15594 15599 LE_32(rep.IOCLogInfo));
15595 15600 switch (LE_16(rep.IOCStatus) & MPI2_IOCSTATUS_MASK) {
15596 15601 case MPI2_IOCSTATUS_INVALID_FUNCTION:
15597 15602 case MPI2_IOCSTATUS_INVALID_VPID:
15598 15603 case MPI2_IOCSTATUS_INVALID_FIELD:
15599 15604 case MPI2_IOCSTATUS_INVALID_STATE:
15600 15605 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
15601 15606 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
15602 15607 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
15603 15608 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
15604 15609 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
15605 15610 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
15606 15611 return (EINVAL);
15607 15612 case MPI2_IOCSTATUS_BUSY:
15608 15613 return (EBUSY);
15609 15614 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
15610 15615 return (EAGAIN);
15611 15616 case MPI2_IOCSTATUS_INVALID_SGL:
15612 15617 case MPI2_IOCSTATUS_INTERNAL_ERROR:
15613 15618 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
15614 15619 default:
15615 15620 return (EIO);
15616 15621 }
15617 15622 }
15618 15623 if (act != MPI2_SEP_REQ_ACTION_WRITE_STATUS) {
15619 15624 *status = LE_32(rep.SlotStatus);
15620 15625 }
15621 15626
15622 15627 return (0);
15623 15628 }
15624 15629
15625 15630 int
15626 15631 mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr,
15627 15632 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp,
15628 15633 uint32_t alloc_size, ddi_dma_cookie_t *cookiep)
15629 15634 {
15630 15635 ddi_dma_cookie_t new_cookie;
15631 15636 size_t alloc_len;
15632 15637 uint_t ncookie;
15633 15638
15634 15639 if (cookiep == NULL)
15635 15640 cookiep = &new_cookie;
15636 15641
15637 15642 if (ddi_dma_alloc_handle(mpt->m_dip, &dma_attr, DDI_DMA_SLEEP,
15638 15643 NULL, dma_hdp) != DDI_SUCCESS) {
15639 15644 dma_hdp = NULL;
15640 15645 return (FALSE);
15641 15646 }
15642 15647
15643 15648 if (ddi_dma_mem_alloc(*dma_hdp, alloc_size, &mpt->m_dev_acc_attr,
15644 15649 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, dma_memp, &alloc_len,
15645 15650 acc_hdp) != DDI_SUCCESS) {
15646 15651 ddi_dma_free_handle(dma_hdp);
15647 15652 dma_hdp = NULL;
15648 15653 return (FALSE);
15649 15654 }
15650 15655
15651 15656 if (ddi_dma_addr_bind_handle(*dma_hdp, NULL, *dma_memp, alloc_len,
15652 15657 (DDI_DMA_RDWR | DDI_DMA_CONSISTENT), DDI_DMA_SLEEP, NULL,
15653 15658 cookiep, &ncookie) != DDI_DMA_MAPPED) {
15654 15659 (void) ddi_dma_mem_free(acc_hdp);
15655 15660 ddi_dma_free_handle(dma_hdp);
15656 15661 dma_hdp = NULL;
15657 15662 return (FALSE);
15658 15663 }
15659 15664
15660 15665 return (TRUE);
15661 15666 }
15662 15667
15663 15668 void
15664 15669 mptsas_dma_addr_destroy(ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp)
15665 15670 {
15666 15671 if (*dma_hdp == NULL)
15667 15672 return;
15668 15673
15669 15674 (void) ddi_dma_unbind_handle(*dma_hdp);
15670 15675 (void) ddi_dma_mem_free(acc_hdp);
15671 15676 ddi_dma_free_handle(dma_hdp);
15672 15677 dma_hdp = NULL;
15673 15678 }
|
↓ open down ↓ |
760 lines elided |
↑ open up ↑ |
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX