1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
24 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
25 * Copyright (c) 2013, Joyent, Inc. All rights reserved.
26 */
27
28 /*
29 * Copyright (c) 2000 to 2010, LSI Corporation.
30 * All rights reserved.
31 *
32 * Redistribution and use in source and binary forms of all code within
33 * this file that is exclusively owned by LSI, with or without
34 * modification, is permitted provided that, in addition to the CDDL 1.0
35 * License requirements, the following conditions are met:
36 *
37 * Neither the name of the author nor the names of its contributors may be
38 * used to endorse or promote products derived from this software without
39 * specific prior written permission.
40 *
41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
42 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
43 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
44 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
45 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
46 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
47 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
48 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
49 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
50 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
51 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
52 * DAMAGE.
53 */
54
55 /*
56 * mptsas - This is a driver based on LSI Logic's MPT2.0 interface.
57 *
58 */
59
60 #if defined(lint) || defined(DEBUG)
61 #define MPTSAS_DEBUG
62 #endif
63
64 /*
65 * standard header files.
66 */
67 #include <sys/note.h>
68 #include <sys/scsi/scsi.h>
69 #include <sys/pci.h>
70 #include <sys/file.h>
71 #include <sys/policy.h>
72 #include <sys/model.h>
73 #include <sys/sysevent.h>
74 #include <sys/sysevent/eventdefs.h>
75 #include <sys/sysevent/dr.h>
76 #include <sys/sata/sata_defs.h>
77 #include <sys/scsi/generic/sas.h>
78 #include <sys/scsi/impl/scsi_sas.h>
79
80 #pragma pack(1)
81 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h>
82 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2.h>
83 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h>
84 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h>
85 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h>
86 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h>
87 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h>
88 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h>
89 #pragma pack()
90
91 /*
92 * private header files.
93 *
94 */
95 #include <sys/scsi/impl/scsi_reset_notify.h>
96 #include <sys/scsi/adapters/mpt_sas/mptsas_var.h>
97 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h>
98 #include <sys/scsi/adapters/mpt_sas/mptsas_smhba.h>
99 #include <sys/raidioctl.h>
100
101 #include <sys/fs/dv_node.h> /* devfs_clean */
102
103 /*
104 * FMA header files
105 */
106 #include <sys/ddifm.h>
107 #include <sys/fm/protocol.h>
108 #include <sys/fm/util.h>
109 #include <sys/fm/io/ddi.h>
110
111 /*
112 * autoconfiguration data and routines.
113 */
114 static int mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
115 static int mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd);
116 static int mptsas_power(dev_info_t *dip, int component, int level);
117
118 /*
119 * cb_ops function
120 */
121 static int mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode,
122 cred_t *credp, int *rval);
123 #ifdef __sparc
124 static int mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd);
125 #else /* __sparc */
126 static int mptsas_quiesce(dev_info_t *devi);
127 #endif /* __sparc */
128
129 /*
130 * Resource initilaization for hardware
131 */
132 static void mptsas_setup_cmd_reg(mptsas_t *mpt);
133 static void mptsas_disable_bus_master(mptsas_t *mpt);
134 static void mptsas_hba_fini(mptsas_t *mpt);
135 static void mptsas_cfg_fini(mptsas_t *mptsas_blkp);
136 static int mptsas_hba_setup(mptsas_t *mpt);
137 static void mptsas_hba_teardown(mptsas_t *mpt);
138 static int mptsas_config_space_init(mptsas_t *mpt);
139 static void mptsas_config_space_fini(mptsas_t *mpt);
140 static void mptsas_iport_register(mptsas_t *mpt);
141 static int mptsas_smp_setup(mptsas_t *mpt);
142 static void mptsas_smp_teardown(mptsas_t *mpt);
143 static int mptsas_cache_create(mptsas_t *mpt);
144 static void mptsas_cache_destroy(mptsas_t *mpt);
145 static int mptsas_alloc_request_frames(mptsas_t *mpt);
146 static int mptsas_alloc_reply_frames(mptsas_t *mpt);
147 static int mptsas_alloc_free_queue(mptsas_t *mpt);
148 static int mptsas_alloc_post_queue(mptsas_t *mpt);
149 static void mptsas_alloc_reply_args(mptsas_t *mpt);
150 static int mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd);
151 static void mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd);
152 static int mptsas_init_chip(mptsas_t *mpt, int first_time);
153
154 /*
155 * SCSA function prototypes
156 */
157 static int mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt);
158 static int mptsas_scsi_reset(struct scsi_address *ap, int level);
159 static int mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt);
160 static int mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly);
161 static int mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value,
162 int tgtonly);
163 static void mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt);
164 static struct scsi_pkt *mptsas_scsi_init_pkt(struct scsi_address *ap,
165 struct scsi_pkt *pkt, struct buf *bp, int cmdlen, int statuslen,
166 int tgtlen, int flags, int (*callback)(), caddr_t arg);
167 static void mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt);
168 static void mptsas_scsi_destroy_pkt(struct scsi_address *ap,
169 struct scsi_pkt *pkt);
170 static int mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
171 scsi_hba_tran_t *hba_tran, struct scsi_device *sd);
172 static void mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
173 scsi_hba_tran_t *hba_tran, struct scsi_device *sd);
174 static int mptsas_scsi_reset_notify(struct scsi_address *ap, int flag,
175 void (*callback)(caddr_t), caddr_t arg);
176 static int mptsas_get_name(struct scsi_device *sd, char *name, int len);
177 static int mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len);
178 static int mptsas_scsi_quiesce(dev_info_t *dip);
179 static int mptsas_scsi_unquiesce(dev_info_t *dip);
180 static int mptsas_bus_config(dev_info_t *pdip, uint_t flags,
181 ddi_bus_config_op_t op, void *arg, dev_info_t **childp);
182
183 /*
184 * SMP functions
185 */
186 static int mptsas_smp_start(struct smp_pkt *smp_pkt);
187
188 /*
189 * internal function prototypes.
190 */
191 static void mptsas_list_add(mptsas_t *mpt);
192 static void mptsas_list_del(mptsas_t *mpt);
193
194 static int mptsas_quiesce_bus(mptsas_t *mpt);
195 static int mptsas_unquiesce_bus(mptsas_t *mpt);
196
197 static int mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size);
198 static void mptsas_free_handshake_msg(mptsas_t *mpt);
199
200 static void mptsas_ncmds_checkdrain(void *arg);
201
202 static int mptsas_prepare_pkt(mptsas_cmd_t *cmd);
203 static int mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *sp);
204 static int mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *sp);
205 static void mptsas_accept_tx_waitq(mptsas_t *mpt);
206
207 static int mptsas_do_detach(dev_info_t *dev);
208 static int mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl);
209 static int mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun,
210 struct scsi_pkt *pkt);
211 static int mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp);
212
213 static void mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd);
214 static void mptsas_handle_event(void *args);
215 static int mptsas_handle_event_sync(void *args);
216 static void mptsas_handle_dr(void *args);
217 static void mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node,
218 dev_info_t *pdip);
219
220 static void mptsas_restart_cmd(void *);
221
222 static void mptsas_flush_hba(mptsas_t *mpt);
223 static void mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun,
224 uint8_t tasktype);
225 static void mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd,
226 uchar_t reason, uint_t stat);
227
228 static uint_t mptsas_intr(caddr_t arg1, caddr_t arg2);
229 static void mptsas_process_intr(mptsas_t *mpt,
230 pMpi2ReplyDescriptorsUnion_t reply_desc_union);
231 static void mptsas_handle_scsi_io_success(mptsas_t *mpt,
232 pMpi2ReplyDescriptorsUnion_t reply_desc);
233 static void mptsas_handle_address_reply(mptsas_t *mpt,
234 pMpi2ReplyDescriptorsUnion_t reply_desc);
235 static int mptsas_wait_intr(mptsas_t *mpt, int polltime);
236 static void mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd,
237 uint32_t *control, pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl);
238
239 static void mptsas_watch(void *arg);
240 static void mptsas_watchsubr(mptsas_t *mpt);
241 static void mptsas_cmd_timeout(mptsas_t *mpt, uint16_t devhdl);
242
243 static void mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd);
244 static int mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply,
245 uint8_t *data, uint32_t request_size, uint32_t reply_size,
246 uint32_t data_size, uint32_t direction, uint8_t *dataout,
247 uint32_t dataout_size, short timeout, int mode);
248 static int mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl);
249
250 static uint8_t mptsas_get_fw_diag_buffer_number(mptsas_t *mpt,
251 uint32_t unique_id);
252 static void mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd);
253 static int mptsas_post_fw_diag_buffer(mptsas_t *mpt,
254 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code);
255 static int mptsas_release_fw_diag_buffer(mptsas_t *mpt,
256 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code,
257 uint32_t diag_type);
258 static int mptsas_diag_register(mptsas_t *mpt,
259 mptsas_fw_diag_register_t *diag_register, uint32_t *return_code);
260 static int mptsas_diag_unregister(mptsas_t *mpt,
261 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code);
262 static int mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query,
263 uint32_t *return_code);
264 static int mptsas_diag_read_buffer(mptsas_t *mpt,
265 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf,
266 uint32_t *return_code, int ioctl_mode);
267 static int mptsas_diag_release(mptsas_t *mpt,
268 mptsas_fw_diag_release_t *diag_release, uint32_t *return_code);
269 static int mptsas_do_diag_action(mptsas_t *mpt, uint32_t action,
270 uint8_t *diag_action, uint32_t length, uint32_t *return_code,
271 int ioctl_mode);
272 static int mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *data,
273 int mode);
274
275 static int mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd,
276 int cmdlen, int tgtlen, int statuslen, int kf);
277 static void mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd);
278
279 static int mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags);
280 static void mptsas_kmem_cache_destructor(void *buf, void *cdrarg);
281
282 static int mptsas_cache_frames_constructor(void *buf, void *cdrarg,
283 int kmflags);
284 static void mptsas_cache_frames_destructor(void *buf, void *cdrarg);
285
286 static void mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply,
287 mptsas_cmd_t *cmd);
288 static void mptsas_check_task_mgt(mptsas_t *mpt,
289 pMpi2SCSIManagementReply_t reply, mptsas_cmd_t *cmd);
290 static int mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap,
291 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp,
292 int *resid);
293
294 static int mptsas_alloc_active_slots(mptsas_t *mpt, int flag);
295 static void mptsas_free_active_slots(mptsas_t *mpt);
296 static int mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
297
298 static void mptsas_restart_hba(mptsas_t *mpt);
299 static void mptsas_restart_waitq(mptsas_t *mpt);
300
301 static void mptsas_deliver_doneq_thread(mptsas_t *mpt);
302 static void mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd);
303 static void mptsas_doneq_mv(mptsas_t *mpt, uint64_t t);
304
305 static mptsas_cmd_t *mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t);
306 static void mptsas_doneq_empty(mptsas_t *mpt);
307 static void mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg);
308
309 static mptsas_cmd_t *mptsas_waitq_rm(mptsas_t *mpt);
310 static void mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd);
311 static mptsas_cmd_t *mptsas_tx_waitq_rm(mptsas_t *mpt);
312 static void mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd);
313
314
315 static void mptsas_start_watch_reset_delay();
316 static void mptsas_setup_bus_reset_delay(mptsas_t *mpt);
317 static void mptsas_watch_reset_delay(void *arg);
318 static int mptsas_watch_reset_delay_subr(mptsas_t *mpt);
319
320 /*
321 * helper functions
322 */
323 static void mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
324
325 static dev_info_t *mptsas_find_child(dev_info_t *pdip, char *name);
326 static dev_info_t *mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy);
327 static dev_info_t *mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr,
328 int lun);
329 static mdi_pathinfo_t *mptsas_find_path_addr(dev_info_t *pdip, uint64_t sasaddr,
330 int lun);
331 static mdi_pathinfo_t *mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy);
332 static dev_info_t *mptsas_find_smp_child(dev_info_t *pdip, char *str_wwn);
333
334 static int mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy,
335 int *lun);
336 static int mptsas_parse_smp_name(char *name, uint64_t *wwn);
337
338 static mptsas_target_t *mptsas_phy_to_tgt(mptsas_t *mpt, int phymask,
339 uint8_t phy);
340 static mptsas_target_t *mptsas_wwid_to_ptgt(mptsas_t *mpt, int phymask,
341 uint64_t wwid);
342 static mptsas_smp_t *mptsas_wwid_to_psmp(mptsas_t *mpt, int phymask,
343 uint64_t wwid);
344
345 static int mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun,
346 uchar_t page, unsigned char *buf, int len, int *rlen, uchar_t evpd);
347
348 static int mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address,
349 uint16_t *handle, mptsas_target_t **pptgt);
350 static void mptsas_update_phymask(mptsas_t *mpt);
351
352 static int mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt,
353 uint32_t *status, uint8_t cmd);
354 static dev_info_t *mptsas_get_dip_from_dev(dev_t dev,
355 mptsas_phymask_t *phymask);
356 static mptsas_target_t *mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr,
357 mptsas_phymask_t phymask);
358 static int mptsas_flush_led_status(mptsas_t *mpt, mptsas_target_t *ptgt);
359
360
361 /*
362 * Enumeration / DR functions
363 */
364 static void mptsas_config_all(dev_info_t *pdip);
365 static int mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun,
366 dev_info_t **lundip);
367 static int mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun,
368 dev_info_t **lundip);
369
370 static int mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt);
371 static int mptsas_offline_target(dev_info_t *pdip, char *name);
372
373 static int mptsas_config_raid(dev_info_t *pdip, uint16_t target,
374 dev_info_t **dip);
375
376 static int mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt);
377 static int mptsas_probe_lun(dev_info_t *pdip, int lun,
378 dev_info_t **dip, mptsas_target_t *ptgt);
379
380 static int mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq,
381 dev_info_t **dip, mptsas_target_t *ptgt, int lun);
382
383 static int mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *sd,
384 char *guid, dev_info_t **dip, mptsas_target_t *ptgt, int lun);
385 static int mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *sd,
386 char *guid, dev_info_t **dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt,
387 int lun);
388
389 static void mptsas_offline_missed_luns(dev_info_t *pdip,
390 uint16_t *repluns, int lun_cnt, mptsas_target_t *ptgt);
391 static int mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip,
392 mdi_pathinfo_t *rpip, uint_t flags);
393
394 static int mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn,
395 dev_info_t **smp_dip);
396 static int mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
397 uint_t flags);
398
399 static int mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data,
400 int mode, int *rval);
401 static int mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data,
402 int mode, int *rval);
403 static int mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data,
404 int mode, int *rval);
405 static void mptsas_record_event(void *args);
406 static int mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data,
407 int mode);
408
409 static void mptsas_hash_init(mptsas_hash_table_t *hashtab);
410 static void mptsas_hash_uninit(mptsas_hash_table_t *hashtab, size_t datalen);
411 static void mptsas_hash_add(mptsas_hash_table_t *hashtab, void *data);
412 static void * mptsas_hash_rem(mptsas_hash_table_t *hashtab, uint64_t key1,
413 mptsas_phymask_t key2);
414 static void * mptsas_hash_search(mptsas_hash_table_t *hashtab, uint64_t key1,
415 mptsas_phymask_t key2);
416 static void * mptsas_hash_traverse(mptsas_hash_table_t *hashtab, int pos);
417
418 mptsas_target_t *mptsas_tgt_alloc(mptsas_hash_table_t *, uint16_t, uint64_t,
419 uint32_t, mptsas_phymask_t, uint8_t);
420 static mptsas_smp_t *mptsas_smp_alloc(mptsas_hash_table_t *hashtab,
421 mptsas_smp_t *data);
422 static void mptsas_smp_free(mptsas_hash_table_t *hashtab, uint64_t wwid,
423 mptsas_phymask_t phymask);
424 static void mptsas_tgt_free(mptsas_hash_table_t *, uint64_t, mptsas_phymask_t);
425 static void * mptsas_search_by_devhdl(mptsas_hash_table_t *, uint16_t);
426 static int mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
427 dev_info_t **smp_dip);
428
429 /*
430 * Power management functions
431 */
432 static int mptsas_get_pci_cap(mptsas_t *mpt);
433 static int mptsas_init_pm(mptsas_t *mpt);
434
435 /*
436 * MPT MSI tunable:
437 *
438 * By default MSI is enabled on all supported platforms.
439 */
440 boolean_t mptsas_enable_msi = B_TRUE;
441 boolean_t mptsas_physical_bind_failed_page_83 = B_FALSE;
442
443 static int mptsas_register_intrs(mptsas_t *);
444 static void mptsas_unregister_intrs(mptsas_t *);
445 static int mptsas_add_intrs(mptsas_t *, int);
446 static void mptsas_rem_intrs(mptsas_t *);
447
448 /*
449 * FMA Prototypes
450 */
451 static void mptsas_fm_init(mptsas_t *mpt);
452 static void mptsas_fm_fini(mptsas_t *mpt);
453 static int mptsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *, const void *);
454
455 extern pri_t minclsyspri, maxclsyspri;
456
457 /*
458 * This device is created by the SCSI pseudo nexus driver (SCSI vHCI). It is
459 * under this device that the paths to a physical device are created when
460 * MPxIO is used.
461 */
462 extern dev_info_t *scsi_vhci_dip;
463
464 /*
465 * Tunable timeout value for Inquiry VPD page 0x83
466 * By default the value is 30 seconds.
467 */
468 int mptsas_inq83_retry_timeout = 30;
469
470 /*
471 * This is used to allocate memory for message frame storage, not for
472 * data I/O DMA. All message frames must be stored in the first 4G of
473 * physical memory.
474 */
475 ddi_dma_attr_t mptsas_dma_attrs = {
476 DMA_ATTR_V0, /* attribute layout version */
477 0x0ull, /* address low - should be 0 (longlong) */
478 0xffffffffull, /* address high - 32-bit max range */
479 0x00ffffffull, /* count max - max DMA object size */
480 4, /* allocation alignment requirements */
481 0x78, /* burstsizes - binary encoded values */
482 1, /* minxfer - gran. of DMA engine */
483 0x00ffffffull, /* maxxfer - gran. of DMA engine */
484 0xffffffffull, /* max segment size (DMA boundary) */
485 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */
486 512, /* granularity - device transfer size */
487 0 /* flags, set to 0 */
488 };
489
490 /*
491 * This is used for data I/O DMA memory allocation. (full 64-bit DMA
492 * physical addresses are supported.)
493 */
494 ddi_dma_attr_t mptsas_dma_attrs64 = {
495 DMA_ATTR_V0, /* attribute layout version */
496 0x0ull, /* address low - should be 0 (longlong) */
497 0xffffffffffffffffull, /* address high - 64-bit max */
498 0x00ffffffull, /* count max - max DMA object size */
499 4, /* allocation alignment requirements */
500 0x78, /* burstsizes - binary encoded values */
501 1, /* minxfer - gran. of DMA engine */
502 0x00ffffffull, /* maxxfer - gran. of DMA engine */
503 0xffffffffull, /* max segment size (DMA boundary) */
504 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */
505 512, /* granularity - device transfer size */
506 DDI_DMA_RELAXED_ORDERING /* flags, enable relaxed ordering */
507 };
508
509 ddi_device_acc_attr_t mptsas_dev_attr = {
510 DDI_DEVICE_ATTR_V1,
511 DDI_STRUCTURE_LE_ACC,
512 DDI_STRICTORDER_ACC,
513 DDI_DEFAULT_ACC
514 };
515
516 static struct cb_ops mptsas_cb_ops = {
517 scsi_hba_open, /* open */
518 scsi_hba_close, /* close */
519 nodev, /* strategy */
520 nodev, /* print */
521 nodev, /* dump */
522 nodev, /* read */
523 nodev, /* write */
524 mptsas_ioctl, /* ioctl */
525 nodev, /* devmap */
526 nodev, /* mmap */
527 nodev, /* segmap */
528 nochpoll, /* chpoll */
529 ddi_prop_op, /* cb_prop_op */
530 NULL, /* streamtab */
531 D_MP, /* cb_flag */
532 CB_REV, /* rev */
533 nodev, /* aread */
534 nodev /* awrite */
535 };
536
537 static struct dev_ops mptsas_ops = {
538 DEVO_REV, /* devo_rev, */
539 0, /* refcnt */
540 ddi_no_info, /* info */
541 nulldev, /* identify */
542 nulldev, /* probe */
543 mptsas_attach, /* attach */
544 mptsas_detach, /* detach */
545 #ifdef __sparc
546 mptsas_reset,
547 #else
548 nodev, /* reset */
549 #endif /* __sparc */
550 &mptsas_cb_ops, /* driver operations */
551 NULL, /* bus operations */
552 mptsas_power, /* power management */
553 #ifdef __sparc
554 ddi_quiesce_not_needed
555 #else
556 mptsas_quiesce /* quiesce */
557 #endif /* __sparc */
558 };
559
560
561 #define MPTSAS_MOD_STRING "MPTSAS HBA Driver 00.00.00.24"
562
563 static struct modldrv modldrv = {
564 &mod_driverops, /* Type of module. This one is a driver */
565 MPTSAS_MOD_STRING, /* Name of the module. */
566 &mptsas_ops, /* driver ops */
567 };
568
569 static struct modlinkage modlinkage = {
570 MODREV_1, &modldrv, NULL
571 };
572 #define TARGET_PROP "target"
573 #define LUN_PROP "lun"
574 #define LUN64_PROP "lun64"
575 #define SAS_PROP "sas-mpt"
576 #define MDI_GUID "wwn"
577 #define NDI_GUID "guid"
578 #define MPTSAS_DEV_GONE "mptsas_dev_gone"
579
580 /*
581 * Local static data
582 */
583 #if defined(MPTSAS_DEBUG)
584 uint32_t mptsas_debug_flags = 0;
585 #endif /* defined(MPTSAS_DEBUG) */
586 uint32_t mptsas_debug_resets = 0;
587
588 static kmutex_t mptsas_global_mutex;
589 static void *mptsas_state; /* soft state ptr */
590 static krwlock_t mptsas_global_rwlock;
591
592 static kmutex_t mptsas_log_mutex;
593 static char mptsas_log_buf[256];
594 _NOTE(MUTEX_PROTECTS_DATA(mptsas_log_mutex, mptsas_log_buf))
595
596 static mptsas_t *mptsas_head, *mptsas_tail;
597 static clock_t mptsas_scsi_watchdog_tick;
598 static clock_t mptsas_tick;
599 static timeout_id_t mptsas_reset_watch;
600 static timeout_id_t mptsas_timeout_id;
601 static int mptsas_timeouts_enabled = 0;
602 /*
603 * warlock directives
604 */
605 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", scsi_pkt \
606 mptsas_cmd NcrTableIndirect buf scsi_cdb scsi_status))
607 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", smp_pkt))
608 _NOTE(SCHEME_PROTECTS_DATA("stable data", scsi_device scsi_address))
609 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", mptsas_tgt_private))
610 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", scsi_hba_tran::tran_tgt_private))
611
612 /*
613 * SM - HBA statics
614 */
615 char *mptsas_driver_rev = MPTSAS_MOD_STRING;
616
617 #ifdef MPTSAS_DEBUG
618 void debug_enter(char *);
619 #endif
620
621 /*
622 * Notes:
623 * - scsi_hba_init(9F) initializes SCSI HBA modules
624 * - must call scsi_hba_fini(9F) if modload() fails
625 */
626 int
627 _init(void)
628 {
629 int status;
630 /* CONSTCOND */
631 ASSERT(NO_COMPETING_THREADS);
632
633 NDBG0(("_init"));
634
635 status = ddi_soft_state_init(&mptsas_state, MPTSAS_SIZE,
636 MPTSAS_INITIAL_SOFT_SPACE);
637 if (status != 0) {
638 return (status);
639 }
640
641 if ((status = scsi_hba_init(&modlinkage)) != 0) {
642 ddi_soft_state_fini(&mptsas_state);
643 return (status);
644 }
645
646 mutex_init(&mptsas_global_mutex, NULL, MUTEX_DRIVER, NULL);
647 rw_init(&mptsas_global_rwlock, NULL, RW_DRIVER, NULL);
648 mutex_init(&mptsas_log_mutex, NULL, MUTEX_DRIVER, NULL);
649
650 if ((status = mod_install(&modlinkage)) != 0) {
651 mutex_destroy(&mptsas_log_mutex);
652 rw_destroy(&mptsas_global_rwlock);
653 mutex_destroy(&mptsas_global_mutex);
654 ddi_soft_state_fini(&mptsas_state);
655 scsi_hba_fini(&modlinkage);
656 }
657
658 return (status);
659 }
660
661 /*
662 * Notes:
663 * - scsi_hba_fini(9F) uninitializes SCSI HBA modules
664 */
665 int
666 _fini(void)
667 {
668 int status;
669 /* CONSTCOND */
670 ASSERT(NO_COMPETING_THREADS);
671
672 NDBG0(("_fini"));
673
674 if ((status = mod_remove(&modlinkage)) == 0) {
675 ddi_soft_state_fini(&mptsas_state);
676 scsi_hba_fini(&modlinkage);
677 mutex_destroy(&mptsas_global_mutex);
678 rw_destroy(&mptsas_global_rwlock);
679 mutex_destroy(&mptsas_log_mutex);
680 }
681 return (status);
682 }
683
684 /*
685 * The loadable-module _info(9E) entry point
686 */
687 int
688 _info(struct modinfo *modinfop)
689 {
690 /* CONSTCOND */
691 ASSERT(NO_COMPETING_THREADS);
692 NDBG0(("mptsas _info"));
693
694 return (mod_info(&modlinkage, modinfop));
695 }
696
697
698 static int
699 mptsas_iport_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
700 {
701 dev_info_t *pdip;
702 mptsas_t *mpt;
703 scsi_hba_tran_t *hba_tran;
704 char *iport = NULL;
705 char phymask[MPTSAS_MAX_PHYS];
706 mptsas_phymask_t phy_mask = 0;
707 int dynamic_port = 0;
708 uint32_t page_address;
709 char initiator_wwnstr[MPTSAS_WWN_STRLEN];
710 int rval = DDI_FAILURE;
711 int i = 0;
712 uint8_t numphys = 0;
713 uint8_t phy_id;
714 uint8_t phy_port = 0;
715 uint16_t attached_devhdl = 0;
716 uint32_t dev_info;
717 uint64_t attached_sas_wwn;
718 uint16_t dev_hdl;
719 uint16_t pdev_hdl;
720 uint16_t bay_num, enclosure;
721 char attached_wwnstr[MPTSAS_WWN_STRLEN];
722
723 /* CONSTCOND */
724 ASSERT(NO_COMPETING_THREADS);
725
726 switch (cmd) {
727 case DDI_ATTACH:
728 break;
729
730 case DDI_RESUME:
731 /*
732 * If this a scsi-iport node, nothing to do here.
733 */
734 return (DDI_SUCCESS);
735
736 default:
737 return (DDI_FAILURE);
738 }
739
740 pdip = ddi_get_parent(dip);
741
742 if ((hba_tran = ndi_flavorv_get(pdip, SCSA_FLAVOR_SCSI_DEVICE)) ==
743 NULL) {
744 cmn_err(CE_WARN, "Failed attach iport because fail to "
745 "get tran vector for the HBA node");
746 return (DDI_FAILURE);
747 }
748
749 mpt = TRAN2MPT(hba_tran);
750 ASSERT(mpt != NULL);
751 if (mpt == NULL)
752 return (DDI_FAILURE);
753
754 if ((hba_tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) ==
755 NULL) {
756 mptsas_log(mpt, CE_WARN, "Failed attach iport because fail to "
757 "get tran vector for the iport node");
758 return (DDI_FAILURE);
759 }
760
761 /*
762 * Overwrite parent's tran_hba_private to iport's tran vector
763 */
764 hba_tran->tran_hba_private = mpt;
765
766 ddi_report_dev(dip);
767
768 /*
769 * Get SAS address for initiator port according dev_handle
770 */
771 iport = ddi_get_name_addr(dip);
772 if (iport && strncmp(iport, "v0", 2) == 0) {
773 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
774 MPTSAS_VIRTUAL_PORT, 1) !=
775 DDI_PROP_SUCCESS) {
776 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
777 MPTSAS_VIRTUAL_PORT);
778 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
779 "prop update failed");
780 return (DDI_FAILURE);
781 }
782 return (DDI_SUCCESS);
783 }
784
785 mutex_enter(&mpt->m_mutex);
786 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
787 bzero(phymask, sizeof (phymask));
788 (void) sprintf(phymask,
789 "%x", mpt->m_phy_info[i].phy_mask);
790 if (strcmp(phymask, iport) == 0) {
791 break;
792 }
793 }
794
795 if (i == MPTSAS_MAX_PHYS) {
796 mptsas_log(mpt, CE_WARN, "Failed attach port %s because port"
797 "seems not exist", iport);
798 mutex_exit(&mpt->m_mutex);
799 return (DDI_FAILURE);
800 }
801
802 phy_mask = mpt->m_phy_info[i].phy_mask;
803
804 if (mpt->m_phy_info[i].port_flags & AUTO_PORT_CONFIGURATION)
805 dynamic_port = 1;
806 else
807 dynamic_port = 0;
808
809 /*
810 * Update PHY info for smhba
811 */
812 if (mptsas_smhba_phy_init(mpt)) {
813 mutex_exit(&mpt->m_mutex);
814 mptsas_log(mpt, CE_WARN, "mptsas phy update "
815 "failed");
816 return (DDI_FAILURE);
817 }
818
819 mutex_exit(&mpt->m_mutex);
820
821 numphys = 0;
822 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
823 if ((phy_mask >> i) & 0x01) {
824 numphys++;
825 }
826 }
827
828 bzero(initiator_wwnstr, sizeof (initiator_wwnstr));
829 (void) sprintf(initiator_wwnstr, "w%016"PRIx64,
830 mpt->un.m_base_wwid);
831
832 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip,
833 SCSI_ADDR_PROP_INITIATOR_PORT, initiator_wwnstr) !=
834 DDI_PROP_SUCCESS) {
835 (void) ddi_prop_remove(DDI_DEV_T_NONE,
836 dip, SCSI_ADDR_PROP_INITIATOR_PORT);
837 mptsas_log(mpt, CE_WARN, "mptsas Initiator port "
838 "prop update failed");
839 return (DDI_FAILURE);
840 }
841 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
842 MPTSAS_NUM_PHYS, numphys) !=
843 DDI_PROP_SUCCESS) {
844 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, MPTSAS_NUM_PHYS);
845 return (DDI_FAILURE);
846 }
847
848 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
849 "phymask", phy_mask) !=
850 DDI_PROP_SUCCESS) {
851 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "phymask");
852 mptsas_log(mpt, CE_WARN, "mptsas phy mask "
853 "prop update failed");
854 return (DDI_FAILURE);
855 }
856
857 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
858 "dynamic-port", dynamic_port) !=
859 DDI_PROP_SUCCESS) {
860 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "dynamic-port");
861 mptsas_log(mpt, CE_WARN, "mptsas dynamic port "
862 "prop update failed");
863 return (DDI_FAILURE);
864 }
865 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
866 MPTSAS_VIRTUAL_PORT, 0) !=
867 DDI_PROP_SUCCESS) {
868 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
869 MPTSAS_VIRTUAL_PORT);
870 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
871 "prop update failed");
872 return (DDI_FAILURE);
873 }
874 mptsas_smhba_set_phy_props(mpt,
875 iport, dip, numphys, &attached_devhdl);
876
877 mutex_enter(&mpt->m_mutex);
878 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
879 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)attached_devhdl;
880 rval = mptsas_get_sas_device_page0(mpt, page_address, &dev_hdl,
881 &attached_sas_wwn, &dev_info, &phy_port, &phy_id,
882 &pdev_hdl, &bay_num, &enclosure);
883 if (rval != DDI_SUCCESS) {
884 mptsas_log(mpt, CE_WARN,
885 "Failed to get device page0 for handle:%d",
886 attached_devhdl);
887 mutex_exit(&mpt->m_mutex);
888 return (DDI_FAILURE);
889 }
890
891 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
892 bzero(phymask, sizeof (phymask));
893 (void) sprintf(phymask, "%x", mpt->m_phy_info[i].phy_mask);
894 if (strcmp(phymask, iport) == 0) {
895 (void) sprintf(&mpt->m_phy_info[i].smhba_info.path[0],
896 "%x",
897 mpt->m_phy_info[i].phy_mask);
898 }
899 }
900 mutex_exit(&mpt->m_mutex);
901
902 bzero(attached_wwnstr, sizeof (attached_wwnstr));
903 (void) sprintf(attached_wwnstr, "w%016"PRIx64,
904 attached_sas_wwn);
905 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip,
906 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
907 DDI_PROP_SUCCESS) {
908 (void) ddi_prop_remove(DDI_DEV_T_NONE,
909 dip, SCSI_ADDR_PROP_ATTACHED_PORT);
910 return (DDI_FAILURE);
911 }
912
913 /* Create kstats for each phy on this iport */
914
915 mptsas_create_phy_stats(mpt, iport, dip);
916
917 /*
918 * register sas hba iport with mdi (MPxIO/vhci)
919 */
920 if (mdi_phci_register(MDI_HCI_CLASS_SCSI,
921 dip, 0) == MDI_SUCCESS) {
922 mpt->m_mpxio_enable = TRUE;
923 }
924 return (DDI_SUCCESS);
925 }
926
927 /*
928 * Notes:
929 * Set up all device state and allocate data structures,
930 * mutexes, condition variables, etc. for device operation.
931 * Add interrupts needed.
932 * Return DDI_SUCCESS if device is ready, else return DDI_FAILURE.
933 */
934 static int
935 mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
936 {
937 mptsas_t *mpt = NULL;
938 int instance, i, j;
939 int doneq_thread_num;
940 char intr_added = 0;
941 char map_setup = 0;
942 char config_setup = 0;
943 char hba_attach_setup = 0;
944 char smp_attach_setup = 0;
945 char mutex_init_done = 0;
946 char event_taskq_create = 0;
947 char dr_taskq_create = 0;
948 char doneq_thread_create = 0;
949 scsi_hba_tran_t *hba_tran;
950 uint_t mem_bar = MEM_SPACE;
951 int rval = DDI_FAILURE;
952
953 /* CONSTCOND */
954 ASSERT(NO_COMPETING_THREADS);
955
956 if (scsi_hba_iport_unit_address(dip)) {
957 return (mptsas_iport_attach(dip, cmd));
958 }
959
960 switch (cmd) {
961 case DDI_ATTACH:
962 break;
963
964 case DDI_RESUME:
965 if ((hba_tran = ddi_get_driver_private(dip)) == NULL)
966 return (DDI_FAILURE);
967
968 mpt = TRAN2MPT(hba_tran);
969
970 if (!mpt) {
971 return (DDI_FAILURE);
972 }
973
974 /*
975 * Reset hardware and softc to "no outstanding commands"
976 * Note that a check condition can result on first command
977 * to a target.
978 */
979 mutex_enter(&mpt->m_mutex);
980
981 /*
982 * raise power.
983 */
984 if (mpt->m_options & MPTSAS_OPT_PM) {
985 mutex_exit(&mpt->m_mutex);
986 (void) pm_busy_component(dip, 0);
987 rval = pm_power_has_changed(dip, 0, PM_LEVEL_D0);
988 if (rval == DDI_SUCCESS) {
989 mutex_enter(&mpt->m_mutex);
990 } else {
991 /*
992 * The pm_raise_power() call above failed,
993 * and that can only occur if we were unable
994 * to reset the hardware. This is probably
995 * due to unhealty hardware, and because
996 * important filesystems(such as the root
997 * filesystem) could be on the attached disks,
998 * it would not be a good idea to continue,
999 * as we won't be entirely certain we are
1000 * writing correct data. So we panic() here
1001 * to not only prevent possible data corruption,
1002 * but to give developers or end users a hope
1003 * of identifying and correcting any problems.
1004 */
1005 fm_panic("mptsas could not reset hardware "
1006 "during resume");
1007 }
1008 }
1009
1010 mpt->m_suspended = 0;
1011
1012 /*
1013 * Reinitialize ioc
1014 */
1015 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1016 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) {
1017 mutex_exit(&mpt->m_mutex);
1018 if (mpt->m_options & MPTSAS_OPT_PM) {
1019 (void) pm_idle_component(dip, 0);
1020 }
1021 fm_panic("mptsas init chip fail during resume");
1022 }
1023 /*
1024 * mptsas_update_driver_data needs interrupts so enable them
1025 * first.
1026 */
1027 MPTSAS_ENABLE_INTR(mpt);
1028 mptsas_update_driver_data(mpt);
1029
1030 /* start requests, if possible */
1031 mptsas_restart_hba(mpt);
1032
1033 mutex_exit(&mpt->m_mutex);
1034
1035 /*
1036 * Restart watch thread
1037 */
1038 mutex_enter(&mptsas_global_mutex);
1039 if (mptsas_timeout_id == 0) {
1040 mptsas_timeout_id = timeout(mptsas_watch, NULL,
1041 mptsas_tick);
1042 mptsas_timeouts_enabled = 1;
1043 }
1044 mutex_exit(&mptsas_global_mutex);
1045
1046 /* report idle status to pm framework */
1047 if (mpt->m_options & MPTSAS_OPT_PM) {
1048 (void) pm_idle_component(dip, 0);
1049 }
1050
1051 return (DDI_SUCCESS);
1052
1053 default:
1054 return (DDI_FAILURE);
1055
1056 }
1057
1058 instance = ddi_get_instance(dip);
1059
1060 /*
1061 * Allocate softc information.
1062 */
1063 if (ddi_soft_state_zalloc(mptsas_state, instance) != DDI_SUCCESS) {
1064 mptsas_log(NULL, CE_WARN,
1065 "mptsas%d: cannot allocate soft state", instance);
1066 goto fail;
1067 }
1068
1069 mpt = ddi_get_soft_state(mptsas_state, instance);
1070
1071 if (mpt == NULL) {
1072 mptsas_log(NULL, CE_WARN,
1073 "mptsas%d: cannot get soft state", instance);
1074 goto fail;
1075 }
1076
1077 /* Indicate that we are 'sizeof (scsi_*(9S))' clean. */
1078 scsi_size_clean(dip);
1079
1080 mpt->m_dip = dip;
1081 mpt->m_instance = instance;
1082
1083 /* Make a per-instance copy of the structures */
1084 mpt->m_io_dma_attr = mptsas_dma_attrs64;
1085 mpt->m_msg_dma_attr = mptsas_dma_attrs;
1086 mpt->m_reg_acc_attr = mptsas_dev_attr;
1087 mpt->m_dev_acc_attr = mptsas_dev_attr;
1088
1089 /*
1090 * Initialize FMA
1091 */
1092 mpt->m_fm_capabilities = ddi_getprop(DDI_DEV_T_ANY, mpt->m_dip,
1093 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable",
1094 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
1095 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
1096
1097 mptsas_fm_init(mpt);
1098
1099 if (mptsas_alloc_handshake_msg(mpt,
1100 sizeof (Mpi2SCSITaskManagementRequest_t)) == DDI_FAILURE) {
1101 mptsas_log(mpt, CE_WARN, "cannot initialize handshake msg.");
1102 goto fail;
1103 }
1104
1105 /*
1106 * Setup configuration space
1107 */
1108 if (mptsas_config_space_init(mpt) == FALSE) {
1109 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init failed");
1110 goto fail;
1111 }
1112 config_setup++;
1113
1114 if (ddi_regs_map_setup(dip, mem_bar, (caddr_t *)&mpt->m_reg,
1115 0, 0, &mpt->m_reg_acc_attr, &mpt->m_datap) != DDI_SUCCESS) {
1116 mptsas_log(mpt, CE_WARN, "map setup failed");
1117 goto fail;
1118 }
1119 map_setup++;
1120
1121 /*
1122 * A taskq is created for dealing with the event handler
1123 */
1124 if ((mpt->m_event_taskq = ddi_taskq_create(dip, "mptsas_event_taskq",
1125 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
1126 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create failed");
1127 goto fail;
1128 }
1129 event_taskq_create++;
1130
1131 /*
1132 * A taskq is created for dealing with dr events
1133 */
1134 if ((mpt->m_dr_taskq = ddi_taskq_create(dip,
1135 "mptsas_dr_taskq",
1136 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
1137 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create for discovery "
1138 "failed");
1139 goto fail;
1140 }
1141 dr_taskq_create++;
1142
1143 mpt->m_doneq_thread_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1144 0, "mptsas_doneq_thread_threshold_prop", 10);
1145 mpt->m_doneq_length_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1146 0, "mptsas_doneq_length_threshold_prop", 8);
1147 mpt->m_doneq_thread_n = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1148 0, "mptsas_doneq_thread_n_prop", 8);
1149
1150 if (mpt->m_doneq_thread_n) {
1151 cv_init(&mpt->m_doneq_thread_cv, NULL, CV_DRIVER, NULL);
1152 mutex_init(&mpt->m_doneq_mutex, NULL, MUTEX_DRIVER, NULL);
1153
1154 mutex_enter(&mpt->m_doneq_mutex);
1155 mpt->m_doneq_thread_id =
1156 kmem_zalloc(sizeof (mptsas_doneq_thread_list_t)
1157 * mpt->m_doneq_thread_n, KM_SLEEP);
1158
1159 for (j = 0; j < mpt->m_doneq_thread_n; j++) {
1160 cv_init(&mpt->m_doneq_thread_id[j].cv, NULL,
1161 CV_DRIVER, NULL);
1162 mutex_init(&mpt->m_doneq_thread_id[j].mutex, NULL,
1163 MUTEX_DRIVER, NULL);
1164 mutex_enter(&mpt->m_doneq_thread_id[j].mutex);
1165 mpt->m_doneq_thread_id[j].flag |=
1166 MPTSAS_DONEQ_THREAD_ACTIVE;
1167 mpt->m_doneq_thread_id[j].arg.mpt = mpt;
1168 mpt->m_doneq_thread_id[j].arg.t = j;
1169 mpt->m_doneq_thread_id[j].threadp =
1170 thread_create(NULL, 0, mptsas_doneq_thread,
1171 &mpt->m_doneq_thread_id[j].arg,
1172 0, &p0, TS_RUN, minclsyspri);
1173 mpt->m_doneq_thread_id[j].donetail =
1174 &mpt->m_doneq_thread_id[j].doneq;
1175 mutex_exit(&mpt->m_doneq_thread_id[j].mutex);
1176 }
1177 mutex_exit(&mpt->m_doneq_mutex);
1178 doneq_thread_create++;
1179 }
1180
1181 /* Initialize mutex used in interrupt handler */
1182 mutex_init(&mpt->m_mutex, NULL, MUTEX_DRIVER,
1183 DDI_INTR_PRI(mpt->m_intr_pri));
1184 mutex_init(&mpt->m_passthru_mutex, NULL, MUTEX_DRIVER, NULL);
1185 mutex_init(&mpt->m_tx_waitq_mutex, NULL, MUTEX_DRIVER,
1186 DDI_INTR_PRI(mpt->m_intr_pri));
1187 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1188 mutex_init(&mpt->m_phy_info[i].smhba_info.phy_mutex,
1189 NULL, MUTEX_DRIVER,
1190 DDI_INTR_PRI(mpt->m_intr_pri));
1191 }
1192
1193 cv_init(&mpt->m_cv, NULL, CV_DRIVER, NULL);
1194 cv_init(&mpt->m_passthru_cv, NULL, CV_DRIVER, NULL);
1195 cv_init(&mpt->m_fw_cv, NULL, CV_DRIVER, NULL);
1196 cv_init(&mpt->m_config_cv, NULL, CV_DRIVER, NULL);
1197 cv_init(&mpt->m_fw_diag_cv, NULL, CV_DRIVER, NULL);
1198 mutex_init_done++;
1199
1200 /*
1201 * Disable hardware interrupt since we're not ready to
1202 * handle it yet.
1203 */
1204 MPTSAS_DISABLE_INTR(mpt);
1205 if (mptsas_register_intrs(mpt) == FALSE)
1206 goto fail;
1207 intr_added++;
1208
1209 mutex_enter(&mpt->m_mutex);
1210 /*
1211 * Initialize power management component
1212 */
1213 if (mpt->m_options & MPTSAS_OPT_PM) {
1214 if (mptsas_init_pm(mpt)) {
1215 mutex_exit(&mpt->m_mutex);
1216 mptsas_log(mpt, CE_WARN, "mptsas pm initialization "
1217 "failed");
1218 goto fail;
1219 }
1220 }
1221
1222 /*
1223 * Initialize chip using Message Unit Reset, if allowed
1224 */
1225 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1226 if (mptsas_init_chip(mpt, TRUE) == DDI_FAILURE) {
1227 mutex_exit(&mpt->m_mutex);
1228 mptsas_log(mpt, CE_WARN, "mptsas chip initialization failed");
1229 goto fail;
1230 }
1231
1232 /*
1233 * Fill in the phy_info structure and get the base WWID
1234 */
1235 if (mptsas_get_manufacture_page5(mpt) == DDI_FAILURE) {
1236 mptsas_log(mpt, CE_WARN,
1237 "mptsas_get_manufacture_page5 failed!");
1238 goto fail;
1239 }
1240
1241 if (mptsas_get_sas_io_unit_page_hndshk(mpt)) {
1242 mptsas_log(mpt, CE_WARN,
1243 "mptsas_get_sas_io_unit_page_hndshk failed!");
1244 goto fail;
1245 }
1246
1247 if (mptsas_get_manufacture_page0(mpt) == DDI_FAILURE) {
1248 mptsas_log(mpt, CE_WARN,
1249 "mptsas_get_manufacture_page0 failed!");
1250 goto fail;
1251 }
1252
1253 mutex_exit(&mpt->m_mutex);
1254
1255 /*
1256 * Register the iport for multiple port HBA
1257 */
1258 mptsas_iport_register(mpt);
1259
1260 /*
1261 * initialize SCSI HBA transport structure
1262 */
1263 if (mptsas_hba_setup(mpt) == FALSE)
1264 goto fail;
1265 hba_attach_setup++;
1266
1267 if (mptsas_smp_setup(mpt) == FALSE)
1268 goto fail;
1269 smp_attach_setup++;
1270
1271 if (mptsas_cache_create(mpt) == FALSE)
1272 goto fail;
1273
1274 mpt->m_scsi_reset_delay = ddi_prop_get_int(DDI_DEV_T_ANY,
1275 dip, 0, "scsi-reset-delay", SCSI_DEFAULT_RESET_DELAY);
1276 if (mpt->m_scsi_reset_delay == 0) {
1277 mptsas_log(mpt, CE_NOTE,
1278 "scsi_reset_delay of 0 is not recommended,"
1279 " resetting to SCSI_DEFAULT_RESET_DELAY\n");
1280 mpt->m_scsi_reset_delay = SCSI_DEFAULT_RESET_DELAY;
1281 }
1282
1283 /*
1284 * Initialize the wait and done FIFO queue
1285 */
1286 mpt->m_donetail = &mpt->m_doneq;
1287 mpt->m_waitqtail = &mpt->m_waitq;
1288 mpt->m_tx_waitqtail = &mpt->m_tx_waitq;
1289 mpt->m_tx_draining = 0;
1290
1291 /*
1292 * ioc cmd queue initialize
1293 */
1294 mpt->m_ioc_event_cmdtail = &mpt->m_ioc_event_cmdq;
1295 mpt->m_dev_handle = 0xFFFF;
1296
1297 MPTSAS_ENABLE_INTR(mpt);
1298
1299 /*
1300 * enable event notification
1301 */
1302 mutex_enter(&mpt->m_mutex);
1303 if (mptsas_ioc_enable_event_notification(mpt)) {
1304 mutex_exit(&mpt->m_mutex);
1305 goto fail;
1306 }
1307 mutex_exit(&mpt->m_mutex);
1308
1309 /*
1310 * Initialize PHY info for smhba
1311 */
1312 if (mptsas_smhba_setup(mpt)) {
1313 mptsas_log(mpt, CE_WARN, "mptsas phy initialization "
1314 "failed");
1315 goto fail;
1316 }
1317
1318 /* Check all dma handles allocated in attach */
1319 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl)
1320 != DDI_SUCCESS) ||
1321 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl)
1322 != DDI_SUCCESS) ||
1323 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl)
1324 != DDI_SUCCESS) ||
1325 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl)
1326 != DDI_SUCCESS) ||
1327 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl)
1328 != DDI_SUCCESS)) {
1329 goto fail;
1330 }
1331
1332 /* Check all acc handles allocated in attach */
1333 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) ||
1334 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl)
1335 != DDI_SUCCESS) ||
1336 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl)
1337 != DDI_SUCCESS) ||
1338 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl)
1339 != DDI_SUCCESS) ||
1340 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl)
1341 != DDI_SUCCESS) ||
1342 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl)
1343 != DDI_SUCCESS) ||
1344 (mptsas_check_acc_handle(mpt->m_config_handle)
1345 != DDI_SUCCESS)) {
1346 goto fail;
1347 }
1348
1349 /*
1350 * After this point, we are not going to fail the attach.
1351 */
1352 /*
1353 * used for mptsas_watch
1354 */
1355 mptsas_list_add(mpt);
1356
1357 mutex_enter(&mptsas_global_mutex);
1358 if (mptsas_timeouts_enabled == 0) {
1359 mptsas_scsi_watchdog_tick = ddi_prop_get_int(DDI_DEV_T_ANY,
1360 dip, 0, "scsi-watchdog-tick", DEFAULT_WD_TICK);
1361
1362 mptsas_tick = mptsas_scsi_watchdog_tick *
1363 drv_usectohz((clock_t)1000000);
1364
1365 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick);
1366 mptsas_timeouts_enabled = 1;
1367 }
1368 mutex_exit(&mptsas_global_mutex);
1369
1370 /* Print message of HBA present */
1371 ddi_report_dev(dip);
1372
1373 /* report idle status to pm framework */
1374 if (mpt->m_options & MPTSAS_OPT_PM) {
1375 (void) pm_idle_component(dip, 0);
1376 }
1377
1378 return (DDI_SUCCESS);
1379
1380 fail:
1381 mptsas_log(mpt, CE_WARN, "attach failed");
1382 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE);
1383 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST);
1384 if (mpt) {
1385 mutex_enter(&mptsas_global_mutex);
1386
1387 if (mptsas_timeout_id && (mptsas_head == NULL)) {
1388 timeout_id_t tid = mptsas_timeout_id;
1389 mptsas_timeouts_enabled = 0;
1390 mptsas_timeout_id = 0;
1391 mutex_exit(&mptsas_global_mutex);
1392 (void) untimeout(tid);
1393 mutex_enter(&mptsas_global_mutex);
1394 }
1395 mutex_exit(&mptsas_global_mutex);
1396 /* deallocate in reverse order */
1397 mptsas_cache_destroy(mpt);
1398
1399 if (smp_attach_setup) {
1400 mptsas_smp_teardown(mpt);
1401 }
1402 if (hba_attach_setup) {
1403 mptsas_hba_teardown(mpt);
1404 }
1405
1406 if (mpt->m_active) {
1407 mptsas_hash_uninit(&mpt->m_active->m_smptbl,
1408 sizeof (mptsas_smp_t));
1409 mptsas_hash_uninit(&mpt->m_active->m_tgttbl,
1410 sizeof (mptsas_target_t));
1411 mptsas_free_active_slots(mpt);
1412 }
1413 if (intr_added) {
1414 mptsas_unregister_intrs(mpt);
1415 }
1416
1417 if (doneq_thread_create) {
1418 mutex_enter(&mpt->m_doneq_mutex);
1419 doneq_thread_num = mpt->m_doneq_thread_n;
1420 for (j = 0; j < mpt->m_doneq_thread_n; j++) {
1421 mutex_enter(&mpt->m_doneq_thread_id[j].mutex);
1422 mpt->m_doneq_thread_id[j].flag &=
1423 (~MPTSAS_DONEQ_THREAD_ACTIVE);
1424 cv_signal(&mpt->m_doneq_thread_id[j].cv);
1425 mutex_exit(&mpt->m_doneq_thread_id[j].mutex);
1426 }
1427 while (mpt->m_doneq_thread_n) {
1428 cv_wait(&mpt->m_doneq_thread_cv,
1429 &mpt->m_doneq_mutex);
1430 }
1431 for (j = 0; j < doneq_thread_num; j++) {
1432 cv_destroy(&mpt->m_doneq_thread_id[j].cv);
1433 mutex_destroy(&mpt->m_doneq_thread_id[j].mutex);
1434 }
1435 kmem_free(mpt->m_doneq_thread_id,
1436 sizeof (mptsas_doneq_thread_list_t)
1437 * doneq_thread_num);
1438 mutex_exit(&mpt->m_doneq_mutex);
1439 cv_destroy(&mpt->m_doneq_thread_cv);
1440 mutex_destroy(&mpt->m_doneq_mutex);
1441 }
1442 if (event_taskq_create) {
1443 ddi_taskq_destroy(mpt->m_event_taskq);
1444 }
1445 if (dr_taskq_create) {
1446 ddi_taskq_destroy(mpt->m_dr_taskq);
1447 }
1448 if (mutex_init_done) {
1449 mutex_destroy(&mpt->m_tx_waitq_mutex);
1450 mutex_destroy(&mpt->m_passthru_mutex);
1451 mutex_destroy(&mpt->m_mutex);
1452 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1453 mutex_destroy(
1454 &mpt->m_phy_info[i].smhba_info.phy_mutex);
1455 }
1456 cv_destroy(&mpt->m_cv);
1457 cv_destroy(&mpt->m_passthru_cv);
1458 cv_destroy(&mpt->m_fw_cv);
1459 cv_destroy(&mpt->m_config_cv);
1460 cv_destroy(&mpt->m_fw_diag_cv);
1461 }
1462
1463 if (map_setup) {
1464 mptsas_cfg_fini(mpt);
1465 }
1466 if (config_setup) {
1467 mptsas_config_space_fini(mpt);
1468 }
1469 mptsas_free_handshake_msg(mpt);
1470 mptsas_hba_fini(mpt);
1471
1472 mptsas_fm_fini(mpt);
1473 ddi_soft_state_free(mptsas_state, instance);
1474 ddi_prop_remove_all(dip);
1475 }
1476 return (DDI_FAILURE);
1477 }
1478
1479 static int
1480 mptsas_suspend(dev_info_t *devi)
1481 {
1482 mptsas_t *mpt, *g;
1483 scsi_hba_tran_t *tran;
1484
1485 if (scsi_hba_iport_unit_address(devi)) {
1486 return (DDI_SUCCESS);
1487 }
1488
1489 if ((tran = ddi_get_driver_private(devi)) == NULL)
1490 return (DDI_SUCCESS);
1491
1492 mpt = TRAN2MPT(tran);
1493 if (!mpt) {
1494 return (DDI_SUCCESS);
1495 }
1496
1497 mutex_enter(&mpt->m_mutex);
1498
1499 if (mpt->m_suspended++) {
1500 mutex_exit(&mpt->m_mutex);
1501 return (DDI_SUCCESS);
1502 }
1503
1504 /*
1505 * Cancel timeout threads for this mpt
1506 */
1507 if (mpt->m_quiesce_timeid) {
1508 timeout_id_t tid = mpt->m_quiesce_timeid;
1509 mpt->m_quiesce_timeid = 0;
1510 mutex_exit(&mpt->m_mutex);
1511 (void) untimeout(tid);
1512 mutex_enter(&mpt->m_mutex);
1513 }
1514
1515 if (mpt->m_restart_cmd_timeid) {
1516 timeout_id_t tid = mpt->m_restart_cmd_timeid;
1517 mpt->m_restart_cmd_timeid = 0;
1518 mutex_exit(&mpt->m_mutex);
1519 (void) untimeout(tid);
1520 mutex_enter(&mpt->m_mutex);
1521 }
1522
1523 mutex_exit(&mpt->m_mutex);
1524
1525 (void) pm_idle_component(mpt->m_dip, 0);
1526
1527 /*
1528 * Cancel watch threads if all mpts suspended
1529 */
1530 rw_enter(&mptsas_global_rwlock, RW_WRITER);
1531 for (g = mptsas_head; g != NULL; g = g->m_next) {
1532 if (!g->m_suspended)
1533 break;
1534 }
1535 rw_exit(&mptsas_global_rwlock);
1536
1537 mutex_enter(&mptsas_global_mutex);
1538 if (g == NULL) {
1539 timeout_id_t tid;
1540
1541 mptsas_timeouts_enabled = 0;
1542 if (mptsas_timeout_id) {
1543 tid = mptsas_timeout_id;
1544 mptsas_timeout_id = 0;
1545 mutex_exit(&mptsas_global_mutex);
1546 (void) untimeout(tid);
1547 mutex_enter(&mptsas_global_mutex);
1548 }
1549 if (mptsas_reset_watch) {
1550 tid = mptsas_reset_watch;
1551 mptsas_reset_watch = 0;
1552 mutex_exit(&mptsas_global_mutex);
1553 (void) untimeout(tid);
1554 mutex_enter(&mptsas_global_mutex);
1555 }
1556 }
1557 mutex_exit(&mptsas_global_mutex);
1558
1559 mutex_enter(&mpt->m_mutex);
1560
1561 /*
1562 * If this mpt is not in full power(PM_LEVEL_D0), just return.
1563 */
1564 if ((mpt->m_options & MPTSAS_OPT_PM) &&
1565 (mpt->m_power_level != PM_LEVEL_D0)) {
1566 mutex_exit(&mpt->m_mutex);
1567 return (DDI_SUCCESS);
1568 }
1569
1570 /* Disable HBA interrupts in hardware */
1571 MPTSAS_DISABLE_INTR(mpt);
1572 /*
1573 * Send RAID action system shutdown to sync IR
1574 */
1575 mptsas_raid_action_system_shutdown(mpt);
1576
1577 mutex_exit(&mpt->m_mutex);
1578
1579 /* drain the taskq */
1580 ddi_taskq_wait(mpt->m_event_taskq);
1581 ddi_taskq_wait(mpt->m_dr_taskq);
1582
1583 return (DDI_SUCCESS);
1584 }
1585
1586 #ifdef __sparc
1587 /*ARGSUSED*/
1588 static int
1589 mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd)
1590 {
1591 mptsas_t *mpt;
1592 scsi_hba_tran_t *tran;
1593
1594 /*
1595 * If this call is for iport, just return.
1596 */
1597 if (scsi_hba_iport_unit_address(devi))
1598 return (DDI_SUCCESS);
1599
1600 if ((tran = ddi_get_driver_private(devi)) == NULL)
1601 return (DDI_SUCCESS);
1602
1603 if ((mpt = TRAN2MPT(tran)) == NULL)
1604 return (DDI_SUCCESS);
1605
1606 /*
1607 * Send RAID action system shutdown to sync IR. Disable HBA
1608 * interrupts in hardware first.
1609 */
1610 MPTSAS_DISABLE_INTR(mpt);
1611 mptsas_raid_action_system_shutdown(mpt);
1612
1613 return (DDI_SUCCESS);
1614 }
1615 #else /* __sparc */
1616 /*
1617 * quiesce(9E) entry point.
1618 *
1619 * This function is called when the system is single-threaded at high
1620 * PIL with preemption disabled. Therefore, this function must not be
1621 * blocked.
1622 *
1623 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
1624 * DDI_FAILURE indicates an error condition and should almost never happen.
1625 */
1626 static int
1627 mptsas_quiesce(dev_info_t *devi)
1628 {
1629 mptsas_t *mpt;
1630 scsi_hba_tran_t *tran;
1631
1632 /*
1633 * If this call is for iport, just return.
1634 */
1635 if (scsi_hba_iport_unit_address(devi))
1636 return (DDI_SUCCESS);
1637
1638 if ((tran = ddi_get_driver_private(devi)) == NULL)
1639 return (DDI_SUCCESS);
1640
1641 if ((mpt = TRAN2MPT(tran)) == NULL)
1642 return (DDI_SUCCESS);
1643
1644 /* Disable HBA interrupts in hardware */
1645 MPTSAS_DISABLE_INTR(mpt);
1646 /* Send RAID action system shutdonw to sync IR */
1647 mptsas_raid_action_system_shutdown(mpt);
1648
1649 return (DDI_SUCCESS);
1650 }
1651 #endif /* __sparc */
1652
1653 /*
1654 * detach(9E). Remove all device allocations and system resources;
1655 * disable device interrupts.
1656 * Return DDI_SUCCESS if done; DDI_FAILURE if there's a problem.
1657 */
1658 static int
1659 mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd)
1660 {
1661 /* CONSTCOND */
1662 ASSERT(NO_COMPETING_THREADS);
1663 NDBG0(("mptsas_detach: dip=0x%p cmd=0x%p", (void *)devi, (void *)cmd));
1664
1665 switch (cmd) {
1666 case DDI_DETACH:
1667 return (mptsas_do_detach(devi));
1668
1669 case DDI_SUSPEND:
1670 return (mptsas_suspend(devi));
1671
1672 default:
1673 return (DDI_FAILURE);
1674 }
1675 /* NOTREACHED */
1676 }
1677
1678 static int
1679 mptsas_do_detach(dev_info_t *dip)
1680 {
1681 mptsas_t *mpt;
1682 scsi_hba_tran_t *tran;
1683 int circ = 0;
1684 int circ1 = 0;
1685 mdi_pathinfo_t *pip = NULL;
1686 int i;
1687 int doneq_thread_num = 0;
1688
1689 NDBG0(("mptsas_do_detach: dip=0x%p", (void *)dip));
1690
1691 if ((tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == NULL)
1692 return (DDI_FAILURE);
1693
1694 mpt = TRAN2MPT(tran);
1695 if (!mpt) {
1696 return (DDI_FAILURE);
1697 }
1698 /*
1699 * Still have pathinfo child, should not detach mpt driver
1700 */
1701 if (scsi_hba_iport_unit_address(dip)) {
1702 if (mpt->m_mpxio_enable) {
1703 /*
1704 * MPxIO enabled for the iport
1705 */
1706 ndi_devi_enter(scsi_vhci_dip, &circ1);
1707 ndi_devi_enter(dip, &circ);
1708 while (pip = mdi_get_next_client_path(dip, NULL)) {
1709 if (mdi_pi_free(pip, 0) == MDI_SUCCESS) {
1710 continue;
1711 }
1712 ndi_devi_exit(dip, circ);
1713 ndi_devi_exit(scsi_vhci_dip, circ1);
1714 NDBG12(("detach failed because of "
1715 "outstanding path info"));
1716 return (DDI_FAILURE);
1717 }
1718 ndi_devi_exit(dip, circ);
1719 ndi_devi_exit(scsi_vhci_dip, circ1);
1720 (void) mdi_phci_unregister(dip, 0);
1721 }
1722
1723 ddi_prop_remove_all(dip);
1724
1725 return (DDI_SUCCESS);
1726 }
1727
1728 /* Make sure power level is D0 before accessing registers */
1729 if (mpt->m_options & MPTSAS_OPT_PM) {
1730 (void) pm_busy_component(dip, 0);
1731 if (mpt->m_power_level != PM_LEVEL_D0) {
1732 if (pm_raise_power(dip, 0, PM_LEVEL_D0) !=
1733 DDI_SUCCESS) {
1734 mptsas_log(mpt, CE_WARN,
1735 "mptsas%d: Raise power request failed.",
1736 mpt->m_instance);
1737 (void) pm_idle_component(dip, 0);
1738 return (DDI_FAILURE);
1739 }
1740 }
1741 }
1742
1743 /*
1744 * Send RAID action system shutdown to sync IR. After action, send a
1745 * Message Unit Reset. Since after that DMA resource will be freed,
1746 * set ioc to READY state will avoid HBA initiated DMA operation.
1747 */
1748 mutex_enter(&mpt->m_mutex);
1749 MPTSAS_DISABLE_INTR(mpt);
1750 mptsas_raid_action_system_shutdown(mpt);
1751 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1752 (void) mptsas_ioc_reset(mpt, FALSE);
1753 mutex_exit(&mpt->m_mutex);
1754 mptsas_rem_intrs(mpt);
1755 ddi_taskq_destroy(mpt->m_event_taskq);
1756 ddi_taskq_destroy(mpt->m_dr_taskq);
1757
1758 if (mpt->m_doneq_thread_n) {
1759 mutex_enter(&mpt->m_doneq_mutex);
1760 doneq_thread_num = mpt->m_doneq_thread_n;
1761 for (i = 0; i < mpt->m_doneq_thread_n; i++) {
1762 mutex_enter(&mpt->m_doneq_thread_id[i].mutex);
1763 mpt->m_doneq_thread_id[i].flag &=
1764 (~MPTSAS_DONEQ_THREAD_ACTIVE);
1765 cv_signal(&mpt->m_doneq_thread_id[i].cv);
1766 mutex_exit(&mpt->m_doneq_thread_id[i].mutex);
1767 }
1768 while (mpt->m_doneq_thread_n) {
1769 cv_wait(&mpt->m_doneq_thread_cv,
1770 &mpt->m_doneq_mutex);
1771 }
1772 for (i = 0; i < doneq_thread_num; i++) {
1773 cv_destroy(&mpt->m_doneq_thread_id[i].cv);
1774 mutex_destroy(&mpt->m_doneq_thread_id[i].mutex);
1775 }
1776 kmem_free(mpt->m_doneq_thread_id,
1777 sizeof (mptsas_doneq_thread_list_t)
1778 * doneq_thread_num);
1779 mutex_exit(&mpt->m_doneq_mutex);
1780 cv_destroy(&mpt->m_doneq_thread_cv);
1781 mutex_destroy(&mpt->m_doneq_mutex);
1782 }
1783
1784 scsi_hba_reset_notify_tear_down(mpt->m_reset_notify_listf);
1785
1786 mptsas_list_del(mpt);
1787
1788 /*
1789 * Cancel timeout threads for this mpt
1790 */
1791 mutex_enter(&mpt->m_mutex);
1792 if (mpt->m_quiesce_timeid) {
1793 timeout_id_t tid = mpt->m_quiesce_timeid;
1794 mpt->m_quiesce_timeid = 0;
1795 mutex_exit(&mpt->m_mutex);
1796 (void) untimeout(tid);
1797 mutex_enter(&mpt->m_mutex);
1798 }
1799
1800 if (mpt->m_restart_cmd_timeid) {
1801 timeout_id_t tid = mpt->m_restart_cmd_timeid;
1802 mpt->m_restart_cmd_timeid = 0;
1803 mutex_exit(&mpt->m_mutex);
1804 (void) untimeout(tid);
1805 mutex_enter(&mpt->m_mutex);
1806 }
1807
1808 mutex_exit(&mpt->m_mutex);
1809
1810 /*
1811 * last mpt? ... if active, CANCEL watch threads.
1812 */
1813 mutex_enter(&mptsas_global_mutex);
1814 if (mptsas_head == NULL) {
1815 timeout_id_t tid;
1816 /*
1817 * Clear mptsas_timeouts_enable so that the watch thread
1818 * gets restarted on DDI_ATTACH
1819 */
1820 mptsas_timeouts_enabled = 0;
1821 if (mptsas_timeout_id) {
1822 tid = mptsas_timeout_id;
1823 mptsas_timeout_id = 0;
1824 mutex_exit(&mptsas_global_mutex);
1825 (void) untimeout(tid);
1826 mutex_enter(&mptsas_global_mutex);
1827 }
1828 if (mptsas_reset_watch) {
1829 tid = mptsas_reset_watch;
1830 mptsas_reset_watch = 0;
1831 mutex_exit(&mptsas_global_mutex);
1832 (void) untimeout(tid);
1833 mutex_enter(&mptsas_global_mutex);
1834 }
1835 }
1836 mutex_exit(&mptsas_global_mutex);
1837
1838 /*
1839 * Delete Phy stats
1840 */
1841 mptsas_destroy_phy_stats(mpt);
1842
1843 /*
1844 * Delete nt_active.
1845 */
1846 mutex_enter(&mpt->m_mutex);
1847 mptsas_hash_uninit(&mpt->m_active->m_tgttbl, sizeof (mptsas_target_t));
1848 mptsas_hash_uninit(&mpt->m_active->m_smptbl, sizeof (mptsas_smp_t));
1849 mptsas_free_active_slots(mpt);
1850 mutex_exit(&mpt->m_mutex);
1851
1852 /* deallocate everything that was allocated in mptsas_attach */
1853 mptsas_cache_destroy(mpt);
1854
1855 mptsas_hba_fini(mpt);
1856 mptsas_cfg_fini(mpt);
1857
1858 /* Lower the power informing PM Framework */
1859 if (mpt->m_options & MPTSAS_OPT_PM) {
1860 if (pm_lower_power(dip, 0, PM_LEVEL_D3) != DDI_SUCCESS)
1861 mptsas_log(mpt, CE_WARN,
1862 "!mptsas%d: Lower power request failed "
1863 "during detach, ignoring.",
1864 mpt->m_instance);
1865 }
1866
1867 mutex_destroy(&mpt->m_tx_waitq_mutex);
1868 mutex_destroy(&mpt->m_passthru_mutex);
1869 mutex_destroy(&mpt->m_mutex);
1870 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1871 mutex_destroy(&mpt->m_phy_info[i].smhba_info.phy_mutex);
1872 }
1873 cv_destroy(&mpt->m_cv);
1874 cv_destroy(&mpt->m_passthru_cv);
1875 cv_destroy(&mpt->m_fw_cv);
1876 cv_destroy(&mpt->m_config_cv);
1877 cv_destroy(&mpt->m_fw_diag_cv);
1878
1879
1880 mptsas_smp_teardown(mpt);
1881 mptsas_hba_teardown(mpt);
1882
1883 mptsas_config_space_fini(mpt);
1884
1885 mptsas_free_handshake_msg(mpt);
1886
1887 mptsas_fm_fini(mpt);
1888 ddi_soft_state_free(mptsas_state, ddi_get_instance(dip));
1889 ddi_prop_remove_all(dip);
1890
1891 return (DDI_SUCCESS);
1892 }
1893
1894 static void
1895 mptsas_list_add(mptsas_t *mpt)
1896 {
1897 rw_enter(&mptsas_global_rwlock, RW_WRITER);
1898
1899 if (mptsas_head == NULL) {
1900 mptsas_head = mpt;
1901 } else {
1902 mptsas_tail->m_next = mpt;
1903 }
1904 mptsas_tail = mpt;
1905 rw_exit(&mptsas_global_rwlock);
1906 }
1907
1908 static void
1909 mptsas_list_del(mptsas_t *mpt)
1910 {
1911 mptsas_t *m;
1912 /*
1913 * Remove device instance from the global linked list
1914 */
1915 rw_enter(&mptsas_global_rwlock, RW_WRITER);
1916 if (mptsas_head == mpt) {
1917 m = mptsas_head = mpt->m_next;
1918 } else {
1919 for (m = mptsas_head; m != NULL; m = m->m_next) {
1920 if (m->m_next == mpt) {
1921 m->m_next = mpt->m_next;
1922 break;
1923 }
1924 }
1925 if (m == NULL) {
1926 mptsas_log(mpt, CE_PANIC, "Not in softc list!");
1927 }
1928 }
1929
1930 if (mptsas_tail == mpt) {
1931 mptsas_tail = m;
1932 }
1933 rw_exit(&mptsas_global_rwlock);
1934 }
1935
1936 static int
1937 mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size)
1938 {
1939 ddi_dma_attr_t task_dma_attrs;
1940
1941 task_dma_attrs = mpt->m_msg_dma_attr;
1942 task_dma_attrs.dma_attr_sgllen = 1;
1943 task_dma_attrs.dma_attr_granular = (uint32_t)(alloc_size);
1944
1945 /* allocate Task Management ddi_dma resources */
1946 if (mptsas_dma_addr_create(mpt, task_dma_attrs,
1947 &mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl, &mpt->m_hshk_memp,
1948 alloc_size, NULL) == FALSE) {
1949 return (DDI_FAILURE);
1950 }
1951 mpt->m_hshk_dma_size = alloc_size;
1952
1953 return (DDI_SUCCESS);
1954 }
1955
1956 static void
1957 mptsas_free_handshake_msg(mptsas_t *mpt)
1958 {
1959 mptsas_dma_addr_destroy(&mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl);
1960 mpt->m_hshk_dma_size = 0;
1961 }
1962
1963 static int
1964 mptsas_hba_setup(mptsas_t *mpt)
1965 {
1966 scsi_hba_tran_t *hba_tran;
1967 int tran_flags;
1968
1969 /* Allocate a transport structure */
1970 hba_tran = mpt->m_tran = scsi_hba_tran_alloc(mpt->m_dip,
1971 SCSI_HBA_CANSLEEP);
1972 ASSERT(mpt->m_tran != NULL);
1973
1974 hba_tran->tran_hba_private = mpt;
1975 hba_tran->tran_tgt_private = NULL;
1976
1977 hba_tran->tran_tgt_init = mptsas_scsi_tgt_init;
1978 hba_tran->tran_tgt_free = mptsas_scsi_tgt_free;
1979
1980 hba_tran->tran_start = mptsas_scsi_start;
1981 hba_tran->tran_reset = mptsas_scsi_reset;
1982 hba_tran->tran_abort = mptsas_scsi_abort;
1983 hba_tran->tran_getcap = mptsas_scsi_getcap;
1984 hba_tran->tran_setcap = mptsas_scsi_setcap;
1985 hba_tran->tran_init_pkt = mptsas_scsi_init_pkt;
1986 hba_tran->tran_destroy_pkt = mptsas_scsi_destroy_pkt;
1987
1988 hba_tran->tran_dmafree = mptsas_scsi_dmafree;
1989 hba_tran->tran_sync_pkt = mptsas_scsi_sync_pkt;
1990 hba_tran->tran_reset_notify = mptsas_scsi_reset_notify;
1991
1992 hba_tran->tran_get_bus_addr = mptsas_get_bus_addr;
1993 hba_tran->tran_get_name = mptsas_get_name;
1994
1995 hba_tran->tran_quiesce = mptsas_scsi_quiesce;
1996 hba_tran->tran_unquiesce = mptsas_scsi_unquiesce;
1997 hba_tran->tran_bus_reset = NULL;
1998
1999 hba_tran->tran_add_eventcall = NULL;
2000 hba_tran->tran_get_eventcookie = NULL;
2001 hba_tran->tran_post_event = NULL;
2002 hba_tran->tran_remove_eventcall = NULL;
2003
2004 hba_tran->tran_bus_config = mptsas_bus_config;
2005
2006 hba_tran->tran_interconnect_type = INTERCONNECT_SAS;
2007
2008 /*
2009 * All children of the HBA are iports. We need tran was cloned.
2010 * So we pass the flags to SCSA. SCSI_HBA_TRAN_CLONE will be
2011 * inherited to iport's tran vector.
2012 */
2013 tran_flags = (SCSI_HBA_HBA | SCSI_HBA_TRAN_CLONE);
2014
2015 if (scsi_hba_attach_setup(mpt->m_dip, &mpt->m_msg_dma_attr,
2016 hba_tran, tran_flags) != DDI_SUCCESS) {
2017 mptsas_log(mpt, CE_WARN, "hba attach setup failed");
2018 scsi_hba_tran_free(hba_tran);
2019 mpt->m_tran = NULL;
2020 return (FALSE);
2021 }
2022 return (TRUE);
2023 }
2024
2025 static void
2026 mptsas_hba_teardown(mptsas_t *mpt)
2027 {
2028 (void) scsi_hba_detach(mpt->m_dip);
2029 if (mpt->m_tran != NULL) {
2030 scsi_hba_tran_free(mpt->m_tran);
2031 mpt->m_tran = NULL;
2032 }
2033 }
2034
2035 static void
2036 mptsas_iport_register(mptsas_t *mpt)
2037 {
2038 int i, j;
2039 mptsas_phymask_t mask = 0x0;
2040 /*
2041 * initial value of mask is 0
2042 */
2043 mutex_enter(&mpt->m_mutex);
2044 for (i = 0; i < mpt->m_num_phys; i++) {
2045 mptsas_phymask_t phy_mask = 0x0;
2046 char phy_mask_name[MPTSAS_MAX_PHYS];
2047 uint8_t current_port;
2048
2049 if (mpt->m_phy_info[i].attached_devhdl == 0)
2050 continue;
2051
2052 bzero(phy_mask_name, sizeof (phy_mask_name));
2053
2054 current_port = mpt->m_phy_info[i].port_num;
2055
2056 if ((mask & (1 << i)) != 0)
2057 continue;
2058
2059 for (j = 0; j < mpt->m_num_phys; j++) {
2060 if (mpt->m_phy_info[j].attached_devhdl &&
2061 (mpt->m_phy_info[j].port_num == current_port)) {
2062 phy_mask |= (1 << j);
2063 }
2064 }
2065 mask = mask | phy_mask;
2066
2067 for (j = 0; j < mpt->m_num_phys; j++) {
2068 if ((phy_mask >> j) & 0x01) {
2069 mpt->m_phy_info[j].phy_mask = phy_mask;
2070 }
2071 }
2072
2073 (void) sprintf(phy_mask_name, "%x", phy_mask);
2074
2075 mutex_exit(&mpt->m_mutex);
2076 /*
2077 * register a iport
2078 */
2079 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name);
2080 mutex_enter(&mpt->m_mutex);
2081 }
2082 mutex_exit(&mpt->m_mutex);
2083 /*
2084 * register a virtual port for RAID volume always
2085 */
2086 (void) scsi_hba_iport_register(mpt->m_dip, "v0");
2087
2088 }
2089
2090 static int
2091 mptsas_smp_setup(mptsas_t *mpt)
2092 {
2093 mpt->m_smptran = smp_hba_tran_alloc(mpt->m_dip);
2094 ASSERT(mpt->m_smptran != NULL);
2095 mpt->m_smptran->smp_tran_hba_private = mpt;
2096 mpt->m_smptran->smp_tran_start = mptsas_smp_start;
2097 if (smp_hba_attach_setup(mpt->m_dip, mpt->m_smptran) != DDI_SUCCESS) {
2098 mptsas_log(mpt, CE_WARN, "smp attach setup failed");
2099 smp_hba_tran_free(mpt->m_smptran);
2100 mpt->m_smptran = NULL;
2101 return (FALSE);
2102 }
2103 /*
2104 * Initialize smp hash table
2105 */
2106 mptsas_hash_init(&mpt->m_active->m_smptbl);
2107 mpt->m_smp_devhdl = 0xFFFF;
2108
2109 return (TRUE);
2110 }
2111
2112 static void
2113 mptsas_smp_teardown(mptsas_t *mpt)
2114 {
2115 (void) smp_hba_detach(mpt->m_dip);
2116 if (mpt->m_smptran != NULL) {
2117 smp_hba_tran_free(mpt->m_smptran);
2118 mpt->m_smptran = NULL;
2119 }
2120 mpt->m_smp_devhdl = 0;
2121 }
2122
2123 static int
2124 mptsas_cache_create(mptsas_t *mpt)
2125 {
2126 int instance = mpt->m_instance;
2127 char buf[64];
2128
2129 /*
2130 * create kmem cache for packets
2131 */
2132 (void) sprintf(buf, "mptsas%d_cache", instance);
2133 mpt->m_kmem_cache = kmem_cache_create(buf,
2134 sizeof (struct mptsas_cmd) + scsi_pkt_size(), 8,
2135 mptsas_kmem_cache_constructor, mptsas_kmem_cache_destructor,
2136 NULL, (void *)mpt, NULL, 0);
2137
2138 if (mpt->m_kmem_cache == NULL) {
2139 mptsas_log(mpt, CE_WARN, "creating kmem cache failed");
2140 return (FALSE);
2141 }
2142
2143 /*
2144 * create kmem cache for extra SGL frames if SGL cannot
2145 * be accomodated into main request frame.
2146 */
2147 (void) sprintf(buf, "mptsas%d_cache_frames", instance);
2148 mpt->m_cache_frames = kmem_cache_create(buf,
2149 sizeof (mptsas_cache_frames_t), 8,
2150 mptsas_cache_frames_constructor, mptsas_cache_frames_destructor,
2151 NULL, (void *)mpt, NULL, 0);
2152
2153 if (mpt->m_cache_frames == NULL) {
2154 mptsas_log(mpt, CE_WARN, "creating cache for frames failed");
2155 return (FALSE);
2156 }
2157
2158 return (TRUE);
2159 }
2160
2161 static void
2162 mptsas_cache_destroy(mptsas_t *mpt)
2163 {
2164 /* deallocate in reverse order */
2165 if (mpt->m_cache_frames) {
2166 kmem_cache_destroy(mpt->m_cache_frames);
2167 mpt->m_cache_frames = NULL;
2168 }
2169 if (mpt->m_kmem_cache) {
2170 kmem_cache_destroy(mpt->m_kmem_cache);
2171 mpt->m_kmem_cache = NULL;
2172 }
2173 }
2174
2175 static int
2176 mptsas_power(dev_info_t *dip, int component, int level)
2177 {
2178 #ifndef __lock_lint
2179 _NOTE(ARGUNUSED(component))
2180 #endif
2181 mptsas_t *mpt;
2182 int rval = DDI_SUCCESS;
2183 int polls = 0;
2184 uint32_t ioc_status;
2185
2186 if (scsi_hba_iport_unit_address(dip) != 0)
2187 return (DDI_SUCCESS);
2188
2189 mpt = ddi_get_soft_state(mptsas_state, ddi_get_instance(dip));
2190 if (mpt == NULL) {
2191 return (DDI_FAILURE);
2192 }
2193
2194 mutex_enter(&mpt->m_mutex);
2195
2196 /*
2197 * If the device is busy, don't lower its power level
2198 */
2199 if (mpt->m_busy && (mpt->m_power_level > level)) {
2200 mutex_exit(&mpt->m_mutex);
2201 return (DDI_FAILURE);
2202 }
2203 switch (level) {
2204 case PM_LEVEL_D0:
2205 NDBG11(("mptsas%d: turning power ON.", mpt->m_instance));
2206 MPTSAS_POWER_ON(mpt);
2207 /*
2208 * Wait up to 30 seconds for IOC to come out of reset.
2209 */
2210 while (((ioc_status = ddi_get32(mpt->m_datap,
2211 &mpt->m_reg->Doorbell)) &
2212 MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
2213 if (polls++ > 3000) {
2214 break;
2215 }
2216 delay(drv_usectohz(10000));
2217 }
2218 /*
2219 * If IOC is not in operational state, try to hard reset it.
2220 */
2221 if ((ioc_status & MPI2_IOC_STATE_MASK) !=
2222 MPI2_IOC_STATE_OPERATIONAL) {
2223 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
2224 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) {
2225 mptsas_log(mpt, CE_WARN,
2226 "mptsas_power: hard reset failed");
2227 mutex_exit(&mpt->m_mutex);
2228 return (DDI_FAILURE);
2229 }
2230 }
2231 mpt->m_power_level = PM_LEVEL_D0;
2232 break;
2233 case PM_LEVEL_D3:
2234 NDBG11(("mptsas%d: turning power OFF.", mpt->m_instance));
2235 MPTSAS_POWER_OFF(mpt);
2236 break;
2237 default:
2238 mptsas_log(mpt, CE_WARN, "mptsas%d: unknown power level <%x>.",
2239 mpt->m_instance, level);
2240 rval = DDI_FAILURE;
2241 break;
2242 }
2243 mutex_exit(&mpt->m_mutex);
2244 return (rval);
2245 }
2246
2247 /*
2248 * Initialize configuration space and figure out which
2249 * chip and revison of the chip the mpt driver is using.
2250 */
2251 static int
2252 mptsas_config_space_init(mptsas_t *mpt)
2253 {
2254 NDBG0(("mptsas_config_space_init"));
2255
2256 if (mpt->m_config_handle != NULL)
2257 return (TRUE);
2258
2259 if (pci_config_setup(mpt->m_dip,
2260 &mpt->m_config_handle) != DDI_SUCCESS) {
2261 mptsas_log(mpt, CE_WARN, "cannot map configuration space.");
2262 return (FALSE);
2263 }
2264
2265 /*
2266 * This is a workaround for a XMITS ASIC bug which does not
2267 * drive the CBE upper bits.
2268 */
2269 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) &
2270 PCI_STAT_PERROR) {
2271 pci_config_put16(mpt->m_config_handle, PCI_CONF_STAT,
2272 PCI_STAT_PERROR);
2273 }
2274
2275 mptsas_setup_cmd_reg(mpt);
2276
2277 /*
2278 * Get the chip device id:
2279 */
2280 mpt->m_devid = pci_config_get16(mpt->m_config_handle, PCI_CONF_DEVID);
2281
2282 /*
2283 * Save the revision.
2284 */
2285 mpt->m_revid = pci_config_get8(mpt->m_config_handle, PCI_CONF_REVID);
2286
2287 /*
2288 * Save the SubSystem Vendor and Device IDs
2289 */
2290 mpt->m_svid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBVENID);
2291 mpt->m_ssid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBSYSID);
2292
2293 /*
2294 * Set the latency timer to 0x40 as specified by the upa -> pci
2295 * bridge chip design team. This may be done by the sparc pci
2296 * bus nexus driver, but the driver should make sure the latency
2297 * timer is correct for performance reasons.
2298 */
2299 pci_config_put8(mpt->m_config_handle, PCI_CONF_LATENCY_TIMER,
2300 MPTSAS_LATENCY_TIMER);
2301
2302 (void) mptsas_get_pci_cap(mpt);
2303 return (TRUE);
2304 }
2305
2306 static void
2307 mptsas_config_space_fini(mptsas_t *mpt)
2308 {
2309 if (mpt->m_config_handle != NULL) {
2310 mptsas_disable_bus_master(mpt);
2311 pci_config_teardown(&mpt->m_config_handle);
2312 mpt->m_config_handle = NULL;
2313 }
2314 }
2315
2316 static void
2317 mptsas_setup_cmd_reg(mptsas_t *mpt)
2318 {
2319 ushort_t cmdreg;
2320
2321 /*
2322 * Set the command register to the needed values.
2323 */
2324 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM);
2325 cmdreg |= (PCI_COMM_ME | PCI_COMM_SERR_ENABLE |
2326 PCI_COMM_PARITY_DETECT | PCI_COMM_MAE);
2327 cmdreg &= ~PCI_COMM_IO;
2328 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg);
2329 }
2330
2331 static void
2332 mptsas_disable_bus_master(mptsas_t *mpt)
2333 {
2334 ushort_t cmdreg;
2335
2336 /*
2337 * Clear the master enable bit in the PCI command register.
2338 * This prevents any bus mastering activity like DMA.
2339 */
2340 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM);
2341 cmdreg &= ~PCI_COMM_ME;
2342 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg);
2343 }
2344
2345 int
2346 mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep)
2347 {
2348 ddi_dma_attr_t attrs;
2349
2350 attrs = mpt->m_io_dma_attr;
2351 attrs.dma_attr_sgllen = 1;
2352
2353 ASSERT(dma_statep != NULL);
2354
2355 if (mptsas_dma_addr_create(mpt, attrs, &dma_statep->handle,
2356 &dma_statep->accessp, &dma_statep->memp, dma_statep->size,
2357 &dma_statep->cookie) == FALSE) {
2358 return (DDI_FAILURE);
2359 }
2360
2361 return (DDI_SUCCESS);
2362 }
2363
2364 void
2365 mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep)
2366 {
2367 ASSERT(dma_statep != NULL);
2368 mptsas_dma_addr_destroy(&dma_statep->handle, &dma_statep->accessp);
2369 dma_statep->size = 0;
2370 }
2371
2372 int
2373 mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)())
2374 {
2375 ddi_dma_attr_t attrs;
2376 ddi_dma_handle_t dma_handle;
2377 caddr_t memp;
2378 ddi_acc_handle_t accessp;
2379 int rval;
2380
2381 ASSERT(mutex_owned(&mpt->m_mutex));
2382
2383 attrs = mpt->m_msg_dma_attr;
2384 attrs.dma_attr_sgllen = 1;
2385 attrs.dma_attr_granular = size;
2386
2387 if (mptsas_dma_addr_create(mpt, attrs, &dma_handle,
2388 &accessp, &memp, size, NULL) == FALSE) {
2389 return (DDI_FAILURE);
2390 }
2391
2392 rval = (*callback) (mpt, memp, var, accessp);
2393
2394 if ((mptsas_check_dma_handle(dma_handle) != DDI_SUCCESS) ||
2395 (mptsas_check_acc_handle(accessp) != DDI_SUCCESS)) {
2396 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
2397 rval = DDI_FAILURE;
2398 }
2399
2400 mptsas_dma_addr_destroy(&dma_handle, &accessp);
2401 return (rval);
2402
2403 }
2404
2405 static int
2406 mptsas_alloc_request_frames(mptsas_t *mpt)
2407 {
2408 ddi_dma_attr_t frame_dma_attrs;
2409 caddr_t memp;
2410 ddi_dma_cookie_t cookie;
2411 size_t mem_size;
2412
2413 /*
2414 * re-alloc when it has already alloced
2415 */
2416 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl,
2417 &mpt->m_acc_req_frame_hdl);
2418
2419 /*
2420 * The size of the request frame pool is:
2421 * Number of Request Frames * Request Frame Size
2422 */
2423 mem_size = mpt->m_max_requests * mpt->m_req_frame_size;
2424
2425 /*
2426 * set the DMA attributes. System Request Message Frames must be
2427 * aligned on a 16-byte boundry.
2428 */
2429 frame_dma_attrs = mpt->m_msg_dma_attr;
2430 frame_dma_attrs.dma_attr_align = 16;
2431 frame_dma_attrs.dma_attr_sgllen = 1;
2432
2433 /*
2434 * allocate the request frame pool.
2435 */
2436 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2437 &mpt->m_dma_req_frame_hdl, &mpt->m_acc_req_frame_hdl, &memp,
2438 mem_size, &cookie) == FALSE) {
2439 return (DDI_FAILURE);
2440 }
2441
2442 /*
2443 * Store the request frame memory address. This chip uses this
2444 * address to dma to and from the driver's frame. The second
2445 * address is the address mpt uses to fill in the frame.
2446 */
2447 mpt->m_req_frame_dma_addr = cookie.dmac_laddress;
2448 mpt->m_req_frame = memp;
2449
2450 /*
2451 * Clear the request frame pool.
2452 */
2453 bzero(mpt->m_req_frame, mem_size);
2454
2455 return (DDI_SUCCESS);
2456 }
2457
2458 static int
2459 mptsas_alloc_reply_frames(mptsas_t *mpt)
2460 {
2461 ddi_dma_attr_t frame_dma_attrs;
2462 caddr_t memp;
2463 ddi_dma_cookie_t cookie;
2464 size_t mem_size;
2465
2466 /*
2467 * re-alloc when it has already alloced
2468 */
2469 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl,
2470 &mpt->m_acc_reply_frame_hdl);
2471
2472 /*
2473 * The size of the reply frame pool is:
2474 * Number of Reply Frames * Reply Frame Size
2475 */
2476 mem_size = mpt->m_max_replies * mpt->m_reply_frame_size;
2477
2478 /*
2479 * set the DMA attributes. System Reply Message Frames must be
2480 * aligned on a 4-byte boundry. This is the default.
2481 */
2482 frame_dma_attrs = mpt->m_msg_dma_attr;
2483 frame_dma_attrs.dma_attr_sgllen = 1;
2484
2485 /*
2486 * allocate the reply frame pool
2487 */
2488 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2489 &mpt->m_dma_reply_frame_hdl, &mpt->m_acc_reply_frame_hdl, &memp,
2490 mem_size, &cookie) == FALSE) {
2491 return (DDI_FAILURE);
2492 }
2493
2494 /*
2495 * Store the reply frame memory address. This chip uses this
2496 * address to dma to and from the driver's frame. The second
2497 * address is the address mpt uses to process the frame.
2498 */
2499 mpt->m_reply_frame_dma_addr = cookie.dmac_laddress;
2500 mpt->m_reply_frame = memp;
2501
2502 /*
2503 * Clear the reply frame pool.
2504 */
2505 bzero(mpt->m_reply_frame, mem_size);
2506
2507 return (DDI_SUCCESS);
2508 }
2509
2510 static int
2511 mptsas_alloc_free_queue(mptsas_t *mpt)
2512 {
2513 ddi_dma_attr_t frame_dma_attrs;
2514 caddr_t memp;
2515 ddi_dma_cookie_t cookie;
2516 size_t mem_size;
2517
2518 /*
2519 * re-alloc when it has already alloced
2520 */
2521 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl,
2522 &mpt->m_acc_free_queue_hdl);
2523
2524 /*
2525 * The reply free queue size is:
2526 * Reply Free Queue Depth * 4
2527 * The "4" is the size of one 32 bit address (low part of 64-bit
2528 * address)
2529 */
2530 mem_size = mpt->m_free_queue_depth * 4;
2531
2532 /*
2533 * set the DMA attributes The Reply Free Queue must be aligned on a
2534 * 16-byte boundry.
2535 */
2536 frame_dma_attrs = mpt->m_msg_dma_attr;
2537 frame_dma_attrs.dma_attr_align = 16;
2538 frame_dma_attrs.dma_attr_sgllen = 1;
2539
2540 /*
2541 * allocate the reply free queue
2542 */
2543 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2544 &mpt->m_dma_free_queue_hdl, &mpt->m_acc_free_queue_hdl, &memp,
2545 mem_size, &cookie) == FALSE) {
2546 return (DDI_FAILURE);
2547 }
2548
2549 /*
2550 * Store the reply free queue memory address. This chip uses this
2551 * address to read from the reply free queue. The second address
2552 * is the address mpt uses to manage the queue.
2553 */
2554 mpt->m_free_queue_dma_addr = cookie.dmac_laddress;
2555 mpt->m_free_queue = memp;
2556
2557 /*
2558 * Clear the reply free queue memory.
2559 */
2560 bzero(mpt->m_free_queue, mem_size);
2561
2562 return (DDI_SUCCESS);
2563 }
2564
2565 static int
2566 mptsas_alloc_post_queue(mptsas_t *mpt)
2567 {
2568 ddi_dma_attr_t frame_dma_attrs;
2569 caddr_t memp;
2570 ddi_dma_cookie_t cookie;
2571 size_t mem_size;
2572
2573 /*
2574 * re-alloc when it has already alloced
2575 */
2576 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl,
2577 &mpt->m_acc_post_queue_hdl);
2578
2579 /*
2580 * The reply descriptor post queue size is:
2581 * Reply Descriptor Post Queue Depth * 8
2582 * The "8" is the size of each descriptor (8 bytes or 64 bits).
2583 */
2584 mem_size = mpt->m_post_queue_depth * 8;
2585
2586 /*
2587 * set the DMA attributes. The Reply Descriptor Post Queue must be
2588 * aligned on a 16-byte boundry.
2589 */
2590 frame_dma_attrs = mpt->m_msg_dma_attr;
2591 frame_dma_attrs.dma_attr_align = 16;
2592 frame_dma_attrs.dma_attr_sgllen = 1;
2593
2594 /*
2595 * allocate the reply post queue
2596 */
2597 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2598 &mpt->m_dma_post_queue_hdl, &mpt->m_acc_post_queue_hdl, &memp,
2599 mem_size, &cookie) == FALSE) {
2600 return (DDI_FAILURE);
2601 }
2602
2603 /*
2604 * Store the reply descriptor post queue memory address. This chip
2605 * uses this address to write to the reply descriptor post queue. The
2606 * second address is the address mpt uses to manage the queue.
2607 */
2608 mpt->m_post_queue_dma_addr = cookie.dmac_laddress;
2609 mpt->m_post_queue = memp;
2610
2611 /*
2612 * Clear the reply post queue memory.
2613 */
2614 bzero(mpt->m_post_queue, mem_size);
2615
2616 return (DDI_SUCCESS);
2617 }
2618
2619 static void
2620 mptsas_alloc_reply_args(mptsas_t *mpt)
2621 {
2622 if (mpt->m_replyh_args == NULL) {
2623 mpt->m_replyh_args = kmem_zalloc(sizeof (m_replyh_arg_t) *
2624 mpt->m_max_replies, KM_SLEEP);
2625 }
2626 }
2627
2628 static int
2629 mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd)
2630 {
2631 mptsas_cache_frames_t *frames = NULL;
2632 if (cmd->cmd_extra_frames == NULL) {
2633 frames = kmem_cache_alloc(mpt->m_cache_frames, KM_NOSLEEP);
2634 if (frames == NULL) {
2635 return (DDI_FAILURE);
2636 }
2637 cmd->cmd_extra_frames = frames;
2638 }
2639 return (DDI_SUCCESS);
2640 }
2641
2642 static void
2643 mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd)
2644 {
2645 if (cmd->cmd_extra_frames) {
2646 kmem_cache_free(mpt->m_cache_frames,
2647 (void *)cmd->cmd_extra_frames);
2648 cmd->cmd_extra_frames = NULL;
2649 }
2650 }
2651
2652 static void
2653 mptsas_cfg_fini(mptsas_t *mpt)
2654 {
2655 NDBG0(("mptsas_cfg_fini"));
2656 ddi_regs_map_free(&mpt->m_datap);
2657 }
2658
2659 static void
2660 mptsas_hba_fini(mptsas_t *mpt)
2661 {
2662 NDBG0(("mptsas_hba_fini"));
2663
2664 /*
2665 * Free up any allocated memory
2666 */
2667 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl,
2668 &mpt->m_acc_req_frame_hdl);
2669
2670 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl,
2671 &mpt->m_acc_reply_frame_hdl);
2672
2673 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl,
2674 &mpt->m_acc_free_queue_hdl);
2675
2676 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl,
2677 &mpt->m_acc_post_queue_hdl);
2678
2679 if (mpt->m_replyh_args != NULL) {
2680 kmem_free(mpt->m_replyh_args, sizeof (m_replyh_arg_t)
2681 * mpt->m_max_replies);
2682 }
2683 }
2684
2685 static int
2686 mptsas_name_child(dev_info_t *lun_dip, char *name, int len)
2687 {
2688 int lun = 0;
2689 char *sas_wwn = NULL;
2690 int phynum = -1;
2691 int reallen = 0;
2692
2693 /* Get the target num */
2694 lun = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, DDI_PROP_DONTPASS,
2695 LUN_PROP, 0);
2696
2697 if ((phynum = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip,
2698 DDI_PROP_DONTPASS, "sata-phy", -1)) != -1) {
2699 /*
2700 * Stick in the address of form "pPHY,LUN"
2701 */
2702 reallen = snprintf(name, len, "p%x,%x", phynum, lun);
2703 } else if (ddi_prop_lookup_string(DDI_DEV_T_ANY, lun_dip,
2704 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &sas_wwn)
2705 == DDI_PROP_SUCCESS) {
2706 /*
2707 * Stick in the address of the form "wWWN,LUN"
2708 */
2709 reallen = snprintf(name, len, "%s,%x", sas_wwn, lun);
2710 ddi_prop_free(sas_wwn);
2711 } else {
2712 return (DDI_FAILURE);
2713 }
2714
2715 ASSERT(reallen < len);
2716 if (reallen >= len) {
2717 mptsas_log(0, CE_WARN, "!mptsas_get_name: name parameter "
2718 "length too small, it needs to be %d bytes", reallen + 1);
2719 }
2720 return (DDI_SUCCESS);
2721 }
2722
2723 /*
2724 * tran_tgt_init(9E) - target device instance initialization
2725 */
2726 static int
2727 mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
2728 scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
2729 {
2730 #ifndef __lock_lint
2731 _NOTE(ARGUNUSED(hba_tran))
2732 #endif
2733
2734 /*
2735 * At this point, the scsi_device structure already exists
2736 * and has been initialized.
2737 *
2738 * Use this function to allocate target-private data structures,
2739 * if needed by this HBA. Add revised flow-control and queue
2740 * properties for child here, if desired and if you can tell they
2741 * support tagged queueing by now.
2742 */
2743 mptsas_t *mpt;
2744 int lun = sd->sd_address.a_lun;
2745 mdi_pathinfo_t *pip = NULL;
2746 mptsas_tgt_private_t *tgt_private = NULL;
2747 mptsas_target_t *ptgt = NULL;
2748 char *psas_wwn = NULL;
2749 int phymask = 0;
2750 uint64_t sas_wwn = 0;
2751 mpt = SDEV2MPT(sd);
2752
2753 ASSERT(scsi_hba_iport_unit_address(hba_dip) != 0);
2754
2755 NDBG0(("mptsas_scsi_tgt_init: hbadip=0x%p tgtdip=0x%p lun=%d",
2756 (void *)hba_dip, (void *)tgt_dip, lun));
2757
2758 if (ndi_dev_is_persistent_node(tgt_dip) == 0) {
2759 (void) ndi_merge_node(tgt_dip, mptsas_name_child);
2760 ddi_set_name_addr(tgt_dip, NULL);
2761 return (DDI_FAILURE);
2762 }
2763 /*
2764 * phymask is 0 means the virtual port for RAID
2765 */
2766 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, hba_dip, 0,
2767 "phymask", 0);
2768 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) {
2769 if ((pip = (void *)(sd->sd_private)) == NULL) {
2770 /*
2771 * Very bad news if this occurs. Somehow scsi_vhci has
2772 * lost the pathinfo node for this target.
2773 */
2774 return (DDI_NOT_WELL_FORMED);
2775 }
2776
2777 if (mdi_prop_lookup_int(pip, LUN_PROP, &lun) !=
2778 DDI_PROP_SUCCESS) {
2779 mptsas_log(mpt, CE_WARN, "Get lun property failed\n");
2780 return (DDI_FAILURE);
2781 }
2782
2783 if (mdi_prop_lookup_string(pip, SCSI_ADDR_PROP_TARGET_PORT,
2784 &psas_wwn) == MDI_SUCCESS) {
2785 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) {
2786 sas_wwn = 0;
2787 }
2788 (void) mdi_prop_free(psas_wwn);
2789 }
2790 } else {
2791 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tgt_dip,
2792 DDI_PROP_DONTPASS, LUN_PROP, 0);
2793 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, tgt_dip,
2794 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &psas_wwn) ==
2795 DDI_PROP_SUCCESS) {
2796 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) {
2797 sas_wwn = 0;
2798 }
2799 ddi_prop_free(psas_wwn);
2800 } else {
2801 sas_wwn = 0;
2802 }
2803 }
2804 ASSERT((sas_wwn != 0) || (phymask != 0));
2805 mutex_enter(&mpt->m_mutex);
2806 ptgt = mptsas_hash_search(&mpt->m_active->m_tgttbl, sas_wwn, phymask);
2807 mutex_exit(&mpt->m_mutex);
2808 if (ptgt == NULL) {
2809 mptsas_log(mpt, CE_WARN, "!tgt_init: target doesn't exist or "
2810 "gone already! phymask:%x, saswwn %"PRIx64, phymask,
2811 sas_wwn);
2812 return (DDI_FAILURE);
2813 }
2814 if (hba_tran->tran_tgt_private == NULL) {
2815 tgt_private = kmem_zalloc(sizeof (mptsas_tgt_private_t),
2816 KM_SLEEP);
2817 tgt_private->t_lun = lun;
2818 tgt_private->t_private = ptgt;
2819 hba_tran->tran_tgt_private = tgt_private;
2820 }
2821
2822 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) {
2823 return (DDI_SUCCESS);
2824 }
2825 mutex_enter(&mpt->m_mutex);
2826
2827 if (ptgt->m_deviceinfo &
2828 (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
2829 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
2830 uchar_t *inq89 = NULL;
2831 int inq89_len = 0x238;
2832 int reallen = 0;
2833 int rval = 0;
2834 struct sata_id *sid = NULL;
2835 char model[SATA_ID_MODEL_LEN + 1];
2836 char fw[SATA_ID_FW_LEN + 1];
2837 char *vid, *pid;
2838 int i;
2839
2840 mutex_exit(&mpt->m_mutex);
2841 /*
2842 * According SCSI/ATA Translation -2 (SAT-2) revision 01a
2843 * chapter 12.4.2 VPD page 89h includes 512 bytes ATA IDENTIFY
2844 * DEVICE data or ATA IDENTIFY PACKET DEVICE data.
2845 */
2846 inq89 = kmem_zalloc(inq89_len, KM_SLEEP);
2847 rval = mptsas_inquiry(mpt, ptgt, 0, 0x89,
2848 inq89, inq89_len, &reallen, 1);
2849
2850 if (rval != 0) {
2851 if (inq89 != NULL) {
2852 kmem_free(inq89, inq89_len);
2853 }
2854
2855 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
2856 "0x89 for SATA target:%x failed!", ptgt->m_devhdl);
2857 return (DDI_SUCCESS);
2858 }
2859 sid = (void *)(&inq89[60]);
2860
2861 swab(sid->ai_model, model, SATA_ID_MODEL_LEN);
2862 swab(sid->ai_fw, fw, SATA_ID_FW_LEN);
2863
2864 model[SATA_ID_MODEL_LEN] = 0;
2865 fw[SATA_ID_FW_LEN] = 0;
2866
2867 /*
2868 * split model into into vid/pid
2869 */
2870 for (i = 0, pid = model; i < SATA_ID_MODEL_LEN; i++, pid++)
2871 if ((*pid == ' ') || (*pid == '\t'))
2872 break;
2873 if (i < SATA_ID_MODEL_LEN) {
2874 vid = model;
2875 /*
2876 * terminate vid, establish pid
2877 */
2878 *pid++ = 0;
2879 } else {
2880 /*
2881 * vid will stay "ATA ", the rule is same
2882 * as sata framework implementation.
2883 */
2884 vid = NULL;
2885 /*
2886 * model is all pid
2887 */
2888 pid = model;
2889 }
2890
2891 /*
2892 * override SCSA "inquiry-*" properties
2893 */
2894 if (vid)
2895 (void) scsi_device_prop_update_inqstring(sd,
2896 INQUIRY_VENDOR_ID, vid, strlen(vid));
2897 if (pid)
2898 (void) scsi_device_prop_update_inqstring(sd,
2899 INQUIRY_PRODUCT_ID, pid, strlen(pid));
2900 (void) scsi_device_prop_update_inqstring(sd,
2901 INQUIRY_REVISION_ID, fw, strlen(fw));
2902
2903 if (inq89 != NULL) {
2904 kmem_free(inq89, inq89_len);
2905 }
2906 } else {
2907 mutex_exit(&mpt->m_mutex);
2908 }
2909
2910 return (DDI_SUCCESS);
2911 }
2912 /*
2913 * tran_tgt_free(9E) - target device instance deallocation
2914 */
2915 static void
2916 mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
2917 scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
2918 {
2919 #ifndef __lock_lint
2920 _NOTE(ARGUNUSED(hba_dip, tgt_dip, hba_tran, sd))
2921 #endif
2922
2923 mptsas_tgt_private_t *tgt_private = hba_tran->tran_tgt_private;
2924
2925 if (tgt_private != NULL) {
2926 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t));
2927 hba_tran->tran_tgt_private = NULL;
2928 }
2929 }
2930
2931 /*
2932 * scsi_pkt handling
2933 *
2934 * Visible to the external world via the transport structure.
2935 */
2936
2937 /*
2938 * Notes:
2939 * - transport the command to the addressed SCSI target/lun device
2940 * - normal operation is to schedule the command to be transported,
2941 * and return TRAN_ACCEPT if this is successful.
2942 * - if NO_INTR, tran_start must poll device for command completion
2943 */
2944 static int
2945 mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt)
2946 {
2947 #ifndef __lock_lint
2948 _NOTE(ARGUNUSED(ap))
2949 #endif
2950 mptsas_t *mpt = PKT2MPT(pkt);
2951 mptsas_cmd_t *cmd = PKT2CMD(pkt);
2952 int rval;
2953 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
2954
2955 NDBG1(("mptsas_scsi_start: pkt=0x%p", (void *)pkt));
2956 ASSERT(ptgt);
2957 if (ptgt == NULL)
2958 return (TRAN_FATAL_ERROR);
2959
2960 /*
2961 * prepare the pkt before taking mutex.
2962 */
2963 rval = mptsas_prepare_pkt(cmd);
2964 if (rval != TRAN_ACCEPT) {
2965 return (rval);
2966 }
2967
2968 /*
2969 * Send the command to target/lun, however your HBA requires it.
2970 * If busy, return TRAN_BUSY; if there's some other formatting error
2971 * in the packet, return TRAN_BADPKT; otherwise, fall through to the
2972 * return of TRAN_ACCEPT.
2973 *
2974 * Remember that access to shared resources, including the mptsas_t
2975 * data structure and the HBA hardware registers, must be protected
2976 * with mutexes, here and everywhere.
2977 *
2978 * Also remember that at interrupt time, you'll get an argument
2979 * to the interrupt handler which is a pointer to your mptsas_t
2980 * structure; you'll have to remember which commands are outstanding
2981 * and which scsi_pkt is the currently-running command so the
2982 * interrupt handler can refer to the pkt to set completion
2983 * status, call the target driver back through pkt_comp, etc.
2984 *
2985 * If the instance lock is held by other thread, don't spin to wait
2986 * for it. Instead, queue the cmd and next time when the instance lock
2987 * is not held, accept all the queued cmd. A extra tx_waitq is
2988 * introduced to protect the queue.
2989 *
2990 * The polled cmd will not be queud and accepted as usual.
2991 *
2992 * Under the tx_waitq mutex, record whether a thread is draining
2993 * the tx_waitq. An IO requesting thread that finds the instance
2994 * mutex contended appends to the tx_waitq and while holding the
2995 * tx_wait mutex, if the draining flag is not set, sets it and then
2996 * proceeds to spin for the instance mutex. This scheme ensures that
2997 * the last cmd in a burst be processed.
2998 *
2999 * we enable this feature only when the helper threads are enabled,
3000 * at which we think the loads are heavy.
3001 *
3002 * per instance mutex m_tx_waitq_mutex is introduced to protect the
3003 * m_tx_waitqtail, m_tx_waitq, m_tx_draining.
3004 */
3005
3006 if (mpt->m_doneq_thread_n) {
3007 if (mutex_tryenter(&mpt->m_mutex) != 0) {
3008 rval = mptsas_accept_txwq_and_pkt(mpt, cmd);
3009 mutex_exit(&mpt->m_mutex);
3010 } else if (cmd->cmd_pkt_flags & FLAG_NOINTR) {
3011 mutex_enter(&mpt->m_mutex);
3012 rval = mptsas_accept_txwq_and_pkt(mpt, cmd);
3013 mutex_exit(&mpt->m_mutex);
3014 } else {
3015 mutex_enter(&mpt->m_tx_waitq_mutex);
3016 /*
3017 * ptgt->m_dr_flag is protected by m_mutex or
3018 * m_tx_waitq_mutex. In this case, m_tx_waitq_mutex
3019 * is acquired.
3020 */
3021 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3022 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3023 /*
3024 * The command should be allowed to
3025 * retry by returning TRAN_BUSY to
3026 * to stall the I/O's which come from
3027 * scsi_vhci since the device/path is
3028 * in unstable state now.
3029 */
3030 mutex_exit(&mpt->m_tx_waitq_mutex);
3031 return (TRAN_BUSY);
3032 } else {
3033 /*
3034 * The device is offline, just fail the
3035 * command by returning
3036 * TRAN_FATAL_ERROR.
3037 */
3038 mutex_exit(&mpt->m_tx_waitq_mutex);
3039 return (TRAN_FATAL_ERROR);
3040 }
3041 }
3042 if (mpt->m_tx_draining) {
3043 cmd->cmd_flags |= CFLAG_TXQ;
3044 *mpt->m_tx_waitqtail = cmd;
3045 mpt->m_tx_waitqtail = &cmd->cmd_linkp;
3046 mutex_exit(&mpt->m_tx_waitq_mutex);
3047 } else { /* drain the queue */
3048 mpt->m_tx_draining = 1;
3049 mutex_exit(&mpt->m_tx_waitq_mutex);
3050 mutex_enter(&mpt->m_mutex);
3051 rval = mptsas_accept_txwq_and_pkt(mpt, cmd);
3052 mutex_exit(&mpt->m_mutex);
3053 }
3054 }
3055 } else {
3056 mutex_enter(&mpt->m_mutex);
3057 /*
3058 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex
3059 * in this case, m_mutex is acquired.
3060 */
3061 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3062 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3063 /*
3064 * commands should be allowed to retry by
3065 * returning TRAN_BUSY to stall the I/O's
3066 * which come from scsi_vhci since the device/
3067 * path is in unstable state now.
3068 */
3069 mutex_exit(&mpt->m_mutex);
3070 return (TRAN_BUSY);
3071 } else {
3072 /*
3073 * The device is offline, just fail the
3074 * command by returning TRAN_FATAL_ERROR.
3075 */
3076 mutex_exit(&mpt->m_mutex);
3077 return (TRAN_FATAL_ERROR);
3078 }
3079 }
3080 rval = mptsas_accept_pkt(mpt, cmd);
3081 mutex_exit(&mpt->m_mutex);
3082 }
3083
3084 return (rval);
3085 }
3086
3087 /*
3088 * Accept all the queued cmds(if any) before accept the current one.
3089 */
3090 static int
3091 mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd)
3092 {
3093 int rval;
3094 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3095
3096 ASSERT(mutex_owned(&mpt->m_mutex));
3097 /*
3098 * The call to mptsas_accept_tx_waitq() must always be performed
3099 * because that is where mpt->m_tx_draining is cleared.
3100 */
3101 mutex_enter(&mpt->m_tx_waitq_mutex);
3102 mptsas_accept_tx_waitq(mpt);
3103 mutex_exit(&mpt->m_tx_waitq_mutex);
3104 /*
3105 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex
3106 * in this case, m_mutex is acquired.
3107 */
3108 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3109 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3110 /*
3111 * The command should be allowed to retry by returning
3112 * TRAN_BUSY to stall the I/O's which come from
3113 * scsi_vhci since the device/path is in unstable state
3114 * now.
3115 */
3116 return (TRAN_BUSY);
3117 } else {
3118 /*
3119 * The device is offline, just fail the command by
3120 * return TRAN_FATAL_ERROR.
3121 */
3122 return (TRAN_FATAL_ERROR);
3123 }
3124 }
3125 rval = mptsas_accept_pkt(mpt, cmd);
3126
3127 return (rval);
3128 }
3129
3130 static int
3131 mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd)
3132 {
3133 int rval = TRAN_ACCEPT;
3134 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3135
3136 NDBG1(("mptsas_accept_pkt: cmd=0x%p", (void *)cmd));
3137
3138 ASSERT(mutex_owned(&mpt->m_mutex));
3139
3140 if ((cmd->cmd_flags & CFLAG_PREPARED) == 0) {
3141 rval = mptsas_prepare_pkt(cmd);
3142 if (rval != TRAN_ACCEPT) {
3143 cmd->cmd_flags &= ~CFLAG_TRANFLAG;
3144 return (rval);
3145 }
3146 }
3147
3148 /*
3149 * reset the throttle if we were draining
3150 */
3151 if ((ptgt->m_t_ncmds == 0) &&
3152 (ptgt->m_t_throttle == DRAIN_THROTTLE)) {
3153 NDBG23(("reset throttle"));
3154 ASSERT(ptgt->m_reset_delay == 0);
3155 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
3156 }
3157
3158 /*
3159 * If HBA is being reset, the DevHandles are being re-initialized,
3160 * which means that they could be invalid even if the target is still
3161 * attached. Check if being reset and if DevHandle is being
3162 * re-initialized. If this is the case, return BUSY so the I/O can be
3163 * retried later.
3164 */
3165 if ((ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) && mpt->m_in_reset) {
3166 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
3167 if (cmd->cmd_flags & CFLAG_TXQ) {
3168 mptsas_doneq_add(mpt, cmd);
3169 mptsas_doneq_empty(mpt);
3170 return (rval);
3171 } else {
3172 return (TRAN_BUSY);
3173 }
3174 }
3175
3176 /*
3177 * If device handle has already been invalidated, just
3178 * fail the command. In theory, command from scsi_vhci
3179 * client is impossible send down command with invalid
3180 * devhdl since devhdl is set after path offline, target
3181 * driver is not suppose to select a offlined path.
3182 */
3183 if (ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) {
3184 NDBG20(("rejecting command, it might because invalid devhdl "
3185 "request."));
3186 mptsas_set_pkt_reason(mpt, cmd, CMD_DEV_GONE, STAT_TERMINATED);
3187 if (cmd->cmd_flags & CFLAG_TXQ) {
3188 mptsas_doneq_add(mpt, cmd);
3189 mptsas_doneq_empty(mpt);
3190 return (rval);
3191 } else {
3192 return (TRAN_FATAL_ERROR);
3193 }
3194 }
3195 /*
3196 * The first case is the normal case. mpt gets a command from the
3197 * target driver and starts it.
3198 * Since SMID 0 is reserved and the TM slot is reserved, the actual max
3199 * commands is m_max_requests - 2.
3200 */
3201 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) &&
3202 (ptgt->m_t_throttle > HOLD_THROTTLE) &&
3203 (ptgt->m_t_ncmds < ptgt->m_t_throttle) &&
3204 (ptgt->m_reset_delay == 0) &&
3205 (ptgt->m_t_nwait == 0) &&
3206 ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0)) {
3207 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
3208 (void) mptsas_start_cmd(mpt, cmd);
3209 } else {
3210 mptsas_waitq_add(mpt, cmd);
3211 }
3212 } else {
3213 /*
3214 * Add this pkt to the work queue
3215 */
3216 mptsas_waitq_add(mpt, cmd);
3217
3218 if (cmd->cmd_pkt_flags & FLAG_NOINTR) {
3219 (void) mptsas_poll(mpt, cmd, MPTSAS_POLL_TIME);
3220
3221 /*
3222 * Only flush the doneq if this is not a TM
3223 * cmd. For TM cmds the flushing of the
3224 * doneq will be done in those routines.
3225 */
3226 if ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) {
3227 mptsas_doneq_empty(mpt);
3228 }
3229 }
3230 }
3231 return (rval);
3232 }
3233
3234 int
3235 mptsas_save_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
3236 {
3237 mptsas_slots_t *slots;
3238 int slot;
3239 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3240
3241 ASSERT(mutex_owned(&mpt->m_mutex));
3242 slots = mpt->m_active;
3243
3244 /*
3245 * Account for reserved TM request slot and reserved SMID of 0.
3246 */
3247 ASSERT(slots->m_n_slots == (mpt->m_max_requests - 2));
3248
3249 /*
3250 * m_tags is equivalent to the SMID when sending requests. Since the
3251 * SMID cannot be 0, start out at one if rolling over past the size
3252 * of the request queue depth. Also, don't use the last SMID, which is
3253 * reserved for TM requests.
3254 */
3255 slot = (slots->m_tags)++;
3256 if (slots->m_tags > slots->m_n_slots) {
3257 slots->m_tags = 1;
3258 }
3259
3260 alloc_tag:
3261 /* Validate tag, should never fail. */
3262 if (slots->m_slot[slot] == NULL) {
3263 /*
3264 * Make sure SMID is not using reserved value of 0
3265 * and the TM request slot.
3266 */
3267 ASSERT((slot > 0) && (slot <= slots->m_n_slots));
3268 cmd->cmd_slot = slot;
3269 slots->m_slot[slot] = cmd;
3270 mpt->m_ncmds++;
3271
3272 /*
3273 * only increment per target ncmds if this is not a
3274 * command that has no target associated with it (i.e. a
3275 * event acknoledgment)
3276 */
3277 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
3278 ptgt->m_t_ncmds++;
3279 }
3280 cmd->cmd_active_timeout = cmd->cmd_pkt->pkt_time;
3281
3282 /*
3283 * If initial timout is less than or equal to one tick, bump
3284 * the timeout by a tick so that command doesn't timeout before
3285 * its allotted time.
3286 */
3287 if (cmd->cmd_active_timeout <= mptsas_scsi_watchdog_tick) {
3288 cmd->cmd_active_timeout += mptsas_scsi_watchdog_tick;
3289 }
3290 return (TRUE);
3291 } else {
3292 int i;
3293
3294 /*
3295 * If slot in use, scan until a free one is found. Don't use 0
3296 * or final slot, which is reserved for TM requests.
3297 */
3298 for (i = 0; i < slots->m_n_slots; i++) {
3299 slot = slots->m_tags;
3300 if (++(slots->m_tags) > slots->m_n_slots) {
3301 slots->m_tags = 1;
3302 }
3303 if (slots->m_slot[slot] == NULL) {
3304 NDBG22(("found free slot %d", slot));
3305 goto alloc_tag;
3306 }
3307 }
3308 }
3309 return (FALSE);
3310 }
3311
3312 /*
3313 * prepare the pkt:
3314 * the pkt may have been resubmitted or just reused so
3315 * initialize some fields and do some checks.
3316 */
3317 static int
3318 mptsas_prepare_pkt(mptsas_cmd_t *cmd)
3319 {
3320 struct scsi_pkt *pkt = CMD2PKT(cmd);
3321
3322 NDBG1(("mptsas_prepare_pkt: cmd=0x%p", (void *)cmd));
3323
3324 /*
3325 * Reinitialize some fields that need it; the packet may
3326 * have been resubmitted
3327 */
3328 pkt->pkt_reason = CMD_CMPLT;
3329 pkt->pkt_state = 0;
3330 pkt->pkt_statistics = 0;
3331 pkt->pkt_resid = 0;
3332 cmd->cmd_age = 0;
3333 cmd->cmd_pkt_flags = pkt->pkt_flags;
3334
3335 /*
3336 * zero status byte.
3337 */
3338 *(pkt->pkt_scbp) = 0;
3339
3340 if (cmd->cmd_flags & CFLAG_DMAVALID) {
3341 pkt->pkt_resid = cmd->cmd_dmacount;
3342
3343 /*
3344 * consistent packets need to be sync'ed first
3345 * (only for data going out)
3346 */
3347 if ((cmd->cmd_flags & CFLAG_CMDIOPB) &&
3348 (cmd->cmd_flags & CFLAG_DMASEND)) {
3349 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
3350 DDI_DMA_SYNC_FORDEV);
3351 }
3352 }
3353
3354 cmd->cmd_flags =
3355 (cmd->cmd_flags & ~(CFLAG_TRANFLAG)) |
3356 CFLAG_PREPARED | CFLAG_IN_TRANSPORT;
3357
3358 return (TRAN_ACCEPT);
3359 }
3360
3361 /*
3362 * tran_init_pkt(9E) - allocate scsi_pkt(9S) for command
3363 *
3364 * One of three possibilities:
3365 * - allocate scsi_pkt
3366 * - allocate scsi_pkt and DMA resources
3367 * - allocate DMA resources to an already-allocated pkt
3368 */
3369 static struct scsi_pkt *
3370 mptsas_scsi_init_pkt(struct scsi_address *ap, struct scsi_pkt *pkt,
3371 struct buf *bp, int cmdlen, int statuslen, int tgtlen, int flags,
3372 int (*callback)(), caddr_t arg)
3373 {
3374 mptsas_cmd_t *cmd, *new_cmd;
3375 mptsas_t *mpt = ADDR2MPT(ap);
3376 int failure = 1;
3377 uint_t oldcookiec;
3378 mptsas_target_t *ptgt = NULL;
3379 int rval;
3380 mptsas_tgt_private_t *tgt_private;
3381 int kf;
3382
3383 kf = (callback == SLEEP_FUNC)? KM_SLEEP: KM_NOSLEEP;
3384
3385 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->
3386 tran_tgt_private;
3387 ASSERT(tgt_private != NULL);
3388 if (tgt_private == NULL) {
3389 return (NULL);
3390 }
3391 ptgt = tgt_private->t_private;
3392 ASSERT(ptgt != NULL);
3393 if (ptgt == NULL)
3394 return (NULL);
3395 ap->a_target = ptgt->m_devhdl;
3396 ap->a_lun = tgt_private->t_lun;
3397
3398 ASSERT(callback == NULL_FUNC || callback == SLEEP_FUNC);
3399 #ifdef MPTSAS_TEST_EXTRN_ALLOC
3400 statuslen *= 100; tgtlen *= 4;
3401 #endif
3402 NDBG3(("mptsas_scsi_init_pkt:\n"
3403 "\ttgt=%d in=0x%p bp=0x%p clen=%d slen=%d tlen=%d flags=%x",
3404 ap->a_target, (void *)pkt, (void *)bp,
3405 cmdlen, statuslen, tgtlen, flags));
3406
3407 /*
3408 * Allocate the new packet.
3409 */
3410 if (pkt == NULL) {
3411 ddi_dma_handle_t save_dma_handle;
3412 ddi_dma_handle_t save_arq_dma_handle;
3413 struct buf *save_arq_bp;
3414 ddi_dma_cookie_t save_arqcookie;
3415
3416 cmd = kmem_cache_alloc(mpt->m_kmem_cache, kf);
3417
3418 if (cmd) {
3419 save_dma_handle = cmd->cmd_dmahandle;
3420 save_arq_dma_handle = cmd->cmd_arqhandle;
3421 save_arq_bp = cmd->cmd_arq_buf;
3422 save_arqcookie = cmd->cmd_arqcookie;
3423 bzero(cmd, sizeof (*cmd) + scsi_pkt_size());
3424 cmd->cmd_dmahandle = save_dma_handle;
3425 cmd->cmd_arqhandle = save_arq_dma_handle;
3426 cmd->cmd_arq_buf = save_arq_bp;
3427 cmd->cmd_arqcookie = save_arqcookie;
3428
3429 pkt = (void *)((uchar_t *)cmd +
3430 sizeof (struct mptsas_cmd));
3431 pkt->pkt_ha_private = (opaque_t)cmd;
3432 pkt->pkt_address = *ap;
3433 pkt->pkt_private = (opaque_t)cmd->cmd_pkt_private;
3434 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb;
3435 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb;
3436 cmd->cmd_pkt = (struct scsi_pkt *)pkt;
3437 cmd->cmd_cdblen = (uchar_t)cmdlen;
3438 cmd->cmd_scblen = statuslen;
3439 cmd->cmd_rqslen = SENSE_LENGTH;
3440 cmd->cmd_tgt_addr = ptgt;
3441 failure = 0;
3442 }
3443
3444 if (failure || (cmdlen > sizeof (cmd->cmd_cdb)) ||
3445 (tgtlen > PKT_PRIV_LEN) ||
3446 (statuslen > EXTCMDS_STATUS_SIZE)) {
3447 if (failure == 0) {
3448 /*
3449 * if extern alloc fails, all will be
3450 * deallocated, including cmd
3451 */
3452 failure = mptsas_pkt_alloc_extern(mpt, cmd,
3453 cmdlen, tgtlen, statuslen, kf);
3454 }
3455 if (failure) {
3456 /*
3457 * if extern allocation fails, it will
3458 * deallocate the new pkt as well
3459 */
3460 return (NULL);
3461 }
3462 }
3463 new_cmd = cmd;
3464
3465 } else {
3466 cmd = PKT2CMD(pkt);
3467 new_cmd = NULL;
3468 }
3469
3470
3471 /* grab cmd->cmd_cookiec here as oldcookiec */
3472
3473 oldcookiec = cmd->cmd_cookiec;
3474
3475 /*
3476 * If the dma was broken up into PARTIAL transfers cmd_nwin will be
3477 * greater than 0 and we'll need to grab the next dma window
3478 */
3479 /*
3480 * SLM-not doing extra command frame right now; may add later
3481 */
3482
3483 if (cmd->cmd_nwin > 0) {
3484
3485 /*
3486 * Make sure we havn't gone past the the total number
3487 * of windows
3488 */
3489 if (++cmd->cmd_winindex >= cmd->cmd_nwin) {
3490 return (NULL);
3491 }
3492 if (ddi_dma_getwin(cmd->cmd_dmahandle, cmd->cmd_winindex,
3493 &cmd->cmd_dma_offset, &cmd->cmd_dma_len,
3494 &cmd->cmd_cookie, &cmd->cmd_cookiec) == DDI_FAILURE) {
3495 return (NULL);
3496 }
3497 goto get_dma_cookies;
3498 }
3499
3500
3501 if (flags & PKT_XARQ) {
3502 cmd->cmd_flags |= CFLAG_XARQ;
3503 }
3504
3505 /*
3506 * DMA resource allocation. This version assumes your
3507 * HBA has some sort of bus-mastering or onboard DMA capability, with a
3508 * scatter-gather list of length MPTSAS_MAX_DMA_SEGS, as given in the
3509 * ddi_dma_attr_t structure and passed to scsi_impl_dmaget.
3510 */
3511 if (bp && (bp->b_bcount != 0) &&
3512 (cmd->cmd_flags & CFLAG_DMAVALID) == 0) {
3513
3514 int cnt, dma_flags;
3515 mptti_t *dmap; /* ptr to the S/G list */
3516
3517 /*
3518 * Set up DMA memory and position to the next DMA segment.
3519 */
3520 ASSERT(cmd->cmd_dmahandle != NULL);
3521
3522 if (bp->b_flags & B_READ) {
3523 dma_flags = DDI_DMA_READ;
3524 cmd->cmd_flags &= ~CFLAG_DMASEND;
3525 } else {
3526 dma_flags = DDI_DMA_WRITE;
3527 cmd->cmd_flags |= CFLAG_DMASEND;
3528 }
3529 if (flags & PKT_CONSISTENT) {
3530 cmd->cmd_flags |= CFLAG_CMDIOPB;
3531 dma_flags |= DDI_DMA_CONSISTENT;
3532 }
3533
3534 if (flags & PKT_DMA_PARTIAL) {
3535 dma_flags |= DDI_DMA_PARTIAL;
3536 }
3537
3538 /*
3539 * workaround for byte hole issue on psycho and
3540 * schizo pre 2.1
3541 */
3542 if ((bp->b_flags & B_READ) && ((bp->b_flags &
3543 (B_PAGEIO|B_REMAPPED)) != B_PAGEIO) &&
3544 ((uintptr_t)bp->b_un.b_addr & 0x7)) {
3545 dma_flags |= DDI_DMA_CONSISTENT;
3546 }
3547
3548 rval = ddi_dma_buf_bind_handle(cmd->cmd_dmahandle, bp,
3549 dma_flags, callback, arg,
3550 &cmd->cmd_cookie, &cmd->cmd_cookiec);
3551 if (rval == DDI_DMA_PARTIAL_MAP) {
3552 (void) ddi_dma_numwin(cmd->cmd_dmahandle,
3553 &cmd->cmd_nwin);
3554 cmd->cmd_winindex = 0;
3555 (void) ddi_dma_getwin(cmd->cmd_dmahandle,
3556 cmd->cmd_winindex, &cmd->cmd_dma_offset,
3557 &cmd->cmd_dma_len, &cmd->cmd_cookie,
3558 &cmd->cmd_cookiec);
3559 } else if (rval && (rval != DDI_DMA_MAPPED)) {
3560 switch (rval) {
3561 case DDI_DMA_NORESOURCES:
3562 bioerror(bp, 0);
3563 break;
3564 case DDI_DMA_BADATTR:
3565 case DDI_DMA_NOMAPPING:
3566 bioerror(bp, EFAULT);
3567 break;
3568 case DDI_DMA_TOOBIG:
3569 default:
3570 bioerror(bp, EINVAL);
3571 break;
3572 }
3573 cmd->cmd_flags &= ~CFLAG_DMAVALID;
3574 if (new_cmd) {
3575 mptsas_scsi_destroy_pkt(ap, pkt);
3576 }
3577 return ((struct scsi_pkt *)NULL);
3578 }
3579
3580 get_dma_cookies:
3581 cmd->cmd_flags |= CFLAG_DMAVALID;
3582 ASSERT(cmd->cmd_cookiec > 0);
3583
3584 if (cmd->cmd_cookiec > MPTSAS_MAX_CMD_SEGS) {
3585 mptsas_log(mpt, CE_NOTE, "large cookiec received %d\n",
3586 cmd->cmd_cookiec);
3587 bioerror(bp, EINVAL);
3588 if (new_cmd) {
3589 mptsas_scsi_destroy_pkt(ap, pkt);
3590 }
3591 return ((struct scsi_pkt *)NULL);
3592 }
3593
3594 /*
3595 * Allocate extra SGL buffer if needed.
3596 */
3597 if ((cmd->cmd_cookiec > MPTSAS_MAX_FRAME_SGES64(mpt)) &&
3598 (cmd->cmd_extra_frames == NULL)) {
3599 if (mptsas_alloc_extra_sgl_frame(mpt, cmd) ==
3600 DDI_FAILURE) {
3601 mptsas_log(mpt, CE_WARN, "MPT SGL mem alloc "
3602 "failed");
3603 bioerror(bp, ENOMEM);
3604 if (new_cmd) {
3605 mptsas_scsi_destroy_pkt(ap, pkt);
3606 }
3607 return ((struct scsi_pkt *)NULL);
3608 }
3609 }
3610
3611 /*
3612 * Always use scatter-gather transfer
3613 * Use the loop below to store physical addresses of
3614 * DMA segments, from the DMA cookies, into your HBA's
3615 * scatter-gather list.
3616 * We need to ensure we have enough kmem alloc'd
3617 * for the sg entries since we are no longer using an
3618 * array inside mptsas_cmd_t.
3619 *
3620 * We check cmd->cmd_cookiec against oldcookiec so
3621 * the scatter-gather list is correctly allocated
3622 */
3623
3624 if (oldcookiec != cmd->cmd_cookiec) {
3625 if (cmd->cmd_sg != (mptti_t *)NULL) {
3626 kmem_free(cmd->cmd_sg, sizeof (mptti_t) *
3627 oldcookiec);
3628 cmd->cmd_sg = NULL;
3629 }
3630 }
3631
3632 if (cmd->cmd_sg == (mptti_t *)NULL) {
3633 cmd->cmd_sg = kmem_alloc((size_t)(sizeof (mptti_t)*
3634 cmd->cmd_cookiec), kf);
3635
3636 if (cmd->cmd_sg == (mptti_t *)NULL) {
3637 mptsas_log(mpt, CE_WARN,
3638 "unable to kmem_alloc enough memory "
3639 "for scatter/gather list");
3640 /*
3641 * if we have an ENOMEM condition we need to behave
3642 * the same way as the rest of this routine
3643 */
3644
3645 bioerror(bp, ENOMEM);
3646 if (new_cmd) {
3647 mptsas_scsi_destroy_pkt(ap, pkt);
3648 }
3649 return ((struct scsi_pkt *)NULL);
3650 }
3651 }
3652
3653 dmap = cmd->cmd_sg;
3654
3655 ASSERT(cmd->cmd_cookie.dmac_size != 0);
3656
3657 /*
3658 * store the first segment into the S/G list
3659 */
3660 dmap->count = cmd->cmd_cookie.dmac_size;
3661 dmap->addr.address64.Low = (uint32_t)
3662 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull);
3663 dmap->addr.address64.High = (uint32_t)
3664 (cmd->cmd_cookie.dmac_laddress >> 32);
3665
3666 /*
3667 * dmacount counts the size of the dma for this window
3668 * (if partial dma is being used). totaldmacount
3669 * keeps track of the total amount of dma we have
3670 * transferred for all the windows (needed to calculate
3671 * the resid value below).
3672 */
3673 cmd->cmd_dmacount = cmd->cmd_cookie.dmac_size;
3674 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size;
3675
3676 /*
3677 * We already stored the first DMA scatter gather segment,
3678 * start at 1 if we need to store more.
3679 */
3680 for (cnt = 1; cnt < cmd->cmd_cookiec; cnt++) {
3681 /*
3682 * Get next DMA cookie
3683 */
3684 ddi_dma_nextcookie(cmd->cmd_dmahandle,
3685 &cmd->cmd_cookie);
3686 dmap++;
3687
3688 cmd->cmd_dmacount += cmd->cmd_cookie.dmac_size;
3689 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size;
3690
3691 /*
3692 * store the segment parms into the S/G list
3693 */
3694 dmap->count = cmd->cmd_cookie.dmac_size;
3695 dmap->addr.address64.Low = (uint32_t)
3696 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull);
3697 dmap->addr.address64.High = (uint32_t)
3698 (cmd->cmd_cookie.dmac_laddress >> 32);
3699 }
3700
3701 /*
3702 * If this was partially allocated we set the resid
3703 * the amount of data NOT transferred in this window
3704 * If there is only one window, the resid will be 0
3705 */
3706 pkt->pkt_resid = (bp->b_bcount - cmd->cmd_totaldmacount);
3707 NDBG16(("mptsas_dmaget: cmd_dmacount=%d.", cmd->cmd_dmacount));
3708 }
3709 return (pkt);
3710 }
3711
3712 /*
3713 * tran_destroy_pkt(9E) - scsi_pkt(9s) deallocation
3714 *
3715 * Notes:
3716 * - also frees DMA resources if allocated
3717 * - implicit DMA synchonization
3718 */
3719 static void
3720 mptsas_scsi_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
3721 {
3722 mptsas_cmd_t *cmd = PKT2CMD(pkt);
3723 mptsas_t *mpt = ADDR2MPT(ap);
3724
3725 NDBG3(("mptsas_scsi_destroy_pkt: target=%d pkt=0x%p",
3726 ap->a_target, (void *)pkt));
3727
3728 if (cmd->cmd_flags & CFLAG_DMAVALID) {
3729 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle);
3730 cmd->cmd_flags &= ~CFLAG_DMAVALID;
3731 }
3732
3733 if (cmd->cmd_sg) {
3734 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * cmd->cmd_cookiec);
3735 cmd->cmd_sg = NULL;
3736 }
3737
3738 mptsas_free_extra_sgl_frame(mpt, cmd);
3739
3740 if ((cmd->cmd_flags &
3741 (CFLAG_FREE | CFLAG_CDBEXTERN | CFLAG_PRIVEXTERN |
3742 CFLAG_SCBEXTERN)) == 0) {
3743 cmd->cmd_flags = CFLAG_FREE;
3744 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd);
3745 } else {
3746 mptsas_pkt_destroy_extern(mpt, cmd);
3747 }
3748 }
3749
3750 /*
3751 * kmem cache constructor and destructor:
3752 * When constructing, we bzero the cmd and allocate the dma handle
3753 * When destructing, just free the dma handle
3754 */
3755 static int
3756 mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags)
3757 {
3758 mptsas_cmd_t *cmd = buf;
3759 mptsas_t *mpt = cdrarg;
3760 struct scsi_address ap;
3761 uint_t cookiec;
3762 ddi_dma_attr_t arq_dma_attr;
3763 int (*callback)(caddr_t);
3764
3765 callback = (kmflags == KM_SLEEP)? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT;
3766
3767 NDBG4(("mptsas_kmem_cache_constructor"));
3768
3769 ap.a_hba_tran = mpt->m_tran;
3770 ap.a_target = 0;
3771 ap.a_lun = 0;
3772
3773 /*
3774 * allocate a dma handle
3775 */
3776 if ((ddi_dma_alloc_handle(mpt->m_dip, &mpt->m_io_dma_attr, callback,
3777 NULL, &cmd->cmd_dmahandle)) != DDI_SUCCESS) {
3778 cmd->cmd_dmahandle = NULL;
3779 return (-1);
3780 }
3781
3782 cmd->cmd_arq_buf = scsi_alloc_consistent_buf(&ap, (struct buf *)NULL,
3783 SENSE_LENGTH, B_READ, callback, NULL);
3784 if (cmd->cmd_arq_buf == NULL) {
3785 ddi_dma_free_handle(&cmd->cmd_dmahandle);
3786 cmd->cmd_dmahandle = NULL;
3787 return (-1);
3788 }
3789
3790 /*
3791 * allocate a arq handle
3792 */
3793 arq_dma_attr = mpt->m_msg_dma_attr;
3794 arq_dma_attr.dma_attr_sgllen = 1;
3795 if ((ddi_dma_alloc_handle(mpt->m_dip, &arq_dma_attr, callback,
3796 NULL, &cmd->cmd_arqhandle)) != DDI_SUCCESS) {
3797 ddi_dma_free_handle(&cmd->cmd_dmahandle);
3798 scsi_free_consistent_buf(cmd->cmd_arq_buf);
3799 cmd->cmd_dmahandle = NULL;
3800 cmd->cmd_arqhandle = NULL;
3801 return (-1);
3802 }
3803
3804 if (ddi_dma_buf_bind_handle(cmd->cmd_arqhandle,
3805 cmd->cmd_arq_buf, (DDI_DMA_READ | DDI_DMA_CONSISTENT),
3806 callback, NULL, &cmd->cmd_arqcookie, &cookiec) != DDI_SUCCESS) {
3807 ddi_dma_free_handle(&cmd->cmd_dmahandle);
3808 ddi_dma_free_handle(&cmd->cmd_arqhandle);
3809 scsi_free_consistent_buf(cmd->cmd_arq_buf);
3810 cmd->cmd_dmahandle = NULL;
3811 cmd->cmd_arqhandle = NULL;
3812 cmd->cmd_arq_buf = NULL;
3813 return (-1);
3814 }
3815
3816 return (0);
3817 }
3818
3819 static void
3820 mptsas_kmem_cache_destructor(void *buf, void *cdrarg)
3821 {
3822 #ifndef __lock_lint
3823 _NOTE(ARGUNUSED(cdrarg))
3824 #endif
3825 mptsas_cmd_t *cmd = buf;
3826
3827 NDBG4(("mptsas_kmem_cache_destructor"));
3828
3829 if (cmd->cmd_arqhandle) {
3830 (void) ddi_dma_unbind_handle(cmd->cmd_arqhandle);
3831 ddi_dma_free_handle(&cmd->cmd_arqhandle);
3832 cmd->cmd_arqhandle = NULL;
3833 }
3834 if (cmd->cmd_arq_buf) {
3835 scsi_free_consistent_buf(cmd->cmd_arq_buf);
3836 cmd->cmd_arq_buf = NULL;
3837 }
3838 if (cmd->cmd_dmahandle) {
3839 ddi_dma_free_handle(&cmd->cmd_dmahandle);
3840 cmd->cmd_dmahandle = NULL;
3841 }
3842 }
3843
3844 static int
3845 mptsas_cache_frames_constructor(void *buf, void *cdrarg, int kmflags)
3846 {
3847 mptsas_cache_frames_t *p = buf;
3848 mptsas_t *mpt = cdrarg;
3849 ddi_dma_attr_t frame_dma_attr;
3850 size_t mem_size, alloc_len;
3851 ddi_dma_cookie_t cookie;
3852 uint_t ncookie;
3853 int (*callback)(caddr_t) = (kmflags == KM_SLEEP)
3854 ? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT;
3855
3856 frame_dma_attr = mpt->m_msg_dma_attr;
3857 frame_dma_attr.dma_attr_align = 0x10;
3858 frame_dma_attr.dma_attr_sgllen = 1;
3859
3860 if (ddi_dma_alloc_handle(mpt->m_dip, &frame_dma_attr, callback, NULL,
3861 &p->m_dma_hdl) != DDI_SUCCESS) {
3862 mptsas_log(mpt, CE_WARN, "Unable to allocate dma handle for"
3863 " extra SGL.");
3864 return (DDI_FAILURE);
3865 }
3866
3867 mem_size = (mpt->m_max_request_frames - 1) * mpt->m_req_frame_size;
3868
3869 if (ddi_dma_mem_alloc(p->m_dma_hdl, mem_size, &mpt->m_dev_acc_attr,
3870 DDI_DMA_CONSISTENT, callback, NULL, (caddr_t *)&p->m_frames_addr,
3871 &alloc_len, &p->m_acc_hdl) != DDI_SUCCESS) {
3872 ddi_dma_free_handle(&p->m_dma_hdl);
3873 p->m_dma_hdl = NULL;
3874 mptsas_log(mpt, CE_WARN, "Unable to allocate dma memory for"
3875 " extra SGL.");
3876 return (DDI_FAILURE);
3877 }
3878
3879 if (ddi_dma_addr_bind_handle(p->m_dma_hdl, NULL, p->m_frames_addr,
3880 alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, callback, NULL,
3881 &cookie, &ncookie) != DDI_DMA_MAPPED) {
3882 (void) ddi_dma_mem_free(&p->m_acc_hdl);
3883 ddi_dma_free_handle(&p->m_dma_hdl);
3884 p->m_dma_hdl = NULL;
3885 mptsas_log(mpt, CE_WARN, "Unable to bind DMA resources for"
3886 " extra SGL");
3887 return (DDI_FAILURE);
3888 }
3889
3890 /*
3891 * Store the SGL memory address. This chip uses this
3892 * address to dma to and from the driver. The second
3893 * address is the address mpt uses to fill in the SGL.
3894 */
3895 p->m_phys_addr = cookie.dmac_address;
3896
3897 return (DDI_SUCCESS);
3898 }
3899
3900 static void
3901 mptsas_cache_frames_destructor(void *buf, void *cdrarg)
3902 {
3903 #ifndef __lock_lint
3904 _NOTE(ARGUNUSED(cdrarg))
3905 #endif
3906 mptsas_cache_frames_t *p = buf;
3907 if (p->m_dma_hdl != NULL) {
3908 (void) ddi_dma_unbind_handle(p->m_dma_hdl);
3909 (void) ddi_dma_mem_free(&p->m_acc_hdl);
3910 ddi_dma_free_handle(&p->m_dma_hdl);
3911 p->m_phys_addr = NULL;
3912 p->m_frames_addr = NULL;
3913 p->m_dma_hdl = NULL;
3914 p->m_acc_hdl = NULL;
3915 }
3916
3917 }
3918
3919 /*
3920 * allocate and deallocate external pkt space (ie. not part of mptsas_cmd)
3921 * for non-standard length cdb, pkt_private, status areas
3922 * if allocation fails, then deallocate all external space and the pkt
3923 */
3924 /* ARGSUSED */
3925 static int
3926 mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd,
3927 int cmdlen, int tgtlen, int statuslen, int kf)
3928 {
3929 caddr_t cdbp, scbp, tgt;
3930 int (*callback)(caddr_t) = (kf == KM_SLEEP) ?
3931 DDI_DMA_SLEEP : DDI_DMA_DONTWAIT;
3932 struct scsi_address ap;
3933 size_t senselength;
3934 ddi_dma_attr_t ext_arq_dma_attr;
3935 uint_t cookiec;
3936
3937 NDBG3(("mptsas_pkt_alloc_extern: "
3938 "cmd=0x%p cmdlen=%d tgtlen=%d statuslen=%d kf=%x",
3939 (void *)cmd, cmdlen, tgtlen, statuslen, kf));
3940
3941 tgt = cdbp = scbp = NULL;
3942 cmd->cmd_scblen = statuslen;
3943 cmd->cmd_privlen = (uchar_t)tgtlen;
3944
3945 if (cmdlen > sizeof (cmd->cmd_cdb)) {
3946 if ((cdbp = kmem_zalloc((size_t)cmdlen, kf)) == NULL) {
3947 goto fail;
3948 }
3949 cmd->cmd_pkt->pkt_cdbp = (opaque_t)cdbp;
3950 cmd->cmd_flags |= CFLAG_CDBEXTERN;
3951 }
3952 if (tgtlen > PKT_PRIV_LEN) {
3953 if ((tgt = kmem_zalloc((size_t)tgtlen, kf)) == NULL) {
3954 goto fail;
3955 }
3956 cmd->cmd_flags |= CFLAG_PRIVEXTERN;
3957 cmd->cmd_pkt->pkt_private = tgt;
3958 }
3959 if (statuslen > EXTCMDS_STATUS_SIZE) {
3960 if ((scbp = kmem_zalloc((size_t)statuslen, kf)) == NULL) {
3961 goto fail;
3962 }
3963 cmd->cmd_flags |= CFLAG_SCBEXTERN;
3964 cmd->cmd_pkt->pkt_scbp = (opaque_t)scbp;
3965
3966 /* allocate sense data buf for DMA */
3967
3968 senselength = statuslen - MPTSAS_GET_ITEM_OFF(
3969 struct scsi_arq_status, sts_sensedata);
3970 cmd->cmd_rqslen = (uchar_t)senselength;
3971
3972 ap.a_hba_tran = mpt->m_tran;
3973 ap.a_target = 0;
3974 ap.a_lun = 0;
3975
3976 cmd->cmd_ext_arq_buf = scsi_alloc_consistent_buf(&ap,
3977 (struct buf *)NULL, senselength, B_READ,
3978 callback, NULL);
3979
3980 if (cmd->cmd_ext_arq_buf == NULL) {
3981 goto fail;
3982 }
3983 /*
3984 * allocate a extern arq handle and bind the buf
3985 */
3986 ext_arq_dma_attr = mpt->m_msg_dma_attr;
3987 ext_arq_dma_attr.dma_attr_sgllen = 1;
3988 if ((ddi_dma_alloc_handle(mpt->m_dip,
3989 &ext_arq_dma_attr, callback,
3990 NULL, &cmd->cmd_ext_arqhandle)) != DDI_SUCCESS) {
3991 goto fail;
3992 }
3993
3994 if (ddi_dma_buf_bind_handle(cmd->cmd_ext_arqhandle,
3995 cmd->cmd_ext_arq_buf, (DDI_DMA_READ | DDI_DMA_CONSISTENT),
3996 callback, NULL, &cmd->cmd_ext_arqcookie,
3997 &cookiec)
3998 != DDI_SUCCESS) {
3999 goto fail;
4000 }
4001 cmd->cmd_flags |= CFLAG_EXTARQBUFVALID;
4002 }
4003 return (0);
4004 fail:
4005 mptsas_pkt_destroy_extern(mpt, cmd);
4006 return (1);
4007 }
4008
4009 /*
4010 * deallocate external pkt space and deallocate the pkt
4011 */
4012 static void
4013 mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd)
4014 {
4015 NDBG3(("mptsas_pkt_destroy_extern: cmd=0x%p", (void *)cmd));
4016
4017 if (cmd->cmd_flags & CFLAG_FREE) {
4018 mptsas_log(mpt, CE_PANIC,
4019 "mptsas_pkt_destroy_extern: freeing free packet");
4020 _NOTE(NOT_REACHED)
4021 /* NOTREACHED */
4022 }
4023 if (cmd->cmd_flags & CFLAG_CDBEXTERN) {
4024 kmem_free(cmd->cmd_pkt->pkt_cdbp, (size_t)cmd->cmd_cdblen);
4025 }
4026 if (cmd->cmd_flags & CFLAG_SCBEXTERN) {
4027 kmem_free(cmd->cmd_pkt->pkt_scbp, (size_t)cmd->cmd_scblen);
4028 if (cmd->cmd_flags & CFLAG_EXTARQBUFVALID) {
4029 (void) ddi_dma_unbind_handle(cmd->cmd_ext_arqhandle);
4030 }
4031 if (cmd->cmd_ext_arqhandle) {
4032 ddi_dma_free_handle(&cmd->cmd_ext_arqhandle);
4033 cmd->cmd_ext_arqhandle = NULL;
4034 }
4035 if (cmd->cmd_ext_arq_buf)
4036 scsi_free_consistent_buf(cmd->cmd_ext_arq_buf);
4037 }
4038 if (cmd->cmd_flags & CFLAG_PRIVEXTERN) {
4039 kmem_free(cmd->cmd_pkt->pkt_private, (size_t)cmd->cmd_privlen);
4040 }
4041 cmd->cmd_flags = CFLAG_FREE;
4042 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd);
4043 }
4044
4045 /*
4046 * tran_sync_pkt(9E) - explicit DMA synchronization
4047 */
4048 /*ARGSUSED*/
4049 static void
4050 mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
4051 {
4052 mptsas_cmd_t *cmd = PKT2CMD(pkt);
4053
4054 NDBG3(("mptsas_scsi_sync_pkt: target=%d, pkt=0x%p",
4055 ap->a_target, (void *)pkt));
4056
4057 if (cmd->cmd_dmahandle) {
4058 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
4059 (cmd->cmd_flags & CFLAG_DMASEND) ?
4060 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU);
4061 }
4062 }
4063
4064 /*
4065 * tran_dmafree(9E) - deallocate DMA resources allocated for command
4066 */
4067 /*ARGSUSED*/
4068 static void
4069 mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt)
4070 {
4071 mptsas_cmd_t *cmd = PKT2CMD(pkt);
4072 mptsas_t *mpt = ADDR2MPT(ap);
4073
4074 NDBG3(("mptsas_scsi_dmafree: target=%d pkt=0x%p",
4075 ap->a_target, (void *)pkt));
4076
4077 if (cmd->cmd_flags & CFLAG_DMAVALID) {
4078 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle);
4079 cmd->cmd_flags &= ~CFLAG_DMAVALID;
4080 }
4081
4082 if (cmd->cmd_flags & CFLAG_EXTARQBUFVALID) {
4083 (void) ddi_dma_unbind_handle(cmd->cmd_ext_arqhandle);
4084 cmd->cmd_flags &= ~CFLAG_EXTARQBUFVALID;
4085 }
4086
4087 mptsas_free_extra_sgl_frame(mpt, cmd);
4088 }
4089
4090 static void
4091 mptsas_pkt_comp(struct scsi_pkt *pkt, mptsas_cmd_t *cmd)
4092 {
4093 if ((cmd->cmd_flags & CFLAG_CMDIOPB) &&
4094 (!(cmd->cmd_flags & CFLAG_DMASEND))) {
4095 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
4096 DDI_DMA_SYNC_FORCPU);
4097 }
4098 (*pkt->pkt_comp)(pkt);
4099 }
4100
4101 static void
4102 mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, uint32_t *control,
4103 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl)
4104 {
4105 uint_t cookiec;
4106 mptti_t *dmap;
4107 uint32_t flags;
4108 pMpi2SGESimple64_t sge;
4109 pMpi2SGEChain64_t sgechain;
4110 ASSERT(cmd->cmd_flags & CFLAG_DMAVALID);
4111
4112 /*
4113 * Save the number of entries in the DMA
4114 * Scatter/Gather list
4115 */
4116 cookiec = cmd->cmd_cookiec;
4117
4118 NDBG1(("mptsas_sge_setup: cookiec=%d", cookiec));
4119
4120 /*
4121 * Set read/write bit in control.
4122 */
4123 if (cmd->cmd_flags & CFLAG_DMASEND) {
4124 *control |= MPI2_SCSIIO_CONTROL_WRITE;
4125 } else {
4126 *control |= MPI2_SCSIIO_CONTROL_READ;
4127 }
4128
4129 ddi_put32(acc_hdl, &frame->DataLength, cmd->cmd_dmacount);
4130
4131 /*
4132 * We have 2 cases here. First where we can fit all the
4133 * SG elements into the main frame, and the case
4134 * where we can't.
4135 * If we have more cookies than we can attach to a frame
4136 * we will need to use a chain element to point
4137 * a location of memory where the rest of the S/G
4138 * elements reside.
4139 */
4140 if (cookiec <= MPTSAS_MAX_FRAME_SGES64(mpt)) {
4141 dmap = cmd->cmd_sg;
4142 sge = (pMpi2SGESimple64_t)(&frame->SGL);
4143 while (cookiec--) {
4144 ddi_put32(acc_hdl,
4145 &sge->Address.Low, dmap->addr.address64.Low);
4146 ddi_put32(acc_hdl,
4147 &sge->Address.High, dmap->addr.address64.High);
4148 ddi_put32(acc_hdl, &sge->FlagsLength,
4149 dmap->count);
4150 flags = ddi_get32(acc_hdl, &sge->FlagsLength);
4151 flags |= ((uint32_t)
4152 (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4153 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4154 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4155 MPI2_SGE_FLAGS_SHIFT);
4156
4157 /*
4158 * If this is the last cookie, we set the flags
4159 * to indicate so
4160 */
4161 if (cookiec == 0) {
4162 flags |=
4163 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT
4164 | MPI2_SGE_FLAGS_END_OF_BUFFER
4165 | MPI2_SGE_FLAGS_END_OF_LIST) <<
4166 MPI2_SGE_FLAGS_SHIFT);
4167 }
4168 if (cmd->cmd_flags & CFLAG_DMASEND) {
4169 flags |= (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4170 MPI2_SGE_FLAGS_SHIFT);
4171 } else {
4172 flags |= (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4173 MPI2_SGE_FLAGS_SHIFT);
4174 }
4175 ddi_put32(acc_hdl, &sge->FlagsLength, flags);
4176 dmap++;
4177 sge++;
4178 }
4179 } else {
4180 /*
4181 * Hereby we start to deal with multiple frames.
4182 * The process is as follows:
4183 * 1. Determine how many frames are needed for SGL element
4184 * storage; Note that all frames are stored in contiguous
4185 * memory space and in 64-bit DMA mode each element is
4186 * 3 double-words (12 bytes) long.
4187 * 2. Fill up the main frame. We need to do this separately
4188 * since it contains the SCSI IO request header and needs
4189 * dedicated processing. Note that the last 4 double-words
4190 * of the SCSI IO header is for SGL element storage
4191 * (MPI2_SGE_IO_UNION).
4192 * 3. Fill the chain element in the main frame, so the DMA
4193 * engine can use the following frames.
4194 * 4. Enter a loop to fill the remaining frames. Note that the
4195 * last frame contains no chain element. The remaining
4196 * frames go into the mpt SGL buffer allocated on the fly,
4197 * not immediately following the main message frame, as in
4198 * Gen1.
4199 * Some restrictions:
4200 * 1. For 64-bit DMA, the simple element and chain element
4201 * are both of 3 double-words (12 bytes) in size, even
4202 * though all frames are stored in the first 4G of mem
4203 * range and the higher 32-bits of the address are always 0.
4204 * 2. On some controllers (like the 1064/1068), a frame can
4205 * hold SGL elements with the last 1 or 2 double-words
4206 * (4 or 8 bytes) un-used. On these controllers, we should
4207 * recognize that there's not enough room for another SGL
4208 * element and move the sge pointer to the next frame.
4209 */
4210 int i, j, k, l, frames, sgemax;
4211 int temp;
4212 uint8_t chainflags;
4213 uint16_t chainlength;
4214 mptsas_cache_frames_t *p;
4215
4216 /*
4217 * Sgemax is the number of SGE's that will fit
4218 * each extra frame and frames is total
4219 * number of frames we'll need. 1 sge entry per
4220 * frame is reseverd for the chain element thus the -1 below.
4221 */
4222 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_SGE_SIMPLE64))
4223 - 1);
4224 temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax;
4225
4226 /*
4227 * A little check to see if we need to round up the number
4228 * of frames we need
4229 */
4230 if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp *
4231 sgemax) > 1) {
4232 frames = (temp + 1);
4233 } else {
4234 frames = temp;
4235 }
4236 dmap = cmd->cmd_sg;
4237 sge = (pMpi2SGESimple64_t)(&frame->SGL);
4238
4239 /*
4240 * First fill in the main frame
4241 */
4242 for (j = 1; j < MPTSAS_MAX_FRAME_SGES64(mpt); j++) {
4243 ddi_put32(acc_hdl, &sge->Address.Low,
4244 dmap->addr.address64.Low);
4245 ddi_put32(acc_hdl, &sge->Address.High,
4246 dmap->addr.address64.High);
4247 ddi_put32(acc_hdl, &sge->FlagsLength, dmap->count);
4248 flags = ddi_get32(acc_hdl, &sge->FlagsLength);
4249 flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4250 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4251 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4252 MPI2_SGE_FLAGS_SHIFT);
4253
4254 /*
4255 * If this is the last SGE of this frame
4256 * we set the end of list flag
4257 */
4258 if (j == (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) {
4259 flags |= ((uint32_t)
4260 (MPI2_SGE_FLAGS_LAST_ELEMENT) <<
4261 MPI2_SGE_FLAGS_SHIFT);
4262 }
4263 if (cmd->cmd_flags & CFLAG_DMASEND) {
4264 flags |=
4265 (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4266 MPI2_SGE_FLAGS_SHIFT);
4267 } else {
4268 flags |=
4269 (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4270 MPI2_SGE_FLAGS_SHIFT);
4271 }
4272 ddi_put32(acc_hdl, &sge->FlagsLength, flags);
4273 dmap++;
4274 sge++;
4275 }
4276
4277 /*
4278 * Fill in the chain element in the main frame.
4279 * About calculation on ChainOffset:
4280 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes)
4281 * in the end reserved for SGL element storage
4282 * (MPI2_SGE_IO_UNION); we should count it in our
4283 * calculation. See its definition in the header file.
4284 * 2. Constant j is the counter of the current SGL element
4285 * that will be processed, and (j - 1) is the number of
4286 * SGL elements that have been processed (stored in the
4287 * main frame).
4288 * 3. ChainOffset value should be in units of double-words (4
4289 * bytes) so the last value should be divided by 4.
4290 */
4291 ddi_put8(acc_hdl, &frame->ChainOffset,
4292 (sizeof (MPI2_SCSI_IO_REQUEST) -
4293 sizeof (MPI2_SGE_IO_UNION) +
4294 (j - 1) * sizeof (MPI2_SGE_SIMPLE64)) >> 2);
4295 sgechain = (pMpi2SGEChain64_t)sge;
4296 chainflags = (MPI2_SGE_FLAGS_CHAIN_ELEMENT |
4297 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4298 MPI2_SGE_FLAGS_64_BIT_ADDRESSING);
4299 ddi_put8(acc_hdl, &sgechain->Flags, chainflags);
4300
4301 /*
4302 * The size of the next frame is the accurate size of space
4303 * (in bytes) used to store the SGL elements. j is the counter
4304 * of SGL elements. (j - 1) is the number of SGL elements that
4305 * have been processed (stored in frames).
4306 */
4307 if (frames >= 2) {
4308 chainlength = mpt->m_req_frame_size /
4309 sizeof (MPI2_SGE_SIMPLE64) *
4310 sizeof (MPI2_SGE_SIMPLE64);
4311 } else {
4312 chainlength = ((cookiec - (j - 1)) *
4313 sizeof (MPI2_SGE_SIMPLE64));
4314 }
4315
4316 p = cmd->cmd_extra_frames;
4317
4318 ddi_put16(acc_hdl, &sgechain->Length, chainlength);
4319 ddi_put32(acc_hdl, &sgechain->Address.Low,
4320 p->m_phys_addr);
4321 /* SGL is allocated in the first 4G mem range */
4322 ddi_put32(acc_hdl, &sgechain->Address.High, 0);
4323
4324 /*
4325 * If there are more than 2 frames left we have to
4326 * fill in the next chain offset to the location of
4327 * the chain element in the next frame.
4328 * sgemax is the number of simple elements in an extra
4329 * frame. Note that the value NextChainOffset should be
4330 * in double-words (4 bytes).
4331 */
4332 if (frames >= 2) {
4333 ddi_put8(acc_hdl, &sgechain->NextChainOffset,
4334 (sgemax * sizeof (MPI2_SGE_SIMPLE64)) >> 2);
4335 } else {
4336 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 0);
4337 }
4338
4339 /*
4340 * Jump to next frame;
4341 * Starting here, chain buffers go into the per command SGL.
4342 * This buffer is allocated when chain buffers are needed.
4343 */
4344 sge = (pMpi2SGESimple64_t)p->m_frames_addr;
4345 i = cookiec;
4346
4347 /*
4348 * Start filling in frames with SGE's. If we
4349 * reach the end of frame and still have SGE's
4350 * to fill we need to add a chain element and
4351 * use another frame. j will be our counter
4352 * for what cookie we are at and i will be
4353 * the total cookiec. k is the current frame
4354 */
4355 for (k = 1; k <= frames; k++) {
4356 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) {
4357
4358 /*
4359 * If we have reached the end of frame
4360 * and we have more SGE's to fill in
4361 * we have to fill the final entry
4362 * with a chain element and then
4363 * continue to the next frame
4364 */
4365 if ((l == (sgemax + 1)) && (k != frames)) {
4366 sgechain = (pMpi2SGEChain64_t)sge;
4367 j--;
4368 chainflags = (
4369 MPI2_SGE_FLAGS_CHAIN_ELEMENT |
4370 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4371 MPI2_SGE_FLAGS_64_BIT_ADDRESSING);
4372 ddi_put8(p->m_acc_hdl,
4373 &sgechain->Flags, chainflags);
4374 /*
4375 * k is the frame counter and (k + 1)
4376 * is the number of the next frame.
4377 * Note that frames are in contiguous
4378 * memory space.
4379 */
4380 ddi_put32(p->m_acc_hdl,
4381 &sgechain->Address.Low,
4382 (p->m_phys_addr +
4383 (mpt->m_req_frame_size * k)));
4384 ddi_put32(p->m_acc_hdl,
4385 &sgechain->Address.High, 0);
4386
4387 /*
4388 * If there are more than 2 frames left
4389 * we have to next chain offset to
4390 * the location of the chain element
4391 * in the next frame and fill in the
4392 * length of the next chain
4393 */
4394 if ((frames - k) >= 2) {
4395 ddi_put8(p->m_acc_hdl,
4396 &sgechain->NextChainOffset,
4397 (sgemax *
4398 sizeof (MPI2_SGE_SIMPLE64))
4399 >> 2);
4400 ddi_put16(p->m_acc_hdl,
4401 &sgechain->Length,
4402 mpt->m_req_frame_size /
4403 sizeof (MPI2_SGE_SIMPLE64) *
4404 sizeof (MPI2_SGE_SIMPLE64));
4405 } else {
4406 /*
4407 * This is the last frame. Set
4408 * the NextChainOffset to 0 and
4409 * Length is the total size of
4410 * all remaining simple elements
4411 */
4412 ddi_put8(p->m_acc_hdl,
4413 &sgechain->NextChainOffset,
4414 0);
4415 ddi_put16(p->m_acc_hdl,
4416 &sgechain->Length,
4417 (cookiec - j) *
4418 sizeof (MPI2_SGE_SIMPLE64));
4419 }
4420
4421 /* Jump to the next frame */
4422 sge = (pMpi2SGESimple64_t)
4423 ((char *)p->m_frames_addr +
4424 (int)mpt->m_req_frame_size * k);
4425
4426 continue;
4427 }
4428
4429 ddi_put32(p->m_acc_hdl,
4430 &sge->Address.Low,
4431 dmap->addr.address64.Low);
4432 ddi_put32(p->m_acc_hdl,
4433 &sge->Address.High,
4434 dmap->addr.address64.High);
4435 ddi_put32(p->m_acc_hdl,
4436 &sge->FlagsLength, dmap->count);
4437 flags = ddi_get32(p->m_acc_hdl,
4438 &sge->FlagsLength);
4439 flags |= ((uint32_t)(
4440 MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4441 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4442 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4443 MPI2_SGE_FLAGS_SHIFT);
4444
4445 /*
4446 * If we are at the end of the frame and
4447 * there is another frame to fill in
4448 * we set the last simple element as last
4449 * element
4450 */
4451 if ((l == sgemax) && (k != frames)) {
4452 flags |= ((uint32_t)
4453 (MPI2_SGE_FLAGS_LAST_ELEMENT) <<
4454 MPI2_SGE_FLAGS_SHIFT);
4455 }
4456
4457 /*
4458 * If this is the final cookie we
4459 * indicate it by setting the flags
4460 */
4461 if (j == i) {
4462 flags |= ((uint32_t)
4463 (MPI2_SGE_FLAGS_LAST_ELEMENT |
4464 MPI2_SGE_FLAGS_END_OF_BUFFER |
4465 MPI2_SGE_FLAGS_END_OF_LIST) <<
4466 MPI2_SGE_FLAGS_SHIFT);
4467 }
4468 if (cmd->cmd_flags & CFLAG_DMASEND) {
4469 flags |=
4470 (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4471 MPI2_SGE_FLAGS_SHIFT);
4472 } else {
4473 flags |=
4474 (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4475 MPI2_SGE_FLAGS_SHIFT);
4476 }
4477 ddi_put32(p->m_acc_hdl,
4478 &sge->FlagsLength, flags);
4479 dmap++;
4480 sge++;
4481 }
4482 }
4483
4484 /*
4485 * Sync DMA with the chain buffers that were just created
4486 */
4487 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
4488 }
4489 }
4490
4491 /*
4492 * Interrupt handling
4493 * Utility routine. Poll for status of a command sent to HBA
4494 * without interrupts (a FLAG_NOINTR command).
4495 */
4496 int
4497 mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime)
4498 {
4499 int rval = TRUE;
4500
4501 NDBG5(("mptsas_poll: cmd=0x%p", (void *)poll_cmd));
4502
4503 if ((poll_cmd->cmd_flags & CFLAG_TM_CMD) == 0) {
4504 mptsas_restart_hba(mpt);
4505 }
4506
4507 /*
4508 * Wait, using drv_usecwait(), long enough for the command to
4509 * reasonably return from the target if the target isn't
4510 * "dead". A polled command may well be sent from scsi_poll, and
4511 * there are retries built in to scsi_poll if the transport
4512 * accepted the packet (TRAN_ACCEPT). scsi_poll waits 1 second
4513 * and retries the transport up to scsi_poll_busycnt times
4514 * (currently 60) if
4515 * 1. pkt_reason is CMD_INCOMPLETE and pkt_state is 0, or
4516 * 2. pkt_reason is CMD_CMPLT and *pkt_scbp has STATUS_BUSY
4517 *
4518 * limit the waiting to avoid a hang in the event that the
4519 * cmd never gets started but we are still receiving interrupts
4520 */
4521 while (!(poll_cmd->cmd_flags & CFLAG_FINISHED)) {
4522 if (mptsas_wait_intr(mpt, polltime) == FALSE) {
4523 NDBG5(("mptsas_poll: command incomplete"));
4524 rval = FALSE;
4525 break;
4526 }
4527 }
4528
4529 if (rval == FALSE) {
4530
4531 /*
4532 * this isn't supposed to happen, the hba must be wedged
4533 * Mark this cmd as a timeout.
4534 */
4535 mptsas_set_pkt_reason(mpt, poll_cmd, CMD_TIMEOUT,
4536 (STAT_TIMEOUT|STAT_ABORTED));
4537
4538 if (poll_cmd->cmd_queued == FALSE) {
4539
4540 NDBG5(("mptsas_poll: not on waitq"));
4541
4542 poll_cmd->cmd_pkt->pkt_state |=
4543 (STATE_GOT_BUS|STATE_GOT_TARGET|STATE_SENT_CMD);
4544 } else {
4545
4546 /* find and remove it from the waitq */
4547 NDBG5(("mptsas_poll: delete from waitq"));
4548 mptsas_waitq_delete(mpt, poll_cmd);
4549 }
4550
4551 }
4552 mptsas_fma_check(mpt, poll_cmd);
4553 NDBG5(("mptsas_poll: done"));
4554 return (rval);
4555 }
4556
4557 /*
4558 * Used for polling cmds and TM function
4559 */
4560 static int
4561 mptsas_wait_intr(mptsas_t *mpt, int polltime)
4562 {
4563 int cnt;
4564 pMpi2ReplyDescriptorsUnion_t reply_desc_union;
4565 uint32_t int_mask;
4566
4567 NDBG5(("mptsas_wait_intr"));
4568
4569 mpt->m_polled_intr = 1;
4570
4571 /*
4572 * Get the current interrupt mask and disable interrupts. When
4573 * re-enabling ints, set mask to saved value.
4574 */
4575 int_mask = ddi_get32(mpt->m_datap, &mpt->m_reg->HostInterruptMask);
4576 MPTSAS_DISABLE_INTR(mpt);
4577
4578 /*
4579 * Keep polling for at least (polltime * 1000) seconds
4580 */
4581 for (cnt = 0; cnt < polltime; cnt++) {
4582 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
4583 DDI_DMA_SYNC_FORCPU);
4584
4585 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t)
4586 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index);
4587
4588 if (ddi_get32(mpt->m_acc_post_queue_hdl,
4589 &reply_desc_union->Words.Low) == 0xFFFFFFFF ||
4590 ddi_get32(mpt->m_acc_post_queue_hdl,
4591 &reply_desc_union->Words.High) == 0xFFFFFFFF) {
4592 drv_usecwait(1000);
4593 continue;
4594 }
4595
4596 /*
4597 * The reply is valid, process it according to its
4598 * type.
4599 */
4600 mptsas_process_intr(mpt, reply_desc_union);
4601
4602 if (++mpt->m_post_index == mpt->m_post_queue_depth) {
4603 mpt->m_post_index = 0;
4604 }
4605
4606 /*
4607 * Update the global reply index
4608 */
4609 ddi_put32(mpt->m_datap,
4610 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index);
4611 mpt->m_polled_intr = 0;
4612
4613 /*
4614 * Re-enable interrupts and quit.
4615 */
4616 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask,
4617 int_mask);
4618 return (TRUE);
4619
4620 }
4621
4622 /*
4623 * Clear polling flag, re-enable interrupts and quit.
4624 */
4625 mpt->m_polled_intr = 0;
4626 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, int_mask);
4627 return (FALSE);
4628 }
4629
4630 static void
4631 mptsas_handle_scsi_io_success(mptsas_t *mpt,
4632 pMpi2ReplyDescriptorsUnion_t reply_desc)
4633 {
4634 pMpi2SCSIIOSuccessReplyDescriptor_t scsi_io_success;
4635 uint16_t SMID;
4636 mptsas_slots_t *slots = mpt->m_active;
4637 mptsas_cmd_t *cmd = NULL;
4638 struct scsi_pkt *pkt;
4639
4640 ASSERT(mutex_owned(&mpt->m_mutex));
4641
4642 scsi_io_success = (pMpi2SCSIIOSuccessReplyDescriptor_t)reply_desc;
4643 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &scsi_io_success->SMID);
4644
4645 /*
4646 * This is a success reply so just complete the IO. First, do a sanity
4647 * check on the SMID. The final slot is used for TM requests, which
4648 * would not come into this reply handler.
4649 */
4650 if ((SMID == 0) || (SMID > slots->m_n_slots)) {
4651 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of %d\n",
4652 SMID);
4653 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
4654 return;
4655 }
4656
4657 cmd = slots->m_slot[SMID];
4658
4659 /*
4660 * print warning and return if the slot is empty
4661 */
4662 if (cmd == NULL) {
4663 mptsas_log(mpt, CE_WARN, "?NULL command for successful SCSI IO "
4664 "in slot %d", SMID);
4665 return;
4666 }
4667
4668 pkt = CMD2PKT(cmd);
4669 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | STATE_SENT_CMD |
4670 STATE_GOT_STATUS);
4671 if (cmd->cmd_flags & CFLAG_DMAVALID) {
4672 pkt->pkt_state |= STATE_XFERRED_DATA;
4673 }
4674 pkt->pkt_resid = 0;
4675
4676 if (cmd->cmd_flags & CFLAG_PASSTHRU) {
4677 cmd->cmd_flags |= CFLAG_FINISHED;
4678 cv_broadcast(&mpt->m_passthru_cv);
4679 return;
4680 } else {
4681 mptsas_remove_cmd(mpt, cmd);
4682 }
4683
4684 if (cmd->cmd_flags & CFLAG_RETRY) {
4685 /*
4686 * The target returned QFULL or busy, do not add tihs
4687 * pkt to the doneq since the hba will retry
4688 * this cmd.
4689 *
4690 * The pkt has already been resubmitted in
4691 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error().
4692 * Remove this cmd_flag here.
4693 */
4694 cmd->cmd_flags &= ~CFLAG_RETRY;
4695 } else {
4696 mptsas_doneq_add(mpt, cmd);
4697 }
4698 }
4699
4700 static void
4701 mptsas_handle_address_reply(mptsas_t *mpt,
4702 pMpi2ReplyDescriptorsUnion_t reply_desc)
4703 {
4704 pMpi2AddressReplyDescriptor_t address_reply;
4705 pMPI2DefaultReply_t reply;
4706 mptsas_fw_diagnostic_buffer_t *pBuffer;
4707 uint32_t reply_addr;
4708 uint16_t SMID, iocstatus;
4709 mptsas_slots_t *slots = mpt->m_active;
4710 mptsas_cmd_t *cmd = NULL;
4711 uint8_t function, buffer_type;
4712 m_replyh_arg_t *args;
4713 int reply_frame_no;
4714
4715 ASSERT(mutex_owned(&mpt->m_mutex));
4716
4717 address_reply = (pMpi2AddressReplyDescriptor_t)reply_desc;
4718 reply_addr = ddi_get32(mpt->m_acc_post_queue_hdl,
4719 &address_reply->ReplyFrameAddress);
4720 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &address_reply->SMID);
4721
4722 /*
4723 * If reply frame is not in the proper range we should ignore this
4724 * message and exit the interrupt handler.
4725 */
4726 if ((reply_addr < mpt->m_reply_frame_dma_addr) ||
4727 (reply_addr >= (mpt->m_reply_frame_dma_addr +
4728 (mpt->m_reply_frame_size * mpt->m_max_replies))) ||
4729 ((reply_addr - mpt->m_reply_frame_dma_addr) %
4730 mpt->m_reply_frame_size != 0)) {
4731 mptsas_log(mpt, CE_WARN, "?Received invalid reply frame "
4732 "address 0x%x\n", reply_addr);
4733 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
4734 return;
4735 }
4736
4737 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
4738 DDI_DMA_SYNC_FORCPU);
4739 reply = (pMPI2DefaultReply_t)(mpt->m_reply_frame + (reply_addr -
4740 mpt->m_reply_frame_dma_addr));
4741 function = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->Function);
4742
4743 /*
4744 * don't get slot information and command for events since these values
4745 * don't exist
4746 */
4747 if ((function != MPI2_FUNCTION_EVENT_NOTIFICATION) &&
4748 (function != MPI2_FUNCTION_DIAG_BUFFER_POST)) {
4749 /*
4750 * This could be a TM reply, which use the last allocated SMID,
4751 * so allow for that.
4752 */
4753 if ((SMID == 0) || (SMID > (slots->m_n_slots + 1))) {
4754 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of "
4755 "%d\n", SMID);
4756 ddi_fm_service_impact(mpt->m_dip,
4757 DDI_SERVICE_UNAFFECTED);
4758 return;
4759 }
4760
4761 cmd = slots->m_slot[SMID];
4762
4763 /*
4764 * print warning and return if the slot is empty
4765 */
4766 if (cmd == NULL) {
4767 mptsas_log(mpt, CE_WARN, "?NULL command for address "
4768 "reply in slot %d", SMID);
4769 return;
4770 }
4771 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
4772 (cmd->cmd_flags & CFLAG_CONFIG) ||
4773 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
4774 cmd->cmd_rfm = reply_addr;
4775 cmd->cmd_flags |= CFLAG_FINISHED;
4776 cv_broadcast(&mpt->m_passthru_cv);
4777 cv_broadcast(&mpt->m_config_cv);
4778 cv_broadcast(&mpt->m_fw_diag_cv);
4779 return;
4780 } else if (!(cmd->cmd_flags & CFLAG_FW_CMD)) {
4781 mptsas_remove_cmd(mpt, cmd);
4782 }
4783 NDBG31(("\t\tmptsas_process_intr: slot=%d", SMID));
4784 }
4785 /*
4786 * Depending on the function, we need to handle
4787 * the reply frame (and cmd) differently.
4788 */
4789 switch (function) {
4790 case MPI2_FUNCTION_SCSI_IO_REQUEST:
4791 mptsas_check_scsi_io_error(mpt, (pMpi2SCSIIOReply_t)reply, cmd);
4792 break;
4793 case MPI2_FUNCTION_SCSI_TASK_MGMT:
4794 cmd->cmd_rfm = reply_addr;
4795 mptsas_check_task_mgt(mpt, (pMpi2SCSIManagementReply_t)reply,
4796 cmd);
4797 break;
4798 case MPI2_FUNCTION_FW_DOWNLOAD:
4799 cmd->cmd_flags |= CFLAG_FINISHED;
4800 cv_signal(&mpt->m_fw_cv);
4801 break;
4802 case MPI2_FUNCTION_EVENT_NOTIFICATION:
4803 reply_frame_no = (reply_addr - mpt->m_reply_frame_dma_addr) /
4804 mpt->m_reply_frame_size;
4805 args = &mpt->m_replyh_args[reply_frame_no];
4806 args->mpt = (void *)mpt;
4807 args->rfm = reply_addr;
4808
4809 /*
4810 * Record the event if its type is enabled in
4811 * this mpt instance by ioctl.
4812 */
4813 mptsas_record_event(args);
4814
4815 /*
4816 * Handle time critical events
4817 * NOT_RESPONDING/ADDED only now
4818 */
4819 if (mptsas_handle_event_sync(args) == DDI_SUCCESS) {
4820 /*
4821 * Would not return main process,
4822 * just let taskq resolve ack action
4823 * and ack would be sent in taskq thread
4824 */
4825 NDBG20(("send mptsas_handle_event_sync success"));
4826 }
4827
4828 if (mpt->m_in_reset) {
4829 NDBG20(("dropping event received during reset"));
4830 return;
4831 }
4832
4833 if ((ddi_taskq_dispatch(mpt->m_event_taskq, mptsas_handle_event,
4834 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) {
4835 mptsas_log(mpt, CE_WARN, "No memory available"
4836 "for dispatch taskq");
4837 /*
4838 * Return the reply frame to the free queue.
4839 */
4840 ddi_put32(mpt->m_acc_free_queue_hdl,
4841 &((uint32_t *)(void *)
4842 mpt->m_free_queue)[mpt->m_free_index], reply_addr);
4843 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
4844 DDI_DMA_SYNC_FORDEV);
4845 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
4846 mpt->m_free_index = 0;
4847 }
4848
4849 ddi_put32(mpt->m_datap,
4850 &mpt->m_reg->ReplyFreeHostIndex, mpt->m_free_index);
4851 }
4852 return;
4853 case MPI2_FUNCTION_DIAG_BUFFER_POST:
4854 /*
4855 * If SMID is 0, this implies that the reply is due to a
4856 * release function with a status that the buffer has been
4857 * released. Set the buffer flags accordingly.
4858 */
4859 if (SMID == 0) {
4860 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
4861 &reply->IOCStatus);
4862 buffer_type = ddi_get8(mpt->m_acc_reply_frame_hdl,
4863 &(((pMpi2DiagBufferPostReply_t)reply)->BufferType));
4864 if (iocstatus == MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED) {
4865 pBuffer =
4866 &mpt->m_fw_diag_buffer_list[buffer_type];
4867 pBuffer->valid_data = TRUE;
4868 pBuffer->owned_by_firmware = FALSE;
4869 pBuffer->immediate = FALSE;
4870 }
4871 } else {
4872 /*
4873 * Normal handling of diag post reply with SMID.
4874 */
4875 cmd = slots->m_slot[SMID];
4876
4877 /*
4878 * print warning and return if the slot is empty
4879 */
4880 if (cmd == NULL) {
4881 mptsas_log(mpt, CE_WARN, "?NULL command for "
4882 "address reply in slot %d", SMID);
4883 return;
4884 }
4885 cmd->cmd_rfm = reply_addr;
4886 cmd->cmd_flags |= CFLAG_FINISHED;
4887 cv_broadcast(&mpt->m_fw_diag_cv);
4888 }
4889 return;
4890 default:
4891 mptsas_log(mpt, CE_WARN, "Unknown function 0x%x ", function);
4892 break;
4893 }
4894
4895 /*
4896 * Return the reply frame to the free queue.
4897 */
4898 ddi_put32(mpt->m_acc_free_queue_hdl,
4899 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
4900 reply_addr);
4901 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
4902 DDI_DMA_SYNC_FORDEV);
4903 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
4904 mpt->m_free_index = 0;
4905 }
4906 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
4907 mpt->m_free_index);
4908
4909 if (cmd->cmd_flags & CFLAG_FW_CMD)
4910 return;
4911
4912 if (cmd->cmd_flags & CFLAG_RETRY) {
4913 /*
4914 * The target returned QFULL or busy, do not add tihs
4915 * pkt to the doneq since the hba will retry
4916 * this cmd.
4917 *
4918 * The pkt has already been resubmitted in
4919 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error().
4920 * Remove this cmd_flag here.
4921 */
4922 cmd->cmd_flags &= ~CFLAG_RETRY;
4923 } else {
4924 mptsas_doneq_add(mpt, cmd);
4925 }
4926 }
4927
4928 static void
4929 mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply,
4930 mptsas_cmd_t *cmd)
4931 {
4932 uint8_t scsi_status, scsi_state;
4933 uint16_t ioc_status;
4934 uint32_t xferred, sensecount, responsedata, loginfo = 0;
4935 struct scsi_pkt *pkt;
4936 struct scsi_arq_status *arqstat;
4937 struct buf *bp;
4938 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
4939 uint8_t *sensedata = NULL;
4940
4941 if ((cmd->cmd_flags & (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) ==
4942 (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) {
4943 bp = cmd->cmd_ext_arq_buf;
4944 } else {
4945 bp = cmd->cmd_arq_buf;
4946 }
4947
4948 scsi_status = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIStatus);
4949 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus);
4950 scsi_state = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIState);
4951 xferred = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->TransferCount);
4952 sensecount = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->SenseCount);
4953 responsedata = ddi_get32(mpt->m_acc_reply_frame_hdl,
4954 &reply->ResponseInfo);
4955
4956 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
4957 loginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
4958 &reply->IOCLogInfo);
4959 mptsas_log(mpt, CE_NOTE,
4960 "?Log info 0x%x received for target %d.\n"
4961 "\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x",
4962 loginfo, Tgt(cmd), scsi_status, ioc_status,
4963 scsi_state);
4964 }
4965
4966 NDBG31(("\t\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x",
4967 scsi_status, ioc_status, scsi_state));
4968
4969 pkt = CMD2PKT(cmd);
4970 *(pkt->pkt_scbp) = scsi_status;
4971
4972 if (loginfo == 0x31170000) {
4973 /*
4974 * if loginfo PL_LOGINFO_CODE_IO_DEVICE_MISSING_DELAY_RETRY
4975 * 0x31170000 comes, that means the device missing delay
4976 * is in progressing, the command need retry later.
4977 */
4978 *(pkt->pkt_scbp) = STATUS_BUSY;
4979 return;
4980 }
4981
4982 if ((scsi_state & MPI2_SCSI_STATE_NO_SCSI_STATUS) &&
4983 ((ioc_status & MPI2_IOCSTATUS_MASK) ==
4984 MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE)) {
4985 pkt->pkt_reason = CMD_INCOMPLETE;
4986 pkt->pkt_state |= STATE_GOT_BUS;
4987 if (ptgt->m_reset_delay == 0) {
4988 mptsas_set_throttle(mpt, ptgt,
4989 DRAIN_THROTTLE);
4990 }
4991 return;
4992 }
4993
4994 if (scsi_state & MPI2_SCSI_STATE_RESPONSE_INFO_VALID) {
4995 responsedata &= 0x000000FF;
4996 if (responsedata & MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF) {
4997 mptsas_log(mpt, CE_NOTE, "Do not support the TLR\n");
4998 pkt->pkt_reason = CMD_TLR_OFF;
4999 return;
5000 }
5001 }
5002
5003
5004 switch (scsi_status) {
5005 case MPI2_SCSI_STATUS_CHECK_CONDITION:
5006 pkt->pkt_resid = (cmd->cmd_dmacount - xferred);
5007 arqstat = (void*)(pkt->pkt_scbp);
5008 arqstat->sts_rqpkt_status = *((struct scsi_status *)
5009 (pkt->pkt_scbp));
5010 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET |
5011 STATE_SENT_CMD | STATE_GOT_STATUS | STATE_ARQ_DONE);
5012 if (cmd->cmd_flags & CFLAG_XARQ) {
5013 pkt->pkt_state |= STATE_XARQ_DONE;
5014 }
5015 if (pkt->pkt_resid != cmd->cmd_dmacount) {
5016 pkt->pkt_state |= STATE_XFERRED_DATA;
5017 }
5018 arqstat->sts_rqpkt_reason = pkt->pkt_reason;
5019 arqstat->sts_rqpkt_state = pkt->pkt_state;
5020 arqstat->sts_rqpkt_state |= STATE_XFERRED_DATA;
5021 arqstat->sts_rqpkt_statistics = pkt->pkt_statistics;
5022 sensedata = (uint8_t *)&arqstat->sts_sensedata;
5023
5024 bcopy((uchar_t *)bp->b_un.b_addr, sensedata,
5025 ((cmd->cmd_rqslen >= sensecount) ? sensecount :
5026 cmd->cmd_rqslen));
5027 arqstat->sts_rqpkt_resid = (cmd->cmd_rqslen - sensecount);
5028 cmd->cmd_flags |= CFLAG_CMDARQ;
5029 /*
5030 * Set proper status for pkt if autosense was valid
5031 */
5032 if (scsi_state & MPI2_SCSI_STATE_AUTOSENSE_VALID) {
5033 struct scsi_status zero_status = { 0 };
5034 arqstat->sts_rqpkt_status = zero_status;
5035 }
5036
5037 /*
5038 * ASC=0x47 is parity error
5039 * ASC=0x48 is initiator detected error received
5040 */
5041 if ((scsi_sense_key(sensedata) == KEY_ABORTED_COMMAND) &&
5042 ((scsi_sense_asc(sensedata) == 0x47) ||
5043 (scsi_sense_asc(sensedata) == 0x48))) {
5044 mptsas_log(mpt, CE_NOTE, "Aborted_command!");
5045 }
5046
5047 /*
5048 * ASC/ASCQ=0x3F/0x0E means report_luns data changed
5049 * ASC/ASCQ=0x25/0x00 means invalid lun
5050 */
5051 if (((scsi_sense_key(sensedata) == KEY_UNIT_ATTENTION) &&
5052 (scsi_sense_asc(sensedata) == 0x3F) &&
5053 (scsi_sense_ascq(sensedata) == 0x0E)) ||
5054 ((scsi_sense_key(sensedata) == KEY_ILLEGAL_REQUEST) &&
5055 (scsi_sense_asc(sensedata) == 0x25) &&
5056 (scsi_sense_ascq(sensedata) == 0x00))) {
5057 mptsas_topo_change_list_t *topo_node = NULL;
5058
5059 topo_node = kmem_zalloc(
5060 sizeof (mptsas_topo_change_list_t),
5061 KM_NOSLEEP);
5062 if (topo_node == NULL) {
5063 mptsas_log(mpt, CE_NOTE, "No memory"
5064 "resource for handle SAS dynamic"
5065 "reconfigure.\n");
5066 break;
5067 }
5068 topo_node->mpt = mpt;
5069 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_TARGET;
5070 topo_node->un.phymask = ptgt->m_phymask;
5071 topo_node->devhdl = ptgt->m_devhdl;
5072 topo_node->object = (void *)ptgt;
5073 topo_node->flags = MPTSAS_TOPO_FLAG_LUN_ASSOCIATED;
5074
5075 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
5076 mptsas_handle_dr,
5077 (void *)topo_node,
5078 DDI_NOSLEEP)) != DDI_SUCCESS) {
5079 mptsas_log(mpt, CE_NOTE, "mptsas start taskq"
5080 "for handle SAS dynamic reconfigure"
5081 "failed. \n");
5082 }
5083 }
5084 break;
5085 case MPI2_SCSI_STATUS_GOOD:
5086 switch (ioc_status & MPI2_IOCSTATUS_MASK) {
5087 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
5088 pkt->pkt_reason = CMD_DEV_GONE;
5089 pkt->pkt_state |= STATE_GOT_BUS;
5090 if (ptgt->m_reset_delay == 0) {
5091 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5092 }
5093 NDBG31(("lost disk for target%d, command:%x",
5094 Tgt(cmd), pkt->pkt_cdbp[0]));
5095 break;
5096 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
5097 NDBG31(("data overrun: xferred=%d", xferred));
5098 NDBG31(("dmacount=%d", cmd->cmd_dmacount));
5099 pkt->pkt_reason = CMD_DATA_OVR;
5100 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET
5101 | STATE_SENT_CMD | STATE_GOT_STATUS
5102 | STATE_XFERRED_DATA);
5103 pkt->pkt_resid = 0;
5104 break;
5105 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
5106 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
5107 NDBG31(("data underrun: xferred=%d", xferred));
5108 NDBG31(("dmacount=%d", cmd->cmd_dmacount));
5109 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET
5110 | STATE_SENT_CMD | STATE_GOT_STATUS);
5111 pkt->pkt_resid = (cmd->cmd_dmacount - xferred);
5112 if (pkt->pkt_resid != cmd->cmd_dmacount) {
5113 pkt->pkt_state |= STATE_XFERRED_DATA;
5114 }
5115 break;
5116 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
5117 mptsas_set_pkt_reason(mpt,
5118 cmd, CMD_RESET, STAT_BUS_RESET);
5119 break;
5120 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
5121 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
5122 mptsas_set_pkt_reason(mpt,
5123 cmd, CMD_RESET, STAT_DEV_RESET);
5124 break;
5125 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
5126 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
5127 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET);
5128 mptsas_set_pkt_reason(mpt,
5129 cmd, CMD_TERMINATED, STAT_TERMINATED);
5130 break;
5131 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
5132 case MPI2_IOCSTATUS_BUSY:
5133 /*
5134 * set throttles to drain
5135 */
5136 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
5137 &mpt->m_active->m_tgttbl, MPTSAS_HASH_FIRST);
5138 while (ptgt != NULL) {
5139 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5140
5141 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
5142 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
5143 }
5144
5145 /*
5146 * retry command
5147 */
5148 cmd->cmd_flags |= CFLAG_RETRY;
5149 cmd->cmd_pkt_flags |= FLAG_HEAD;
5150
5151 (void) mptsas_accept_pkt(mpt, cmd);
5152 break;
5153 default:
5154 mptsas_log(mpt, CE_WARN,
5155 "unknown ioc_status = %x\n", ioc_status);
5156 mptsas_log(mpt, CE_CONT, "scsi_state = %x, transfer "
5157 "count = %x, scsi_status = %x", scsi_state,
5158 xferred, scsi_status);
5159 break;
5160 }
5161 break;
5162 case MPI2_SCSI_STATUS_TASK_SET_FULL:
5163 mptsas_handle_qfull(mpt, cmd);
5164 break;
5165 case MPI2_SCSI_STATUS_BUSY:
5166 NDBG31(("scsi_status busy received"));
5167 break;
5168 case MPI2_SCSI_STATUS_RESERVATION_CONFLICT:
5169 NDBG31(("scsi_status reservation conflict received"));
5170 break;
5171 default:
5172 mptsas_log(mpt, CE_WARN, "scsi_status=%x, ioc_status=%x\n",
5173 scsi_status, ioc_status);
5174 mptsas_log(mpt, CE_WARN,
5175 "mptsas_process_intr: invalid scsi status\n");
5176 break;
5177 }
5178 }
5179
5180 static void
5181 mptsas_check_task_mgt(mptsas_t *mpt, pMpi2SCSIManagementReply_t reply,
5182 mptsas_cmd_t *cmd)
5183 {
5184 uint8_t task_type;
5185 uint16_t ioc_status;
5186 uint32_t log_info;
5187 uint16_t dev_handle;
5188 struct scsi_pkt *pkt = CMD2PKT(cmd);
5189
5190 task_type = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->TaskType);
5191 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus);
5192 log_info = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->IOCLogInfo);
5193 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->DevHandle);
5194
5195 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5196 mptsas_log(mpt, CE_WARN, "mptsas_check_task_mgt: Task 0x%x "
5197 "failed. IOCStatus=0x%x IOCLogInfo=0x%x target=%d\n",
5198 task_type, ioc_status, log_info, dev_handle);
5199 pkt->pkt_reason = CMD_INCOMPLETE;
5200 return;
5201 }
5202
5203 switch (task_type) {
5204 case MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK:
5205 case MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET:
5206 case MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK:
5207 case MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA:
5208 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET:
5209 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_UNIT_ATTENTION:
5210 break;
5211 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
5212 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
5213 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
5214 /*
5215 * Check for invalid DevHandle of 0 in case application
5216 * sends bad command. DevHandle of 0 could cause problems.
5217 */
5218 if (dev_handle == 0) {
5219 mptsas_log(mpt, CE_WARN, "!Can't flush target with"
5220 " DevHandle of 0.");
5221 } else {
5222 mptsas_flush_target(mpt, dev_handle, Lun(cmd),
5223 task_type);
5224 }
5225 break;
5226 default:
5227 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.",
5228 task_type);
5229 mptsas_log(mpt, CE_WARN, "ioc status = %x", ioc_status);
5230 break;
5231 }
5232 }
5233
5234 static void
5235 mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg)
5236 {
5237 mptsas_t *mpt = arg->mpt;
5238 uint64_t t = arg->t;
5239 mptsas_cmd_t *cmd;
5240 struct scsi_pkt *pkt;
5241 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
5242
5243 mutex_enter(&item->mutex);
5244 while (item->flag & MPTSAS_DONEQ_THREAD_ACTIVE) {
5245 if (!item->doneq) {
5246 cv_wait(&item->cv, &item->mutex);
5247 }
5248 pkt = NULL;
5249 if ((cmd = mptsas_doneq_thread_rm(mpt, t)) != NULL) {
5250 cmd->cmd_flags |= CFLAG_COMPLETED;
5251 pkt = CMD2PKT(cmd);
5252 }
5253 mutex_exit(&item->mutex);
5254 if (pkt) {
5255 mptsas_pkt_comp(pkt, cmd);
5256 }
5257 mutex_enter(&item->mutex);
5258 }
5259 mutex_exit(&item->mutex);
5260 mutex_enter(&mpt->m_doneq_mutex);
5261 mpt->m_doneq_thread_n--;
5262 cv_broadcast(&mpt->m_doneq_thread_cv);
5263 mutex_exit(&mpt->m_doneq_mutex);
5264 }
5265
5266
5267 /*
5268 * mpt interrupt handler.
5269 */
5270 static uint_t
5271 mptsas_intr(caddr_t arg1, caddr_t arg2)
5272 {
5273 mptsas_t *mpt = (void *)arg1;
5274 pMpi2ReplyDescriptorsUnion_t reply_desc_union;
5275 uchar_t did_reply = FALSE;
5276
5277 NDBG1(("mptsas_intr: arg1 0x%p arg2 0x%p", (void *)arg1, (void *)arg2));
5278
5279 mutex_enter(&mpt->m_mutex);
5280
5281 /*
5282 * If interrupts are shared by two channels then check whether this
5283 * interrupt is genuinely for this channel by making sure first the
5284 * chip is in high power state.
5285 */
5286 if ((mpt->m_options & MPTSAS_OPT_PM) &&
5287 (mpt->m_power_level != PM_LEVEL_D0)) {
5288 mutex_exit(&mpt->m_mutex);
5289 return (DDI_INTR_UNCLAIMED);
5290 }
5291
5292 /*
5293 * If polling, interrupt was triggered by some shared interrupt because
5294 * IOC interrupts are disabled during polling, so polling routine will
5295 * handle any replies. Considering this, if polling is happening,
5296 * return with interrupt unclaimed.
5297 */
5298 if (mpt->m_polled_intr) {
5299 mutex_exit(&mpt->m_mutex);
5300 mptsas_log(mpt, CE_WARN, "mpt_sas: Unclaimed interrupt");
5301 return (DDI_INTR_UNCLAIMED);
5302 }
5303
5304 /*
5305 * Read the istat register.
5306 */
5307 if ((INTPENDING(mpt)) != 0) {
5308 /*
5309 * read fifo until empty.
5310 */
5311 #ifndef __lock_lint
5312 _NOTE(CONSTCOND)
5313 #endif
5314 while (TRUE) {
5315 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
5316 DDI_DMA_SYNC_FORCPU);
5317 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t)
5318 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index);
5319
5320 if (ddi_get32(mpt->m_acc_post_queue_hdl,
5321 &reply_desc_union->Words.Low) == 0xFFFFFFFF ||
5322 ddi_get32(mpt->m_acc_post_queue_hdl,
5323 &reply_desc_union->Words.High) == 0xFFFFFFFF) {
5324 break;
5325 }
5326
5327 /*
5328 * The reply is valid, process it according to its
5329 * type. Also, set a flag for updating the reply index
5330 * after they've all been processed.
5331 */
5332 did_reply = TRUE;
5333
5334 mptsas_process_intr(mpt, reply_desc_union);
5335
5336 /*
5337 * Increment post index and roll over if needed.
5338 */
5339 if (++mpt->m_post_index == mpt->m_post_queue_depth) {
5340 mpt->m_post_index = 0;
5341 }
5342 }
5343
5344 /*
5345 * Update the global reply index if at least one reply was
5346 * processed.
5347 */
5348 if (did_reply) {
5349 ddi_put32(mpt->m_datap,
5350 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index);
5351 }
5352 } else {
5353 mutex_exit(&mpt->m_mutex);
5354 return (DDI_INTR_UNCLAIMED);
5355 }
5356 NDBG1(("mptsas_intr complete"));
5357
5358 /*
5359 * If no helper threads are created, process the doneq in ISR. If
5360 * helpers are created, use the doneq length as a metric to measure the
5361 * load on the interrupt CPU. If it is long enough, which indicates the
5362 * load is heavy, then we deliver the IO completions to the helpers.
5363 * This measurement has some limitations, although it is simple and
5364 * straightforward and works well for most of the cases at present.
5365 */
5366 if (!mpt->m_doneq_thread_n ||
5367 (mpt->m_doneq_len <= mpt->m_doneq_length_threshold)) {
5368 mptsas_doneq_empty(mpt);
5369 } else {
5370 mptsas_deliver_doneq_thread(mpt);
5371 }
5372
5373 /*
5374 * If there are queued cmd, start them now.
5375 */
5376 if (mpt->m_waitq != NULL) {
5377 mptsas_restart_waitq(mpt);
5378 }
5379
5380 mutex_exit(&mpt->m_mutex);
5381 return (DDI_INTR_CLAIMED);
5382 }
5383
5384 static void
5385 mptsas_process_intr(mptsas_t *mpt,
5386 pMpi2ReplyDescriptorsUnion_t reply_desc_union)
5387 {
5388 uint8_t reply_type;
5389
5390 ASSERT(mutex_owned(&mpt->m_mutex));
5391
5392 /*
5393 * The reply is valid, process it according to its
5394 * type. Also, set a flag for updated the reply index
5395 * after they've all been processed.
5396 */
5397 reply_type = ddi_get8(mpt->m_acc_post_queue_hdl,
5398 &reply_desc_union->Default.ReplyFlags);
5399 reply_type &= MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
5400 if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
5401 mptsas_handle_scsi_io_success(mpt, reply_desc_union);
5402 } else if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
5403 mptsas_handle_address_reply(mpt, reply_desc_union);
5404 } else {
5405 mptsas_log(mpt, CE_WARN, "?Bad reply type %x", reply_type);
5406 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
5407 }
5408
5409 /*
5410 * Clear the reply descriptor for re-use and increment
5411 * index.
5412 */
5413 ddi_put64(mpt->m_acc_post_queue_hdl,
5414 &((uint64_t *)(void *)mpt->m_post_queue)[mpt->m_post_index],
5415 0xFFFFFFFFFFFFFFFF);
5416 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
5417 DDI_DMA_SYNC_FORDEV);
5418 }
5419
5420 /*
5421 * handle qfull condition
5422 */
5423 static void
5424 mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd)
5425 {
5426 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
5427
5428 if ((++cmd->cmd_qfull_retries > ptgt->m_qfull_retries) ||
5429 (ptgt->m_qfull_retries == 0)) {
5430 /*
5431 * We have exhausted the retries on QFULL, or,
5432 * the target driver has indicated that it
5433 * wants to handle QFULL itself by setting
5434 * qfull-retries capability to 0. In either case
5435 * we want the target driver's QFULL handling
5436 * to kick in. We do this by having pkt_reason
5437 * as CMD_CMPLT and pkt_scbp as STATUS_QFULL.
5438 */
5439 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5440 } else {
5441 if (ptgt->m_reset_delay == 0) {
5442 ptgt->m_t_throttle =
5443 max((ptgt->m_t_ncmds - 2), 0);
5444 }
5445
5446 cmd->cmd_pkt_flags |= FLAG_HEAD;
5447 cmd->cmd_flags &= ~(CFLAG_TRANFLAG);
5448 cmd->cmd_flags |= CFLAG_RETRY;
5449
5450 (void) mptsas_accept_pkt(mpt, cmd);
5451
5452 /*
5453 * when target gives queue full status with no commands
5454 * outstanding (m_t_ncmds == 0), throttle is set to 0
5455 * (HOLD_THROTTLE), and the queue full handling start
5456 * (see psarc/1994/313); if there are commands outstanding,
5457 * throttle is set to (m_t_ncmds - 2)
5458 */
5459 if (ptgt->m_t_throttle == HOLD_THROTTLE) {
5460 /*
5461 * By setting throttle to QFULL_THROTTLE, we
5462 * avoid submitting new commands and in
5463 * mptsas_restart_cmd find out slots which need
5464 * their throttles to be cleared.
5465 */
5466 mptsas_set_throttle(mpt, ptgt, QFULL_THROTTLE);
5467 if (mpt->m_restart_cmd_timeid == 0) {
5468 mpt->m_restart_cmd_timeid =
5469 timeout(mptsas_restart_cmd, mpt,
5470 ptgt->m_qfull_retry_interval);
5471 }
5472 }
5473 }
5474 }
5475
5476 mptsas_phymask_t
5477 mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport)
5478 {
5479 mptsas_phymask_t phy_mask = 0;
5480 uint8_t i = 0;
5481
5482 NDBG20(("mptsas%d physport_to_phymask enter", mpt->m_instance));
5483
5484 ASSERT(mutex_owned(&mpt->m_mutex));
5485
5486 /*
5487 * If physport is 0xFF, this is a RAID volume. Use phymask of 0.
5488 */
5489 if (physport == 0xFF) {
5490 return (0);
5491 }
5492
5493 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
5494 if (mpt->m_phy_info[i].attached_devhdl &&
5495 (mpt->m_phy_info[i].phy_mask != 0) &&
5496 (mpt->m_phy_info[i].port_num == physport)) {
5497 phy_mask = mpt->m_phy_info[i].phy_mask;
5498 break;
5499 }
5500 }
5501 NDBG20(("mptsas%d physport_to_phymask:physport :%x phymask :%x, ",
5502 mpt->m_instance, physport, phy_mask));
5503 return (phy_mask);
5504 }
5505
5506 /*
5507 * mpt free device handle after device gone, by use of passthrough
5508 */
5509 static int
5510 mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl)
5511 {
5512 Mpi2SasIoUnitControlRequest_t req;
5513 Mpi2SasIoUnitControlReply_t rep;
5514 int ret;
5515
5516 ASSERT(mutex_owned(&mpt->m_mutex));
5517
5518 /*
5519 * Need to compose a SAS IO Unit Control request message
5520 * and call mptsas_do_passthru() function
5521 */
5522 bzero(&req, sizeof (req));
5523 bzero(&rep, sizeof (rep));
5524
5525 req.Function = MPI2_FUNCTION_SAS_IO_UNIT_CONTROL;
5526 req.Operation = MPI2_SAS_OP_REMOVE_DEVICE;
5527 req.DevHandle = LE_16(devhdl);
5528
5529 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL,
5530 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL);
5531 if (ret != 0) {
5532 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit "
5533 "Control error %d", ret);
5534 return (DDI_FAILURE);
5535 }
5536
5537 /* do passthrough success, check the ioc status */
5538 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
5539 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit "
5540 "Control IOCStatus %d", LE_16(rep.IOCStatus));
5541 return (DDI_FAILURE);
5542 }
5543
5544 return (DDI_SUCCESS);
5545 }
5546
5547 static void
5548 mptsas_update_phymask(mptsas_t *mpt)
5549 {
5550 mptsas_phymask_t mask = 0, phy_mask;
5551 char *phy_mask_name;
5552 uint8_t current_port;
5553 int i, j;
5554
5555 NDBG20(("mptsas%d update phymask ", mpt->m_instance));
5556
5557 ASSERT(mutex_owned(&mpt->m_mutex));
5558
5559 (void) mptsas_get_sas_io_unit_page(mpt);
5560
5561 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
5562
5563 for (i = 0; i < mpt->m_num_phys; i++) {
5564 phy_mask = 0x00;
5565
5566 if (mpt->m_phy_info[i].attached_devhdl == 0)
5567 continue;
5568
5569 bzero(phy_mask_name, sizeof (phy_mask_name));
5570
5571 current_port = mpt->m_phy_info[i].port_num;
5572
5573 if ((mask & (1 << i)) != 0)
5574 continue;
5575
5576 for (j = 0; j < mpt->m_num_phys; j++) {
5577 if (mpt->m_phy_info[j].attached_devhdl &&
5578 (mpt->m_phy_info[j].port_num == current_port)) {
5579 phy_mask |= (1 << j);
5580 }
5581 }
5582 mask = mask | phy_mask;
5583
5584 for (j = 0; j < mpt->m_num_phys; j++) {
5585 if ((phy_mask >> j) & 0x01) {
5586 mpt->m_phy_info[j].phy_mask = phy_mask;
5587 }
5588 }
5589
5590 (void) sprintf(phy_mask_name, "%x", phy_mask);
5591
5592 mutex_exit(&mpt->m_mutex);
5593 /*
5594 * register a iport, if the port has already been existed
5595 * SCSA will do nothing and just return.
5596 */
5597 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name);
5598 mutex_enter(&mpt->m_mutex);
5599 }
5600 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
5601 NDBG20(("mptsas%d update phymask return", mpt->m_instance));
5602 }
5603
5604 /*
5605 * mptsas_handle_dr is a task handler for DR, the DR action includes:
5606 * 1. Directly attched Device Added/Removed.
5607 * 2. Expander Device Added/Removed.
5608 * 3. Indirectly Attached Device Added/Expander.
5609 * 4. LUNs of a existing device status change.
5610 * 5. RAID volume created/deleted.
5611 * 6. Member of RAID volume is released because of RAID deletion.
5612 * 7. Physical disks are removed because of RAID creation.
5613 */
5614 static void
5615 mptsas_handle_dr(void *args) {
5616 mptsas_topo_change_list_t *topo_node = NULL;
5617 mptsas_topo_change_list_t *save_node = NULL;
5618 mptsas_t *mpt;
5619 dev_info_t *parent = NULL;
5620 mptsas_phymask_t phymask = 0;
5621 char *phy_mask_name;
5622 uint8_t flags = 0, physport = 0xff;
5623 uint8_t port_update = 0;
5624 uint_t event;
5625
5626 topo_node = (mptsas_topo_change_list_t *)args;
5627
5628 mpt = topo_node->mpt;
5629 event = topo_node->event;
5630 flags = topo_node->flags;
5631
5632 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
5633
5634 NDBG20(("mptsas%d handle_dr enter", mpt->m_instance));
5635
5636 switch (event) {
5637 case MPTSAS_DR_EVENT_RECONFIG_TARGET:
5638 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
5639 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE) ||
5640 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) {
5641 /*
5642 * Direct attached or expander attached device added
5643 * into system or a Phys Disk that is being unhidden.
5644 */
5645 port_update = 1;
5646 }
5647 break;
5648 case MPTSAS_DR_EVENT_RECONFIG_SMP:
5649 /*
5650 * New expander added into system, it must be the head
5651 * of topo_change_list_t
5652 */
5653 port_update = 1;
5654 break;
5655 default:
5656 port_update = 0;
5657 break;
5658 }
5659 /*
5660 * All cases port_update == 1 may cause initiator port form change
5661 */
5662 mutex_enter(&mpt->m_mutex);
5663 if (mpt->m_port_chng && port_update) {
5664 /*
5665 * mpt->m_port_chng flag indicates some PHYs of initiator
5666 * port have changed to online. So when expander added or
5667 * directly attached device online event come, we force to
5668 * update port information by issueing SAS IO Unit Page and
5669 * update PHYMASKs.
5670 */
5671 (void) mptsas_update_phymask(mpt);
5672 mpt->m_port_chng = 0;
5673
5674 }
5675 mutex_exit(&mpt->m_mutex);
5676 while (topo_node) {
5677 phymask = 0;
5678 if (parent == NULL) {
5679 physport = topo_node->un.physport;
5680 event = topo_node->event;
5681 flags = topo_node->flags;
5682 if (event & (MPTSAS_DR_EVENT_OFFLINE_TARGET |
5683 MPTSAS_DR_EVENT_OFFLINE_SMP)) {
5684 /*
5685 * For all offline events, phymask is known
5686 */
5687 phymask = topo_node->un.phymask;
5688 goto find_parent;
5689 }
5690 if (event & MPTSAS_TOPO_FLAG_REMOVE_HANDLE) {
5691 goto handle_topo_change;
5692 }
5693 if (flags & MPTSAS_TOPO_FLAG_LUN_ASSOCIATED) {
5694 phymask = topo_node->un.phymask;
5695 goto find_parent;
5696 }
5697
5698 if ((flags ==
5699 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) &&
5700 (event == MPTSAS_DR_EVENT_RECONFIG_TARGET)) {
5701 /*
5702 * There is no any field in IR_CONFIG_CHANGE
5703 * event indicate physport/phynum, let's get
5704 * parent after SAS Device Page0 request.
5705 */
5706 goto handle_topo_change;
5707 }
5708
5709 mutex_enter(&mpt->m_mutex);
5710 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
5711 /*
5712 * If the direct attached device added or a
5713 * phys disk is being unhidden, argument
5714 * physport actually is PHY#, so we have to get
5715 * phymask according PHY#.
5716 */
5717 physport = mpt->m_phy_info[physport].port_num;
5718 }
5719
5720 /*
5721 * Translate physport to phymask so that we can search
5722 * parent dip.
5723 */
5724 phymask = mptsas_physport_to_phymask(mpt,
5725 physport);
5726 mutex_exit(&mpt->m_mutex);
5727
5728 find_parent:
5729 bzero(phy_mask_name, MPTSAS_MAX_PHYS);
5730 /*
5731 * For RAID topology change node, write the iport name
5732 * as v0.
5733 */
5734 if (flags & MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
5735 (void) sprintf(phy_mask_name, "v0");
5736 } else {
5737 /*
5738 * phymask can bo 0 if the drive has been
5739 * pulled by the time an add event is
5740 * processed. If phymask is 0, just skip this
5741 * event and continue.
5742 */
5743 if (phymask == 0) {
5744 mutex_enter(&mpt->m_mutex);
5745 save_node = topo_node;
5746 topo_node = topo_node->next;
5747 ASSERT(save_node);
5748 kmem_free(save_node,
5749 sizeof (mptsas_topo_change_list_t));
5750 mutex_exit(&mpt->m_mutex);
5751
5752 parent = NULL;
5753 continue;
5754 }
5755 (void) sprintf(phy_mask_name, "%x", phymask);
5756 }
5757 parent = scsi_hba_iport_find(mpt->m_dip,
5758 phy_mask_name);
5759 if (parent == NULL) {
5760 mptsas_log(mpt, CE_WARN, "Failed to find an "
5761 "iport, should not happen!");
5762 goto out;
5763 }
5764
5765 }
5766 ASSERT(parent);
5767 handle_topo_change:
5768
5769 mutex_enter(&mpt->m_mutex);
5770 /*
5771 * If HBA is being reset, don't perform operations depending
5772 * on the IOC. We must free the topo list, however.
5773 */
5774 if (!mpt->m_in_reset)
5775 mptsas_handle_topo_change(topo_node, parent);
5776 else
5777 NDBG20(("skipping topo change received during reset"));
5778 save_node = topo_node;
5779 topo_node = topo_node->next;
5780 ASSERT(save_node);
5781 kmem_free(save_node, sizeof (mptsas_topo_change_list_t));
5782 mutex_exit(&mpt->m_mutex);
5783
5784 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
5785 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) ||
5786 (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED)) {
5787 /*
5788 * If direct attached device associated, make sure
5789 * reset the parent before start the next one. But
5790 * all devices associated with expander shares the
5791 * parent. Also, reset parent if this is for RAID.
5792 */
5793 parent = NULL;
5794 }
5795 }
5796 out:
5797 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
5798 }
5799
5800 static void
5801 mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node,
5802 dev_info_t *parent)
5803 {
5804 mptsas_target_t *ptgt = NULL;
5805 mptsas_smp_t *psmp = NULL;
5806 mptsas_t *mpt = (void *)topo_node->mpt;
5807 uint16_t devhdl;
5808 uint16_t attached_devhdl;
5809 uint64_t sas_wwn = 0;
5810 int rval = 0;
5811 uint32_t page_address;
5812 uint8_t phy, flags;
5813 char *addr = NULL;
5814 dev_info_t *lundip;
5815 int circ = 0, circ1 = 0;
5816 char attached_wwnstr[MPTSAS_WWN_STRLEN];
5817
5818 NDBG20(("mptsas%d handle_topo_change enter", mpt->m_instance));
5819
5820 ASSERT(mutex_owned(&mpt->m_mutex));
5821
5822 switch (topo_node->event) {
5823 case MPTSAS_DR_EVENT_RECONFIG_TARGET:
5824 {
5825 char *phy_mask_name;
5826 mptsas_phymask_t phymask = 0;
5827
5828 if (topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
5829 /*
5830 * Get latest RAID info.
5831 */
5832 (void) mptsas_get_raid_info(mpt);
5833 ptgt = mptsas_search_by_devhdl(
5834 &mpt->m_active->m_tgttbl, topo_node->devhdl);
5835 if (ptgt == NULL)
5836 break;
5837 } else {
5838 ptgt = (void *)topo_node->object;
5839 }
5840
5841 if (ptgt == NULL) {
5842 /*
5843 * If a Phys Disk was deleted, RAID info needs to be
5844 * updated to reflect the new topology.
5845 */
5846 (void) mptsas_get_raid_info(mpt);
5847
5848 /*
5849 * Get sas device page 0 by DevHandle to make sure if
5850 * SSP/SATA end device exist.
5851 */
5852 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
5853 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
5854 topo_node->devhdl;
5855
5856 rval = mptsas_get_target_device_info(mpt, page_address,
5857 &devhdl, &ptgt);
5858 if (rval == DEV_INFO_WRONG_DEVICE_TYPE) {
5859 mptsas_log(mpt, CE_NOTE,
5860 "mptsas_handle_topo_change: target %d is "
5861 "not a SAS/SATA device. \n",
5862 topo_node->devhdl);
5863 } else if (rval == DEV_INFO_FAIL_ALLOC) {
5864 mptsas_log(mpt, CE_NOTE,
5865 "mptsas_handle_topo_change: could not "
5866 "allocate memory. \n");
5867 }
5868 /*
5869 * If rval is DEV_INFO_PHYS_DISK than there is nothing
5870 * else to do, just leave.
5871 */
5872 if (rval != DEV_INFO_SUCCESS) {
5873 return;
5874 }
5875 }
5876
5877 ASSERT(ptgt->m_devhdl == topo_node->devhdl);
5878
5879 mutex_exit(&mpt->m_mutex);
5880 flags = topo_node->flags;
5881
5882 if (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) {
5883 phymask = ptgt->m_phymask;
5884 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
5885 (void) sprintf(phy_mask_name, "%x", phymask);
5886 parent = scsi_hba_iport_find(mpt->m_dip,
5887 phy_mask_name);
5888 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
5889 if (parent == NULL) {
5890 mptsas_log(mpt, CE_WARN, "Failed to find a "
5891 "iport for PD, should not happen!");
5892 mutex_enter(&mpt->m_mutex);
5893 break;
5894 }
5895 }
5896
5897 if (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
5898 ndi_devi_enter(parent, &circ1);
5899 (void) mptsas_config_raid(parent, topo_node->devhdl,
5900 &lundip);
5901 ndi_devi_exit(parent, circ1);
5902 } else {
5903 /*
5904 * hold nexus for bus configure
5905 */
5906 ndi_devi_enter(scsi_vhci_dip, &circ);
5907 ndi_devi_enter(parent, &circ1);
5908 rval = mptsas_config_target(parent, ptgt);
5909 /*
5910 * release nexus for bus configure
5911 */
5912 ndi_devi_exit(parent, circ1);
5913 ndi_devi_exit(scsi_vhci_dip, circ);
5914
5915 /*
5916 * Add parent's props for SMHBA support
5917 */
5918 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
5919 bzero(attached_wwnstr,
5920 sizeof (attached_wwnstr));
5921 (void) sprintf(attached_wwnstr, "w%016"PRIx64,
5922 ptgt->m_sas_wwn);
5923 if (ddi_prop_update_string(DDI_DEV_T_NONE,
5924 parent,
5925 SCSI_ADDR_PROP_ATTACHED_PORT,
5926 attached_wwnstr)
5927 != DDI_PROP_SUCCESS) {
5928 (void) ddi_prop_remove(DDI_DEV_T_NONE,
5929 parent,
5930 SCSI_ADDR_PROP_ATTACHED_PORT);
5931 mptsas_log(mpt, CE_WARN, "Failed to"
5932 "attached-port props");
5933 return;
5934 }
5935 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
5936 MPTSAS_NUM_PHYS, 1) !=
5937 DDI_PROP_SUCCESS) {
5938 (void) ddi_prop_remove(DDI_DEV_T_NONE,
5939 parent, MPTSAS_NUM_PHYS);
5940 mptsas_log(mpt, CE_WARN, "Failed to"
5941 " create num-phys props");
5942 return;
5943 }
5944
5945 /*
5946 * Update PHY info for smhba
5947 */
5948 mutex_enter(&mpt->m_mutex);
5949 if (mptsas_smhba_phy_init(mpt)) {
5950 mutex_exit(&mpt->m_mutex);
5951 mptsas_log(mpt, CE_WARN, "mptsas phy"
5952 " update failed");
5953 return;
5954 }
5955 mutex_exit(&mpt->m_mutex);
5956 mptsas_smhba_set_phy_props(mpt,
5957 ddi_get_name_addr(parent), parent,
5958 1, &attached_devhdl);
5959 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
5960 MPTSAS_VIRTUAL_PORT, 0) !=
5961 DDI_PROP_SUCCESS) {
5962 (void) ddi_prop_remove(DDI_DEV_T_NONE,
5963 parent, MPTSAS_VIRTUAL_PORT);
5964 mptsas_log(mpt, CE_WARN,
5965 "mptsas virtual-port"
5966 "port prop update failed");
5967 return;
5968 }
5969 }
5970 }
5971 mutex_enter(&mpt->m_mutex);
5972
5973 NDBG20(("mptsas%d handle_topo_change to online devhdl:%x, "
5974 "phymask:%x.", mpt->m_instance, ptgt->m_devhdl,
5975 ptgt->m_phymask));
5976 break;
5977 }
5978 case MPTSAS_DR_EVENT_OFFLINE_TARGET:
5979 {
5980 mptsas_hash_table_t *tgttbl = &mpt->m_active->m_tgttbl;
5981 devhdl = topo_node->devhdl;
5982 ptgt = mptsas_search_by_devhdl(tgttbl, devhdl);
5983 if (ptgt == NULL)
5984 break;
5985
5986 sas_wwn = ptgt->m_sas_wwn;
5987 phy = ptgt->m_phynum;
5988
5989 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
5990
5991 if (sas_wwn) {
5992 (void) sprintf(addr, "w%016"PRIx64, sas_wwn);
5993 } else {
5994 (void) sprintf(addr, "p%x", phy);
5995 }
5996 ASSERT(ptgt->m_devhdl == devhdl);
5997
5998 if ((topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) ||
5999 (topo_node->flags ==
6000 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) {
6001 /*
6002 * Get latest RAID info if RAID volume status changes
6003 * or Phys Disk status changes
6004 */
6005 (void) mptsas_get_raid_info(mpt);
6006 }
6007 /*
6008 * Abort all outstanding command on the device
6009 */
6010 rval = mptsas_do_scsi_reset(mpt, devhdl);
6011 if (rval) {
6012 NDBG20(("mptsas%d handle_topo_change to reset target "
6013 "before offline devhdl:%x, phymask:%x, rval:%x",
6014 mpt->m_instance, ptgt->m_devhdl, ptgt->m_phymask,
6015 rval));
6016 }
6017
6018 mutex_exit(&mpt->m_mutex);
6019
6020 ndi_devi_enter(scsi_vhci_dip, &circ);
6021 ndi_devi_enter(parent, &circ1);
6022 rval = mptsas_offline_target(parent, addr);
6023 ndi_devi_exit(parent, circ1);
6024 ndi_devi_exit(scsi_vhci_dip, circ);
6025 NDBG20(("mptsas%d handle_topo_change to offline devhdl:%x, "
6026 "phymask:%x, rval:%x", mpt->m_instance,
6027 ptgt->m_devhdl, ptgt->m_phymask, rval));
6028
6029 kmem_free(addr, SCSI_MAXNAMELEN);
6030
6031 /*
6032 * Clear parent's props for SMHBA support
6033 */
6034 flags = topo_node->flags;
6035 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6036 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6037 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent,
6038 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
6039 DDI_PROP_SUCCESS) {
6040 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6041 SCSI_ADDR_PROP_ATTACHED_PORT);
6042 mptsas_log(mpt, CE_WARN, "mptsas attached port "
6043 "prop update failed");
6044 break;
6045 }
6046 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6047 MPTSAS_NUM_PHYS, 0) !=
6048 DDI_PROP_SUCCESS) {
6049 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6050 MPTSAS_NUM_PHYS);
6051 mptsas_log(mpt, CE_WARN, "mptsas num phys "
6052 "prop update failed");
6053 break;
6054 }
6055 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6056 MPTSAS_VIRTUAL_PORT, 1) !=
6057 DDI_PROP_SUCCESS) {
6058 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6059 MPTSAS_VIRTUAL_PORT);
6060 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
6061 "prop update failed");
6062 break;
6063 }
6064 }
6065
6066 mutex_enter(&mpt->m_mutex);
6067 ptgt->m_led_status = 0;
6068 (void) mptsas_flush_led_status(mpt, ptgt);
6069 if (rval == DDI_SUCCESS) {
6070 mptsas_tgt_free(&mpt->m_active->m_tgttbl,
6071 ptgt->m_sas_wwn, ptgt->m_phymask);
6072 ptgt = NULL;
6073 } else {
6074 /*
6075 * clean DR_INTRANSITION flag to allow I/O down to
6076 * PHCI driver since failover finished.
6077 * Invalidate the devhdl
6078 */
6079 ptgt->m_devhdl = MPTSAS_INVALID_DEVHDL;
6080 ptgt->m_tgt_unconfigured = 0;
6081 mutex_enter(&mpt->m_tx_waitq_mutex);
6082 ptgt->m_dr_flag = MPTSAS_DR_INACTIVE;
6083 mutex_exit(&mpt->m_tx_waitq_mutex);
6084 }
6085
6086 /*
6087 * Send SAS IO Unit Control to free the dev handle
6088 */
6089 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6090 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE)) {
6091 rval = mptsas_free_devhdl(mpt, devhdl);
6092
6093 NDBG20(("mptsas%d handle_topo_change to remove "
6094 "devhdl:%x, rval:%x", mpt->m_instance, devhdl,
6095 rval));
6096 }
6097
6098 break;
6099 }
6100 case MPTSAS_TOPO_FLAG_REMOVE_HANDLE:
6101 {
6102 devhdl = topo_node->devhdl;
6103 /*
6104 * If this is the remove handle event, do a reset first.
6105 */
6106 if (topo_node->event == MPTSAS_TOPO_FLAG_REMOVE_HANDLE) {
6107 rval = mptsas_do_scsi_reset(mpt, devhdl);
6108 if (rval) {
6109 NDBG20(("mpt%d reset target before remove "
6110 "devhdl:%x, rval:%x", mpt->m_instance,
6111 devhdl, rval));
6112 }
6113 }
6114
6115 /*
6116 * Send SAS IO Unit Control to free the dev handle
6117 */
6118 rval = mptsas_free_devhdl(mpt, devhdl);
6119 NDBG20(("mptsas%d handle_topo_change to remove "
6120 "devhdl:%x, rval:%x", mpt->m_instance, devhdl,
6121 rval));
6122 break;
6123 }
6124 case MPTSAS_DR_EVENT_RECONFIG_SMP:
6125 {
6126 mptsas_smp_t smp;
6127 dev_info_t *smpdip;
6128 mptsas_hash_table_t *smptbl = &mpt->m_active->m_smptbl;
6129
6130 devhdl = topo_node->devhdl;
6131
6132 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL &
6133 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)devhdl;
6134 rval = mptsas_get_sas_expander_page0(mpt, page_address, &smp);
6135 if (rval != DDI_SUCCESS) {
6136 mptsas_log(mpt, CE_WARN, "failed to online smp, "
6137 "handle %x", devhdl);
6138 return;
6139 }
6140
6141 psmp = mptsas_smp_alloc(smptbl, &smp);
6142 if (psmp == NULL) {
6143 return;
6144 }
6145
6146 mutex_exit(&mpt->m_mutex);
6147 ndi_devi_enter(parent, &circ1);
6148 (void) mptsas_online_smp(parent, psmp, &smpdip);
6149 ndi_devi_exit(parent, circ1);
6150
6151 mutex_enter(&mpt->m_mutex);
6152 break;
6153 }
6154 case MPTSAS_DR_EVENT_OFFLINE_SMP:
6155 {
6156 mptsas_hash_table_t *smptbl = &mpt->m_active->m_smptbl;
6157 devhdl = topo_node->devhdl;
6158 uint32_t dev_info;
6159
6160 psmp = mptsas_search_by_devhdl(smptbl, devhdl);
6161 if (psmp == NULL)
6162 break;
6163 /*
6164 * The mptsas_smp_t data is released only if the dip is offlined
6165 * successfully.
6166 */
6167 mutex_exit(&mpt->m_mutex);
6168
6169 ndi_devi_enter(parent, &circ1);
6170 rval = mptsas_offline_smp(parent, psmp, NDI_DEVI_REMOVE);
6171 ndi_devi_exit(parent, circ1);
6172
6173 dev_info = psmp->m_deviceinfo;
6174 if ((dev_info & DEVINFO_DIRECT_ATTACHED) ==
6175 DEVINFO_DIRECT_ATTACHED) {
6176 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6177 MPTSAS_VIRTUAL_PORT, 1) !=
6178 DDI_PROP_SUCCESS) {
6179 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6180 MPTSAS_VIRTUAL_PORT);
6181 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
6182 "prop update failed");
6183 return;
6184 }
6185 /*
6186 * Check whether the smp connected to the iport,
6187 */
6188 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6189 MPTSAS_NUM_PHYS, 0) !=
6190 DDI_PROP_SUCCESS) {
6191 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6192 MPTSAS_NUM_PHYS);
6193 mptsas_log(mpt, CE_WARN, "mptsas num phys"
6194 "prop update failed");
6195 return;
6196 }
6197 /*
6198 * Clear parent's attached-port props
6199 */
6200 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6201 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent,
6202 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
6203 DDI_PROP_SUCCESS) {
6204 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6205 SCSI_ADDR_PROP_ATTACHED_PORT);
6206 mptsas_log(mpt, CE_WARN, "mptsas attached port "
6207 "prop update failed");
6208 return;
6209 }
6210 }
6211
6212 mutex_enter(&mpt->m_mutex);
6213 NDBG20(("mptsas%d handle_topo_change to remove devhdl:%x, "
6214 "rval:%x", mpt->m_instance, psmp->m_devhdl, rval));
6215 if (rval == DDI_SUCCESS) {
6216 mptsas_smp_free(smptbl, psmp->m_sasaddr,
6217 psmp->m_phymask);
6218 } else {
6219 psmp->m_devhdl = MPTSAS_INVALID_DEVHDL;
6220 }
6221
6222 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6223
6224 break;
6225 }
6226 default:
6227 return;
6228 }
6229 }
6230
6231 /*
6232 * Record the event if its type is enabled in mpt instance by ioctl.
6233 */
6234 static void
6235 mptsas_record_event(void *args)
6236 {
6237 m_replyh_arg_t *replyh_arg;
6238 pMpi2EventNotificationReply_t eventreply;
6239 uint32_t event, rfm;
6240 mptsas_t *mpt;
6241 int i, j;
6242 uint16_t event_data_len;
6243 boolean_t sendAEN = FALSE;
6244
6245 replyh_arg = (m_replyh_arg_t *)args;
6246 rfm = replyh_arg->rfm;
6247 mpt = replyh_arg->mpt;
6248
6249 eventreply = (pMpi2EventNotificationReply_t)
6250 (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr));
6251 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
6252
6253
6254 /*
6255 * Generate a system event to let anyone who cares know that a
6256 * LOG_ENTRY_ADDED event has occurred. This is sent no matter what the
6257 * event mask is set to.
6258 */
6259 if (event == MPI2_EVENT_LOG_ENTRY_ADDED) {
6260 sendAEN = TRUE;
6261 }
6262
6263 /*
6264 * Record the event only if it is not masked. Determine which dword
6265 * and bit of event mask to test.
6266 */
6267 i = (uint8_t)(event / 32);
6268 j = (uint8_t)(event % 32);
6269 if ((i < 4) && ((1 << j) & mpt->m_event_mask[i])) {
6270 i = mpt->m_event_index;
6271 mpt->m_events[i].Type = event;
6272 mpt->m_events[i].Number = ++mpt->m_event_number;
6273 bzero(mpt->m_events[i].Data, MPTSAS_MAX_EVENT_DATA_LENGTH * 4);
6274 event_data_len = ddi_get16(mpt->m_acc_reply_frame_hdl,
6275 &eventreply->EventDataLength);
6276
6277 if (event_data_len > 0) {
6278 /*
6279 * Limit data to size in m_event entry
6280 */
6281 if (event_data_len > MPTSAS_MAX_EVENT_DATA_LENGTH) {
6282 event_data_len = MPTSAS_MAX_EVENT_DATA_LENGTH;
6283 }
6284 for (j = 0; j < event_data_len; j++) {
6285 mpt->m_events[i].Data[j] =
6286 ddi_get32(mpt->m_acc_reply_frame_hdl,
6287 &(eventreply->EventData[j]));
6288 }
6289
6290 /*
6291 * check for index wrap-around
6292 */
6293 if (++i == MPTSAS_EVENT_QUEUE_SIZE) {
6294 i = 0;
6295 }
6296 mpt->m_event_index = (uint8_t)i;
6297
6298 /*
6299 * Set flag to send the event.
6300 */
6301 sendAEN = TRUE;
6302 }
6303 }
6304
6305 /*
6306 * Generate a system event if flag is set to let anyone who cares know
6307 * that an event has occurred.
6308 */
6309 if (sendAEN) {
6310 (void) ddi_log_sysevent(mpt->m_dip, DDI_VENDOR_LSI, "MPT_SAS",
6311 "SAS", NULL, NULL, DDI_NOSLEEP);
6312 }
6313 }
6314
6315 #define SMP_RESET_IN_PROGRESS MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS
6316 /*
6317 * handle sync events from ioc in interrupt
6318 * return value:
6319 * DDI_SUCCESS: The event is handled by this func
6320 * DDI_FAILURE: Event is not handled
6321 */
6322 static int
6323 mptsas_handle_event_sync(void *args)
6324 {
6325 m_replyh_arg_t *replyh_arg;
6326 pMpi2EventNotificationReply_t eventreply;
6327 uint32_t event, rfm;
6328 mptsas_t *mpt;
6329 uint_t iocstatus;
6330
6331 replyh_arg = (m_replyh_arg_t *)args;
6332 rfm = replyh_arg->rfm;
6333 mpt = replyh_arg->mpt;
6334
6335 ASSERT(mutex_owned(&mpt->m_mutex));
6336
6337 eventreply = (pMpi2EventNotificationReply_t)
6338 (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr));
6339 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
6340
6341 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
6342 &eventreply->IOCStatus)) {
6343 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
6344 mptsas_log(mpt, CE_WARN,
6345 "!mptsas_handle_event_sync: IOCStatus=0x%x, "
6346 "IOCLogInfo=0x%x", iocstatus,
6347 ddi_get32(mpt->m_acc_reply_frame_hdl,
6348 &eventreply->IOCLogInfo));
6349 } else {
6350 mptsas_log(mpt, CE_WARN,
6351 "mptsas_handle_event_sync: IOCStatus=0x%x, "
6352 "IOCLogInfo=0x%x", iocstatus,
6353 ddi_get32(mpt->m_acc_reply_frame_hdl,
6354 &eventreply->IOCLogInfo));
6355 }
6356 }
6357
6358 /*
6359 * figure out what kind of event we got and handle accordingly
6360 */
6361 switch (event) {
6362 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
6363 {
6364 pMpi2EventDataSasTopologyChangeList_t sas_topo_change_list;
6365 uint8_t num_entries, expstatus, phy;
6366 uint8_t phystatus, physport, state, i;
6367 uint8_t start_phy_num, link_rate;
6368 uint16_t dev_handle, reason_code;
6369 uint16_t enc_handle, expd_handle;
6370 char string[80], curr[80], prev[80];
6371 mptsas_topo_change_list_t *topo_head = NULL;
6372 mptsas_topo_change_list_t *topo_tail = NULL;
6373 mptsas_topo_change_list_t *topo_node = NULL;
6374 mptsas_target_t *ptgt;
6375 mptsas_smp_t *psmp;
6376 mptsas_hash_table_t *tgttbl, *smptbl;
6377 uint8_t flags = 0, exp_flag;
6378 smhba_info_t *pSmhba = NULL;
6379
6380 NDBG20(("mptsas_handle_event_sync: SAS topology change"));
6381
6382 tgttbl = &mpt->m_active->m_tgttbl;
6383 smptbl = &mpt->m_active->m_smptbl;
6384
6385 sas_topo_change_list = (pMpi2EventDataSasTopologyChangeList_t)
6386 eventreply->EventData;
6387
6388 enc_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6389 &sas_topo_change_list->EnclosureHandle);
6390 expd_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6391 &sas_topo_change_list->ExpanderDevHandle);
6392 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl,
6393 &sas_topo_change_list->NumEntries);
6394 start_phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl,
6395 &sas_topo_change_list->StartPhyNum);
6396 expstatus = ddi_get8(mpt->m_acc_reply_frame_hdl,
6397 &sas_topo_change_list->ExpStatus);
6398 physport = ddi_get8(mpt->m_acc_reply_frame_hdl,
6399 &sas_topo_change_list->PhysicalPort);
6400
6401 string[0] = 0;
6402 if (expd_handle) {
6403 flags = MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED;
6404 switch (expstatus) {
6405 case MPI2_EVENT_SAS_TOPO_ES_ADDED:
6406 (void) sprintf(string, " added");
6407 /*
6408 * New expander device added
6409 */
6410 mpt->m_port_chng = 1;
6411 topo_node = kmem_zalloc(
6412 sizeof (mptsas_topo_change_list_t),
6413 KM_SLEEP);
6414 topo_node->mpt = mpt;
6415 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_SMP;
6416 topo_node->un.physport = physport;
6417 topo_node->devhdl = expd_handle;
6418 topo_node->flags = flags;
6419 topo_node->object = NULL;
6420 if (topo_head == NULL) {
6421 topo_head = topo_tail = topo_node;
6422 } else {
6423 topo_tail->next = topo_node;
6424 topo_tail = topo_node;
6425 }
6426 break;
6427 case MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING:
6428 (void) sprintf(string, " not responding, "
6429 "removed");
6430 psmp = mptsas_search_by_devhdl(smptbl,
6431 expd_handle);
6432 if (psmp == NULL)
6433 break;
6434
6435 topo_node = kmem_zalloc(
6436 sizeof (mptsas_topo_change_list_t),
6437 KM_SLEEP);
6438 topo_node->mpt = mpt;
6439 topo_node->un.phymask = psmp->m_phymask;
6440 topo_node->event = MPTSAS_DR_EVENT_OFFLINE_SMP;
6441 topo_node->devhdl = expd_handle;
6442 topo_node->flags = flags;
6443 topo_node->object = NULL;
6444 if (topo_head == NULL) {
6445 topo_head = topo_tail = topo_node;
6446 } else {
6447 topo_tail->next = topo_node;
6448 topo_tail = topo_node;
6449 }
6450 break;
6451 case MPI2_EVENT_SAS_TOPO_ES_RESPONDING:
6452 break;
6453 case MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING:
6454 (void) sprintf(string, " not responding, "
6455 "delaying removal");
6456 break;
6457 default:
6458 break;
6459 }
6460 } else {
6461 flags = MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE;
6462 }
6463
6464 NDBG20(("SAS TOPOLOGY CHANGE for enclosure %x expander %x%s\n",
6465 enc_handle, expd_handle, string));
6466 for (i = 0; i < num_entries; i++) {
6467 phy = i + start_phy_num;
6468 phystatus = ddi_get8(mpt->m_acc_reply_frame_hdl,
6469 &sas_topo_change_list->PHY[i].PhyStatus);
6470 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6471 &sas_topo_change_list->PHY[i].AttachedDevHandle);
6472 reason_code = phystatus & MPI2_EVENT_SAS_TOPO_RC_MASK;
6473 /*
6474 * Filter out processing of Phy Vacant Status unless
6475 * the reason code is "Not Responding". Process all
6476 * other combinations of Phy Status and Reason Codes.
6477 */
6478 if ((phystatus &
6479 MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT) &&
6480 (reason_code !=
6481 MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING)) {
6482 continue;
6483 }
6484 curr[0] = 0;
6485 prev[0] = 0;
6486 string[0] = 0;
6487 switch (reason_code) {
6488 case MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED:
6489 {
6490 NDBG20(("mptsas%d phy %d physical_port %d "
6491 "dev_handle %d added", mpt->m_instance, phy,
6492 physport, dev_handle));
6493 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl,
6494 &sas_topo_change_list->PHY[i].LinkRate);
6495 state = (link_rate &
6496 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >>
6497 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT;
6498 switch (state) {
6499 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
6500 (void) sprintf(curr, "is disabled");
6501 break;
6502 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
6503 (void) sprintf(curr, "is offline, "
6504 "failed speed negotiation");
6505 break;
6506 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
6507 (void) sprintf(curr, "SATA OOB "
6508 "complete");
6509 break;
6510 case SMP_RESET_IN_PROGRESS:
6511 (void) sprintf(curr, "SMP reset in "
6512 "progress");
6513 break;
6514 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
6515 (void) sprintf(curr, "is online at "
6516 "1.5 Gbps");
6517 break;
6518 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
6519 (void) sprintf(curr, "is online at 3.0 "
6520 "Gbps");
6521 break;
6522 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
6523 (void) sprintf(curr, "is online at 6.0 "
6524 "Gbps");
6525 break;
6526 default:
6527 (void) sprintf(curr, "state is "
6528 "unknown");
6529 break;
6530 }
6531 /*
6532 * New target device added into the system.
6533 * Set association flag according to if an
6534 * expander is used or not.
6535 */
6536 exp_flag =
6537 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE;
6538 if (flags ==
6539 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) {
6540 flags = exp_flag;
6541 }
6542 topo_node = kmem_zalloc(
6543 sizeof (mptsas_topo_change_list_t),
6544 KM_SLEEP);
6545 topo_node->mpt = mpt;
6546 topo_node->event =
6547 MPTSAS_DR_EVENT_RECONFIG_TARGET;
6548 if (expd_handle == 0) {
6549 /*
6550 * Per MPI 2, if expander dev handle
6551 * is 0, it's a directly attached
6552 * device. So driver use PHY to decide
6553 * which iport is associated
6554 */
6555 physport = phy;
6556 mpt->m_port_chng = 1;
6557 }
6558 topo_node->un.physport = physport;
6559 topo_node->devhdl = dev_handle;
6560 topo_node->flags = flags;
6561 topo_node->object = NULL;
6562 if (topo_head == NULL) {
6563 topo_head = topo_tail = topo_node;
6564 } else {
6565 topo_tail->next = topo_node;
6566 topo_tail = topo_node;
6567 }
6568 break;
6569 }
6570 case MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING:
6571 {
6572 NDBG20(("mptsas%d phy %d physical_port %d "
6573 "dev_handle %d removed", mpt->m_instance,
6574 phy, physport, dev_handle));
6575 /*
6576 * Set association flag according to if an
6577 * expander is used or not.
6578 */
6579 exp_flag =
6580 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE;
6581 if (flags ==
6582 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) {
6583 flags = exp_flag;
6584 }
6585 /*
6586 * Target device is removed from the system
6587 * Before the device is really offline from
6588 * from system.
6589 */
6590 ptgt = mptsas_search_by_devhdl(tgttbl,
6591 dev_handle);
6592 /*
6593 * If ptgt is NULL here, it means that the
6594 * DevHandle is not in the hash table. This is
6595 * reasonable sometimes. For example, if a
6596 * disk was pulled, then added, then pulled
6597 * again, the disk will not have been put into
6598 * the hash table because the add event will
6599 * have an invalid phymask. BUT, this does not
6600 * mean that the DevHandle is invalid. The
6601 * controller will still have a valid DevHandle
6602 * that must be removed. To do this, use the
6603 * MPTSAS_TOPO_FLAG_REMOVE_HANDLE event.
6604 */
6605 if (ptgt == NULL) {
6606 topo_node = kmem_zalloc(
6607 sizeof (mptsas_topo_change_list_t),
6608 KM_SLEEP);
6609 topo_node->mpt = mpt;
6610 topo_node->un.phymask = 0;
6611 topo_node->event =
6612 MPTSAS_TOPO_FLAG_REMOVE_HANDLE;
6613 topo_node->devhdl = dev_handle;
6614 topo_node->flags = flags;
6615 topo_node->object = NULL;
6616 if (topo_head == NULL) {
6617 topo_head = topo_tail =
6618 topo_node;
6619 } else {
6620 topo_tail->next = topo_node;
6621 topo_tail = topo_node;
6622 }
6623 break;
6624 }
6625
6626 /*
6627 * Update DR flag immediately avoid I/O failure
6628 * before failover finish. Pay attention to the
6629 * mutex protect, we need grab m_tx_waitq_mutex
6630 * during set m_dr_flag because we won't add
6631 * the following command into waitq, instead,
6632 * we need return TRAN_BUSY in the tran_start
6633 * context.
6634 */
6635 mutex_enter(&mpt->m_tx_waitq_mutex);
6636 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
6637 mutex_exit(&mpt->m_tx_waitq_mutex);
6638
6639 topo_node = kmem_zalloc(
6640 sizeof (mptsas_topo_change_list_t),
6641 KM_SLEEP);
6642 topo_node->mpt = mpt;
6643 topo_node->un.phymask = ptgt->m_phymask;
6644 topo_node->event =
6645 MPTSAS_DR_EVENT_OFFLINE_TARGET;
6646 topo_node->devhdl = dev_handle;
6647 topo_node->flags = flags;
6648 topo_node->object = NULL;
6649 if (topo_head == NULL) {
6650 topo_head = topo_tail = topo_node;
6651 } else {
6652 topo_tail->next = topo_node;
6653 topo_tail = topo_node;
6654 }
6655 break;
6656 }
6657 case MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED:
6658 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl,
6659 &sas_topo_change_list->PHY[i].LinkRate);
6660 state = (link_rate &
6661 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >>
6662 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT;
6663 pSmhba = &mpt->m_phy_info[i].smhba_info;
6664 pSmhba->negotiated_link_rate = state;
6665 switch (state) {
6666 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
6667 (void) sprintf(curr, "is disabled");
6668 mptsas_smhba_log_sysevent(mpt,
6669 ESC_SAS_PHY_EVENT,
6670 SAS_PHY_REMOVE,
6671 &mpt->m_phy_info[i].smhba_info);
6672 mpt->m_phy_info[i].smhba_info.
6673 negotiated_link_rate
6674 = 0x1;
6675 break;
6676 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
6677 (void) sprintf(curr, "is offline, "
6678 "failed speed negotiation");
6679 mptsas_smhba_log_sysevent(mpt,
6680 ESC_SAS_PHY_EVENT,
6681 SAS_PHY_OFFLINE,
6682 &mpt->m_phy_info[i].smhba_info);
6683 break;
6684 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
6685 (void) sprintf(curr, "SATA OOB "
6686 "complete");
6687 break;
6688 case SMP_RESET_IN_PROGRESS:
6689 (void) sprintf(curr, "SMP reset in "
6690 "progress");
6691 break;
6692 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
6693 (void) sprintf(curr, "is online at "
6694 "1.5 Gbps");
6695 if ((expd_handle == 0) &&
6696 (enc_handle == 1)) {
6697 mpt->m_port_chng = 1;
6698 }
6699 mptsas_smhba_log_sysevent(mpt,
6700 ESC_SAS_PHY_EVENT,
6701 SAS_PHY_ONLINE,
6702 &mpt->m_phy_info[i].smhba_info);
6703 break;
6704 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
6705 (void) sprintf(curr, "is online at 3.0 "
6706 "Gbps");
6707 if ((expd_handle == 0) &&
6708 (enc_handle == 1)) {
6709 mpt->m_port_chng = 1;
6710 }
6711 mptsas_smhba_log_sysevent(mpt,
6712 ESC_SAS_PHY_EVENT,
6713 SAS_PHY_ONLINE,
6714 &mpt->m_phy_info[i].smhba_info);
6715 break;
6716 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
6717 (void) sprintf(curr, "is online at "
6718 "6.0 Gbps");
6719 if ((expd_handle == 0) &&
6720 (enc_handle == 1)) {
6721 mpt->m_port_chng = 1;
6722 }
6723 mptsas_smhba_log_sysevent(mpt,
6724 ESC_SAS_PHY_EVENT,
6725 SAS_PHY_ONLINE,
6726 &mpt->m_phy_info[i].smhba_info);
6727 break;
6728 default:
6729 (void) sprintf(curr, "state is "
6730 "unknown");
6731 break;
6732 }
6733
6734 state = (link_rate &
6735 MPI2_EVENT_SAS_TOPO_LR_PREV_MASK) >>
6736 MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT;
6737 switch (state) {
6738 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
6739 (void) sprintf(prev, ", was disabled");
6740 break;
6741 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
6742 (void) sprintf(prev, ", was offline, "
6743 "failed speed negotiation");
6744 break;
6745 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
6746 (void) sprintf(prev, ", was SATA OOB "
6747 "complete");
6748 break;
6749 case SMP_RESET_IN_PROGRESS:
6750 (void) sprintf(prev, ", was SMP reset "
6751 "in progress");
6752 break;
6753 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
6754 (void) sprintf(prev, ", was online at "
6755 "1.5 Gbps");
6756 break;
6757 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
6758 (void) sprintf(prev, ", was online at "
6759 "3.0 Gbps");
6760 break;
6761 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
6762 (void) sprintf(prev, ", was online at "
6763 "6.0 Gbps");
6764 break;
6765 default:
6766 break;
6767 }
6768 (void) sprintf(&string[strlen(string)], "link "
6769 "changed, ");
6770 break;
6771 case MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE:
6772 continue;
6773 case MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING:
6774 (void) sprintf(&string[strlen(string)],
6775 "target not responding, delaying "
6776 "removal");
6777 break;
6778 }
6779 NDBG20(("mptsas%d phy %d DevHandle %x, %s%s%s\n",
6780 mpt->m_instance, phy, dev_handle, string, curr,
6781 prev));
6782 }
6783 if (topo_head != NULL) {
6784 /*
6785 * Launch DR taskq to handle topology change
6786 */
6787 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
6788 mptsas_handle_dr, (void *)topo_head,
6789 DDI_NOSLEEP)) != DDI_SUCCESS) {
6790 mptsas_log(mpt, CE_NOTE, "mptsas start taskq "
6791 "for handle SAS DR event failed. \n");
6792 }
6793 }
6794 break;
6795 }
6796 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
6797 {
6798 Mpi2EventDataIrConfigChangeList_t *irChangeList;
6799 mptsas_topo_change_list_t *topo_head = NULL;
6800 mptsas_topo_change_list_t *topo_tail = NULL;
6801 mptsas_topo_change_list_t *topo_node = NULL;
6802 mptsas_target_t *ptgt;
6803 mptsas_hash_table_t *tgttbl;
6804 uint8_t num_entries, i, reason;
6805 uint16_t volhandle, diskhandle;
6806
6807 irChangeList = (pMpi2EventDataIrConfigChangeList_t)
6808 eventreply->EventData;
6809 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl,
6810 &irChangeList->NumElements);
6811
6812 tgttbl = &mpt->m_active->m_tgttbl;
6813
6814 NDBG20(("mptsas%d IR_CONFIGURATION_CHANGE_LIST event received",
6815 mpt->m_instance));
6816
6817 for (i = 0; i < num_entries; i++) {
6818 reason = ddi_get8(mpt->m_acc_reply_frame_hdl,
6819 &irChangeList->ConfigElement[i].ReasonCode);
6820 volhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6821 &irChangeList->ConfigElement[i].VolDevHandle);
6822 diskhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6823 &irChangeList->ConfigElement[i].PhysDiskDevHandle);
6824
6825 switch (reason) {
6826 case MPI2_EVENT_IR_CHANGE_RC_ADDED:
6827 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED:
6828 {
6829 NDBG20(("mptsas %d volume added\n",
6830 mpt->m_instance));
6831
6832 topo_node = kmem_zalloc(
6833 sizeof (mptsas_topo_change_list_t),
6834 KM_SLEEP);
6835
6836 topo_node->mpt = mpt;
6837 topo_node->event =
6838 MPTSAS_DR_EVENT_RECONFIG_TARGET;
6839 topo_node->un.physport = 0xff;
6840 topo_node->devhdl = volhandle;
6841 topo_node->flags =
6842 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED;
6843 topo_node->object = NULL;
6844 if (topo_head == NULL) {
6845 topo_head = topo_tail = topo_node;
6846 } else {
6847 topo_tail->next = topo_node;
6848 topo_tail = topo_node;
6849 }
6850 break;
6851 }
6852 case MPI2_EVENT_IR_CHANGE_RC_REMOVED:
6853 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED:
6854 {
6855 NDBG20(("mptsas %d volume deleted\n",
6856 mpt->m_instance));
6857 ptgt = mptsas_search_by_devhdl(tgttbl,
6858 volhandle);
6859 if (ptgt == NULL)
6860 break;
6861
6862 /*
6863 * Clear any flags related to volume
6864 */
6865 (void) mptsas_delete_volume(mpt, volhandle);
6866
6867 /*
6868 * Update DR flag immediately avoid I/O failure
6869 */
6870 mutex_enter(&mpt->m_tx_waitq_mutex);
6871 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
6872 mutex_exit(&mpt->m_tx_waitq_mutex);
6873
6874 topo_node = kmem_zalloc(
6875 sizeof (mptsas_topo_change_list_t),
6876 KM_SLEEP);
6877 topo_node->mpt = mpt;
6878 topo_node->un.phymask = ptgt->m_phymask;
6879 topo_node->event =
6880 MPTSAS_DR_EVENT_OFFLINE_TARGET;
6881 topo_node->devhdl = volhandle;
6882 topo_node->flags =
6883 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED;
6884 topo_node->object = (void *)ptgt;
6885 if (topo_head == NULL) {
6886 topo_head = topo_tail = topo_node;
6887 } else {
6888 topo_tail->next = topo_node;
6889 topo_tail = topo_node;
6890 }
6891 break;
6892 }
6893 case MPI2_EVENT_IR_CHANGE_RC_PD_CREATED:
6894 case MPI2_EVENT_IR_CHANGE_RC_HIDE:
6895 {
6896 ptgt = mptsas_search_by_devhdl(tgttbl,
6897 diskhandle);
6898 if (ptgt == NULL)
6899 break;
6900
6901 /*
6902 * Update DR flag immediately avoid I/O failure
6903 */
6904 mutex_enter(&mpt->m_tx_waitq_mutex);
6905 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
6906 mutex_exit(&mpt->m_tx_waitq_mutex);
6907
6908 topo_node = kmem_zalloc(
6909 sizeof (mptsas_topo_change_list_t),
6910 KM_SLEEP);
6911 topo_node->mpt = mpt;
6912 topo_node->un.phymask = ptgt->m_phymask;
6913 topo_node->event =
6914 MPTSAS_DR_EVENT_OFFLINE_TARGET;
6915 topo_node->devhdl = diskhandle;
6916 topo_node->flags =
6917 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED;
6918 topo_node->object = (void *)ptgt;
6919 if (topo_head == NULL) {
6920 topo_head = topo_tail = topo_node;
6921 } else {
6922 topo_tail->next = topo_node;
6923 topo_tail = topo_node;
6924 }
6925 break;
6926 }
6927 case MPI2_EVENT_IR_CHANGE_RC_UNHIDE:
6928 case MPI2_EVENT_IR_CHANGE_RC_PD_DELETED:
6929 {
6930 /*
6931 * The physical drive is released by a IR
6932 * volume. But we cannot get the the physport
6933 * or phynum from the event data, so we only
6934 * can get the physport/phynum after SAS
6935 * Device Page0 request for the devhdl.
6936 */
6937 topo_node = kmem_zalloc(
6938 sizeof (mptsas_topo_change_list_t),
6939 KM_SLEEP);
6940 topo_node->mpt = mpt;
6941 topo_node->un.phymask = 0;
6942 topo_node->event =
6943 MPTSAS_DR_EVENT_RECONFIG_TARGET;
6944 topo_node->devhdl = diskhandle;
6945 topo_node->flags =
6946 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED;
6947 topo_node->object = NULL;
6948 mpt->m_port_chng = 1;
6949 if (topo_head == NULL) {
6950 topo_head = topo_tail = topo_node;
6951 } else {
6952 topo_tail->next = topo_node;
6953 topo_tail = topo_node;
6954 }
6955 break;
6956 }
6957 default:
6958 break;
6959 }
6960 }
6961
6962 if (topo_head != NULL) {
6963 /*
6964 * Launch DR taskq to handle topology change
6965 */
6966 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
6967 mptsas_handle_dr, (void *)topo_head,
6968 DDI_NOSLEEP)) != DDI_SUCCESS) {
6969 mptsas_log(mpt, CE_NOTE, "mptsas start taskq "
6970 "for handle SAS DR event failed. \n");
6971 }
6972 }
6973 break;
6974 }
6975 default:
6976 return (DDI_FAILURE);
6977 }
6978
6979 return (DDI_SUCCESS);
6980 }
6981
6982 /*
6983 * handle events from ioc
6984 */
6985 static void
6986 mptsas_handle_event(void *args)
6987 {
6988 m_replyh_arg_t *replyh_arg;
6989 pMpi2EventNotificationReply_t eventreply;
6990 uint32_t event, iocloginfo, rfm;
6991 uint32_t status;
6992 uint8_t port;
6993 mptsas_t *mpt;
6994 uint_t iocstatus;
6995
6996 replyh_arg = (m_replyh_arg_t *)args;
6997 rfm = replyh_arg->rfm;
6998 mpt = replyh_arg->mpt;
6999
7000 mutex_enter(&mpt->m_mutex);
7001 /*
7002 * If HBA is being reset, drop incoming event.
7003 */
7004 if (mpt->m_in_reset) {
7005 NDBG20(("dropping event received prior to reset"));
7006 mutex_exit(&mpt->m_mutex);
7007 return;
7008 }
7009
7010 eventreply = (pMpi2EventNotificationReply_t)
7011 (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr));
7012 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
7013
7014 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
7015 &eventreply->IOCStatus)) {
7016 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
7017 mptsas_log(mpt, CE_WARN,
7018 "!mptsas_handle_event: IOCStatus=0x%x, "
7019 "IOCLogInfo=0x%x", iocstatus,
7020 ddi_get32(mpt->m_acc_reply_frame_hdl,
7021 &eventreply->IOCLogInfo));
7022 } else {
7023 mptsas_log(mpt, CE_WARN,
7024 "mptsas_handle_event: IOCStatus=0x%x, "
7025 "IOCLogInfo=0x%x", iocstatus,
7026 ddi_get32(mpt->m_acc_reply_frame_hdl,
7027 &eventreply->IOCLogInfo));
7028 }
7029 }
7030
7031 /*
7032 * figure out what kind of event we got and handle accordingly
7033 */
7034 switch (event) {
7035 case MPI2_EVENT_LOG_ENTRY_ADDED:
7036 break;
7037 case MPI2_EVENT_LOG_DATA:
7038 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
7039 &eventreply->IOCLogInfo);
7040 NDBG20(("mptsas %d log info %x received.\n", mpt->m_instance,
7041 iocloginfo));
7042 break;
7043 case MPI2_EVENT_STATE_CHANGE:
7044 NDBG20(("mptsas%d state change.", mpt->m_instance));
7045 break;
7046 case MPI2_EVENT_HARD_RESET_RECEIVED:
7047 NDBG20(("mptsas%d event change.", mpt->m_instance));
7048 break;
7049 case MPI2_EVENT_SAS_DISCOVERY:
7050 {
7051 MPI2_EVENT_DATA_SAS_DISCOVERY *sasdiscovery;
7052 char string[80];
7053 uint8_t rc;
7054
7055 sasdiscovery =
7056 (pMpi2EventDataSasDiscovery_t)eventreply->EventData;
7057
7058 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7059 &sasdiscovery->ReasonCode);
7060 port = ddi_get8(mpt->m_acc_reply_frame_hdl,
7061 &sasdiscovery->PhysicalPort);
7062 status = ddi_get32(mpt->m_acc_reply_frame_hdl,
7063 &sasdiscovery->DiscoveryStatus);
7064
7065 string[0] = 0;
7066 switch (rc) {
7067 case MPI2_EVENT_SAS_DISC_RC_STARTED:
7068 (void) sprintf(string, "STARTING");
7069 break;
7070 case MPI2_EVENT_SAS_DISC_RC_COMPLETED:
7071 (void) sprintf(string, "COMPLETED");
7072 break;
7073 default:
7074 (void) sprintf(string, "UNKNOWN");
7075 break;
7076 }
7077
7078 NDBG20(("SAS DISCOVERY is %s for port %d, status %x", string,
7079 port, status));
7080
7081 break;
7082 }
7083 case MPI2_EVENT_EVENT_CHANGE:
7084 NDBG20(("mptsas%d event change.", mpt->m_instance));
7085 break;
7086 case MPI2_EVENT_TASK_SET_FULL:
7087 {
7088 pMpi2EventDataTaskSetFull_t taskfull;
7089
7090 taskfull = (pMpi2EventDataTaskSetFull_t)eventreply->EventData;
7091
7092 NDBG20(("TASK_SET_FULL received for mptsas%d, depth %d\n",
7093 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl,
7094 &taskfull->CurrentDepth)));
7095 break;
7096 }
7097 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
7098 {
7099 /*
7100 * SAS TOPOLOGY CHANGE LIST Event has already been handled
7101 * in mptsas_handle_event_sync() of interrupt context
7102 */
7103 break;
7104 }
7105 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
7106 {
7107 pMpi2EventDataSasEnclDevStatusChange_t encstatus;
7108 uint8_t rc;
7109 char string[80];
7110
7111 encstatus = (pMpi2EventDataSasEnclDevStatusChange_t)
7112 eventreply->EventData;
7113
7114 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7115 &encstatus->ReasonCode);
7116 switch (rc) {
7117 case MPI2_EVENT_SAS_ENCL_RC_ADDED:
7118 (void) sprintf(string, "added");
7119 break;
7120 case MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING:
7121 (void) sprintf(string, ", not responding");
7122 break;
7123 default:
7124 break;
7125 }
7126 NDBG20(("mptsas%d ENCLOSURE STATUS CHANGE for enclosure %x%s\n",
7127 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl,
7128 &encstatus->EnclosureHandle), string));
7129 break;
7130 }
7131
7132 /*
7133 * MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE is handled by
7134 * mptsas_handle_event_sync,in here just send ack message.
7135 */
7136 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
7137 {
7138 pMpi2EventDataSasDeviceStatusChange_t statuschange;
7139 uint8_t rc;
7140 uint16_t devhdl;
7141 uint64_t wwn = 0;
7142 uint32_t wwn_lo, wwn_hi;
7143
7144 statuschange = (pMpi2EventDataSasDeviceStatusChange_t)
7145 eventreply->EventData;
7146 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7147 &statuschange->ReasonCode);
7148 wwn_lo = ddi_get32(mpt->m_acc_reply_frame_hdl,
7149 (uint32_t *)(void *)&statuschange->SASAddress);
7150 wwn_hi = ddi_get32(mpt->m_acc_reply_frame_hdl,
7151 (uint32_t *)(void *)&statuschange->SASAddress + 1);
7152 wwn = ((uint64_t)wwn_hi << 32) | wwn_lo;
7153 devhdl = ddi_get16(mpt->m_acc_reply_frame_hdl,
7154 &statuschange->DevHandle);
7155
7156 NDBG13(("MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE wwn is %"PRIx64,
7157 wwn));
7158
7159 switch (rc) {
7160 case MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA:
7161 NDBG20(("SMART data received, ASC/ASCQ = %02x/%02x",
7162 ddi_get8(mpt->m_acc_reply_frame_hdl,
7163 &statuschange->ASC),
7164 ddi_get8(mpt->m_acc_reply_frame_hdl,
7165 &statuschange->ASCQ)));
7166 break;
7167
7168 case MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED:
7169 NDBG20(("Device not supported"));
7170 break;
7171
7172 case MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET:
7173 NDBG20(("IOC internally generated the Target Reset "
7174 "for devhdl:%x", devhdl));
7175 break;
7176
7177 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET:
7178 NDBG20(("IOC's internally generated Target Reset "
7179 "completed for devhdl:%x", devhdl));
7180 break;
7181
7182 case MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL:
7183 NDBG20(("IOC internally generated Abort Task"));
7184 break;
7185
7186 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL:
7187 NDBG20(("IOC's internally generated Abort Task "
7188 "completed"));
7189 break;
7190
7191 case MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL:
7192 NDBG20(("IOC internally generated Abort Task Set"));
7193 break;
7194
7195 case MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL:
7196 NDBG20(("IOC internally generated Clear Task Set"));
7197 break;
7198
7199 case MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL:
7200 NDBG20(("IOC internally generated Query Task"));
7201 break;
7202
7203 case MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION:
7204 NDBG20(("Device sent an Asynchronous Notification"));
7205 break;
7206
7207 default:
7208 break;
7209 }
7210 break;
7211 }
7212 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
7213 {
7214 /*
7215 * IR TOPOLOGY CHANGE LIST Event has already been handled
7216 * in mpt_handle_event_sync() of interrupt context
7217 */
7218 break;
7219 }
7220 case MPI2_EVENT_IR_OPERATION_STATUS:
7221 {
7222 Mpi2EventDataIrOperationStatus_t *irOpStatus;
7223 char reason_str[80];
7224 uint8_t rc, percent;
7225 uint16_t handle;
7226
7227 irOpStatus = (pMpi2EventDataIrOperationStatus_t)
7228 eventreply->EventData;
7229 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7230 &irOpStatus->RAIDOperation);
7231 percent = ddi_get8(mpt->m_acc_reply_frame_hdl,
7232 &irOpStatus->PercentComplete);
7233 handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7234 &irOpStatus->VolDevHandle);
7235
7236 switch (rc) {
7237 case MPI2_EVENT_IR_RAIDOP_RESYNC:
7238 (void) sprintf(reason_str, "resync");
7239 break;
7240 case MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION:
7241 (void) sprintf(reason_str, "online capacity "
7242 "expansion");
7243 break;
7244 case MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK:
7245 (void) sprintf(reason_str, "consistency check");
7246 break;
7247 default:
7248 (void) sprintf(reason_str, "unknown reason %x",
7249 rc);
7250 }
7251
7252 NDBG20(("mptsas%d raid operational status: (%s)"
7253 "\thandle(0x%04x), percent complete(%d)\n",
7254 mpt->m_instance, reason_str, handle, percent));
7255 break;
7256 }
7257 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
7258 {
7259 pMpi2EventDataSasBroadcastPrimitive_t sas_broadcast;
7260 uint8_t phy_num;
7261 uint8_t primitive;
7262
7263 sas_broadcast = (pMpi2EventDataSasBroadcastPrimitive_t)
7264 eventreply->EventData;
7265
7266 phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl,
7267 &sas_broadcast->PhyNum);
7268 primitive = ddi_get8(mpt->m_acc_reply_frame_hdl,
7269 &sas_broadcast->Primitive);
7270
7271 switch (primitive) {
7272 case MPI2_EVENT_PRIMITIVE_CHANGE:
7273 mptsas_smhba_log_sysevent(mpt,
7274 ESC_SAS_HBA_PORT_BROADCAST,
7275 SAS_PORT_BROADCAST_CHANGE,
7276 &mpt->m_phy_info[phy_num].smhba_info);
7277 break;
7278 case MPI2_EVENT_PRIMITIVE_SES:
7279 mptsas_smhba_log_sysevent(mpt,
7280 ESC_SAS_HBA_PORT_BROADCAST,
7281 SAS_PORT_BROADCAST_SES,
7282 &mpt->m_phy_info[phy_num].smhba_info);
7283 break;
7284 case MPI2_EVENT_PRIMITIVE_EXPANDER:
7285 mptsas_smhba_log_sysevent(mpt,
7286 ESC_SAS_HBA_PORT_BROADCAST,
7287 SAS_PORT_BROADCAST_D01_4,
7288 &mpt->m_phy_info[phy_num].smhba_info);
7289 break;
7290 case MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT:
7291 mptsas_smhba_log_sysevent(mpt,
7292 ESC_SAS_HBA_PORT_BROADCAST,
7293 SAS_PORT_BROADCAST_D04_7,
7294 &mpt->m_phy_info[phy_num].smhba_info);
7295 break;
7296 case MPI2_EVENT_PRIMITIVE_RESERVED3:
7297 mptsas_smhba_log_sysevent(mpt,
7298 ESC_SAS_HBA_PORT_BROADCAST,
7299 SAS_PORT_BROADCAST_D16_7,
7300 &mpt->m_phy_info[phy_num].smhba_info);
7301 break;
7302 case MPI2_EVENT_PRIMITIVE_RESERVED4:
7303 mptsas_smhba_log_sysevent(mpt,
7304 ESC_SAS_HBA_PORT_BROADCAST,
7305 SAS_PORT_BROADCAST_D29_7,
7306 &mpt->m_phy_info[phy_num].smhba_info);
7307 break;
7308 case MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED:
7309 mptsas_smhba_log_sysevent(mpt,
7310 ESC_SAS_HBA_PORT_BROADCAST,
7311 SAS_PORT_BROADCAST_D24_0,
7312 &mpt->m_phy_info[phy_num].smhba_info);
7313 break;
7314 case MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED:
7315 mptsas_smhba_log_sysevent(mpt,
7316 ESC_SAS_HBA_PORT_BROADCAST,
7317 SAS_PORT_BROADCAST_D27_4,
7318 &mpt->m_phy_info[phy_num].smhba_info);
7319 break;
7320 default:
7321 NDBG20(("mptsas%d: unknown BROADCAST PRIMITIVE"
7322 " %x received",
7323 mpt->m_instance, primitive));
7324 break;
7325 }
7326 NDBG20(("mptsas%d sas broadcast primitive: "
7327 "\tprimitive(0x%04x), phy(%d) complete\n",
7328 mpt->m_instance, primitive, phy_num));
7329 break;
7330 }
7331 case MPI2_EVENT_IR_VOLUME:
7332 {
7333 Mpi2EventDataIrVolume_t *irVolume;
7334 uint16_t devhandle;
7335 uint32_t state;
7336 int config, vol;
7337 mptsas_slots_t *slots = mpt->m_active;
7338 uint8_t found = FALSE;
7339
7340 irVolume = (pMpi2EventDataIrVolume_t)eventreply->EventData;
7341 state = ddi_get32(mpt->m_acc_reply_frame_hdl,
7342 &irVolume->NewValue);
7343 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7344 &irVolume->VolDevHandle);
7345
7346 NDBG20(("EVENT_IR_VOLUME event is received"));
7347
7348 /*
7349 * Get latest RAID info and then find the DevHandle for this
7350 * event in the configuration. If the DevHandle is not found
7351 * just exit the event.
7352 */
7353 (void) mptsas_get_raid_info(mpt);
7354 for (config = 0; (config < slots->m_num_raid_configs) &&
7355 (!found); config++) {
7356 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) {
7357 if (slots->m_raidconfig[config].m_raidvol[vol].
7358 m_raidhandle == devhandle) {
7359 found = TRUE;
7360 break;
7361 }
7362 }
7363 }
7364 if (!found) {
7365 break;
7366 }
7367
7368 switch (irVolume->ReasonCode) {
7369 case MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED:
7370 {
7371 uint32_t i;
7372 slots->m_raidconfig[config].m_raidvol[vol].m_settings =
7373 state;
7374
7375 i = state & MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING;
7376 mptsas_log(mpt, CE_NOTE, " Volume %d settings changed"
7377 ", auto-config of hot-swap drives is %s"
7378 ", write caching is %s"
7379 ", hot-spare pool mask is %02x\n",
7380 vol, state &
7381 MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE
7382 ? "disabled" : "enabled",
7383 i == MPI2_RAIDVOL0_SETTING_UNCHANGED
7384 ? "controlled by member disks" :
7385 i == MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING
7386 ? "disabled" :
7387 i == MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING
7388 ? "enabled" :
7389 "incorrectly set",
7390 (state >> 16) & 0xff);
7391 break;
7392 }
7393 case MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED:
7394 {
7395 slots->m_raidconfig[config].m_raidvol[vol].m_state =
7396 (uint8_t)state;
7397
7398 mptsas_log(mpt, CE_NOTE,
7399 "Volume %d is now %s\n", vol,
7400 state == MPI2_RAID_VOL_STATE_OPTIMAL
7401 ? "optimal" :
7402 state == MPI2_RAID_VOL_STATE_DEGRADED
7403 ? "degraded" :
7404 state == MPI2_RAID_VOL_STATE_ONLINE
7405 ? "online" :
7406 state == MPI2_RAID_VOL_STATE_INITIALIZING
7407 ? "initializing" :
7408 state == MPI2_RAID_VOL_STATE_FAILED
7409 ? "failed" :
7410 state == MPI2_RAID_VOL_STATE_MISSING
7411 ? "missing" :
7412 "state unknown");
7413 break;
7414 }
7415 case MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED:
7416 {
7417 slots->m_raidconfig[config].m_raidvol[vol].
7418 m_statusflags = state;
7419
7420 mptsas_log(mpt, CE_NOTE,
7421 " Volume %d is now %s%s%s%s%s%s%s%s%s\n",
7422 vol,
7423 state & MPI2_RAIDVOL0_STATUS_FLAG_ENABLED
7424 ? ", enabled" : ", disabled",
7425 state & MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED
7426 ? ", quiesced" : "",
7427 state & MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE
7428 ? ", inactive" : ", active",
7429 state &
7430 MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL
7431 ? ", bad block table is full" : "",
7432 state &
7433 MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS
7434 ? ", resync in progress" : "",
7435 state & MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT
7436 ? ", background initialization in progress" : "",
7437 state &
7438 MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION
7439 ? ", capacity expansion in progress" : "",
7440 state &
7441 MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK
7442 ? ", consistency check in progress" : "",
7443 state & MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB
7444 ? ", data scrub in progress" : "");
7445 break;
7446 }
7447 default:
7448 break;
7449 }
7450 break;
7451 }
7452 case MPI2_EVENT_IR_PHYSICAL_DISK:
7453 {
7454 Mpi2EventDataIrPhysicalDisk_t *irPhysDisk;
7455 uint16_t devhandle, enchandle, slot;
7456 uint32_t status, state;
7457 uint8_t physdisknum, reason;
7458
7459 irPhysDisk = (Mpi2EventDataIrPhysicalDisk_t *)
7460 eventreply->EventData;
7461 physdisknum = ddi_get8(mpt->m_acc_reply_frame_hdl,
7462 &irPhysDisk->PhysDiskNum);
7463 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7464 &irPhysDisk->PhysDiskDevHandle);
7465 enchandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7466 &irPhysDisk->EnclosureHandle);
7467 slot = ddi_get16(mpt->m_acc_reply_frame_hdl,
7468 &irPhysDisk->Slot);
7469 state = ddi_get32(mpt->m_acc_reply_frame_hdl,
7470 &irPhysDisk->NewValue);
7471 reason = ddi_get8(mpt->m_acc_reply_frame_hdl,
7472 &irPhysDisk->ReasonCode);
7473
7474 NDBG20(("EVENT_IR_PHYSICAL_DISK event is received"));
7475
7476 switch (reason) {
7477 case MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED:
7478 mptsas_log(mpt, CE_NOTE,
7479 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
7480 "for enclosure with handle 0x%x is now in hot "
7481 "spare pool %d",
7482 physdisknum, devhandle, slot, enchandle,
7483 (state >> 16) & 0xff);
7484 break;
7485
7486 case MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED:
7487 status = state;
7488 mptsas_log(mpt, CE_NOTE,
7489 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
7490 "for enclosure with handle 0x%x is now "
7491 "%s%s%s%s%s\n", physdisknum, devhandle, slot,
7492 enchandle,
7493 status & MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME
7494 ? ", inactive" : ", active",
7495 status & MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC
7496 ? ", out of sync" : "",
7497 status & MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED
7498 ? ", quiesced" : "",
7499 status &
7500 MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED
7501 ? ", write cache enabled" : "",
7502 status & MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET
7503 ? ", capacity expansion target" : "");
7504 break;
7505
7506 case MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED:
7507 mptsas_log(mpt, CE_NOTE,
7508 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
7509 "for enclosure with handle 0x%x is now %s\n",
7510 physdisknum, devhandle, slot, enchandle,
7511 state == MPI2_RAID_PD_STATE_OPTIMAL
7512 ? "optimal" :
7513 state == MPI2_RAID_PD_STATE_REBUILDING
7514 ? "rebuilding" :
7515 state == MPI2_RAID_PD_STATE_DEGRADED
7516 ? "degraded" :
7517 state == MPI2_RAID_PD_STATE_HOT_SPARE
7518 ? "a hot spare" :
7519 state == MPI2_RAID_PD_STATE_ONLINE
7520 ? "online" :
7521 state == MPI2_RAID_PD_STATE_OFFLINE
7522 ? "offline" :
7523 state == MPI2_RAID_PD_STATE_NOT_COMPATIBLE
7524 ? "not compatible" :
7525 state == MPI2_RAID_PD_STATE_NOT_CONFIGURED
7526 ? "not configured" :
7527 "state unknown");
7528 break;
7529 }
7530 break;
7531 }
7532 default:
7533 NDBG20(("mptsas%d: unknown event %x received",
7534 mpt->m_instance, event));
7535 break;
7536 }
7537
7538 /*
7539 * Return the reply frame to the free queue.
7540 */
7541 ddi_put32(mpt->m_acc_free_queue_hdl,
7542 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], rfm);
7543 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
7544 DDI_DMA_SYNC_FORDEV);
7545 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
7546 mpt->m_free_index = 0;
7547 }
7548 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
7549 mpt->m_free_index);
7550 mutex_exit(&mpt->m_mutex);
7551 }
7552
7553 /*
7554 * invoked from timeout() to restart qfull cmds with throttle == 0
7555 */
7556 static void
7557 mptsas_restart_cmd(void *arg)
7558 {
7559 mptsas_t *mpt = arg;
7560 mptsas_target_t *ptgt = NULL;
7561
7562 mutex_enter(&mpt->m_mutex);
7563
7564 mpt->m_restart_cmd_timeid = 0;
7565
7566 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
7567 MPTSAS_HASH_FIRST);
7568 while (ptgt != NULL) {
7569 if (ptgt->m_reset_delay == 0) {
7570 if (ptgt->m_t_throttle == QFULL_THROTTLE) {
7571 mptsas_set_throttle(mpt, ptgt,
7572 MAX_THROTTLE);
7573 }
7574 }
7575
7576 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
7577 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
7578 }
7579 mptsas_restart_hba(mpt);
7580 mutex_exit(&mpt->m_mutex);
7581 }
7582
7583 void
7584 mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
7585 {
7586 int slot;
7587 mptsas_slots_t *slots = mpt->m_active;
7588 int t;
7589 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
7590
7591 ASSERT(cmd != NULL);
7592 ASSERT(cmd->cmd_queued == FALSE);
7593
7594 /*
7595 * Task Management cmds are removed in their own routines. Also,
7596 * we don't want to modify timeout based on TM cmds.
7597 */
7598 if (cmd->cmd_flags & CFLAG_TM_CMD) {
7599 return;
7600 }
7601
7602 t = Tgt(cmd);
7603 slot = cmd->cmd_slot;
7604
7605 /*
7606 * remove the cmd.
7607 */
7608 if (cmd == slots->m_slot[slot]) {
7609 NDBG31(("mptsas_remove_cmd: removing cmd=0x%p", (void *)cmd));
7610 slots->m_slot[slot] = NULL;
7611 mpt->m_ncmds--;
7612
7613 /*
7614 * only decrement per target ncmds if command
7615 * has a target associated with it.
7616 */
7617 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
7618 ptgt->m_t_ncmds--;
7619 /*
7620 * reset throttle if we just ran an untagged command
7621 * to a tagged target
7622 */
7623 if ((ptgt->m_t_ncmds == 0) &&
7624 ((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0)) {
7625 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
7626 }
7627 }
7628
7629 }
7630
7631 /*
7632 * This is all we need to do for ioc commands.
7633 */
7634 if (cmd->cmd_flags & CFLAG_CMDIOC) {
7635 mptsas_return_to_pool(mpt, cmd);
7636 return;
7637 }
7638
7639 /*
7640 * Figure out what to set tag Q timeout for...
7641 *
7642 * Optimize: If we have duplicate's of same timeout
7643 * we're using, then we'll use it again until we run
7644 * out of duplicates. This should be the normal case
7645 * for block and raw I/O.
7646 * If no duplicates, we have to scan through tag que and
7647 * find the longest timeout value and use it. This is
7648 * going to take a while...
7649 * Add 1 to m_n_slots to account for TM request.
7650 */
7651 if (cmd->cmd_pkt->pkt_time == ptgt->m_timebase) {
7652 if (--(ptgt->m_dups) == 0) {
7653 if (ptgt->m_t_ncmds) {
7654 mptsas_cmd_t *ssp;
7655 uint_t n = 0;
7656 ushort_t nslots = (slots->m_n_slots + 1);
7657 ushort_t i;
7658 /*
7659 * This crude check assumes we don't do
7660 * this too often which seems reasonable
7661 * for block and raw I/O.
7662 */
7663 for (i = 0; i < nslots; i++) {
7664 ssp = slots->m_slot[i];
7665 if (ssp && (Tgt(ssp) == t) &&
7666 (ssp->cmd_pkt->pkt_time > n)) {
7667 n = ssp->cmd_pkt->pkt_time;
7668 ptgt->m_dups = 1;
7669 } else if (ssp && (Tgt(ssp) == t) &&
7670 (ssp->cmd_pkt->pkt_time == n)) {
7671 ptgt->m_dups++;
7672 }
7673 }
7674 ptgt->m_timebase = n;
7675 } else {
7676 ptgt->m_dups = 0;
7677 ptgt->m_timebase = 0;
7678 }
7679 }
7680 }
7681 ptgt->m_timeout = ptgt->m_timebase;
7682
7683 ASSERT(cmd != slots->m_slot[cmd->cmd_slot]);
7684 }
7685
7686 /*
7687 * accept all cmds on the tx_waitq if any and then
7688 * start a fresh request from the top of the device queue.
7689 *
7690 * since there are always cmds queued on the tx_waitq, and rare cmds on
7691 * the instance waitq, so this function should not be invoked in the ISR,
7692 * the mptsas_restart_waitq() is invoked in the ISR instead. otherwise, the
7693 * burden belongs to the IO dispatch CPUs is moved the interrupt CPU.
7694 */
7695 static void
7696 mptsas_restart_hba(mptsas_t *mpt)
7697 {
7698 ASSERT(mutex_owned(&mpt->m_mutex));
7699
7700 mutex_enter(&mpt->m_tx_waitq_mutex);
7701 if (mpt->m_tx_waitq) {
7702 mptsas_accept_tx_waitq(mpt);
7703 }
7704 mutex_exit(&mpt->m_tx_waitq_mutex);
7705 mptsas_restart_waitq(mpt);
7706 }
7707
7708 /*
7709 * start a fresh request from the top of the device queue
7710 */
7711 static void
7712 mptsas_restart_waitq(mptsas_t *mpt)
7713 {
7714 mptsas_cmd_t *cmd, *next_cmd;
7715 mptsas_target_t *ptgt = NULL;
7716
7717 NDBG1(("mptsas_restart_waitq: mpt=0x%p", (void *)mpt));
7718
7719 ASSERT(mutex_owned(&mpt->m_mutex));
7720
7721 /*
7722 * If there is a reset delay, don't start any cmds. Otherwise, start
7723 * as many cmds as possible.
7724 * Since SMID 0 is reserved and the TM slot is reserved, the actual max
7725 * commands is m_max_requests - 2.
7726 */
7727 cmd = mpt->m_waitq;
7728
7729 while (cmd != NULL) {
7730 next_cmd = cmd->cmd_linkp;
7731 if (cmd->cmd_flags & CFLAG_PASSTHRU) {
7732 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
7733 /*
7734 * passthru command get slot need
7735 * set CFLAG_PREPARED.
7736 */
7737 cmd->cmd_flags |= CFLAG_PREPARED;
7738 mptsas_waitq_delete(mpt, cmd);
7739 mptsas_start_passthru(mpt, cmd);
7740 }
7741 cmd = next_cmd;
7742 continue;
7743 }
7744 if (cmd->cmd_flags & CFLAG_CONFIG) {
7745 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
7746 /*
7747 * Send the config page request and delete it
7748 * from the waitq.
7749 */
7750 cmd->cmd_flags |= CFLAG_PREPARED;
7751 mptsas_waitq_delete(mpt, cmd);
7752 mptsas_start_config_page_access(mpt, cmd);
7753 }
7754 cmd = next_cmd;
7755 continue;
7756 }
7757 if (cmd->cmd_flags & CFLAG_FW_DIAG) {
7758 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
7759 /*
7760 * Send the FW Diag request and delete if from
7761 * the waitq.
7762 */
7763 cmd->cmd_flags |= CFLAG_PREPARED;
7764 mptsas_waitq_delete(mpt, cmd);
7765 mptsas_start_diag(mpt, cmd);
7766 }
7767 cmd = next_cmd;
7768 continue;
7769 }
7770
7771 ptgt = cmd->cmd_tgt_addr;
7772 if (ptgt && (ptgt->m_t_throttle == DRAIN_THROTTLE) &&
7773 (ptgt->m_t_ncmds == 0)) {
7774 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
7775 }
7776 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) &&
7777 (ptgt && (ptgt->m_reset_delay == 0)) &&
7778 (ptgt && (ptgt->m_t_ncmds <
7779 ptgt->m_t_throttle))) {
7780 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
7781 mptsas_waitq_delete(mpt, cmd);
7782 (void) mptsas_start_cmd(mpt, cmd);
7783 }
7784 }
7785 cmd = next_cmd;
7786 }
7787 }
7788 /*
7789 * Cmds are queued if tran_start() doesn't get the m_mutexlock(no wait).
7790 * Accept all those queued cmds before new cmd is accept so that the
7791 * cmds are sent in order.
7792 */
7793 static void
7794 mptsas_accept_tx_waitq(mptsas_t *mpt)
7795 {
7796 mptsas_cmd_t *cmd;
7797
7798 ASSERT(mutex_owned(&mpt->m_mutex));
7799 ASSERT(mutex_owned(&mpt->m_tx_waitq_mutex));
7800
7801 /*
7802 * A Bus Reset could occur at any time and flush the tx_waitq,
7803 * so we cannot count on the tx_waitq to contain even one cmd.
7804 * And when the m_tx_waitq_mutex is released and run
7805 * mptsas_accept_pkt(), the tx_waitq may be flushed.
7806 */
7807 cmd = mpt->m_tx_waitq;
7808 for (;;) {
7809 if ((cmd = mpt->m_tx_waitq) == NULL) {
7810 mpt->m_tx_draining = 0;
7811 break;
7812 }
7813 if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL) {
7814 mpt->m_tx_waitqtail = &mpt->m_tx_waitq;
7815 }
7816 cmd->cmd_linkp = NULL;
7817 mutex_exit(&mpt->m_tx_waitq_mutex);
7818 if (mptsas_accept_pkt(mpt, cmd) != TRAN_ACCEPT)
7819 cmn_err(CE_WARN, "mpt: mptsas_accept_tx_waitq: failed "
7820 "to accept cmd on queue\n");
7821 mutex_enter(&mpt->m_tx_waitq_mutex);
7822 }
7823 }
7824
7825
7826 /*
7827 * mpt tag type lookup
7828 */
7829 static char mptsas_tag_lookup[] =
7830 {0, MSG_HEAD_QTAG, MSG_ORDERED_QTAG, 0, MSG_SIMPLE_QTAG};
7831
7832 static int
7833 mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
7834 {
7835 struct scsi_pkt *pkt = CMD2PKT(cmd);
7836 uint32_t control = 0;
7837 int n;
7838 caddr_t mem;
7839 pMpi2SCSIIORequest_t io_request;
7840 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl;
7841 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl;
7842 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
7843 uint16_t SMID, io_flags = 0;
7844 uint32_t request_desc_low, request_desc_high;
7845
7846 NDBG1(("mptsas_start_cmd: cmd=0x%p", (void *)cmd));
7847
7848 /*
7849 * Set SMID and increment index. Rollover to 1 instead of 0 if index
7850 * is at the max. 0 is an invalid SMID, so we call the first index 1.
7851 */
7852 SMID = cmd->cmd_slot;
7853
7854 /*
7855 * It is possible for back to back device reset to
7856 * happen before the reset delay has expired. That's
7857 * ok, just let the device reset go out on the bus.
7858 */
7859 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
7860 ASSERT(ptgt->m_reset_delay == 0);
7861 }
7862
7863 /*
7864 * if a non-tagged cmd is submitted to an active tagged target
7865 * then drain before submitting this cmd; SCSI-2 allows RQSENSE
7866 * to be untagged
7867 */
7868 if (((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0) &&
7869 (ptgt->m_t_ncmds > 1) &&
7870 ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) &&
7871 (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE)) {
7872 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
7873 NDBG23(("target=%d, untagged cmd, start draining\n",
7874 ptgt->m_devhdl));
7875
7876 if (ptgt->m_reset_delay == 0) {
7877 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
7878 }
7879
7880 mptsas_remove_cmd(mpt, cmd);
7881 cmd->cmd_pkt_flags |= FLAG_HEAD;
7882 mptsas_waitq_add(mpt, cmd);
7883 }
7884 return (DDI_FAILURE);
7885 }
7886
7887 /*
7888 * Set correct tag bits.
7889 */
7890 if (cmd->cmd_pkt_flags & FLAG_TAGMASK) {
7891 switch (mptsas_tag_lookup[((cmd->cmd_pkt_flags &
7892 FLAG_TAGMASK) >> 12)]) {
7893 case MSG_SIMPLE_QTAG:
7894 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
7895 break;
7896 case MSG_HEAD_QTAG:
7897 control |= MPI2_SCSIIO_CONTROL_HEADOFQ;
7898 break;
7899 case MSG_ORDERED_QTAG:
7900 control |= MPI2_SCSIIO_CONTROL_ORDEREDQ;
7901 break;
7902 default:
7903 mptsas_log(mpt, CE_WARN, "mpt: Invalid tag type\n");
7904 break;
7905 }
7906 } else {
7907 if (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE) {
7908 ptgt->m_t_throttle = 1;
7909 }
7910 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
7911 }
7912
7913 if (cmd->cmd_pkt_flags & FLAG_TLR) {
7914 control |= MPI2_SCSIIO_CONTROL_TLR_ON;
7915 }
7916
7917 mem = mpt->m_req_frame + (mpt->m_req_frame_size * SMID);
7918 io_request = (pMpi2SCSIIORequest_t)mem;
7919
7920 bzero(io_request, sizeof (Mpi2SCSIIORequest_t));
7921 ddi_put8(acc_hdl, &io_request->SGLOffset0, offsetof
7922 (MPI2_SCSI_IO_REQUEST, SGL) / 4);
7923 mptsas_init_std_hdr(acc_hdl, io_request, ptgt->m_devhdl, Lun(cmd), 0,
7924 MPI2_FUNCTION_SCSI_IO_REQUEST);
7925
7926 (void) ddi_rep_put8(acc_hdl, (uint8_t *)pkt->pkt_cdbp,
7927 io_request->CDB.CDB32, cmd->cmd_cdblen, DDI_DEV_AUTOINCR);
7928
7929 io_flags = cmd->cmd_cdblen;
7930 ddi_put16(acc_hdl, &io_request->IoFlags, io_flags);
7931 /*
7932 * setup the Scatter/Gather DMA list for this request
7933 */
7934 if (cmd->cmd_cookiec > 0) {
7935 mptsas_sge_setup(mpt, cmd, &control, io_request, acc_hdl);
7936 } else {
7937 ddi_put32(acc_hdl, &io_request->SGL.MpiSimple.FlagsLength,
7938 ((uint32_t)MPI2_SGE_FLAGS_LAST_ELEMENT |
7939 MPI2_SGE_FLAGS_END_OF_BUFFER |
7940 MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
7941 MPI2_SGE_FLAGS_END_OF_LIST) << MPI2_SGE_FLAGS_SHIFT);
7942 }
7943
7944 /*
7945 * save ARQ information
7946 */
7947 ddi_put8(acc_hdl, &io_request->SenseBufferLength, cmd->cmd_rqslen);
7948 if ((cmd->cmd_flags & (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) ==
7949 (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) {
7950 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress,
7951 cmd->cmd_ext_arqcookie.dmac_address);
7952 } else {
7953 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress,
7954 cmd->cmd_arqcookie.dmac_address);
7955 }
7956
7957 ddi_put32(acc_hdl, &io_request->Control, control);
7958
7959 NDBG31(("starting message=0x%p, with cmd=0x%p",
7960 (void *)(uintptr_t)mpt->m_req_frame_dma_addr, (void *)cmd));
7961
7962 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
7963
7964 /*
7965 * Build request descriptor and write it to the request desc post reg.
7966 */
7967 request_desc_low = (SMID << 16) + MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
7968 request_desc_high = ptgt->m_devhdl << 16;
7969 MPTSAS_START_CMD(mpt, request_desc_low, request_desc_high);
7970
7971 /*
7972 * Start timeout.
7973 */
7974 #ifdef MPTSAS_TEST
7975 /*
7976 * Temporarily set timebase = 0; needed for
7977 * timeout torture test.
7978 */
7979 if (mptsas_test_timeouts) {
7980 ptgt->m_timebase = 0;
7981 }
7982 #endif
7983 n = pkt->pkt_time - ptgt->m_timebase;
7984
7985 if (n == 0) {
7986 (ptgt->m_dups)++;
7987 ptgt->m_timeout = ptgt->m_timebase;
7988 } else if (n > 0) {
7989 ptgt->m_timeout =
7990 ptgt->m_timebase = pkt->pkt_time;
7991 ptgt->m_dups = 1;
7992 } else if (n < 0) {
7993 ptgt->m_timeout = ptgt->m_timebase;
7994 }
7995 #ifdef MPTSAS_TEST
7996 /*
7997 * Set back to a number higher than
7998 * mptsas_scsi_watchdog_tick
7999 * so timeouts will happen in mptsas_watchsubr
8000 */
8001 if (mptsas_test_timeouts) {
8002 ptgt->m_timebase = 60;
8003 }
8004 #endif
8005
8006 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) ||
8007 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) {
8008 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8009 return (DDI_FAILURE);
8010 }
8011 return (DDI_SUCCESS);
8012 }
8013
8014 /*
8015 * Select a helper thread to handle current doneq
8016 */
8017 static void
8018 mptsas_deliver_doneq_thread(mptsas_t *mpt)
8019 {
8020 uint64_t t, i;
8021 uint32_t min = 0xffffffff;
8022 mptsas_doneq_thread_list_t *item;
8023
8024 for (i = 0; i < mpt->m_doneq_thread_n; i++) {
8025 item = &mpt->m_doneq_thread_id[i];
8026 /*
8027 * If the completed command on help thread[i] less than
8028 * doneq_thread_threshold, then pick the thread[i]. Otherwise
8029 * pick a thread which has least completed command.
8030 */
8031
8032 mutex_enter(&item->mutex);
8033 if (item->len < mpt->m_doneq_thread_threshold) {
8034 t = i;
8035 mutex_exit(&item->mutex);
8036 break;
8037 }
8038 if (item->len < min) {
8039 min = item->len;
8040 t = i;
8041 }
8042 mutex_exit(&item->mutex);
8043 }
8044 mutex_enter(&mpt->m_doneq_thread_id[t].mutex);
8045 mptsas_doneq_mv(mpt, t);
8046 cv_signal(&mpt->m_doneq_thread_id[t].cv);
8047 mutex_exit(&mpt->m_doneq_thread_id[t].mutex);
8048 }
8049
8050 /*
8051 * move the current global doneq to the doneq of thead[t]
8052 */
8053 static void
8054 mptsas_doneq_mv(mptsas_t *mpt, uint64_t t)
8055 {
8056 mptsas_cmd_t *cmd;
8057 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
8058
8059 ASSERT(mutex_owned(&item->mutex));
8060 while ((cmd = mpt->m_doneq) != NULL) {
8061 if ((mpt->m_doneq = cmd->cmd_linkp) == NULL) {
8062 mpt->m_donetail = &mpt->m_doneq;
8063 }
8064 cmd->cmd_linkp = NULL;
8065 *item->donetail = cmd;
8066 item->donetail = &cmd->cmd_linkp;
8067 mpt->m_doneq_len--;
8068 item->len++;
8069 }
8070 }
8071
8072 void
8073 mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd)
8074 {
8075 struct scsi_pkt *pkt = CMD2PKT(cmd);
8076
8077 /* Check all acc and dma handles */
8078 if ((mptsas_check_acc_handle(mpt->m_datap) !=
8079 DDI_SUCCESS) ||
8080 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
8081 DDI_SUCCESS) ||
8082 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) !=
8083 DDI_SUCCESS) ||
8084 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) !=
8085 DDI_SUCCESS) ||
8086 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) !=
8087 DDI_SUCCESS) ||
8088 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) !=
8089 DDI_SUCCESS) ||
8090 (mptsas_check_acc_handle(mpt->m_config_handle) !=
8091 DDI_SUCCESS)) {
8092 ddi_fm_service_impact(mpt->m_dip,
8093 DDI_SERVICE_UNAFFECTED);
8094 ddi_fm_acc_err_clear(mpt->m_config_handle,
8095 DDI_FME_VER0);
8096 pkt->pkt_reason = CMD_TRAN_ERR;
8097 pkt->pkt_statistics = 0;
8098 }
8099 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
8100 DDI_SUCCESS) ||
8101 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) !=
8102 DDI_SUCCESS) ||
8103 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) !=
8104 DDI_SUCCESS) ||
8105 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) !=
8106 DDI_SUCCESS) ||
8107 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) !=
8108 DDI_SUCCESS)) {
8109 ddi_fm_service_impact(mpt->m_dip,
8110 DDI_SERVICE_UNAFFECTED);
8111 pkt->pkt_reason = CMD_TRAN_ERR;
8112 pkt->pkt_statistics = 0;
8113 }
8114 if (cmd->cmd_dmahandle &&
8115 (mptsas_check_dma_handle(cmd->cmd_dmahandle) != DDI_SUCCESS)) {
8116 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8117 pkt->pkt_reason = CMD_TRAN_ERR;
8118 pkt->pkt_statistics = 0;
8119 }
8120 if ((cmd->cmd_extra_frames &&
8121 ((mptsas_check_dma_handle(cmd->cmd_extra_frames->m_dma_hdl) !=
8122 DDI_SUCCESS) ||
8123 (mptsas_check_acc_handle(cmd->cmd_extra_frames->m_acc_hdl) !=
8124 DDI_SUCCESS)))) {
8125 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8126 pkt->pkt_reason = CMD_TRAN_ERR;
8127 pkt->pkt_statistics = 0;
8128 }
8129 if (cmd->cmd_arqhandle &&
8130 (mptsas_check_dma_handle(cmd->cmd_arqhandle) != DDI_SUCCESS)) {
8131 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8132 pkt->pkt_reason = CMD_TRAN_ERR;
8133 pkt->pkt_statistics = 0;
8134 }
8135 if (cmd->cmd_ext_arqhandle &&
8136 (mptsas_check_dma_handle(cmd->cmd_ext_arqhandle) != DDI_SUCCESS)) {
8137 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8138 pkt->pkt_reason = CMD_TRAN_ERR;
8139 pkt->pkt_statistics = 0;
8140 }
8141 }
8142
8143 /*
8144 * These routines manipulate the queue of commands that
8145 * are waiting for their completion routines to be called.
8146 * The queue is usually in FIFO order but on an MP system
8147 * it's possible for the completion routines to get out
8148 * of order. If that's a problem you need to add a global
8149 * mutex around the code that calls the completion routine
8150 * in the interrupt handler.
8151 */
8152 static void
8153 mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd)
8154 {
8155 struct scsi_pkt *pkt = CMD2PKT(cmd);
8156
8157 NDBG31(("mptsas_doneq_add: cmd=0x%p", (void *)cmd));
8158
8159 ASSERT((cmd->cmd_flags & CFLAG_COMPLETED) == 0);
8160 cmd->cmd_linkp = NULL;
8161 cmd->cmd_flags |= CFLAG_FINISHED;
8162 cmd->cmd_flags &= ~CFLAG_IN_TRANSPORT;
8163
8164 mptsas_fma_check(mpt, cmd);
8165
8166 /*
8167 * only add scsi pkts that have completion routines to
8168 * the doneq. no intr cmds do not have callbacks.
8169 */
8170 if (pkt && (pkt->pkt_comp)) {
8171 *mpt->m_donetail = cmd;
8172 mpt->m_donetail = &cmd->cmd_linkp;
8173 mpt->m_doneq_len++;
8174 }
8175 }
8176
8177 static mptsas_cmd_t *
8178 mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t)
8179 {
8180 mptsas_cmd_t *cmd;
8181 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
8182
8183 /* pop one off the done queue */
8184 if ((cmd = item->doneq) != NULL) {
8185 /* if the queue is now empty fix the tail pointer */
8186 NDBG31(("mptsas_doneq_thread_rm: cmd=0x%p", (void *)cmd));
8187 if ((item->doneq = cmd->cmd_linkp) == NULL) {
8188 item->donetail = &item->doneq;
8189 }
8190 cmd->cmd_linkp = NULL;
8191 item->len--;
8192 }
8193 return (cmd);
8194 }
8195
8196 static void
8197 mptsas_doneq_empty(mptsas_t *mpt)
8198 {
8199 if (mpt->m_doneq && !mpt->m_in_callback) {
8200 mptsas_cmd_t *cmd, *next;
8201 struct scsi_pkt *pkt;
8202
8203 mpt->m_in_callback = 1;
8204 cmd = mpt->m_doneq;
8205 mpt->m_doneq = NULL;
8206 mpt->m_donetail = &mpt->m_doneq;
8207 mpt->m_doneq_len = 0;
8208
8209 mutex_exit(&mpt->m_mutex);
8210 /*
8211 * run the completion routines of all the
8212 * completed commands
8213 */
8214 while (cmd != NULL) {
8215 next = cmd->cmd_linkp;
8216 cmd->cmd_linkp = NULL;
8217 /* run this command's completion routine */
8218 cmd->cmd_flags |= CFLAG_COMPLETED;
8219 pkt = CMD2PKT(cmd);
8220 mptsas_pkt_comp(pkt, cmd);
8221 cmd = next;
8222 }
8223 mutex_enter(&mpt->m_mutex);
8224 mpt->m_in_callback = 0;
8225 }
8226 }
8227
8228 /*
8229 * These routines manipulate the target's queue of pending requests
8230 */
8231 void
8232 mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd)
8233 {
8234 NDBG7(("mptsas_waitq_add: cmd=0x%p", (void *)cmd));
8235 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8236 cmd->cmd_queued = TRUE;
8237 if (ptgt)
8238 ptgt->m_t_nwait++;
8239 if (cmd->cmd_pkt_flags & FLAG_HEAD) {
8240 if ((cmd->cmd_linkp = mpt->m_waitq) == NULL) {
8241 mpt->m_waitqtail = &cmd->cmd_linkp;
8242 }
8243 mpt->m_waitq = cmd;
8244 } else {
8245 cmd->cmd_linkp = NULL;
8246 *(mpt->m_waitqtail) = cmd;
8247 mpt->m_waitqtail = &cmd->cmd_linkp;
8248 }
8249 }
8250
8251 static mptsas_cmd_t *
8252 mptsas_waitq_rm(mptsas_t *mpt)
8253 {
8254 mptsas_cmd_t *cmd;
8255 mptsas_target_t *ptgt;
8256 NDBG7(("mptsas_waitq_rm"));
8257
8258 MPTSAS_WAITQ_RM(mpt, cmd);
8259
8260 NDBG7(("mptsas_waitq_rm: cmd=0x%p", (void *)cmd));
8261 if (cmd) {
8262 ptgt = cmd->cmd_tgt_addr;
8263 if (ptgt) {
8264 ptgt->m_t_nwait--;
8265 ASSERT(ptgt->m_t_nwait >= 0);
8266 }
8267 }
8268 return (cmd);
8269 }
8270
8271 /*
8272 * remove specified cmd from the middle of the wait queue.
8273 */
8274 static void
8275 mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd)
8276 {
8277 mptsas_cmd_t *prevp = mpt->m_waitq;
8278 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8279
8280 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
8281 (void *)mpt, (void *)cmd));
8282 if (ptgt) {
8283 ptgt->m_t_nwait--;
8284 ASSERT(ptgt->m_t_nwait >= 0);
8285 }
8286
8287 if (prevp == cmd) {
8288 if ((mpt->m_waitq = cmd->cmd_linkp) == NULL)
8289 mpt->m_waitqtail = &mpt->m_waitq;
8290
8291 cmd->cmd_linkp = NULL;
8292 cmd->cmd_queued = FALSE;
8293 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
8294 (void *)mpt, (void *)cmd));
8295 return;
8296 }
8297
8298 while (prevp != NULL) {
8299 if (prevp->cmd_linkp == cmd) {
8300 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL)
8301 mpt->m_waitqtail = &prevp->cmd_linkp;
8302
8303 cmd->cmd_linkp = NULL;
8304 cmd->cmd_queued = FALSE;
8305 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
8306 (void *)mpt, (void *)cmd));
8307 return;
8308 }
8309 prevp = prevp->cmd_linkp;
8310 }
8311 cmn_err(CE_PANIC, "mpt: mptsas_waitq_delete: queue botch");
8312 }
8313
8314 static mptsas_cmd_t *
8315 mptsas_tx_waitq_rm(mptsas_t *mpt)
8316 {
8317 mptsas_cmd_t *cmd;
8318 NDBG7(("mptsas_tx_waitq_rm"));
8319
8320 MPTSAS_TX_WAITQ_RM(mpt, cmd);
8321
8322 NDBG7(("mptsas_tx_waitq_rm: cmd=0x%p", (void *)cmd));
8323
8324 return (cmd);
8325 }
8326
8327 /*
8328 * remove specified cmd from the middle of the tx_waitq.
8329 */
8330 static void
8331 mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd)
8332 {
8333 mptsas_cmd_t *prevp = mpt->m_tx_waitq;
8334
8335 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p",
8336 (void *)mpt, (void *)cmd));
8337
8338 if (prevp == cmd) {
8339 if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL)
8340 mpt->m_tx_waitqtail = &mpt->m_tx_waitq;
8341
8342 cmd->cmd_linkp = NULL;
8343 cmd->cmd_queued = FALSE;
8344 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p",
8345 (void *)mpt, (void *)cmd));
8346 return;
8347 }
8348
8349 while (prevp != NULL) {
8350 if (prevp->cmd_linkp == cmd) {
8351 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL)
8352 mpt->m_tx_waitqtail = &prevp->cmd_linkp;
8353
8354 cmd->cmd_linkp = NULL;
8355 cmd->cmd_queued = FALSE;
8356 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p",
8357 (void *)mpt, (void *)cmd));
8358 return;
8359 }
8360 prevp = prevp->cmd_linkp;
8361 }
8362 cmn_err(CE_PANIC, "mpt: mptsas_tx_waitq_delete: queue botch");
8363 }
8364
8365 /*
8366 * device and bus reset handling
8367 *
8368 * Notes:
8369 * - RESET_ALL: reset the controller
8370 * - RESET_TARGET: reset the target specified in scsi_address
8371 */
8372 static int
8373 mptsas_scsi_reset(struct scsi_address *ap, int level)
8374 {
8375 mptsas_t *mpt = ADDR2MPT(ap);
8376 int rval;
8377 mptsas_tgt_private_t *tgt_private;
8378 mptsas_target_t *ptgt = NULL;
8379
8380 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->tran_tgt_private;
8381 ptgt = tgt_private->t_private;
8382 if (ptgt == NULL) {
8383 return (FALSE);
8384 }
8385 NDBG22(("mptsas_scsi_reset: target=%d level=%d", ptgt->m_devhdl,
8386 level));
8387
8388 mutex_enter(&mpt->m_mutex);
8389 /*
8390 * if we are not in panic set up a reset delay for this target
8391 */
8392 if (!ddi_in_panic()) {
8393 mptsas_setup_bus_reset_delay(mpt);
8394 } else {
8395 drv_usecwait(mpt->m_scsi_reset_delay * 1000);
8396 }
8397 rval = mptsas_do_scsi_reset(mpt, ptgt->m_devhdl);
8398 mutex_exit(&mpt->m_mutex);
8399
8400 /*
8401 * The transport layer expect to only see TRUE and
8402 * FALSE. Therefore, we will adjust the return value
8403 * if mptsas_do_scsi_reset returns FAILED.
8404 */
8405 if (rval == FAILED)
8406 rval = FALSE;
8407 return (rval);
8408 }
8409
8410 static int
8411 mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl)
8412 {
8413 int rval = FALSE;
8414 uint8_t config, disk;
8415 mptsas_slots_t *slots = mpt->m_active;
8416
8417 ASSERT(mutex_owned(&mpt->m_mutex));
8418
8419 if (mptsas_debug_resets) {
8420 mptsas_log(mpt, CE_WARN, "mptsas_do_scsi_reset: target=%d",
8421 devhdl);
8422 }
8423
8424 /*
8425 * Issue a Target Reset message to the target specified but not to a
8426 * disk making up a raid volume. Just look through the RAID config
8427 * Phys Disk list of DevHandles. If the target's DevHandle is in this
8428 * list, then don't reset this target.
8429 */
8430 for (config = 0; config < slots->m_num_raid_configs; config++) {
8431 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) {
8432 if (devhdl == slots->m_raidconfig[config].
8433 m_physdisk_devhdl[disk]) {
8434 return (TRUE);
8435 }
8436 }
8437 }
8438
8439 rval = mptsas_ioc_task_management(mpt,
8440 MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, devhdl, 0, NULL, 0, 0);
8441
8442 mptsas_doneq_empty(mpt);
8443 return (rval);
8444 }
8445
8446 static int
8447 mptsas_scsi_reset_notify(struct scsi_address *ap, int flag,
8448 void (*callback)(caddr_t), caddr_t arg)
8449 {
8450 mptsas_t *mpt = ADDR2MPT(ap);
8451
8452 NDBG22(("mptsas_scsi_reset_notify: tgt=%d", ap->a_target));
8453
8454 return (scsi_hba_reset_notify_setup(ap, flag, callback, arg,
8455 &mpt->m_mutex, &mpt->m_reset_notify_listf));
8456 }
8457
8458 static int
8459 mptsas_get_name(struct scsi_device *sd, char *name, int len)
8460 {
8461 dev_info_t *lun_dip = NULL;
8462
8463 ASSERT(sd != NULL);
8464 ASSERT(name != NULL);
8465 lun_dip = sd->sd_dev;
8466 ASSERT(lun_dip != NULL);
8467
8468 if (mptsas_name_child(lun_dip, name, len) == DDI_SUCCESS) {
8469 return (1);
8470 } else {
8471 return (0);
8472 }
8473 }
8474
8475 static int
8476 mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len)
8477 {
8478 return (mptsas_get_name(sd, name, len));
8479 }
8480
8481 void
8482 mptsas_set_throttle(mptsas_t *mpt, mptsas_target_t *ptgt, int what)
8483 {
8484
8485 NDBG25(("mptsas_set_throttle: throttle=%x", what));
8486
8487 /*
8488 * if the bus is draining/quiesced, no changes to the throttles
8489 * are allowed. Not allowing change of throttles during draining
8490 * limits error recovery but will reduce draining time
8491 *
8492 * all throttles should have been set to HOLD_THROTTLE
8493 */
8494 if (mpt->m_softstate & (MPTSAS_SS_QUIESCED | MPTSAS_SS_DRAINING)) {
8495 return;
8496 }
8497
8498 if (what == HOLD_THROTTLE) {
8499 ptgt->m_t_throttle = HOLD_THROTTLE;
8500 } else if (ptgt->m_reset_delay == 0) {
8501 ptgt->m_t_throttle = what;
8502 }
8503 }
8504
8505 /*
8506 * Clean up from a device reset.
8507 * For the case of target reset, this function clears the waitq of all
8508 * commands for a particular target. For the case of abort task set, this
8509 * function clears the waitq of all commonds for a particular target/lun.
8510 */
8511 static void
8512 mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, uint8_t tasktype)
8513 {
8514 mptsas_slots_t *slots = mpt->m_active;
8515 mptsas_cmd_t *cmd, *next_cmd;
8516 int slot;
8517 uchar_t reason;
8518 uint_t stat;
8519
8520 NDBG25(("mptsas_flush_target: target=%d lun=%d", target, lun));
8521
8522 /*
8523 * Make sure the I/O Controller has flushed all cmds
8524 * that are associated with this target for a target reset
8525 * and target/lun for abort task set.
8526 * Account for TM requests, which use the last SMID.
8527 */
8528 for (slot = 0; slot <= mpt->m_active->m_n_slots; slot++) {
8529 if ((cmd = slots->m_slot[slot]) == NULL)
8530 continue;
8531 reason = CMD_RESET;
8532 stat = STAT_DEV_RESET;
8533 switch (tasktype) {
8534 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
8535 if (Tgt(cmd) == target) {
8536 NDBG25(("mptsas_flush_target discovered non-"
8537 "NULL cmd in slot %d, tasktype 0x%x", slot,
8538 tasktype));
8539 mptsas_dump_cmd(mpt, cmd);
8540 mptsas_remove_cmd(mpt, cmd);
8541 mptsas_set_pkt_reason(mpt, cmd, reason, stat);
8542 mptsas_doneq_add(mpt, cmd);
8543 }
8544 break;
8545 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
8546 reason = CMD_ABORTED;
8547 stat = STAT_ABORTED;
8548 /*FALLTHROUGH*/
8549 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
8550 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
8551
8552 NDBG25(("mptsas_flush_target discovered non-"
8553 "NULL cmd in slot %d, tasktype 0x%x", slot,
8554 tasktype));
8555 mptsas_dump_cmd(mpt, cmd);
8556 mptsas_remove_cmd(mpt, cmd);
8557 mptsas_set_pkt_reason(mpt, cmd, reason,
8558 stat);
8559 mptsas_doneq_add(mpt, cmd);
8560 }
8561 break;
8562 default:
8563 break;
8564 }
8565 }
8566
8567 /*
8568 * Flush the waitq and tx_waitq of this target's cmds
8569 */
8570 cmd = mpt->m_waitq;
8571
8572 reason = CMD_RESET;
8573 stat = STAT_DEV_RESET;
8574
8575 switch (tasktype) {
8576 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
8577 while (cmd != NULL) {
8578 next_cmd = cmd->cmd_linkp;
8579 if (Tgt(cmd) == target) {
8580 mptsas_waitq_delete(mpt, cmd);
8581 mptsas_set_pkt_reason(mpt, cmd,
8582 reason, stat);
8583 mptsas_doneq_add(mpt, cmd);
8584 }
8585 cmd = next_cmd;
8586 }
8587 mutex_enter(&mpt->m_tx_waitq_mutex);
8588 cmd = mpt->m_tx_waitq;
8589 while (cmd != NULL) {
8590 next_cmd = cmd->cmd_linkp;
8591 if (Tgt(cmd) == target) {
8592 mptsas_tx_waitq_delete(mpt, cmd);
8593 mutex_exit(&mpt->m_tx_waitq_mutex);
8594 mptsas_set_pkt_reason(mpt, cmd,
8595 reason, stat);
8596 mptsas_doneq_add(mpt, cmd);
8597 mutex_enter(&mpt->m_tx_waitq_mutex);
8598 }
8599 cmd = next_cmd;
8600 }
8601 mutex_exit(&mpt->m_tx_waitq_mutex);
8602 break;
8603 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
8604 reason = CMD_ABORTED;
8605 stat = STAT_ABORTED;
8606 /*FALLTHROUGH*/
8607 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
8608 while (cmd != NULL) {
8609 next_cmd = cmd->cmd_linkp;
8610 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
8611 mptsas_waitq_delete(mpt, cmd);
8612 mptsas_set_pkt_reason(mpt, cmd,
8613 reason, stat);
8614 mptsas_doneq_add(mpt, cmd);
8615 }
8616 cmd = next_cmd;
8617 }
8618 mutex_enter(&mpt->m_tx_waitq_mutex);
8619 cmd = mpt->m_tx_waitq;
8620 while (cmd != NULL) {
8621 next_cmd = cmd->cmd_linkp;
8622 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
8623 mptsas_tx_waitq_delete(mpt, cmd);
8624 mutex_exit(&mpt->m_tx_waitq_mutex);
8625 mptsas_set_pkt_reason(mpt, cmd,
8626 reason, stat);
8627 mptsas_doneq_add(mpt, cmd);
8628 mutex_enter(&mpt->m_tx_waitq_mutex);
8629 }
8630 cmd = next_cmd;
8631 }
8632 mutex_exit(&mpt->m_tx_waitq_mutex);
8633 break;
8634 default:
8635 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.",
8636 tasktype);
8637 break;
8638 }
8639 }
8640
8641 /*
8642 * Clean up hba state, abort all outstanding command and commands in waitq
8643 * reset timeout of all targets.
8644 */
8645 static void
8646 mptsas_flush_hba(mptsas_t *mpt)
8647 {
8648 mptsas_slots_t *slots = mpt->m_active;
8649 mptsas_cmd_t *cmd;
8650 int slot;
8651
8652 NDBG25(("mptsas_flush_hba"));
8653
8654 /*
8655 * The I/O Controller should have already sent back
8656 * all commands via the scsi I/O reply frame. Make
8657 * sure all commands have been flushed.
8658 * Account for TM request, which use the last SMID.
8659 */
8660 for (slot = 0; slot <= mpt->m_active->m_n_slots; slot++) {
8661 if ((cmd = slots->m_slot[slot]) == NULL)
8662 continue;
8663
8664 if (cmd->cmd_flags & CFLAG_CMDIOC) {
8665 /*
8666 * Need to make sure to tell everyone that might be
8667 * waiting on this command that it's going to fail. If
8668 * we get here, this command will never timeout because
8669 * the active command table is going to be re-allocated,
8670 * so there will be nothing to check against a time out.
8671 * Instead, mark the command as failed due to reset.
8672 */
8673 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET,
8674 STAT_BUS_RESET);
8675 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
8676 (cmd->cmd_flags & CFLAG_CONFIG) ||
8677 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
8678 cmd->cmd_flags |= CFLAG_FINISHED;
8679 cv_broadcast(&mpt->m_passthru_cv);
8680 cv_broadcast(&mpt->m_config_cv);
8681 cv_broadcast(&mpt->m_fw_diag_cv);
8682 }
8683 continue;
8684 }
8685
8686 NDBG25(("mptsas_flush_hba discovered non-NULL cmd in slot %d",
8687 slot));
8688 mptsas_dump_cmd(mpt, cmd);
8689
8690 mptsas_remove_cmd(mpt, cmd);
8691 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
8692 mptsas_doneq_add(mpt, cmd);
8693 }
8694
8695 /*
8696 * Flush the waitq.
8697 */
8698 while ((cmd = mptsas_waitq_rm(mpt)) != NULL) {
8699 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
8700 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
8701 (cmd->cmd_flags & CFLAG_CONFIG) ||
8702 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
8703 cmd->cmd_flags |= CFLAG_FINISHED;
8704 cv_broadcast(&mpt->m_passthru_cv);
8705 cv_broadcast(&mpt->m_config_cv);
8706 cv_broadcast(&mpt->m_fw_diag_cv);
8707 } else {
8708 mptsas_doneq_add(mpt, cmd);
8709 }
8710 }
8711
8712 /*
8713 * Flush the tx_waitq
8714 */
8715 mutex_enter(&mpt->m_tx_waitq_mutex);
8716 while ((cmd = mptsas_tx_waitq_rm(mpt)) != NULL) {
8717 mutex_exit(&mpt->m_tx_waitq_mutex);
8718 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
8719 mptsas_doneq_add(mpt, cmd);
8720 mutex_enter(&mpt->m_tx_waitq_mutex);
8721 }
8722 mutex_exit(&mpt->m_tx_waitq_mutex);
8723
8724 /*
8725 * Drain the taskqs prior to reallocating resources.
8726 */
8727 mutex_exit(&mpt->m_mutex);
8728 ddi_taskq_wait(mpt->m_event_taskq);
8729 ddi_taskq_wait(mpt->m_dr_taskq);
8730 mutex_enter(&mpt->m_mutex);
8731 }
8732
8733 /*
8734 * set pkt_reason and OR in pkt_statistics flag
8735 */
8736 static void
8737 mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, uchar_t reason,
8738 uint_t stat)
8739 {
8740 #ifndef __lock_lint
8741 _NOTE(ARGUNUSED(mpt))
8742 #endif
8743
8744 NDBG25(("mptsas_set_pkt_reason: cmd=0x%p reason=%x stat=%x",
8745 (void *)cmd, reason, stat));
8746
8747 if (cmd) {
8748 if (cmd->cmd_pkt->pkt_reason == CMD_CMPLT) {
8749 cmd->cmd_pkt->pkt_reason = reason;
8750 }
8751 cmd->cmd_pkt->pkt_statistics |= stat;
8752 }
8753 }
8754
8755 static void
8756 mptsas_start_watch_reset_delay()
8757 {
8758 NDBG22(("mptsas_start_watch_reset_delay"));
8759
8760 mutex_enter(&mptsas_global_mutex);
8761 if (mptsas_reset_watch == NULL && mptsas_timeouts_enabled) {
8762 mptsas_reset_watch = timeout(mptsas_watch_reset_delay, NULL,
8763 drv_usectohz((clock_t)
8764 MPTSAS_WATCH_RESET_DELAY_TICK * 1000));
8765 ASSERT(mptsas_reset_watch != NULL);
8766 }
8767 mutex_exit(&mptsas_global_mutex);
8768 }
8769
8770 static void
8771 mptsas_setup_bus_reset_delay(mptsas_t *mpt)
8772 {
8773 mptsas_target_t *ptgt = NULL;
8774
8775 NDBG22(("mptsas_setup_bus_reset_delay"));
8776 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
8777 MPTSAS_HASH_FIRST);
8778 while (ptgt != NULL) {
8779 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
8780 ptgt->m_reset_delay = mpt->m_scsi_reset_delay;
8781
8782 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
8783 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
8784 }
8785
8786 mptsas_start_watch_reset_delay();
8787 }
8788
8789 /*
8790 * mptsas_watch_reset_delay(_subr) is invoked by timeout() and checks every
8791 * mpt instance for active reset delays
8792 */
8793 static void
8794 mptsas_watch_reset_delay(void *arg)
8795 {
8796 #ifndef __lock_lint
8797 _NOTE(ARGUNUSED(arg))
8798 #endif
8799
8800 mptsas_t *mpt;
8801 int not_done = 0;
8802
8803 NDBG22(("mptsas_watch_reset_delay"));
8804
8805 mutex_enter(&mptsas_global_mutex);
8806 mptsas_reset_watch = 0;
8807 mutex_exit(&mptsas_global_mutex);
8808 rw_enter(&mptsas_global_rwlock, RW_READER);
8809 for (mpt = mptsas_head; mpt != NULL; mpt = mpt->m_next) {
8810 if (mpt->m_tran == 0) {
8811 continue;
8812 }
8813 mutex_enter(&mpt->m_mutex);
8814 not_done += mptsas_watch_reset_delay_subr(mpt);
8815 mutex_exit(&mpt->m_mutex);
8816 }
8817 rw_exit(&mptsas_global_rwlock);
8818
8819 if (not_done) {
8820 mptsas_start_watch_reset_delay();
8821 }
8822 }
8823
8824 static int
8825 mptsas_watch_reset_delay_subr(mptsas_t *mpt)
8826 {
8827 int done = 0;
8828 int restart = 0;
8829 mptsas_target_t *ptgt = NULL;
8830
8831 NDBG22(("mptsas_watch_reset_delay_subr: mpt=0x%p", (void *)mpt));
8832
8833 ASSERT(mutex_owned(&mpt->m_mutex));
8834
8835 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
8836 MPTSAS_HASH_FIRST);
8837 while (ptgt != NULL) {
8838 if (ptgt->m_reset_delay != 0) {
8839 ptgt->m_reset_delay -=
8840 MPTSAS_WATCH_RESET_DELAY_TICK;
8841 if (ptgt->m_reset_delay <= 0) {
8842 ptgt->m_reset_delay = 0;
8843 mptsas_set_throttle(mpt, ptgt,
8844 MAX_THROTTLE);
8845 restart++;
8846 } else {
8847 done = -1;
8848 }
8849 }
8850
8851 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
8852 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
8853 }
8854
8855 if (restart > 0) {
8856 mptsas_restart_hba(mpt);
8857 }
8858 return (done);
8859 }
8860
8861 #ifdef MPTSAS_TEST
8862 static void
8863 mptsas_test_reset(mptsas_t *mpt, int target)
8864 {
8865 mptsas_target_t *ptgt = NULL;
8866
8867 if (mptsas_rtest == target) {
8868 if (mptsas_do_scsi_reset(mpt, target) == TRUE) {
8869 mptsas_rtest = -1;
8870 }
8871 if (mptsas_rtest == -1) {
8872 NDBG22(("mptsas_test_reset success"));
8873 }
8874 }
8875 }
8876 #endif
8877
8878 /*
8879 * abort handling:
8880 *
8881 * Notes:
8882 * - if pkt is not NULL, abort just that command
8883 * - if pkt is NULL, abort all outstanding commands for target
8884 */
8885 static int
8886 mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt)
8887 {
8888 mptsas_t *mpt = ADDR2MPT(ap);
8889 int rval;
8890 mptsas_tgt_private_t *tgt_private;
8891 int target, lun;
8892
8893 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->
8894 tran_tgt_private;
8895 ASSERT(tgt_private != NULL);
8896 target = tgt_private->t_private->m_devhdl;
8897 lun = tgt_private->t_lun;
8898
8899 NDBG23(("mptsas_scsi_abort: target=%d.%d", target, lun));
8900
8901 mutex_enter(&mpt->m_mutex);
8902 rval = mptsas_do_scsi_abort(mpt, target, lun, pkt);
8903 mutex_exit(&mpt->m_mutex);
8904 return (rval);
8905 }
8906
8907 static int
8908 mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, struct scsi_pkt *pkt)
8909 {
8910 mptsas_cmd_t *sp = NULL;
8911 mptsas_slots_t *slots = mpt->m_active;
8912 int rval = FALSE;
8913
8914 ASSERT(mutex_owned(&mpt->m_mutex));
8915
8916 /*
8917 * Abort the command pkt on the target/lun in ap. If pkt is
8918 * NULL, abort all outstanding commands on that target/lun.
8919 * If you can abort them, return 1, else return 0.
8920 * Each packet that's aborted should be sent back to the target
8921 * driver through the callback routine, with pkt_reason set to
8922 * CMD_ABORTED.
8923 *
8924 * abort cmd pkt on HBA hardware; clean out of outstanding
8925 * command lists, etc.
8926 */
8927 if (pkt != NULL) {
8928 /* abort the specified packet */
8929 sp = PKT2CMD(pkt);
8930
8931 if (sp->cmd_queued) {
8932 NDBG23(("mptsas_do_scsi_abort: queued sp=0x%p aborted",
8933 (void *)sp));
8934 mptsas_waitq_delete(mpt, sp);
8935 mptsas_set_pkt_reason(mpt, sp, CMD_ABORTED,
8936 STAT_ABORTED);
8937 mptsas_doneq_add(mpt, sp);
8938 rval = TRUE;
8939 goto done;
8940 }
8941
8942 /*
8943 * Have mpt firmware abort this command
8944 */
8945
8946 if (slots->m_slot[sp->cmd_slot] != NULL) {
8947 rval = mptsas_ioc_task_management(mpt,
8948 MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK, target,
8949 lun, NULL, 0, 0);
8950
8951 /*
8952 * The transport layer expects only TRUE and FALSE.
8953 * Therefore, if mptsas_ioc_task_management returns
8954 * FAILED we will return FALSE.
8955 */
8956 if (rval == FAILED)
8957 rval = FALSE;
8958 goto done;
8959 }
8960 }
8961
8962 /*
8963 * If pkt is NULL then abort task set
8964 */
8965 rval = mptsas_ioc_task_management(mpt,
8966 MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET, target, lun, NULL, 0, 0);
8967
8968 /*
8969 * The transport layer expects only TRUE and FALSE.
8970 * Therefore, if mptsas_ioc_task_management returns
8971 * FAILED we will return FALSE.
8972 */
8973 if (rval == FAILED)
8974 rval = FALSE;
8975
8976 #ifdef MPTSAS_TEST
8977 if (rval && mptsas_test_stop) {
8978 debug_enter("mptsas_do_scsi_abort");
8979 }
8980 #endif
8981
8982 done:
8983 mptsas_doneq_empty(mpt);
8984 return (rval);
8985 }
8986
8987 /*
8988 * capability handling:
8989 * (*tran_getcap). Get the capability named, and return its value.
8990 */
8991 static int
8992 mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly)
8993 {
8994 mptsas_t *mpt = ADDR2MPT(ap);
8995 int ckey;
8996 int rval = FALSE;
8997
8998 NDBG24(("mptsas_scsi_getcap: target=%d, cap=%s tgtonly=%x",
8999 ap->a_target, cap, tgtonly));
9000
9001 mutex_enter(&mpt->m_mutex);
9002
9003 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) {
9004 mutex_exit(&mpt->m_mutex);
9005 return (UNDEFINED);
9006 }
9007
9008 switch (ckey) {
9009 case SCSI_CAP_DMA_MAX:
9010 rval = (int)mpt->m_msg_dma_attr.dma_attr_maxxfer;
9011 break;
9012 case SCSI_CAP_ARQ:
9013 rval = TRUE;
9014 break;
9015 case SCSI_CAP_MSG_OUT:
9016 case SCSI_CAP_PARITY:
9017 case SCSI_CAP_UNTAGGED_QING:
9018 rval = TRUE;
9019 break;
9020 case SCSI_CAP_TAGGED_QING:
9021 rval = TRUE;
9022 break;
9023 case SCSI_CAP_RESET_NOTIFICATION:
9024 rval = TRUE;
9025 break;
9026 case SCSI_CAP_LINKED_CMDS:
9027 rval = FALSE;
9028 break;
9029 case SCSI_CAP_QFULL_RETRIES:
9030 rval = ((mptsas_tgt_private_t *)(ap->a_hba_tran->
9031 tran_tgt_private))->t_private->m_qfull_retries;
9032 break;
9033 case SCSI_CAP_QFULL_RETRY_INTERVAL:
9034 rval = drv_hztousec(((mptsas_tgt_private_t *)
9035 (ap->a_hba_tran->tran_tgt_private))->
9036 t_private->m_qfull_retry_interval) / 1000;
9037 break;
9038 case SCSI_CAP_CDB_LEN:
9039 rval = CDB_GROUP4;
9040 break;
9041 case SCSI_CAP_INTERCONNECT_TYPE:
9042 rval = INTERCONNECT_SAS;
9043 break;
9044 case SCSI_CAP_TRAN_LAYER_RETRIES:
9045 if (mpt->m_ioc_capabilities &
9046 MPI2_IOCFACTS_CAPABILITY_TLR)
9047 rval = TRUE;
9048 else
9049 rval = FALSE;
9050 break;
9051 default:
9052 rval = UNDEFINED;
9053 break;
9054 }
9055
9056 NDBG24(("mptsas_scsi_getcap: %s, rval=%x", cap, rval));
9057
9058 mutex_exit(&mpt->m_mutex);
9059 return (rval);
9060 }
9061
9062 /*
9063 * (*tran_setcap). Set the capability named to the value given.
9064 */
9065 static int
9066 mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, int tgtonly)
9067 {
9068 mptsas_t *mpt = ADDR2MPT(ap);
9069 int ckey;
9070 int rval = FALSE;
9071
9072 NDBG24(("mptsas_scsi_setcap: target=%d, cap=%s value=%x tgtonly=%x",
9073 ap->a_target, cap, value, tgtonly));
9074
9075 if (!tgtonly) {
9076 return (rval);
9077 }
9078
9079 mutex_enter(&mpt->m_mutex);
9080
9081 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) {
9082 mutex_exit(&mpt->m_mutex);
9083 return (UNDEFINED);
9084 }
9085
9086 switch (ckey) {
9087 case SCSI_CAP_DMA_MAX:
9088 case SCSI_CAP_MSG_OUT:
9089 case SCSI_CAP_PARITY:
9090 case SCSI_CAP_INITIATOR_ID:
9091 case SCSI_CAP_LINKED_CMDS:
9092 case SCSI_CAP_UNTAGGED_QING:
9093 case SCSI_CAP_RESET_NOTIFICATION:
9094 /*
9095 * None of these are settable via
9096 * the capability interface.
9097 */
9098 break;
9099 case SCSI_CAP_ARQ:
9100 /*
9101 * We cannot turn off arq so return false if asked to
9102 */
9103 if (value) {
9104 rval = TRUE;
9105 } else {
9106 rval = FALSE;
9107 }
9108 break;
9109 case SCSI_CAP_TAGGED_QING:
9110 mptsas_set_throttle(mpt, ((mptsas_tgt_private_t *)
9111 (ap->a_hba_tran->tran_tgt_private))->t_private,
9112 MAX_THROTTLE);
9113 rval = TRUE;
9114 break;
9115 case SCSI_CAP_QFULL_RETRIES:
9116 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))->
9117 t_private->m_qfull_retries = (uchar_t)value;
9118 rval = TRUE;
9119 break;
9120 case SCSI_CAP_QFULL_RETRY_INTERVAL:
9121 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))->
9122 t_private->m_qfull_retry_interval =
9123 drv_usectohz(value * 1000);
9124 rval = TRUE;
9125 break;
9126 default:
9127 rval = UNDEFINED;
9128 break;
9129 }
9130 mutex_exit(&mpt->m_mutex);
9131 return (rval);
9132 }
9133
9134 /*
9135 * Utility routine for mptsas_ifsetcap/ifgetcap
9136 */
9137 /*ARGSUSED*/
9138 static int
9139 mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp)
9140 {
9141 NDBG24(("mptsas_scsi_capchk: cap=%s", cap));
9142
9143 if (!cap)
9144 return (FALSE);
9145
9146 *cidxp = scsi_hba_lookup_capstr(cap);
9147 return (TRUE);
9148 }
9149
9150 static int
9151 mptsas_alloc_active_slots(mptsas_t *mpt, int flag)
9152 {
9153 mptsas_slots_t *old_active = mpt->m_active;
9154 mptsas_slots_t *new_active;
9155 size_t size;
9156 int rval = -1, i;
9157
9158 /*
9159 * if there are active commands, then we cannot
9160 * change size of active slots array.
9161 */
9162 ASSERT(mpt->m_ncmds == 0);
9163
9164 size = MPTSAS_SLOTS_SIZE(mpt);
9165 new_active = kmem_zalloc(size, flag);
9166 if (new_active == NULL) {
9167 NDBG1(("new active alloc failed"));
9168 return (rval);
9169 }
9170 /*
9171 * Since SMID 0 is reserved and the TM slot is reserved, the
9172 * number of slots that can be used at any one time is
9173 * m_max_requests - 2.
9174 */
9175 new_active->m_n_slots = (mpt->m_max_requests - 2);
9176 new_active->m_size = size;
9177 new_active->m_tags = 1;
9178 if (old_active) {
9179 new_active->m_tgttbl = old_active->m_tgttbl;
9180 new_active->m_smptbl = old_active->m_smptbl;
9181 new_active->m_num_raid_configs =
9182 old_active->m_num_raid_configs;
9183 for (i = 0; i < new_active->m_num_raid_configs; i++) {
9184 new_active->m_raidconfig[i] =
9185 old_active->m_raidconfig[i];
9186 }
9187 mptsas_free_active_slots(mpt);
9188 }
9189 mpt->m_active = new_active;
9190 rval = 0;
9191
9192 return (rval);
9193 }
9194
9195 static void
9196 mptsas_free_active_slots(mptsas_t *mpt)
9197 {
9198 mptsas_slots_t *active = mpt->m_active;
9199 size_t size;
9200
9201 if (active == NULL)
9202 return;
9203 size = active->m_size;
9204 kmem_free(active, size);
9205 mpt->m_active = NULL;
9206 }
9207
9208 /*
9209 * Error logging, printing, and debug print routines.
9210 */
9211 static char *mptsas_label = "mpt_sas";
9212
9213 /*PRINTFLIKE3*/
9214 void
9215 mptsas_log(mptsas_t *mpt, int level, char *fmt, ...)
9216 {
9217 dev_info_t *dev;
9218 va_list ap;
9219
9220 if (mpt) {
9221 dev = mpt->m_dip;
9222 } else {
9223 dev = 0;
9224 }
9225
9226 mutex_enter(&mptsas_log_mutex);
9227
9228 va_start(ap, fmt);
9229 (void) vsprintf(mptsas_log_buf, fmt, ap);
9230 va_end(ap);
9231
9232 if (level == CE_CONT) {
9233 scsi_log(dev, mptsas_label, level, "%s\n", mptsas_log_buf);
9234 } else {
9235 scsi_log(dev, mptsas_label, level, "%s", mptsas_log_buf);
9236 }
9237
9238 mutex_exit(&mptsas_log_mutex);
9239 }
9240
9241 #ifdef MPTSAS_DEBUG
9242 /*PRINTFLIKE1*/
9243 void
9244 mptsas_printf(char *fmt, ...)
9245 {
9246 dev_info_t *dev = 0;
9247 va_list ap;
9248
9249 mutex_enter(&mptsas_log_mutex);
9250
9251 va_start(ap, fmt);
9252 (void) vsprintf(mptsas_log_buf, fmt, ap);
9253 va_end(ap);
9254
9255 #ifdef PROM_PRINTF
9256 prom_printf("%s:\t%s\n", mptsas_label, mptsas_log_buf);
9257 #else
9258 scsi_log(dev, mptsas_label, SCSI_DEBUG, "%s\n", mptsas_log_buf);
9259 #endif
9260 mutex_exit(&mptsas_log_mutex);
9261 }
9262 #endif
9263
9264 /*
9265 * timeout handling
9266 */
9267 static void
9268 mptsas_watch(void *arg)
9269 {
9270 #ifndef __lock_lint
9271 _NOTE(ARGUNUSED(arg))
9272 #endif
9273
9274 mptsas_t *mpt;
9275 uint32_t doorbell;
9276
9277 NDBG30(("mptsas_watch"));
9278
9279 rw_enter(&mptsas_global_rwlock, RW_READER);
9280 for (mpt = mptsas_head; mpt != (mptsas_t *)NULL; mpt = mpt->m_next) {
9281
9282 mutex_enter(&mpt->m_mutex);
9283
9284 /* Skip device if not powered on */
9285 if (mpt->m_options & MPTSAS_OPT_PM) {
9286 if (mpt->m_power_level == PM_LEVEL_D0) {
9287 (void) pm_busy_component(mpt->m_dip, 0);
9288 mpt->m_busy = 1;
9289 } else {
9290 mutex_exit(&mpt->m_mutex);
9291 continue;
9292 }
9293 }
9294
9295 /*
9296 * Check if controller is in a FAULT state. If so, reset it.
9297 */
9298 doorbell = ddi_get32(mpt->m_datap, &mpt->m_reg->Doorbell);
9299 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
9300 doorbell &= MPI2_DOORBELL_DATA_MASK;
9301 mptsas_log(mpt, CE_WARN, "MPT Firmware Fault, "
9302 "code: %04x", doorbell);
9303 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
9304 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
9305 mptsas_log(mpt, CE_WARN, "Reset failed"
9306 "after fault was detected");
9307 }
9308 }
9309
9310 /*
9311 * For now, always call mptsas_watchsubr.
9312 */
9313 mptsas_watchsubr(mpt);
9314
9315 if (mpt->m_options & MPTSAS_OPT_PM) {
9316 mpt->m_busy = 0;
9317 (void) pm_idle_component(mpt->m_dip, 0);
9318 }
9319
9320 mutex_exit(&mpt->m_mutex);
9321 }
9322 rw_exit(&mptsas_global_rwlock);
9323
9324 mutex_enter(&mptsas_global_mutex);
9325 if (mptsas_timeouts_enabled)
9326 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick);
9327 mutex_exit(&mptsas_global_mutex);
9328 }
9329
9330 static void
9331 mptsas_watchsubr(mptsas_t *mpt)
9332 {
9333 int i;
9334 mptsas_cmd_t *cmd;
9335 mptsas_target_t *ptgt = NULL;
9336
9337 NDBG30(("mptsas_watchsubr: mpt=0x%p", (void *)mpt));
9338
9339 #ifdef MPTSAS_TEST
9340 if (mptsas_enable_untagged) {
9341 mptsas_test_untagged++;
9342 }
9343 #endif
9344
9345 /*
9346 * Check for commands stuck in active slot
9347 * Account for TM requests, which use the last SMID.
9348 */
9349 for (i = 0; i <= mpt->m_active->m_n_slots; i++) {
9350 if ((cmd = mpt->m_active->m_slot[i]) != NULL) {
9351 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
9352 cmd->cmd_active_timeout -=
9353 mptsas_scsi_watchdog_tick;
9354 if (cmd->cmd_active_timeout <= 0) {
9355 /*
9356 * There seems to be a command stuck
9357 * in the active slot. Drain throttle.
9358 */
9359 mptsas_set_throttle(mpt,
9360 cmd->cmd_tgt_addr,
9361 DRAIN_THROTTLE);
9362 }
9363 }
9364 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
9365 (cmd->cmd_flags & CFLAG_CONFIG) ||
9366 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
9367 cmd->cmd_active_timeout -=
9368 mptsas_scsi_watchdog_tick;
9369 if (cmd->cmd_active_timeout <= 0) {
9370 /*
9371 * passthrough command timeout
9372 */
9373 cmd->cmd_flags |= (CFLAG_FINISHED |
9374 CFLAG_TIMEOUT);
9375 cv_broadcast(&mpt->m_passthru_cv);
9376 cv_broadcast(&mpt->m_config_cv);
9377 cv_broadcast(&mpt->m_fw_diag_cv);
9378 }
9379 }
9380 }
9381 }
9382
9383 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
9384 MPTSAS_HASH_FIRST);
9385 while (ptgt != NULL) {
9386 /*
9387 * If we were draining due to a qfull condition,
9388 * go back to full throttle.
9389 */
9390 if ((ptgt->m_t_throttle < MAX_THROTTLE) &&
9391 (ptgt->m_t_throttle > HOLD_THROTTLE) &&
9392 (ptgt->m_t_ncmds < ptgt->m_t_throttle)) {
9393 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
9394 mptsas_restart_hba(mpt);
9395 }
9396
9397 if ((ptgt->m_t_ncmds > 0) &&
9398 (ptgt->m_timebase)) {
9399
9400 if (ptgt->m_timebase <=
9401 mptsas_scsi_watchdog_tick) {
9402 ptgt->m_timebase +=
9403 mptsas_scsi_watchdog_tick;
9404 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9405 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9406 continue;
9407 }
9408
9409 ptgt->m_timeout -= mptsas_scsi_watchdog_tick;
9410
9411 if (ptgt->m_timeout < 0) {
9412 mptsas_cmd_timeout(mpt, ptgt->m_devhdl);
9413 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9414 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9415 continue;
9416 }
9417
9418 if ((ptgt->m_timeout) <=
9419 mptsas_scsi_watchdog_tick) {
9420 NDBG23(("pending timeout"));
9421 mptsas_set_throttle(mpt, ptgt,
9422 DRAIN_THROTTLE);
9423 }
9424 }
9425
9426 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9427 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9428 }
9429 }
9430
9431 /*
9432 * timeout recovery
9433 */
9434 static void
9435 mptsas_cmd_timeout(mptsas_t *mpt, uint16_t devhdl)
9436 {
9437
9438 NDBG29(("mptsas_cmd_timeout: target=%d", devhdl));
9439 mptsas_log(mpt, CE_WARN, "Disconnected command timeout for "
9440 "Target %d", devhdl);
9441
9442 /*
9443 * If the current target is not the target passed in,
9444 * try to reset that target.
9445 */
9446 NDBG29(("mptsas_cmd_timeout: device reset"));
9447 if (mptsas_do_scsi_reset(mpt, devhdl) != TRUE) {
9448 mptsas_log(mpt, CE_WARN, "Target %d reset for command timeout "
9449 "recovery failed!", devhdl);
9450 }
9451 }
9452
9453 /*
9454 * Device / Hotplug control
9455 */
9456 static int
9457 mptsas_scsi_quiesce(dev_info_t *dip)
9458 {
9459 mptsas_t *mpt;
9460 scsi_hba_tran_t *tran;
9461
9462 tran = ddi_get_driver_private(dip);
9463 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL)
9464 return (-1);
9465
9466 return (mptsas_quiesce_bus(mpt));
9467 }
9468
9469 static int
9470 mptsas_scsi_unquiesce(dev_info_t *dip)
9471 {
9472 mptsas_t *mpt;
9473 scsi_hba_tran_t *tran;
9474
9475 tran = ddi_get_driver_private(dip);
9476 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL)
9477 return (-1);
9478
9479 return (mptsas_unquiesce_bus(mpt));
9480 }
9481
9482 static int
9483 mptsas_quiesce_bus(mptsas_t *mpt)
9484 {
9485 mptsas_target_t *ptgt = NULL;
9486
9487 NDBG28(("mptsas_quiesce_bus"));
9488 mutex_enter(&mpt->m_mutex);
9489
9490 /* Set all the throttles to zero */
9491 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
9492 MPTSAS_HASH_FIRST);
9493 while (ptgt != NULL) {
9494 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
9495
9496 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9497 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9498 }
9499
9500 /* If there are any outstanding commands in the queue */
9501 if (mpt->m_ncmds) {
9502 mpt->m_softstate |= MPTSAS_SS_DRAINING;
9503 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain,
9504 mpt, (MPTSAS_QUIESCE_TIMEOUT * drv_usectohz(1000000)));
9505 if (cv_wait_sig(&mpt->m_cv, &mpt->m_mutex) == 0) {
9506 /*
9507 * Quiesce has been interrupted
9508 */
9509 mpt->m_softstate &= ~MPTSAS_SS_DRAINING;
9510 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9511 &mpt->m_active->m_tgttbl, MPTSAS_HASH_FIRST);
9512 while (ptgt != NULL) {
9513 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
9514
9515 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9516 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9517 }
9518 mptsas_restart_hba(mpt);
9519 if (mpt->m_quiesce_timeid != 0) {
9520 timeout_id_t tid = mpt->m_quiesce_timeid;
9521 mpt->m_quiesce_timeid = 0;
9522 mutex_exit(&mpt->m_mutex);
9523 (void) untimeout(tid);
9524 return (-1);
9525 }
9526 mutex_exit(&mpt->m_mutex);
9527 return (-1);
9528 } else {
9529 /* Bus has been quiesced */
9530 ASSERT(mpt->m_quiesce_timeid == 0);
9531 mpt->m_softstate &= ~MPTSAS_SS_DRAINING;
9532 mpt->m_softstate |= MPTSAS_SS_QUIESCED;
9533 mutex_exit(&mpt->m_mutex);
9534 return (0);
9535 }
9536 }
9537 /* Bus was not busy - QUIESCED */
9538 mutex_exit(&mpt->m_mutex);
9539
9540 return (0);
9541 }
9542
9543 static int
9544 mptsas_unquiesce_bus(mptsas_t *mpt)
9545 {
9546 mptsas_target_t *ptgt = NULL;
9547
9548 NDBG28(("mptsas_unquiesce_bus"));
9549 mutex_enter(&mpt->m_mutex);
9550 mpt->m_softstate &= ~MPTSAS_SS_QUIESCED;
9551 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
9552 MPTSAS_HASH_FIRST);
9553 while (ptgt != NULL) {
9554 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
9555
9556 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9557 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9558 }
9559 mptsas_restart_hba(mpt);
9560 mutex_exit(&mpt->m_mutex);
9561 return (0);
9562 }
9563
9564 static void
9565 mptsas_ncmds_checkdrain(void *arg)
9566 {
9567 mptsas_t *mpt = arg;
9568 mptsas_target_t *ptgt = NULL;
9569
9570 mutex_enter(&mpt->m_mutex);
9571 if (mpt->m_softstate & MPTSAS_SS_DRAINING) {
9572 mpt->m_quiesce_timeid = 0;
9573 if (mpt->m_ncmds == 0) {
9574 /* Command queue has been drained */
9575 cv_signal(&mpt->m_cv);
9576 } else {
9577 /*
9578 * The throttle may have been reset because
9579 * of a SCSI bus reset
9580 */
9581 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9582 &mpt->m_active->m_tgttbl, MPTSAS_HASH_FIRST);
9583 while (ptgt != NULL) {
9584 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
9585
9586 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9587 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9588 }
9589
9590 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain,
9591 mpt, (MPTSAS_QUIESCE_TIMEOUT *
9592 drv_usectohz(1000000)));
9593 }
9594 }
9595 mutex_exit(&mpt->m_mutex);
9596 }
9597
9598 /*ARGSUSED*/
9599 static void
9600 mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
9601 {
9602 int i;
9603 uint8_t *cp = (uchar_t *)cmd->cmd_pkt->pkt_cdbp;
9604 char buf[128];
9605
9606 buf[0] = '\0';
9607 NDBG25(("?Cmd (0x%p) dump for Target %d Lun %d:\n", (void *)cmd,
9608 Tgt(cmd), Lun(cmd)));
9609 (void) sprintf(&buf[0], "\tcdb=[");
9610 for (i = 0; i < (int)cmd->cmd_cdblen; i++) {
9611 (void) sprintf(&buf[strlen(buf)], " 0x%x", *cp++);
9612 }
9613 (void) sprintf(&buf[strlen(buf)], " ]");
9614 NDBG25(("?%s\n", buf));
9615 NDBG25(("?pkt_flags=0x%x pkt_statistics=0x%x pkt_state=0x%x\n",
9616 cmd->cmd_pkt->pkt_flags, cmd->cmd_pkt->pkt_statistics,
9617 cmd->cmd_pkt->pkt_state));
9618 NDBG25(("?pkt_scbp=0x%x cmd_flags=0x%x\n", cmd->cmd_pkt->pkt_scbp ?
9619 *(cmd->cmd_pkt->pkt_scbp) : 0, cmd->cmd_flags));
9620 }
9621
9622 static void
9623 mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd)
9624 {
9625 caddr_t memp;
9626 pMPI2RequestHeader_t request_hdrp;
9627 struct scsi_pkt *pkt = cmd->cmd_pkt;
9628 mptsas_pt_request_t *pt = pkt->pkt_ha_private;
9629 uint32_t request_size, data_size, dataout_size;
9630 uint32_t direction;
9631 ddi_dma_cookie_t data_cookie;
9632 ddi_dma_cookie_t dataout_cookie;
9633 uint32_t request_desc_low, request_desc_high = 0;
9634 uint32_t i, sense_bufp;
9635 uint8_t desc_type;
9636 uint8_t *request, function;
9637 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl;
9638 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl;
9639
9640 desc_type = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
9641
9642 request = pt->request;
9643 direction = pt->direction;
9644 request_size = pt->request_size;
9645 data_size = pt->data_size;
9646 dataout_size = pt->dataout_size;
9647 data_cookie = pt->data_cookie;
9648 dataout_cookie = pt->dataout_cookie;
9649
9650 /*
9651 * Store the passthrough message in memory location
9652 * corresponding to our slot number
9653 */
9654 memp = mpt->m_req_frame + (mpt->m_req_frame_size * cmd->cmd_slot);
9655 request_hdrp = (pMPI2RequestHeader_t)memp;
9656 bzero(memp, mpt->m_req_frame_size);
9657
9658 for (i = 0; i < request_size; i++) {
9659 bcopy(request + i, memp + i, 1);
9660 }
9661
9662 if (data_size || dataout_size) {
9663 pMpi2SGESimple64_t sgep;
9664 uint32_t sge_flags;
9665
9666 sgep = (pMpi2SGESimple64_t)((uint8_t *)request_hdrp +
9667 request_size);
9668 if (dataout_size) {
9669
9670 sge_flags = dataout_size |
9671 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
9672 MPI2_SGE_FLAGS_END_OF_BUFFER |
9673 MPI2_SGE_FLAGS_HOST_TO_IOC |
9674 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
9675 MPI2_SGE_FLAGS_SHIFT);
9676 ddi_put32(acc_hdl, &sgep->FlagsLength, sge_flags);
9677 ddi_put32(acc_hdl, &sgep->Address.Low,
9678 (uint32_t)(dataout_cookie.dmac_laddress &
9679 0xffffffffull));
9680 ddi_put32(acc_hdl, &sgep->Address.High,
9681 (uint32_t)(dataout_cookie.dmac_laddress
9682 >> 32));
9683 sgep++;
9684 }
9685 sge_flags = data_size;
9686 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
9687 MPI2_SGE_FLAGS_LAST_ELEMENT |
9688 MPI2_SGE_FLAGS_END_OF_BUFFER |
9689 MPI2_SGE_FLAGS_END_OF_LIST |
9690 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
9691 MPI2_SGE_FLAGS_SHIFT);
9692 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) {
9693 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) <<
9694 MPI2_SGE_FLAGS_SHIFT);
9695 } else {
9696 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) <<
9697 MPI2_SGE_FLAGS_SHIFT);
9698 }
9699 ddi_put32(acc_hdl, &sgep->FlagsLength,
9700 sge_flags);
9701 ddi_put32(acc_hdl, &sgep->Address.Low,
9702 (uint32_t)(data_cookie.dmac_laddress &
9703 0xffffffffull));
9704 ddi_put32(acc_hdl, &sgep->Address.High,
9705 (uint32_t)(data_cookie.dmac_laddress >> 32));
9706 }
9707
9708 function = request_hdrp->Function;
9709 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
9710 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
9711 pMpi2SCSIIORequest_t scsi_io_req;
9712
9713 scsi_io_req = (pMpi2SCSIIORequest_t)request_hdrp;
9714 /*
9715 * Put SGE for data and data_out buffer at the end of
9716 * scsi_io_request message header.(64 bytes in total)
9717 * Following above SGEs, the residual space will be
9718 * used by sense data.
9719 */
9720 ddi_put8(acc_hdl,
9721 &scsi_io_req->SenseBufferLength,
9722 (uint8_t)(request_size - 64));
9723
9724 sense_bufp = mpt->m_req_frame_dma_addr +
9725 (mpt->m_req_frame_size * cmd->cmd_slot);
9726 sense_bufp += 64;
9727 ddi_put32(acc_hdl,
9728 &scsi_io_req->SenseBufferLowAddress, sense_bufp);
9729
9730 /*
9731 * Set SGLOffset0 value
9732 */
9733 ddi_put8(acc_hdl, &scsi_io_req->SGLOffset0,
9734 offsetof(MPI2_SCSI_IO_REQUEST, SGL) / 4);
9735
9736 /*
9737 * Setup descriptor info. RAID passthrough must use the
9738 * default request descriptor which is already set, so if this
9739 * is a SCSI IO request, change the descriptor to SCSI IO.
9740 */
9741 if (function == MPI2_FUNCTION_SCSI_IO_REQUEST) {
9742 desc_type = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
9743 request_desc_high = (ddi_get16(acc_hdl,
9744 &scsi_io_req->DevHandle) << 16);
9745 }
9746 }
9747
9748 /*
9749 * We must wait till the message has been completed before
9750 * beginning the next message so we wait for this one to
9751 * finish.
9752 */
9753 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
9754 request_desc_low = (cmd->cmd_slot << 16) + desc_type;
9755 cmd->cmd_rfm = NULL;
9756 MPTSAS_START_CMD(mpt, request_desc_low, request_desc_high);
9757 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) ||
9758 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) {
9759 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
9760 }
9761 }
9762
9763
9764
9765 static int
9766 mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply,
9767 uint8_t *data, uint32_t request_size, uint32_t reply_size,
9768 uint32_t data_size, uint32_t direction, uint8_t *dataout,
9769 uint32_t dataout_size, short timeout, int mode)
9770 {
9771 mptsas_pt_request_t pt;
9772 mptsas_dma_alloc_state_t data_dma_state;
9773 mptsas_dma_alloc_state_t dataout_dma_state;
9774 caddr_t memp;
9775 mptsas_cmd_t *cmd = NULL;
9776 struct scsi_pkt *pkt;
9777 uint32_t reply_len = 0, sense_len = 0;
9778 pMPI2RequestHeader_t request_hdrp;
9779 pMPI2RequestHeader_t request_msg;
9780 pMPI2DefaultReply_t reply_msg;
9781 Mpi2SCSIIOReply_t rep_msg;
9782 int i, status = 0, pt_flags = 0, rv = 0;
9783 int rvalue;
9784 uint8_t function;
9785
9786 ASSERT(mutex_owned(&mpt->m_mutex));
9787
9788 reply_msg = (pMPI2DefaultReply_t)(&rep_msg);
9789 bzero(reply_msg, sizeof (MPI2_DEFAULT_REPLY));
9790 request_msg = kmem_zalloc(request_size, KM_SLEEP);
9791
9792 mutex_exit(&mpt->m_mutex);
9793 /*
9794 * copy in the request buffer since it could be used by
9795 * another thread when the pt request into waitq
9796 */
9797 if (ddi_copyin(request, request_msg, request_size, mode)) {
9798 mutex_enter(&mpt->m_mutex);
9799 status = EFAULT;
9800 mptsas_log(mpt, CE_WARN, "failed to copy request data");
9801 goto out;
9802 }
9803 mutex_enter(&mpt->m_mutex);
9804
9805 function = request_msg->Function;
9806 if (function == MPI2_FUNCTION_SCSI_TASK_MGMT) {
9807 pMpi2SCSITaskManagementRequest_t task;
9808 task = (pMpi2SCSITaskManagementRequest_t)request_msg;
9809 mptsas_setup_bus_reset_delay(mpt);
9810 rv = mptsas_ioc_task_management(mpt, task->TaskType,
9811 task->DevHandle, (int)task->LUN[1], reply, reply_size,
9812 mode);
9813
9814 if (rv != TRUE) {
9815 status = EIO;
9816 mptsas_log(mpt, CE_WARN, "task management failed");
9817 }
9818 goto out;
9819 }
9820
9821 if (data_size != 0) {
9822 data_dma_state.size = data_size;
9823 if (mptsas_dma_alloc(mpt, &data_dma_state) != DDI_SUCCESS) {
9824 status = ENOMEM;
9825 mptsas_log(mpt, CE_WARN, "failed to alloc DMA "
9826 "resource");
9827 goto out;
9828 }
9829 pt_flags |= MPTSAS_DATA_ALLOCATED;
9830 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) {
9831 mutex_exit(&mpt->m_mutex);
9832 for (i = 0; i < data_size; i++) {
9833 if (ddi_copyin(data + i, (uint8_t *)
9834 data_dma_state.memp + i, 1, mode)) {
9835 mutex_enter(&mpt->m_mutex);
9836 status = EFAULT;
9837 mptsas_log(mpt, CE_WARN, "failed to "
9838 "copy read data");
9839 goto out;
9840 }
9841 }
9842 mutex_enter(&mpt->m_mutex);
9843 }
9844 }
9845
9846 if (dataout_size != 0) {
9847 dataout_dma_state.size = dataout_size;
9848 if (mptsas_dma_alloc(mpt, &dataout_dma_state) != DDI_SUCCESS) {
9849 status = ENOMEM;
9850 mptsas_log(mpt, CE_WARN, "failed to alloc DMA "
9851 "resource");
9852 goto out;
9853 }
9854 pt_flags |= MPTSAS_DATAOUT_ALLOCATED;
9855 mutex_exit(&mpt->m_mutex);
9856 for (i = 0; i < dataout_size; i++) {
9857 if (ddi_copyin(dataout + i, (uint8_t *)
9858 dataout_dma_state.memp + i, 1, mode)) {
9859 mutex_enter(&mpt->m_mutex);
9860 mptsas_log(mpt, CE_WARN, "failed to copy out"
9861 " data");
9862 status = EFAULT;
9863 goto out;
9864 }
9865 }
9866 mutex_enter(&mpt->m_mutex);
9867 }
9868
9869 if ((rvalue = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
9870 status = EAGAIN;
9871 mptsas_log(mpt, CE_NOTE, "event ack command pool is full");
9872 goto out;
9873 }
9874 pt_flags |= MPTSAS_REQUEST_POOL_CMD;
9875
9876 bzero((caddr_t)cmd, sizeof (*cmd));
9877 bzero((caddr_t)pkt, scsi_pkt_size());
9878 bzero((caddr_t)&pt, sizeof (pt));
9879
9880 cmd->ioc_cmd_slot = (uint32_t)(rvalue);
9881
9882 pt.request = (uint8_t *)request_msg;
9883 pt.direction = direction;
9884 pt.request_size = request_size;
9885 pt.data_size = data_size;
9886 pt.dataout_size = dataout_size;
9887 pt.data_cookie = data_dma_state.cookie;
9888 pt.dataout_cookie = dataout_dma_state.cookie;
9889
9890 /*
9891 * Form a blank cmd/pkt to store the acknowledgement message
9892 */
9893 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb[0];
9894 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb;
9895 pkt->pkt_ha_private = (opaque_t)&pt;
9896 pkt->pkt_flags = FLAG_HEAD;
9897 pkt->pkt_time = timeout;
9898 cmd->cmd_pkt = pkt;
9899 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_PASSTHRU;
9900
9901 /*
9902 * Save the command in a slot
9903 */
9904 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
9905 /*
9906 * Once passthru command get slot, set cmd_flags
9907 * CFLAG_PREPARED.
9908 */
9909 cmd->cmd_flags |= CFLAG_PREPARED;
9910 mptsas_start_passthru(mpt, cmd);
9911 } else {
9912 mptsas_waitq_add(mpt, cmd);
9913 }
9914
9915 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
9916 cv_wait(&mpt->m_passthru_cv, &mpt->m_mutex);
9917 }
9918
9919 if (cmd->cmd_flags & CFLAG_PREPARED) {
9920 memp = mpt->m_req_frame + (mpt->m_req_frame_size *
9921 cmd->cmd_slot);
9922 request_hdrp = (pMPI2RequestHeader_t)memp;
9923 }
9924
9925 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
9926 status = ETIMEDOUT;
9927 mptsas_log(mpt, CE_WARN, "passthrough command timeout");
9928 pt_flags |= MPTSAS_CMD_TIMEOUT;
9929 goto out;
9930 }
9931
9932 if (cmd->cmd_rfm) {
9933 /*
9934 * cmd_rfm is zero means the command reply is a CONTEXT
9935 * reply and no PCI Write to post the free reply SMFA
9936 * because no reply message frame is used.
9937 * cmd_rfm is non-zero means the reply is a ADDRESS
9938 * reply and reply message frame is used.
9939 */
9940 pt_flags |= MPTSAS_ADDRESS_REPLY;
9941 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
9942 DDI_DMA_SYNC_FORCPU);
9943 reply_msg = (pMPI2DefaultReply_t)
9944 (mpt->m_reply_frame + (cmd->cmd_rfm -
9945 mpt->m_reply_frame_dma_addr));
9946 }
9947
9948 mptsas_fma_check(mpt, cmd);
9949 if (pkt->pkt_reason == CMD_TRAN_ERR) {
9950 status = EAGAIN;
9951 mptsas_log(mpt, CE_WARN, "passthru fma error");
9952 goto out;
9953 }
9954 if (pkt->pkt_reason == CMD_RESET) {
9955 status = EAGAIN;
9956 mptsas_log(mpt, CE_WARN, "ioc reset abort passthru");
9957 goto out;
9958 }
9959
9960 if (pkt->pkt_reason == CMD_INCOMPLETE) {
9961 status = EIO;
9962 mptsas_log(mpt, CE_WARN, "passthrough command incomplete");
9963 goto out;
9964 }
9965
9966 mutex_exit(&mpt->m_mutex);
9967 if (cmd->cmd_flags & CFLAG_PREPARED) {
9968 function = request_hdrp->Function;
9969 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
9970 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
9971 reply_len = sizeof (MPI2_SCSI_IO_REPLY);
9972 sense_len = reply_size - reply_len;
9973 } else {
9974 reply_len = reply_size;
9975 sense_len = 0;
9976 }
9977
9978 for (i = 0; i < reply_len; i++) {
9979 if (ddi_copyout((uint8_t *)reply_msg + i, reply + i, 1,
9980 mode)) {
9981 mutex_enter(&mpt->m_mutex);
9982 status = EFAULT;
9983 mptsas_log(mpt, CE_WARN, "failed to copy out "
9984 "reply data");
9985 goto out;
9986 }
9987 }
9988 for (i = 0; i < sense_len; i++) {
9989 if (ddi_copyout((uint8_t *)request_hdrp + 64 + i,
9990 reply + reply_len + i, 1, mode)) {
9991 mutex_enter(&mpt->m_mutex);
9992 status = EFAULT;
9993 mptsas_log(mpt, CE_WARN, "failed to copy out "
9994 "sense data");
9995 goto out;
9996 }
9997 }
9998 }
9999
10000 if (data_size) {
10001 if (direction != MPTSAS_PASS_THRU_DIRECTION_WRITE) {
10002 (void) ddi_dma_sync(data_dma_state.handle, 0, 0,
10003 DDI_DMA_SYNC_FORCPU);
10004 for (i = 0; i < data_size; i++) {
10005 if (ddi_copyout((uint8_t *)(
10006 data_dma_state.memp + i), data + i, 1,
10007 mode)) {
10008 mutex_enter(&mpt->m_mutex);
10009 status = EFAULT;
10010 mptsas_log(mpt, CE_WARN, "failed to "
10011 "copy out the reply data");
10012 goto out;
10013 }
10014 }
10015 }
10016 }
10017 mutex_enter(&mpt->m_mutex);
10018 out:
10019 /*
10020 * Put the reply frame back on the free queue, increment the free
10021 * index, and write the new index to the free index register. But only
10022 * if this reply is an ADDRESS reply.
10023 */
10024 if (pt_flags & MPTSAS_ADDRESS_REPLY) {
10025 ddi_put32(mpt->m_acc_free_queue_hdl,
10026 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
10027 cmd->cmd_rfm);
10028 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
10029 DDI_DMA_SYNC_FORDEV);
10030 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
10031 mpt->m_free_index = 0;
10032 }
10033 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
10034 mpt->m_free_index);
10035 }
10036 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
10037 mptsas_remove_cmd(mpt, cmd);
10038 pt_flags &= (~MPTSAS_REQUEST_POOL_CMD);
10039 }
10040 if (pt_flags & MPTSAS_REQUEST_POOL_CMD)
10041 mptsas_return_to_pool(mpt, cmd);
10042 if (pt_flags & MPTSAS_DATA_ALLOCATED) {
10043 if (mptsas_check_dma_handle(data_dma_state.handle) !=
10044 DDI_SUCCESS) {
10045 ddi_fm_service_impact(mpt->m_dip,
10046 DDI_SERVICE_UNAFFECTED);
10047 status = EFAULT;
10048 }
10049 mptsas_dma_free(&data_dma_state);
10050 }
10051 if (pt_flags & MPTSAS_DATAOUT_ALLOCATED) {
10052 if (mptsas_check_dma_handle(dataout_dma_state.handle) !=
10053 DDI_SUCCESS) {
10054 ddi_fm_service_impact(mpt->m_dip,
10055 DDI_SERVICE_UNAFFECTED);
10056 status = EFAULT;
10057 }
10058 mptsas_dma_free(&dataout_dma_state);
10059 }
10060 if (pt_flags & MPTSAS_CMD_TIMEOUT) {
10061 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
10062 mptsas_log(mpt, CE_WARN, "mptsas_restart_ioc failed");
10063 }
10064 }
10065 if (request_msg)
10066 kmem_free(request_msg, request_size);
10067
10068 return (status);
10069 }
10070
10071 static int
10072 mptsas_pass_thru(mptsas_t *mpt, mptsas_pass_thru_t *data, int mode)
10073 {
10074 /*
10075 * If timeout is 0, set timeout to default of 60 seconds.
10076 */
10077 if (data->Timeout == 0) {
10078 data->Timeout = MPTSAS_PASS_THRU_TIME_DEFAULT;
10079 }
10080
10081 if (((data->DataSize == 0) &&
10082 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_NONE)) ||
10083 ((data->DataSize != 0) &&
10084 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_READ) ||
10085 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_WRITE) ||
10086 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) &&
10087 (data->DataOutSize != 0))))) {
10088 if (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) {
10089 data->DataDirection = MPTSAS_PASS_THRU_DIRECTION_READ;
10090 } else {
10091 data->DataOutSize = 0;
10092 }
10093 /*
10094 * Send passthru request messages
10095 */
10096 return (mptsas_do_passthru(mpt,
10097 (uint8_t *)((uintptr_t)data->PtrRequest),
10098 (uint8_t *)((uintptr_t)data->PtrReply),
10099 (uint8_t *)((uintptr_t)data->PtrData),
10100 data->RequestSize, data->ReplySize,
10101 data->DataSize, data->DataDirection,
10102 (uint8_t *)((uintptr_t)data->PtrDataOut),
10103 data->DataOutSize, data->Timeout, mode));
10104 } else {
10105 return (EINVAL);
10106 }
10107 }
10108
10109 static uint8_t
10110 mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, uint32_t unique_id)
10111 {
10112 uint8_t index;
10113
10114 for (index = 0; index < MPI2_DIAG_BUF_TYPE_COUNT; index++) {
10115 if (mpt->m_fw_diag_buffer_list[index].unique_id == unique_id) {
10116 return (index);
10117 }
10118 }
10119
10120 return (MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND);
10121 }
10122
10123 static void
10124 mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd)
10125 {
10126 pMpi2DiagBufferPostRequest_t pDiag_post_msg;
10127 pMpi2DiagReleaseRequest_t pDiag_release_msg;
10128 struct scsi_pkt *pkt = cmd->cmd_pkt;
10129 mptsas_diag_request_t *diag = pkt->pkt_ha_private;
10130 uint32_t request_desc_low, i;
10131
10132 ASSERT(mutex_owned(&mpt->m_mutex));
10133
10134 /*
10135 * Form the diag message depending on the post or release function.
10136 */
10137 if (diag->function == MPI2_FUNCTION_DIAG_BUFFER_POST) {
10138 pDiag_post_msg = (pMpi2DiagBufferPostRequest_t)
10139 (mpt->m_req_frame + (mpt->m_req_frame_size *
10140 cmd->cmd_slot));
10141 bzero(pDiag_post_msg, mpt->m_req_frame_size);
10142 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->Function,
10143 diag->function);
10144 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->BufferType,
10145 diag->pBuffer->buffer_type);
10146 ddi_put8(mpt->m_acc_req_frame_hdl,
10147 &pDiag_post_msg->ExtendedType,
10148 diag->pBuffer->extended_type);
10149 ddi_put32(mpt->m_acc_req_frame_hdl,
10150 &pDiag_post_msg->BufferLength,
10151 diag->pBuffer->buffer_data.size);
10152 for (i = 0; i < (sizeof (pDiag_post_msg->ProductSpecific) / 4);
10153 i++) {
10154 ddi_put32(mpt->m_acc_req_frame_hdl,
10155 &pDiag_post_msg->ProductSpecific[i],
10156 diag->pBuffer->product_specific[i]);
10157 }
10158 ddi_put32(mpt->m_acc_req_frame_hdl,
10159 &pDiag_post_msg->BufferAddress.Low,
10160 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress
10161 & 0xffffffffull));
10162 ddi_put32(mpt->m_acc_req_frame_hdl,
10163 &pDiag_post_msg->BufferAddress.High,
10164 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress
10165 >> 32));
10166 } else {
10167 pDiag_release_msg = (pMpi2DiagReleaseRequest_t)
10168 (mpt->m_req_frame + (mpt->m_req_frame_size *
10169 cmd->cmd_slot));
10170 bzero(pDiag_release_msg, mpt->m_req_frame_size);
10171 ddi_put8(mpt->m_acc_req_frame_hdl,
10172 &pDiag_release_msg->Function, diag->function);
10173 ddi_put8(mpt->m_acc_req_frame_hdl,
10174 &pDiag_release_msg->BufferType,
10175 diag->pBuffer->buffer_type);
10176 }
10177
10178 /*
10179 * Send the message
10180 */
10181 (void) ddi_dma_sync(mpt->m_dma_req_frame_hdl, 0, 0,
10182 DDI_DMA_SYNC_FORDEV);
10183 request_desc_low = (cmd->cmd_slot << 16) +
10184 MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
10185 cmd->cmd_rfm = NULL;
10186 MPTSAS_START_CMD(mpt, request_desc_low, 0);
10187 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
10188 DDI_SUCCESS) ||
10189 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
10190 DDI_SUCCESS)) {
10191 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
10192 }
10193 }
10194
10195 static int
10196 mptsas_post_fw_diag_buffer(mptsas_t *mpt,
10197 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code)
10198 {
10199 mptsas_diag_request_t diag;
10200 int status, slot_num, post_flags = 0;
10201 mptsas_cmd_t *cmd = NULL;
10202 struct scsi_pkt *pkt;
10203 pMpi2DiagBufferPostReply_t reply;
10204 uint16_t iocstatus;
10205 uint32_t iocloginfo, transfer_length;
10206
10207 /*
10208 * If buffer is not enabled, just leave.
10209 */
10210 *return_code = MPTSAS_FW_DIAG_ERROR_POST_FAILED;
10211 if (!pBuffer->enabled) {
10212 status = DDI_FAILURE;
10213 goto out;
10214 }
10215
10216 /*
10217 * Clear some flags initially.
10218 */
10219 pBuffer->force_release = FALSE;
10220 pBuffer->valid_data = FALSE;
10221 pBuffer->owned_by_firmware = FALSE;
10222
10223 /*
10224 * Get a cmd buffer from the cmd buffer pool
10225 */
10226 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
10227 status = DDI_FAILURE;
10228 mptsas_log(mpt, CE_NOTE, "command pool is full: Post FW Diag");
10229 goto out;
10230 }
10231 post_flags |= MPTSAS_REQUEST_POOL_CMD;
10232
10233 bzero((caddr_t)cmd, sizeof (*cmd));
10234 bzero((caddr_t)pkt, scsi_pkt_size());
10235
10236 cmd->ioc_cmd_slot = (uint32_t)(slot_num);
10237
10238 diag.pBuffer = pBuffer;
10239 diag.function = MPI2_FUNCTION_DIAG_BUFFER_POST;
10240
10241 /*
10242 * Form a blank cmd/pkt to store the acknowledgement message
10243 */
10244 pkt->pkt_ha_private = (opaque_t)&diag;
10245 pkt->pkt_flags = FLAG_HEAD;
10246 pkt->pkt_time = 60;
10247 cmd->cmd_pkt = pkt;
10248 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG;
10249
10250 /*
10251 * Save the command in a slot
10252 */
10253 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
10254 /*
10255 * Once passthru command get slot, set cmd_flags
10256 * CFLAG_PREPARED.
10257 */
10258 cmd->cmd_flags |= CFLAG_PREPARED;
10259 mptsas_start_diag(mpt, cmd);
10260 } else {
10261 mptsas_waitq_add(mpt, cmd);
10262 }
10263
10264 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
10265 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex);
10266 }
10267
10268 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
10269 status = DDI_FAILURE;
10270 mptsas_log(mpt, CE_WARN, "Post FW Diag command timeout");
10271 goto out;
10272 }
10273
10274 /*
10275 * cmd_rfm points to the reply message if a reply was given. Check the
10276 * IOCStatus to make sure everything went OK with the FW diag request
10277 * and set buffer flags.
10278 */
10279 if (cmd->cmd_rfm) {
10280 post_flags |= MPTSAS_ADDRESS_REPLY;
10281 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
10282 DDI_DMA_SYNC_FORCPU);
10283 reply = (pMpi2DiagBufferPostReply_t)(mpt->m_reply_frame +
10284 (cmd->cmd_rfm - mpt->m_reply_frame_dma_addr));
10285
10286 /*
10287 * Get the reply message data
10288 */
10289 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
10290 &reply->IOCStatus);
10291 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
10292 &reply->IOCLogInfo);
10293 transfer_length = ddi_get32(mpt->m_acc_reply_frame_hdl,
10294 &reply->TransferLength);
10295
10296 /*
10297 * If post failed quit.
10298 */
10299 if (iocstatus != MPI2_IOCSTATUS_SUCCESS) {
10300 status = DDI_FAILURE;
10301 NDBG13(("post FW Diag Buffer failed: IOCStatus=0x%x, "
10302 "IOCLogInfo=0x%x, TransferLength=0x%x", iocstatus,
10303 iocloginfo, transfer_length));
10304 goto out;
10305 }
10306
10307 /*
10308 * Post was successful.
10309 */
10310 pBuffer->valid_data = TRUE;
10311 pBuffer->owned_by_firmware = TRUE;
10312 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
10313 status = DDI_SUCCESS;
10314 }
10315
10316 out:
10317 /*
10318 * Put the reply frame back on the free queue, increment the free
10319 * index, and write the new index to the free index register. But only
10320 * if this reply is an ADDRESS reply.
10321 */
10322 if (post_flags & MPTSAS_ADDRESS_REPLY) {
10323 ddi_put32(mpt->m_acc_free_queue_hdl,
10324 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
10325 cmd->cmd_rfm);
10326 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
10327 DDI_DMA_SYNC_FORDEV);
10328 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
10329 mpt->m_free_index = 0;
10330 }
10331 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
10332 mpt->m_free_index);
10333 }
10334 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
10335 mptsas_remove_cmd(mpt, cmd);
10336 post_flags &= (~MPTSAS_REQUEST_POOL_CMD);
10337 }
10338 if (post_flags & MPTSAS_REQUEST_POOL_CMD) {
10339 mptsas_return_to_pool(mpt, cmd);
10340 }
10341
10342 return (status);
10343 }
10344
10345 static int
10346 mptsas_release_fw_diag_buffer(mptsas_t *mpt,
10347 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code,
10348 uint32_t diag_type)
10349 {
10350 mptsas_diag_request_t diag;
10351 int status, slot_num, rel_flags = 0;
10352 mptsas_cmd_t *cmd = NULL;
10353 struct scsi_pkt *pkt;
10354 pMpi2DiagReleaseReply_t reply;
10355 uint16_t iocstatus;
10356 uint32_t iocloginfo;
10357
10358 /*
10359 * If buffer is not enabled, just leave.
10360 */
10361 *return_code = MPTSAS_FW_DIAG_ERROR_RELEASE_FAILED;
10362 if (!pBuffer->enabled) {
10363 mptsas_log(mpt, CE_NOTE, "This buffer type is not supported "
10364 "by the IOC");
10365 status = DDI_FAILURE;
10366 goto out;
10367 }
10368
10369 /*
10370 * Clear some flags initially.
10371 */
10372 pBuffer->force_release = FALSE;
10373 pBuffer->valid_data = FALSE;
10374 pBuffer->owned_by_firmware = FALSE;
10375
10376 /*
10377 * Get a cmd buffer from the cmd buffer pool
10378 */
10379 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
10380 status = DDI_FAILURE;
10381 mptsas_log(mpt, CE_NOTE, "command pool is full: Release FW "
10382 "Diag");
10383 goto out;
10384 }
10385 rel_flags |= MPTSAS_REQUEST_POOL_CMD;
10386
10387 bzero((caddr_t)cmd, sizeof (*cmd));
10388 bzero((caddr_t)pkt, scsi_pkt_size());
10389
10390 cmd->ioc_cmd_slot = (uint32_t)(slot_num);
10391
10392 diag.pBuffer = pBuffer;
10393 diag.function = MPI2_FUNCTION_DIAG_RELEASE;
10394
10395 /*
10396 * Form a blank cmd/pkt to store the acknowledgement message
10397 */
10398 pkt->pkt_ha_private = (opaque_t)&diag;
10399 pkt->pkt_flags = FLAG_HEAD;
10400 pkt->pkt_time = 60;
10401 cmd->cmd_pkt = pkt;
10402 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG;
10403
10404 /*
10405 * Save the command in a slot
10406 */
10407 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
10408 /*
10409 * Once passthru command get slot, set cmd_flags
10410 * CFLAG_PREPARED.
10411 */
10412 cmd->cmd_flags |= CFLAG_PREPARED;
10413 mptsas_start_diag(mpt, cmd);
10414 } else {
10415 mptsas_waitq_add(mpt, cmd);
10416 }
10417
10418 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
10419 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex);
10420 }
10421
10422 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
10423 status = DDI_FAILURE;
10424 mptsas_log(mpt, CE_WARN, "Release FW Diag command timeout");
10425 goto out;
10426 }
10427
10428 /*
10429 * cmd_rfm points to the reply message if a reply was given. Check the
10430 * IOCStatus to make sure everything went OK with the FW diag request
10431 * and set buffer flags.
10432 */
10433 if (cmd->cmd_rfm) {
10434 rel_flags |= MPTSAS_ADDRESS_REPLY;
10435 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
10436 DDI_DMA_SYNC_FORCPU);
10437 reply = (pMpi2DiagReleaseReply_t)(mpt->m_reply_frame +
10438 (cmd->cmd_rfm - mpt->m_reply_frame_dma_addr));
10439
10440 /*
10441 * Get the reply message data
10442 */
10443 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
10444 &reply->IOCStatus);
10445 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
10446 &reply->IOCLogInfo);
10447
10448 /*
10449 * If release failed quit.
10450 */
10451 if ((iocstatus != MPI2_IOCSTATUS_SUCCESS) ||
10452 pBuffer->owned_by_firmware) {
10453 status = DDI_FAILURE;
10454 NDBG13(("release FW Diag Buffer failed: "
10455 "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus,
10456 iocloginfo));
10457 goto out;
10458 }
10459
10460 /*
10461 * Release was successful.
10462 */
10463 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
10464 status = DDI_SUCCESS;
10465
10466 /*
10467 * If this was for an UNREGISTER diag type command, clear the
10468 * unique ID.
10469 */
10470 if (diag_type == MPTSAS_FW_DIAG_TYPE_UNREGISTER) {
10471 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID;
10472 }
10473 }
10474
10475 out:
10476 /*
10477 * Put the reply frame back on the free queue, increment the free
10478 * index, and write the new index to the free index register. But only
10479 * if this reply is an ADDRESS reply.
10480 */
10481 if (rel_flags & MPTSAS_ADDRESS_REPLY) {
10482 ddi_put32(mpt->m_acc_free_queue_hdl,
10483 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
10484 cmd->cmd_rfm);
10485 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
10486 DDI_DMA_SYNC_FORDEV);
10487 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
10488 mpt->m_free_index = 0;
10489 }
10490 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
10491 mpt->m_free_index);
10492 }
10493 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
10494 mptsas_remove_cmd(mpt, cmd);
10495 rel_flags &= (~MPTSAS_REQUEST_POOL_CMD);
10496 }
10497 if (rel_flags & MPTSAS_REQUEST_POOL_CMD) {
10498 mptsas_return_to_pool(mpt, cmd);
10499 }
10500
10501 return (status);
10502 }
10503
10504 static int
10505 mptsas_diag_register(mptsas_t *mpt, mptsas_fw_diag_register_t *diag_register,
10506 uint32_t *return_code)
10507 {
10508 mptsas_fw_diagnostic_buffer_t *pBuffer;
10509 uint8_t extended_type, buffer_type, i;
10510 uint32_t buffer_size;
10511 uint32_t unique_id;
10512 int status;
10513
10514 ASSERT(mutex_owned(&mpt->m_mutex));
10515
10516 extended_type = diag_register->ExtendedType;
10517 buffer_type = diag_register->BufferType;
10518 buffer_size = diag_register->RequestedBufferSize;
10519 unique_id = diag_register->UniqueId;
10520
10521 /*
10522 * Check for valid buffer type
10523 */
10524 if (buffer_type >= MPI2_DIAG_BUF_TYPE_COUNT) {
10525 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10526 return (DDI_FAILURE);
10527 }
10528
10529 /*
10530 * Get the current buffer and look up the unique ID. The unique ID
10531 * should not be found. If it is, the ID is already in use.
10532 */
10533 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
10534 pBuffer = &mpt->m_fw_diag_buffer_list[buffer_type];
10535 if (i != MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
10536 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10537 return (DDI_FAILURE);
10538 }
10539
10540 /*
10541 * The buffer's unique ID should not be registered yet, and the given
10542 * unique ID cannot be 0.
10543 */
10544 if ((pBuffer->unique_id != MPTSAS_FW_DIAG_INVALID_UID) ||
10545 (unique_id == MPTSAS_FW_DIAG_INVALID_UID)) {
10546 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10547 return (DDI_FAILURE);
10548 }
10549
10550 /*
10551 * If this buffer is already posted as immediate, just change owner.
10552 */
10553 if (pBuffer->immediate && pBuffer->owned_by_firmware &&
10554 (pBuffer->unique_id == MPTSAS_FW_DIAG_INVALID_UID)) {
10555 pBuffer->immediate = FALSE;
10556 pBuffer->unique_id = unique_id;
10557 return (DDI_SUCCESS);
10558 }
10559
10560 /*
10561 * Post a new buffer after checking if it's enabled. The DMA buffer
10562 * that is allocated will be contiguous (sgl_len = 1).
10563 */
10564 if (!pBuffer->enabled) {
10565 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER;
10566 return (DDI_FAILURE);
10567 }
10568 bzero(&pBuffer->buffer_data, sizeof (mptsas_dma_alloc_state_t));
10569 pBuffer->buffer_data.size = buffer_size;
10570 if (mptsas_dma_alloc(mpt, &pBuffer->buffer_data) != DDI_SUCCESS) {
10571 mptsas_log(mpt, CE_WARN, "failed to alloc DMA resource for "
10572 "diag buffer: size = %d bytes", buffer_size);
10573 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER;
10574 return (DDI_FAILURE);
10575 }
10576
10577 /*
10578 * Copy the given info to the diag buffer and post the buffer.
10579 */
10580 pBuffer->buffer_type = buffer_type;
10581 pBuffer->immediate = FALSE;
10582 if (buffer_type == MPI2_DIAG_BUF_TYPE_TRACE) {
10583 for (i = 0; i < (sizeof (pBuffer->product_specific) / 4);
10584 i++) {
10585 pBuffer->product_specific[i] =
10586 diag_register->ProductSpecific[i];
10587 }
10588 }
10589 pBuffer->extended_type = extended_type;
10590 pBuffer->unique_id = unique_id;
10591 status = mptsas_post_fw_diag_buffer(mpt, pBuffer, return_code);
10592
10593 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) !=
10594 DDI_SUCCESS) {
10595 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed in "
10596 "mptsas_diag_register.");
10597 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
10598 status = DDI_FAILURE;
10599 }
10600
10601 /*
10602 * In case there was a failure, free the DMA buffer.
10603 */
10604 if (status == DDI_FAILURE) {
10605 mptsas_dma_free(&pBuffer->buffer_data);
10606 }
10607
10608 return (status);
10609 }
10610
10611 static int
10612 mptsas_diag_unregister(mptsas_t *mpt,
10613 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code)
10614 {
10615 mptsas_fw_diagnostic_buffer_t *pBuffer;
10616 uint8_t i;
10617 uint32_t unique_id;
10618 int status;
10619
10620 ASSERT(mutex_owned(&mpt->m_mutex));
10621
10622 unique_id = diag_unregister->UniqueId;
10623
10624 /*
10625 * Get the current buffer and look up the unique ID. The unique ID
10626 * should be there.
10627 */
10628 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
10629 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
10630 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10631 return (DDI_FAILURE);
10632 }
10633
10634 pBuffer = &mpt->m_fw_diag_buffer_list[i];
10635
10636 /*
10637 * Try to release the buffer from FW before freeing it. If release
10638 * fails, don't free the DMA buffer in case FW tries to access it
10639 * later. If buffer is not owned by firmware, can't release it.
10640 */
10641 if (!pBuffer->owned_by_firmware) {
10642 status = DDI_SUCCESS;
10643 } else {
10644 status = mptsas_release_fw_diag_buffer(mpt, pBuffer,
10645 return_code, MPTSAS_FW_DIAG_TYPE_UNREGISTER);
10646 }
10647
10648 /*
10649 * At this point, return the current status no matter what happens with
10650 * the DMA buffer.
10651 */
10652 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID;
10653 if (status == DDI_SUCCESS) {
10654 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) !=
10655 DDI_SUCCESS) {
10656 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed "
10657 "in mptsas_diag_unregister.");
10658 ddi_fm_service_impact(mpt->m_dip,
10659 DDI_SERVICE_UNAFFECTED);
10660 }
10661 mptsas_dma_free(&pBuffer->buffer_data);
10662 }
10663
10664 return (status);
10665 }
10666
10667 static int
10668 mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query,
10669 uint32_t *return_code)
10670 {
10671 mptsas_fw_diagnostic_buffer_t *pBuffer;
10672 uint8_t i;
10673 uint32_t unique_id;
10674
10675 ASSERT(mutex_owned(&mpt->m_mutex));
10676
10677 unique_id = diag_query->UniqueId;
10678
10679 /*
10680 * If ID is valid, query on ID.
10681 * If ID is invalid, query on buffer type.
10682 */
10683 if (unique_id == MPTSAS_FW_DIAG_INVALID_UID) {
10684 i = diag_query->BufferType;
10685 if (i >= MPI2_DIAG_BUF_TYPE_COUNT) {
10686 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10687 return (DDI_FAILURE);
10688 }
10689 } else {
10690 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
10691 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
10692 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10693 return (DDI_FAILURE);
10694 }
10695 }
10696
10697 /*
10698 * Fill query structure with the diag buffer info.
10699 */
10700 pBuffer = &mpt->m_fw_diag_buffer_list[i];
10701 diag_query->BufferType = pBuffer->buffer_type;
10702 diag_query->ExtendedType = pBuffer->extended_type;
10703 if (diag_query->BufferType == MPI2_DIAG_BUF_TYPE_TRACE) {
10704 for (i = 0; i < (sizeof (diag_query->ProductSpecific) / 4);
10705 i++) {
10706 diag_query->ProductSpecific[i] =
10707 pBuffer->product_specific[i];
10708 }
10709 }
10710 diag_query->TotalBufferSize = pBuffer->buffer_data.size;
10711 diag_query->DriverAddedBufferSize = 0;
10712 diag_query->UniqueId = pBuffer->unique_id;
10713 diag_query->ApplicationFlags = 0;
10714 diag_query->DiagnosticFlags = 0;
10715
10716 /*
10717 * Set/Clear application flags
10718 */
10719 if (pBuffer->immediate) {
10720 diag_query->ApplicationFlags &= ~MPTSAS_FW_DIAG_FLAG_APP_OWNED;
10721 } else {
10722 diag_query->ApplicationFlags |= MPTSAS_FW_DIAG_FLAG_APP_OWNED;
10723 }
10724 if (pBuffer->valid_data || pBuffer->owned_by_firmware) {
10725 diag_query->ApplicationFlags |=
10726 MPTSAS_FW_DIAG_FLAG_BUFFER_VALID;
10727 } else {
10728 diag_query->ApplicationFlags &=
10729 ~MPTSAS_FW_DIAG_FLAG_BUFFER_VALID;
10730 }
10731 if (pBuffer->owned_by_firmware) {
10732 diag_query->ApplicationFlags |=
10733 MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS;
10734 } else {
10735 diag_query->ApplicationFlags &=
10736 ~MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS;
10737 }
10738
10739 return (DDI_SUCCESS);
10740 }
10741
10742 static int
10743 mptsas_diag_read_buffer(mptsas_t *mpt,
10744 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf,
10745 uint32_t *return_code, int ioctl_mode)
10746 {
10747 mptsas_fw_diagnostic_buffer_t *pBuffer;
10748 uint8_t i, *pData;
10749 uint32_t unique_id, byte;
10750 int status;
10751
10752 ASSERT(mutex_owned(&mpt->m_mutex));
10753
10754 unique_id = diag_read_buffer->UniqueId;
10755
10756 /*
10757 * Get the current buffer and look up the unique ID. The unique ID
10758 * should be there.
10759 */
10760 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
10761 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
10762 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10763 return (DDI_FAILURE);
10764 }
10765
10766 pBuffer = &mpt->m_fw_diag_buffer_list[i];
10767
10768 /*
10769 * Make sure requested read is within limits
10770 */
10771 if (diag_read_buffer->StartingOffset + diag_read_buffer->BytesToRead >
10772 pBuffer->buffer_data.size) {
10773 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10774 return (DDI_FAILURE);
10775 }
10776
10777 /*
10778 * Copy the requested data from DMA to the diag_read_buffer. The DMA
10779 * buffer that was allocated is one contiguous buffer.
10780 */
10781 pData = (uint8_t *)(pBuffer->buffer_data.memp +
10782 diag_read_buffer->StartingOffset);
10783 (void) ddi_dma_sync(pBuffer->buffer_data.handle, 0, 0,
10784 DDI_DMA_SYNC_FORCPU);
10785 for (byte = 0; byte < diag_read_buffer->BytesToRead; byte++) {
10786 if (ddi_copyout(pData + byte, ioctl_buf + byte, 1, ioctl_mode)
10787 != 0) {
10788 return (DDI_FAILURE);
10789 }
10790 }
10791 diag_read_buffer->Status = 0;
10792
10793 /*
10794 * Set or clear the Force Release flag.
10795 */
10796 if (pBuffer->force_release) {
10797 diag_read_buffer->Flags |= MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE;
10798 } else {
10799 diag_read_buffer->Flags &= ~MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE;
10800 }
10801
10802 /*
10803 * If buffer is to be reregistered, make sure it's not already owned by
10804 * firmware first.
10805 */
10806 status = DDI_SUCCESS;
10807 if (!pBuffer->owned_by_firmware) {
10808 if (diag_read_buffer->Flags & MPTSAS_FW_DIAG_FLAG_REREGISTER) {
10809 status = mptsas_post_fw_diag_buffer(mpt, pBuffer,
10810 return_code);
10811 }
10812 }
10813
10814 return (status);
10815 }
10816
10817 static int
10818 mptsas_diag_release(mptsas_t *mpt, mptsas_fw_diag_release_t *diag_release,
10819 uint32_t *return_code)
10820 {
10821 mptsas_fw_diagnostic_buffer_t *pBuffer;
10822 uint8_t i;
10823 uint32_t unique_id;
10824 int status;
10825
10826 ASSERT(mutex_owned(&mpt->m_mutex));
10827
10828 unique_id = diag_release->UniqueId;
10829
10830 /*
10831 * Get the current buffer and look up the unique ID. The unique ID
10832 * should be there.
10833 */
10834 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
10835 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
10836 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10837 return (DDI_FAILURE);
10838 }
10839
10840 pBuffer = &mpt->m_fw_diag_buffer_list[i];
10841
10842 /*
10843 * If buffer is not owned by firmware, it's already been released.
10844 */
10845 if (!pBuffer->owned_by_firmware) {
10846 *return_code = MPTSAS_FW_DIAG_ERROR_ALREADY_RELEASED;
10847 return (DDI_FAILURE);
10848 }
10849
10850 /*
10851 * Release the buffer.
10852 */
10853 status = mptsas_release_fw_diag_buffer(mpt, pBuffer, return_code,
10854 MPTSAS_FW_DIAG_TYPE_RELEASE);
10855 return (status);
10856 }
10857
10858 static int
10859 mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, uint8_t *diag_action,
10860 uint32_t length, uint32_t *return_code, int ioctl_mode)
10861 {
10862 mptsas_fw_diag_register_t diag_register;
10863 mptsas_fw_diag_unregister_t diag_unregister;
10864 mptsas_fw_diag_query_t diag_query;
10865 mptsas_diag_read_buffer_t diag_read_buffer;
10866 mptsas_fw_diag_release_t diag_release;
10867 int status = DDI_SUCCESS;
10868 uint32_t original_return_code, read_buf_len;
10869
10870 ASSERT(mutex_owned(&mpt->m_mutex));
10871
10872 original_return_code = *return_code;
10873 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
10874
10875 switch (action) {
10876 case MPTSAS_FW_DIAG_TYPE_REGISTER:
10877 if (!length) {
10878 *return_code =
10879 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10880 status = DDI_FAILURE;
10881 break;
10882 }
10883 if (ddi_copyin(diag_action, &diag_register,
10884 sizeof (diag_register), ioctl_mode) != 0) {
10885 return (DDI_FAILURE);
10886 }
10887 status = mptsas_diag_register(mpt, &diag_register,
10888 return_code);
10889 break;
10890
10891 case MPTSAS_FW_DIAG_TYPE_UNREGISTER:
10892 if (length < sizeof (diag_unregister)) {
10893 *return_code =
10894 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10895 status = DDI_FAILURE;
10896 break;
10897 }
10898 if (ddi_copyin(diag_action, &diag_unregister,
10899 sizeof (diag_unregister), ioctl_mode) != 0) {
10900 return (DDI_FAILURE);
10901 }
10902 status = mptsas_diag_unregister(mpt, &diag_unregister,
10903 return_code);
10904 break;
10905
10906 case MPTSAS_FW_DIAG_TYPE_QUERY:
10907 if (length < sizeof (diag_query)) {
10908 *return_code =
10909 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10910 status = DDI_FAILURE;
10911 break;
10912 }
10913 if (ddi_copyin(diag_action, &diag_query,
10914 sizeof (diag_query), ioctl_mode) != 0) {
10915 return (DDI_FAILURE);
10916 }
10917 status = mptsas_diag_query(mpt, &diag_query,
10918 return_code);
10919 if (status == DDI_SUCCESS) {
10920 if (ddi_copyout(&diag_query, diag_action,
10921 sizeof (diag_query), ioctl_mode) != 0) {
10922 return (DDI_FAILURE);
10923 }
10924 }
10925 break;
10926
10927 case MPTSAS_FW_DIAG_TYPE_READ_BUFFER:
10928 if (ddi_copyin(diag_action, &diag_read_buffer,
10929 sizeof (diag_read_buffer) - 4, ioctl_mode) != 0) {
10930 return (DDI_FAILURE);
10931 }
10932 read_buf_len = sizeof (diag_read_buffer) -
10933 sizeof (diag_read_buffer.DataBuffer) +
10934 diag_read_buffer.BytesToRead;
10935 if (length < read_buf_len) {
10936 *return_code =
10937 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10938 status = DDI_FAILURE;
10939 break;
10940 }
10941 status = mptsas_diag_read_buffer(mpt,
10942 &diag_read_buffer, diag_action +
10943 sizeof (diag_read_buffer) - 4, return_code,
10944 ioctl_mode);
10945 if (status == DDI_SUCCESS) {
10946 if (ddi_copyout(&diag_read_buffer, diag_action,
10947 sizeof (diag_read_buffer) - 4, ioctl_mode)
10948 != 0) {
10949 return (DDI_FAILURE);
10950 }
10951 }
10952 break;
10953
10954 case MPTSAS_FW_DIAG_TYPE_RELEASE:
10955 if (length < sizeof (diag_release)) {
10956 *return_code =
10957 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10958 status = DDI_FAILURE;
10959 break;
10960 }
10961 if (ddi_copyin(diag_action, &diag_release,
10962 sizeof (diag_release), ioctl_mode) != 0) {
10963 return (DDI_FAILURE);
10964 }
10965 status = mptsas_diag_release(mpt, &diag_release,
10966 return_code);
10967 break;
10968
10969 default:
10970 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10971 status = DDI_FAILURE;
10972 break;
10973 }
10974
10975 if ((status == DDI_FAILURE) &&
10976 (original_return_code == MPTSAS_FW_DIAG_NEW) &&
10977 (*return_code != MPTSAS_FW_DIAG_ERROR_SUCCESS)) {
10978 status = DDI_SUCCESS;
10979 }
10980
10981 return (status);
10982 }
10983
10984 static int
10985 mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *user_data, int mode)
10986 {
10987 int status;
10988 mptsas_diag_action_t driver_data;
10989
10990 ASSERT(mutex_owned(&mpt->m_mutex));
10991
10992 /*
10993 * Copy the user data to a driver data buffer.
10994 */
10995 if (ddi_copyin(user_data, &driver_data, sizeof (mptsas_diag_action_t),
10996 mode) == 0) {
10997 /*
10998 * Send diag action request if Action is valid
10999 */
11000 if (driver_data.Action == MPTSAS_FW_DIAG_TYPE_REGISTER ||
11001 driver_data.Action == MPTSAS_FW_DIAG_TYPE_UNREGISTER ||
11002 driver_data.Action == MPTSAS_FW_DIAG_TYPE_QUERY ||
11003 driver_data.Action == MPTSAS_FW_DIAG_TYPE_READ_BUFFER ||
11004 driver_data.Action == MPTSAS_FW_DIAG_TYPE_RELEASE) {
11005 status = mptsas_do_diag_action(mpt, driver_data.Action,
11006 (void *)(uintptr_t)driver_data.PtrDiagAction,
11007 driver_data.Length, &driver_data.ReturnCode,
11008 mode);
11009 if (status == DDI_SUCCESS) {
11010 if (ddi_copyout(&driver_data.ReturnCode,
11011 &user_data->ReturnCode,
11012 sizeof (user_data->ReturnCode), mode)
11013 != 0) {
11014 status = EFAULT;
11015 } else {
11016 status = 0;
11017 }
11018 } else {
11019 status = EIO;
11020 }
11021 } else {
11022 status = EINVAL;
11023 }
11024 } else {
11025 status = EFAULT;
11026 }
11027
11028 return (status);
11029 }
11030
11031 /*
11032 * This routine handles the "event query" ioctl.
11033 */
11034 static int
11035 mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, int mode,
11036 int *rval)
11037 {
11038 int status;
11039 mptsas_event_query_t driverdata;
11040 uint8_t i;
11041
11042 driverdata.Entries = MPTSAS_EVENT_QUEUE_SIZE;
11043
11044 mutex_enter(&mpt->m_mutex);
11045 for (i = 0; i < 4; i++) {
11046 driverdata.Types[i] = mpt->m_event_mask[i];
11047 }
11048 mutex_exit(&mpt->m_mutex);
11049
11050 if (ddi_copyout(&driverdata, data, sizeof (driverdata), mode) != 0) {
11051 status = EFAULT;
11052 } else {
11053 *rval = MPTIOCTL_STATUS_GOOD;
11054 status = 0;
11055 }
11056
11057 return (status);
11058 }
11059
11060 /*
11061 * This routine handles the "event enable" ioctl.
11062 */
11063 static int
11064 mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, int mode,
11065 int *rval)
11066 {
11067 int status;
11068 mptsas_event_enable_t driverdata;
11069 uint8_t i;
11070
11071 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) {
11072 mutex_enter(&mpt->m_mutex);
11073 for (i = 0; i < 4; i++) {
11074 mpt->m_event_mask[i] = driverdata.Types[i];
11075 }
11076 mutex_exit(&mpt->m_mutex);
11077
11078 *rval = MPTIOCTL_STATUS_GOOD;
11079 status = 0;
11080 } else {
11081 status = EFAULT;
11082 }
11083 return (status);
11084 }
11085
11086 /*
11087 * This routine handles the "event report" ioctl.
11088 */
11089 static int
11090 mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, int mode,
11091 int *rval)
11092 {
11093 int status;
11094 mptsas_event_report_t driverdata;
11095
11096 mutex_enter(&mpt->m_mutex);
11097
11098 if (ddi_copyin(&data->Size, &driverdata.Size, sizeof (driverdata.Size),
11099 mode) == 0) {
11100 if (driverdata.Size >= sizeof (mpt->m_events)) {
11101 if (ddi_copyout(mpt->m_events, data->Events,
11102 sizeof (mpt->m_events), mode) != 0) {
11103 status = EFAULT;
11104 } else {
11105 if (driverdata.Size > sizeof (mpt->m_events)) {
11106 driverdata.Size =
11107 sizeof (mpt->m_events);
11108 if (ddi_copyout(&driverdata.Size,
11109 &data->Size,
11110 sizeof (driverdata.Size),
11111 mode) != 0) {
11112 status = EFAULT;
11113 } else {
11114 *rval = MPTIOCTL_STATUS_GOOD;
11115 status = 0;
11116 }
11117 } else {
11118 *rval = MPTIOCTL_STATUS_GOOD;
11119 status = 0;
11120 }
11121 }
11122 } else {
11123 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT;
11124 status = 0;
11125 }
11126 } else {
11127 status = EFAULT;
11128 }
11129
11130 mutex_exit(&mpt->m_mutex);
11131 return (status);
11132 }
11133
11134 static void
11135 mptsas_lookup_pci_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data)
11136 {
11137 int *reg_data;
11138 uint_t reglen;
11139
11140 /*
11141 * Lookup the 'reg' property and extract the other data
11142 */
11143 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip,
11144 DDI_PROP_DONTPASS, "reg", ®_data, ®len) ==
11145 DDI_PROP_SUCCESS) {
11146 /*
11147 * Extract the PCI data from the 'reg' property first DWORD.
11148 * The entry looks like the following:
11149 * First DWORD:
11150 * Bits 0 - 7 8-bit Register number
11151 * Bits 8 - 10 3-bit Function number
11152 * Bits 11 - 15 5-bit Device number
11153 * Bits 16 - 23 8-bit Bus number
11154 * Bits 24 - 25 2-bit Address Space type identifier
11155 *
11156 */
11157 adapter_data->PciInformation.u.bits.BusNumber =
11158 (reg_data[0] & 0x00FF0000) >> 16;
11159 adapter_data->PciInformation.u.bits.DeviceNumber =
11160 (reg_data[0] & 0x0000F800) >> 11;
11161 adapter_data->PciInformation.u.bits.FunctionNumber =
11162 (reg_data[0] & 0x00000700) >> 8;
11163 ddi_prop_free((void *)reg_data);
11164 } else {
11165 /*
11166 * If we can't determine the PCI data then we fill in FF's for
11167 * the data to indicate this.
11168 */
11169 adapter_data->PCIDeviceHwId = 0xFFFFFFFF;
11170 adapter_data->MpiPortNumber = 0xFFFFFFFF;
11171 adapter_data->PciInformation.u.AsDWORD = 0xFFFFFFFF;
11172 }
11173
11174 /*
11175 * Saved in the mpt->m_fwversion
11176 */
11177 adapter_data->MpiFirmwareVersion = mpt->m_fwversion;
11178 }
11179
11180 static void
11181 mptsas_read_adapter_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data)
11182 {
11183 char *driver_verstr = MPTSAS_MOD_STRING;
11184
11185 mptsas_lookup_pci_data(mpt, adapter_data);
11186 adapter_data->AdapterType = MPTIOCTL_ADAPTER_TYPE_SAS2;
11187 adapter_data->PCIDeviceHwId = (uint32_t)mpt->m_devid;
11188 adapter_data->PCIDeviceHwRev = (uint32_t)mpt->m_revid;
11189 adapter_data->SubSystemId = (uint32_t)mpt->m_ssid;
11190 adapter_data->SubsystemVendorId = (uint32_t)mpt->m_svid;
11191 (void) strcpy((char *)&adapter_data->DriverVersion[0], driver_verstr);
11192 adapter_data->BiosVersion = 0;
11193 (void) mptsas_get_bios_page3(mpt, &adapter_data->BiosVersion);
11194 }
11195
11196 static void
11197 mptsas_read_pci_info(mptsas_t *mpt, mptsas_pci_info_t *pci_info)
11198 {
11199 int *reg_data, i;
11200 uint_t reglen;
11201
11202 /*
11203 * Lookup the 'reg' property and extract the other data
11204 */
11205 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip,
11206 DDI_PROP_DONTPASS, "reg", ®_data, ®len) ==
11207 DDI_PROP_SUCCESS) {
11208 /*
11209 * Extract the PCI data from the 'reg' property first DWORD.
11210 * The entry looks like the following:
11211 * First DWORD:
11212 * Bits 8 - 10 3-bit Function number
11213 * Bits 11 - 15 5-bit Device number
11214 * Bits 16 - 23 8-bit Bus number
11215 */
11216 pci_info->BusNumber = (reg_data[0] & 0x00FF0000) >> 16;
11217 pci_info->DeviceNumber = (reg_data[0] & 0x0000F800) >> 11;
11218 pci_info->FunctionNumber = (reg_data[0] & 0x00000700) >> 8;
11219 ddi_prop_free((void *)reg_data);
11220 } else {
11221 /*
11222 * If we can't determine the PCI info then we fill in FF's for
11223 * the data to indicate this.
11224 */
11225 pci_info->BusNumber = 0xFFFFFFFF;
11226 pci_info->DeviceNumber = 0xFF;
11227 pci_info->FunctionNumber = 0xFF;
11228 }
11229
11230 /*
11231 * Now get the interrupt vector and the pci header. The vector can
11232 * only be 0 right now. The header is the first 256 bytes of config
11233 * space.
11234 */
11235 pci_info->InterruptVector = 0;
11236 for (i = 0; i < sizeof (pci_info->PciHeader); i++) {
11237 pci_info->PciHeader[i] = pci_config_get8(mpt->m_config_handle,
11238 i);
11239 }
11240 }
11241
11242 static int
11243 mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, int mode)
11244 {
11245 int status = 0;
11246 mptsas_reg_access_t driverdata;
11247
11248 mutex_enter(&mpt->m_mutex);
11249 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) {
11250 switch (driverdata.Command) {
11251 /*
11252 * IO access is not supported.
11253 */
11254 case REG_IO_READ:
11255 case REG_IO_WRITE:
11256 mptsas_log(mpt, CE_WARN, "IO access is not "
11257 "supported. Use memory access.");
11258 status = EINVAL;
11259 break;
11260
11261 case REG_MEM_READ:
11262 driverdata.RegData = ddi_get32(mpt->m_datap,
11263 (uint32_t *)(void *)mpt->m_reg +
11264 driverdata.RegOffset);
11265 if (ddi_copyout(&driverdata.RegData,
11266 &data->RegData,
11267 sizeof (driverdata.RegData), mode) != 0) {
11268 mptsas_log(mpt, CE_WARN, "Register "
11269 "Read Failed");
11270 status = EFAULT;
11271 }
11272 break;
11273
11274 case REG_MEM_WRITE:
11275 ddi_put32(mpt->m_datap,
11276 (uint32_t *)(void *)mpt->m_reg +
11277 driverdata.RegOffset,
11278 driverdata.RegData);
11279 break;
11280
11281 default:
11282 status = EINVAL;
11283 break;
11284 }
11285 } else {
11286 status = EFAULT;
11287 }
11288
11289 mutex_exit(&mpt->m_mutex);
11290 return (status);
11291 }
11292
11293 static int
11294 led_control(mptsas_t *mpt, intptr_t data, int mode)
11295 {
11296 int ret = 0;
11297 mptsas_led_control_t lc;
11298 mptsas_target_t *ptgt;
11299
11300 if (ddi_copyin((void *)data, &lc, sizeof (lc), mode) != 0) {
11301 return (EFAULT);
11302 }
11303
11304 if ((lc.Command != MPTSAS_LEDCTL_FLAG_SET &&
11305 lc.Command != MPTSAS_LEDCTL_FLAG_GET) ||
11306 lc.Led < MPTSAS_LEDCTL_LED_MIN ||
11307 lc.Led > MPTSAS_LEDCTL_LED_MAX ||
11308 (lc.Command == MPTSAS_LEDCTL_FLAG_SET && lc.LedStatus != 0 &&
11309 lc.LedStatus != 1)) {
11310 return (EINVAL);
11311 }
11312
11313 if ((lc.Command == MPTSAS_LEDCTL_FLAG_SET && (mode & FWRITE) == 0) ||
11314 (lc.Command == MPTSAS_LEDCTL_FLAG_GET && (mode & FREAD) == 0))
11315 return (EACCES);
11316
11317 /* Locate the target we're interrogating... */
11318 mutex_enter(&mpt->m_mutex);
11319 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
11320 MPTSAS_HASH_FIRST);
11321 while (ptgt != NULL) {
11322 if (ptgt->m_enclosure == lc.Enclosure &&
11323 ptgt->m_slot_num == lc.Slot) {
11324 break;
11325 }
11326 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
11327 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
11328 }
11329 if (ptgt == NULL) {
11330 /* We could not find a target for that enclosure/slot. */
11331 mutex_exit(&mpt->m_mutex);
11332 return (ENOENT);
11333 }
11334
11335 if (lc.Command == MPTSAS_LEDCTL_FLAG_SET) {
11336 /* Update our internal LED state. */
11337 ptgt->m_led_status &= ~(1 << (lc.Led - 1));
11338 ptgt->m_led_status |= lc.LedStatus << (lc.Led - 1);
11339
11340 /* Flush it to the controller. */
11341 ret = mptsas_flush_led_status(mpt, ptgt);
11342 mutex_exit(&mpt->m_mutex);
11343 return (ret);
11344 }
11345
11346 /* Return our internal LED state. */
11347 lc.LedStatus = (ptgt->m_led_status >> (lc.Led - 1)) & 1;
11348 mutex_exit(&mpt->m_mutex);
11349
11350 if (ddi_copyout(&lc, (void *)data, sizeof (lc), mode) != 0) {
11351 return (EFAULT);
11352 }
11353
11354 return (0);
11355 }
11356
11357 static int
11358 get_disk_info(mptsas_t *mpt, intptr_t data, int mode)
11359 {
11360 uint16_t i = 0;
11361 uint16_t count = 0;
11362 int ret = 0;
11363 mptsas_target_t *ptgt;
11364 mptsas_disk_info_t *di;
11365 STRUCT_DECL(mptsas_get_disk_info, gdi);
11366
11367 if ((mode & FREAD) == 0)
11368 return (EACCES);
11369
11370 STRUCT_INIT(gdi, get_udatamodel());
11371
11372 if (ddi_copyin((void *)data, STRUCT_BUF(gdi), STRUCT_SIZE(gdi),
11373 mode) != 0) {
11374 return (EFAULT);
11375 }
11376
11377 /* Find out how many targets there are. */
11378 mutex_enter(&mpt->m_mutex);
11379 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
11380 MPTSAS_HASH_FIRST);
11381 while (ptgt != NULL) {
11382 count++;
11383 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
11384 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
11385 }
11386 mutex_exit(&mpt->m_mutex);
11387
11388 /*
11389 * If we haven't been asked to copy out information on each target,
11390 * then just return the count.
11391 */
11392 STRUCT_FSET(gdi, DiskCount, count);
11393 if (STRUCT_FGETP(gdi, PtrDiskInfoArray) == NULL)
11394 goto copy_out;
11395
11396 /*
11397 * If we haven't been given a large enough buffer to copy out into,
11398 * let the caller know.
11399 */
11400 if (STRUCT_FGET(gdi, DiskInfoArraySize) <
11401 count * sizeof (mptsas_disk_info_t)) {
11402 ret = ENOSPC;
11403 goto copy_out;
11404 }
11405
11406 di = kmem_zalloc(count * sizeof (mptsas_disk_info_t), KM_SLEEP);
11407
11408 mutex_enter(&mpt->m_mutex);
11409 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
11410 MPTSAS_HASH_FIRST);
11411 while (ptgt != NULL) {
11412 if (i >= count) {
11413 /*
11414 * The number of targets changed while we weren't
11415 * looking, so give up.
11416 */
11417 mutex_exit(&mpt->m_mutex);
11418 kmem_free(di, count * sizeof (mptsas_disk_info_t));
11419 return (EAGAIN);
11420 }
11421 di[i].Instance = mpt->m_instance;
11422 di[i].Enclosure = ptgt->m_enclosure;
11423 di[i].Slot = ptgt->m_slot_num;
11424 di[i].SasAddress = ptgt->m_sas_wwn;
11425
11426 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
11427 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
11428 i++;
11429 }
11430 mutex_exit(&mpt->m_mutex);
11431 STRUCT_FSET(gdi, DiskCount, i);
11432
11433 /* Copy out the disk information to the caller. */
11434 if (ddi_copyout((void *)di, STRUCT_FGETP(gdi, PtrDiskInfoArray),
11435 i * sizeof (mptsas_disk_info_t), mode) != 0) {
11436 ret = EFAULT;
11437 }
11438
11439 kmem_free(di, count * sizeof (mptsas_disk_info_t));
11440
11441 copy_out:
11442 if (ddi_copyout(STRUCT_BUF(gdi), (void *)data, STRUCT_SIZE(gdi),
11443 mode) != 0) {
11444 ret = EFAULT;
11445 }
11446
11447 return (ret);
11448 }
11449
11450 static int
11451 mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, cred_t *credp,
11452 int *rval)
11453 {
11454 int status = 0;
11455 mptsas_t *mpt;
11456 mptsas_update_flash_t flashdata;
11457 mptsas_pass_thru_t passthru_data;
11458 mptsas_adapter_data_t adapter_data;
11459 mptsas_pci_info_t pci_info;
11460 int copylen;
11461
11462 int iport_flag = 0;
11463 dev_info_t *dip = NULL;
11464 mptsas_phymask_t phymask = 0;
11465 struct devctl_iocdata *dcp = NULL;
11466 char *addr = NULL;
11467 mptsas_target_t *ptgt = NULL;
11468
11469 *rval = MPTIOCTL_STATUS_GOOD;
11470 if (secpolicy_sys_config(credp, B_FALSE) != 0) {
11471 return (EPERM);
11472 }
11473
11474 mpt = ddi_get_soft_state(mptsas_state, MINOR2INST(getminor(dev)));
11475 if (mpt == NULL) {
11476 /*
11477 * Called from iport node, get the states
11478 */
11479 iport_flag = 1;
11480 dip = mptsas_get_dip_from_dev(dev, &phymask);
11481 if (dip == NULL) {
11482 return (ENXIO);
11483 }
11484 mpt = DIP2MPT(dip);
11485 }
11486 /* Make sure power level is D0 before accessing registers */
11487 mutex_enter(&mpt->m_mutex);
11488 if (mpt->m_options & MPTSAS_OPT_PM) {
11489 (void) pm_busy_component(mpt->m_dip, 0);
11490 if (mpt->m_power_level != PM_LEVEL_D0) {
11491 mutex_exit(&mpt->m_mutex);
11492 if (pm_raise_power(mpt->m_dip, 0, PM_LEVEL_D0) !=
11493 DDI_SUCCESS) {
11494 mptsas_log(mpt, CE_WARN,
11495 "mptsas%d: mptsas_ioctl: Raise power "
11496 "request failed.", mpt->m_instance);
11497 (void) pm_idle_component(mpt->m_dip, 0);
11498 return (ENXIO);
11499 }
11500 } else {
11501 mutex_exit(&mpt->m_mutex);
11502 }
11503 } else {
11504 mutex_exit(&mpt->m_mutex);
11505 }
11506
11507 if (iport_flag) {
11508 status = scsi_hba_ioctl(dev, cmd, data, mode, credp, rval);
11509 if (status != 0) {
11510 goto out;
11511 }
11512 /*
11513 * The following code control the OK2RM LED, it doesn't affect
11514 * the ioctl return status.
11515 */
11516 if ((cmd == DEVCTL_DEVICE_ONLINE) ||
11517 (cmd == DEVCTL_DEVICE_OFFLINE)) {
11518 if (ndi_dc_allochdl((void *)data, &dcp) !=
11519 NDI_SUCCESS) {
11520 goto out;
11521 }
11522 addr = ndi_dc_getaddr(dcp);
11523 ptgt = mptsas_addr_to_ptgt(mpt, addr, phymask);
11524 if (ptgt == NULL) {
11525 NDBG14(("mptsas_ioctl led control: tgt %s not "
11526 "found", addr));
11527 ndi_dc_freehdl(dcp);
11528 goto out;
11529 }
11530 mutex_enter(&mpt->m_mutex);
11531 if (cmd == DEVCTL_DEVICE_ONLINE) {
11532 ptgt->m_tgt_unconfigured = 0;
11533 } else if (cmd == DEVCTL_DEVICE_OFFLINE) {
11534 ptgt->m_tgt_unconfigured = 1;
11535 }
11536 if (cmd == DEVCTL_DEVICE_OFFLINE) {
11537 ptgt->m_led_status |=
11538 (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1));
11539 } else {
11540 ptgt->m_led_status &=
11541 ~(1 << (MPTSAS_LEDCTL_LED_OK2RM - 1));
11542 }
11543 (void) mptsas_flush_led_status(mpt, ptgt);
11544 mutex_exit(&mpt->m_mutex);
11545 ndi_dc_freehdl(dcp);
11546 }
11547 goto out;
11548 }
11549 switch (cmd) {
11550 case MPTIOCTL_GET_DISK_INFO:
11551 status = get_disk_info(mpt, data, mode);
11552 break;
11553 case MPTIOCTL_LED_CONTROL:
11554 status = led_control(mpt, data, mode);
11555 break;
11556 case MPTIOCTL_UPDATE_FLASH:
11557 if (ddi_copyin((void *)data, &flashdata,
11558 sizeof (struct mptsas_update_flash), mode)) {
11559 status = EFAULT;
11560 break;
11561 }
11562
11563 mutex_enter(&mpt->m_mutex);
11564 if (mptsas_update_flash(mpt,
11565 (caddr_t)(long)flashdata.PtrBuffer,
11566 flashdata.ImageSize, flashdata.ImageType, mode)) {
11567 status = EFAULT;
11568 }
11569
11570 /*
11571 * Reset the chip to start using the new
11572 * firmware. Reset if failed also.
11573 */
11574 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
11575 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) {
11576 status = EFAULT;
11577 }
11578 mutex_exit(&mpt->m_mutex);
11579 break;
11580 case MPTIOCTL_PASS_THRU:
11581 /*
11582 * The user has requested to pass through a command to
11583 * be executed by the MPT firmware. Call our routine
11584 * which does this. Only allow one passthru IOCTL at
11585 * one time. Other threads will block on
11586 * m_passthru_mutex, which is of adaptive variant.
11587 */
11588 if (ddi_copyin((void *)data, &passthru_data,
11589 sizeof (mptsas_pass_thru_t), mode)) {
11590 status = EFAULT;
11591 break;
11592 }
11593 mutex_enter(&mpt->m_passthru_mutex);
11594 mutex_enter(&mpt->m_mutex);
11595 status = mptsas_pass_thru(mpt, &passthru_data, mode);
11596 mutex_exit(&mpt->m_mutex);
11597 mutex_exit(&mpt->m_passthru_mutex);
11598
11599 break;
11600 case MPTIOCTL_GET_ADAPTER_DATA:
11601 /*
11602 * The user has requested to read adapter data. Call
11603 * our routine which does this.
11604 */
11605 bzero(&adapter_data, sizeof (mptsas_adapter_data_t));
11606 if (ddi_copyin((void *)data, (void *)&adapter_data,
11607 sizeof (mptsas_adapter_data_t), mode)) {
11608 status = EFAULT;
11609 break;
11610 }
11611 if (adapter_data.StructureLength >=
11612 sizeof (mptsas_adapter_data_t)) {
11613 adapter_data.StructureLength = (uint32_t)
11614 sizeof (mptsas_adapter_data_t);
11615 copylen = sizeof (mptsas_adapter_data_t);
11616 mutex_enter(&mpt->m_mutex);
11617 mptsas_read_adapter_data(mpt, &adapter_data);
11618 mutex_exit(&mpt->m_mutex);
11619 } else {
11620 adapter_data.StructureLength = (uint32_t)
11621 sizeof (mptsas_adapter_data_t);
11622 copylen = sizeof (adapter_data.StructureLength);
11623 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT;
11624 }
11625 if (ddi_copyout((void *)(&adapter_data), (void *)data,
11626 copylen, mode) != 0) {
11627 status = EFAULT;
11628 }
11629 break;
11630 case MPTIOCTL_GET_PCI_INFO:
11631 /*
11632 * The user has requested to read pci info. Call
11633 * our routine which does this.
11634 */
11635 bzero(&pci_info, sizeof (mptsas_pci_info_t));
11636 mutex_enter(&mpt->m_mutex);
11637 mptsas_read_pci_info(mpt, &pci_info);
11638 mutex_exit(&mpt->m_mutex);
11639 if (ddi_copyout((void *)(&pci_info), (void *)data,
11640 sizeof (mptsas_pci_info_t), mode) != 0) {
11641 status = EFAULT;
11642 }
11643 break;
11644 case MPTIOCTL_RESET_ADAPTER:
11645 mutex_enter(&mpt->m_mutex);
11646 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
11647 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
11648 mptsas_log(mpt, CE_WARN, "reset adapter IOCTL "
11649 "failed");
11650 status = EFAULT;
11651 }
11652 mutex_exit(&mpt->m_mutex);
11653 break;
11654 case MPTIOCTL_DIAG_ACTION:
11655 /*
11656 * The user has done a diag buffer action. Call our
11657 * routine which does this. Only allow one diag action
11658 * at one time.
11659 */
11660 mutex_enter(&mpt->m_mutex);
11661 if (mpt->m_diag_action_in_progress) {
11662 mutex_exit(&mpt->m_mutex);
11663 return (EBUSY);
11664 }
11665 mpt->m_diag_action_in_progress = 1;
11666 status = mptsas_diag_action(mpt,
11667 (mptsas_diag_action_t *)data, mode);
11668 mpt->m_diag_action_in_progress = 0;
11669 mutex_exit(&mpt->m_mutex);
11670 break;
11671 case MPTIOCTL_EVENT_QUERY:
11672 /*
11673 * The user has done an event query. Call our routine
11674 * which does this.
11675 */
11676 status = mptsas_event_query(mpt,
11677 (mptsas_event_query_t *)data, mode, rval);
11678 break;
11679 case MPTIOCTL_EVENT_ENABLE:
11680 /*
11681 * The user has done an event enable. Call our routine
11682 * which does this.
11683 */
11684 status = mptsas_event_enable(mpt,
11685 (mptsas_event_enable_t *)data, mode, rval);
11686 break;
11687 case MPTIOCTL_EVENT_REPORT:
11688 /*
11689 * The user has done an event report. Call our routine
11690 * which does this.
11691 */
11692 status = mptsas_event_report(mpt,
11693 (mptsas_event_report_t *)data, mode, rval);
11694 break;
11695 case MPTIOCTL_REG_ACCESS:
11696 /*
11697 * The user has requested register access. Call our
11698 * routine which does this.
11699 */
11700 status = mptsas_reg_access(mpt,
11701 (mptsas_reg_access_t *)data, mode);
11702 break;
11703 default:
11704 status = scsi_hba_ioctl(dev, cmd, data, mode, credp,
11705 rval);
11706 break;
11707 }
11708
11709 out:
11710 return (status);
11711 }
11712
11713 int
11714 mptsas_restart_ioc(mptsas_t *mpt)
11715 {
11716 int rval = DDI_SUCCESS;
11717 mptsas_target_t *ptgt = NULL;
11718
11719 ASSERT(mutex_owned(&mpt->m_mutex));
11720
11721 /*
11722 * Set a flag telling I/O path that we're processing a reset. This is
11723 * needed because after the reset is complete, the hash table still
11724 * needs to be rebuilt. If I/Os are started before the hash table is
11725 * rebuilt, I/O errors will occur. This flag allows I/Os to be marked
11726 * so that they can be retried.
11727 */
11728 mpt->m_in_reset = TRUE;
11729
11730 /*
11731 * Set all throttles to HOLD
11732 */
11733 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
11734 MPTSAS_HASH_FIRST);
11735 while (ptgt != NULL) {
11736 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
11737
11738 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
11739 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
11740 }
11741
11742 /*
11743 * Disable interrupts
11744 */
11745 MPTSAS_DISABLE_INTR(mpt);
11746
11747 /*
11748 * Abort all commands: outstanding commands, commands in waitq and
11749 * tx_waitq.
11750 */
11751 mptsas_flush_hba(mpt);
11752
11753 /*
11754 * Reinitialize the chip.
11755 */
11756 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) {
11757 rval = DDI_FAILURE;
11758 }
11759
11760 /*
11761 * Enable interrupts again
11762 */
11763 MPTSAS_ENABLE_INTR(mpt);
11764
11765 /*
11766 * If mptsas_init_chip was successful, update the driver data.
11767 */
11768 if (rval == DDI_SUCCESS) {
11769 mptsas_update_driver_data(mpt);
11770 }
11771
11772 /*
11773 * Reset the throttles
11774 */
11775 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
11776 MPTSAS_HASH_FIRST);
11777 while (ptgt != NULL) {
11778 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
11779
11780 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
11781 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
11782 }
11783
11784 mptsas_doneq_empty(mpt);
11785 mptsas_restart_hba(mpt);
11786
11787 if (rval != DDI_SUCCESS) {
11788 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE);
11789 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST);
11790 }
11791
11792 /*
11793 * Clear the reset flag so that I/Os can continue.
11794 */
11795 mpt->m_in_reset = FALSE;
11796
11797 return (rval);
11798 }
11799
11800 static int
11801 mptsas_init_chip(mptsas_t *mpt, int first_time)
11802 {
11803 ddi_dma_cookie_t cookie;
11804 uint32_t i;
11805 int rval;
11806
11807 /*
11808 * Check to see if the firmware image is valid
11809 */
11810 if (ddi_get32(mpt->m_datap, &mpt->m_reg->HostDiagnostic) &
11811 MPI2_DIAG_FLASH_BAD_SIG) {
11812 mptsas_log(mpt, CE_WARN, "mptsas bad flash signature!");
11813 goto fail;
11814 }
11815
11816 /*
11817 * Reset the chip
11818 */
11819 rval = mptsas_ioc_reset(mpt, first_time);
11820 if (rval == MPTSAS_RESET_FAIL) {
11821 mptsas_log(mpt, CE_WARN, "hard reset failed!");
11822 goto fail;
11823 }
11824
11825 if ((rval == MPTSAS_SUCCESS_MUR) && (!first_time)) {
11826 goto mur;
11827 }
11828 /*
11829 * Setup configuration space
11830 */
11831 if (mptsas_config_space_init(mpt) == FALSE) {
11832 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init "
11833 "failed!");
11834 goto fail;
11835 }
11836
11837 /*
11838 * IOC facts can change after a diag reset so all buffers that are
11839 * based on these numbers must be de-allocated and re-allocated. Get
11840 * new IOC facts each time chip is initialized.
11841 */
11842 if (mptsas_ioc_get_facts(mpt) == DDI_FAILURE) {
11843 mptsas_log(mpt, CE_WARN, "mptsas_ioc_get_facts failed");
11844 goto fail;
11845 }
11846
11847 if (mptsas_alloc_active_slots(mpt, KM_SLEEP)) {
11848 goto fail;
11849 }
11850 /*
11851 * Allocate request message frames, reply free queue, reply descriptor
11852 * post queue, and reply message frames using latest IOC facts.
11853 */
11854 if (mptsas_alloc_request_frames(mpt) == DDI_FAILURE) {
11855 mptsas_log(mpt, CE_WARN, "mptsas_alloc_request_frames failed");
11856 goto fail;
11857 }
11858 if (mptsas_alloc_free_queue(mpt) == DDI_FAILURE) {
11859 mptsas_log(mpt, CE_WARN, "mptsas_alloc_free_queue failed!");
11860 goto fail;
11861 }
11862 if (mptsas_alloc_post_queue(mpt) == DDI_FAILURE) {
11863 mptsas_log(mpt, CE_WARN, "mptsas_alloc_post_queue failed!");
11864 goto fail;
11865 }
11866 if (mptsas_alloc_reply_frames(mpt) == DDI_FAILURE) {
11867 mptsas_log(mpt, CE_WARN, "mptsas_alloc_reply_frames failed!");
11868 goto fail;
11869 }
11870
11871 mur:
11872 /*
11873 * Re-Initialize ioc to operational state
11874 */
11875 if (mptsas_ioc_init(mpt) == DDI_FAILURE) {
11876 mptsas_log(mpt, CE_WARN, "mptsas_ioc_init failed");
11877 goto fail;
11878 }
11879
11880 mptsas_alloc_reply_args(mpt);
11881
11882 /*
11883 * Initialize reply post index. Reply free index is initialized after
11884 * the next loop.
11885 */
11886 mpt->m_post_index = 0;
11887
11888 /*
11889 * Initialize the Reply Free Queue with the physical addresses of our
11890 * reply frames.
11891 */
11892 cookie.dmac_address = mpt->m_reply_frame_dma_addr;
11893 for (i = 0; i < mpt->m_max_replies; i++) {
11894 ddi_put32(mpt->m_acc_free_queue_hdl,
11895 &((uint32_t *)(void *)mpt->m_free_queue)[i],
11896 cookie.dmac_address);
11897 cookie.dmac_address += mpt->m_reply_frame_size;
11898 }
11899 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
11900 DDI_DMA_SYNC_FORDEV);
11901
11902 /*
11903 * Initialize the reply free index to one past the last frame on the
11904 * queue. This will signify that the queue is empty to start with.
11905 */
11906 mpt->m_free_index = i;
11907 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, i);
11908
11909 /*
11910 * Initialize the reply post queue to 0xFFFFFFFF,0xFFFFFFFF's.
11911 */
11912 for (i = 0; i < mpt->m_post_queue_depth; i++) {
11913 ddi_put64(mpt->m_acc_post_queue_hdl,
11914 &((uint64_t *)(void *)mpt->m_post_queue)[i],
11915 0xFFFFFFFFFFFFFFFF);
11916 }
11917 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
11918 DDI_DMA_SYNC_FORDEV);
11919
11920 /*
11921 * Enable ports
11922 */
11923 if (mptsas_ioc_enable_port(mpt) == DDI_FAILURE) {
11924 mptsas_log(mpt, CE_WARN, "mptsas_ioc_enable_port failed");
11925 goto fail;
11926 }
11927
11928 /*
11929 * enable events
11930 */
11931 if (mptsas_ioc_enable_event_notification(mpt)) {
11932 goto fail;
11933 }
11934
11935 /*
11936 * We need checks in attach and these.
11937 * chip_init is called in mult. places
11938 */
11939
11940 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
11941 DDI_SUCCESS) ||
11942 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) !=
11943 DDI_SUCCESS) ||
11944 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) !=
11945 DDI_SUCCESS) ||
11946 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) !=
11947 DDI_SUCCESS) ||
11948 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) !=
11949 DDI_SUCCESS)) {
11950 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
11951 goto fail;
11952 }
11953
11954 /* Check all acc handles */
11955 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) ||
11956 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
11957 DDI_SUCCESS) ||
11958 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) !=
11959 DDI_SUCCESS) ||
11960 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) !=
11961 DDI_SUCCESS) ||
11962 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) !=
11963 DDI_SUCCESS) ||
11964 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) !=
11965 DDI_SUCCESS) ||
11966 (mptsas_check_acc_handle(mpt->m_config_handle) !=
11967 DDI_SUCCESS)) {
11968 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
11969 goto fail;
11970 }
11971
11972 return (DDI_SUCCESS);
11973
11974 fail:
11975 return (DDI_FAILURE);
11976 }
11977
11978 static int
11979 mptsas_get_pci_cap(mptsas_t *mpt)
11980 {
11981 ushort_t caps_ptr, cap, cap_count;
11982
11983 if (mpt->m_config_handle == NULL)
11984 return (FALSE);
11985 /*
11986 * Check if capabilities list is supported and if so,
11987 * get initial capabilities pointer and clear bits 0,1.
11988 */
11989 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT)
11990 & PCI_STAT_CAP) {
11991 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle,
11992 PCI_CONF_CAP_PTR), 4);
11993 } else {
11994 caps_ptr = PCI_CAP_NEXT_PTR_NULL;
11995 }
11996
11997 /*
11998 * Walk capabilities if supported.
11999 */
12000 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) {
12001
12002 /*
12003 * Check that we haven't exceeded the maximum number of
12004 * capabilities and that the pointer is in a valid range.
12005 */
12006 if (++cap_count > 48) {
12007 mptsas_log(mpt, CE_WARN,
12008 "too many device capabilities.\n");
12009 break;
12010 }
12011 if (caps_ptr < 64) {
12012 mptsas_log(mpt, CE_WARN,
12013 "capabilities pointer 0x%x out of range.\n",
12014 caps_ptr);
12015 break;
12016 }
12017
12018 /*
12019 * Get next capability and check that it is valid.
12020 * For now, we only support power management.
12021 */
12022 cap = pci_config_get8(mpt->m_config_handle, caps_ptr);
12023 switch (cap) {
12024 case PCI_CAP_ID_PM:
12025 mptsas_log(mpt, CE_NOTE,
12026 "?mptsas%d supports power management.\n",
12027 mpt->m_instance);
12028 mpt->m_options |= MPTSAS_OPT_PM;
12029
12030 /* Save PMCSR offset */
12031 mpt->m_pmcsr_offset = caps_ptr + PCI_PMCSR;
12032 break;
12033 /*
12034 * The following capabilities are valid. Any others
12035 * will cause a message to be logged.
12036 */
12037 case PCI_CAP_ID_VPD:
12038 case PCI_CAP_ID_MSI:
12039 case PCI_CAP_ID_PCIX:
12040 case PCI_CAP_ID_PCI_E:
12041 case PCI_CAP_ID_MSI_X:
12042 break;
12043 default:
12044 mptsas_log(mpt, CE_NOTE,
12045 "?mptsas%d unrecognized capability "
12046 "0x%x.\n", mpt->m_instance, cap);
12047 break;
12048 }
12049
12050 /*
12051 * Get next capabilities pointer and clear bits 0,1.
12052 */
12053 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle,
12054 (caps_ptr + PCI_CAP_NEXT_PTR)), 4);
12055 }
12056 return (TRUE);
12057 }
12058
12059 static int
12060 mptsas_init_pm(mptsas_t *mpt)
12061 {
12062 char pmc_name[16];
12063 char *pmc[] = {
12064 NULL,
12065 "0=Off (PCI D3 State)",
12066 "3=On (PCI D0 State)",
12067 NULL
12068 };
12069 uint16_t pmcsr_stat;
12070
12071 if (mptsas_get_pci_cap(mpt) == FALSE) {
12072 return (DDI_FAILURE);
12073 }
12074 /*
12075 * If PCI's capability does not support PM, then don't need
12076 * to registe the pm-components
12077 */
12078 if (!(mpt->m_options & MPTSAS_OPT_PM))
12079 return (DDI_SUCCESS);
12080 /*
12081 * If power management is supported by this chip, create
12082 * pm-components property for the power management framework
12083 */
12084 (void) sprintf(pmc_name, "NAME=mptsas%d", mpt->m_instance);
12085 pmc[0] = pmc_name;
12086 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, mpt->m_dip,
12087 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) {
12088 mpt->m_options &= ~MPTSAS_OPT_PM;
12089 mptsas_log(mpt, CE_WARN,
12090 "mptsas%d: pm-component property creation failed.",
12091 mpt->m_instance);
12092 return (DDI_FAILURE);
12093 }
12094
12095 /*
12096 * Power on device.
12097 */
12098 (void) pm_busy_component(mpt->m_dip, 0);
12099 pmcsr_stat = pci_config_get16(mpt->m_config_handle,
12100 mpt->m_pmcsr_offset);
12101 if ((pmcsr_stat & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_D0) {
12102 mptsas_log(mpt, CE_WARN, "mptsas%d: Power up the device",
12103 mpt->m_instance);
12104 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset,
12105 PCI_PMCSR_D0);
12106 }
12107 if (pm_power_has_changed(mpt->m_dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) {
12108 mptsas_log(mpt, CE_WARN, "pm_power_has_changed failed");
12109 return (DDI_FAILURE);
12110 }
12111 mpt->m_power_level = PM_LEVEL_D0;
12112 /*
12113 * Set pm idle delay.
12114 */
12115 mpt->m_pm_idle_delay = ddi_prop_get_int(DDI_DEV_T_ANY,
12116 mpt->m_dip, 0, "mptsas-pm-idle-delay", MPTSAS_PM_IDLE_TIMEOUT);
12117
12118 return (DDI_SUCCESS);
12119 }
12120
12121 static int
12122 mptsas_register_intrs(mptsas_t *mpt)
12123 {
12124 dev_info_t *dip;
12125 int intr_types;
12126
12127 dip = mpt->m_dip;
12128
12129 /* Get supported interrupt types */
12130 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) {
12131 mptsas_log(mpt, CE_WARN, "ddi_intr_get_supported_types "
12132 "failed\n");
12133 return (FALSE);
12134 }
12135
12136 NDBG6(("ddi_intr_get_supported_types() returned: 0x%x", intr_types));
12137
12138 /*
12139 * Try MSI, but fall back to FIXED
12140 */
12141 if (mptsas_enable_msi && (intr_types & DDI_INTR_TYPE_MSI)) {
12142 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_MSI) == DDI_SUCCESS) {
12143 NDBG0(("Using MSI interrupt type"));
12144 mpt->m_intr_type = DDI_INTR_TYPE_MSI;
12145 return (TRUE);
12146 }
12147 }
12148 if (intr_types & DDI_INTR_TYPE_FIXED) {
12149 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_FIXED) == DDI_SUCCESS) {
12150 NDBG0(("Using FIXED interrupt type"));
12151 mpt->m_intr_type = DDI_INTR_TYPE_FIXED;
12152 return (TRUE);
12153 } else {
12154 NDBG0(("FIXED interrupt registration failed"));
12155 return (FALSE);
12156 }
12157 }
12158
12159 return (FALSE);
12160 }
12161
12162 static void
12163 mptsas_unregister_intrs(mptsas_t *mpt)
12164 {
12165 mptsas_rem_intrs(mpt);
12166 }
12167
12168 /*
12169 * mptsas_add_intrs:
12170 *
12171 * Register FIXED or MSI interrupts.
12172 */
12173 static int
12174 mptsas_add_intrs(mptsas_t *mpt, int intr_type)
12175 {
12176 dev_info_t *dip = mpt->m_dip;
12177 int avail, actual, count = 0;
12178 int i, flag, ret;
12179
12180 NDBG6(("mptsas_add_intrs:interrupt type 0x%x", intr_type));
12181
12182 /* Get number of interrupts */
12183 ret = ddi_intr_get_nintrs(dip, intr_type, &count);
12184 if ((ret != DDI_SUCCESS) || (count <= 0)) {
12185 mptsas_log(mpt, CE_WARN, "ddi_intr_get_nintrs() failed, "
12186 "ret %d count %d\n", ret, count);
12187
12188 return (DDI_FAILURE);
12189 }
12190
12191 /* Get number of available interrupts */
12192 ret = ddi_intr_get_navail(dip, intr_type, &avail);
12193 if ((ret != DDI_SUCCESS) || (avail == 0)) {
12194 mptsas_log(mpt, CE_WARN, "ddi_intr_get_navail() failed, "
12195 "ret %d avail %d\n", ret, avail);
12196
12197 return (DDI_FAILURE);
12198 }
12199
12200 if (avail < count) {
12201 mptsas_log(mpt, CE_NOTE, "ddi_intr_get_nvail returned %d, "
12202 "navail() returned %d", count, avail);
12203 }
12204
12205 /* Mpt only have one interrupt routine */
12206 if ((intr_type == DDI_INTR_TYPE_MSI) && (count > 1)) {
12207 count = 1;
12208 }
12209
12210 /* Allocate an array of interrupt handles */
12211 mpt->m_intr_size = count * sizeof (ddi_intr_handle_t);
12212 mpt->m_htable = kmem_alloc(mpt->m_intr_size, KM_SLEEP);
12213
12214 flag = DDI_INTR_ALLOC_NORMAL;
12215
12216 /* call ddi_intr_alloc() */
12217 ret = ddi_intr_alloc(dip, mpt->m_htable, intr_type, 0,
12218 count, &actual, flag);
12219
12220 if ((ret != DDI_SUCCESS) || (actual == 0)) {
12221 mptsas_log(mpt, CE_WARN, "ddi_intr_alloc() failed, ret %d\n",
12222 ret);
12223 kmem_free(mpt->m_htable, mpt->m_intr_size);
12224 return (DDI_FAILURE);
12225 }
12226
12227 /* use interrupt count returned or abort? */
12228 if (actual < count) {
12229 mptsas_log(mpt, CE_NOTE, "Requested: %d, Received: %d\n",
12230 count, actual);
12231 }
12232
12233 mpt->m_intr_cnt = actual;
12234
12235 /*
12236 * Get priority for first msi, assume remaining are all the same
12237 */
12238 if ((ret = ddi_intr_get_pri(mpt->m_htable[0],
12239 &mpt->m_intr_pri)) != DDI_SUCCESS) {
12240 mptsas_log(mpt, CE_WARN, "ddi_intr_get_pri() failed %d\n", ret);
12241
12242 /* Free already allocated intr */
12243 for (i = 0; i < actual; i++) {
12244 (void) ddi_intr_free(mpt->m_htable[i]);
12245 }
12246
12247 kmem_free(mpt->m_htable, mpt->m_intr_size);
12248 return (DDI_FAILURE);
12249 }
12250
12251 /* Test for high level mutex */
12252 if (mpt->m_intr_pri >= ddi_intr_get_hilevel_pri()) {
12253 mptsas_log(mpt, CE_WARN, "mptsas_add_intrs: "
12254 "Hi level interrupt not supported\n");
12255
12256 /* Free already allocated intr */
12257 for (i = 0; i < actual; i++) {
12258 (void) ddi_intr_free(mpt->m_htable[i]);
12259 }
12260
12261 kmem_free(mpt->m_htable, mpt->m_intr_size);
12262 return (DDI_FAILURE);
12263 }
12264
12265 /* Call ddi_intr_add_handler() */
12266 for (i = 0; i < actual; i++) {
12267 if ((ret = ddi_intr_add_handler(mpt->m_htable[i], mptsas_intr,
12268 (caddr_t)mpt, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) {
12269 mptsas_log(mpt, CE_WARN, "ddi_intr_add_handler() "
12270 "failed %d\n", ret);
12271
12272 /* Free already allocated intr */
12273 for (i = 0; i < actual; i++) {
12274 (void) ddi_intr_free(mpt->m_htable[i]);
12275 }
12276
12277 kmem_free(mpt->m_htable, mpt->m_intr_size);
12278 return (DDI_FAILURE);
12279 }
12280 }
12281
12282 if ((ret = ddi_intr_get_cap(mpt->m_htable[0], &mpt->m_intr_cap))
12283 != DDI_SUCCESS) {
12284 mptsas_log(mpt, CE_WARN, "ddi_intr_get_cap() failed %d\n", ret);
12285
12286 /* Free already allocated intr */
12287 for (i = 0; i < actual; i++) {
12288 (void) ddi_intr_free(mpt->m_htable[i]);
12289 }
12290
12291 kmem_free(mpt->m_htable, mpt->m_intr_size);
12292 return (DDI_FAILURE);
12293 }
12294
12295 /*
12296 * Enable interrupts
12297 */
12298 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) {
12299 /* Call ddi_intr_block_enable() for MSI interrupts */
12300 (void) ddi_intr_block_enable(mpt->m_htable, mpt->m_intr_cnt);
12301 } else {
12302 /* Call ddi_intr_enable for MSI or FIXED interrupts */
12303 for (i = 0; i < mpt->m_intr_cnt; i++) {
12304 (void) ddi_intr_enable(mpt->m_htable[i]);
12305 }
12306 }
12307 return (DDI_SUCCESS);
12308 }
12309
12310 /*
12311 * mptsas_rem_intrs:
12312 *
12313 * Unregister FIXED or MSI interrupts
12314 */
12315 static void
12316 mptsas_rem_intrs(mptsas_t *mpt)
12317 {
12318 int i;
12319
12320 NDBG6(("mptsas_rem_intrs"));
12321
12322 /* Disable all interrupts */
12323 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) {
12324 /* Call ddi_intr_block_disable() */
12325 (void) ddi_intr_block_disable(mpt->m_htable, mpt->m_intr_cnt);
12326 } else {
12327 for (i = 0; i < mpt->m_intr_cnt; i++) {
12328 (void) ddi_intr_disable(mpt->m_htable[i]);
12329 }
12330 }
12331
12332 /* Call ddi_intr_remove_handler() */
12333 for (i = 0; i < mpt->m_intr_cnt; i++) {
12334 (void) ddi_intr_remove_handler(mpt->m_htable[i]);
12335 (void) ddi_intr_free(mpt->m_htable[i]);
12336 }
12337
12338 kmem_free(mpt->m_htable, mpt->m_intr_size);
12339 }
12340
12341 /*
12342 * The IO fault service error handling callback function
12343 */
12344 /*ARGSUSED*/
12345 static int
12346 mptsas_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
12347 {
12348 /*
12349 * as the driver can always deal with an error in any dma or
12350 * access handle, we can just return the fme_status value.
12351 */
12352 pci_ereport_post(dip, err, NULL);
12353 return (err->fme_status);
12354 }
12355
12356 /*
12357 * mptsas_fm_init - initialize fma capabilities and register with IO
12358 * fault services.
12359 */
12360 static void
12361 mptsas_fm_init(mptsas_t *mpt)
12362 {
12363 /*
12364 * Need to change iblock to priority for new MSI intr
12365 */
12366 ddi_iblock_cookie_t fm_ibc;
12367
12368 /* Only register with IO Fault Services if we have some capability */
12369 if (mpt->m_fm_capabilities) {
12370 /* Adjust access and dma attributes for FMA */
12371 mpt->m_reg_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC;
12372 mpt->m_msg_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
12373 mpt->m_io_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
12374
12375 /*
12376 * Register capabilities with IO Fault Services.
12377 * mpt->m_fm_capabilities will be updated to indicate
12378 * capabilities actually supported (not requested.)
12379 */
12380 ddi_fm_init(mpt->m_dip, &mpt->m_fm_capabilities, &fm_ibc);
12381
12382 /*
12383 * Initialize pci ereport capabilities if ereport
12384 * capable (should always be.)
12385 */
12386 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) ||
12387 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
12388 pci_ereport_setup(mpt->m_dip);
12389 }
12390
12391 /*
12392 * Register error callback if error callback capable.
12393 */
12394 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
12395 ddi_fm_handler_register(mpt->m_dip,
12396 mptsas_fm_error_cb, (void *) mpt);
12397 }
12398 }
12399 }
12400
12401 /*
12402 * mptsas_fm_fini - Releases fma capabilities and un-registers with IO
12403 * fault services.
12404 *
12405 */
12406 static void
12407 mptsas_fm_fini(mptsas_t *mpt)
12408 {
12409 /* Only unregister FMA capabilities if registered */
12410 if (mpt->m_fm_capabilities) {
12411
12412 /*
12413 * Un-register error callback if error callback capable.
12414 */
12415
12416 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
12417 ddi_fm_handler_unregister(mpt->m_dip);
12418 }
12419
12420 /*
12421 * Release any resources allocated by pci_ereport_setup()
12422 */
12423
12424 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) ||
12425 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
12426 pci_ereport_teardown(mpt->m_dip);
12427 }
12428
12429 /* Unregister from IO Fault Services */
12430 ddi_fm_fini(mpt->m_dip);
12431
12432 /* Adjust access and dma attributes for FMA */
12433 mpt->m_reg_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC;
12434 mpt->m_msg_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
12435 mpt->m_io_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
12436
12437 }
12438 }
12439
12440 int
12441 mptsas_check_acc_handle(ddi_acc_handle_t handle)
12442 {
12443 ddi_fm_error_t de;
12444
12445 if (handle == NULL)
12446 return (DDI_FAILURE);
12447 ddi_fm_acc_err_get(handle, &de, DDI_FME_VER0);
12448 return (de.fme_status);
12449 }
12450
12451 int
12452 mptsas_check_dma_handle(ddi_dma_handle_t handle)
12453 {
12454 ddi_fm_error_t de;
12455
12456 if (handle == NULL)
12457 return (DDI_FAILURE);
12458 ddi_fm_dma_err_get(handle, &de, DDI_FME_VER0);
12459 return (de.fme_status);
12460 }
12461
12462 void
12463 mptsas_fm_ereport(mptsas_t *mpt, char *detail)
12464 {
12465 uint64_t ena;
12466 char buf[FM_MAX_CLASS];
12467
12468 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
12469 ena = fm_ena_generate(0, FM_ENA_FMT1);
12470 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities)) {
12471 ddi_fm_ereport_post(mpt->m_dip, buf, ena, DDI_NOSLEEP,
12472 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL);
12473 }
12474 }
12475
12476 static int
12477 mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address,
12478 uint16_t *dev_handle, mptsas_target_t **pptgt)
12479 {
12480 int rval;
12481 uint32_t dev_info;
12482 uint64_t sas_wwn;
12483 mptsas_phymask_t phymask;
12484 uint8_t physport, phynum, config, disk;
12485 mptsas_slots_t *slots = mpt->m_active;
12486 uint64_t devicename;
12487 uint16_t pdev_hdl;
12488 mptsas_target_t *tmp_tgt = NULL;
12489 uint16_t bay_num, enclosure;
12490
12491 ASSERT(*pptgt == NULL);
12492
12493 rval = mptsas_get_sas_device_page0(mpt, page_address, dev_handle,
12494 &sas_wwn, &dev_info, &physport, &phynum, &pdev_hdl,
12495 &bay_num, &enclosure);
12496 if (rval != DDI_SUCCESS) {
12497 rval = DEV_INFO_FAIL_PAGE0;
12498 return (rval);
12499 }
12500
12501 if ((dev_info & (MPI2_SAS_DEVICE_INFO_SSP_TARGET |
12502 MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
12503 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) == NULL) {
12504 rval = DEV_INFO_WRONG_DEVICE_TYPE;
12505 return (rval);
12506 }
12507
12508 /*
12509 * Check if the dev handle is for a Phys Disk. If so, set return value
12510 * and exit. Don't add Phys Disks to hash.
12511 */
12512 for (config = 0; config < slots->m_num_raid_configs; config++) {
12513 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) {
12514 if (*dev_handle == slots->m_raidconfig[config].
12515 m_physdisk_devhdl[disk]) {
12516 rval = DEV_INFO_PHYS_DISK;
12517 return (rval);
12518 }
12519 }
12520 }
12521
12522 /*
12523 * Get SATA Device Name from SAS device page0 for
12524 * sata device, if device name doesn't exist, set m_sas_wwn to
12525 * 0 for direct attached SATA. For the device behind the expander
12526 * we still can use STP address assigned by expander.
12527 */
12528 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
12529 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
12530 mutex_exit(&mpt->m_mutex);
12531 /* alloc a tmp_tgt to send the cmd */
12532 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target),
12533 KM_SLEEP);
12534 tmp_tgt->m_devhdl = *dev_handle;
12535 tmp_tgt->m_deviceinfo = dev_info;
12536 tmp_tgt->m_qfull_retries = QFULL_RETRIES;
12537 tmp_tgt->m_qfull_retry_interval =
12538 drv_usectohz(QFULL_RETRY_INTERVAL * 1000);
12539 tmp_tgt->m_t_throttle = MAX_THROTTLE;
12540 devicename = mptsas_get_sata_guid(mpt, tmp_tgt, 0);
12541 kmem_free(tmp_tgt, sizeof (struct mptsas_target));
12542 mutex_enter(&mpt->m_mutex);
12543 if (devicename != 0 && (((devicename >> 56) & 0xf0) == 0x50)) {
12544 sas_wwn = devicename;
12545 } else if (dev_info & MPI2_SAS_DEVICE_INFO_DIRECT_ATTACH) {
12546 sas_wwn = 0;
12547 }
12548 }
12549
12550 phymask = mptsas_physport_to_phymask(mpt, physport);
12551 *pptgt = mptsas_tgt_alloc(&slots->m_tgttbl, *dev_handle, sas_wwn,
12552 dev_info, phymask, phynum);
12553 if (*pptgt == NULL) {
12554 mptsas_log(mpt, CE_WARN, "Failed to allocated target"
12555 "structure!");
12556 rval = DEV_INFO_FAIL_ALLOC;
12557 return (rval);
12558 }
12559 (*pptgt)->m_enclosure = enclosure;
12560 (*pptgt)->m_slot_num = bay_num;
12561 return (DEV_INFO_SUCCESS);
12562 }
12563
12564 uint64_t
12565 mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun)
12566 {
12567 uint64_t sata_guid = 0, *pwwn = NULL;
12568 int target = ptgt->m_devhdl;
12569 uchar_t *inq83 = NULL;
12570 int inq83_len = 0xFF;
12571 uchar_t *dblk = NULL;
12572 int inq83_retry = 3;
12573 int rval = DDI_FAILURE;
12574
12575 inq83 = kmem_zalloc(inq83_len, KM_SLEEP);
12576
12577 inq83_retry:
12578 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83,
12579 inq83_len, NULL, 1);
12580 if (rval != DDI_SUCCESS) {
12581 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
12582 "0x83 for target:%x, lun:%x failed!", target, lun);
12583 goto out;
12584 }
12585 /* According to SAT2, the first descriptor is logic unit name */
12586 dblk = &inq83[4];
12587 if ((dblk[1] & 0x30) != 0) {
12588 mptsas_log(mpt, CE_WARN, "!Descriptor is not lun associated.");
12589 goto out;
12590 }
12591 pwwn = (uint64_t *)(void *)(&dblk[4]);
12592 if ((dblk[4] & 0xf0) == 0x50) {
12593 sata_guid = BE_64(*pwwn);
12594 goto out;
12595 } else if (dblk[4] == 'A') {
12596 NDBG20(("SATA drive has no NAA format GUID."));
12597 goto out;
12598 } else {
12599 /* The data is not ready, wait and retry */
12600 inq83_retry--;
12601 if (inq83_retry <= 0) {
12602 goto out;
12603 }
12604 NDBG20(("The GUID is not ready, retry..."));
12605 delay(1 * drv_usectohz(1000000));
12606 goto inq83_retry;
12607 }
12608 out:
12609 kmem_free(inq83, inq83_len);
12610 return (sata_guid);
12611 }
12612
12613 static int
12614 mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, uchar_t page,
12615 unsigned char *buf, int len, int *reallen, uchar_t evpd)
12616 {
12617 uchar_t cdb[CDB_GROUP0];
12618 struct scsi_address ap;
12619 struct buf *data_bp = NULL;
12620 int resid = 0;
12621 int ret = DDI_FAILURE;
12622
12623 ASSERT(len <= 0xffff);
12624
12625 ap.a_target = MPTSAS_INVALID_DEVHDL;
12626 ap.a_lun = (uchar_t)(lun);
12627 ap.a_hba_tran = mpt->m_tran;
12628
12629 data_bp = scsi_alloc_consistent_buf(&ap,
12630 (struct buf *)NULL, len, B_READ, NULL_FUNC, NULL);
12631 if (data_bp == NULL) {
12632 return (ret);
12633 }
12634 bzero(cdb, CDB_GROUP0);
12635 cdb[0] = SCMD_INQUIRY;
12636 cdb[1] = evpd;
12637 cdb[2] = page;
12638 cdb[3] = (len & 0xff00) >> 8;
12639 cdb[4] = (len & 0x00ff);
12640 cdb[5] = 0;
12641
12642 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP0, data_bp,
12643 &resid);
12644 if (ret == DDI_SUCCESS) {
12645 if (reallen) {
12646 *reallen = len - resid;
12647 }
12648 bcopy((caddr_t)data_bp->b_un.b_addr, buf, len);
12649 }
12650 if (data_bp) {
12651 scsi_free_consistent_buf(data_bp);
12652 }
12653 return (ret);
12654 }
12655
12656 static int
12657 mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap,
12658 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp,
12659 int *resid)
12660 {
12661 struct scsi_pkt *pktp = NULL;
12662 scsi_hba_tran_t *tran_clone = NULL;
12663 mptsas_tgt_private_t *tgt_private = NULL;
12664 int ret = DDI_FAILURE;
12665
12666 /*
12667 * scsi_hba_tran_t->tran_tgt_private is used to pass the address
12668 * information to scsi_init_pkt, allocate a scsi_hba_tran structure
12669 * to simulate the cmds from sd
12670 */
12671 tran_clone = kmem_alloc(
12672 sizeof (scsi_hba_tran_t), KM_SLEEP);
12673 if (tran_clone == NULL) {
12674 goto out;
12675 }
12676 bcopy((caddr_t)mpt->m_tran,
12677 (caddr_t)tran_clone, sizeof (scsi_hba_tran_t));
12678 tgt_private = kmem_alloc(
12679 sizeof (mptsas_tgt_private_t), KM_SLEEP);
12680 if (tgt_private == NULL) {
12681 goto out;
12682 }
12683 tgt_private->t_lun = ap->a_lun;
12684 tgt_private->t_private = ptgt;
12685 tran_clone->tran_tgt_private = tgt_private;
12686 ap->a_hba_tran = tran_clone;
12687
12688 pktp = scsi_init_pkt(ap, (struct scsi_pkt *)NULL,
12689 data_bp, cdblen, sizeof (struct scsi_arq_status),
12690 0, PKT_CONSISTENT, NULL, NULL);
12691 if (pktp == NULL) {
12692 goto out;
12693 }
12694 bcopy(cdb, pktp->pkt_cdbp, cdblen);
12695 pktp->pkt_flags = FLAG_NOPARITY;
12696 if (scsi_poll(pktp) < 0) {
12697 goto out;
12698 }
12699 if (((struct scsi_status *)pktp->pkt_scbp)->sts_chk) {
12700 goto out;
12701 }
12702 if (resid != NULL) {
12703 *resid = pktp->pkt_resid;
12704 }
12705
12706 ret = DDI_SUCCESS;
12707 out:
12708 if (pktp) {
12709 scsi_destroy_pkt(pktp);
12710 }
12711 if (tran_clone) {
12712 kmem_free(tran_clone, sizeof (scsi_hba_tran_t));
12713 }
12714 if (tgt_private) {
12715 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t));
12716 }
12717 return (ret);
12718 }
12719 static int
12720 mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, int *lun)
12721 {
12722 char *cp = NULL;
12723 char *ptr = NULL;
12724 size_t s = 0;
12725 char *wwid_str = NULL;
12726 char *lun_str = NULL;
12727 long lunnum;
12728 long phyid = -1;
12729 int rc = DDI_FAILURE;
12730
12731 ptr = name;
12732 ASSERT(ptr[0] == 'w' || ptr[0] == 'p');
12733 ptr++;
12734 if ((cp = strchr(ptr, ',')) == NULL) {
12735 return (DDI_FAILURE);
12736 }
12737
12738 wwid_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
12739 s = (uintptr_t)cp - (uintptr_t)ptr;
12740
12741 bcopy(ptr, wwid_str, s);
12742 wwid_str[s] = '\0';
12743
12744 ptr = ++cp;
12745
12746 if ((cp = strchr(ptr, '\0')) == NULL) {
12747 goto out;
12748 }
12749 lun_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
12750 s = (uintptr_t)cp - (uintptr_t)ptr;
12751
12752 bcopy(ptr, lun_str, s);
12753 lun_str[s] = '\0';
12754
12755 if (name[0] == 'p') {
12756 rc = ddi_strtol(wwid_str, NULL, 0x10, &phyid);
12757 } else {
12758 rc = scsi_wwnstr_to_wwn(wwid_str, wwid);
12759 }
12760 if (rc != DDI_SUCCESS)
12761 goto out;
12762
12763 if (phyid != -1) {
12764 ASSERT(phyid < MPTSAS_MAX_PHYS);
12765 *phy = (uint8_t)phyid;
12766 }
12767 rc = ddi_strtol(lun_str, NULL, 0x10, &lunnum);
12768 if (rc != 0)
12769 goto out;
12770
12771 *lun = (int)lunnum;
12772 rc = DDI_SUCCESS;
12773 out:
12774 if (wwid_str)
12775 kmem_free(wwid_str, SCSI_MAXNAMELEN);
12776 if (lun_str)
12777 kmem_free(lun_str, SCSI_MAXNAMELEN);
12778
12779 return (rc);
12780 }
12781
12782 /*
12783 * mptsas_parse_smp_name() is to parse sas wwn string
12784 * which format is "wWWN"
12785 */
12786 static int
12787 mptsas_parse_smp_name(char *name, uint64_t *wwn)
12788 {
12789 char *ptr = name;
12790
12791 if (*ptr != 'w') {
12792 return (DDI_FAILURE);
12793 }
12794
12795 ptr++;
12796 if (scsi_wwnstr_to_wwn(ptr, wwn)) {
12797 return (DDI_FAILURE);
12798 }
12799 return (DDI_SUCCESS);
12800 }
12801
12802 static int
12803 mptsas_bus_config(dev_info_t *pdip, uint_t flag,
12804 ddi_bus_config_op_t op, void *arg, dev_info_t **childp)
12805 {
12806 int ret = NDI_FAILURE;
12807 int circ = 0;
12808 int circ1 = 0;
12809 mptsas_t *mpt;
12810 char *ptr = NULL;
12811 char *devnm = NULL;
12812 uint64_t wwid = 0;
12813 uint8_t phy = 0xFF;
12814 int lun = 0;
12815 uint_t mflags = flag;
12816 int bconfig = TRUE;
12817
12818 if (scsi_hba_iport_unit_address(pdip) == 0) {
12819 return (DDI_FAILURE);
12820 }
12821
12822 mpt = DIP2MPT(pdip);
12823 if (!mpt) {
12824 return (DDI_FAILURE);
12825 }
12826 /*
12827 * Hold the nexus across the bus_config
12828 */
12829 ndi_devi_enter(scsi_vhci_dip, &circ);
12830 ndi_devi_enter(pdip, &circ1);
12831 switch (op) {
12832 case BUS_CONFIG_ONE:
12833 /* parse wwid/target name out of name given */
12834 if ((ptr = strchr((char *)arg, '@')) == NULL) {
12835 ret = NDI_FAILURE;
12836 break;
12837 }
12838 ptr++;
12839 if (strncmp((char *)arg, "smp", 3) == 0) {
12840 /*
12841 * This is a SMP target device
12842 */
12843 ret = mptsas_parse_smp_name(ptr, &wwid);
12844 if (ret != DDI_SUCCESS) {
12845 ret = NDI_FAILURE;
12846 break;
12847 }
12848 ret = mptsas_config_smp(pdip, wwid, childp);
12849 } else if ((ptr[0] == 'w') || (ptr[0] == 'p')) {
12850 /*
12851 * OBP could pass down a non-canonical form
12852 * bootpath without LUN part when LUN is 0.
12853 * So driver need adjust the string.
12854 */
12855 if (strchr(ptr, ',') == NULL) {
12856 devnm = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
12857 (void) sprintf(devnm, "%s,0", (char *)arg);
12858 ptr = strchr(devnm, '@');
12859 ptr++;
12860 }
12861
12862 /*
12863 * The device path is wWWID format and the device
12864 * is not SMP target device.
12865 */
12866 ret = mptsas_parse_address(ptr, &wwid, &phy, &lun);
12867 if (ret != DDI_SUCCESS) {
12868 ret = NDI_FAILURE;
12869 break;
12870 }
12871 *childp = NULL;
12872 if (ptr[0] == 'w') {
12873 ret = mptsas_config_one_addr(pdip, wwid,
12874 lun, childp);
12875 } else if (ptr[0] == 'p') {
12876 ret = mptsas_config_one_phy(pdip, phy, lun,
12877 childp);
12878 }
12879
12880 /*
12881 * If this is CD/DVD device in OBP path, the
12882 * ndi_busop_bus_config can be skipped as config one
12883 * operation is done above.
12884 */
12885 if ((ret == NDI_SUCCESS) && (*childp != NULL) &&
12886 (strcmp(ddi_node_name(*childp), "cdrom") == 0) &&
12887 (strncmp((char *)arg, "disk", 4) == 0)) {
12888 bconfig = FALSE;
12889 ndi_hold_devi(*childp);
12890 }
12891 } else {
12892 ret = NDI_FAILURE;
12893 break;
12894 }
12895
12896 /*
12897 * DDI group instructed us to use this flag.
12898 */
12899 mflags |= NDI_MDI_FALLBACK;
12900 break;
12901 case BUS_CONFIG_DRIVER:
12902 case BUS_CONFIG_ALL:
12903 mptsas_config_all(pdip);
12904 ret = NDI_SUCCESS;
12905 break;
12906 }
12907
12908 if ((ret == NDI_SUCCESS) && bconfig) {
12909 ret = ndi_busop_bus_config(pdip, mflags, op,
12910 (devnm == NULL) ? arg : devnm, childp, 0);
12911 }
12912
12913 ndi_devi_exit(pdip, circ1);
12914 ndi_devi_exit(scsi_vhci_dip, circ);
12915 if (devnm != NULL)
12916 kmem_free(devnm, SCSI_MAXNAMELEN);
12917 return (ret);
12918 }
12919
12920 static int
12921 mptsas_probe_lun(dev_info_t *pdip, int lun, dev_info_t **dip,
12922 mptsas_target_t *ptgt)
12923 {
12924 int rval = DDI_FAILURE;
12925 struct scsi_inquiry *sd_inq = NULL;
12926 mptsas_t *mpt = DIP2MPT(pdip);
12927
12928 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP);
12929
12930 rval = mptsas_inquiry(mpt, ptgt, lun, 0, (uchar_t *)sd_inq,
12931 SUN_INQSIZE, 0, (uchar_t)0);
12932
12933 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) {
12934 rval = mptsas_create_lun(pdip, sd_inq, dip, ptgt, lun);
12935 } else {
12936 rval = DDI_FAILURE;
12937 }
12938
12939 kmem_free(sd_inq, SUN_INQSIZE);
12940 return (rval);
12941 }
12942
12943 static int
12944 mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun,
12945 dev_info_t **lundip)
12946 {
12947 int rval;
12948 mptsas_t *mpt = DIP2MPT(pdip);
12949 int phymask;
12950 mptsas_target_t *ptgt = NULL;
12951
12952 /*
12953 * Get the physical port associated to the iport
12954 */
12955 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
12956 "phymask", 0);
12957
12958 ptgt = mptsas_wwid_to_ptgt(mpt, phymask, sasaddr);
12959 if (ptgt == NULL) {
12960 /*
12961 * didn't match any device by searching
12962 */
12963 return (DDI_FAILURE);
12964 }
12965 /*
12966 * If the LUN already exists and the status is online,
12967 * we just return the pointer to dev_info_t directly.
12968 * For the mdi_pathinfo node, we'll handle it in
12969 * mptsas_create_virt_lun()
12970 * TODO should be also in mptsas_handle_dr
12971 */
12972
12973 *lundip = mptsas_find_child_addr(pdip, sasaddr, lun);
12974 if (*lundip != NULL) {
12975 /*
12976 * TODO Another senario is, we hotplug the same disk
12977 * on the same slot, the devhdl changed, is this
12978 * possible?
12979 * tgt_private->t_private != ptgt
12980 */
12981 if (sasaddr != ptgt->m_sas_wwn) {
12982 /*
12983 * The device has changed although the devhdl is the
12984 * same (Enclosure mapping mode, change drive on the
12985 * same slot)
12986 */
12987 return (DDI_FAILURE);
12988 }
12989 return (DDI_SUCCESS);
12990 }
12991
12992 if (phymask == 0) {
12993 /*
12994 * Configure IR volume
12995 */
12996 rval = mptsas_config_raid(pdip, ptgt->m_devhdl, lundip);
12997 return (rval);
12998 }
12999 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt);
13000
13001 return (rval);
13002 }
13003
13004 static int
13005 mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun,
13006 dev_info_t **lundip)
13007 {
13008 int rval;
13009 mptsas_t *mpt = DIP2MPT(pdip);
13010 int phymask;
13011 mptsas_target_t *ptgt = NULL;
13012
13013 /*
13014 * Get the physical port associated to the iport
13015 */
13016 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
13017 "phymask", 0);
13018
13019 ptgt = mptsas_phy_to_tgt(mpt, phymask, phy);
13020 if (ptgt == NULL) {
13021 /*
13022 * didn't match any device by searching
13023 */
13024 return (DDI_FAILURE);
13025 }
13026
13027 /*
13028 * If the LUN already exists and the status is online,
13029 * we just return the pointer to dev_info_t directly.
13030 * For the mdi_pathinfo node, we'll handle it in
13031 * mptsas_create_virt_lun().
13032 */
13033
13034 *lundip = mptsas_find_child_phy(pdip, phy);
13035 if (*lundip != NULL) {
13036 return (DDI_SUCCESS);
13037 }
13038
13039 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt);
13040
13041 return (rval);
13042 }
13043
13044 static int
13045 mptsas_retrieve_lundata(int lun_cnt, uint8_t *buf, uint16_t *lun_num,
13046 uint8_t *lun_addr_type)
13047 {
13048 uint32_t lun_idx = 0;
13049
13050 ASSERT(lun_num != NULL);
13051 ASSERT(lun_addr_type != NULL);
13052
13053 lun_idx = (lun_cnt + 1) * MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE;
13054 /* determine report luns addressing type */
13055 switch (buf[lun_idx] & MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) {
13056 /*
13057 * Vendors in the field have been found to be concatenating
13058 * bus/target/lun to equal the complete lun value instead
13059 * of switching to flat space addressing
13060 */
13061 /* 00b - peripheral device addressing method */
13062 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL:
13063 /* FALLTHRU */
13064 /* 10b - logical unit addressing method */
13065 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT:
13066 /* FALLTHRU */
13067 /* 01b - flat space addressing method */
13068 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE:
13069 /* byte0 bit0-5=msb lun byte1 bit0-7=lsb lun */
13070 *lun_addr_type = (buf[lun_idx] &
13071 MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) >> 6;
13072 *lun_num = (buf[lun_idx] & 0x3F) << 8;
13073 *lun_num |= buf[lun_idx + 1];
13074 return (DDI_SUCCESS);
13075 default:
13076 return (DDI_FAILURE);
13077 }
13078 }
13079
13080 static int
13081 mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt)
13082 {
13083 struct buf *repluns_bp = NULL;
13084 struct scsi_address ap;
13085 uchar_t cdb[CDB_GROUP5];
13086 int ret = DDI_FAILURE;
13087 int retry = 0;
13088 int lun_list_len = 0;
13089 uint16_t lun_num = 0;
13090 uint8_t lun_addr_type = 0;
13091 uint32_t lun_cnt = 0;
13092 uint32_t lun_total = 0;
13093 dev_info_t *cdip = NULL;
13094 uint16_t *saved_repluns = NULL;
13095 char *buffer = NULL;
13096 int buf_len = 128;
13097 mptsas_t *mpt = DIP2MPT(pdip);
13098 uint64_t sas_wwn = 0;
13099 uint8_t phy = 0xFF;
13100 uint32_t dev_info = 0;
13101
13102 mutex_enter(&mpt->m_mutex);
13103 sas_wwn = ptgt->m_sas_wwn;
13104 phy = ptgt->m_phynum;
13105 dev_info = ptgt->m_deviceinfo;
13106 mutex_exit(&mpt->m_mutex);
13107
13108 if (sas_wwn == 0) {
13109 /*
13110 * It's a SATA without Device Name
13111 * So don't try multi-LUNs
13112 */
13113 if (mptsas_find_child_phy(pdip, phy)) {
13114 return (DDI_SUCCESS);
13115 } else {
13116 /*
13117 * need configure and create node
13118 */
13119 return (DDI_FAILURE);
13120 }
13121 }
13122
13123 /*
13124 * WWN (SAS address or Device Name exist)
13125 */
13126 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
13127 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
13128 /*
13129 * SATA device with Device Name
13130 * So don't try multi-LUNs
13131 */
13132 if (mptsas_find_child_addr(pdip, sas_wwn, 0)) {
13133 return (DDI_SUCCESS);
13134 } else {
13135 return (DDI_FAILURE);
13136 }
13137 }
13138
13139 do {
13140 ap.a_target = MPTSAS_INVALID_DEVHDL;
13141 ap.a_lun = 0;
13142 ap.a_hba_tran = mpt->m_tran;
13143 repluns_bp = scsi_alloc_consistent_buf(&ap,
13144 (struct buf *)NULL, buf_len, B_READ, NULL_FUNC, NULL);
13145 if (repluns_bp == NULL) {
13146 retry++;
13147 continue;
13148 }
13149 bzero(cdb, CDB_GROUP5);
13150 cdb[0] = SCMD_REPORT_LUNS;
13151 cdb[6] = (buf_len & 0xff000000) >> 24;
13152 cdb[7] = (buf_len & 0x00ff0000) >> 16;
13153 cdb[8] = (buf_len & 0x0000ff00) >> 8;
13154 cdb[9] = (buf_len & 0x000000ff);
13155
13156 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP5,
13157 repluns_bp, NULL);
13158 if (ret != DDI_SUCCESS) {
13159 scsi_free_consistent_buf(repluns_bp);
13160 retry++;
13161 continue;
13162 }
13163 lun_list_len = BE_32(*(int *)((void *)(
13164 repluns_bp->b_un.b_addr)));
13165 if (buf_len >= lun_list_len + 8) {
13166 ret = DDI_SUCCESS;
13167 break;
13168 }
13169 scsi_free_consistent_buf(repluns_bp);
13170 buf_len = lun_list_len + 8;
13171
13172 } while (retry < 3);
13173
13174 if (ret != DDI_SUCCESS)
13175 return (ret);
13176 buffer = (char *)repluns_bp->b_un.b_addr;
13177 /*
13178 * find out the number of luns returned by the SCSI ReportLun call
13179 * and allocate buffer space
13180 */
13181 lun_total = lun_list_len / MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE;
13182 saved_repluns = kmem_zalloc(sizeof (uint16_t) * lun_total, KM_SLEEP);
13183 if (saved_repluns == NULL) {
13184 scsi_free_consistent_buf(repluns_bp);
13185 return (DDI_FAILURE);
13186 }
13187 for (lun_cnt = 0; lun_cnt < lun_total; lun_cnt++) {
13188 if (mptsas_retrieve_lundata(lun_cnt, (uint8_t *)(buffer),
13189 &lun_num, &lun_addr_type) != DDI_SUCCESS) {
13190 continue;
13191 }
13192 saved_repluns[lun_cnt] = lun_num;
13193 if (cdip = mptsas_find_child_addr(pdip, sas_wwn, lun_num))
13194 ret = DDI_SUCCESS;
13195 else
13196 ret = mptsas_probe_lun(pdip, lun_num, &cdip,
13197 ptgt);
13198 if ((ret == DDI_SUCCESS) && (cdip != NULL)) {
13199 (void) ndi_prop_remove(DDI_DEV_T_NONE, cdip,
13200 MPTSAS_DEV_GONE);
13201 }
13202 }
13203 mptsas_offline_missed_luns(pdip, saved_repluns, lun_total, ptgt);
13204 kmem_free(saved_repluns, sizeof (uint16_t) * lun_total);
13205 scsi_free_consistent_buf(repluns_bp);
13206 return (DDI_SUCCESS);
13207 }
13208
13209 static int
13210 mptsas_config_raid(dev_info_t *pdip, uint16_t target, dev_info_t **dip)
13211 {
13212 int rval = DDI_FAILURE;
13213 struct scsi_inquiry *sd_inq = NULL;
13214 mptsas_t *mpt = DIP2MPT(pdip);
13215 mptsas_target_t *ptgt = NULL;
13216
13217 mutex_enter(&mpt->m_mutex);
13218 ptgt = mptsas_search_by_devhdl(&mpt->m_active->m_tgttbl, target);
13219 mutex_exit(&mpt->m_mutex);
13220 if (ptgt == NULL) {
13221 mptsas_log(mpt, CE_WARN, "Volume with VolDevHandle of 0x%x "
13222 "not found.", target);
13223 return (rval);
13224 }
13225
13226 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP);
13227 rval = mptsas_inquiry(mpt, ptgt, 0, 0, (uchar_t *)sd_inq,
13228 SUN_INQSIZE, 0, (uchar_t)0);
13229
13230 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) {
13231 rval = mptsas_create_phys_lun(pdip, sd_inq, NULL, dip, ptgt,
13232 0);
13233 } else {
13234 rval = DDI_FAILURE;
13235 }
13236
13237 kmem_free(sd_inq, SUN_INQSIZE);
13238 return (rval);
13239 }
13240
13241 /*
13242 * configure all RAID volumes for virtual iport
13243 */
13244 static void
13245 mptsas_config_all_viport(dev_info_t *pdip)
13246 {
13247 mptsas_t *mpt = DIP2MPT(pdip);
13248 int config, vol;
13249 int target;
13250 dev_info_t *lundip = NULL;
13251 mptsas_slots_t *slots = mpt->m_active;
13252
13253 /*
13254 * Get latest RAID info and search for any Volume DevHandles. If any
13255 * are found, configure the volume.
13256 */
13257 mutex_enter(&mpt->m_mutex);
13258 for (config = 0; config < slots->m_num_raid_configs; config++) {
13259 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) {
13260 if (slots->m_raidconfig[config].m_raidvol[vol].m_israid
13261 == 1) {
13262 target = slots->m_raidconfig[config].
13263 m_raidvol[vol].m_raidhandle;
13264 mutex_exit(&mpt->m_mutex);
13265 (void) mptsas_config_raid(pdip, target,
13266 &lundip);
13267 mutex_enter(&mpt->m_mutex);
13268 }
13269 }
13270 }
13271 mutex_exit(&mpt->m_mutex);
13272 }
13273
13274 static void
13275 mptsas_offline_missed_luns(dev_info_t *pdip, uint16_t *repluns,
13276 int lun_cnt, mptsas_target_t *ptgt)
13277 {
13278 dev_info_t *child = NULL, *savechild = NULL;
13279 mdi_pathinfo_t *pip = NULL, *savepip = NULL;
13280 uint64_t sas_wwn, wwid;
13281 uint8_t phy;
13282 int lun;
13283 int i;
13284 int find;
13285 char *addr;
13286 char *nodename;
13287 mptsas_t *mpt = DIP2MPT(pdip);
13288
13289 mutex_enter(&mpt->m_mutex);
13290 wwid = ptgt->m_sas_wwn;
13291 mutex_exit(&mpt->m_mutex);
13292
13293 child = ddi_get_child(pdip);
13294 while (child) {
13295 find = 0;
13296 savechild = child;
13297 child = ddi_get_next_sibling(child);
13298
13299 nodename = ddi_node_name(savechild);
13300 if (strcmp(nodename, "smp") == 0) {
13301 continue;
13302 }
13303
13304 addr = ddi_get_name_addr(savechild);
13305 if (addr == NULL) {
13306 continue;
13307 }
13308
13309 if (mptsas_parse_address(addr, &sas_wwn, &phy, &lun) !=
13310 DDI_SUCCESS) {
13311 continue;
13312 }
13313
13314 if (wwid == sas_wwn) {
13315 for (i = 0; i < lun_cnt; i++) {
13316 if (repluns[i] == lun) {
13317 find = 1;
13318 break;
13319 }
13320 }
13321 } else {
13322 continue;
13323 }
13324 if (find == 0) {
13325 /*
13326 * The lun has not been there already
13327 */
13328 (void) mptsas_offline_lun(pdip, savechild, NULL,
13329 NDI_DEVI_REMOVE);
13330 }
13331 }
13332
13333 pip = mdi_get_next_client_path(pdip, NULL);
13334 while (pip) {
13335 find = 0;
13336 savepip = pip;
13337 addr = MDI_PI(pip)->pi_addr;
13338
13339 pip = mdi_get_next_client_path(pdip, pip);
13340
13341 if (addr == NULL) {
13342 continue;
13343 }
13344
13345 if (mptsas_parse_address(addr, &sas_wwn, &phy,
13346 &lun) != DDI_SUCCESS) {
13347 continue;
13348 }
13349
13350 if (sas_wwn == wwid) {
13351 for (i = 0; i < lun_cnt; i++) {
13352 if (repluns[i] == lun) {
13353 find = 1;
13354 break;
13355 }
13356 }
13357 } else {
13358 continue;
13359 }
13360
13361 if (find == 0) {
13362 /*
13363 * The lun has not been there already
13364 */
13365 (void) mptsas_offline_lun(pdip, NULL, savepip,
13366 NDI_DEVI_REMOVE);
13367 }
13368 }
13369 }
13370
13371 void
13372 mptsas_update_hashtab(struct mptsas *mpt)
13373 {
13374 uint32_t page_address;
13375 int rval = 0;
13376 uint16_t dev_handle;
13377 mptsas_target_t *ptgt = NULL;
13378 mptsas_smp_t smp_node;
13379
13380 /*
13381 * Get latest RAID info.
13382 */
13383 (void) mptsas_get_raid_info(mpt);
13384
13385 dev_handle = mpt->m_smp_devhdl;
13386 for (; mpt->m_done_traverse_smp == 0; ) {
13387 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL &
13388 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)dev_handle;
13389 if (mptsas_get_sas_expander_page0(mpt, page_address, &smp_node)
13390 != DDI_SUCCESS) {
13391 break;
13392 }
13393 mpt->m_smp_devhdl = dev_handle = smp_node.m_devhdl;
13394 (void) mptsas_smp_alloc(&mpt->m_active->m_smptbl, &smp_node);
13395 }
13396
13397 /*
13398 * Config target devices
13399 */
13400 dev_handle = mpt->m_dev_handle;
13401
13402 /*
13403 * Do loop to get sas device page 0 by GetNextHandle till the
13404 * the last handle. If the sas device is a SATA/SSP target,
13405 * we try to config it.
13406 */
13407 for (; mpt->m_done_traverse_dev == 0; ) {
13408 ptgt = NULL;
13409 page_address =
13410 (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
13411 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
13412 (uint32_t)dev_handle;
13413 rval = mptsas_get_target_device_info(mpt, page_address,
13414 &dev_handle, &ptgt);
13415 if ((rval == DEV_INFO_FAIL_PAGE0) ||
13416 (rval == DEV_INFO_FAIL_ALLOC)) {
13417 break;
13418 }
13419
13420 mpt->m_dev_handle = dev_handle;
13421 }
13422
13423 }
13424
13425 void
13426 mptsas_invalid_hashtab(mptsas_hash_table_t *hashtab)
13427 {
13428 mptsas_hash_data_t *data;
13429 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_FIRST);
13430 while (data != NULL) {
13431 data->devhdl = MPTSAS_INVALID_DEVHDL;
13432 data->device_info = 0;
13433 /*
13434 * For tgttbl, clear dr_flag.
13435 */
13436 data->dr_flag = MPTSAS_DR_INACTIVE;
13437 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_NEXT);
13438 }
13439 }
13440
13441 void
13442 mptsas_update_driver_data(struct mptsas *mpt)
13443 {
13444 /*
13445 * TODO after hard reset, update the driver data structures
13446 * 1. update port/phymask mapping table mpt->m_phy_info
13447 * 2. invalid all the entries in hash table
13448 * m_devhdl = 0xffff and m_deviceinfo = 0
13449 * 3. call sas_device_page/expander_page to update hash table
13450 */
13451 mptsas_update_phymask(mpt);
13452 /*
13453 * Invalid the existing entries
13454 */
13455 mptsas_invalid_hashtab(&mpt->m_active->m_tgttbl);
13456 mptsas_invalid_hashtab(&mpt->m_active->m_smptbl);
13457 mpt->m_done_traverse_dev = 0;
13458 mpt->m_done_traverse_smp = 0;
13459 mpt->m_dev_handle = mpt->m_smp_devhdl = MPTSAS_INVALID_DEVHDL;
13460 mptsas_update_hashtab(mpt);
13461 }
13462
13463 static void
13464 mptsas_config_all(dev_info_t *pdip)
13465 {
13466 dev_info_t *smpdip = NULL;
13467 mptsas_t *mpt = DIP2MPT(pdip);
13468 int phymask = 0;
13469 mptsas_phymask_t phy_mask;
13470 mptsas_target_t *ptgt = NULL;
13471 mptsas_smp_t *psmp;
13472
13473 /*
13474 * Get the phymask associated to the iport
13475 */
13476 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
13477 "phymask", 0);
13478
13479 /*
13480 * Enumerate RAID volumes here (phymask == 0).
13481 */
13482 if (phymask == 0) {
13483 mptsas_config_all_viport(pdip);
13484 return;
13485 }
13486
13487 mutex_enter(&mpt->m_mutex);
13488
13489 if (!mpt->m_done_traverse_dev || !mpt->m_done_traverse_smp) {
13490 mptsas_update_hashtab(mpt);
13491 }
13492
13493 psmp = (mptsas_smp_t *)mptsas_hash_traverse(&mpt->m_active->m_smptbl,
13494 MPTSAS_HASH_FIRST);
13495 while (psmp != NULL) {
13496 phy_mask = psmp->m_phymask;
13497 if (phy_mask == phymask) {
13498 smpdip = NULL;
13499 mutex_exit(&mpt->m_mutex);
13500 (void) mptsas_online_smp(pdip, psmp, &smpdip);
13501 mutex_enter(&mpt->m_mutex);
13502 }
13503 psmp = (mptsas_smp_t *)mptsas_hash_traverse(
13504 &mpt->m_active->m_smptbl, MPTSAS_HASH_NEXT);
13505 }
13506
13507 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
13508 MPTSAS_HASH_FIRST);
13509 while (ptgt != NULL) {
13510 phy_mask = ptgt->m_phymask;
13511 if (phy_mask == phymask) {
13512 mutex_exit(&mpt->m_mutex);
13513 (void) mptsas_config_target(pdip, ptgt);
13514 mutex_enter(&mpt->m_mutex);
13515 }
13516
13517 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
13518 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
13519 }
13520 mutex_exit(&mpt->m_mutex);
13521 }
13522
13523 static int
13524 mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt)
13525 {
13526 int rval = DDI_FAILURE;
13527 dev_info_t *tdip;
13528
13529 rval = mptsas_config_luns(pdip, ptgt);
13530 if (rval != DDI_SUCCESS) {
13531 /*
13532 * The return value means the SCMD_REPORT_LUNS
13533 * did not execute successfully. The target maybe
13534 * doesn't support such command.
13535 */
13536 rval = mptsas_probe_lun(pdip, 0, &tdip, ptgt);
13537 }
13538 return (rval);
13539 }
13540
13541 /*
13542 * Return fail if not all the childs/paths are freed.
13543 * if there is any path under the HBA, the return value will be always fail
13544 * because we didn't call mdi_pi_free for path
13545 */
13546 static int
13547 mptsas_offline_target(dev_info_t *pdip, char *name)
13548 {
13549 dev_info_t *child = NULL, *prechild = NULL;
13550 mdi_pathinfo_t *pip = NULL, *savepip = NULL;
13551 int tmp_rval, rval = DDI_SUCCESS;
13552 char *addr, *cp;
13553 size_t s;
13554 mptsas_t *mpt = DIP2MPT(pdip);
13555
13556 child = ddi_get_child(pdip);
13557 while (child) {
13558 addr = ddi_get_name_addr(child);
13559 prechild = child;
13560 child = ddi_get_next_sibling(child);
13561
13562 if (addr == NULL) {
13563 continue;
13564 }
13565 if ((cp = strchr(addr, ',')) == NULL) {
13566 continue;
13567 }
13568
13569 s = (uintptr_t)cp - (uintptr_t)addr;
13570
13571 if (strncmp(addr, name, s) != 0) {
13572 continue;
13573 }
13574
13575 tmp_rval = mptsas_offline_lun(pdip, prechild, NULL,
13576 NDI_DEVI_REMOVE);
13577 if (tmp_rval != DDI_SUCCESS) {
13578 rval = DDI_FAILURE;
13579 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
13580 prechild, MPTSAS_DEV_GONE) !=
13581 DDI_PROP_SUCCESS) {
13582 mptsas_log(mpt, CE_WARN, "mptsas driver "
13583 "unable to create property for "
13584 "SAS %s (MPTSAS_DEV_GONE)", addr);
13585 }
13586 }
13587 }
13588
13589 pip = mdi_get_next_client_path(pdip, NULL);
13590 while (pip) {
13591 addr = MDI_PI(pip)->pi_addr;
13592 savepip = pip;
13593 pip = mdi_get_next_client_path(pdip, pip);
13594 if (addr == NULL) {
13595 continue;
13596 }
13597
13598 if ((cp = strchr(addr, ',')) == NULL) {
13599 continue;
13600 }
13601
13602 s = (uintptr_t)cp - (uintptr_t)addr;
13603
13604 if (strncmp(addr, name, s) != 0) {
13605 continue;
13606 }
13607
13608 (void) mptsas_offline_lun(pdip, NULL, savepip,
13609 NDI_DEVI_REMOVE);
13610 /*
13611 * driver will not invoke mdi_pi_free, so path will not
13612 * be freed forever, return DDI_FAILURE.
13613 */
13614 rval = DDI_FAILURE;
13615 }
13616 return (rval);
13617 }
13618
13619 static int
13620 mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip,
13621 mdi_pathinfo_t *rpip, uint_t flags)
13622 {
13623 int rval = DDI_FAILURE;
13624 char *devname;
13625 dev_info_t *cdip, *parent;
13626
13627 if (rpip != NULL) {
13628 parent = scsi_vhci_dip;
13629 cdip = mdi_pi_get_client(rpip);
13630 } else if (rdip != NULL) {
13631 parent = pdip;
13632 cdip = rdip;
13633 } else {
13634 return (DDI_FAILURE);
13635 }
13636
13637 /*
13638 * Make sure node is attached otherwise
13639 * it won't have related cache nodes to
13640 * clean up. i_ddi_devi_attached is
13641 * similiar to i_ddi_node_state(cdip) >=
13642 * DS_ATTACHED.
13643 */
13644 if (i_ddi_devi_attached(cdip)) {
13645
13646 /* Get full devname */
13647 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP);
13648 (void) ddi_deviname(cdip, devname);
13649 /* Clean cache */
13650 (void) devfs_clean(parent, devname + 1,
13651 DV_CLEAN_FORCE);
13652 kmem_free(devname, MAXNAMELEN + 1);
13653 }
13654 if (rpip != NULL) {
13655 if (MDI_PI_IS_OFFLINE(rpip)) {
13656 rval = DDI_SUCCESS;
13657 } else {
13658 rval = mdi_pi_offline(rpip, 0);
13659 }
13660 } else {
13661 rval = ndi_devi_offline(cdip, flags);
13662 }
13663
13664 return (rval);
13665 }
13666
13667 static dev_info_t *
13668 mptsas_find_smp_child(dev_info_t *parent, char *str_wwn)
13669 {
13670 dev_info_t *child = NULL;
13671 char *smp_wwn = NULL;
13672
13673 child = ddi_get_child(parent);
13674 while (child) {
13675 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, child,
13676 DDI_PROP_DONTPASS, SMP_WWN, &smp_wwn)
13677 != DDI_SUCCESS) {
13678 child = ddi_get_next_sibling(child);
13679 continue;
13680 }
13681
13682 if (strcmp(smp_wwn, str_wwn) == 0) {
13683 ddi_prop_free(smp_wwn);
13684 break;
13685 }
13686 child = ddi_get_next_sibling(child);
13687 ddi_prop_free(smp_wwn);
13688 }
13689 return (child);
13690 }
13691
13692 static int
13693 mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, uint_t flags)
13694 {
13695 int rval = DDI_FAILURE;
13696 char *devname;
13697 char wwn_str[MPTSAS_WWN_STRLEN];
13698 dev_info_t *cdip;
13699
13700 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_sasaddr);
13701
13702 cdip = mptsas_find_smp_child(pdip, wwn_str);
13703
13704 if (cdip == NULL)
13705 return (DDI_SUCCESS);
13706
13707 /*
13708 * Make sure node is attached otherwise
13709 * it won't have related cache nodes to
13710 * clean up. i_ddi_devi_attached is
13711 * similiar to i_ddi_node_state(cdip) >=
13712 * DS_ATTACHED.
13713 */
13714 if (i_ddi_devi_attached(cdip)) {
13715
13716 /* Get full devname */
13717 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP);
13718 (void) ddi_deviname(cdip, devname);
13719 /* Clean cache */
13720 (void) devfs_clean(pdip, devname + 1,
13721 DV_CLEAN_FORCE);
13722 kmem_free(devname, MAXNAMELEN + 1);
13723 }
13724
13725 rval = ndi_devi_offline(cdip, flags);
13726
13727 return (rval);
13728 }
13729
13730 static dev_info_t *
13731 mptsas_find_child(dev_info_t *pdip, char *name)
13732 {
13733 dev_info_t *child = NULL;
13734 char *rname = NULL;
13735 int rval = DDI_FAILURE;
13736
13737 rname = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13738
13739 child = ddi_get_child(pdip);
13740 while (child) {
13741 rval = mptsas_name_child(child, rname, SCSI_MAXNAMELEN);
13742 if (rval != DDI_SUCCESS) {
13743 child = ddi_get_next_sibling(child);
13744 bzero(rname, SCSI_MAXNAMELEN);
13745 continue;
13746 }
13747
13748 if (strcmp(rname, name) == 0) {
13749 break;
13750 }
13751 child = ddi_get_next_sibling(child);
13752 bzero(rname, SCSI_MAXNAMELEN);
13753 }
13754
13755 kmem_free(rname, SCSI_MAXNAMELEN);
13756
13757 return (child);
13758 }
13759
13760
13761 static dev_info_t *
13762 mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, int lun)
13763 {
13764 dev_info_t *child = NULL;
13765 char *name = NULL;
13766 char *addr = NULL;
13767
13768 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13769 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13770 (void) sprintf(name, "%016"PRIx64, sasaddr);
13771 (void) sprintf(addr, "w%s,%x", name, lun);
13772 child = mptsas_find_child(pdip, addr);
13773 kmem_free(name, SCSI_MAXNAMELEN);
13774 kmem_free(addr, SCSI_MAXNAMELEN);
13775 return (child);
13776 }
13777
13778 static dev_info_t *
13779 mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy)
13780 {
13781 dev_info_t *child;
13782 char *addr;
13783
13784 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13785 (void) sprintf(addr, "p%x,0", phy);
13786 child = mptsas_find_child(pdip, addr);
13787 kmem_free(addr, SCSI_MAXNAMELEN);
13788 return (child);
13789 }
13790
13791 static mdi_pathinfo_t *
13792 mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy)
13793 {
13794 mdi_pathinfo_t *path;
13795 char *addr = NULL;
13796
13797 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13798 (void) sprintf(addr, "p%x,0", phy);
13799 path = mdi_pi_find(pdip, NULL, addr);
13800 kmem_free(addr, SCSI_MAXNAMELEN);
13801 return (path);
13802 }
13803
13804 static mdi_pathinfo_t *
13805 mptsas_find_path_addr(dev_info_t *parent, uint64_t sasaddr, int lun)
13806 {
13807 mdi_pathinfo_t *path;
13808 char *name = NULL;
13809 char *addr = NULL;
13810
13811 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13812 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13813 (void) sprintf(name, "%016"PRIx64, sasaddr);
13814 (void) sprintf(addr, "w%s,%x", name, lun);
13815 path = mdi_pi_find(parent, NULL, addr);
13816 kmem_free(name, SCSI_MAXNAMELEN);
13817 kmem_free(addr, SCSI_MAXNAMELEN);
13818
13819 return (path);
13820 }
13821
13822 static int
13823 mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq,
13824 dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun)
13825 {
13826 int i = 0;
13827 uchar_t *inq83 = NULL;
13828 int inq83_len1 = 0xFF;
13829 int inq83_len = 0;
13830 int rval = DDI_FAILURE;
13831 ddi_devid_t devid;
13832 char *guid = NULL;
13833 int target = ptgt->m_devhdl;
13834 mdi_pathinfo_t *pip = NULL;
13835 mptsas_t *mpt = DIP2MPT(pdip);
13836
13837 /*
13838 * For DVD/CD ROM and tape devices and optical
13839 * devices, we won't try to enumerate them under
13840 * scsi_vhci, so no need to try page83
13841 */
13842 if (sd_inq && (sd_inq->inq_dtype == DTYPE_RODIRECT ||
13843 sd_inq->inq_dtype == DTYPE_OPTICAL ||
13844 sd_inq->inq_dtype == DTYPE_ESI))
13845 goto create_lun;
13846
13847 /*
13848 * The LCA returns good SCSI status, but corrupt page 83 data the first
13849 * time it is queried. The solution is to keep trying to request page83
13850 * and verify the GUID is not (DDI_NOT_WELL_FORMED) in
13851 * mptsas_inq83_retry_timeout seconds. If the timeout expires, driver
13852 * give up to get VPD page at this stage and fail the enumeration.
13853 */
13854
13855 inq83 = kmem_zalloc(inq83_len1, KM_SLEEP);
13856
13857 for (i = 0; i < mptsas_inq83_retry_timeout; i++) {
13858 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83,
13859 inq83_len1, &inq83_len, 1);
13860 if (rval != 0) {
13861 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
13862 "0x83 for target:%x, lun:%x failed!", target, lun);
13863 if (mptsas_physical_bind_failed_page_83 != B_FALSE)
13864 goto create_lun;
13865 goto out;
13866 }
13867 /*
13868 * create DEVID from inquiry data
13869 */
13870 if ((rval = ddi_devid_scsi_encode(
13871 DEVID_SCSI_ENCODE_VERSION_LATEST, NULL, (uchar_t *)sd_inq,
13872 sizeof (struct scsi_inquiry), NULL, 0, inq83,
13873 (size_t)inq83_len, &devid)) == DDI_SUCCESS) {
13874 /*
13875 * extract GUID from DEVID
13876 */
13877 guid = ddi_devid_to_guid(devid);
13878
13879 /*
13880 * Do not enable MPXIO if the strlen(guid) is greater
13881 * than MPTSAS_MAX_GUID_LEN, this constrain would be
13882 * handled by framework later.
13883 */
13884 if (guid && (strlen(guid) > MPTSAS_MAX_GUID_LEN)) {
13885 ddi_devid_free_guid(guid);
13886 guid = NULL;
13887 if (mpt->m_mpxio_enable == TRUE) {
13888 mptsas_log(mpt, CE_NOTE, "!Target:%x, "
13889 "lun:%x doesn't have a valid GUID, "
13890 "multipathing for this drive is "
13891 "not enabled", target, lun);
13892 }
13893 }
13894
13895 /*
13896 * devid no longer needed
13897 */
13898 ddi_devid_free(devid);
13899 break;
13900 } else if (rval == DDI_NOT_WELL_FORMED) {
13901 /*
13902 * return value of ddi_devid_scsi_encode equal to
13903 * DDI_NOT_WELL_FORMED means DEVID_RETRY, it worth
13904 * to retry inquiry page 0x83 and get GUID.
13905 */
13906 NDBG20(("Not well formed devid, retry..."));
13907 delay(1 * drv_usectohz(1000000));
13908 continue;
13909 } else {
13910 mptsas_log(mpt, CE_WARN, "!Encode devid failed for "
13911 "path target:%x, lun:%x", target, lun);
13912 rval = DDI_FAILURE;
13913 goto create_lun;
13914 }
13915 }
13916
13917 if (i == mptsas_inq83_retry_timeout) {
13918 mptsas_log(mpt, CE_WARN, "!Repeated page83 requests timeout "
13919 "for path target:%x, lun:%x", target, lun);
13920 }
13921
13922 rval = DDI_FAILURE;
13923
13924 create_lun:
13925 if ((guid != NULL) && (mpt->m_mpxio_enable == TRUE)) {
13926 rval = mptsas_create_virt_lun(pdip, sd_inq, guid, lun_dip, &pip,
13927 ptgt, lun);
13928 }
13929 if (rval != DDI_SUCCESS) {
13930 rval = mptsas_create_phys_lun(pdip, sd_inq, guid, lun_dip,
13931 ptgt, lun);
13932
13933 }
13934 out:
13935 if (guid != NULL) {
13936 /*
13937 * guid no longer needed
13938 */
13939 ddi_devid_free_guid(guid);
13940 }
13941 if (inq83 != NULL)
13942 kmem_free(inq83, inq83_len1);
13943 return (rval);
13944 }
13945
13946 static int
13947 mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *inq, char *guid,
13948 dev_info_t **lun_dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, int lun)
13949 {
13950 int target;
13951 char *nodename = NULL;
13952 char **compatible = NULL;
13953 int ncompatible = 0;
13954 int mdi_rtn = MDI_FAILURE;
13955 int rval = DDI_FAILURE;
13956 char *old_guid = NULL;
13957 mptsas_t *mpt = DIP2MPT(pdip);
13958 char *lun_addr = NULL;
13959 char *wwn_str = NULL;
13960 char *attached_wwn_str = NULL;
13961 char *component = NULL;
13962 uint8_t phy = 0xFF;
13963 uint64_t sas_wwn;
13964 int64_t lun64 = 0;
13965 uint32_t devinfo;
13966 uint16_t dev_hdl;
13967 uint16_t pdev_hdl;
13968 uint64_t dev_sas_wwn;
13969 uint64_t pdev_sas_wwn;
13970 uint32_t pdev_info;
13971 uint8_t physport;
13972 uint8_t phy_id;
13973 uint32_t page_address;
13974 uint16_t bay_num, enclosure;
13975 char pdev_wwn_str[MPTSAS_WWN_STRLEN];
13976 uint32_t dev_info;
13977
13978 mutex_enter(&mpt->m_mutex);
13979 target = ptgt->m_devhdl;
13980 sas_wwn = ptgt->m_sas_wwn;
13981 devinfo = ptgt->m_deviceinfo;
13982 phy = ptgt->m_phynum;
13983 mutex_exit(&mpt->m_mutex);
13984
13985 if (sas_wwn) {
13986 *pip = mptsas_find_path_addr(pdip, sas_wwn, lun);
13987 } else {
13988 *pip = mptsas_find_path_phy(pdip, phy);
13989 }
13990
13991 if (*pip != NULL) {
13992 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip;
13993 ASSERT(*lun_dip != NULL);
13994 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, *lun_dip,
13995 (DDI_PROP_DONTPASS | DDI_PROP_NOTPROM),
13996 MDI_CLIENT_GUID_PROP, &old_guid) == DDI_SUCCESS) {
13997 if (strncmp(guid, old_guid, strlen(guid)) == 0) {
13998 /*
13999 * Same path back online again.
14000 */
14001 (void) ddi_prop_free(old_guid);
14002 if ((!MDI_PI_IS_ONLINE(*pip)) &&
14003 (!MDI_PI_IS_STANDBY(*pip)) &&
14004 (ptgt->m_tgt_unconfigured == 0)) {
14005 rval = mdi_pi_online(*pip, 0);
14006 mutex_enter(&mpt->m_mutex);
14007 ptgt->m_led_status = 0;
14008 (void) mptsas_flush_led_status(mpt,
14009 ptgt);
14010 mutex_exit(&mpt->m_mutex);
14011 } else {
14012 rval = DDI_SUCCESS;
14013 }
14014 if (rval != DDI_SUCCESS) {
14015 mptsas_log(mpt, CE_WARN, "path:target: "
14016 "%x, lun:%x online failed!", target,
14017 lun);
14018 *pip = NULL;
14019 *lun_dip = NULL;
14020 }
14021 return (rval);
14022 } else {
14023 /*
14024 * The GUID of the LUN has changed which maybe
14025 * because customer mapped another volume to the
14026 * same LUN.
14027 */
14028 mptsas_log(mpt, CE_WARN, "The GUID of the "
14029 "target:%x, lun:%x was changed, maybe "
14030 "because someone mapped another volume "
14031 "to the same LUN", target, lun);
14032 (void) ddi_prop_free(old_guid);
14033 if (!MDI_PI_IS_OFFLINE(*pip)) {
14034 rval = mdi_pi_offline(*pip, 0);
14035 if (rval != MDI_SUCCESS) {
14036 mptsas_log(mpt, CE_WARN, "path:"
14037 "target:%x, lun:%x offline "
14038 "failed!", target, lun);
14039 *pip = NULL;
14040 *lun_dip = NULL;
14041 return (DDI_FAILURE);
14042 }
14043 }
14044 if (mdi_pi_free(*pip, 0) != MDI_SUCCESS) {
14045 mptsas_log(mpt, CE_WARN, "path:target:"
14046 "%x, lun:%x free failed!", target,
14047 lun);
14048 *pip = NULL;
14049 *lun_dip = NULL;
14050 return (DDI_FAILURE);
14051 }
14052 }
14053 } else {
14054 mptsas_log(mpt, CE_WARN, "Can't get client-guid "
14055 "property for path:target:%x, lun:%x", target, lun);
14056 *pip = NULL;
14057 *lun_dip = NULL;
14058 return (DDI_FAILURE);
14059 }
14060 }
14061 scsi_hba_nodename_compatible_get(inq, NULL,
14062 inq->inq_dtype, NULL, &nodename, &compatible, &ncompatible);
14063
14064 /*
14065 * if nodename can't be determined then print a message and skip it
14066 */
14067 if (nodename == NULL) {
14068 mptsas_log(mpt, CE_WARN, "mptsas driver found no compatible "
14069 "driver for target%d lun %d dtype:0x%02x", target, lun,
14070 inq->inq_dtype);
14071 return (DDI_FAILURE);
14072 }
14073
14074 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP);
14075 /* The property is needed by MPAPI */
14076 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn);
14077
14078 lun_addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14079 if (guid) {
14080 (void) sprintf(lun_addr, "w%s,%x", wwn_str, lun);
14081 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
14082 } else {
14083 (void) sprintf(lun_addr, "p%x,%x", phy, lun);
14084 (void) sprintf(wwn_str, "p%x", phy);
14085 }
14086
14087 mdi_rtn = mdi_pi_alloc_compatible(pdip, nodename,
14088 guid, lun_addr, compatible, ncompatible,
14089 0, pip);
14090 if (mdi_rtn == MDI_SUCCESS) {
14091
14092 if (mdi_prop_update_string(*pip, MDI_GUID,
14093 guid) != DDI_SUCCESS) {
14094 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14095 "create prop for target %d lun %d (MDI_GUID)",
14096 target, lun);
14097 mdi_rtn = MDI_FAILURE;
14098 goto virt_create_done;
14099 }
14100
14101 if (mdi_prop_update_int(*pip, LUN_PROP,
14102 lun) != DDI_SUCCESS) {
14103 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14104 "create prop for target %d lun %d (LUN_PROP)",
14105 target, lun);
14106 mdi_rtn = MDI_FAILURE;
14107 goto virt_create_done;
14108 }
14109 lun64 = (int64_t)lun;
14110 if (mdi_prop_update_int64(*pip, LUN64_PROP,
14111 lun64) != DDI_SUCCESS) {
14112 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14113 "create prop for target %d (LUN64_PROP)",
14114 target);
14115 mdi_rtn = MDI_FAILURE;
14116 goto virt_create_done;
14117 }
14118 if (mdi_prop_update_string_array(*pip, "compatible",
14119 compatible, ncompatible) !=
14120 DDI_PROP_SUCCESS) {
14121 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14122 "create prop for target %d lun %d (COMPATIBLE)",
14123 target, lun);
14124 mdi_rtn = MDI_FAILURE;
14125 goto virt_create_done;
14126 }
14127 if (sas_wwn && (mdi_prop_update_string(*pip,
14128 SCSI_ADDR_PROP_TARGET_PORT, wwn_str) != DDI_PROP_SUCCESS)) {
14129 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14130 "create prop for target %d lun %d "
14131 "(target-port)", target, lun);
14132 mdi_rtn = MDI_FAILURE;
14133 goto virt_create_done;
14134 } else if ((sas_wwn == 0) && (mdi_prop_update_int(*pip,
14135 "sata-phy", phy) != DDI_PROP_SUCCESS)) {
14136 /*
14137 * Direct attached SATA device without DeviceName
14138 */
14139 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14140 "create prop for SAS target %d lun %d "
14141 "(sata-phy)", target, lun);
14142 mdi_rtn = MDI_FAILURE;
14143 goto virt_create_done;
14144 }
14145 mutex_enter(&mpt->m_mutex);
14146
14147 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14148 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
14149 (uint32_t)ptgt->m_devhdl;
14150 rval = mptsas_get_sas_device_page0(mpt, page_address,
14151 &dev_hdl, &dev_sas_wwn, &dev_info, &physport,
14152 &phy_id, &pdev_hdl, &bay_num, &enclosure);
14153 if (rval != DDI_SUCCESS) {
14154 mutex_exit(&mpt->m_mutex);
14155 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
14156 "parent device for handle %d", page_address);
14157 mdi_rtn = MDI_FAILURE;
14158 goto virt_create_done;
14159 }
14160
14161 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14162 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl;
14163 rval = mptsas_get_sas_device_page0(mpt, page_address,
14164 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport,
14165 &phy_id, &pdev_hdl, &bay_num, &enclosure);
14166 if (rval != DDI_SUCCESS) {
14167 mutex_exit(&mpt->m_mutex);
14168 mptsas_log(mpt, CE_WARN, "mptsas unable to get"
14169 "device info for handle %d", page_address);
14170 mdi_rtn = MDI_FAILURE;
14171 goto virt_create_done;
14172 }
14173
14174 mutex_exit(&mpt->m_mutex);
14175
14176 /*
14177 * If this device direct attached to the controller
14178 * set the attached-port to the base wwid
14179 */
14180 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
14181 != DEVINFO_DIRECT_ATTACHED) {
14182 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
14183 pdev_sas_wwn);
14184 } else {
14185 /*
14186 * Update the iport's attached-port to guid
14187 */
14188 if (sas_wwn == 0) {
14189 (void) sprintf(wwn_str, "p%x", phy);
14190 } else {
14191 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
14192 }
14193 if (ddi_prop_update_string(DDI_DEV_T_NONE,
14194 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
14195 DDI_PROP_SUCCESS) {
14196 mptsas_log(mpt, CE_WARN,
14197 "mptsas unable to create "
14198 "property for iport target-port"
14199 " %s (sas_wwn)",
14200 wwn_str);
14201 mdi_rtn = MDI_FAILURE;
14202 goto virt_create_done;
14203 }
14204
14205 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
14206 mpt->un.m_base_wwid);
14207 }
14208
14209 if (mdi_prop_update_string(*pip,
14210 SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) !=
14211 DDI_PROP_SUCCESS) {
14212 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14213 "property for iport attached-port %s (sas_wwn)",
14214 attached_wwn_str);
14215 mdi_rtn = MDI_FAILURE;
14216 goto virt_create_done;
14217 }
14218
14219
14220 if (inq->inq_dtype == 0) {
14221 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP);
14222 /*
14223 * set obp path for pathinfo
14224 */
14225 (void) snprintf(component, MAXPATHLEN,
14226 "disk@%s", lun_addr);
14227
14228 if (mdi_pi_pathname_obp_set(*pip, component) !=
14229 DDI_SUCCESS) {
14230 mptsas_log(mpt, CE_WARN, "mpt_sas driver "
14231 "unable to set obp-path for object %s",
14232 component);
14233 mdi_rtn = MDI_FAILURE;
14234 goto virt_create_done;
14235 }
14236 }
14237
14238 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip;
14239 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
14240 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
14241 if ((ndi_prop_update_int(DDI_DEV_T_NONE, *lun_dip,
14242 "pm-capable", 1)) !=
14243 DDI_PROP_SUCCESS) {
14244 mptsas_log(mpt, CE_WARN, "mptsas driver"
14245 "failed to create pm-capable "
14246 "property, target %d", target);
14247 mdi_rtn = MDI_FAILURE;
14248 goto virt_create_done;
14249 }
14250 }
14251 /*
14252 * Create the phy-num property
14253 */
14254 if (mdi_prop_update_int(*pip, "phy-num",
14255 ptgt->m_phynum) != DDI_SUCCESS) {
14256 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14257 "create phy-num property for target %d lun %d",
14258 target, lun);
14259 mdi_rtn = MDI_FAILURE;
14260 goto virt_create_done;
14261 }
14262 NDBG20(("new path:%s onlining,", MDI_PI(*pip)->pi_addr));
14263 mdi_rtn = mdi_pi_online(*pip, 0);
14264 if (mdi_rtn == MDI_SUCCESS) {
14265 mutex_enter(&mpt->m_mutex);
14266 ptgt->m_led_status = 0;
14267 (void) mptsas_flush_led_status(mpt, ptgt);
14268 mutex_exit(&mpt->m_mutex);
14269 }
14270 if (mdi_rtn == MDI_NOT_SUPPORTED) {
14271 mdi_rtn = MDI_FAILURE;
14272 }
14273 virt_create_done:
14274 if (*pip && mdi_rtn != MDI_SUCCESS) {
14275 (void) mdi_pi_free(*pip, 0);
14276 *pip = NULL;
14277 *lun_dip = NULL;
14278 }
14279 }
14280
14281 scsi_hba_nodename_compatible_free(nodename, compatible);
14282 if (lun_addr != NULL) {
14283 kmem_free(lun_addr, SCSI_MAXNAMELEN);
14284 }
14285 if (wwn_str != NULL) {
14286 kmem_free(wwn_str, MPTSAS_WWN_STRLEN);
14287 }
14288 if (component != NULL) {
14289 kmem_free(component, MAXPATHLEN);
14290 }
14291
14292 return ((mdi_rtn == MDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
14293 }
14294
14295 static int
14296 mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *inq,
14297 char *guid, dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun)
14298 {
14299 int target;
14300 int rval;
14301 int ndi_rtn = NDI_FAILURE;
14302 uint64_t be_sas_wwn;
14303 char *nodename = NULL;
14304 char **compatible = NULL;
14305 int ncompatible = 0;
14306 int instance = 0;
14307 mptsas_t *mpt = DIP2MPT(pdip);
14308 char *wwn_str = NULL;
14309 char *component = NULL;
14310 char *attached_wwn_str = NULL;
14311 uint8_t phy = 0xFF;
14312 uint64_t sas_wwn;
14313 uint32_t devinfo;
14314 uint16_t dev_hdl;
14315 uint16_t pdev_hdl;
14316 uint64_t pdev_sas_wwn;
14317 uint64_t dev_sas_wwn;
14318 uint32_t pdev_info;
14319 uint8_t physport;
14320 uint8_t phy_id;
14321 uint32_t page_address;
14322 uint16_t bay_num, enclosure;
14323 char pdev_wwn_str[MPTSAS_WWN_STRLEN];
14324 uint32_t dev_info;
14325 int64_t lun64 = 0;
14326
14327 mutex_enter(&mpt->m_mutex);
14328 target = ptgt->m_devhdl;
14329 sas_wwn = ptgt->m_sas_wwn;
14330 devinfo = ptgt->m_deviceinfo;
14331 phy = ptgt->m_phynum;
14332 mutex_exit(&mpt->m_mutex);
14333
14334 /*
14335 * generate compatible property with binding-set "mpt"
14336 */
14337 scsi_hba_nodename_compatible_get(inq, NULL, inq->inq_dtype, NULL,
14338 &nodename, &compatible, &ncompatible);
14339
14340 /*
14341 * if nodename can't be determined then print a message and skip it
14342 */
14343 if (nodename == NULL) {
14344 mptsas_log(mpt, CE_WARN, "mptsas found no compatible driver "
14345 "for target %d lun %d", target, lun);
14346 return (DDI_FAILURE);
14347 }
14348
14349 ndi_rtn = ndi_devi_alloc(pdip, nodename,
14350 DEVI_SID_NODEID, lun_dip);
14351
14352 /*
14353 * if lun alloc success, set props
14354 */
14355 if (ndi_rtn == NDI_SUCCESS) {
14356
14357 if (ndi_prop_update_int(DDI_DEV_T_NONE,
14358 *lun_dip, LUN_PROP, lun) !=
14359 DDI_PROP_SUCCESS) {
14360 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14361 "property for target %d lun %d (LUN_PROP)",
14362 target, lun);
14363 ndi_rtn = NDI_FAILURE;
14364 goto phys_create_done;
14365 }
14366
14367 lun64 = (int64_t)lun;
14368 if (ndi_prop_update_int64(DDI_DEV_T_NONE,
14369 *lun_dip, LUN64_PROP, lun64) !=
14370 DDI_PROP_SUCCESS) {
14371 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14372 "property for target %d lun64 %d (LUN64_PROP)",
14373 target, lun);
14374 ndi_rtn = NDI_FAILURE;
14375 goto phys_create_done;
14376 }
14377 if (ndi_prop_update_string_array(DDI_DEV_T_NONE,
14378 *lun_dip, "compatible", compatible, ncompatible)
14379 != DDI_PROP_SUCCESS) {
14380 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14381 "property for target %d lun %d (COMPATIBLE)",
14382 target, lun);
14383 ndi_rtn = NDI_FAILURE;
14384 goto phys_create_done;
14385 }
14386
14387 /*
14388 * We need the SAS WWN for non-multipath devices, so
14389 * we'll use the same property as that multipathing
14390 * devices need to present for MPAPI. If we don't have
14391 * a WWN (e.g. parallel SCSI), don't create the prop.
14392 */
14393 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP);
14394 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
14395 if (sas_wwn && ndi_prop_update_string(DDI_DEV_T_NONE,
14396 *lun_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str)
14397 != DDI_PROP_SUCCESS) {
14398 mptsas_log(mpt, CE_WARN, "mptsas unable to "
14399 "create property for SAS target %d lun %d "
14400 "(target-port)", target, lun);
14401 ndi_rtn = NDI_FAILURE;
14402 goto phys_create_done;
14403 }
14404
14405 be_sas_wwn = BE_64(sas_wwn);
14406 if (sas_wwn && ndi_prop_update_byte_array(
14407 DDI_DEV_T_NONE, *lun_dip, "port-wwn",
14408 (uchar_t *)&be_sas_wwn, 8) != DDI_PROP_SUCCESS) {
14409 mptsas_log(mpt, CE_WARN, "mptsas unable to "
14410 "create property for SAS target %d lun %d "
14411 "(port-wwn)", target, lun);
14412 ndi_rtn = NDI_FAILURE;
14413 goto phys_create_done;
14414 } else if ((sas_wwn == 0) && (ndi_prop_update_int(
14415 DDI_DEV_T_NONE, *lun_dip, "sata-phy", phy) !=
14416 DDI_PROP_SUCCESS)) {
14417 /*
14418 * Direct attached SATA device without DeviceName
14419 */
14420 mptsas_log(mpt, CE_WARN, "mptsas unable to "
14421 "create property for SAS target %d lun %d "
14422 "(sata-phy)", target, lun);
14423 ndi_rtn = NDI_FAILURE;
14424 goto phys_create_done;
14425 }
14426
14427 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
14428 *lun_dip, SAS_PROP) != DDI_PROP_SUCCESS) {
14429 mptsas_log(mpt, CE_WARN, "mptsas unable to"
14430 "create property for SAS target %d lun %d"
14431 " (SAS_PROP)", target, lun);
14432 ndi_rtn = NDI_FAILURE;
14433 goto phys_create_done;
14434 }
14435 if (guid && (ndi_prop_update_string(DDI_DEV_T_NONE,
14436 *lun_dip, NDI_GUID, guid) != DDI_SUCCESS)) {
14437 mptsas_log(mpt, CE_WARN, "mptsas unable "
14438 "to create guid property for target %d "
14439 "lun %d", target, lun);
14440 ndi_rtn = NDI_FAILURE;
14441 goto phys_create_done;
14442 }
14443
14444 /*
14445 * The following code is to set properties for SM-HBA support,
14446 * it doesn't apply to RAID volumes
14447 */
14448 if (ptgt->m_phymask == 0)
14449 goto phys_raid_lun;
14450
14451 mutex_enter(&mpt->m_mutex);
14452
14453 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14454 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
14455 (uint32_t)ptgt->m_devhdl;
14456 rval = mptsas_get_sas_device_page0(mpt, page_address,
14457 &dev_hdl, &dev_sas_wwn, &dev_info,
14458 &physport, &phy_id, &pdev_hdl,
14459 &bay_num, &enclosure);
14460 if (rval != DDI_SUCCESS) {
14461 mutex_exit(&mpt->m_mutex);
14462 mptsas_log(mpt, CE_WARN, "mptsas unable to get"
14463 "parent device for handle %d.", page_address);
14464 ndi_rtn = NDI_FAILURE;
14465 goto phys_create_done;
14466 }
14467
14468 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14469 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl;
14470 rval = mptsas_get_sas_device_page0(mpt, page_address,
14471 &dev_hdl, &pdev_sas_wwn, &pdev_info,
14472 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure);
14473 if (rval != DDI_SUCCESS) {
14474 mutex_exit(&mpt->m_mutex);
14475 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14476 "device for handle %d.", page_address);
14477 ndi_rtn = NDI_FAILURE;
14478 goto phys_create_done;
14479 }
14480
14481 mutex_exit(&mpt->m_mutex);
14482
14483 /*
14484 * If this device direct attached to the controller
14485 * set the attached-port to the base wwid
14486 */
14487 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
14488 != DEVINFO_DIRECT_ATTACHED) {
14489 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
14490 pdev_sas_wwn);
14491 } else {
14492 /*
14493 * Update the iport's attached-port to guid
14494 */
14495 if (sas_wwn == 0) {
14496 (void) sprintf(wwn_str, "p%x", phy);
14497 } else {
14498 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
14499 }
14500 if (ddi_prop_update_string(DDI_DEV_T_NONE,
14501 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
14502 DDI_PROP_SUCCESS) {
14503 mptsas_log(mpt, CE_WARN,
14504 "mptsas unable to create "
14505 "property for iport target-port"
14506 " %s (sas_wwn)",
14507 wwn_str);
14508 ndi_rtn = NDI_FAILURE;
14509 goto phys_create_done;
14510 }
14511
14512 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
14513 mpt->un.m_base_wwid);
14514 }
14515
14516 if (ndi_prop_update_string(DDI_DEV_T_NONE,
14517 *lun_dip, SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) !=
14518 DDI_PROP_SUCCESS) {
14519 mptsas_log(mpt, CE_WARN,
14520 "mptsas unable to create "
14521 "property for iport attached-port %s (sas_wwn)",
14522 attached_wwn_str);
14523 ndi_rtn = NDI_FAILURE;
14524 goto phys_create_done;
14525 }
14526
14527 if (IS_SATA_DEVICE(dev_info)) {
14528 if (ndi_prop_update_string(DDI_DEV_T_NONE,
14529 *lun_dip, MPTSAS_VARIANT, "sata") !=
14530 DDI_PROP_SUCCESS) {
14531 mptsas_log(mpt, CE_WARN,
14532 "mptsas unable to create "
14533 "property for device variant ");
14534 ndi_rtn = NDI_FAILURE;
14535 goto phys_create_done;
14536 }
14537 }
14538
14539 if (IS_ATAPI_DEVICE(dev_info)) {
14540 if (ndi_prop_update_string(DDI_DEV_T_NONE,
14541 *lun_dip, MPTSAS_VARIANT, "atapi") !=
14542 DDI_PROP_SUCCESS) {
14543 mptsas_log(mpt, CE_WARN,
14544 "mptsas unable to create "
14545 "property for device variant ");
14546 ndi_rtn = NDI_FAILURE;
14547 goto phys_create_done;
14548 }
14549 }
14550
14551 phys_raid_lun:
14552 /*
14553 * if this is a SAS controller, and the target is a SATA
14554 * drive, set the 'pm-capable' property for sd and if on
14555 * an OPL platform, also check if this is an ATAPI
14556 * device.
14557 */
14558 instance = ddi_get_instance(mpt->m_dip);
14559 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
14560 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
14561 NDBG2(("mptsas%d: creating pm-capable property, "
14562 "target %d", instance, target));
14563
14564 if ((ndi_prop_update_int(DDI_DEV_T_NONE,
14565 *lun_dip, "pm-capable", 1)) !=
14566 DDI_PROP_SUCCESS) {
14567 mptsas_log(mpt, CE_WARN, "mptsas "
14568 "failed to create pm-capable "
14569 "property, target %d", target);
14570 ndi_rtn = NDI_FAILURE;
14571 goto phys_create_done;
14572 }
14573
14574 }
14575
14576 if ((inq->inq_dtype == 0) || (inq->inq_dtype == 5)) {
14577 /*
14578 * add 'obp-path' properties for devinfo
14579 */
14580 bzero(wwn_str, sizeof (wwn_str));
14581 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn);
14582 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP);
14583 if (guid) {
14584 (void) snprintf(component, MAXPATHLEN,
14585 "disk@w%s,%x", wwn_str, lun);
14586 } else {
14587 (void) snprintf(component, MAXPATHLEN,
14588 "disk@p%x,%x", phy, lun);
14589 }
14590 if (ddi_pathname_obp_set(*lun_dip, component)
14591 != DDI_SUCCESS) {
14592 mptsas_log(mpt, CE_WARN, "mpt_sas driver "
14593 "unable to set obp-path for SAS "
14594 "object %s", component);
14595 ndi_rtn = NDI_FAILURE;
14596 goto phys_create_done;
14597 }
14598 }
14599 /*
14600 * Create the phy-num property for non-raid disk
14601 */
14602 if (ptgt->m_phymask != 0) {
14603 if (ndi_prop_update_int(DDI_DEV_T_NONE,
14604 *lun_dip, "phy-num", ptgt->m_phynum) !=
14605 DDI_PROP_SUCCESS) {
14606 mptsas_log(mpt, CE_WARN, "mptsas driver "
14607 "failed to create phy-num property for "
14608 "target %d", target);
14609 ndi_rtn = NDI_FAILURE;
14610 goto phys_create_done;
14611 }
14612 }
14613 phys_create_done:
14614 /*
14615 * If props were setup ok, online the lun
14616 */
14617 if (ndi_rtn == NDI_SUCCESS) {
14618 /*
14619 * Try to online the new node
14620 */
14621 ndi_rtn = ndi_devi_online(*lun_dip, NDI_ONLINE_ATTACH);
14622 }
14623 if (ndi_rtn == NDI_SUCCESS) {
14624 mutex_enter(&mpt->m_mutex);
14625 ptgt->m_led_status = 0;
14626 (void) mptsas_flush_led_status(mpt, ptgt);
14627 mutex_exit(&mpt->m_mutex);
14628 }
14629
14630 /*
14631 * If success set rtn flag, else unwire alloc'd lun
14632 */
14633 if (ndi_rtn != NDI_SUCCESS) {
14634 NDBG12(("mptsas driver unable to online "
14635 "target %d lun %d", target, lun));
14636 ndi_prop_remove_all(*lun_dip);
14637 (void) ndi_devi_free(*lun_dip);
14638 *lun_dip = NULL;
14639 }
14640 }
14641
14642 scsi_hba_nodename_compatible_free(nodename, compatible);
14643
14644 if (wwn_str != NULL) {
14645 kmem_free(wwn_str, MPTSAS_WWN_STRLEN);
14646 }
14647 if (component != NULL) {
14648 kmem_free(component, MAXPATHLEN);
14649 }
14650
14651
14652 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
14653 }
14654
14655 static int
14656 mptsas_probe_smp(dev_info_t *pdip, uint64_t wwn)
14657 {
14658 mptsas_t *mpt = DIP2MPT(pdip);
14659 struct smp_device smp_sd;
14660
14661 /* XXX An HBA driver should not be allocating an smp_device. */
14662 bzero(&smp_sd, sizeof (struct smp_device));
14663 smp_sd.smp_sd_address.smp_a_hba_tran = mpt->m_smptran;
14664 bcopy(&wwn, smp_sd.smp_sd_address.smp_a_wwn, SAS_WWN_BYTE_SIZE);
14665
14666 if (smp_probe(&smp_sd) != DDI_PROBE_SUCCESS)
14667 return (NDI_FAILURE);
14668 return (NDI_SUCCESS);
14669 }
14670
14671 static int
14672 mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, dev_info_t **smp_dip)
14673 {
14674 mptsas_t *mpt = DIP2MPT(pdip);
14675 mptsas_smp_t *psmp = NULL;
14676 int rval;
14677 int phymask;
14678
14679 /*
14680 * Get the physical port associated to the iport
14681 * PHYMASK TODO
14682 */
14683 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
14684 "phymask", 0);
14685 /*
14686 * Find the smp node in hash table with specified sas address and
14687 * physical port
14688 */
14689 psmp = mptsas_wwid_to_psmp(mpt, phymask, sas_wwn);
14690 if (psmp == NULL) {
14691 return (DDI_FAILURE);
14692 }
14693
14694 rval = mptsas_online_smp(pdip, psmp, smp_dip);
14695
14696 return (rval);
14697 }
14698
14699 static int
14700 mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
14701 dev_info_t **smp_dip)
14702 {
14703 char wwn_str[MPTSAS_WWN_STRLEN];
14704 char attached_wwn_str[MPTSAS_WWN_STRLEN];
14705 int ndi_rtn = NDI_FAILURE;
14706 int rval = 0;
14707 mptsas_smp_t dev_info;
14708 uint32_t page_address;
14709 mptsas_t *mpt = DIP2MPT(pdip);
14710 uint16_t dev_hdl;
14711 uint64_t sas_wwn;
14712 uint64_t smp_sas_wwn;
14713 uint8_t physport;
14714 uint8_t phy_id;
14715 uint16_t pdev_hdl;
14716 uint8_t numphys = 0;
14717 uint16_t i = 0;
14718 char phymask[MPTSAS_MAX_PHYS];
14719 char *iport = NULL;
14720 mptsas_phymask_t phy_mask = 0;
14721 uint16_t attached_devhdl;
14722 uint16_t bay_num, enclosure;
14723
14724 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_sasaddr);
14725
14726 /*
14727 * Probe smp device, prevent the node of removed device from being
14728 * configured succesfully
14729 */
14730 if (mptsas_probe_smp(pdip, smp_node->m_sasaddr) != NDI_SUCCESS) {
14731 return (DDI_FAILURE);
14732 }
14733
14734 if ((*smp_dip = mptsas_find_smp_child(pdip, wwn_str)) != NULL) {
14735 return (DDI_SUCCESS);
14736 }
14737
14738 ndi_rtn = ndi_devi_alloc(pdip, "smp", DEVI_SID_NODEID, smp_dip);
14739
14740 /*
14741 * if lun alloc success, set props
14742 */
14743 if (ndi_rtn == NDI_SUCCESS) {
14744 /*
14745 * Set the flavor of the child to be SMP flavored
14746 */
14747 ndi_flavor_set(*smp_dip, SCSA_FLAVOR_SMP);
14748
14749 if (ndi_prop_update_string(DDI_DEV_T_NONE,
14750 *smp_dip, SMP_WWN, wwn_str) !=
14751 DDI_PROP_SUCCESS) {
14752 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14753 "property for smp device %s (sas_wwn)",
14754 wwn_str);
14755 ndi_rtn = NDI_FAILURE;
14756 goto smp_create_done;
14757 }
14758 (void) sprintf(wwn_str, "w%"PRIx64, smp_node->m_sasaddr);
14759 if (ndi_prop_update_string(DDI_DEV_T_NONE,
14760 *smp_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str) !=
14761 DDI_PROP_SUCCESS) {
14762 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14763 "property for iport target-port %s (sas_wwn)",
14764 wwn_str);
14765 ndi_rtn = NDI_FAILURE;
14766 goto smp_create_done;
14767 }
14768
14769 mutex_enter(&mpt->m_mutex);
14770
14771 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL &
14772 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | smp_node->m_devhdl;
14773 rval = mptsas_get_sas_expander_page0(mpt, page_address,
14774 &dev_info);
14775 if (rval != DDI_SUCCESS) {
14776 mutex_exit(&mpt->m_mutex);
14777 mptsas_log(mpt, CE_WARN,
14778 "mptsas unable to get expander "
14779 "parent device info for %x", page_address);
14780 ndi_rtn = NDI_FAILURE;
14781 goto smp_create_done;
14782 }
14783
14784 smp_node->m_pdevhdl = dev_info.m_pdevhdl;
14785 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14786 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
14787 (uint32_t)dev_info.m_pdevhdl;
14788 rval = mptsas_get_sas_device_page0(mpt, page_address,
14789 &dev_hdl, &sas_wwn, &smp_node->m_pdevinfo,
14790 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure);
14791 if (rval != DDI_SUCCESS) {
14792 mutex_exit(&mpt->m_mutex);
14793 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
14794 "device info for %x", page_address);
14795 ndi_rtn = NDI_FAILURE;
14796 goto smp_create_done;
14797 }
14798
14799 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14800 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
14801 (uint32_t)dev_info.m_devhdl;
14802 rval = mptsas_get_sas_device_page0(mpt, page_address,
14803 &dev_hdl, &smp_sas_wwn, &smp_node->m_deviceinfo,
14804 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure);
14805 if (rval != DDI_SUCCESS) {
14806 mutex_exit(&mpt->m_mutex);
14807 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
14808 "device info for %x", page_address);
14809 ndi_rtn = NDI_FAILURE;
14810 goto smp_create_done;
14811 }
14812 mutex_exit(&mpt->m_mutex);
14813
14814 /*
14815 * If this smp direct attached to the controller
14816 * set the attached-port to the base wwid
14817 */
14818 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
14819 != DEVINFO_DIRECT_ATTACHED) {
14820 (void) sprintf(attached_wwn_str, "w%016"PRIx64,
14821 sas_wwn);
14822 } else {
14823 (void) sprintf(attached_wwn_str, "w%016"PRIx64,
14824 mpt->un.m_base_wwid);
14825 }
14826
14827 if (ndi_prop_update_string(DDI_DEV_T_NONE,
14828 *smp_dip, SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwn_str) !=
14829 DDI_PROP_SUCCESS) {
14830 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14831 "property for smp attached-port %s (sas_wwn)",
14832 attached_wwn_str);
14833 ndi_rtn = NDI_FAILURE;
14834 goto smp_create_done;
14835 }
14836
14837 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
14838 *smp_dip, SMP_PROP) != DDI_PROP_SUCCESS) {
14839 mptsas_log(mpt, CE_WARN, "mptsas unable to "
14840 "create property for SMP %s (SMP_PROP) ",
14841 wwn_str);
14842 ndi_rtn = NDI_FAILURE;
14843 goto smp_create_done;
14844 }
14845
14846 /*
14847 * check the smp to see whether it direct
14848 * attached to the controller
14849 */
14850 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
14851 != DEVINFO_DIRECT_ATTACHED) {
14852 goto smp_create_done;
14853 }
14854 numphys = ddi_prop_get_int(DDI_DEV_T_ANY, pdip,
14855 DDI_PROP_DONTPASS, MPTSAS_NUM_PHYS, -1);
14856 if (numphys > 0) {
14857 goto smp_create_done;
14858 }
14859 /*
14860 * this iport is an old iport, we need to
14861 * reconfig the props for it.
14862 */
14863 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip,
14864 MPTSAS_VIRTUAL_PORT, 0) !=
14865 DDI_PROP_SUCCESS) {
14866 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
14867 MPTSAS_VIRTUAL_PORT);
14868 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
14869 "prop update failed");
14870 goto smp_create_done;
14871 }
14872
14873 mutex_enter(&mpt->m_mutex);
14874 numphys = 0;
14875 iport = ddi_get_name_addr(pdip);
14876 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
14877 bzero(phymask, sizeof (phymask));
14878 (void) sprintf(phymask,
14879 "%x", mpt->m_phy_info[i].phy_mask);
14880 if (strcmp(phymask, iport) == 0) {
14881 phy_mask = mpt->m_phy_info[i].phy_mask;
14882 break;
14883 }
14884 }
14885
14886 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
14887 if ((phy_mask >> i) & 0x01) {
14888 numphys++;
14889 }
14890 }
14891 /*
14892 * Update PHY info for smhba
14893 */
14894 if (mptsas_smhba_phy_init(mpt)) {
14895 mutex_exit(&mpt->m_mutex);
14896 mptsas_log(mpt, CE_WARN, "mptsas phy update "
14897 "failed");
14898 goto smp_create_done;
14899 }
14900 mutex_exit(&mpt->m_mutex);
14901
14902 mptsas_smhba_set_phy_props(mpt, iport, pdip,
14903 numphys, &attached_devhdl);
14904
14905 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip,
14906 MPTSAS_NUM_PHYS, numphys) !=
14907 DDI_PROP_SUCCESS) {
14908 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
14909 MPTSAS_NUM_PHYS);
14910 mptsas_log(mpt, CE_WARN, "mptsas update "
14911 "num phys props failed");
14912 goto smp_create_done;
14913 }
14914 /*
14915 * Add parent's props for SMHBA support
14916 */
14917 if (ddi_prop_update_string(DDI_DEV_T_NONE, pdip,
14918 SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
14919 DDI_PROP_SUCCESS) {
14920 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
14921 SCSI_ADDR_PROP_ATTACHED_PORT);
14922 mptsas_log(mpt, CE_WARN, "mptsas update iport"
14923 "attached-port failed");
14924 goto smp_create_done;
14925 }
14926
14927 smp_create_done:
14928 /*
14929 * If props were setup ok, online the lun
14930 */
14931 if (ndi_rtn == NDI_SUCCESS) {
14932 /*
14933 * Try to online the new node
14934 */
14935 ndi_rtn = ndi_devi_online(*smp_dip, NDI_ONLINE_ATTACH);
14936 }
14937
14938 /*
14939 * If success set rtn flag, else unwire alloc'd lun
14940 */
14941 if (ndi_rtn != NDI_SUCCESS) {
14942 NDBG12(("mptsas unable to online "
14943 "SMP target %s", wwn_str));
14944 ndi_prop_remove_all(*smp_dip);
14945 (void) ndi_devi_free(*smp_dip);
14946 }
14947 }
14948
14949 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
14950 }
14951
14952 /* smp transport routine */
14953 static int mptsas_smp_start(struct smp_pkt *smp_pkt)
14954 {
14955 uint64_t wwn;
14956 Mpi2SmpPassthroughRequest_t req;
14957 Mpi2SmpPassthroughReply_t rep;
14958 uint32_t direction = 0;
14959 mptsas_t *mpt;
14960 int ret;
14961 uint64_t tmp64;
14962
14963 mpt = (mptsas_t *)smp_pkt->smp_pkt_address->
14964 smp_a_hba_tran->smp_tran_hba_private;
14965
14966 bcopy(smp_pkt->smp_pkt_address->smp_a_wwn, &wwn, SAS_WWN_BYTE_SIZE);
14967 /*
14968 * Need to compose a SMP request message
14969 * and call mptsas_do_passthru() function
14970 */
14971 bzero(&req, sizeof (req));
14972 bzero(&rep, sizeof (rep));
14973 req.PassthroughFlags = 0;
14974 req.PhysicalPort = 0xff;
14975 req.ChainOffset = 0;
14976 req.Function = MPI2_FUNCTION_SMP_PASSTHROUGH;
14977
14978 if ((smp_pkt->smp_pkt_reqsize & 0xffff0000ul) != 0) {
14979 smp_pkt->smp_pkt_reason = ERANGE;
14980 return (DDI_FAILURE);
14981 }
14982 req.RequestDataLength = LE_16((uint16_t)(smp_pkt->smp_pkt_reqsize - 4));
14983
14984 req.MsgFlags = 0;
14985 tmp64 = LE_64(wwn);
14986 bcopy(&tmp64, &req.SASAddress, SAS_WWN_BYTE_SIZE);
14987 if (smp_pkt->smp_pkt_rspsize > 0) {
14988 direction |= MPTSAS_PASS_THRU_DIRECTION_READ;
14989 }
14990 if (smp_pkt->smp_pkt_reqsize > 0) {
14991 direction |= MPTSAS_PASS_THRU_DIRECTION_WRITE;
14992 }
14993
14994 mutex_enter(&mpt->m_mutex);
14995 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep,
14996 (uint8_t *)smp_pkt->smp_pkt_rsp,
14997 offsetof(Mpi2SmpPassthroughRequest_t, SGL), sizeof (rep),
14998 smp_pkt->smp_pkt_rspsize - 4, direction,
14999 (uint8_t *)smp_pkt->smp_pkt_req, smp_pkt->smp_pkt_reqsize - 4,
15000 smp_pkt->smp_pkt_timeout, FKIOCTL);
15001 mutex_exit(&mpt->m_mutex);
15002 if (ret != 0) {
15003 cmn_err(CE_WARN, "smp_start do passthru error %d", ret);
15004 smp_pkt->smp_pkt_reason = (uchar_t)(ret);
15005 return (DDI_FAILURE);
15006 }
15007 /* do passthrough success, check the smp status */
15008 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
15009 switch (LE_16(rep.IOCStatus)) {
15010 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
15011 smp_pkt->smp_pkt_reason = ENODEV;
15012 break;
15013 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
15014 smp_pkt->smp_pkt_reason = EOVERFLOW;
15015 break;
15016 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
15017 smp_pkt->smp_pkt_reason = EIO;
15018 break;
15019 default:
15020 mptsas_log(mpt, CE_NOTE, "smp_start: get unknown ioc"
15021 "status:%x", LE_16(rep.IOCStatus));
15022 smp_pkt->smp_pkt_reason = EIO;
15023 break;
15024 }
15025 return (DDI_FAILURE);
15026 }
15027 if (rep.SASStatus != MPI2_SASSTATUS_SUCCESS) {
15028 mptsas_log(mpt, CE_NOTE, "smp_start: get error SAS status:%x",
15029 rep.SASStatus);
15030 smp_pkt->smp_pkt_reason = EIO;
15031 return (DDI_FAILURE);
15032 }
15033
15034 return (DDI_SUCCESS);
15035 }
15036
15037 /*
15038 * If we didn't get a match, we need to get sas page0 for each device, and
15039 * untill we get a match. If failed, return NULL
15040 */
15041 static mptsas_target_t *
15042 mptsas_phy_to_tgt(mptsas_t *mpt, int phymask, uint8_t phy)
15043 {
15044 int i, j = 0;
15045 int rval = 0;
15046 uint16_t cur_handle;
15047 uint32_t page_address;
15048 mptsas_target_t *ptgt = NULL;
15049
15050 /*
15051 * PHY named device must be direct attached and attaches to
15052 * narrow port, if the iport is not parent of the device which
15053 * we are looking for.
15054 */
15055 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
15056 if ((1 << i) & phymask)
15057 j++;
15058 }
15059
15060 if (j > 1)
15061 return (NULL);
15062
15063 /*
15064 * Must be a narrow port and single device attached to the narrow port
15065 * So the physical port num of device which is equal to the iport's
15066 * port num is the device what we are looking for.
15067 */
15068
15069 if (mpt->m_phy_info[phy].phy_mask != phymask)
15070 return (NULL);
15071
15072 mutex_enter(&mpt->m_mutex);
15073
15074 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
15075 MPTSAS_HASH_FIRST);
15076 while (ptgt != NULL) {
15077 if ((ptgt->m_sas_wwn == 0) && (ptgt->m_phynum == phy)) {
15078 mutex_exit(&mpt->m_mutex);
15079 return (ptgt);
15080 }
15081
15082 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
15083 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
15084 }
15085
15086 if (mpt->m_done_traverse_dev) {
15087 mutex_exit(&mpt->m_mutex);
15088 return (NULL);
15089 }
15090
15091 /* If didn't get a match, come here */
15092 cur_handle = mpt->m_dev_handle;
15093 for (; ; ) {
15094 ptgt = NULL;
15095 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
15096 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)cur_handle;
15097 rval = mptsas_get_target_device_info(mpt, page_address,
15098 &cur_handle, &ptgt);
15099 if ((rval == DEV_INFO_FAIL_PAGE0) ||
15100 (rval == DEV_INFO_FAIL_ALLOC)) {
15101 break;
15102 }
15103 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) ||
15104 (rval == DEV_INFO_PHYS_DISK)) {
15105 continue;
15106 }
15107 mpt->m_dev_handle = cur_handle;
15108
15109 if ((ptgt->m_sas_wwn == 0) && (ptgt->m_phynum == phy)) {
15110 break;
15111 }
15112 }
15113
15114 mutex_exit(&mpt->m_mutex);
15115 return (ptgt);
15116 }
15117
15118 /*
15119 * The ptgt->m_sas_wwn contains the wwid for each disk.
15120 * For Raid volumes, we need to check m_raidvol[x].m_raidwwid
15121 * If we didn't get a match, we need to get sas page0 for each device, and
15122 * untill we get a match
15123 * If failed, return NULL
15124 */
15125 static mptsas_target_t *
15126 mptsas_wwid_to_ptgt(mptsas_t *mpt, int phymask, uint64_t wwid)
15127 {
15128 int rval = 0;
15129 uint16_t cur_handle;
15130 uint32_t page_address;
15131 mptsas_target_t *tmp_tgt = NULL;
15132
15133 mutex_enter(&mpt->m_mutex);
15134 tmp_tgt = (struct mptsas_target *)mptsas_hash_search(
15135 &mpt->m_active->m_tgttbl, wwid, phymask);
15136 if (tmp_tgt != NULL) {
15137 mutex_exit(&mpt->m_mutex);
15138 return (tmp_tgt);
15139 }
15140
15141 if (phymask == 0) {
15142 /*
15143 * It's IR volume
15144 */
15145 rval = mptsas_get_raid_info(mpt);
15146 if (rval) {
15147 tmp_tgt = (struct mptsas_target *)mptsas_hash_search(
15148 &mpt->m_active->m_tgttbl, wwid, phymask);
15149 }
15150 mutex_exit(&mpt->m_mutex);
15151 return (tmp_tgt);
15152 }
15153
15154 if (mpt->m_done_traverse_dev) {
15155 mutex_exit(&mpt->m_mutex);
15156 return (NULL);
15157 }
15158
15159 /* If didn't get a match, come here */
15160 cur_handle = mpt->m_dev_handle;
15161 for (; ; ) {
15162 tmp_tgt = NULL;
15163 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
15164 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | cur_handle;
15165 rval = mptsas_get_target_device_info(mpt, page_address,
15166 &cur_handle, &tmp_tgt);
15167 if ((rval == DEV_INFO_FAIL_PAGE0) ||
15168 (rval == DEV_INFO_FAIL_ALLOC)) {
15169 tmp_tgt = NULL;
15170 break;
15171 }
15172 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) ||
15173 (rval == DEV_INFO_PHYS_DISK)) {
15174 continue;
15175 }
15176 mpt->m_dev_handle = cur_handle;
15177 if ((tmp_tgt->m_sas_wwn) && (tmp_tgt->m_sas_wwn == wwid) &&
15178 (tmp_tgt->m_phymask == phymask)) {
15179 break;
15180 }
15181 }
15182
15183 mutex_exit(&mpt->m_mutex);
15184 return (tmp_tgt);
15185 }
15186
15187 static mptsas_smp_t *
15188 mptsas_wwid_to_psmp(mptsas_t *mpt, int phymask, uint64_t wwid)
15189 {
15190 int rval = 0;
15191 uint16_t cur_handle;
15192 uint32_t page_address;
15193 mptsas_smp_t smp_node, *psmp = NULL;
15194
15195 mutex_enter(&mpt->m_mutex);
15196 psmp = (struct mptsas_smp *)mptsas_hash_search(&mpt->m_active->m_smptbl,
15197 wwid, phymask);
15198 if (psmp != NULL) {
15199 mutex_exit(&mpt->m_mutex);
15200 return (psmp);
15201 }
15202
15203 if (mpt->m_done_traverse_smp) {
15204 mutex_exit(&mpt->m_mutex);
15205 return (NULL);
15206 }
15207
15208 /* If didn't get a match, come here */
15209 cur_handle = mpt->m_smp_devhdl;
15210 for (; ; ) {
15211 psmp = NULL;
15212 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL &
15213 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)cur_handle;
15214 rval = mptsas_get_sas_expander_page0(mpt, page_address,
15215 &smp_node);
15216 if (rval != DDI_SUCCESS) {
15217 break;
15218 }
15219 mpt->m_smp_devhdl = cur_handle = smp_node.m_devhdl;
15220 psmp = mptsas_smp_alloc(&mpt->m_active->m_smptbl, &smp_node);
15221 ASSERT(psmp);
15222 if ((psmp->m_sasaddr) && (psmp->m_sasaddr == wwid) &&
15223 (psmp->m_phymask == phymask)) {
15224 break;
15225 }
15226 }
15227
15228 mutex_exit(&mpt->m_mutex);
15229 return (psmp);
15230 }
15231
15232 /* helper functions using hash */
15233
15234 /*
15235 * Can't have duplicate entries for same devhdl,
15236 * if there are invalid entries, the devhdl should be set to 0xffff
15237 */
15238 static void *
15239 mptsas_search_by_devhdl(mptsas_hash_table_t *hashtab, uint16_t devhdl)
15240 {
15241 mptsas_hash_data_t *data;
15242
15243 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_FIRST);
15244 while (data != NULL) {
15245 if (data->devhdl == devhdl) {
15246 break;
15247 }
15248 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_NEXT);
15249 }
15250 return (data);
15251 }
15252
15253 mptsas_target_t *
15254 mptsas_tgt_alloc(mptsas_hash_table_t *hashtab, uint16_t devhdl, uint64_t wwid,
15255 uint32_t devinfo, mptsas_phymask_t phymask, uint8_t phynum)
15256 {
15257 mptsas_target_t *tmp_tgt = NULL;
15258
15259 tmp_tgt = mptsas_hash_search(hashtab, wwid, phymask);
15260 if (tmp_tgt != NULL) {
15261 NDBG20(("Hash item already exist"));
15262 tmp_tgt->m_deviceinfo = devinfo;
15263 tmp_tgt->m_devhdl = devhdl;
15264 return (tmp_tgt);
15265 }
15266 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target), KM_SLEEP);
15267 if (tmp_tgt == NULL) {
15268 cmn_err(CE_WARN, "Fatal, allocated tgt failed");
15269 return (NULL);
15270 }
15271 tmp_tgt->m_devhdl = devhdl;
15272 tmp_tgt->m_sas_wwn = wwid;
15273 tmp_tgt->m_deviceinfo = devinfo;
15274 tmp_tgt->m_phymask = phymask;
15275 tmp_tgt->m_phynum = phynum;
15276 /* Initialized the tgt structure */
15277 tmp_tgt->m_qfull_retries = QFULL_RETRIES;
15278 tmp_tgt->m_qfull_retry_interval =
15279 drv_usectohz(QFULL_RETRY_INTERVAL * 1000);
15280 tmp_tgt->m_t_throttle = MAX_THROTTLE;
15281
15282 mptsas_hash_add(hashtab, tmp_tgt);
15283
15284 return (tmp_tgt);
15285 }
15286
15287 static void
15288 mptsas_tgt_free(mptsas_hash_table_t *hashtab, uint64_t wwid,
15289 mptsas_phymask_t phymask)
15290 {
15291 mptsas_target_t *tmp_tgt;
15292 tmp_tgt = mptsas_hash_rem(hashtab, wwid, phymask);
15293 if (tmp_tgt == NULL) {
15294 cmn_err(CE_WARN, "Tgt not found, nothing to free");
15295 } else {
15296 kmem_free(tmp_tgt, sizeof (struct mptsas_target));
15297 }
15298 }
15299
15300 /*
15301 * Return the entry in the hash table
15302 */
15303 static mptsas_smp_t *
15304 mptsas_smp_alloc(mptsas_hash_table_t *hashtab, mptsas_smp_t *data)
15305 {
15306 uint64_t key1 = data->m_sasaddr;
15307 mptsas_phymask_t key2 = data->m_phymask;
15308 mptsas_smp_t *ret_data;
15309
15310 ret_data = mptsas_hash_search(hashtab, key1, key2);
15311 if (ret_data != NULL) {
15312 bcopy(data, ret_data, sizeof (mptsas_smp_t));
15313 return (ret_data);
15314 }
15315
15316 ret_data = kmem_alloc(sizeof (mptsas_smp_t), KM_SLEEP);
15317 bcopy(data, ret_data, sizeof (mptsas_smp_t));
15318 mptsas_hash_add(hashtab, ret_data);
15319 return (ret_data);
15320 }
15321
15322 static void
15323 mptsas_smp_free(mptsas_hash_table_t *hashtab, uint64_t wwid,
15324 mptsas_phymask_t phymask)
15325 {
15326 mptsas_smp_t *tmp_smp;
15327 tmp_smp = mptsas_hash_rem(hashtab, wwid, phymask);
15328 if (tmp_smp == NULL) {
15329 cmn_err(CE_WARN, "Smp element not found, nothing to free");
15330 } else {
15331 kmem_free(tmp_smp, sizeof (struct mptsas_smp));
15332 }
15333 }
15334
15335 /*
15336 * Hash operation functions
15337 * key1 is the sas_wwn, key2 is the phymask
15338 */
15339 static void
15340 mptsas_hash_init(mptsas_hash_table_t *hashtab)
15341 {
15342 if (hashtab == NULL) {
15343 return;
15344 }
15345 bzero(hashtab->head, sizeof (mptsas_hash_node_t) *
15346 MPTSAS_HASH_ARRAY_SIZE);
15347 hashtab->cur = NULL;
15348 hashtab->line = 0;
15349 }
15350
15351 static void
15352 mptsas_hash_uninit(mptsas_hash_table_t *hashtab, size_t datalen)
15353 {
15354 uint16_t line = 0;
15355 mptsas_hash_node_t *cur = NULL, *last = NULL;
15356
15357 if (hashtab == NULL) {
15358 return;
15359 }
15360 for (line = 0; line < MPTSAS_HASH_ARRAY_SIZE; line++) {
15361 cur = hashtab->head[line];
15362 while (cur != NULL) {
15363 last = cur;
15364 cur = cur->next;
15365 kmem_free(last->data, datalen);
15366 kmem_free(last, sizeof (mptsas_hash_node_t));
15367 }
15368 }
15369 }
15370
15371 /*
15372 * You must guarantee the element doesn't exist in the hash table
15373 * before you call mptsas_hash_add()
15374 */
15375 static void
15376 mptsas_hash_add(mptsas_hash_table_t *hashtab, void *data)
15377 {
15378 uint64_t key1 = ((mptsas_hash_data_t *)data)->key1;
15379 mptsas_phymask_t key2 = ((mptsas_hash_data_t *)data)->key2;
15380 mptsas_hash_node_t **head = NULL;
15381 mptsas_hash_node_t *node = NULL;
15382
15383 if (hashtab == NULL) {
15384 return;
15385 }
15386 ASSERT(mptsas_hash_search(hashtab, key1, key2) == NULL);
15387 node = kmem_zalloc(sizeof (mptsas_hash_node_t), KM_NOSLEEP);
15388 node->data = data;
15389
15390 head = &(hashtab->head[key1 % MPTSAS_HASH_ARRAY_SIZE]);
15391 if (*head == NULL) {
15392 *head = node;
15393 } else {
15394 node->next = *head;
15395 *head = node;
15396 }
15397 }
15398
15399 static void *
15400 mptsas_hash_rem(mptsas_hash_table_t *hashtab, uint64_t key1,
15401 mptsas_phymask_t key2)
15402 {
15403 mptsas_hash_node_t **head = NULL;
15404 mptsas_hash_node_t *last = NULL, *cur = NULL;
15405 mptsas_hash_data_t *data;
15406 if (hashtab == NULL) {
15407 return (NULL);
15408 }
15409 head = &(hashtab->head[key1 % MPTSAS_HASH_ARRAY_SIZE]);
15410 cur = *head;
15411 while (cur != NULL) {
15412 data = cur->data;
15413 if ((data->key1 == key1) && (data->key2 == key2)) {
15414 if (last == NULL) {
15415 (*head) = cur->next;
15416 } else {
15417 last->next = cur->next;
15418 }
15419 kmem_free(cur, sizeof (mptsas_hash_node_t));
15420 return (data);
15421 } else {
15422 last = cur;
15423 cur = cur->next;
15424 }
15425 }
15426 return (NULL);
15427 }
15428
15429 static void *
15430 mptsas_hash_search(mptsas_hash_table_t *hashtab, uint64_t key1,
15431 mptsas_phymask_t key2)
15432 {
15433 mptsas_hash_node_t *cur = NULL;
15434 mptsas_hash_data_t *data;
15435 if (hashtab == NULL) {
15436 return (NULL);
15437 }
15438 cur = hashtab->head[key1 % MPTSAS_HASH_ARRAY_SIZE];
15439 while (cur != NULL) {
15440 data = cur->data;
15441 if ((data->key1 == key1) && (data->key2 == key2)) {
15442 return (data);
15443 } else {
15444 cur = cur->next;
15445 }
15446 }
15447 return (NULL);
15448 }
15449
15450 static void *
15451 mptsas_hash_traverse(mptsas_hash_table_t *hashtab, int pos)
15452 {
15453 mptsas_hash_node_t *this = NULL;
15454
15455 if (hashtab == NULL) {
15456 return (NULL);
15457 }
15458
15459 if (pos == MPTSAS_HASH_FIRST) {
15460 hashtab->line = 0;
15461 hashtab->cur = NULL;
15462 this = hashtab->head[0];
15463 } else {
15464 if (hashtab->cur == NULL) {
15465 return (NULL);
15466 } else {
15467 this = hashtab->cur->next;
15468 }
15469 }
15470
15471 while (this == NULL) {
15472 hashtab->line++;
15473 if (hashtab->line >= MPTSAS_HASH_ARRAY_SIZE) {
15474 /* the traverse reaches the end */
15475 hashtab->cur = NULL;
15476 return (NULL);
15477 } else {
15478 this = hashtab->head[hashtab->line];
15479 }
15480 }
15481 hashtab->cur = this;
15482 return (this->data);
15483 }
15484
15485 /*
15486 * Functions for SGPIO LED support
15487 */
15488 static dev_info_t *
15489 mptsas_get_dip_from_dev(dev_t dev, mptsas_phymask_t *phymask)
15490 {
15491 dev_info_t *dip;
15492 int prop;
15493 dip = e_ddi_hold_devi_by_dev(dev, 0);
15494 if (dip == NULL)
15495 return (dip);
15496 prop = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
15497 "phymask", 0);
15498 *phymask = (mptsas_phymask_t)prop;
15499 ddi_release_devi(dip);
15500 return (dip);
15501 }
15502 static mptsas_target_t *
15503 mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr, mptsas_phymask_t phymask)
15504 {
15505 uint8_t phynum;
15506 uint64_t wwn;
15507 int lun;
15508 mptsas_target_t *ptgt = NULL;
15509
15510 if (mptsas_parse_address(addr, &wwn, &phynum, &lun) != DDI_SUCCESS) {
15511 return (NULL);
15512 }
15513 if (addr[0] == 'w') {
15514 ptgt = mptsas_wwid_to_ptgt(mpt, (int)phymask, wwn);
15515 } else {
15516 ptgt = mptsas_phy_to_tgt(mpt, (int)phymask, phynum);
15517 }
15518 return (ptgt);
15519 }
15520
15521 static int
15522 mptsas_flush_led_status(mptsas_t *mpt, mptsas_target_t *ptgt)
15523 {
15524 uint32_t slotstatus = 0;
15525
15526 /* Build an MPI2 Slot Status based on our view of the world */
15527 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_IDENT - 1)))
15528 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST;
15529 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_FAIL - 1)))
15530 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT;
15531 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1)))
15532 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE;
15533
15534 /* Write it to the controller */
15535 NDBG14(("mptsas_ioctl: set LED status %x for slot %x",
15536 slotstatus, ptgt->m_slot_num));
15537 return (mptsas_send_sep(mpt, ptgt, &slotstatus,
15538 MPI2_SEP_REQ_ACTION_WRITE_STATUS));
15539 }
15540
15541 /*
15542 * send sep request, use enclosure/slot addressing
15543 */
15544 static int
15545 mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt,
15546 uint32_t *status, uint8_t act)
15547 {
15548 Mpi2SepRequest_t req;
15549 Mpi2SepReply_t rep;
15550 int ret;
15551
15552 ASSERT(mutex_owned(&mpt->m_mutex));
15553
15554 /*
15555 * We only support SEP control of directly-attached targets, in which
15556 * case the "SEP" we're talking to is a virtual one contained within
15557 * the HBA itself. This is necessary because DA targets typically have
15558 * no other mechanism for LED control. Targets for which a separate
15559 * enclosure service processor exists should be controlled via ses(7d)
15560 * or sgen(7d). Furthermore, since such requests can time out, they
15561 * should be made in user context rather than in response to
15562 * asynchronous fabric changes.
15563 *
15564 * In addition, we do not support this operation for RAID volumes,
15565 * since there is no slot associated with them.
15566 */
15567 if (!(ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) ||
15568 ptgt->m_phymask == 0) {
15569 return (ENOTTY);
15570 }
15571
15572 bzero(&req, sizeof (req));
15573 bzero(&rep, sizeof (rep));
15574
15575 req.Function = MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR;
15576 req.Action = act;
15577 req.Flags = MPI2_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS;
15578 req.EnclosureHandle = LE_16(ptgt->m_enclosure);
15579 req.Slot = LE_16(ptgt->m_slot_num);
15580 if (act == MPI2_SEP_REQ_ACTION_WRITE_STATUS) {
15581 req.SlotStatus = LE_32(*status);
15582 }
15583 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL,
15584 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL);
15585 if (ret != 0) {
15586 mptsas_log(mpt, CE_NOTE, "mptsas_send_sep: passthru SEP "
15587 "Processor Request message error %d", ret);
15588 return (ret);
15589 }
15590 /* do passthrough success, check the ioc status */
15591 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
15592 mptsas_log(mpt, CE_NOTE, "send_sep act %x: ioc "
15593 "status:%x loginfo %x", act, LE_16(rep.IOCStatus),
15594 LE_32(rep.IOCLogInfo));
15595 switch (LE_16(rep.IOCStatus) & MPI2_IOCSTATUS_MASK) {
15596 case MPI2_IOCSTATUS_INVALID_FUNCTION:
15597 case MPI2_IOCSTATUS_INVALID_VPID:
15598 case MPI2_IOCSTATUS_INVALID_FIELD:
15599 case MPI2_IOCSTATUS_INVALID_STATE:
15600 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
15601 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
15602 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
15603 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
15604 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
15605 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
15606 return (EINVAL);
15607 case MPI2_IOCSTATUS_BUSY:
15608 return (EBUSY);
15609 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
15610 return (EAGAIN);
15611 case MPI2_IOCSTATUS_INVALID_SGL:
15612 case MPI2_IOCSTATUS_INTERNAL_ERROR:
15613 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
15614 default:
15615 return (EIO);
15616 }
15617 }
15618 if (act != MPI2_SEP_REQ_ACTION_WRITE_STATUS) {
15619 *status = LE_32(rep.SlotStatus);
15620 }
15621
15622 return (0);
15623 }
15624
15625 int
15626 mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr,
15627 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp,
15628 uint32_t alloc_size, ddi_dma_cookie_t *cookiep)
15629 {
15630 ddi_dma_cookie_t new_cookie;
15631 size_t alloc_len;
15632 uint_t ncookie;
15633
15634 if (cookiep == NULL)
15635 cookiep = &new_cookie;
15636
15637 if (ddi_dma_alloc_handle(mpt->m_dip, &dma_attr, DDI_DMA_SLEEP,
15638 NULL, dma_hdp) != DDI_SUCCESS) {
15639 dma_hdp = NULL;
15640 return (FALSE);
15641 }
15642
15643 if (ddi_dma_mem_alloc(*dma_hdp, alloc_size, &mpt->m_dev_acc_attr,
15644 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, dma_memp, &alloc_len,
15645 acc_hdp) != DDI_SUCCESS) {
15646 ddi_dma_free_handle(dma_hdp);
15647 dma_hdp = NULL;
15648 return (FALSE);
15649 }
15650
15651 if (ddi_dma_addr_bind_handle(*dma_hdp, NULL, *dma_memp, alloc_len,
15652 (DDI_DMA_RDWR | DDI_DMA_CONSISTENT), DDI_DMA_SLEEP, NULL,
15653 cookiep, &ncookie) != DDI_DMA_MAPPED) {
15654 (void) ddi_dma_mem_free(acc_hdp);
15655 ddi_dma_free_handle(dma_hdp);
15656 dma_hdp = NULL;
15657 return (FALSE);
15658 }
15659
15660 return (TRUE);
15661 }
15662
15663 void
15664 mptsas_dma_addr_destroy(ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp)
15665 {
15666 if (*dma_hdp == NULL)
15667 return;
15668
15669 (void) ddi_dma_unbind_handle(*dma_hdp);
15670 (void) ddi_dma_mem_free(acc_hdp);
15671 ddi_dma_free_handle(dma_hdp);
15672 dma_hdp = NULL;
15673 }