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3832 AMD E721 workaround panics on KVM
Reviewed by: Marcel Telka <marcel@telka.sk>
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--- old/usr/src/uts/i86pc/os/mp_startup.c
+++ new/usr/src/uts/i86pc/os/mp_startup.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
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21 21
22 22 /*
23 23 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 */
25 25 /*
26 26 * Copyright (c) 2010, Intel Corporation.
27 27 * All rights reserved.
28 28 */
29 29 /*
30 30 * Copyright (c) 2012, Joyent, Inc. All rights reserved.
31 + * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
31 32 */
32 33
33 34 #include <sys/types.h>
34 35 #include <sys/thread.h>
35 36 #include <sys/cpuvar.h>
36 37 #include <sys/cpu.h>
37 38 #include <sys/t_lock.h>
38 39 #include <sys/param.h>
39 40 #include <sys/proc.h>
40 41 #include <sys/disp.h>
41 42 #include <sys/class.h>
42 43 #include <sys/cmn_err.h>
43 44 #include <sys/debug.h>
44 45 #include <sys/note.h>
45 46 #include <sys/asm_linkage.h>
46 47 #include <sys/x_call.h>
47 48 #include <sys/systm.h>
48 49 #include <sys/var.h>
49 50 #include <sys/vtrace.h>
50 51 #include <vm/hat.h>
51 52 #include <vm/as.h>
52 53 #include <vm/seg_kmem.h>
53 54 #include <vm/seg_kp.h>
54 55 #include <sys/segments.h>
55 56 #include <sys/kmem.h>
56 57 #include <sys/stack.h>
57 58 #include <sys/smp_impldefs.h>
58 59 #include <sys/x86_archext.h>
59 60 #include <sys/machsystm.h>
60 61 #include <sys/traptrace.h>
61 62 #include <sys/clock.h>
62 63 #include <sys/cpc_impl.h>
63 64 #include <sys/pg.h>
64 65 #include <sys/cmt.h>
65 66 #include <sys/dtrace.h>
66 67 #include <sys/archsystm.h>
67 68 #include <sys/fp.h>
68 69 #include <sys/reboot.h>
69 70 #include <sys/kdi_machimpl.h>
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70 71 #include <vm/hat_i86.h>
71 72 #include <vm/vm_dep.h>
72 73 #include <sys/memnode.h>
73 74 #include <sys/pci_cfgspace.h>
74 75 #include <sys/mach_mmu.h>
75 76 #include <sys/sysmacros.h>
76 77 #if defined(__xpv)
77 78 #include <sys/hypervisor.h>
78 79 #endif
79 80 #include <sys/cpu_module.h>
81 +#include <sys/ontrap.h>
80 82
81 83 struct cpu cpus[1]; /* CPU data */
82 84 struct cpu *cpu[NCPU] = {&cpus[0]}; /* pointers to all CPUs */
83 85 struct cpu *cpu_free_list; /* list for released CPUs */
84 86 cpu_core_t cpu_core[NCPU]; /* cpu_core structures */
85 87
86 88 #define cpu_next_free cpu_prev
87 89
88 90 /*
89 91 * Useful for disabling MP bring-up on a MP capable system.
90 92 */
91 93 int use_mp = 1;
92 94
93 95 /*
94 96 * to be set by a PSM to indicate what cpus
95 97 * are sitting around on the system.
96 98 */
97 99 cpuset_t mp_cpus;
98 100
99 101 /*
100 102 * This variable is used by the hat layer to decide whether or not
101 103 * critical sections are needed to prevent race conditions. For sun4m,
102 104 * this variable is set once enough MP initialization has been done in
103 105 * order to allow cross calls.
104 106 */
105 107 int flushes_require_xcalls;
106 108
107 109 cpuset_t cpu_ready_set; /* initialized in startup() */
108 110
109 111 static void mp_startup_boot(void);
110 112 static void mp_startup_hotplug(void);
111 113
112 114 static void cpu_sep_enable(void);
113 115 static void cpu_sep_disable(void);
114 116 static void cpu_asysc_enable(void);
115 117 static void cpu_asysc_disable(void);
116 118
117 119 /*
118 120 * Init CPU info - get CPU type info for processor_info system call.
119 121 */
120 122 void
121 123 init_cpu_info(struct cpu *cp)
122 124 {
123 125 processor_info_t *pi = &cp->cpu_type_info;
124 126
125 127 /*
126 128 * Get clock-frequency property for the CPU.
127 129 */
128 130 pi->pi_clock = cpu_freq;
129 131
130 132 /*
131 133 * Current frequency in Hz.
132 134 */
133 135 cp->cpu_curr_clock = cpu_freq_hz;
134 136
135 137 /*
136 138 * Supported frequencies.
137 139 */
138 140 if (cp->cpu_supp_freqs == NULL) {
139 141 cpu_set_supp_freqs(cp, NULL);
140 142 }
141 143
142 144 (void) strcpy(pi->pi_processor_type, "i386");
143 145 if (fpu_exists)
144 146 (void) strcpy(pi->pi_fputypes, "i387 compatible");
145 147
146 148 cp->cpu_idstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP);
147 149 cp->cpu_brandstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP);
148 150
149 151 /*
150 152 * If called for the BSP, cp is equal to current CPU.
151 153 * For non-BSPs, cpuid info of cp is not ready yet, so use cpuid info
152 154 * of current CPU as default values for cpu_idstr and cpu_brandstr.
153 155 * They will be corrected in mp_startup_common() after cpuid_pass1()
154 156 * has been invoked on target CPU.
155 157 */
156 158 (void) cpuid_getidstr(CPU, cp->cpu_idstr, CPU_IDSTRLEN);
157 159 (void) cpuid_getbrandstr(CPU, cp->cpu_brandstr, CPU_IDSTRLEN);
158 160 }
159 161
160 162 /*
161 163 * Configure syscall support on this CPU.
162 164 */
163 165 /*ARGSUSED*/
164 166 void
165 167 init_cpu_syscall(struct cpu *cp)
166 168 {
167 169 kpreempt_disable();
168 170
169 171 #if defined(__amd64)
170 172 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
171 173 is_x86_feature(x86_featureset, X86FSET_ASYSC)) {
172 174
173 175 #if !defined(__lint)
174 176 /*
175 177 * The syscall instruction imposes a certain ordering on
176 178 * segment selectors, so we double-check that ordering
177 179 * here.
178 180 */
179 181 ASSERT(KDS_SEL == KCS_SEL + 8);
180 182 ASSERT(UDS_SEL == U32CS_SEL + 8);
181 183 ASSERT(UCS_SEL == U32CS_SEL + 16);
182 184 #endif
183 185 /*
184 186 * Turn syscall/sysret extensions on.
185 187 */
186 188 cpu_asysc_enable();
187 189
188 190 /*
189 191 * Program the magic registers ..
190 192 */
191 193 wrmsr(MSR_AMD_STAR,
192 194 ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32);
193 195 wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall);
194 196 wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32);
195 197
196 198 /*
197 199 * This list of flags is masked off the incoming
198 200 * %rfl when we enter the kernel.
199 201 */
200 202 wrmsr(MSR_AMD_SFMASK, (uint64_t)(uintptr_t)(PS_IE | PS_T));
201 203 }
202 204 #endif
203 205
204 206 /*
205 207 * On 32-bit kernels, we use sysenter/sysexit because it's too
206 208 * hard to use syscall/sysret, and it is more portable anyway.
207 209 *
208 210 * On 64-bit kernels on Nocona machines, the 32-bit syscall
209 211 * variant isn't available to 32-bit applications, but sysenter is.
210 212 */
211 213 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
212 214 is_x86_feature(x86_featureset, X86FSET_SEP)) {
213 215
214 216 #if !defined(__lint)
215 217 /*
216 218 * The sysenter instruction imposes a certain ordering on
217 219 * segment selectors, so we double-check that ordering
218 220 * here. See "sysenter" in Intel document 245471-012, "IA-32
219 221 * Intel Architecture Software Developer's Manual Volume 2:
220 222 * Instruction Set Reference"
221 223 */
222 224 ASSERT(KDS_SEL == KCS_SEL + 8);
223 225
224 226 ASSERT32(UCS_SEL == ((KCS_SEL + 16) | 3));
225 227 ASSERT32(UDS_SEL == UCS_SEL + 8);
226 228
227 229 ASSERT64(U32CS_SEL == ((KCS_SEL + 16) | 3));
228 230 ASSERT64(UDS_SEL == U32CS_SEL + 8);
229 231 #endif
230 232
231 233 cpu_sep_enable();
232 234
233 235 /*
234 236 * resume() sets this value to the base of the threads stack
235 237 * via a context handler.
236 238 */
237 239 wrmsr(MSR_INTC_SEP_ESP, 0);
238 240 wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter);
239 241 }
240 242
241 243 kpreempt_enable();
242 244 }
243 245
244 246 /*
245 247 * Multiprocessor initialization.
246 248 *
247 249 * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the
248 250 * startup and idle threads for the specified CPU.
249 251 * Parameter boot is true for boot time operations and is false for CPU
250 252 * DR operations.
251 253 */
252 254 static struct cpu *
253 255 mp_cpu_configure_common(int cpun, boolean_t boot)
254 256 {
255 257 struct cpu *cp;
256 258 kthread_id_t tp;
257 259 caddr_t sp;
258 260 proc_t *procp;
259 261 #if !defined(__xpv)
260 262 extern int idle_cpu_prefer_mwait;
261 263 extern void cpu_idle_mwait();
262 264 #endif
263 265 extern void idle();
264 266 extern void cpu_idle();
265 267
266 268 #ifdef TRAPTRACE
267 269 trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun];
268 270 #endif
269 271
270 272 ASSERT(MUTEX_HELD(&cpu_lock));
271 273 ASSERT(cpun < NCPU && cpu[cpun] == NULL);
272 274
273 275 if (cpu_free_list == NULL) {
274 276 cp = kmem_zalloc(sizeof (*cp), KM_SLEEP);
275 277 } else {
276 278 cp = cpu_free_list;
277 279 cpu_free_list = cp->cpu_next_free;
278 280 }
279 281
280 282 cp->cpu_m.mcpu_istamp = cpun << 16;
281 283
282 284 /* Create per CPU specific threads in the process p0. */
283 285 procp = &p0;
284 286
285 287 /*
286 288 * Initialize the dispatcher first.
287 289 */
288 290 disp_cpu_init(cp);
289 291
290 292 cpu_vm_data_init(cp);
291 293
292 294 /*
293 295 * Allocate and initialize the startup thread for this CPU.
294 296 * Interrupt and process switch stacks get allocated later
295 297 * when the CPU starts running.
296 298 */
297 299 tp = thread_create(NULL, 0, NULL, NULL, 0, procp,
298 300 TS_STOPPED, maxclsyspri);
299 301
300 302 /*
301 303 * Set state to TS_ONPROC since this thread will start running
302 304 * as soon as the CPU comes online.
303 305 *
304 306 * All the other fields of the thread structure are setup by
305 307 * thread_create().
306 308 */
307 309 THREAD_ONPROC(tp, cp);
308 310 tp->t_preempt = 1;
309 311 tp->t_bound_cpu = cp;
310 312 tp->t_affinitycnt = 1;
311 313 tp->t_cpu = cp;
312 314 tp->t_disp_queue = cp->cpu_disp;
313 315
314 316 /*
315 317 * Setup thread to start in mp_startup_common.
316 318 */
317 319 sp = tp->t_stk;
318 320 tp->t_sp = (uintptr_t)(sp - MINFRAME);
319 321 #if defined(__amd64)
320 322 tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */
321 323 #endif
322 324 /*
323 325 * Setup thread start entry point for boot or hotplug.
324 326 */
325 327 if (boot) {
326 328 tp->t_pc = (uintptr_t)mp_startup_boot;
327 329 } else {
328 330 tp->t_pc = (uintptr_t)mp_startup_hotplug;
329 331 }
330 332
331 333 cp->cpu_id = cpun;
332 334 cp->cpu_self = cp;
333 335 cp->cpu_thread = tp;
334 336 cp->cpu_lwp = NULL;
335 337 cp->cpu_dispthread = tp;
336 338 cp->cpu_dispatch_pri = DISP_PRIO(tp);
337 339
338 340 /*
339 341 * cpu_base_spl must be set explicitly here to prevent any blocking
340 342 * operations in mp_startup_common from causing the spl of the cpu
341 343 * to drop to 0 (allowing device interrupts before we're ready) in
342 344 * resume().
343 345 * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY.
344 346 * As an extra bit of security on DEBUG kernels, this is enforced with
345 347 * an assertion in mp_startup_common() -- before cpu_base_spl is set
346 348 * to its proper value.
347 349 */
348 350 cp->cpu_base_spl = ipltospl(LOCK_LEVEL);
349 351
350 352 /*
351 353 * Now, initialize per-CPU idle thread for this CPU.
352 354 */
353 355 tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1);
354 356
355 357 cp->cpu_idle_thread = tp;
356 358
357 359 tp->t_preempt = 1;
358 360 tp->t_bound_cpu = cp;
359 361 tp->t_affinitycnt = 1;
360 362 tp->t_cpu = cp;
361 363 tp->t_disp_queue = cp->cpu_disp;
362 364
363 365 /*
364 366 * Bootstrap the CPU's PG data
365 367 */
366 368 pg_cpu_bootstrap(cp);
367 369
368 370 /*
369 371 * Perform CPC initialization on the new CPU.
370 372 */
371 373 kcpc_hw_init(cp);
372 374
373 375 /*
374 376 * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2
375 377 * for each CPU.
376 378 */
377 379 setup_vaddr_for_ppcopy(cp);
378 380
379 381 /*
380 382 * Allocate page for new GDT and initialize from current GDT.
381 383 */
382 384 #if !defined(__lint)
383 385 ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE);
384 386 #endif
385 387 cp->cpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP);
386 388 bcopy(CPU->cpu_gdt, cp->cpu_gdt, (sizeof (*cp->cpu_gdt) * NGDT));
387 389
388 390 #if defined(__i386)
389 391 /*
390 392 * setup kernel %gs.
391 393 */
392 394 set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA,
393 395 SEL_KPL, 0, 1);
394 396 #endif
395 397
396 398 /*
397 399 * If we have more than one node, each cpu gets a copy of IDT
398 400 * local to its node. If this is a Pentium box, we use cpu 0's
399 401 * IDT. cpu 0's IDT has been made read-only to workaround the
400 402 * cmpxchgl register bug
401 403 */
402 404 if (system_hardware.hd_nodes && x86_type != X86_TYPE_P5) {
403 405 #if !defined(__lint)
404 406 ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE);
405 407 #endif
406 408 cp->cpu_idt = kmem_zalloc(PAGESIZE, KM_SLEEP);
407 409 bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE);
408 410 } else {
409 411 cp->cpu_idt = CPU->cpu_idt;
410 412 }
411 413
412 414 /*
413 415 * Get interrupt priority data from cpu 0.
414 416 */
415 417 cp->cpu_pri_data = CPU->cpu_pri_data;
416 418
417 419 /*
418 420 * alloc space for cpuid info
419 421 */
420 422 cpuid_alloc_space(cp);
421 423 #if !defined(__xpv)
422 424 if (is_x86_feature(x86_featureset, X86FSET_MWAIT) &&
423 425 idle_cpu_prefer_mwait) {
424 426 cp->cpu_m.mcpu_mwait = cpuid_mwait_alloc(cp);
425 427 cp->cpu_m.mcpu_idle_cpu = cpu_idle_mwait;
426 428 } else
427 429 #endif
428 430 cp->cpu_m.mcpu_idle_cpu = cpu_idle;
429 431
430 432 init_cpu_info(cp);
431 433
432 434 /*
433 435 * alloc space for ucode_info
434 436 */
435 437 ucode_alloc_space(cp);
436 438 xc_init_cpu(cp);
437 439 hat_cpu_online(cp);
438 440
439 441 #ifdef TRAPTRACE
440 442 /*
441 443 * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers
442 444 */
443 445 ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP);
444 446 ttc->ttc_next = ttc->ttc_first;
445 447 ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize;
446 448 #endif
447 449
448 450 /*
449 451 * Record that we have another CPU.
450 452 */
451 453 /*
452 454 * Initialize the interrupt threads for this CPU
453 455 */
454 456 cpu_intr_alloc(cp, NINTR_THREADS);
455 457
456 458 cp->cpu_flags = CPU_OFFLINE | CPU_QUIESCED | CPU_POWEROFF;
457 459 cpu_set_state(cp);
458 460
459 461 /*
460 462 * Add CPU to list of available CPUs. It'll be on the active list
461 463 * after mp_startup_common().
462 464 */
463 465 cpu_add_unit(cp);
464 466
465 467 return (cp);
466 468 }
467 469
468 470 /*
469 471 * Undo what was done in mp_cpu_configure_common
470 472 */
471 473 static void
472 474 mp_cpu_unconfigure_common(struct cpu *cp, int error)
473 475 {
474 476 ASSERT(MUTEX_HELD(&cpu_lock));
475 477
476 478 /*
477 479 * Remove the CPU from the list of available CPUs.
478 480 */
479 481 cpu_del_unit(cp->cpu_id);
480 482
481 483 if (error == ETIMEDOUT) {
482 484 /*
483 485 * The cpu was started, but never *seemed* to run any
484 486 * code in the kernel; it's probably off spinning in its
485 487 * own private world, though with potential references to
486 488 * our kmem-allocated IDTs and GDTs (for example).
487 489 *
488 490 * Worse still, it may actually wake up some time later,
489 491 * so rather than guess what it might or might not do, we
490 492 * leave the fundamental data structures intact.
491 493 */
492 494 cp->cpu_flags = 0;
493 495 return;
494 496 }
495 497
496 498 /*
497 499 * At this point, the only threads bound to this CPU should
498 500 * special per-cpu threads: it's idle thread, it's pause threads,
499 501 * and it's interrupt threads. Clean these up.
500 502 */
501 503 cpu_destroy_bound_threads(cp);
502 504 cp->cpu_idle_thread = NULL;
503 505
504 506 /*
505 507 * Free the interrupt stack.
506 508 */
507 509 segkp_release(segkp,
508 510 cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME)));
509 511 cp->cpu_intr_stack = NULL;
510 512
511 513 #ifdef TRAPTRACE
512 514 /*
513 515 * Discard the trap trace buffer
514 516 */
515 517 {
516 518 trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id];
517 519
518 520 kmem_free((void *)ttc->ttc_first, trap_trace_bufsize);
519 521 ttc->ttc_first = NULL;
520 522 }
521 523 #endif
522 524
523 525 hat_cpu_offline(cp);
524 526
525 527 ucode_free_space(cp);
526 528
527 529 /* Free CPU ID string and brand string. */
528 530 if (cp->cpu_idstr) {
529 531 kmem_free(cp->cpu_idstr, CPU_IDSTRLEN);
530 532 cp->cpu_idstr = NULL;
531 533 }
532 534 if (cp->cpu_brandstr) {
533 535 kmem_free(cp->cpu_brandstr, CPU_IDSTRLEN);
534 536 cp->cpu_brandstr = NULL;
535 537 }
536 538
537 539 #if !defined(__xpv)
538 540 if (cp->cpu_m.mcpu_mwait != NULL) {
539 541 cpuid_mwait_free(cp);
540 542 cp->cpu_m.mcpu_mwait = NULL;
541 543 }
542 544 #endif
543 545 cpuid_free_space(cp);
544 546
545 547 if (cp->cpu_idt != CPU->cpu_idt)
546 548 kmem_free(cp->cpu_idt, PAGESIZE);
547 549 cp->cpu_idt = NULL;
548 550
549 551 kmem_free(cp->cpu_gdt, PAGESIZE);
550 552 cp->cpu_gdt = NULL;
551 553
552 554 if (cp->cpu_supp_freqs != NULL) {
553 555 size_t len = strlen(cp->cpu_supp_freqs) + 1;
554 556 kmem_free(cp->cpu_supp_freqs, len);
555 557 cp->cpu_supp_freqs = NULL;
556 558 }
557 559
558 560 teardown_vaddr_for_ppcopy(cp);
559 561
560 562 kcpc_hw_fini(cp);
561 563
562 564 cp->cpu_dispthread = NULL;
563 565 cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */
564 566
565 567 cpu_vm_data_destroy(cp);
566 568
567 569 xc_fini_cpu(cp);
568 570 disp_cpu_fini(cp);
569 571
570 572 ASSERT(cp != CPU0);
571 573 bzero(cp, sizeof (*cp));
572 574 cp->cpu_next_free = cpu_free_list;
573 575 cpu_free_list = cp;
574 576 }
575 577
576 578 /*
577 579 * Apply workarounds for known errata, and warn about those that are absent.
578 580 *
579 581 * System vendors occasionally create configurations which contain different
580 582 * revisions of the CPUs that are almost but not exactly the same. At the
581 583 * time of writing, this meant that their clock rates were the same, their
582 584 * feature sets were the same, but the required workaround were -not-
583 585 * necessarily the same. So, this routine is invoked on -every- CPU soon
584 586 * after starting to make sure that the resulting system contains the most
585 587 * pessimal set of workarounds needed to cope with *any* of the CPUs in the
586 588 * system.
587 589 *
588 590 * workaround_errata is invoked early in mlsetup() for CPU 0, and in
589 591 * mp_startup_common() for all slave CPUs. Slaves process workaround_errata
590 592 * prior to acknowledging their readiness to the master, so this routine will
591 593 * never be executed by multiple CPUs in parallel, thus making updates to
592 594 * global data safe.
593 595 *
594 596 * These workarounds are based on Rev 3.57 of the Revision Guide for
595 597 * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005.
596 598 */
597 599
598 600 #if defined(OPTERON_ERRATUM_88)
599 601 int opteron_erratum_88; /* if non-zero -> at least one cpu has it */
600 602 #endif
601 603
602 604 #if defined(OPTERON_ERRATUM_91)
603 605 int opteron_erratum_91; /* if non-zero -> at least one cpu has it */
604 606 #endif
605 607
606 608 #if defined(OPTERON_ERRATUM_93)
607 609 int opteron_erratum_93; /* if non-zero -> at least one cpu has it */
608 610 #endif
609 611
610 612 #if defined(OPTERON_ERRATUM_95)
611 613 int opteron_erratum_95; /* if non-zero -> at least one cpu has it */
612 614 #endif
613 615
614 616 #if defined(OPTERON_ERRATUM_100)
615 617 int opteron_erratum_100; /* if non-zero -> at least one cpu has it */
616 618 #endif
617 619
618 620 #if defined(OPTERON_ERRATUM_108)
619 621 int opteron_erratum_108; /* if non-zero -> at least one cpu has it */
620 622 #endif
621 623
622 624 #if defined(OPTERON_ERRATUM_109)
623 625 int opteron_erratum_109; /* if non-zero -> at least one cpu has it */
624 626 #endif
625 627
626 628 #if defined(OPTERON_ERRATUM_121)
627 629 int opteron_erratum_121; /* if non-zero -> at least one cpu has it */
628 630 #endif
629 631
630 632 #if defined(OPTERON_ERRATUM_122)
631 633 int opteron_erratum_122; /* if non-zero -> at least one cpu has it */
632 634 #endif
633 635
634 636 #if defined(OPTERON_ERRATUM_123)
635 637 int opteron_erratum_123; /* if non-zero -> at least one cpu has it */
636 638 #endif
637 639
638 640 #if defined(OPTERON_ERRATUM_131)
639 641 int opteron_erratum_131; /* if non-zero -> at least one cpu has it */
640 642 #endif
641 643
642 644 #if defined(OPTERON_WORKAROUND_6336786)
643 645 int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */
644 646 int opteron_workaround_6336786_UP = 0; /* Not needed for UP */
645 647 #endif
646 648
647 649 #if defined(OPTERON_WORKAROUND_6323525)
648 650 int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */
649 651 #endif
650 652
651 653 #if defined(OPTERON_ERRATUM_298)
652 654 int opteron_erratum_298;
653 655 #endif
654 656
655 657 #if defined(OPTERON_ERRATUM_721)
656 658 int opteron_erratum_721;
657 659 #endif
658 660
659 661 static void
660 662 workaround_warning(cpu_t *cp, uint_t erratum)
661 663 {
662 664 cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u",
663 665 cp->cpu_id, erratum);
664 666 }
665 667
666 668 static void
667 669 workaround_applied(uint_t erratum)
668 670 {
669 671 if (erratum > 1000000)
670 672 cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n",
671 673 erratum);
672 674 else
673 675 cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n",
674 676 erratum);
675 677 }
676 678
677 679 static void
678 680 msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error)
679 681 {
680 682 cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d",
681 683 cp->cpu_id, rw, msr, error);
682 684 }
683 685
684 686 /*
685 687 * Determine the number of nodes in a Hammer / Greyhound / Griffin family
686 688 * system.
687 689 */
688 690 static uint_t
689 691 opteron_get_nnodes(void)
690 692 {
691 693 static uint_t nnodes = 0;
692 694
693 695 if (nnodes == 0) {
694 696 #ifdef DEBUG
695 697 uint_t family;
696 698
697 699 /*
698 700 * This routine uses a PCI config space based mechanism
699 701 * for retrieving the number of nodes in the system.
700 702 * Device 24, function 0, offset 0x60 as used here is not
701 703 * AMD processor architectural, and may not work on processor
702 704 * families other than those listed below.
703 705 *
704 706 * Callers of this routine must ensure that we're running on
705 707 * a processor which supports this mechanism.
706 708 * The assertion below is meant to catch calls on unsupported
707 709 * processors.
708 710 */
709 711 family = cpuid_getfamily(CPU);
710 712 ASSERT(family == 0xf || family == 0x10 || family == 0x11);
711 713 #endif /* DEBUG */
712 714
713 715 /*
714 716 * Obtain the number of nodes in the system from
715 717 * bits [6:4] of the Node ID register on node 0.
716 718 *
717 719 * The actual node count is NodeID[6:4] + 1
718 720 *
719 721 * The Node ID register is accessed via function 0,
720 722 * offset 0x60. Node 0 is device 24.
721 723 */
722 724 nnodes = ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1;
723 725 }
724 726 return (nnodes);
725 727 }
726 728
727 729 uint_t
728 730 do_erratum_298(struct cpu *cpu)
729 731 {
730 732 static int osvwrc = -3;
731 733 extern int osvw_opteron_erratum(cpu_t *, uint_t);
732 734
733 735 /*
734 736 * L2 Eviction May Occur During Processor Operation To Set
735 737 * Accessed or Dirty Bit.
736 738 */
737 739 if (osvwrc == -3) {
738 740 osvwrc = osvw_opteron_erratum(cpu, 298);
739 741 } else {
740 742 /* osvw return codes should be consistent for all cpus */
741 743 ASSERT(osvwrc == osvw_opteron_erratum(cpu, 298));
742 744 }
743 745
744 746 switch (osvwrc) {
745 747 case 0: /* erratum is not present: do nothing */
746 748 break;
747 749 case 1: /* erratum is present: BIOS workaround applied */
748 750 /*
749 751 * check if workaround is actually in place and issue warning
750 752 * if not.
751 753 */
752 754 if (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) ||
753 755 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0)) {
754 756 #if defined(OPTERON_ERRATUM_298)
755 757 opteron_erratum_298++;
756 758 #else
757 759 workaround_warning(cpu, 298);
758 760 return (1);
759 761 #endif
760 762 }
761 763 break;
762 764 case -1: /* cannot determine via osvw: check cpuid */
763 765 if ((cpuid_opteron_erratum(cpu, 298) > 0) &&
764 766 (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) ||
765 767 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0))) {
766 768 #if defined(OPTERON_ERRATUM_298)
767 769 opteron_erratum_298++;
768 770 #else
769 771 workaround_warning(cpu, 298);
770 772 return (1);
771 773 #endif
772 774 }
773 775 break;
774 776 }
775 777 return (0);
776 778 }
777 779
778 780 uint_t
779 781 workaround_errata(struct cpu *cpu)
780 782 {
781 783 uint_t missing = 0;
782 784
783 785 ASSERT(cpu == CPU);
784 786
785 787 /*LINTED*/
786 788 if (cpuid_opteron_erratum(cpu, 88) > 0) {
787 789 /*
788 790 * SWAPGS May Fail To Read Correct GS Base
789 791 */
790 792 #if defined(OPTERON_ERRATUM_88)
791 793 /*
792 794 * The workaround is an mfence in the relevant assembler code
793 795 */
794 796 opteron_erratum_88++;
795 797 #else
796 798 workaround_warning(cpu, 88);
797 799 missing++;
798 800 #endif
799 801 }
800 802
801 803 if (cpuid_opteron_erratum(cpu, 91) > 0) {
802 804 /*
803 805 * Software Prefetches May Report A Page Fault
804 806 */
805 807 #if defined(OPTERON_ERRATUM_91)
806 808 /*
807 809 * fix is in trap.c
808 810 */
809 811 opteron_erratum_91++;
810 812 #else
811 813 workaround_warning(cpu, 91);
812 814 missing++;
813 815 #endif
814 816 }
815 817
816 818 if (cpuid_opteron_erratum(cpu, 93) > 0) {
817 819 /*
818 820 * RSM Auto-Halt Restart Returns to Incorrect RIP
819 821 */
820 822 #if defined(OPTERON_ERRATUM_93)
821 823 /*
822 824 * fix is in trap.c
823 825 */
824 826 opteron_erratum_93++;
825 827 #else
826 828 workaround_warning(cpu, 93);
827 829 missing++;
828 830 #endif
829 831 }
830 832
831 833 /*LINTED*/
832 834 if (cpuid_opteron_erratum(cpu, 95) > 0) {
833 835 /*
834 836 * RET Instruction May Return to Incorrect EIP
835 837 */
836 838 #if defined(OPTERON_ERRATUM_95)
837 839 #if defined(_LP64)
838 840 /*
839 841 * Workaround this by ensuring that 32-bit user code and
840 842 * 64-bit kernel code never occupy the same address
841 843 * range mod 4G.
842 844 */
843 845 if (_userlimit32 > 0xc0000000ul)
844 846 *(uintptr_t *)&_userlimit32 = 0xc0000000ul;
845 847
846 848 /*LINTED*/
847 849 ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u);
848 850 opteron_erratum_95++;
849 851 #endif /* _LP64 */
850 852 #else
851 853 workaround_warning(cpu, 95);
852 854 missing++;
853 855 #endif
854 856 }
855 857
856 858 if (cpuid_opteron_erratum(cpu, 100) > 0) {
857 859 /*
858 860 * Compatibility Mode Branches Transfer to Illegal Address
859 861 */
860 862 #if defined(OPTERON_ERRATUM_100)
861 863 /*
862 864 * fix is in trap.c
863 865 */
864 866 opteron_erratum_100++;
865 867 #else
866 868 workaround_warning(cpu, 100);
867 869 missing++;
868 870 #endif
869 871 }
870 872
871 873 /*LINTED*/
872 874 if (cpuid_opteron_erratum(cpu, 108) > 0) {
873 875 /*
874 876 * CPUID Instruction May Return Incorrect Model Number In
875 877 * Some Processors
876 878 */
877 879 #if defined(OPTERON_ERRATUM_108)
878 880 /*
879 881 * (Our cpuid-handling code corrects the model number on
880 882 * those processors)
881 883 */
882 884 #else
883 885 workaround_warning(cpu, 108);
884 886 missing++;
885 887 #endif
886 888 }
887 889
888 890 /*LINTED*/
889 891 if (cpuid_opteron_erratum(cpu, 109) > 0) do {
890 892 /*
891 893 * Certain Reverse REP MOVS May Produce Unpredictable Behavior
892 894 */
893 895 #if defined(OPTERON_ERRATUM_109)
894 896 /*
895 897 * The "workaround" is to print a warning to upgrade the BIOS
896 898 */
897 899 uint64_t value;
898 900 const uint_t msr = MSR_AMD_PATCHLEVEL;
899 901 int err;
900 902
901 903 if ((err = checked_rdmsr(msr, &value)) != 0) {
902 904 msr_warning(cpu, "rd", msr, err);
903 905 workaround_warning(cpu, 109);
904 906 missing++;
905 907 }
906 908 if (value == 0)
907 909 opteron_erratum_109++;
908 910 #else
909 911 workaround_warning(cpu, 109);
910 912 missing++;
911 913 #endif
912 914 /*CONSTANTCONDITION*/
913 915 } while (0);
914 916
915 917 /*LINTED*/
916 918 if (cpuid_opteron_erratum(cpu, 121) > 0) {
917 919 /*
918 920 * Sequential Execution Across Non_Canonical Boundary Caused
919 921 * Processor Hang
920 922 */
921 923 #if defined(OPTERON_ERRATUM_121)
922 924 #if defined(_LP64)
923 925 /*
924 926 * Erratum 121 is only present in long (64 bit) mode.
925 927 * Workaround is to include the page immediately before the
926 928 * va hole to eliminate the possibility of system hangs due to
927 929 * sequential execution across the va hole boundary.
928 930 */
929 931 if (opteron_erratum_121)
930 932 opteron_erratum_121++;
931 933 else {
932 934 if (hole_start) {
933 935 hole_start -= PAGESIZE;
934 936 } else {
935 937 /*
936 938 * hole_start not yet initialized by
937 939 * mmu_init. Initialize hole_start
938 940 * with value to be subtracted.
939 941 */
940 942 hole_start = PAGESIZE;
941 943 }
942 944 opteron_erratum_121++;
943 945 }
944 946 #endif /* _LP64 */
945 947 #else
946 948 workaround_warning(cpu, 121);
947 949 missing++;
948 950 #endif
949 951 }
950 952
951 953 /*LINTED*/
952 954 if (cpuid_opteron_erratum(cpu, 122) > 0) do {
953 955 /*
954 956 * TLB Flush Filter May Cause Coherency Problem in
955 957 * Multiprocessor Systems
956 958 */
957 959 #if defined(OPTERON_ERRATUM_122)
958 960 uint64_t value;
959 961 const uint_t msr = MSR_AMD_HWCR;
960 962 int error;
961 963
962 964 /*
963 965 * Erratum 122 is only present in MP configurations (multi-core
964 966 * or multi-processor).
965 967 */
966 968 #if defined(__xpv)
967 969 if (!DOMAIN_IS_INITDOMAIN(xen_info))
968 970 break;
969 971 if (!opteron_erratum_122 && xpv_nr_phys_cpus() == 1)
970 972 break;
971 973 #else
972 974 if (!opteron_erratum_122 && opteron_get_nnodes() == 1 &&
973 975 cpuid_get_ncpu_per_chip(cpu) == 1)
974 976 break;
975 977 #endif
976 978 /* disable TLB Flush Filter */
977 979
978 980 if ((error = checked_rdmsr(msr, &value)) != 0) {
979 981 msr_warning(cpu, "rd", msr, error);
980 982 workaround_warning(cpu, 122);
981 983 missing++;
982 984 } else {
983 985 value |= (uint64_t)AMD_HWCR_FFDIS;
984 986 if ((error = checked_wrmsr(msr, value)) != 0) {
985 987 msr_warning(cpu, "wr", msr, error);
986 988 workaround_warning(cpu, 122);
987 989 missing++;
988 990 }
989 991 }
990 992 opteron_erratum_122++;
991 993 #else
992 994 workaround_warning(cpu, 122);
993 995 missing++;
994 996 #endif
995 997 /*CONSTANTCONDITION*/
996 998 } while (0);
997 999
998 1000 /*LINTED*/
999 1001 if (cpuid_opteron_erratum(cpu, 123) > 0) do {
1000 1002 /*
1001 1003 * Bypassed Reads May Cause Data Corruption of System Hang in
1002 1004 * Dual Core Processors
1003 1005 */
1004 1006 #if defined(OPTERON_ERRATUM_123)
1005 1007 uint64_t value;
1006 1008 const uint_t msr = MSR_AMD_PATCHLEVEL;
1007 1009 int err;
1008 1010
1009 1011 /*
1010 1012 * Erratum 123 applies only to multi-core cpus.
1011 1013 */
1012 1014 if (cpuid_get_ncpu_per_chip(cpu) < 2)
1013 1015 break;
1014 1016 #if defined(__xpv)
1015 1017 if (!DOMAIN_IS_INITDOMAIN(xen_info))
1016 1018 break;
1017 1019 #endif
1018 1020 /*
1019 1021 * The "workaround" is to print a warning to upgrade the BIOS
1020 1022 */
1021 1023 if ((err = checked_rdmsr(msr, &value)) != 0) {
1022 1024 msr_warning(cpu, "rd", msr, err);
1023 1025 workaround_warning(cpu, 123);
1024 1026 missing++;
1025 1027 }
1026 1028 if (value == 0)
1027 1029 opteron_erratum_123++;
1028 1030 #else
1029 1031 workaround_warning(cpu, 123);
1030 1032 missing++;
1031 1033
1032 1034 #endif
1033 1035 /*CONSTANTCONDITION*/
1034 1036 } while (0);
1035 1037
1036 1038 /*LINTED*/
1037 1039 if (cpuid_opteron_erratum(cpu, 131) > 0) do {
1038 1040 /*
1039 1041 * Multiprocessor Systems with Four or More Cores May Deadlock
1040 1042 * Waiting for a Probe Response
1041 1043 */
1042 1044 #if defined(OPTERON_ERRATUM_131)
1043 1045 uint64_t nbcfg;
1044 1046 const uint_t msr = MSR_AMD_NB_CFG;
1045 1047 const uint64_t wabits =
1046 1048 AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR;
1047 1049 int error;
1048 1050
1049 1051 /*
1050 1052 * Erratum 131 applies to any system with four or more cores.
1051 1053 */
1052 1054 if (opteron_erratum_131)
1053 1055 break;
1054 1056 #if defined(__xpv)
1055 1057 if (!DOMAIN_IS_INITDOMAIN(xen_info))
1056 1058 break;
1057 1059 if (xpv_nr_phys_cpus() < 4)
1058 1060 break;
1059 1061 #else
1060 1062 if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu) < 4)
1061 1063 break;
1062 1064 #endif
1063 1065 /*
1064 1066 * Print a warning if neither of the workarounds for
1065 1067 * erratum 131 is present.
1066 1068 */
1067 1069 if ((error = checked_rdmsr(msr, &nbcfg)) != 0) {
1068 1070 msr_warning(cpu, "rd", msr, error);
1069 1071 workaround_warning(cpu, 131);
1070 1072 missing++;
1071 1073 } else if ((nbcfg & wabits) == 0) {
1072 1074 opteron_erratum_131++;
1073 1075 } else {
1074 1076 /* cannot have both workarounds set */
1075 1077 ASSERT((nbcfg & wabits) != wabits);
1076 1078 }
1077 1079 #else
1078 1080 workaround_warning(cpu, 131);
1079 1081 missing++;
1080 1082 #endif
1081 1083 /*CONSTANTCONDITION*/
1082 1084 } while (0);
1083 1085
1084 1086 /*
1085 1087 * This isn't really an erratum, but for convenience the
1086 1088 * detection/workaround code lives here and in cpuid_opteron_erratum.
1087 1089 */
1088 1090 if (cpuid_opteron_erratum(cpu, 6336786) > 0) {
1089 1091 #if defined(OPTERON_WORKAROUND_6336786)
1090 1092 /*
1091 1093 * Disable C1-Clock ramping on multi-core/multi-processor
1092 1094 * K8 platforms to guard against TSC drift.
1093 1095 */
1094 1096 if (opteron_workaround_6336786) {
1095 1097 opteron_workaround_6336786++;
1096 1098 #if defined(__xpv)
1097 1099 } else if ((DOMAIN_IS_INITDOMAIN(xen_info) &&
1098 1100 xpv_nr_phys_cpus() > 1) ||
1099 1101 opteron_workaround_6336786_UP) {
1100 1102 /*
1101 1103 * XXPV Hmm. We can't walk the Northbridges on
1102 1104 * the hypervisor; so just complain and drive
1103 1105 * on. This probably needs to be fixed in
1104 1106 * the hypervisor itself.
1105 1107 */
1106 1108 opteron_workaround_6336786++;
1107 1109 workaround_warning(cpu, 6336786);
1108 1110 #else /* __xpv */
1109 1111 } else if ((opteron_get_nnodes() *
1110 1112 cpuid_get_ncpu_per_chip(cpu) > 1) ||
1111 1113 opteron_workaround_6336786_UP) {
1112 1114
1113 1115 uint_t node, nnodes;
1114 1116 uint8_t data;
1115 1117
1116 1118 nnodes = opteron_get_nnodes();
1117 1119 for (node = 0; node < nnodes; node++) {
1118 1120 /*
1119 1121 * Clear PMM7[1:0] (function 3, offset 0x87)
1120 1122 * Northbridge device is the node id + 24.
1121 1123 */
1122 1124 data = pci_getb_func(0, node + 24, 3, 0x87);
1123 1125 data &= 0xFC;
1124 1126 pci_putb_func(0, node + 24, 3, 0x87, data);
1125 1127 }
1126 1128 opteron_workaround_6336786++;
1127 1129 #endif /* __xpv */
1128 1130 }
1129 1131 #else
1130 1132 workaround_warning(cpu, 6336786);
1131 1133 missing++;
1132 1134 #endif
1133 1135 }
1134 1136
1135 1137 /*LINTED*/
1136 1138 /*
1137 1139 * Mutex primitives don't work as expected.
1138 1140 */
1139 1141 if (cpuid_opteron_erratum(cpu, 6323525) > 0) {
1140 1142 #if defined(OPTERON_WORKAROUND_6323525)
1141 1143 /*
1142 1144 * This problem only occurs with 2 or more cores. If bit in
1143 1145 * MSR_AMD_BU_CFG set, then not applicable. The workaround
1144 1146 * is to patch the semaphone routines with the lfence
1145 1147 * instruction to provide necessary load memory barrier with
1146 1148 * possible subsequent read-modify-write ops.
1147 1149 *
1148 1150 * It is too early in boot to call the patch routine so
1149 1151 * set erratum variable to be done in startup_end().
1150 1152 */
1151 1153 if (opteron_workaround_6323525) {
1152 1154 opteron_workaround_6323525++;
1153 1155 #if defined(__xpv)
1154 1156 } else if (is_x86_feature(x86_featureset, X86FSET_SSE2)) {
1155 1157 if (DOMAIN_IS_INITDOMAIN(xen_info)) {
1156 1158 /*
1157 1159 * XXPV Use dom0_msr here when extended
1158 1160 * operations are supported?
1159 1161 */
1160 1162 if (xpv_nr_phys_cpus() > 1)
1161 1163 opteron_workaround_6323525++;
1162 1164 } else {
1163 1165 /*
1164 1166 * We have no way to tell how many physical
1165 1167 * cpus there are, or even if this processor
1166 1168 * has the problem, so enable the workaround
1167 1169 * unconditionally (at some performance cost).
1168 1170 */
1169 1171 opteron_workaround_6323525++;
1170 1172 }
1171 1173 #else /* __xpv */
1172 1174 } else if (is_x86_feature(x86_featureset, X86FSET_SSE2) &&
1173 1175 ((opteron_get_nnodes() *
1174 1176 cpuid_get_ncpu_per_chip(cpu)) > 1)) {
1175 1177 if ((xrdmsr(MSR_AMD_BU_CFG) & (UINT64_C(1) << 33)) == 0)
1176 1178 opteron_workaround_6323525++;
1177 1179 #endif /* __xpv */
1178 1180 }
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1179 1181 #else
1180 1182 workaround_warning(cpu, 6323525);
1181 1183 missing++;
1182 1184 #endif
1183 1185 }
1184 1186
1185 1187 missing += do_erratum_298(cpu);
1186 1188
1187 1189 if (cpuid_opteron_erratum(cpu, 721) > 0) {
1188 1190 #if defined(OPTERON_ERRATUM_721)
1189 - wrmsr(MSR_AMD_DE_CFG, rdmsr(MSR_AMD_DE_CFG) | AMD_DE_CFG_E721);
1191 + on_trap_data_t otd;
1192 +
1193 + if (!on_trap(&otd, OT_DATA_ACCESS))
1194 + wrmsr(MSR_AMD_DE_CFG,
1195 + rdmsr(MSR_AMD_DE_CFG) | AMD_DE_CFG_E721);
1196 + no_trap();
1197 +
1190 1198 opteron_erratum_721++;
1191 1199 #else
1192 1200 workaround_warning(cpu, 721);
1193 1201 missing++;
1194 1202 #endif
1195 1203 }
1196 1204
1197 1205 #ifdef __xpv
1198 1206 return (0);
1199 1207 #else
1200 1208 return (missing);
1201 1209 #endif
1202 1210 }
1203 1211
1204 1212 void
1205 1213 workaround_errata_end()
1206 1214 {
1207 1215 #if defined(OPTERON_ERRATUM_88)
1208 1216 if (opteron_erratum_88)
1209 1217 workaround_applied(88);
1210 1218 #endif
1211 1219 #if defined(OPTERON_ERRATUM_91)
1212 1220 if (opteron_erratum_91)
1213 1221 workaround_applied(91);
1214 1222 #endif
1215 1223 #if defined(OPTERON_ERRATUM_93)
1216 1224 if (opteron_erratum_93)
1217 1225 workaround_applied(93);
1218 1226 #endif
1219 1227 #if defined(OPTERON_ERRATUM_95)
1220 1228 if (opteron_erratum_95)
1221 1229 workaround_applied(95);
1222 1230 #endif
1223 1231 #if defined(OPTERON_ERRATUM_100)
1224 1232 if (opteron_erratum_100)
1225 1233 workaround_applied(100);
1226 1234 #endif
1227 1235 #if defined(OPTERON_ERRATUM_108)
1228 1236 if (opteron_erratum_108)
1229 1237 workaround_applied(108);
1230 1238 #endif
1231 1239 #if defined(OPTERON_ERRATUM_109)
1232 1240 if (opteron_erratum_109) {
1233 1241 cmn_err(CE_WARN,
1234 1242 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1235 1243 " processor\nerratum 109 was not detected; updating your"
1236 1244 " system's BIOS to a version\ncontaining this"
1237 1245 " microcode patch is HIGHLY recommended or erroneous"
1238 1246 " system\noperation may occur.\n");
1239 1247 }
1240 1248 #endif
1241 1249 #if defined(OPTERON_ERRATUM_121)
1242 1250 if (opteron_erratum_121)
1243 1251 workaround_applied(121);
1244 1252 #endif
1245 1253 #if defined(OPTERON_ERRATUM_122)
1246 1254 if (opteron_erratum_122)
1247 1255 workaround_applied(122);
1248 1256 #endif
1249 1257 #if defined(OPTERON_ERRATUM_123)
1250 1258 if (opteron_erratum_123) {
1251 1259 cmn_err(CE_WARN,
1252 1260 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1253 1261 " processor\nerratum 123 was not detected; updating your"
1254 1262 " system's BIOS to a version\ncontaining this"
1255 1263 " microcode patch is HIGHLY recommended or erroneous"
1256 1264 " system\noperation may occur.\n");
1257 1265 }
1258 1266 #endif
1259 1267 #if defined(OPTERON_ERRATUM_131)
1260 1268 if (opteron_erratum_131) {
1261 1269 cmn_err(CE_WARN,
1262 1270 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1263 1271 " processor\nerratum 131 was not detected; updating your"
1264 1272 " system's BIOS to a version\ncontaining this"
1265 1273 " microcode patch is HIGHLY recommended or erroneous"
1266 1274 " system\noperation may occur.\n");
1267 1275 }
1268 1276 #endif
1269 1277 #if defined(OPTERON_WORKAROUND_6336786)
1270 1278 if (opteron_workaround_6336786)
1271 1279 workaround_applied(6336786);
1272 1280 #endif
1273 1281 #if defined(OPTERON_WORKAROUND_6323525)
1274 1282 if (opteron_workaround_6323525)
1275 1283 workaround_applied(6323525);
1276 1284 #endif
1277 1285 #if defined(OPTERON_ERRATUM_298)
1278 1286 if (opteron_erratum_298) {
1279 1287 cmn_err(CE_WARN,
1280 1288 "BIOS microcode patch for AMD 64/Opteron(tm)"
1281 1289 " processor\nerratum 298 was not detected; updating your"
1282 1290 " system's BIOS to a version\ncontaining this"
1283 1291 " microcode patch is HIGHLY recommended or erroneous"
1284 1292 " system\noperation may occur.\n");
1285 1293 }
1286 1294 #endif
1287 1295 #if defined(OPTERON_ERRATUM_721)
1288 1296 if (opteron_erratum_721)
1289 1297 workaround_applied(721);
1290 1298 #endif
1291 1299 }
1292 1300
1293 1301 /*
1294 1302 * The procset_slave and procset_master are used to synchronize
1295 1303 * between the control CPU and the target CPU when starting CPUs.
1296 1304 */
1297 1305 static cpuset_t procset_slave, procset_master;
1298 1306
1299 1307 static void
1300 1308 mp_startup_wait(cpuset_t *sp, processorid_t cpuid)
1301 1309 {
1302 1310 cpuset_t tempset;
1303 1311
1304 1312 for (tempset = *sp; !CPU_IN_SET(tempset, cpuid);
1305 1313 tempset = *(volatile cpuset_t *)sp) {
1306 1314 SMT_PAUSE();
1307 1315 }
1308 1316 CPUSET_ATOMIC_DEL(*(cpuset_t *)sp, cpuid);
1309 1317 }
1310 1318
1311 1319 static void
1312 1320 mp_startup_signal(cpuset_t *sp, processorid_t cpuid)
1313 1321 {
1314 1322 cpuset_t tempset;
1315 1323
1316 1324 CPUSET_ATOMIC_ADD(*(cpuset_t *)sp, cpuid);
1317 1325 for (tempset = *sp; CPU_IN_SET(tempset, cpuid);
1318 1326 tempset = *(volatile cpuset_t *)sp) {
1319 1327 SMT_PAUSE();
1320 1328 }
1321 1329 }
1322 1330
1323 1331 int
1324 1332 mp_start_cpu_common(cpu_t *cp, boolean_t boot)
1325 1333 {
1326 1334 _NOTE(ARGUNUSED(boot));
1327 1335
1328 1336 void *ctx;
1329 1337 int delays;
1330 1338 int error = 0;
1331 1339 cpuset_t tempset;
1332 1340 processorid_t cpuid;
1333 1341 #ifndef __xpv
1334 1342 extern void cpupm_init(cpu_t *);
1335 1343 #endif
1336 1344
1337 1345 ASSERT(cp != NULL);
1338 1346 cpuid = cp->cpu_id;
1339 1347 ctx = mach_cpucontext_alloc(cp);
1340 1348 if (ctx == NULL) {
1341 1349 cmn_err(CE_WARN,
1342 1350 "cpu%d: failed to allocate context", cp->cpu_id);
1343 1351 return (EAGAIN);
1344 1352 }
1345 1353 error = mach_cpu_start(cp, ctx);
1346 1354 if (error != 0) {
1347 1355 cmn_err(CE_WARN,
1348 1356 "cpu%d: failed to start, error %d", cp->cpu_id, error);
1349 1357 mach_cpucontext_free(cp, ctx, error);
1350 1358 return (error);
1351 1359 }
1352 1360
1353 1361 for (delays = 0, tempset = procset_slave; !CPU_IN_SET(tempset, cpuid);
1354 1362 delays++) {
1355 1363 if (delays == 500) {
1356 1364 /*
1357 1365 * After five seconds, things are probably looking
1358 1366 * a bit bleak - explain the hang.
1359 1367 */
1360 1368 cmn_err(CE_NOTE, "cpu%d: started, "
1361 1369 "but not running in the kernel yet", cpuid);
1362 1370 } else if (delays > 2000) {
1363 1371 /*
1364 1372 * We waited at least 20 seconds, bail ..
1365 1373 */
1366 1374 error = ETIMEDOUT;
1367 1375 cmn_err(CE_WARN, "cpu%d: timed out", cpuid);
1368 1376 mach_cpucontext_free(cp, ctx, error);
1369 1377 return (error);
1370 1378 }
1371 1379
1372 1380 /*
1373 1381 * wait at least 10ms, then check again..
1374 1382 */
1375 1383 delay(USEC_TO_TICK_ROUNDUP(10000));
1376 1384 tempset = *((volatile cpuset_t *)&procset_slave);
1377 1385 }
1378 1386 CPUSET_ATOMIC_DEL(procset_slave, cpuid);
1379 1387
1380 1388 mach_cpucontext_free(cp, ctx, 0);
1381 1389
1382 1390 #ifndef __xpv
1383 1391 if (tsc_gethrtime_enable)
1384 1392 tsc_sync_master(cpuid);
1385 1393 #endif
1386 1394
1387 1395 if (dtrace_cpu_init != NULL) {
1388 1396 (*dtrace_cpu_init)(cpuid);
1389 1397 }
1390 1398
1391 1399 /*
1392 1400 * During CPU DR operations, the cpu_lock is held by current
1393 1401 * (the control) thread. We can't release the cpu_lock here
1394 1402 * because that will break the CPU DR logic.
1395 1403 * On the other hand, CPUPM and processor group initialization
1396 1404 * routines need to access the cpu_lock. So we invoke those
1397 1405 * routines here on behalf of mp_startup_common().
1398 1406 *
1399 1407 * CPUPM and processor group initialization routines depend
1400 1408 * on the cpuid probing results. Wait for mp_startup_common()
1401 1409 * to signal that cpuid probing is done.
1402 1410 */
1403 1411 mp_startup_wait(&procset_slave, cpuid);
1404 1412 #ifndef __xpv
1405 1413 cpupm_init(cp);
1406 1414 #endif
1407 1415 (void) pg_cpu_init(cp, B_FALSE);
1408 1416 cpu_set_state(cp);
1409 1417 mp_startup_signal(&procset_master, cpuid);
1410 1418
1411 1419 return (0);
1412 1420 }
1413 1421
1414 1422 /*
1415 1423 * Start a single cpu, assuming that the kernel context is available
1416 1424 * to successfully start another cpu.
1417 1425 *
1418 1426 * (For example, real mode code is mapped into the right place
1419 1427 * in memory and is ready to be run.)
1420 1428 */
1421 1429 int
1422 1430 start_cpu(processorid_t who)
1423 1431 {
1424 1432 cpu_t *cp;
1425 1433 int error = 0;
1426 1434 cpuset_t tempset;
1427 1435
1428 1436 ASSERT(who != 0);
1429 1437
1430 1438 /*
1431 1439 * Check if there's at least a Mbyte of kmem available
1432 1440 * before attempting to start the cpu.
1433 1441 */
1434 1442 if (kmem_avail() < 1024 * 1024) {
1435 1443 /*
1436 1444 * Kick off a reap in case that helps us with
1437 1445 * later attempts ..
1438 1446 */
1439 1447 kmem_reap();
1440 1448 return (ENOMEM);
1441 1449 }
1442 1450
1443 1451 /*
1444 1452 * First configure cpu.
1445 1453 */
1446 1454 cp = mp_cpu_configure_common(who, B_TRUE);
1447 1455 ASSERT(cp != NULL);
1448 1456
1449 1457 /*
1450 1458 * Then start cpu.
1451 1459 */
1452 1460 error = mp_start_cpu_common(cp, B_TRUE);
1453 1461 if (error != 0) {
1454 1462 mp_cpu_unconfigure_common(cp, error);
1455 1463 return (error);
1456 1464 }
1457 1465
1458 1466 mutex_exit(&cpu_lock);
1459 1467 tempset = cpu_ready_set;
1460 1468 while (!CPU_IN_SET(tempset, who)) {
1461 1469 drv_usecwait(1);
1462 1470 tempset = *((volatile cpuset_t *)&cpu_ready_set);
1463 1471 }
1464 1472 mutex_enter(&cpu_lock);
1465 1473
1466 1474 return (0);
1467 1475 }
1468 1476
1469 1477 void
1470 1478 start_other_cpus(int cprboot)
1471 1479 {
1472 1480 _NOTE(ARGUNUSED(cprboot));
1473 1481
1474 1482 uint_t who;
1475 1483 uint_t bootcpuid = 0;
1476 1484
1477 1485 /*
1478 1486 * Initialize our own cpu_info.
1479 1487 */
1480 1488 init_cpu_info(CPU);
1481 1489
1482 1490 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_idstr);
1483 1491 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_brandstr);
1484 1492
1485 1493 /*
1486 1494 * Initialize our syscall handlers
1487 1495 */
1488 1496 init_cpu_syscall(CPU);
1489 1497
1490 1498 /*
1491 1499 * Take the boot cpu out of the mp_cpus set because we know
1492 1500 * it's already running. Add it to the cpu_ready_set for
1493 1501 * precisely the same reason.
1494 1502 */
1495 1503 CPUSET_DEL(mp_cpus, bootcpuid);
1496 1504 CPUSET_ADD(cpu_ready_set, bootcpuid);
1497 1505
1498 1506 /*
1499 1507 * skip the rest of this if
1500 1508 * . only 1 cpu dectected and system isn't hotplug-capable
1501 1509 * . not using MP
1502 1510 */
1503 1511 if ((CPUSET_ISNULL(mp_cpus) && plat_dr_support_cpu() == 0) ||
1504 1512 use_mp == 0) {
1505 1513 if (use_mp == 0)
1506 1514 cmn_err(CE_CONT, "?***** Not in MP mode\n");
1507 1515 goto done;
1508 1516 }
1509 1517
1510 1518 /*
1511 1519 * perform such initialization as is needed
1512 1520 * to be able to take CPUs on- and off-line.
1513 1521 */
1514 1522 cpu_pause_init();
1515 1523
1516 1524 xc_init_cpu(CPU); /* initialize processor crosscalls */
1517 1525
1518 1526 if (mach_cpucontext_init() != 0)
1519 1527 goto done;
1520 1528
1521 1529 flushes_require_xcalls = 1;
1522 1530
1523 1531 /*
1524 1532 * We lock our affinity to the master CPU to ensure that all slave CPUs
1525 1533 * do their TSC syncs with the same CPU.
1526 1534 */
1527 1535 affinity_set(CPU_CURRENT);
1528 1536
1529 1537 for (who = 0; who < NCPU; who++) {
1530 1538 if (!CPU_IN_SET(mp_cpus, who))
1531 1539 continue;
1532 1540 ASSERT(who != bootcpuid);
1533 1541
1534 1542 mutex_enter(&cpu_lock);
1535 1543 if (start_cpu(who) != 0)
1536 1544 CPUSET_DEL(mp_cpus, who);
1537 1545 cpu_state_change_notify(who, CPU_SETUP);
1538 1546 mutex_exit(&cpu_lock);
1539 1547 }
1540 1548
1541 1549 /* Free the space allocated to hold the microcode file */
1542 1550 ucode_cleanup();
1543 1551
1544 1552 affinity_clear();
1545 1553
1546 1554 mach_cpucontext_fini();
1547 1555
1548 1556 done:
1549 1557 if (get_hwenv() == HW_NATIVE)
1550 1558 workaround_errata_end();
1551 1559 cmi_post_mpstartup();
1552 1560
1553 1561 if (use_mp && ncpus != boot_max_ncpus) {
1554 1562 cmn_err(CE_NOTE,
1555 1563 "System detected %d cpus, but "
1556 1564 "only %d cpu(s) were enabled during boot.",
1557 1565 boot_max_ncpus, ncpus);
1558 1566 cmn_err(CE_NOTE,
1559 1567 "Use \"boot-ncpus\" parameter to enable more CPU(s). "
1560 1568 "See eeprom(1M).");
1561 1569 }
1562 1570 }
1563 1571
1564 1572 int
1565 1573 mp_cpu_configure(int cpuid)
1566 1574 {
1567 1575 cpu_t *cp;
1568 1576
1569 1577 if (use_mp == 0 || plat_dr_support_cpu() == 0) {
1570 1578 return (ENOTSUP);
1571 1579 }
1572 1580
1573 1581 cp = cpu_get(cpuid);
1574 1582 if (cp != NULL) {
1575 1583 return (EALREADY);
1576 1584 }
1577 1585
1578 1586 /*
1579 1587 * Check if there's at least a Mbyte of kmem available
1580 1588 * before attempting to start the cpu.
1581 1589 */
1582 1590 if (kmem_avail() < 1024 * 1024) {
1583 1591 /*
1584 1592 * Kick off a reap in case that helps us with
1585 1593 * later attempts ..
1586 1594 */
1587 1595 kmem_reap();
1588 1596 return (ENOMEM);
1589 1597 }
1590 1598
1591 1599 cp = mp_cpu_configure_common(cpuid, B_FALSE);
1592 1600 ASSERT(cp != NULL && cpu_get(cpuid) == cp);
1593 1601
1594 1602 return (cp != NULL ? 0 : EAGAIN);
1595 1603 }
1596 1604
1597 1605 int
1598 1606 mp_cpu_unconfigure(int cpuid)
1599 1607 {
1600 1608 cpu_t *cp;
1601 1609
1602 1610 if (use_mp == 0 || plat_dr_support_cpu() == 0) {
1603 1611 return (ENOTSUP);
1604 1612 } else if (cpuid < 0 || cpuid >= max_ncpus) {
1605 1613 return (EINVAL);
1606 1614 }
1607 1615
1608 1616 cp = cpu_get(cpuid);
1609 1617 if (cp == NULL) {
1610 1618 return (ENODEV);
1611 1619 }
1612 1620 mp_cpu_unconfigure_common(cp, 0);
1613 1621
1614 1622 return (0);
1615 1623 }
1616 1624
1617 1625 /*
1618 1626 * Startup function for 'other' CPUs (besides boot cpu).
1619 1627 * Called from real_mode_start.
1620 1628 *
1621 1629 * WARNING: until CPU_READY is set, mp_startup_common and routines called by
1622 1630 * mp_startup_common should not call routines (e.g. kmem_free) that could call
1623 1631 * hat_unload which requires CPU_READY to be set.
1624 1632 */
1625 1633 static void
1626 1634 mp_startup_common(boolean_t boot)
1627 1635 {
1628 1636 cpu_t *cp = CPU;
1629 1637 uchar_t new_x86_featureset[BT_SIZEOFMAP(NUM_X86_FEATURES)];
1630 1638 extern void cpu_event_init_cpu(cpu_t *);
1631 1639
1632 1640 /*
1633 1641 * We need to get TSC on this proc synced (i.e., any delta
1634 1642 * from cpu0 accounted for) as soon as we can, because many
1635 1643 * many things use gethrtime/pc_gethrestime, including
1636 1644 * interrupts, cmn_err, etc.
1637 1645 */
1638 1646
1639 1647 /* Let the control CPU continue into tsc_sync_master() */
1640 1648 mp_startup_signal(&procset_slave, cp->cpu_id);
1641 1649
1642 1650 #ifndef __xpv
1643 1651 if (tsc_gethrtime_enable)
1644 1652 tsc_sync_slave();
1645 1653 #endif
1646 1654
1647 1655 /*
1648 1656 * Once this was done from assembly, but it's safer here; if
1649 1657 * it blocks, we need to be able to swtch() to and from, and
1650 1658 * since we get here by calling t_pc, we need to do that call
1651 1659 * before swtch() overwrites it.
1652 1660 */
1653 1661 (void) (*ap_mlsetup)();
1654 1662
1655 1663 bzero(new_x86_featureset, BT_SIZEOFMAP(NUM_X86_FEATURES));
1656 1664 cpuid_pass1(cp, new_x86_featureset);
1657 1665
1658 1666 #ifndef __xpv
1659 1667 /*
1660 1668 * Program this cpu's PAT
1661 1669 */
1662 1670 if (is_x86_feature(x86_featureset, X86FSET_PAT))
1663 1671 pat_sync();
1664 1672 #endif
1665 1673
1666 1674 /*
1667 1675 * Set up TSC_AUX to contain the cpuid for this processor
1668 1676 * for the rdtscp instruction.
1669 1677 */
1670 1678 if (is_x86_feature(x86_featureset, X86FSET_TSCP))
1671 1679 (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id);
1672 1680
1673 1681 /*
1674 1682 * Initialize this CPU's syscall handlers
1675 1683 */
1676 1684 init_cpu_syscall(cp);
1677 1685
1678 1686 /*
1679 1687 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the
1680 1688 * highest level at which a routine is permitted to block on
1681 1689 * an adaptive mutex (allows for cpu poke interrupt in case
1682 1690 * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks
1683 1691 * device interrupts that may end up in the hat layer issuing cross
1684 1692 * calls before CPU_READY is set.
1685 1693 */
1686 1694 splx(ipltospl(LOCK_LEVEL));
1687 1695 sti();
1688 1696
1689 1697 /*
1690 1698 * Do a sanity check to make sure this new CPU is a sane thing
1691 1699 * to add to the collection of processors running this system.
1692 1700 *
1693 1701 * XXX Clearly this needs to get more sophisticated, if x86
1694 1702 * systems start to get built out of heterogenous CPUs; as is
1695 1703 * likely to happen once the number of processors in a configuration
1696 1704 * gets large enough.
1697 1705 */
1698 1706 if (compare_x86_featureset(x86_featureset, new_x86_featureset) ==
1699 1707 B_FALSE) {
1700 1708 cmn_err(CE_CONT, "cpu%d: featureset\n", cp->cpu_id);
1701 1709 print_x86_featureset(new_x86_featureset);
1702 1710 cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id);
1703 1711 }
1704 1712
1705 1713 /*
1706 1714 * We do not support cpus with mixed monitor/mwait support if the
1707 1715 * boot cpu supports monitor/mwait.
1708 1716 */
1709 1717 if (is_x86_feature(x86_featureset, X86FSET_MWAIT) !=
1710 1718 is_x86_feature(new_x86_featureset, X86FSET_MWAIT))
1711 1719 panic("unsupported mixed cpu monitor/mwait support detected");
1712 1720
1713 1721 /*
1714 1722 * We could be more sophisticated here, and just mark the CPU
1715 1723 * as "faulted" but at this point we'll opt for the easier
1716 1724 * answer of dying horribly. Provided the boot cpu is ok,
1717 1725 * the system can be recovered by booting with use_mp set to zero.
1718 1726 */
1719 1727 if (workaround_errata(cp) != 0)
1720 1728 panic("critical workaround(s) missing for cpu%d", cp->cpu_id);
1721 1729
1722 1730 /*
1723 1731 * We can touch cpu_flags here without acquiring the cpu_lock here
1724 1732 * because the cpu_lock is held by the control CPU which is running
1725 1733 * mp_start_cpu_common().
1726 1734 * Need to clear CPU_QUIESCED flag before calling any function which
1727 1735 * may cause thread context switching, such as kmem_alloc() etc.
1728 1736 * The idle thread checks for CPU_QUIESCED flag and loops for ever if
1729 1737 * it's set. So the startup thread may have no chance to switch back
1730 1738 * again if it's switched away with CPU_QUIESCED set.
1731 1739 */
1732 1740 cp->cpu_flags &= ~(CPU_POWEROFF | CPU_QUIESCED);
1733 1741
1734 1742 /*
1735 1743 * Setup this processor for XSAVE.
1736 1744 */
1737 1745 if (fp_save_mech == FP_XSAVE) {
1738 1746 xsave_setup_msr(cp);
1739 1747 }
1740 1748
1741 1749 cpuid_pass2(cp);
1742 1750 cpuid_pass3(cp);
1743 1751 cpuid_pass4(cp, NULL);
1744 1752
1745 1753 /*
1746 1754 * Correct cpu_idstr and cpu_brandstr on target CPU after
1747 1755 * cpuid_pass1() is done.
1748 1756 */
1749 1757 (void) cpuid_getidstr(cp, cp->cpu_idstr, CPU_IDSTRLEN);
1750 1758 (void) cpuid_getbrandstr(cp, cp->cpu_brandstr, CPU_IDSTRLEN);
1751 1759
1752 1760 cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_EXISTS;
1753 1761
1754 1762 post_startup_cpu_fixups();
1755 1763
1756 1764 cpu_event_init_cpu(cp);
1757 1765
1758 1766 /*
1759 1767 * Enable preemption here so that contention for any locks acquired
1760 1768 * later in mp_startup_common may be preempted if the thread owning
1761 1769 * those locks is continuously executing on other CPUs (for example,
1762 1770 * this CPU must be preemptible to allow other CPUs to pause it during
1763 1771 * their startup phases). It's safe to enable preemption here because
1764 1772 * the CPU state is pretty-much fully constructed.
1765 1773 */
1766 1774 curthread->t_preempt = 0;
1767 1775
1768 1776 /* The base spl should still be at LOCK LEVEL here */
1769 1777 ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL));
1770 1778 set_base_spl(); /* Restore the spl to its proper value */
1771 1779
1772 1780 pghw_physid_create(cp);
1773 1781 /*
1774 1782 * Delegate initialization tasks, which need to access the cpu_lock,
1775 1783 * to mp_start_cpu_common() because we can't acquire the cpu_lock here
1776 1784 * during CPU DR operations.
1777 1785 */
1778 1786 mp_startup_signal(&procset_slave, cp->cpu_id);
1779 1787 mp_startup_wait(&procset_master, cp->cpu_id);
1780 1788 pg_cmt_cpu_startup(cp);
1781 1789
1782 1790 if (boot) {
1783 1791 mutex_enter(&cpu_lock);
1784 1792 cp->cpu_flags &= ~CPU_OFFLINE;
1785 1793 cpu_enable_intr(cp);
1786 1794 cpu_add_active(cp);
1787 1795 mutex_exit(&cpu_lock);
1788 1796 }
1789 1797
1790 1798 /* Enable interrupts */
1791 1799 (void) spl0();
1792 1800
1793 1801 /*
1794 1802 * Fill out cpu_ucode_info. Update microcode if necessary.
1795 1803 */
1796 1804 ucode_check(cp);
1797 1805
1798 1806 #ifndef __xpv
1799 1807 {
1800 1808 /*
1801 1809 * Set up the CPU module for this CPU. This can't be done
1802 1810 * before this CPU is made CPU_READY, because we may (in
1803 1811 * heterogeneous systems) need to go load another CPU module.
1804 1812 * The act of attempting to load a module may trigger a
1805 1813 * cross-call, which will ASSERT unless this cpu is CPU_READY.
1806 1814 */
1807 1815 cmi_hdl_t hdl;
1808 1816
1809 1817 if ((hdl = cmi_init(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU),
1810 1818 cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandid(CPU))) != NULL) {
1811 1819 if (is_x86_feature(x86_featureset, X86FSET_MCA))
1812 1820 cmi_mca_init(hdl);
1813 1821 cp->cpu_m.mcpu_cmi_hdl = hdl;
1814 1822 }
1815 1823 }
1816 1824 #endif /* __xpv */
1817 1825
1818 1826 if (boothowto & RB_DEBUG)
1819 1827 kdi_cpu_init();
1820 1828
1821 1829 /*
1822 1830 * Setting the bit in cpu_ready_set must be the last operation in
1823 1831 * processor initialization; the boot CPU will continue to boot once
1824 1832 * it sees this bit set for all active CPUs.
1825 1833 */
1826 1834 CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id);
1827 1835
1828 1836 (void) mach_cpu_create_device_node(cp, NULL);
1829 1837
1830 1838 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr);
1831 1839 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr);
1832 1840 cmn_err(CE_CONT, "?cpu%d initialization complete - online\n",
1833 1841 cp->cpu_id);
1834 1842
1835 1843 /*
1836 1844 * Now we are done with the startup thread, so free it up.
1837 1845 */
1838 1846 thread_exit();
1839 1847 panic("mp_startup: cannot return");
1840 1848 /*NOTREACHED*/
1841 1849 }
1842 1850
1843 1851 /*
1844 1852 * Startup function for 'other' CPUs at boot time (besides boot cpu).
1845 1853 */
1846 1854 static void
1847 1855 mp_startup_boot(void)
1848 1856 {
1849 1857 mp_startup_common(B_TRUE);
1850 1858 }
1851 1859
1852 1860 /*
1853 1861 * Startup function for hotplug CPUs at runtime.
1854 1862 */
1855 1863 void
1856 1864 mp_startup_hotplug(void)
1857 1865 {
1858 1866 mp_startup_common(B_FALSE);
1859 1867 }
1860 1868
1861 1869 /*
1862 1870 * Start CPU on user request.
1863 1871 */
1864 1872 /* ARGSUSED */
1865 1873 int
1866 1874 mp_cpu_start(struct cpu *cp)
1867 1875 {
1868 1876 ASSERT(MUTEX_HELD(&cpu_lock));
1869 1877 return (0);
1870 1878 }
1871 1879
1872 1880 /*
1873 1881 * Stop CPU on user request.
1874 1882 */
1875 1883 int
1876 1884 mp_cpu_stop(struct cpu *cp)
1877 1885 {
1878 1886 extern int cbe_psm_timer_mode;
1879 1887 ASSERT(MUTEX_HELD(&cpu_lock));
1880 1888
1881 1889 #ifdef __xpv
1882 1890 /*
1883 1891 * We can't offline vcpu0.
1884 1892 */
1885 1893 if (cp->cpu_id == 0)
1886 1894 return (EBUSY);
1887 1895 #endif
1888 1896
1889 1897 /*
1890 1898 * If TIMER_PERIODIC mode is used, CPU0 is the one running it;
1891 1899 * can't stop it. (This is true only for machines with no TSC.)
1892 1900 */
1893 1901
1894 1902 if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0))
1895 1903 return (EBUSY);
1896 1904
1897 1905 return (0);
1898 1906 }
1899 1907
1900 1908 /*
1901 1909 * Take the specified CPU out of participation in interrupts.
1902 1910 */
1903 1911 int
1904 1912 cpu_disable_intr(struct cpu *cp)
1905 1913 {
1906 1914 if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS)
1907 1915 return (EBUSY);
1908 1916
1909 1917 cp->cpu_flags &= ~CPU_ENABLE;
1910 1918 return (0);
1911 1919 }
1912 1920
1913 1921 /*
1914 1922 * Allow the specified CPU to participate in interrupts.
1915 1923 */
1916 1924 void
1917 1925 cpu_enable_intr(struct cpu *cp)
1918 1926 {
1919 1927 ASSERT(MUTEX_HELD(&cpu_lock));
1920 1928 cp->cpu_flags |= CPU_ENABLE;
1921 1929 psm_enable_intr(cp->cpu_id);
1922 1930 }
1923 1931
1924 1932 void
1925 1933 mp_cpu_faulted_enter(struct cpu *cp)
1926 1934 {
1927 1935 #ifdef __xpv
1928 1936 _NOTE(ARGUNUSED(cp));
1929 1937 #else
1930 1938 cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl;
1931 1939
1932 1940 if (hdl != NULL) {
1933 1941 cmi_hdl_hold(hdl);
1934 1942 } else {
1935 1943 hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp),
1936 1944 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp));
1937 1945 }
1938 1946 if (hdl != NULL) {
1939 1947 cmi_faulted_enter(hdl);
1940 1948 cmi_hdl_rele(hdl);
1941 1949 }
1942 1950 #endif
1943 1951 }
1944 1952
1945 1953 void
1946 1954 mp_cpu_faulted_exit(struct cpu *cp)
1947 1955 {
1948 1956 #ifdef __xpv
1949 1957 _NOTE(ARGUNUSED(cp));
1950 1958 #else
1951 1959 cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl;
1952 1960
1953 1961 if (hdl != NULL) {
1954 1962 cmi_hdl_hold(hdl);
1955 1963 } else {
1956 1964 hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp),
1957 1965 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp));
1958 1966 }
1959 1967 if (hdl != NULL) {
1960 1968 cmi_faulted_exit(hdl);
1961 1969 cmi_hdl_rele(hdl);
1962 1970 }
1963 1971 #endif
1964 1972 }
1965 1973
1966 1974 /*
1967 1975 * The following two routines are used as context operators on threads belonging
1968 1976 * to processes with a private LDT (see sysi86). Due to the rarity of such
1969 1977 * processes, these routines are currently written for best code readability and
1970 1978 * organization rather than speed. We could avoid checking x86_featureset at
1971 1979 * every context switch by installing different context ops, depending on
1972 1980 * x86_featureset, at LDT creation time -- one for each combination of fast
1973 1981 * syscall features.
1974 1982 */
1975 1983
1976 1984 /*ARGSUSED*/
1977 1985 void
1978 1986 cpu_fast_syscall_disable(void *arg)
1979 1987 {
1980 1988 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
1981 1989 is_x86_feature(x86_featureset, X86FSET_SEP))
1982 1990 cpu_sep_disable();
1983 1991 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
1984 1992 is_x86_feature(x86_featureset, X86FSET_ASYSC))
1985 1993 cpu_asysc_disable();
1986 1994 }
1987 1995
1988 1996 /*ARGSUSED*/
1989 1997 void
1990 1998 cpu_fast_syscall_enable(void *arg)
1991 1999 {
1992 2000 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
1993 2001 is_x86_feature(x86_featureset, X86FSET_SEP))
1994 2002 cpu_sep_enable();
1995 2003 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
1996 2004 is_x86_feature(x86_featureset, X86FSET_ASYSC))
1997 2005 cpu_asysc_enable();
1998 2006 }
1999 2007
2000 2008 static void
2001 2009 cpu_sep_enable(void)
2002 2010 {
2003 2011 ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP));
2004 2012 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2005 2013
2006 2014 wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL);
2007 2015 }
2008 2016
2009 2017 static void
2010 2018 cpu_sep_disable(void)
2011 2019 {
2012 2020 ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP));
2013 2021 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2014 2022
2015 2023 /*
2016 2024 * Setting the SYSENTER_CS_MSR register to 0 causes software executing
2017 2025 * the sysenter or sysexit instruction to trigger a #gp fault.
2018 2026 */
2019 2027 wrmsr(MSR_INTC_SEP_CS, 0);
2020 2028 }
2021 2029
2022 2030 static void
2023 2031 cpu_asysc_enable(void)
2024 2032 {
2025 2033 ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC));
2026 2034 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2027 2035
2028 2036 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) |
2029 2037 (uint64_t)(uintptr_t)AMD_EFER_SCE);
2030 2038 }
2031 2039
2032 2040 static void
2033 2041 cpu_asysc_disable(void)
2034 2042 {
2035 2043 ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC));
2036 2044 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2037 2045
2038 2046 /*
2039 2047 * Turn off the SCE (syscall enable) bit in the EFER register. Software
2040 2048 * executing syscall or sysret with this bit off will incur a #ud trap.
2041 2049 */
2042 2050 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) &
2043 2051 ~((uint64_t)(uintptr_t)AMD_EFER_SCE));
2044 2052 }
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