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3408 detect socket type of newer AMD CPUs
Reviewed by: Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
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--- old/usr/src/uts/intel/sys/x86_archext.h
+++ new/usr/src/uts/intel/sys/x86_archext.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
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21 21 /*
22 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 24 */
25 25 /*
26 26 * Copyright (c) 2010, Intel Corporation.
27 27 * All rights reserved.
28 28 */
29 29 /*
30 30 * Copyright (c) 2011, Joyent, Inc. All rights reserved.
31 + * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
32 + * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
31 33 */
32 34
33 35 #ifndef _SYS_X86_ARCHEXT_H
34 36 #define _SYS_X86_ARCHEXT_H
35 37
36 38 #if !defined(_ASM)
37 39 #include <sys/regset.h>
38 40 #include <sys/processor.h>
39 41 #include <vm/seg_enum.h>
40 42 #include <vm/page.h>
41 43 #endif /* _ASM */
42 44
43 45 #ifdef __cplusplus
44 46 extern "C" {
45 47 #endif
46 48
47 49 /*
48 50 * cpuid instruction feature flags in %edx (standard function 1)
49 51 */
50 52
51 53 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */
52 54 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */
53 55 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */
54 56 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */
55 57 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */
56 58 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
57 59 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */
58 60 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */
59 61 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
60 62 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */
61 63 /* 0x400 - reserved */
62 64 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */
63 65 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */
64 66 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */
65 67 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */
66 68 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */
67 69 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */
68 70 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
69 71 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */
70 72 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */
71 73 /* 0x100000 - reserved */
72 74 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */
73 75 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */
74 76 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */
75 77 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
76 78 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */
77 79 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */
78 80 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */
79 81 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */
80 82 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */
81 83 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */
82 84 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */
83 85
84 86 #define FMT_CPUID_INTC_EDX \
85 87 "\20" \
86 88 "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr" \
87 89 "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat" \
88 90 "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \
89 91 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
90 92
91 93 /*
92 94 * cpuid instruction feature flags in %ecx (standard function 1)
93 95 */
94 96
95 97 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */
96 98 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */
97 99 /* 0x00000004 - reserved */
98 100 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */
99 101 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
100 102 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */
101 103 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */
102 104 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */
103 105 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */
104 106 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */
105 107 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */
106 108 /* 0x00000800 - reserved */
107 109 /* 0x00001000 - reserved */
108 110 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */
109 111 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */
110 112 /* 0x00008000 - reserved */
111 113 /* 0x00010000 - reserved */
112 114 /* 0x00020000 - reserved */
113 115 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */
114 116 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */
115 117 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */
116 118 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */
117 119 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */
118 120 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */
119 121 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */
120 122 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */
121 123 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
122 124
123 125 #define FMT_CPUID_INTC_ECX \
124 126 "\20" \
125 127 "\35avx\34osxsav\33xsave" \
126 128 "\32aes" \
127 129 "\30popcnt\27movbe\25sse4.2\24sse4.1\23dca" \
128 130 "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \
129 131 "\10est\7smx\6vmx\5dscpl\4mon\2pclmulqdq\1sse3"
130 132
131 133 /*
132 134 * cpuid instruction feature flags in %edx (extended function 0x80000001)
133 135 */
134 136
135 137 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */
136 138 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */
137 139 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */
138 140 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */
139 141 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */
140 142 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
141 143 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */
142 144 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */
143 145 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
144 146 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */
145 147 /* 0x00000400 - sysc on K6m6 */
146 148 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */
147 149 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */
148 150 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */
149 151 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */
150 152 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */
151 153 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */
152 154 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */
153 155 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
154 156 /* 0x00040000 - reserved */
155 157 /* 0x00080000 - reserved */
156 158 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */
157 159 /* 0x00200000 - reserved */
158 160 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */
159 161 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */
160 162 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
161 163 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */
162 164 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */
163 165 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */
164 166 /* 0x10000000 - reserved */
165 167 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */
166 168 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */
167 169 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */
168 170
169 171 #define FMT_CPUID_AMD_EDX \
170 172 "\20" \
171 173 "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \
172 174 "\30mmx\27mmxext\25nx\22pse\21pat" \
173 175 "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \
174 176 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
175 177
176 178 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
177 179 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
178 180 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
179 181 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
180 182 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
181 183 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
182 184 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
183 185 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
184 186 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
185 187 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
186 188 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
187 189 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */
188 190 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
189 191 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
190 192 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
191 193
192 194 #define FMT_CPUID_AMD_ECX \
193 195 "\20" \
194 196 "\22topoext" \
195 197 "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas" \
196 198 "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64"
197 199
198 200 /*
199 201 * Intel now seems to have claimed part of the "extended" function
200 202 * space that we previously for non-Intel implementors to use.
201 203 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
202 204 * is available in long mode i.e. what AMD indicate using bit 0.
203 205 * On the other hand, everything else is labelled as reserved.
204 206 */
205 207 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
206 208
207 209
208 210 #define P5_MCHADDR 0x0
209 211 #define P5_CESR 0x11
210 212 #define P5_CTR0 0x12
211 213 #define P5_CTR1 0x13
212 214
213 215 #define K5_MCHADDR 0x0
214 216 #define K5_MCHTYPE 0x01
215 217 #define K5_TSC 0x10
216 218 #define K5_TR12 0x12
217 219
218 220 #define REG_PAT 0x277
219 221
220 222 #define REG_MC0_CTL 0x400
221 223 #define REG_MC5_MISC 0x417
222 224 #define REG_PERFCTR0 0xc1
223 225 #define REG_PERFCTR1 0xc2
224 226
225 227 #define REG_PERFEVNT0 0x186
226 228 #define REG_PERFEVNT1 0x187
227 229
228 230 #define REG_TSC 0x10 /* timestamp counter */
229 231 #define REG_APIC_BASE_MSR 0x1b
230 232 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */
231 233
232 234 #if !defined(__xpv)
233 235 /*
234 236 * AMD C1E
235 237 */
236 238 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055
237 239 #define AMD_ACTONCMPHALT_SHIFT 27
238 240 #define AMD_ACTONCMPHALT_MASK 3
239 241 #endif
240 242
241 243 #define MSR_DEBUGCTL 0x1d9
242 244
243 245 #define DEBUGCTL_LBR 0x01
244 246 #define DEBUGCTL_BTF 0x02
245 247
246 248 /* Intel P6, AMD */
247 249 #define MSR_LBR_FROM 0x1db
248 250 #define MSR_LBR_TO 0x1dc
249 251 #define MSR_LEX_FROM 0x1dd
250 252 #define MSR_LEX_TO 0x1de
251 253
252 254 /* Intel P4 (pre-Prescott, non P4 M) */
253 255 #define MSR_P4_LBSTK_TOS 0x1da
254 256 #define MSR_P4_LBSTK_0 0x1db
255 257 #define MSR_P4_LBSTK_1 0x1dc
256 258 #define MSR_P4_LBSTK_2 0x1dd
257 259 #define MSR_P4_LBSTK_3 0x1de
258 260
259 261 /* Intel Pentium M */
260 262 #define MSR_P6M_LBSTK_TOS 0x1c9
261 263 #define MSR_P6M_LBSTK_0 0x040
262 264 #define MSR_P6M_LBSTK_1 0x041
263 265 #define MSR_P6M_LBSTK_2 0x042
264 266 #define MSR_P6M_LBSTK_3 0x043
265 267 #define MSR_P6M_LBSTK_4 0x044
266 268 #define MSR_P6M_LBSTK_5 0x045
267 269 #define MSR_P6M_LBSTK_6 0x046
268 270 #define MSR_P6M_LBSTK_7 0x047
269 271
270 272 /* Intel P4 (Prescott) */
271 273 #define MSR_PRP4_LBSTK_TOS 0x1da
272 274 #define MSR_PRP4_LBSTK_FROM_0 0x680
273 275 #define MSR_PRP4_LBSTK_FROM_1 0x681
274 276 #define MSR_PRP4_LBSTK_FROM_2 0x682
275 277 #define MSR_PRP4_LBSTK_FROM_3 0x683
276 278 #define MSR_PRP4_LBSTK_FROM_4 0x684
277 279 #define MSR_PRP4_LBSTK_FROM_5 0x685
278 280 #define MSR_PRP4_LBSTK_FROM_6 0x686
279 281 #define MSR_PRP4_LBSTK_FROM_7 0x687
280 282 #define MSR_PRP4_LBSTK_FROM_8 0x688
281 283 #define MSR_PRP4_LBSTK_FROM_9 0x689
282 284 #define MSR_PRP4_LBSTK_FROM_10 0x68a
283 285 #define MSR_PRP4_LBSTK_FROM_11 0x68b
284 286 #define MSR_PRP4_LBSTK_FROM_12 0x68c
285 287 #define MSR_PRP4_LBSTK_FROM_13 0x68d
286 288 #define MSR_PRP4_LBSTK_FROM_14 0x68e
287 289 #define MSR_PRP4_LBSTK_FROM_15 0x68f
288 290 #define MSR_PRP4_LBSTK_TO_0 0x6c0
289 291 #define MSR_PRP4_LBSTK_TO_1 0x6c1
290 292 #define MSR_PRP4_LBSTK_TO_2 0x6c2
291 293 #define MSR_PRP4_LBSTK_TO_3 0x6c3
292 294 #define MSR_PRP4_LBSTK_TO_4 0x6c4
293 295 #define MSR_PRP4_LBSTK_TO_5 0x6c5
294 296 #define MSR_PRP4_LBSTK_TO_6 0x6c6
295 297 #define MSR_PRP4_LBSTK_TO_7 0x6c7
296 298 #define MSR_PRP4_LBSTK_TO_8 0x6c8
297 299 #define MSR_PRP4_LBSTK_TO_9 0x6c9
298 300 #define MSR_PRP4_LBSTK_TO_10 0x6ca
299 301 #define MSR_PRP4_LBSTK_TO_11 0x6cb
300 302 #define MSR_PRP4_LBSTK_TO_12 0x6cc
301 303 #define MSR_PRP4_LBSTK_TO_13 0x6cd
302 304 #define MSR_PRP4_LBSTK_TO_14 0x6ce
303 305 #define MSR_PRP4_LBSTK_TO_15 0x6cf
304 306
305 307 #define MCI_CTL_VALUE 0xffffffff
306 308
307 309 #define MTRR_TYPE_UC 0
308 310 #define MTRR_TYPE_WC 1
309 311 #define MTRR_TYPE_WT 4
310 312 #define MTRR_TYPE_WP 5
311 313 #define MTRR_TYPE_WB 6
312 314 #define MTRR_TYPE_UC_ 7
313 315
314 316 /*
315 317 * For Solaris we set up the page attritubute table in the following way:
316 318 * PAT0 Write-Back
317 319 * PAT1 Write-Through
318 320 * PAT2 Unchacheable-
319 321 * PAT3 Uncacheable
320 322 * PAT4 Write-Back
321 323 * PAT5 Write-Through
322 324 * PAT6 Write-Combine
323 325 * PAT7 Uncacheable
324 326 * The only difference from h/w default is entry 6.
325 327 */
326 328 #define PAT_DEFAULT_ATTRIBUTE \
327 329 ((uint64_t)MTRR_TYPE_WB | \
328 330 ((uint64_t)MTRR_TYPE_WT << 8) | \
329 331 ((uint64_t)MTRR_TYPE_UC_ << 16) | \
330 332 ((uint64_t)MTRR_TYPE_UC << 24) | \
331 333 ((uint64_t)MTRR_TYPE_WB << 32) | \
332 334 ((uint64_t)MTRR_TYPE_WT << 40) | \
333 335 ((uint64_t)MTRR_TYPE_WC << 48) | \
334 336 ((uint64_t)MTRR_TYPE_UC << 56))
335 337
336 338 #define X86FSET_LARGEPAGE 0
337 339 #define X86FSET_TSC 1
338 340 #define X86FSET_MSR 2
339 341 #define X86FSET_MTRR 3
340 342 #define X86FSET_PGE 4
341 343 #define X86FSET_DE 5
342 344 #define X86FSET_CMOV 6
343 345 #define X86FSET_MMX 7
344 346 #define X86FSET_MCA 8
345 347 #define X86FSET_PAE 9
346 348 #define X86FSET_CX8 10
347 349 #define X86FSET_PAT 11
348 350 #define X86FSET_SEP 12
349 351 #define X86FSET_SSE 13
350 352 #define X86FSET_SSE2 14
351 353 #define X86FSET_HTT 15
352 354 #define X86FSET_ASYSC 16
353 355 #define X86FSET_NX 17
354 356 #define X86FSET_SSE3 18
355 357 #define X86FSET_CX16 19
356 358 #define X86FSET_CMP 20
357 359 #define X86FSET_TSCP 21
358 360 #define X86FSET_MWAIT 22
359 361 #define X86FSET_SSE4A 23
360 362 #define X86FSET_CPUID 24
361 363 #define X86FSET_SSSE3 25
362 364 #define X86FSET_SSE4_1 26
363 365 #define X86FSET_SSE4_2 27
364 366 #define X86FSET_1GPG 28
365 367 #define X86FSET_CLFSH 29
366 368 #define X86FSET_64 30
367 369 #define X86FSET_AES 31
368 370 #define X86FSET_PCLMULQDQ 32
369 371 #define X86FSET_XSAVE 33
370 372 #define X86FSET_AVX 34
371 373 #define X86FSET_VMX 35
372 374 #define X86FSET_SVM 36
373 375 #define X86FSET_TOPOEXT 37
374 376
375 377 /*
376 378 * flags to patch tsc_read routine.
377 379 */
378 380 #define X86_NO_TSC 0x0
379 381 #define X86_HAVE_TSCP 0x1
380 382 #define X86_TSC_MFENCE 0x2
381 383 #define X86_TSC_LFENCE 0x4
382 384
383 385 /*
384 386 * Intel Deep C-State invariant TSC in leaf 0x80000007.
385 387 */
386 388 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
387 389
388 390 /*
389 391 * Intel Deep C-state always-running local APIC timer
390 392 */
391 393 #define CPUID_CSTATE_ARAT (0x4)
392 394
393 395 /*
394 396 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3].
395 397 */
396 398 #define CPUID_EPB_SUPPORT (1 << 3)
397 399
398 400 /*
399 401 * Intel TSC deadline timer
400 402 */
401 403 #define CPUID_DEADLINE_TSC (1 << 24)
402 404
403 405 /*
404 406 * x86_type is a legacy concept; this is supplanted
405 407 * for most purposes by x86_featureset; modern CPUs
406 408 * should be X86_TYPE_OTHER
407 409 */
408 410 #define X86_TYPE_OTHER 0
409 411 #define X86_TYPE_486 1
410 412 #define X86_TYPE_P5 2
411 413 #define X86_TYPE_P6 3
412 414 #define X86_TYPE_CYRIX_486 4
413 415 #define X86_TYPE_CYRIX_6x86L 5
414 416 #define X86_TYPE_CYRIX_6x86 6
415 417 #define X86_TYPE_CYRIX_GXm 7
416 418 #define X86_TYPE_CYRIX_6x86MX 8
417 419 #define X86_TYPE_CYRIX_MediaGX 9
418 420 #define X86_TYPE_CYRIX_MII 10
419 421 #define X86_TYPE_VIA_CYRIX_III 11
420 422 #define X86_TYPE_P4 12
421 423
422 424 /*
423 425 * x86_vendor allows us to select between
424 426 * implementation features and helps guide
425 427 * the interpretation of the cpuid instruction.
426 428 */
427 429 #define X86_VENDOR_Intel 0
428 430 #define X86_VENDORSTR_Intel "GenuineIntel"
429 431
430 432 #define X86_VENDOR_IntelClone 1
431 433
432 434 #define X86_VENDOR_AMD 2
433 435 #define X86_VENDORSTR_AMD "AuthenticAMD"
434 436
435 437 #define X86_VENDOR_Cyrix 3
436 438 #define X86_VENDORSTR_CYRIX "CyrixInstead"
437 439
438 440 #define X86_VENDOR_UMC 4
439 441 #define X86_VENDORSTR_UMC "UMC UMC UMC "
440 442
441 443 #define X86_VENDOR_NexGen 5
442 444 #define X86_VENDORSTR_NexGen "NexGenDriven"
443 445
444 446 #define X86_VENDOR_Centaur 6
445 447 #define X86_VENDORSTR_Centaur "CentaurHauls"
446 448
447 449 #define X86_VENDOR_Rise 7
448 450 #define X86_VENDORSTR_Rise "RiseRiseRise"
449 451
450 452 #define X86_VENDOR_SiS 8
451 453 #define X86_VENDORSTR_SiS "SiS SiS SiS "
452 454
453 455 #define X86_VENDOR_TM 9
454 456 #define X86_VENDORSTR_TM "GenuineTMx86"
455 457
456 458 #define X86_VENDOR_NSC 10
457 459 #define X86_VENDORSTR_NSC "Geode by NSC"
458 460
459 461 /*
460 462 * Vendor string max len + \0
461 463 */
462 464 #define X86_VENDOR_STRLEN 13
463 465
464 466 /*
465 467 * Some vendor/family/model/stepping ranges are commonly grouped under
466 468 * a single identifying banner by the vendor. The following encode
467 469 * that "revision" in a uint32_t with the 8 most significant bits
468 470 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the
469 471 * family, and the remaining 16 typically forming a bitmask of revisions
470 472 * within that family with more significant bits indicating "later" revisions.
471 473 */
472 474
473 475 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u
474 476 #define _X86_CHIPREV_VENDOR_SHIFT 24
475 477 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u
476 478 #define _X86_CHIPREV_FAMILY_SHIFT 16
477 479 #define _X86_CHIPREV_REV_MASK 0x0000ffffu
478 480
479 481 #define _X86_CHIPREV_VENDOR(x) \
480 482 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT)
481 483 #define _X86_CHIPREV_FAMILY(x) \
482 484 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT)
483 485 #define _X86_CHIPREV_REV(x) \
484 486 ((x) & _X86_CHIPREV_REV_MASK)
485 487
486 488 /* True if x matches in vendor and family and if x matches the given rev mask */
487 489 #define X86_CHIPREV_MATCH(x, mask) \
488 490 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \
489 491 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \
490 492 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0))
491 493
492 494 /* True if x matches in vendor and family, and rev is at least minx */
493 495 #define X86_CHIPREV_ATLEAST(x, minx) \
494 496 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
495 497 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \
496 498 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx))
497 499
498 500 #define _X86_CHIPREV_MKREV(vendor, family, rev) \
499 501 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \
500 502 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev))
501 503
502 504 /* True if x matches in vendor, and family is at least minx */
503 505 #define X86_CHIPFAM_ATLEAST(x, minx) \
504 506 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
505 507 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx))
506 508
507 509 /* Revision default */
508 510 #define X86_CHIPREV_UNKNOWN 0x0
509 511
510 512 /*
511 513 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are
512 514 * sufficiently different that we will distinguish them; in all other
513 515 * case we will identify the major revision.
514 516 */
515 517 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001)
516 518 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002)
517 519 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004)
518 520 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008)
519 521 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010)
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520 522 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020)
521 523 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040)
522 524
523 525 /*
524 526 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only.
525 527 */
526 528 #define X86_CHIPREV_AMD_10_REV_A \
527 529 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001)
528 530 #define X86_CHIPREV_AMD_10_REV_B \
529 531 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002)
530 -#define X86_CHIPREV_AMD_10_REV_C \
532 +#define X86_CHIPREV_AMD_10_REV_C2 \
531 533 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004)
532 -#define X86_CHIPREV_AMD_10_REV_D \
534 +#define X86_CHIPREV_AMD_10_REV_C3 \
533 535 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008)
536 +#define X86_CHIPREV_AMD_10_REV_D0 \
537 + _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010)
538 +#define X86_CHIPREV_AMD_10_REV_D1 \
539 + _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020)
540 +#define X86_CHIPREV_AMD_10_REV_E \
541 + _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040)
534 542
535 543 /*
536 544 * Definitions for AMD Family 0x11.
537 545 */
538 -#define X86_CHIPREV_AMD_11 \
539 - _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0001)
546 +#define X86_CHIPREV_AMD_11_REV_B \
547 + _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002)
540 548
549 +/*
550 + * Definitions for AMD Family 0x12.
551 + */
552 +#define X86_CHIPREV_AMD_12_REV_B \
553 + _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002)
541 554
542 555 /*
556 + * Definitions for AMD Family 0x14.
557 + */
558 +#define X86_CHIPREV_AMD_14_REV_B \
559 + _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002)
560 +#define X86_CHIPREV_AMD_14_REV_C \
561 + _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004)
562 +
563 +/*
564 + * Definitions for AMD Family 0x15
565 + */
566 +#define X86_CHIPREV_AMD_15OR_REV_B2 \
567 + _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001)
568 +
569 +#define X86_CHIPREV_AMD_15TN_REV_A1 \
570 + _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002)
571 +
572 +/*
543 573 * Various socket/package types, extended as the need to distinguish
544 574 * a new type arises. The top 8 byte identfies the vendor and the
545 575 * remaining 24 bits describe 24 socket types.
546 576 */
547 577
548 578 #define _X86_SOCKET_VENDOR_SHIFT 24
549 579 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT)
550 580 #define _X86_SOCKET_TYPE_MASK 0x00ffffff
551 581 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK)
552 582
553 583 #define _X86_SOCKET_MKVAL(vendor, bitval) \
554 584 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval))
555 585
556 586 #define X86_SOCKET_MATCH(s, mask) \
557 587 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \
558 588 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0)
559 589
560 590 #define X86_SOCKET_UNKNOWN 0x0
561 591 /*
562 592 * AMD socket types
563 593 */
564 594 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001)
565 595 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002)
566 596 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004)
567 597 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008)
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568 598 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010)
569 599 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020)
570 600 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040)
571 601 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080)
572 602 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100)
573 603 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200)
574 604 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400)
575 605 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800)
576 606 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000)
577 607 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000)
608 +#define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000)
609 +#define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000)
610 +#define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000)
611 +#define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000)
612 +#define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000)
613 +#define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000)
614 +#define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000)
615 +#define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000)
578 616
579 617 /*
580 618 * xgetbv/xsetbv support
581 619 */
582 620
583 621 #define XFEATURE_ENABLED_MASK 0x0
584 622 /*
585 623 * XFEATURE_ENABLED_MASK values (eax)
586 624 */
587 625 #define XFEATURE_LEGACY_FP 0x1
588 626 #define XFEATURE_SSE 0x2
589 627 #define XFEATURE_AVX 0x4
590 628 #define XFEATURE_MAX XFEATURE_AVX
591 629 #define XFEATURE_FP_ALL (XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX)
592 630
593 631 #if !defined(_ASM)
594 632
595 633 #if defined(_KERNEL) || defined(_KMEMUSER)
596 634
597 635 #define NUM_X86_FEATURES 38
598 636 extern uchar_t x86_featureset[];
599 637
600 638 extern void free_x86_featureset(void *featureset);
601 639 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
602 640 extern void add_x86_feature(void *featureset, uint_t feature);
603 641 extern void remove_x86_feature(void *featureset, uint_t feature);
604 642 extern boolean_t compare_x86_featureset(void *setA, void *setB);
605 643 extern void print_x86_featureset(void *featureset);
606 644
607 645
608 646 extern uint_t x86_type;
609 647 extern uint_t x86_vendor;
610 648 extern uint_t x86_clflush_size;
611 649
612 650 extern uint_t pentiumpro_bug4046376;
613 651 extern uint_t pentiumpro_bug4064495;
614 652
615 653 extern uint_t enable486;
616 654
617 655 extern const char CyrixInstead[];
618 656
619 657 #endif
620 658
621 659 #if defined(_KERNEL)
622 660
623 661 /*
624 662 * This structure is used to pass arguments and get return values back
625 663 * from the CPUID instruction in __cpuid_insn() routine.
626 664 */
627 665 struct cpuid_regs {
628 666 uint32_t cp_eax;
629 667 uint32_t cp_ebx;
630 668 uint32_t cp_ecx;
631 669 uint32_t cp_edx;
632 670 };
633 671
634 672 /*
635 673 * Utility functions to get/set extended control registers (XCR)
636 674 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
637 675 */
638 676 extern uint64_t get_xcr(uint_t);
639 677 extern void set_xcr(uint_t, uint64_t);
640 678
641 679 extern uint64_t rdmsr(uint_t);
642 680 extern void wrmsr(uint_t, const uint64_t);
643 681 extern uint64_t xrdmsr(uint_t);
644 682 extern void xwrmsr(uint_t, const uint64_t);
645 683 extern int checked_rdmsr(uint_t, uint64_t *);
646 684 extern int checked_wrmsr(uint_t, uint64_t);
647 685
648 686 extern void invalidate_cache(void);
649 687 extern ulong_t getcr4(void);
650 688 extern void setcr4(ulong_t);
651 689
652 690 extern void mtrr_sync(void);
653 691
654 692 extern void cpu_fast_syscall_enable(void *);
655 693 extern void cpu_fast_syscall_disable(void *);
656 694
657 695 struct cpu;
658 696
659 697 extern int cpuid_checkpass(struct cpu *, int);
660 698 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *);
661 699 extern uint32_t __cpuid_insn(struct cpuid_regs *);
662 700 extern int cpuid_getbrandstr(struct cpu *, char *, size_t);
663 701 extern int cpuid_getidstr(struct cpu *, char *, size_t);
664 702 extern const char *cpuid_getvendorstr(struct cpu *);
665 703 extern uint_t cpuid_getvendor(struct cpu *);
666 704 extern uint_t cpuid_getfamily(struct cpu *);
667 705 extern uint_t cpuid_getmodel(struct cpu *);
668 706 extern uint_t cpuid_getstep(struct cpu *);
669 707 extern uint_t cpuid_getsig(struct cpu *);
670 708 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *);
671 709 extern uint_t cpuid_get_ncore_per_chip(struct cpu *);
672 710 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *);
673 711 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *);
674 712 extern int cpuid_get_chipid(struct cpu *);
675 713 extern id_t cpuid_get_coreid(struct cpu *);
676 714 extern int cpuid_get_pkgcoreid(struct cpu *);
677 715 extern int cpuid_get_clogid(struct cpu *);
678 716 extern int cpuid_get_cacheid(struct cpu *);
679 717 extern uint32_t cpuid_get_apicid(struct cpu *);
680 718 extern uint_t cpuid_get_procnodeid(struct cpu *cpu);
681 719 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu);
682 720 extern uint_t cpuid_get_compunitid(struct cpu *cpu);
683 721 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu);
684 722 extern int cpuid_is_cmt(struct cpu *);
685 723 extern int cpuid_syscall32_insn(struct cpu *);
686 724 extern int getl2cacheinfo(struct cpu *, int *, int *, int *);
687 725
688 726 extern uint32_t cpuid_getchiprev(struct cpu *);
689 727 extern const char *cpuid_getchiprevstr(struct cpu *);
690 728 extern uint32_t cpuid_getsockettype(struct cpu *);
691 729 extern const char *cpuid_getsocketstr(struct cpu *);
692 730
693 731 extern int cpuid_have_cr8access(struct cpu *);
694 732
695 733 extern int cpuid_opteron_erratum(struct cpu *, uint_t);
696 734
697 735 struct cpuid_info;
698 736
699 737 extern void setx86isalist(void);
700 738 extern void cpuid_alloc_space(struct cpu *);
701 739 extern void cpuid_free_space(struct cpu *);
702 740 extern void cpuid_pass1(struct cpu *, uchar_t *);
703 741 extern void cpuid_pass2(struct cpu *);
704 742 extern void cpuid_pass3(struct cpu *);
705 743 extern uint_t cpuid_pass4(struct cpu *);
706 744 extern void cpuid_set_cpu_properties(void *, processorid_t,
707 745 struct cpuid_info *);
708 746
709 747 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *);
710 748 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t);
711 749
712 750 #if !defined(__xpv)
713 751 extern uint32_t *cpuid_mwait_alloc(struct cpu *);
714 752 extern void cpuid_mwait_free(struct cpu *);
715 753 extern int cpuid_deep_cstates_supported(void);
716 754 extern int cpuid_arat_supported(void);
717 755 extern int cpuid_iepb_supported(struct cpu *);
718 756 extern int cpuid_deadline_tsc_supported(void);
719 757 extern int vmware_platform(void);
720 758 #endif
721 759
722 760 struct cpu_ucode_info;
723 761
724 762 extern void ucode_alloc_space(struct cpu *);
725 763 extern void ucode_free_space(struct cpu *);
726 764 extern void ucode_check(struct cpu *);
727 765 extern void ucode_cleanup();
728 766
729 767 #if !defined(__xpv)
730 768 extern char _tsc_mfence_start;
731 769 extern char _tsc_mfence_end;
732 770 extern char _tscp_start;
733 771 extern char _tscp_end;
734 772 extern char _no_rdtsc_start;
735 773 extern char _no_rdtsc_end;
736 774 extern char _tsc_lfence_start;
737 775 extern char _tsc_lfence_end;
738 776 #endif
739 777
740 778 #if !defined(__xpv)
741 779 extern char bcopy_patch_start;
742 780 extern char bcopy_patch_end;
743 781 extern char bcopy_ck_size;
744 782 #endif
745 783
746 784 extern void post_startup_cpu_fixups(void);
747 785
748 786 extern uint_t workaround_errata(struct cpu *);
749 787
750 788 #if defined(OPTERON_ERRATUM_93)
751 789 extern int opteron_erratum_93;
752 790 #endif
753 791
754 792 #if defined(OPTERON_ERRATUM_91)
755 793 extern int opteron_erratum_91;
756 794 #endif
757 795
758 796 #if defined(OPTERON_ERRATUM_100)
759 797 extern int opteron_erratum_100;
760 798 #endif
761 799
762 800 #if defined(OPTERON_ERRATUM_121)
763 801 extern int opteron_erratum_121;
764 802 #endif
765 803
766 804 #if defined(OPTERON_WORKAROUND_6323525)
767 805 extern int opteron_workaround_6323525;
768 806 extern void patch_workaround_6323525(void);
769 807 #endif
770 808
771 809 #if !defined(__xpv)
772 810 extern void determine_platform(void);
773 811 #endif
774 812 extern int get_hwenv(void);
775 813 extern int is_controldom(void);
776 814
777 815 extern void xsave_setup_msr(struct cpu *);
778 816
779 817 /*
780 818 * Defined hardware environments
781 819 */
782 820 #define HW_NATIVE 0x00 /* Running on bare metal */
783 821 #define HW_XEN_PV 0x01 /* Running on Xen Hypervisor paravirutualized */
784 822 #define HW_XEN_HVM 0x02 /* Running on Xen hypervisor HVM */
785 823 #define HW_VMWARE 0x03 /* Running on VMware hypervisor */
786 824
787 825 #endif /* _KERNEL */
788 826
789 827 #endif
790 828
791 829 #ifdef __cplusplus
792 830 }
793 831 #endif
794 832
795 833 #endif /* _SYS_X86_ARCHEXT_H */
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