1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 */
25 /*
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
28 */
29 /*
30 * Copyright (c) 2011, Joyent, Inc. All rights reserved.
31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
33 */
34
35 #ifndef _SYS_X86_ARCHEXT_H
36 #define _SYS_X86_ARCHEXT_H
37
38 #if !defined(_ASM)
39 #include <sys/regset.h>
40 #include <sys/processor.h>
41 #include <vm/seg_enum.h>
42 #include <vm/page.h>
43 #endif /* _ASM */
44
45 #ifdef __cplusplus
46 extern "C" {
47 #endif
48
49 /*
50 * cpuid instruction feature flags in %edx (standard function 1)
51 */
52
53 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */
54 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */
55 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */
56 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */
57 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */
58 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
59 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */
60 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */
61 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
62 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */
63 /* 0x400 - reserved */
64 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */
65 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */
66 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */
67 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */
68 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */
69 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */
70 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
71 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */
72 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */
73 /* 0x100000 - reserved */
74 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */
75 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */
76 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */
77 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
78 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */
79 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */
80 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */
81 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */
82 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */
83 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */
84 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */
85
86 #define FMT_CPUID_INTC_EDX \
87 "\20" \
88 "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr" \
89 "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat" \
90 "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \
91 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
92
93 /*
94 * cpuid instruction feature flags in %ecx (standard function 1)
95 */
96
97 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */
98 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */
99 /* 0x00000004 - reserved */
100 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */
101 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
102 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */
103 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */
104 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */
105 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */
106 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */
107 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */
108 /* 0x00000800 - reserved */
109 /* 0x00001000 - reserved */
110 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */
111 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */
112 /* 0x00008000 - reserved */
113 /* 0x00010000 - reserved */
114 /* 0x00020000 - reserved */
115 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */
116 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */
117 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */
118 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */
119 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */
120 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */
121 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */
122 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */
123 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
124
125 #define FMT_CPUID_INTC_ECX \
126 "\20" \
127 "\35avx\34osxsav\33xsave" \
128 "\32aes" \
129 "\30popcnt\27movbe\25sse4.2\24sse4.1\23dca" \
130 "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \
131 "\10est\7smx\6vmx\5dscpl\4mon\2pclmulqdq\1sse3"
132
133 /*
134 * cpuid instruction feature flags in %edx (extended function 0x80000001)
135 */
136
137 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */
138 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */
139 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */
140 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */
141 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */
142 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
143 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */
144 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */
145 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
146 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */
147 /* 0x00000400 - sysc on K6m6 */
148 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */
149 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */
150 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */
151 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */
152 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */
153 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */
154 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */
155 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
156 /* 0x00040000 - reserved */
157 /* 0x00080000 - reserved */
158 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */
159 /* 0x00200000 - reserved */
160 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */
161 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */
162 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
163 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */
164 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */
165 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */
166 /* 0x10000000 - reserved */
167 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */
168 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */
169 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */
170
171 #define FMT_CPUID_AMD_EDX \
172 "\20" \
173 "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \
174 "\30mmx\27mmxext\25nx\22pse\21pat" \
175 "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \
176 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
177
178 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
179 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
180 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
181 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
182 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
183 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
184 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
185 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
186 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
187 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
188 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
189 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */
190 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
191 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
192 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
193
194 #define FMT_CPUID_AMD_ECX \
195 "\20" \
196 "\22topoext" \
197 "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas" \
198 "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64"
199
200 /*
201 * Intel now seems to have claimed part of the "extended" function
202 * space that we previously for non-Intel implementors to use.
203 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
204 * is available in long mode i.e. what AMD indicate using bit 0.
205 * On the other hand, everything else is labelled as reserved.
206 */
207 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
208
209
210 #define P5_MCHADDR 0x0
211 #define P5_CESR 0x11
212 #define P5_CTR0 0x12
213 #define P5_CTR1 0x13
214
215 #define K5_MCHADDR 0x0
216 #define K5_MCHTYPE 0x01
217 #define K5_TSC 0x10
218 #define K5_TR12 0x12
219
220 #define REG_PAT 0x277
221
222 #define REG_MC0_CTL 0x400
223 #define REG_MC5_MISC 0x417
224 #define REG_PERFCTR0 0xc1
225 #define REG_PERFCTR1 0xc2
226
227 #define REG_PERFEVNT0 0x186
228 #define REG_PERFEVNT1 0x187
229
230 #define REG_TSC 0x10 /* timestamp counter */
231 #define REG_APIC_BASE_MSR 0x1b
232 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */
233
234 #if !defined(__xpv)
235 /*
236 * AMD C1E
237 */
238 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055
239 #define AMD_ACTONCMPHALT_SHIFT 27
240 #define AMD_ACTONCMPHALT_MASK 3
241 #endif
242
243 #define MSR_DEBUGCTL 0x1d9
244
245 #define DEBUGCTL_LBR 0x01
246 #define DEBUGCTL_BTF 0x02
247
248 /* Intel P6, AMD */
249 #define MSR_LBR_FROM 0x1db
250 #define MSR_LBR_TO 0x1dc
251 #define MSR_LEX_FROM 0x1dd
252 #define MSR_LEX_TO 0x1de
253
254 /* Intel P4 (pre-Prescott, non P4 M) */
255 #define MSR_P4_LBSTK_TOS 0x1da
256 #define MSR_P4_LBSTK_0 0x1db
257 #define MSR_P4_LBSTK_1 0x1dc
258 #define MSR_P4_LBSTK_2 0x1dd
259 #define MSR_P4_LBSTK_3 0x1de
260
261 /* Intel Pentium M */
262 #define MSR_P6M_LBSTK_TOS 0x1c9
263 #define MSR_P6M_LBSTK_0 0x040
264 #define MSR_P6M_LBSTK_1 0x041
265 #define MSR_P6M_LBSTK_2 0x042
266 #define MSR_P6M_LBSTK_3 0x043
267 #define MSR_P6M_LBSTK_4 0x044
268 #define MSR_P6M_LBSTK_5 0x045
269 #define MSR_P6M_LBSTK_6 0x046
270 #define MSR_P6M_LBSTK_7 0x047
271
272 /* Intel P4 (Prescott) */
273 #define MSR_PRP4_LBSTK_TOS 0x1da
274 #define MSR_PRP4_LBSTK_FROM_0 0x680
275 #define MSR_PRP4_LBSTK_FROM_1 0x681
276 #define MSR_PRP4_LBSTK_FROM_2 0x682
277 #define MSR_PRP4_LBSTK_FROM_3 0x683
278 #define MSR_PRP4_LBSTK_FROM_4 0x684
279 #define MSR_PRP4_LBSTK_FROM_5 0x685
280 #define MSR_PRP4_LBSTK_FROM_6 0x686
281 #define MSR_PRP4_LBSTK_FROM_7 0x687
282 #define MSR_PRP4_LBSTK_FROM_8 0x688
283 #define MSR_PRP4_LBSTK_FROM_9 0x689
284 #define MSR_PRP4_LBSTK_FROM_10 0x68a
285 #define MSR_PRP4_LBSTK_FROM_11 0x68b
286 #define MSR_PRP4_LBSTK_FROM_12 0x68c
287 #define MSR_PRP4_LBSTK_FROM_13 0x68d
288 #define MSR_PRP4_LBSTK_FROM_14 0x68e
289 #define MSR_PRP4_LBSTK_FROM_15 0x68f
290 #define MSR_PRP4_LBSTK_TO_0 0x6c0
291 #define MSR_PRP4_LBSTK_TO_1 0x6c1
292 #define MSR_PRP4_LBSTK_TO_2 0x6c2
293 #define MSR_PRP4_LBSTK_TO_3 0x6c3
294 #define MSR_PRP4_LBSTK_TO_4 0x6c4
295 #define MSR_PRP4_LBSTK_TO_5 0x6c5
296 #define MSR_PRP4_LBSTK_TO_6 0x6c6
297 #define MSR_PRP4_LBSTK_TO_7 0x6c7
298 #define MSR_PRP4_LBSTK_TO_8 0x6c8
299 #define MSR_PRP4_LBSTK_TO_9 0x6c9
300 #define MSR_PRP4_LBSTK_TO_10 0x6ca
301 #define MSR_PRP4_LBSTK_TO_11 0x6cb
302 #define MSR_PRP4_LBSTK_TO_12 0x6cc
303 #define MSR_PRP4_LBSTK_TO_13 0x6cd
304 #define MSR_PRP4_LBSTK_TO_14 0x6ce
305 #define MSR_PRP4_LBSTK_TO_15 0x6cf
306
307 #define MCI_CTL_VALUE 0xffffffff
308
309 #define MTRR_TYPE_UC 0
310 #define MTRR_TYPE_WC 1
311 #define MTRR_TYPE_WT 4
312 #define MTRR_TYPE_WP 5
313 #define MTRR_TYPE_WB 6
314 #define MTRR_TYPE_UC_ 7
315
316 /*
317 * For Solaris we set up the page attritubute table in the following way:
318 * PAT0 Write-Back
319 * PAT1 Write-Through
320 * PAT2 Unchacheable-
321 * PAT3 Uncacheable
322 * PAT4 Write-Back
323 * PAT5 Write-Through
324 * PAT6 Write-Combine
325 * PAT7 Uncacheable
326 * The only difference from h/w default is entry 6.
327 */
328 #define PAT_DEFAULT_ATTRIBUTE \
329 ((uint64_t)MTRR_TYPE_WB | \
330 ((uint64_t)MTRR_TYPE_WT << 8) | \
331 ((uint64_t)MTRR_TYPE_UC_ << 16) | \
332 ((uint64_t)MTRR_TYPE_UC << 24) | \
333 ((uint64_t)MTRR_TYPE_WB << 32) | \
334 ((uint64_t)MTRR_TYPE_WT << 40) | \
335 ((uint64_t)MTRR_TYPE_WC << 48) | \
336 ((uint64_t)MTRR_TYPE_UC << 56))
337
338 #define X86FSET_LARGEPAGE 0
339 #define X86FSET_TSC 1
340 #define X86FSET_MSR 2
341 #define X86FSET_MTRR 3
342 #define X86FSET_PGE 4
343 #define X86FSET_DE 5
344 #define X86FSET_CMOV 6
345 #define X86FSET_MMX 7
346 #define X86FSET_MCA 8
347 #define X86FSET_PAE 9
348 #define X86FSET_CX8 10
349 #define X86FSET_PAT 11
350 #define X86FSET_SEP 12
351 #define X86FSET_SSE 13
352 #define X86FSET_SSE2 14
353 #define X86FSET_HTT 15
354 #define X86FSET_ASYSC 16
355 #define X86FSET_NX 17
356 #define X86FSET_SSE3 18
357 #define X86FSET_CX16 19
358 #define X86FSET_CMP 20
359 #define X86FSET_TSCP 21
360 #define X86FSET_MWAIT 22
361 #define X86FSET_SSE4A 23
362 #define X86FSET_CPUID 24
363 #define X86FSET_SSSE3 25
364 #define X86FSET_SSE4_1 26
365 #define X86FSET_SSE4_2 27
366 #define X86FSET_1GPG 28
367 #define X86FSET_CLFSH 29
368 #define X86FSET_64 30
369 #define X86FSET_AES 31
370 #define X86FSET_PCLMULQDQ 32
371 #define X86FSET_XSAVE 33
372 #define X86FSET_AVX 34
373 #define X86FSET_VMX 35
374 #define X86FSET_SVM 36
375 #define X86FSET_TOPOEXT 37
376
377 /*
378 * flags to patch tsc_read routine.
379 */
380 #define X86_NO_TSC 0x0
381 #define X86_HAVE_TSCP 0x1
382 #define X86_TSC_MFENCE 0x2
383 #define X86_TSC_LFENCE 0x4
384
385 /*
386 * Intel Deep C-State invariant TSC in leaf 0x80000007.
387 */
388 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
389
390 /*
391 * Intel Deep C-state always-running local APIC timer
392 */
393 #define CPUID_CSTATE_ARAT (0x4)
394
395 /*
396 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3].
397 */
398 #define CPUID_EPB_SUPPORT (1 << 3)
399
400 /*
401 * Intel TSC deadline timer
402 */
403 #define CPUID_DEADLINE_TSC (1 << 24)
404
405 /*
406 * x86_type is a legacy concept; this is supplanted
407 * for most purposes by x86_featureset; modern CPUs
408 * should be X86_TYPE_OTHER
409 */
410 #define X86_TYPE_OTHER 0
411 #define X86_TYPE_486 1
412 #define X86_TYPE_P5 2
413 #define X86_TYPE_P6 3
414 #define X86_TYPE_CYRIX_486 4
415 #define X86_TYPE_CYRIX_6x86L 5
416 #define X86_TYPE_CYRIX_6x86 6
417 #define X86_TYPE_CYRIX_GXm 7
418 #define X86_TYPE_CYRIX_6x86MX 8
419 #define X86_TYPE_CYRIX_MediaGX 9
420 #define X86_TYPE_CYRIX_MII 10
421 #define X86_TYPE_VIA_CYRIX_III 11
422 #define X86_TYPE_P4 12
423
424 /*
425 * x86_vendor allows us to select between
426 * implementation features and helps guide
427 * the interpretation of the cpuid instruction.
428 */
429 #define X86_VENDOR_Intel 0
430 #define X86_VENDORSTR_Intel "GenuineIntel"
431
432 #define X86_VENDOR_IntelClone 1
433
434 #define X86_VENDOR_AMD 2
435 #define X86_VENDORSTR_AMD "AuthenticAMD"
436
437 #define X86_VENDOR_Cyrix 3
438 #define X86_VENDORSTR_CYRIX "CyrixInstead"
439
440 #define X86_VENDOR_UMC 4
441 #define X86_VENDORSTR_UMC "UMC UMC UMC "
442
443 #define X86_VENDOR_NexGen 5
444 #define X86_VENDORSTR_NexGen "NexGenDriven"
445
446 #define X86_VENDOR_Centaur 6
447 #define X86_VENDORSTR_Centaur "CentaurHauls"
448
449 #define X86_VENDOR_Rise 7
450 #define X86_VENDORSTR_Rise "RiseRiseRise"
451
452 #define X86_VENDOR_SiS 8
453 #define X86_VENDORSTR_SiS "SiS SiS SiS "
454
455 #define X86_VENDOR_TM 9
456 #define X86_VENDORSTR_TM "GenuineTMx86"
457
458 #define X86_VENDOR_NSC 10
459 #define X86_VENDORSTR_NSC "Geode by NSC"
460
461 /*
462 * Vendor string max len + \0
463 */
464 #define X86_VENDOR_STRLEN 13
465
466 /*
467 * Some vendor/family/model/stepping ranges are commonly grouped under
468 * a single identifying banner by the vendor. The following encode
469 * that "revision" in a uint32_t with the 8 most significant bits
470 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the
471 * family, and the remaining 16 typically forming a bitmask of revisions
472 * within that family with more significant bits indicating "later" revisions.
473 */
474
475 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u
476 #define _X86_CHIPREV_VENDOR_SHIFT 24
477 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u
478 #define _X86_CHIPREV_FAMILY_SHIFT 16
479 #define _X86_CHIPREV_REV_MASK 0x0000ffffu
480
481 #define _X86_CHIPREV_VENDOR(x) \
482 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT)
483 #define _X86_CHIPREV_FAMILY(x) \
484 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT)
485 #define _X86_CHIPREV_REV(x) \
486 ((x) & _X86_CHIPREV_REV_MASK)
487
488 /* True if x matches in vendor and family and if x matches the given rev mask */
489 #define X86_CHIPREV_MATCH(x, mask) \
490 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \
491 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \
492 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0))
493
494 /* True if x matches in vendor and family, and rev is at least minx */
495 #define X86_CHIPREV_ATLEAST(x, minx) \
496 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
497 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \
498 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx))
499
500 #define _X86_CHIPREV_MKREV(vendor, family, rev) \
501 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \
502 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev))
503
504 /* True if x matches in vendor, and family is at least minx */
505 #define X86_CHIPFAM_ATLEAST(x, minx) \
506 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
507 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx))
508
509 /* Revision default */
510 #define X86_CHIPREV_UNKNOWN 0x0
511
512 /*
513 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are
514 * sufficiently different that we will distinguish them; in all other
515 * case we will identify the major revision.
516 */
517 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001)
518 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002)
519 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004)
520 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008)
521 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010)
522 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020)
523 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040)
524
525 /*
526 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only.
527 */
528 #define X86_CHIPREV_AMD_10_REV_A \
529 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001)
530 #define X86_CHIPREV_AMD_10_REV_B \
531 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002)
532 #define X86_CHIPREV_AMD_10_REV_C2 \
533 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004)
534 #define X86_CHIPREV_AMD_10_REV_C3 \
535 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008)
536 #define X86_CHIPREV_AMD_10_REV_D0 \
537 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010)
538 #define X86_CHIPREV_AMD_10_REV_D1 \
539 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020)
540 #define X86_CHIPREV_AMD_10_REV_E \
541 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040)
542
543 /*
544 * Definitions for AMD Family 0x11.
545 */
546 #define X86_CHIPREV_AMD_11_REV_B \
547 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002)
548
549 /*
550 * Definitions for AMD Family 0x12.
551 */
552 #define X86_CHIPREV_AMD_12_REV_B \
553 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002)
554
555 /*
556 * Definitions for AMD Family 0x14.
557 */
558 #define X86_CHIPREV_AMD_14_REV_B \
559 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002)
560 #define X86_CHIPREV_AMD_14_REV_C \
561 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004)
562
563 /*
564 * Definitions for AMD Family 0x15
565 */
566 #define X86_CHIPREV_AMD_15OR_REV_B2 \
567 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001)
568
569 #define X86_CHIPREV_AMD_15TN_REV_A1 \
570 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002)
571
572 /*
573 * Various socket/package types, extended as the need to distinguish
574 * a new type arises. The top 8 byte identfies the vendor and the
575 * remaining 24 bits describe 24 socket types.
576 */
577
578 #define _X86_SOCKET_VENDOR_SHIFT 24
579 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT)
580 #define _X86_SOCKET_TYPE_MASK 0x00ffffff
581 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK)
582
583 #define _X86_SOCKET_MKVAL(vendor, bitval) \
584 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval))
585
586 #define X86_SOCKET_MATCH(s, mask) \
587 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \
588 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0)
589
590 #define X86_SOCKET_UNKNOWN 0x0
591 /*
592 * AMD socket types
593 */
594 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001)
595 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002)
596 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004)
597 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008)
598 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010)
599 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020)
600 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040)
601 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080)
602 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100)
603 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200)
604 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400)
605 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800)
606 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000)
607 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000)
608 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000)
609 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000)
610 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000)
611 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000)
612 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000)
613 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000)
614 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000)
615 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000)
616
617 /*
618 * xgetbv/xsetbv support
619 */
620
621 #define XFEATURE_ENABLED_MASK 0x0
622 /*
623 * XFEATURE_ENABLED_MASK values (eax)
624 */
625 #define XFEATURE_LEGACY_FP 0x1
626 #define XFEATURE_SSE 0x2
627 #define XFEATURE_AVX 0x4
628 #define XFEATURE_MAX XFEATURE_AVX
629 #define XFEATURE_FP_ALL (XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX)
630
631 #if !defined(_ASM)
632
633 #if defined(_KERNEL) || defined(_KMEMUSER)
634
635 #define NUM_X86_FEATURES 38
636 extern uchar_t x86_featureset[];
637
638 extern void free_x86_featureset(void *featureset);
639 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
640 extern void add_x86_feature(void *featureset, uint_t feature);
641 extern void remove_x86_feature(void *featureset, uint_t feature);
642 extern boolean_t compare_x86_featureset(void *setA, void *setB);
643 extern void print_x86_featureset(void *featureset);
644
645
646 extern uint_t x86_type;
647 extern uint_t x86_vendor;
648 extern uint_t x86_clflush_size;
649
650 extern uint_t pentiumpro_bug4046376;
651 extern uint_t pentiumpro_bug4064495;
652
653 extern uint_t enable486;
654
655 extern const char CyrixInstead[];
656
657 #endif
658
659 #if defined(_KERNEL)
660
661 /*
662 * This structure is used to pass arguments and get return values back
663 * from the CPUID instruction in __cpuid_insn() routine.
664 */
665 struct cpuid_regs {
666 uint32_t cp_eax;
667 uint32_t cp_ebx;
668 uint32_t cp_ecx;
669 uint32_t cp_edx;
670 };
671
672 /*
673 * Utility functions to get/set extended control registers (XCR)
674 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
675 */
676 extern uint64_t get_xcr(uint_t);
677 extern void set_xcr(uint_t, uint64_t);
678
679 extern uint64_t rdmsr(uint_t);
680 extern void wrmsr(uint_t, const uint64_t);
681 extern uint64_t xrdmsr(uint_t);
682 extern void xwrmsr(uint_t, const uint64_t);
683 extern int checked_rdmsr(uint_t, uint64_t *);
684 extern int checked_wrmsr(uint_t, uint64_t);
685
686 extern void invalidate_cache(void);
687 extern ulong_t getcr4(void);
688 extern void setcr4(ulong_t);
689
690 extern void mtrr_sync(void);
691
692 extern void cpu_fast_syscall_enable(void *);
693 extern void cpu_fast_syscall_disable(void *);
694
695 struct cpu;
696
697 extern int cpuid_checkpass(struct cpu *, int);
698 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *);
699 extern uint32_t __cpuid_insn(struct cpuid_regs *);
700 extern int cpuid_getbrandstr(struct cpu *, char *, size_t);
701 extern int cpuid_getidstr(struct cpu *, char *, size_t);
702 extern const char *cpuid_getvendorstr(struct cpu *);
703 extern uint_t cpuid_getvendor(struct cpu *);
704 extern uint_t cpuid_getfamily(struct cpu *);
705 extern uint_t cpuid_getmodel(struct cpu *);
706 extern uint_t cpuid_getstep(struct cpu *);
707 extern uint_t cpuid_getsig(struct cpu *);
708 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *);
709 extern uint_t cpuid_get_ncore_per_chip(struct cpu *);
710 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *);
711 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *);
712 extern int cpuid_get_chipid(struct cpu *);
713 extern id_t cpuid_get_coreid(struct cpu *);
714 extern int cpuid_get_pkgcoreid(struct cpu *);
715 extern int cpuid_get_clogid(struct cpu *);
716 extern int cpuid_get_cacheid(struct cpu *);
717 extern uint32_t cpuid_get_apicid(struct cpu *);
718 extern uint_t cpuid_get_procnodeid(struct cpu *cpu);
719 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu);
720 extern uint_t cpuid_get_compunitid(struct cpu *cpu);
721 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu);
722 extern int cpuid_is_cmt(struct cpu *);
723 extern int cpuid_syscall32_insn(struct cpu *);
724 extern int getl2cacheinfo(struct cpu *, int *, int *, int *);
725
726 extern uint32_t cpuid_getchiprev(struct cpu *);
727 extern const char *cpuid_getchiprevstr(struct cpu *);
728 extern uint32_t cpuid_getsockettype(struct cpu *);
729 extern const char *cpuid_getsocketstr(struct cpu *);
730
731 extern int cpuid_have_cr8access(struct cpu *);
732
733 extern int cpuid_opteron_erratum(struct cpu *, uint_t);
734
735 struct cpuid_info;
736
737 extern void setx86isalist(void);
738 extern void cpuid_alloc_space(struct cpu *);
739 extern void cpuid_free_space(struct cpu *);
740 extern void cpuid_pass1(struct cpu *, uchar_t *);
741 extern void cpuid_pass2(struct cpu *);
742 extern void cpuid_pass3(struct cpu *);
743 extern uint_t cpuid_pass4(struct cpu *);
744 extern void cpuid_set_cpu_properties(void *, processorid_t,
745 struct cpuid_info *);
746
747 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *);
748 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t);
749
750 #if !defined(__xpv)
751 extern uint32_t *cpuid_mwait_alloc(struct cpu *);
752 extern void cpuid_mwait_free(struct cpu *);
753 extern int cpuid_deep_cstates_supported(void);
754 extern int cpuid_arat_supported(void);
755 extern int cpuid_iepb_supported(struct cpu *);
756 extern int cpuid_deadline_tsc_supported(void);
757 extern int vmware_platform(void);
758 #endif
759
760 struct cpu_ucode_info;
761
762 extern void ucode_alloc_space(struct cpu *);
763 extern void ucode_free_space(struct cpu *);
764 extern void ucode_check(struct cpu *);
765 extern void ucode_cleanup();
766
767 #if !defined(__xpv)
768 extern char _tsc_mfence_start;
769 extern char _tsc_mfence_end;
770 extern char _tscp_start;
771 extern char _tscp_end;
772 extern char _no_rdtsc_start;
773 extern char _no_rdtsc_end;
774 extern char _tsc_lfence_start;
775 extern char _tsc_lfence_end;
776 #endif
777
778 #if !defined(__xpv)
779 extern char bcopy_patch_start;
780 extern char bcopy_patch_end;
781 extern char bcopy_ck_size;
782 #endif
783
784 extern void post_startup_cpu_fixups(void);
785
786 extern uint_t workaround_errata(struct cpu *);
787
788 #if defined(OPTERON_ERRATUM_93)
789 extern int opteron_erratum_93;
790 #endif
791
792 #if defined(OPTERON_ERRATUM_91)
793 extern int opteron_erratum_91;
794 #endif
795
796 #if defined(OPTERON_ERRATUM_100)
797 extern int opteron_erratum_100;
798 #endif
799
800 #if defined(OPTERON_ERRATUM_121)
801 extern int opteron_erratum_121;
802 #endif
803
804 #if defined(OPTERON_WORKAROUND_6323525)
805 extern int opteron_workaround_6323525;
806 extern void patch_workaround_6323525(void);
807 #endif
808
809 #if !defined(__xpv)
810 extern void determine_platform(void);
811 #endif
812 extern int get_hwenv(void);
813 extern int is_controldom(void);
814
815 extern void xsave_setup_msr(struct cpu *);
816
817 /*
818 * Defined hardware environments
819 */
820 #define HW_NATIVE 0x00 /* Running on bare metal */
821 #define HW_XEN_PV 0x01 /* Running on Xen Hypervisor paravirutualized */
822 #define HW_XEN_HVM 0x02 /* Running on Xen hypervisor HVM */
823 #define HW_VMWARE 0x03 /* Running on VMware hypervisor */
824
825 #endif /* _KERNEL */
826
827 #endif
828
829 #ifdef __cplusplus
830 }
831 #endif
832
833 #endif /* _SYS_X86_ARCHEXT_H */