1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 */
25 /*
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
28 */
29 /*
30 * Copyright (c) 2011, Joyent, Inc. All rights reserved.
31 */
32
33 #ifndef _SYS_X86_ARCHEXT_H
34 #define _SYS_X86_ARCHEXT_H
35
36 #if !defined(_ASM)
37 #include <sys/regset.h>
38 #include <sys/processor.h>
39 #include <vm/seg_enum.h>
40 #include <vm/page.h>
41 #endif /* _ASM */
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46
47 /*
48 * cpuid instruction feature flags in %edx (standard function 1)
49 */
50
51 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */
52 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */
53 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */
54 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */
55 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */
56 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
57 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */
58 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */
59 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
60 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */
61 /* 0x400 - reserved */
62 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */
63 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */
64 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */
65 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */
66 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */
67 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */
68 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
69 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */
70 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */
71 /* 0x100000 - reserved */
72 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */
73 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */
74 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */
75 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
76 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */
77 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */
78 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */
79 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */
80 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */
81 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */
82 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */
83
84 #define FMT_CPUID_INTC_EDX \
85 "\20" \
86 "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr" \
87 "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat" \
88 "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \
89 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
90
91 /*
92 * cpuid instruction feature flags in %ecx (standard function 1)
93 */
94
95 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */
96 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */
97 /* 0x00000004 - reserved */
98 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */
99 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
100 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */
101 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */
102 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */
103 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */
104 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */
105 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */
106 /* 0x00000800 - reserved */
107 /* 0x00001000 - reserved */
108 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */
109 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */
110 /* 0x00008000 - reserved */
111 /* 0x00010000 - reserved */
112 /* 0x00020000 - reserved */
113 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */
114 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */
115 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */
116 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */
117 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */
118 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */
119 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */
120 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */
121 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
122
123 #define FMT_CPUID_INTC_ECX \
124 "\20" \
125 "\35avx\34osxsav\33xsave" \
126 "\32aes" \
127 "\30popcnt\27movbe\25sse4.2\24sse4.1\23dca" \
128 "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \
129 "\10est\7smx\6vmx\5dscpl\4mon\2pclmulqdq\1sse3"
130
131 /*
132 * cpuid instruction feature flags in %edx (extended function 0x80000001)
133 */
134
135 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */
136 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */
137 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */
138 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */
139 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */
140 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
141 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */
142 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */
143 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
144 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */
145 /* 0x00000400 - sysc on K6m6 */
146 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */
147 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */
148 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */
149 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */
150 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */
151 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */
152 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */
153 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
154 /* 0x00040000 - reserved */
155 /* 0x00080000 - reserved */
156 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */
157 /* 0x00200000 - reserved */
158 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */
159 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */
160 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
161 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */
162 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */
163 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */
164 /* 0x10000000 - reserved */
165 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */
166 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */
167 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */
168
169 #define FMT_CPUID_AMD_EDX \
170 "\20" \
171 "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \
172 "\30mmx\27mmxext\25nx\22pse\21pat" \
173 "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \
174 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
175
176 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
177 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
178 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
179 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
180 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
181 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
182 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
183 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
184 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
185 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
186 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
187 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */
188 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
189 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
190 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
191
192 #define FMT_CPUID_AMD_ECX \
193 "\20" \
194 "\22topoext" \
195 "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas" \
196 "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64"
197
198 /*
199 * Intel now seems to have claimed part of the "extended" function
200 * space that we previously for non-Intel implementors to use.
201 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
202 * is available in long mode i.e. what AMD indicate using bit 0.
203 * On the other hand, everything else is labelled as reserved.
204 */
205 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
206
207
208 #define P5_MCHADDR 0x0
209 #define P5_CESR 0x11
210 #define P5_CTR0 0x12
211 #define P5_CTR1 0x13
212
213 #define K5_MCHADDR 0x0
214 #define K5_MCHTYPE 0x01
215 #define K5_TSC 0x10
216 #define K5_TR12 0x12
217
218 #define REG_PAT 0x277
219
220 #define REG_MC0_CTL 0x400
221 #define REG_MC5_MISC 0x417
222 #define REG_PERFCTR0 0xc1
223 #define REG_PERFCTR1 0xc2
224
225 #define REG_PERFEVNT0 0x186
226 #define REG_PERFEVNT1 0x187
227
228 #define REG_TSC 0x10 /* timestamp counter */
229 #define REG_APIC_BASE_MSR 0x1b
230 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */
231
232 #if !defined(__xpv)
233 /*
234 * AMD C1E
235 */
236 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055
237 #define AMD_ACTONCMPHALT_SHIFT 27
238 #define AMD_ACTONCMPHALT_MASK 3
239 #endif
240
241 #define MSR_DEBUGCTL 0x1d9
242
243 #define DEBUGCTL_LBR 0x01
244 #define DEBUGCTL_BTF 0x02
245
246 /* Intel P6, AMD */
247 #define MSR_LBR_FROM 0x1db
248 #define MSR_LBR_TO 0x1dc
249 #define MSR_LEX_FROM 0x1dd
250 #define MSR_LEX_TO 0x1de
251
252 /* Intel P4 (pre-Prescott, non P4 M) */
253 #define MSR_P4_LBSTK_TOS 0x1da
254 #define MSR_P4_LBSTK_0 0x1db
255 #define MSR_P4_LBSTK_1 0x1dc
256 #define MSR_P4_LBSTK_2 0x1dd
257 #define MSR_P4_LBSTK_3 0x1de
258
259 /* Intel Pentium M */
260 #define MSR_P6M_LBSTK_TOS 0x1c9
261 #define MSR_P6M_LBSTK_0 0x040
262 #define MSR_P6M_LBSTK_1 0x041
263 #define MSR_P6M_LBSTK_2 0x042
264 #define MSR_P6M_LBSTK_3 0x043
265 #define MSR_P6M_LBSTK_4 0x044
266 #define MSR_P6M_LBSTK_5 0x045
267 #define MSR_P6M_LBSTK_6 0x046
268 #define MSR_P6M_LBSTK_7 0x047
269
270 /* Intel P4 (Prescott) */
271 #define MSR_PRP4_LBSTK_TOS 0x1da
272 #define MSR_PRP4_LBSTK_FROM_0 0x680
273 #define MSR_PRP4_LBSTK_FROM_1 0x681
274 #define MSR_PRP4_LBSTK_FROM_2 0x682
275 #define MSR_PRP4_LBSTK_FROM_3 0x683
276 #define MSR_PRP4_LBSTK_FROM_4 0x684
277 #define MSR_PRP4_LBSTK_FROM_5 0x685
278 #define MSR_PRP4_LBSTK_FROM_6 0x686
279 #define MSR_PRP4_LBSTK_FROM_7 0x687
280 #define MSR_PRP4_LBSTK_FROM_8 0x688
281 #define MSR_PRP4_LBSTK_FROM_9 0x689
282 #define MSR_PRP4_LBSTK_FROM_10 0x68a
283 #define MSR_PRP4_LBSTK_FROM_11 0x68b
284 #define MSR_PRP4_LBSTK_FROM_12 0x68c
285 #define MSR_PRP4_LBSTK_FROM_13 0x68d
286 #define MSR_PRP4_LBSTK_FROM_14 0x68e
287 #define MSR_PRP4_LBSTK_FROM_15 0x68f
288 #define MSR_PRP4_LBSTK_TO_0 0x6c0
289 #define MSR_PRP4_LBSTK_TO_1 0x6c1
290 #define MSR_PRP4_LBSTK_TO_2 0x6c2
291 #define MSR_PRP4_LBSTK_TO_3 0x6c3
292 #define MSR_PRP4_LBSTK_TO_4 0x6c4
293 #define MSR_PRP4_LBSTK_TO_5 0x6c5
294 #define MSR_PRP4_LBSTK_TO_6 0x6c6
295 #define MSR_PRP4_LBSTK_TO_7 0x6c7
296 #define MSR_PRP4_LBSTK_TO_8 0x6c8
297 #define MSR_PRP4_LBSTK_TO_9 0x6c9
298 #define MSR_PRP4_LBSTK_TO_10 0x6ca
299 #define MSR_PRP4_LBSTK_TO_11 0x6cb
300 #define MSR_PRP4_LBSTK_TO_12 0x6cc
301 #define MSR_PRP4_LBSTK_TO_13 0x6cd
302 #define MSR_PRP4_LBSTK_TO_14 0x6ce
303 #define MSR_PRP4_LBSTK_TO_15 0x6cf
304
305 #define MCI_CTL_VALUE 0xffffffff
306
307 #define MTRR_TYPE_UC 0
308 #define MTRR_TYPE_WC 1
309 #define MTRR_TYPE_WT 4
310 #define MTRR_TYPE_WP 5
311 #define MTRR_TYPE_WB 6
312 #define MTRR_TYPE_UC_ 7
313
314 /*
315 * For Solaris we set up the page attritubute table in the following way:
316 * PAT0 Write-Back
317 * PAT1 Write-Through
318 * PAT2 Unchacheable-
319 * PAT3 Uncacheable
320 * PAT4 Write-Back
321 * PAT5 Write-Through
322 * PAT6 Write-Combine
323 * PAT7 Uncacheable
324 * The only difference from h/w default is entry 6.
325 */
326 #define PAT_DEFAULT_ATTRIBUTE \
327 ((uint64_t)MTRR_TYPE_WB | \
328 ((uint64_t)MTRR_TYPE_WT << 8) | \
329 ((uint64_t)MTRR_TYPE_UC_ << 16) | \
330 ((uint64_t)MTRR_TYPE_UC << 24) | \
331 ((uint64_t)MTRR_TYPE_WB << 32) | \
332 ((uint64_t)MTRR_TYPE_WT << 40) | \
333 ((uint64_t)MTRR_TYPE_WC << 48) | \
334 ((uint64_t)MTRR_TYPE_UC << 56))
335
336 #define X86FSET_LARGEPAGE 0
337 #define X86FSET_TSC 1
338 #define X86FSET_MSR 2
339 #define X86FSET_MTRR 3
340 #define X86FSET_PGE 4
341 #define X86FSET_DE 5
342 #define X86FSET_CMOV 6
343 #define X86FSET_MMX 7
344 #define X86FSET_MCA 8
345 #define X86FSET_PAE 9
346 #define X86FSET_CX8 10
347 #define X86FSET_PAT 11
348 #define X86FSET_SEP 12
349 #define X86FSET_SSE 13
350 #define X86FSET_SSE2 14
351 #define X86FSET_HTT 15
352 #define X86FSET_ASYSC 16
353 #define X86FSET_NX 17
354 #define X86FSET_SSE3 18
355 #define X86FSET_CX16 19
356 #define X86FSET_CMP 20
357 #define X86FSET_TSCP 21
358 #define X86FSET_MWAIT 22
359 #define X86FSET_SSE4A 23
360 #define X86FSET_CPUID 24
361 #define X86FSET_SSSE3 25
362 #define X86FSET_SSE4_1 26
363 #define X86FSET_SSE4_2 27
364 #define X86FSET_1GPG 28
365 #define X86FSET_CLFSH 29
366 #define X86FSET_64 30
367 #define X86FSET_AES 31
368 #define X86FSET_PCLMULQDQ 32
369 #define X86FSET_XSAVE 33
370 #define X86FSET_AVX 34
371 #define X86FSET_VMX 35
372 #define X86FSET_SVM 36
373 #define X86FSET_TOPOEXT 37
374
375 /*
376 * flags to patch tsc_read routine.
377 */
378 #define X86_NO_TSC 0x0
379 #define X86_HAVE_TSCP 0x1
380 #define X86_TSC_MFENCE 0x2
381 #define X86_TSC_LFENCE 0x4
382
383 /*
384 * Intel Deep C-State invariant TSC in leaf 0x80000007.
385 */
386 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
387
388 /*
389 * Intel Deep C-state always-running local APIC timer
390 */
391 #define CPUID_CSTATE_ARAT (0x4)
392
393 /*
394 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3].
395 */
396 #define CPUID_EPB_SUPPORT (1 << 3)
397
398 /*
399 * Intel TSC deadline timer
400 */
401 #define CPUID_DEADLINE_TSC (1 << 24)
402
403 /*
404 * x86_type is a legacy concept; this is supplanted
405 * for most purposes by x86_featureset; modern CPUs
406 * should be X86_TYPE_OTHER
407 */
408 #define X86_TYPE_OTHER 0
409 #define X86_TYPE_486 1
410 #define X86_TYPE_P5 2
411 #define X86_TYPE_P6 3
412 #define X86_TYPE_CYRIX_486 4
413 #define X86_TYPE_CYRIX_6x86L 5
414 #define X86_TYPE_CYRIX_6x86 6
415 #define X86_TYPE_CYRIX_GXm 7
416 #define X86_TYPE_CYRIX_6x86MX 8
417 #define X86_TYPE_CYRIX_MediaGX 9
418 #define X86_TYPE_CYRIX_MII 10
419 #define X86_TYPE_VIA_CYRIX_III 11
420 #define X86_TYPE_P4 12
421
422 /*
423 * x86_vendor allows us to select between
424 * implementation features and helps guide
425 * the interpretation of the cpuid instruction.
426 */
427 #define X86_VENDOR_Intel 0
428 #define X86_VENDORSTR_Intel "GenuineIntel"
429
430 #define X86_VENDOR_IntelClone 1
431
432 #define X86_VENDOR_AMD 2
433 #define X86_VENDORSTR_AMD "AuthenticAMD"
434
435 #define X86_VENDOR_Cyrix 3
436 #define X86_VENDORSTR_CYRIX "CyrixInstead"
437
438 #define X86_VENDOR_UMC 4
439 #define X86_VENDORSTR_UMC "UMC UMC UMC "
440
441 #define X86_VENDOR_NexGen 5
442 #define X86_VENDORSTR_NexGen "NexGenDriven"
443
444 #define X86_VENDOR_Centaur 6
445 #define X86_VENDORSTR_Centaur "CentaurHauls"
446
447 #define X86_VENDOR_Rise 7
448 #define X86_VENDORSTR_Rise "RiseRiseRise"
449
450 #define X86_VENDOR_SiS 8
451 #define X86_VENDORSTR_SiS "SiS SiS SiS "
452
453 #define X86_VENDOR_TM 9
454 #define X86_VENDORSTR_TM "GenuineTMx86"
455
456 #define X86_VENDOR_NSC 10
457 #define X86_VENDORSTR_NSC "Geode by NSC"
458
459 /*
460 * Vendor string max len + \0
461 */
462 #define X86_VENDOR_STRLEN 13
463
464 /*
465 * Some vendor/family/model/stepping ranges are commonly grouped under
466 * a single identifying banner by the vendor. The following encode
467 * that "revision" in a uint32_t with the 8 most significant bits
468 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the
469 * family, and the remaining 16 typically forming a bitmask of revisions
470 * within that family with more significant bits indicating "later" revisions.
471 */
472
473 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u
474 #define _X86_CHIPREV_VENDOR_SHIFT 24
475 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u
476 #define _X86_CHIPREV_FAMILY_SHIFT 16
477 #define _X86_CHIPREV_REV_MASK 0x0000ffffu
478
479 #define _X86_CHIPREV_VENDOR(x) \
480 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT)
481 #define _X86_CHIPREV_FAMILY(x) \
482 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT)
483 #define _X86_CHIPREV_REV(x) \
484 ((x) & _X86_CHIPREV_REV_MASK)
485
486 /* True if x matches in vendor and family and if x matches the given rev mask */
487 #define X86_CHIPREV_MATCH(x, mask) \
488 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \
489 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \
490 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0))
491
492 /* True if x matches in vendor and family, and rev is at least minx */
493 #define X86_CHIPREV_ATLEAST(x, minx) \
494 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
495 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \
496 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx))
497
498 #define _X86_CHIPREV_MKREV(vendor, family, rev) \
499 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \
500 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev))
501
502 /* True if x matches in vendor, and family is at least minx */
503 #define X86_CHIPFAM_ATLEAST(x, minx) \
504 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
505 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx))
506
507 /* Revision default */
508 #define X86_CHIPREV_UNKNOWN 0x0
509
510 /*
511 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are
512 * sufficiently different that we will distinguish them; in all other
513 * case we will identify the major revision.
514 */
515 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001)
516 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002)
517 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004)
518 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008)
519 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010)
520 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020)
521 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040)
522
523 /*
524 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only.
525 */
526 #define X86_CHIPREV_AMD_10_REV_A \
527 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001)
528 #define X86_CHIPREV_AMD_10_REV_B \
529 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002)
530 #define X86_CHIPREV_AMD_10_REV_C \
531 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004)
532 #define X86_CHIPREV_AMD_10_REV_D \
533 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008)
534
535 /*
536 * Definitions for AMD Family 0x11.
537 */
538 #define X86_CHIPREV_AMD_11 \
539 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0001)
540
541
542 /*
543 * Various socket/package types, extended as the need to distinguish
544 * a new type arises. The top 8 byte identfies the vendor and the
545 * remaining 24 bits describe 24 socket types.
546 */
547
548 #define _X86_SOCKET_VENDOR_SHIFT 24
549 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT)
550 #define _X86_SOCKET_TYPE_MASK 0x00ffffff
551 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK)
552
553 #define _X86_SOCKET_MKVAL(vendor, bitval) \
554 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval))
555
556 #define X86_SOCKET_MATCH(s, mask) \
557 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \
558 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0)
559
560 #define X86_SOCKET_UNKNOWN 0x0
561 /*
562 * AMD socket types
563 */
564 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001)
565 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002)
566 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004)
567 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008)
568 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010)
569 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020)
570 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040)
571 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080)
572 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100)
573 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200)
574 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400)
575 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800)
576 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000)
577 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000)
578
579 /*
580 * xgetbv/xsetbv support
581 */
582
583 #define XFEATURE_ENABLED_MASK 0x0
584 /*
585 * XFEATURE_ENABLED_MASK values (eax)
586 */
587 #define XFEATURE_LEGACY_FP 0x1
588 #define XFEATURE_SSE 0x2
589 #define XFEATURE_AVX 0x4
590 #define XFEATURE_MAX XFEATURE_AVX
591 #define XFEATURE_FP_ALL (XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX)
592
593 #if !defined(_ASM)
594
595 #if defined(_KERNEL) || defined(_KMEMUSER)
596
597 #define NUM_X86_FEATURES 38
598 extern uchar_t x86_featureset[];
599
600 extern void free_x86_featureset(void *featureset);
601 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
602 extern void add_x86_feature(void *featureset, uint_t feature);
603 extern void remove_x86_feature(void *featureset, uint_t feature);
604 extern boolean_t compare_x86_featureset(void *setA, void *setB);
605 extern void print_x86_featureset(void *featureset);
606
607
608 extern uint_t x86_type;
609 extern uint_t x86_vendor;
610 extern uint_t x86_clflush_size;
611
612 extern uint_t pentiumpro_bug4046376;
613 extern uint_t pentiumpro_bug4064495;
614
615 extern uint_t enable486;
616
617 extern const char CyrixInstead[];
618
619 #endif
620
621 #if defined(_KERNEL)
622
623 /*
624 * This structure is used to pass arguments and get return values back
625 * from the CPUID instruction in __cpuid_insn() routine.
626 */
627 struct cpuid_regs {
628 uint32_t cp_eax;
629 uint32_t cp_ebx;
630 uint32_t cp_ecx;
631 uint32_t cp_edx;
632 };
633
634 /*
635 * Utility functions to get/set extended control registers (XCR)
636 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
637 */
638 extern uint64_t get_xcr(uint_t);
639 extern void set_xcr(uint_t, uint64_t);
640
641 extern uint64_t rdmsr(uint_t);
642 extern void wrmsr(uint_t, const uint64_t);
643 extern uint64_t xrdmsr(uint_t);
644 extern void xwrmsr(uint_t, const uint64_t);
645 extern int checked_rdmsr(uint_t, uint64_t *);
646 extern int checked_wrmsr(uint_t, uint64_t);
647
648 extern void invalidate_cache(void);
649 extern ulong_t getcr4(void);
650 extern void setcr4(ulong_t);
651
652 extern void mtrr_sync(void);
653
654 extern void cpu_fast_syscall_enable(void *);
655 extern void cpu_fast_syscall_disable(void *);
656
657 struct cpu;
658
659 extern int cpuid_checkpass(struct cpu *, int);
660 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *);
661 extern uint32_t __cpuid_insn(struct cpuid_regs *);
662 extern int cpuid_getbrandstr(struct cpu *, char *, size_t);
663 extern int cpuid_getidstr(struct cpu *, char *, size_t);
664 extern const char *cpuid_getvendorstr(struct cpu *);
665 extern uint_t cpuid_getvendor(struct cpu *);
666 extern uint_t cpuid_getfamily(struct cpu *);
667 extern uint_t cpuid_getmodel(struct cpu *);
668 extern uint_t cpuid_getstep(struct cpu *);
669 extern uint_t cpuid_getsig(struct cpu *);
670 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *);
671 extern uint_t cpuid_get_ncore_per_chip(struct cpu *);
672 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *);
673 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *);
674 extern int cpuid_get_chipid(struct cpu *);
675 extern id_t cpuid_get_coreid(struct cpu *);
676 extern int cpuid_get_pkgcoreid(struct cpu *);
677 extern int cpuid_get_clogid(struct cpu *);
678 extern int cpuid_get_cacheid(struct cpu *);
679 extern uint32_t cpuid_get_apicid(struct cpu *);
680 extern uint_t cpuid_get_procnodeid(struct cpu *cpu);
681 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu);
682 extern uint_t cpuid_get_compunitid(struct cpu *cpu);
683 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu);
684 extern int cpuid_is_cmt(struct cpu *);
685 extern int cpuid_syscall32_insn(struct cpu *);
686 extern int getl2cacheinfo(struct cpu *, int *, int *, int *);
687
688 extern uint32_t cpuid_getchiprev(struct cpu *);
689 extern const char *cpuid_getchiprevstr(struct cpu *);
690 extern uint32_t cpuid_getsockettype(struct cpu *);
691 extern const char *cpuid_getsocketstr(struct cpu *);
692
693 extern int cpuid_have_cr8access(struct cpu *);
694
695 extern int cpuid_opteron_erratum(struct cpu *, uint_t);
696
697 struct cpuid_info;
698
699 extern void setx86isalist(void);
700 extern void cpuid_alloc_space(struct cpu *);
701 extern void cpuid_free_space(struct cpu *);
702 extern void cpuid_pass1(struct cpu *, uchar_t *);
703 extern void cpuid_pass2(struct cpu *);
704 extern void cpuid_pass3(struct cpu *);
705 extern uint_t cpuid_pass4(struct cpu *);
706 extern void cpuid_set_cpu_properties(void *, processorid_t,
707 struct cpuid_info *);
708
709 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *);
710 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t);
711
712 #if !defined(__xpv)
713 extern uint32_t *cpuid_mwait_alloc(struct cpu *);
714 extern void cpuid_mwait_free(struct cpu *);
715 extern int cpuid_deep_cstates_supported(void);
716 extern int cpuid_arat_supported(void);
717 extern int cpuid_iepb_supported(struct cpu *);
718 extern int cpuid_deadline_tsc_supported(void);
719 extern int vmware_platform(void);
720 #endif
721
722 struct cpu_ucode_info;
723
724 extern void ucode_alloc_space(struct cpu *);
725 extern void ucode_free_space(struct cpu *);
726 extern void ucode_check(struct cpu *);
727 extern void ucode_cleanup();
728
729 #if !defined(__xpv)
730 extern char _tsc_mfence_start;
731 extern char _tsc_mfence_end;
732 extern char _tscp_start;
733 extern char _tscp_end;
734 extern char _no_rdtsc_start;
735 extern char _no_rdtsc_end;
736 extern char _tsc_lfence_start;
737 extern char _tsc_lfence_end;
738 #endif
739
740 #if !defined(__xpv)
741 extern char bcopy_patch_start;
742 extern char bcopy_patch_end;
743 extern char bcopy_ck_size;
744 #endif
745
746 extern void post_startup_cpu_fixups(void);
747
748 extern uint_t workaround_errata(struct cpu *);
749
750 #if defined(OPTERON_ERRATUM_93)
751 extern int opteron_erratum_93;
752 #endif
753
754 #if defined(OPTERON_ERRATUM_91)
755 extern int opteron_erratum_91;
756 #endif
757
758 #if defined(OPTERON_ERRATUM_100)
759 extern int opteron_erratum_100;
760 #endif
761
762 #if defined(OPTERON_ERRATUM_121)
763 extern int opteron_erratum_121;
764 #endif
765
766 #if defined(OPTERON_WORKAROUND_6323525)
767 extern int opteron_workaround_6323525;
768 extern void patch_workaround_6323525(void);
769 #endif
770
771 #if !defined(__xpv)
772 extern void determine_platform(void);
773 #endif
774 extern int get_hwenv(void);
775 extern int is_controldom(void);
776
777 extern void xsave_setup_msr(struct cpu *);
778
779 /*
780 * Defined hardware environments
781 */
782 #define HW_NATIVE 0x00 /* Running on bare metal */
783 #define HW_XEN_PV 0x01 /* Running on Xen Hypervisor paravirutualized */
784 #define HW_XEN_HVM 0x02 /* Running on Xen hypervisor HVM */
785 #define HW_VMWARE 0x03 /* Running on VMware hypervisor */
786
787 #endif /* _KERNEL */
788
789 #endif
790
791 #ifdef __cplusplus
792 }
793 #endif
794
795 #endif /* _SYS_X86_ARCHEXT_H */