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3408 detect socket type of newer AMD CPUs
Reviewed by: Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
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--- old/usr/src/uts/i86pc/os/cpuid_subr.c
+++ new/usr/src/uts/i86pc/os/cpuid_subr.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
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22 22 /*
23 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
24 24 * Use is subject to license terms.
25 25 */
26 26
27 27 /*
28 28 * Portions Copyright 2009 Advanced Micro Devices, Inc.
29 29 */
30 30
31 31 /*
32 + * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
33 + * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
34 + */
35 +
36 +/*
32 37 * Support functions that interpret CPUID and similar information.
33 38 * These should not be used from anywhere other than cpuid.c and
34 39 * cmi_hw.c - as such we will not list them in any header file
35 40 * such as x86_archext.h.
36 41 *
37 42 * In cpuid.c we process CPUID information for each cpu_t instance
38 43 * we're presented with, and stash this raw information and material
39 44 * derived from it in per-cpu_t structures.
40 45 *
41 46 * If we are virtualized then the CPUID information derived from CPUID
42 47 * instructions executed in the guest is based on whatever the hypervisor
43 48 * wanted to make things look like, and the cpu_t are not necessarily in 1:1
44 49 * or fixed correspondence with real processor execution resources. In cmi_hw.c
45 50 * we are interested in the native properties of a processor - for fault
46 51 * management (and potentially other, such as power management) purposes;
47 52 * it will tunnel through to real hardware information, and use the
48 53 * functionality provided in this file to process it.
49 54 */
50 55
51 56 #include <sys/types.h>
52 57 #include <sys/systm.h>
53 58 #include <sys/bitmap.h>
54 59 #include <sys/x86_archext.h>
55 60 #include <sys/pci_cfgspace.h>
56 61 #ifdef __xpv
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57 62 #include <sys/hypervisor.h>
58 63 #endif
59 64
60 65 /*
61 66 * AMD socket types.
62 67 * First index :
63 68 * 0 for family 0xf, revs B thru E
64 69 * 1 for family 0xf, revs F and G
65 70 * 2 for family 0x10
66 71 * 3 for family 0x11
67 - * Second index by (model & 0x3) for family 0fh
68 - * or CPUID bits for later families
72 + * 4 for family 0x12
73 + * 5 for family 0x14
74 + * 6 for family 0x15, models 00 - 0f
75 + * 7 for family 0x15, models 10 - 1f
76 + * Second index by (model & 0x3) for family 0fh,
77 + * CPUID pkg bits (Fn8000_0001_EBX[31:28]) for later families.
69 78 */
70 -static uint32_t amd_skts[4][8] = {
79 +static uint32_t amd_skts[8][8] = {
71 80 /*
72 81 * Family 0xf revisions B through E
73 82 */
74 83 #define A_SKTS_0 0
75 84 {
76 85 X86_SOCKET_754, /* 0b000 */
77 86 X86_SOCKET_940, /* 0b001 */
78 87 X86_SOCKET_754, /* 0b010 */
79 88 X86_SOCKET_939, /* 0b011 */
80 89 X86_SOCKET_UNKNOWN, /* 0b100 */
81 90 X86_SOCKET_UNKNOWN, /* 0b101 */
82 91 X86_SOCKET_UNKNOWN, /* 0b110 */
83 92 X86_SOCKET_UNKNOWN /* 0b111 */
84 93 },
85 94 /*
86 95 * Family 0xf revisions F and G
87 96 */
88 97 #define A_SKTS_1 1
89 98 {
90 99 X86_SOCKET_S1g1, /* 0b000 */
91 100 X86_SOCKET_F1207, /* 0b001 */
92 101 X86_SOCKET_UNKNOWN, /* 0b010 */
93 102 X86_SOCKET_AM2, /* 0b011 */
94 103 X86_SOCKET_UNKNOWN, /* 0b100 */
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95 104 X86_SOCKET_UNKNOWN, /* 0b101 */
96 105 X86_SOCKET_UNKNOWN, /* 0b110 */
97 106 X86_SOCKET_UNKNOWN /* 0b111 */
98 107 },
99 108 /*
100 109 * Family 0x10
101 110 */
102 111 #define A_SKTS_2 2
103 112 {
104 113 X86_SOCKET_F1207, /* 0b000 */
105 - X86_SOCKET_AM, /* 0b001 */
114 + X86_SOCKET_AM2R2, /* 0b001 */
106 115 X86_SOCKET_S1g3, /* 0b010 */
107 116 X86_SOCKET_G34, /* 0b011 */
108 117 X86_SOCKET_ASB2, /* 0b100 */
109 118 X86_SOCKET_C32, /* 0b101 */
110 119 X86_SOCKET_UNKNOWN, /* 0b110 */
111 120 X86_SOCKET_UNKNOWN /* 0b111 */
112 121 },
113 122
114 123 /*
115 124 * Family 0x11
116 125 */
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117 126 #define A_SKTS_3 3
118 127 {
119 128 X86_SOCKET_UNKNOWN, /* 0b000 */
120 129 X86_SOCKET_UNKNOWN, /* 0b001 */
121 130 X86_SOCKET_S1g2, /* 0b010 */
122 131 X86_SOCKET_UNKNOWN, /* 0b011 */
123 132 X86_SOCKET_UNKNOWN, /* 0b100 */
124 133 X86_SOCKET_UNKNOWN, /* 0b101 */
125 134 X86_SOCKET_UNKNOWN, /* 0b110 */
126 135 X86_SOCKET_UNKNOWN /* 0b111 */
127 - }
136 + },
137 +
138 + /*
139 + * Family 0x12
140 + */
141 +#define A_SKTS_4 4
142 + {
143 + X86_SOCKET_UNKNOWN, /* 0b000 */
144 + X86_SOCKET_FS1, /* 0b001 */
145 + X86_SOCKET_FM1, /* 0b010 */
146 + X86_SOCKET_UNKNOWN, /* 0b011 */
147 + X86_SOCKET_UNKNOWN, /* 0b100 */
148 + X86_SOCKET_UNKNOWN, /* 0b101 */
149 + X86_SOCKET_UNKNOWN, /* 0b110 */
150 + X86_SOCKET_UNKNOWN /* 0b111 */
151 + },
152 +
153 + /*
154 + * Family 0x14
155 + */
156 +#define A_SKTS_5 5
157 + {
158 + X86_SOCKET_FT1, /* 0b000 */
159 + X86_SOCKET_UNKNOWN, /* 0b001 */
160 + X86_SOCKET_UNKNOWN, /* 0b010 */
161 + X86_SOCKET_UNKNOWN, /* 0b011 */
162 + X86_SOCKET_UNKNOWN, /* 0b100 */
163 + X86_SOCKET_UNKNOWN, /* 0b101 */
164 + X86_SOCKET_UNKNOWN, /* 0b110 */
165 + X86_SOCKET_UNKNOWN /* 0b111 */
166 + },
167 +
168 + /*
169 + * Family 0x15 models 00 - 0f
170 + */
171 +#define A_SKTS_6 6
172 + {
173 + X86_SOCKET_UNKNOWN, /* 0b000 */
174 + X86_SOCKET_AM3R2, /* 0b001 */
175 + X86_SOCKET_UNKNOWN, /* 0b010 */
176 + X86_SOCKET_G34, /* 0b011 */
177 + X86_SOCKET_UNKNOWN, /* 0b100 */
178 + X86_SOCKET_C32, /* 0b101 */
179 + X86_SOCKET_UNKNOWN, /* 0b110 */
180 + X86_SOCKET_UNKNOWN /* 0b111 */
181 + },
182 +
183 + /*
184 + * Family 0x15 models 10 - 1f
185 + */
186 +#define A_SKTS_7 7
187 + {
188 + X86_SOCKET_FP2, /* 0b000 */
189 + X86_SOCKET_FS1R2, /* 0b001 */
190 + X86_SOCKET_FM2, /* 0b010 */
191 + X86_SOCKET_UNKNOWN, /* 0b011 */
192 + X86_SOCKET_UNKNOWN, /* 0b100 */
193 + X86_SOCKET_UNKNOWN, /* 0b101 */
194 + X86_SOCKET_UNKNOWN, /* 0b110 */
195 + X86_SOCKET_UNKNOWN /* 0b111 */
196 + },
197 +
128 198 };
129 199
130 200 struct amd_sktmap_s {
131 201 uint32_t skt_code;
132 202 char sktstr[16];
133 203 };
134 -static struct amd_sktmap_s amd_sktmap[15] = {
204 +static struct amd_sktmap_s amd_sktmap[23] = {
135 205 { X86_SOCKET_754, "754" },
136 206 { X86_SOCKET_939, "939" },
137 207 { X86_SOCKET_940, "940" },
138 208 { X86_SOCKET_S1g1, "S1g1" },
139 209 { X86_SOCKET_AM2, "AM2" },
140 210 { X86_SOCKET_F1207, "F(1207)" },
141 211 { X86_SOCKET_S1g2, "S1g2" },
142 212 { X86_SOCKET_S1g3, "S1g3" },
143 213 { X86_SOCKET_AM, "AM" },
144 214 { X86_SOCKET_AM2R2, "AM2r2" },
145 215 { X86_SOCKET_AM3, "AM3" },
146 216 { X86_SOCKET_G34, "G34" },
147 217 { X86_SOCKET_ASB2, "ASB2" },
148 218 { X86_SOCKET_C32, "C32" },
219 + { X86_SOCKET_FT1, "FT1" },
220 + { X86_SOCKET_FM1, "FM1" },
221 + { X86_SOCKET_FS1, "FS1" },
222 + { X86_SOCKET_AM3R2, "AM3r2" },
223 + { X86_SOCKET_FP2, "FP2" },
224 + { X86_SOCKET_FS1R2, "FS1r2" },
225 + { X86_SOCKET_FM2, "FM2" },
149 226 { X86_SOCKET_UNKNOWN, "Unknown" }
150 227 };
151 228
152 229 /*
153 230 * Table for mapping AMD Family 0xf and AMD Family 0x10 model/stepping
154 231 * combination to chip "revision" and socket type.
155 232 *
156 233 * The first member of this array that matches a given family, extended model
157 234 * plus model range, and stepping range will be considered a match.
158 235 */
159 236 static const struct amd_rev_mapent {
160 237 uint_t rm_family;
161 238 uint_t rm_modello;
162 239 uint_t rm_modelhi;
163 240 uint_t rm_steplo;
164 241 uint_t rm_stephi;
165 242 uint32_t rm_chiprev;
166 243 const char *rm_chiprevstr;
167 244 int rm_sktidx;
168 245 } amd_revmap[] = {
169 246 /*
170 247 * =============== AuthenticAMD Family 0xf ===============
171 248 */
172 249
173 250 /*
174 251 * Rev B includes model 0x4 stepping 0 and model 0x5 stepping 0 and 1.
175 252 */
176 253 { 0xf, 0x04, 0x04, 0x0, 0x0, X86_CHIPREV_AMD_F_REV_B, "B", A_SKTS_0 },
177 254 { 0xf, 0x05, 0x05, 0x0, 0x1, X86_CHIPREV_AMD_F_REV_B, "B", A_SKTS_0 },
178 255 /*
179 256 * Rev C0 includes model 0x4 stepping 8 and model 0x5 stepping 8
180 257 */
181 258 { 0xf, 0x04, 0x05, 0x8, 0x8, X86_CHIPREV_AMD_F_REV_C0, "C0", A_SKTS_0 },
182 259 /*
183 260 * Rev CG is the rest of extended model 0x0 - i.e., everything
184 261 * but the rev B and C0 combinations covered above.
185 262 */
186 263 { 0xf, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_CG, "CG", A_SKTS_0 },
187 264 /*
188 265 * Rev D has extended model 0x1.
189 266 */
190 267 { 0xf, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_D, "D", A_SKTS_0 },
191 268 /*
192 269 * Rev E has extended model 0x2.
193 270 * Extended model 0x3 is unused but available to grow into.
194 271 */
195 272 { 0xf, 0x20, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_E, "E", A_SKTS_0 },
196 273 /*
197 274 * Rev F has extended models 0x4 and 0x5.
198 275 */
199 276 { 0xf, 0x40, 0x5f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_F, "F", A_SKTS_1 },
200 277 /*
201 278 * Rev G has extended model 0x6.
202 279 */
203 280 { 0xf, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_G, "G", A_SKTS_1 },
204 281
205 282 /*
206 283 * =============== AuthenticAMD Family 0x10 ===============
207 284 */
208 285
209 286 /*
210 287 * Rev A has model 0 and stepping 0/1/2 for DR-{A0,A1,A2}.
211 288 * Give all of model 0 stepping range to rev A.
212 289 */
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213 290 { 0x10, 0x00, 0x00, 0x0, 0x2, X86_CHIPREV_AMD_10_REV_A, "A", A_SKTS_2 },
214 291
215 292 /*
216 293 * Rev B has model 2 and steppings 0/1/0xa/2 for DR-{B0,B1,BA,B2}.
217 294 * Give all of model 2 stepping range to rev B.
218 295 */
219 296 { 0x10, 0x02, 0x02, 0x0, 0xf, X86_CHIPREV_AMD_10_REV_B, "B", A_SKTS_2 },
220 297
221 298 /*
222 299 * Rev C has models 4-6 (depending on L3 cache configuration)
223 - * Give all of models 4-6 stepping range to rev C.
300 + * Give all of models 4-6 stepping range 0-2 to rev C2.
224 301 */
225 - { 0x10, 0x04, 0x06, 0x0, 0xf, X86_CHIPREV_AMD_10_REV_C, "C", A_SKTS_2 },
302 + { 0x10, 0x4, 0x6, 0x0, 0x2, X86_CHIPREV_AMD_10_REV_C2, "C2", A_SKTS_2 },
226 303
227 304 /*
305 + * Rev C has models 4-6 (depending on L3 cache configuration)
306 + * Give all of models 4-6 stepping range >= 3 to rev C3.
307 + */
308 + { 0x10, 0x4, 0x6, 0x3, 0xf, X86_CHIPREV_AMD_10_REV_C3, "C3", A_SKTS_2 },
309 +
310 + /*
228 311 * Rev D has models 8 and 9
229 - * Give all of model 8 and 9 stepping range to rev D.
312 + * Give all of model 8 and 9 stepping 0 to rev D0.
230 313 */
231 - { 0x10, 0x08, 0x09, 0x0, 0xf, X86_CHIPREV_AMD_10_REV_D, "D", A_SKTS_2 },
314 + { 0x10, 0x8, 0x9, 0x0, 0x0, X86_CHIPREV_AMD_10_REV_D0, "D0", A_SKTS_2 },
232 315
233 316 /*
317 + * Rev D has models 8 and 9
318 + * Give all of model 8 and 9 stepping range >= 1 to rev D1.
319 + */
320 + { 0x10, 0x8, 0x9, 0x1, 0xf, X86_CHIPREV_AMD_10_REV_D1, "D1", A_SKTS_2 },
321 +
322 + /*
323 + * Rev E has models A and stepping 0
324 + * Give all of model A stepping range to rev E.
325 + */
326 + { 0x10, 0xA, 0xA, 0x0, 0xf, X86_CHIPREV_AMD_10_REV_E, "E", A_SKTS_2 },
327 +
328 + /*
234 329 * =============== AuthenticAMD Family 0x11 ===============
235 330 */
236 - { 0x11, 0x03, 0x3, 0x0, 0xf, X86_CHIPREV_AMD_11, "B", A_SKTS_3 },
331 + { 0x11, 0x03, 0x03, 0x0, 0xf, X86_CHIPREV_AMD_11_REV_B, "B", A_SKTS_3 },
332 +
333 + /*
334 + * =============== AuthenticAMD Family 0x12 ===============
335 + */
336 + { 0x12, 0x01, 0x01, 0x0, 0xf, X86_CHIPREV_AMD_12_REV_B, "B", A_SKTS_4 },
337 +
338 + /*
339 + * =============== AuthenticAMD Family 0x14 ===============
340 + */
341 + { 0x14, 0x01, 0x01, 0x0, 0xf, X86_CHIPREV_AMD_14_REV_B, "B", A_SKTS_5 },
342 + { 0x14, 0x02, 0x02, 0x0, 0xf, X86_CHIPREV_AMD_14_REV_C, "C", A_SKTS_5 },
343 +
344 + /*
345 + * =============== AuthenticAMD Family 0x15 ===============
346 + */
347 + { 0x15, 0x01, 0x01, 0x2, 0x2, X86_CHIPREV_AMD_15OR_REV_B2, "B2",
348 + A_SKTS_6 },
349 + { 0x15, 0x10, 0x10, 0x1, 0x1, X86_CHIPREV_AMD_15TN_REV_A1, "A1",
350 + A_SKTS_7 },
237 351 };
238 352
239 353 static void
240 354 synth_amd_info(uint_t family, uint_t model, uint_t step,
241 355 uint32_t *skt_p, uint32_t *chiprev_p, const char **chiprevstr_p)
242 356 {
243 357 const struct amd_rev_mapent *rmp;
244 358 int found = 0;
245 359 int i;
246 360
247 361 if (family < 0xf)
248 362 return;
249 363
250 364 for (i = 0, rmp = amd_revmap; i < sizeof (amd_revmap) / sizeof (*rmp);
251 365 i++, rmp++) {
252 366 if (family == rmp->rm_family &&
253 367 model >= rmp->rm_modello && model <= rmp->rm_modelhi &&
254 368 step >= rmp->rm_steplo && step <= rmp->rm_stephi) {
255 369 found = 1;
256 370 break;
257 371 }
258 372 }
259 373
260 374 if (!found)
261 375 return;
262 376
263 377 if (chiprev_p != NULL)
264 378 *chiprev_p = rmp->rm_chiprev;
265 379 if (chiprevstr_p != NULL)
266 380 *chiprevstr_p = rmp->rm_chiprevstr;
267 381
268 382 if (skt_p != NULL) {
269 383 int platform;
270 384
271 385 #ifdef __xpv
272 386 /* PV guest */
273 387 if (!is_controldom()) {
274 388 *skt_p = X86_SOCKET_UNKNOWN;
275 389 return;
276 390 }
277 391 #endif
278 392 platform = get_hwenv();
279 393
280 394 if ((platform == HW_XEN_HVM) || (platform == HW_VMWARE)) {
281 395 *skt_p = X86_SOCKET_UNKNOWN;
282 396 } else if (family == 0xf) {
283 397 *skt_p = amd_skts[rmp->rm_sktidx][model & 0x3];
284 398 } else {
285 399 /*
286 400 * Starting with family 10h, socket type is stored in
287 401 * CPUID Fn8000_0001_EBX
288 402 */
289 403 struct cpuid_regs cp;
290 404 int idx;
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291 405
292 406 cp.cp_eax = 0x80000001;
293 407 (void) __cpuid_insn(&cp);
294 408
295 409 /* PkgType bits */
296 410 idx = BITX(cp.cp_ebx, 31, 28);
297 411
298 412 if (idx > 7) {
299 413 /* Reserved bits */
300 414 *skt_p = X86_SOCKET_UNKNOWN;
301 - } else if (family == 0x10 &&
302 - amd_skts[rmp->rm_sktidx][idx] ==
303 - X86_SOCKET_AM) {
415 + } else {
416 + *skt_p = amd_skts[rmp->rm_sktidx][idx];
417 + }
418 + if (family == 0x10) {
304 419 /*
305 420 * Look at Ddr3Mode bit of DRAM Configuration
306 421 * High Register to decide whether this is
307 - * AM2r2 (aka AM2+) or AM3.
422 + * actually AM3 or S1g4.
308 423 */
309 424 uint32_t val;
310 425
311 426 val = pci_getl_func(0, 24, 2, 0x94);
312 - if (BITX(val, 8, 8))
313 - *skt_p = X86_SOCKET_AM3;
314 - else
315 - *skt_p = X86_SOCKET_AM2R2;
316 - } else {
317 - *skt_p = amd_skts[rmp->rm_sktidx][idx];
427 + if (BITX(val, 8, 8)) {
428 + if (*skt_p == X86_SOCKET_AM2R2)
429 + *skt_p = X86_SOCKET_AM3;
430 + else if (*skt_p == X86_SOCKET_S1g3)
431 + *skt_p = X86_SOCKET_S1g4;
432 + }
318 433 }
319 434 }
320 435 }
321 436 }
322 437
323 438 uint32_t
324 439 _cpuid_skt(uint_t vendor, uint_t family, uint_t model, uint_t step)
325 440 {
326 441 uint32_t skt = X86_SOCKET_UNKNOWN;
327 442
328 443 switch (vendor) {
329 444 case X86_VENDOR_AMD:
330 445 synth_amd_info(family, model, step, &skt, NULL, NULL);
331 446 break;
332 447
333 448 default:
334 449 break;
335 450
336 451 }
337 452
338 453 return (skt);
339 454 }
340 455
341 456 const char *
342 457 _cpuid_sktstr(uint_t vendor, uint_t family, uint_t model, uint_t step)
343 458 {
344 459 const char *sktstr = "Unknown";
345 460 struct amd_sktmap_s *sktmapp;
346 461 uint32_t skt = X86_SOCKET_UNKNOWN;
347 462
348 463 switch (vendor) {
349 464 case X86_VENDOR_AMD:
350 465 synth_amd_info(family, model, step, &skt, NULL, NULL);
351 466
352 467 sktmapp = amd_sktmap;
353 468 while (sktmapp->skt_code != X86_SOCKET_UNKNOWN) {
354 469 if (sktmapp->skt_code == skt)
355 470 break;
356 471 sktmapp++;
357 472 }
358 473 sktstr = sktmapp->sktstr;
359 474 break;
360 475
361 476 default:
362 477 break;
363 478
364 479 }
365 480
366 481 return (sktstr);
367 482 }
368 483
369 484 uint32_t
370 485 _cpuid_chiprev(uint_t vendor, uint_t family, uint_t model, uint_t step)
371 486 {
372 487 uint32_t chiprev = X86_CHIPREV_UNKNOWN;
373 488
374 489 switch (vendor) {
375 490 case X86_VENDOR_AMD:
376 491 synth_amd_info(family, model, step, NULL, &chiprev, NULL);
377 492 break;
378 493
379 494 default:
380 495 break;
381 496
382 497 }
383 498
384 499 return (chiprev);
385 500 }
386 501
387 502 const char *
388 503 _cpuid_chiprevstr(uint_t vendor, uint_t family, uint_t model, uint_t step)
389 504 {
390 505 const char *revstr = "Unknown";
391 506
392 507 switch (vendor) {
393 508 case X86_VENDOR_AMD:
394 509 synth_amd_info(family, model, step, NULL, NULL, &revstr);
395 510 break;
396 511
397 512 default:
398 513 break;
399 514
400 515 }
401 516
402 517 return (revstr);
403 518
404 519 }
405 520
406 521 /*
407 522 * CyrixInstead is a variable used by the Cyrix detection code
408 523 * in locore.
409 524 */
410 525 const char CyrixInstead[] = X86_VENDORSTR_CYRIX;
411 526
412 527 /*
413 528 * Map the vendor string to a type code
414 529 */
415 530 uint_t
416 531 _cpuid_vendorstr_to_vendorcode(char *vendorstr)
417 532 {
418 533 if (strcmp(vendorstr, X86_VENDORSTR_Intel) == 0)
419 534 return (X86_VENDOR_Intel);
420 535 else if (strcmp(vendorstr, X86_VENDORSTR_AMD) == 0)
421 536 return (X86_VENDOR_AMD);
422 537 else if (strcmp(vendorstr, X86_VENDORSTR_TM) == 0)
423 538 return (X86_VENDOR_TM);
424 539 else if (strcmp(vendorstr, CyrixInstead) == 0)
425 540 return (X86_VENDOR_Cyrix);
426 541 else if (strcmp(vendorstr, X86_VENDORSTR_UMC) == 0)
427 542 return (X86_VENDOR_UMC);
428 543 else if (strcmp(vendorstr, X86_VENDORSTR_NexGen) == 0)
429 544 return (X86_VENDOR_NexGen);
430 545 else if (strcmp(vendorstr, X86_VENDORSTR_Centaur) == 0)
431 546 return (X86_VENDOR_Centaur);
432 547 else if (strcmp(vendorstr, X86_VENDORSTR_Rise) == 0)
433 548 return (X86_VENDOR_Rise);
434 549 else if (strcmp(vendorstr, X86_VENDORSTR_SiS) == 0)
435 550 return (X86_VENDOR_SiS);
436 551 else if (strcmp(vendorstr, X86_VENDORSTR_NSC) == 0)
437 552 return (X86_VENDOR_NSC);
438 553 else
439 554 return (X86_VENDOR_IntelClone);
440 555 }
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