120         (X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_10_REV_A) ? 3 : 0))
 121 
 122 /*
 123  * Families/revision for which we wish not to machine check for GART
 124  * table walk errors - bit 10 of NB CTL.
 125  */
 126 #define AUTHAMD_NOGARTTBLWLK_MC(rev) \
 127         (X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_F_REV_B) || \
 128         X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_10_REV_A))
 129 
 130 /*
 131  * Families/revisions that are potentially L3 capable
 132  */
 133 #define AUTHAMD_L3CAPABLE(rev) \
 134         (X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_10_REV_A))
 135 
 136 /*
 137  * Families/revisions that support x8 ChipKill ECC
 138  */
 139 #define AUTHAMD_SUPPORTS_X8ECC(rev) \
 140         (X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_10_REV_D))
 141 
 142 /*
 143  * We recognise main memory ECC errors for AUTHAMD_MEMECC_RECOGNISED
 144  * revisions as:
 145  *
 146  *      - being reported by the NB
 147  *      - being a compound bus/interconnect error (external to chip)
 148  *      - having LL of LG
 149  *      - having II of MEM (but could still be a master/target abort)
 150  *      - having CECC or UECC set
 151  *
 152  * We do not check the extended error code (first nibble of the
 153  * model-specific error code on AMD) since this has changed from
 154  * family 0xf to family 0x10 (ext code 0 now reserved on family 0x10).
 155  * Instead we use CECC/UECC to separate off the master/target
 156  * abort cases.
 157  *
 158  * We insist that the detector be the NorthBridge bank;  although
 159  * IC/DC can report some main memory errors, they do not capture
 160  * an address at sufficient resolution to be useful and the NB will

 120         (X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_10_REV_A) ? 3 : 0))
 121 
 122 /*
 123  * Families/revision for which we wish not to machine check for GART
 124  * table walk errors - bit 10 of NB CTL.
 125  */
 126 #define AUTHAMD_NOGARTTBLWLK_MC(rev) \
 127         (X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_F_REV_B) || \
 128         X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_10_REV_A))
 129 
 130 /*
 131  * Families/revisions that are potentially L3 capable
 132  */
 133 #define AUTHAMD_L3CAPABLE(rev) \
 134         (X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_10_REV_A))
 135 
 136 /*
 137  * Families/revisions that support x8 ChipKill ECC
 138  */
 139 #define AUTHAMD_SUPPORTS_X8ECC(rev) \
 140         (X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_10_REV_D0))
 141 
 142 /*
 143  * We recognise main memory ECC errors for AUTHAMD_MEMECC_RECOGNISED
 144  * revisions as:
 145  *
 146  *      - being reported by the NB
 147  *      - being a compound bus/interconnect error (external to chip)
 148  *      - having LL of LG
 149  *      - having II of MEM (but could still be a master/target abort)
 150  *      - having CECC or UECC set
 151  *
 152  * We do not check the extended error code (first nibble of the
 153  * model-specific error code on AMD) since this has changed from
 154  * family 0xf to family 0x10 (ext code 0 now reserved on family 0x10).
 155  * Instead we use CECC/UECC to separate off the master/target
 156  * abort cases.
 157  *
 158  * We insist that the detector be the NorthBridge bank;  although
 159  * IC/DC can report some main memory errors, they do not capture
 160  * an address at sufficient resolution to be useful and the NB will