1 /*
2 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
3 * Use is subject to license terms.
4 */
5 /*
6 * radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
7 *
8 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
9 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
10 * All rights reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
29 * DEALINGS IN THE SOFTWARE.
30 *
31 * Authors:
32 * Kevin E. Martin <martin@valinux.com>
33 * Gareth Hughes <gareth@valinux.com>
34 */
35
36 #ifndef __RADEON_DRV_H__
37 #define __RADEON_DRV_H__
38
39 /*
40 * Enable debugging information outputs. Need to recompile
41 *
42 * #define RADEON_FIFO_DEBUG 1
43 */
44
45 /* General customization: */
46
47 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
48
49 #define DRIVER_NAME "radeon"
50 #define DRIVER_DESC "ATI Radeon"
51 #define DRIVER_DATE "20060524"
52
53 /*
54 * Interface history:
55 *
56 * 1.1 - ??
57 * 1.2 - Add vertex2 ioctl (keith)
58 * - Add stencil capability to clear ioctl (gareth, keith)
59 * - Increase MAX_TEXTURE_LEVELS (brian)
60 * 1.3 - Add cmdbuf ioctl (keith)
61 * - Add support for new radeon packets (keith)
62 * - Add getparam ioctl (keith)
63 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
64 * 1.4 - Add scratch registers to get_param ioctl.
65 * 1.5 - Add r200 packets to cmdbuf ioctl
66 * - Add r200 function to init ioctl
67 * - Add 'scalar2' instruction to cmdbuf
68 * 1.6 - Add static GART memory manager
69 * Add irq handler (won't be turned on unless X server knows to)
70 * Add irq ioctls and irq_active getparam.
71 * Add wait command for cmdbuf ioctl
72 * Add GART offset query for getparam
73 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
74 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
75 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
76 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
77 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
78 * Add 'GET' queries for starting additional clients on different
79 * VT's.
80 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
81 * Add texture rectangle support for r100.
82 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
83 * clients use to tell the DRM where they think the framebuffer is
84 * located in the card's address space
85 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
86 * and GL_EXT_blend_[func|equation]_separate on r200
87 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
88 * (No 3D support yet - just microcode loading).
89 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
90 * - Add hyperz support, add hyperz flags to clear ioctl.
91 * 1.14- Add support for color tiling
92 * - Add R100/R200 surface allocation/free support
93 * 1.15- Add support for texture micro tiling
94 * - Add support for r100 cube maps
95 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
96 * texture filtering on r200
97 * 1.17- Add initial support for R300 (3D).
98 * 1.18- Add support for GL_ATI_fragment_shader, new packets
99 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
100 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and
101 * R200_EMIT_ATF_TFACTOR
102 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
103 * 1.19- Add support for gart table in FB memory and PCIE r300
104 * 1.20- Add support for r300 texrect
105 * 1.21- Add support for card type getparam
106 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
107 * 1.23- Add new radeon memory map work from benh
108 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
109 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
110 * new packet type)
111 */
112
113 #define DRIVER_MAJOR 1
114 #define DRIVER_MINOR 25
115 #define DRIVER_PATCHLEVEL 0
116
117 /*
118 * Radeon chip families
119 */
120 enum radeon_family {
121 CHIP_R100,
122 CHIP_RV100,
123 CHIP_RS100,
124 CHIP_RV200,
125 CHIP_RS200,
126 CHIP_R200,
127 CHIP_RV250,
128 CHIP_RS300,
129 CHIP_RV280,
130 CHIP_R300,
131 CHIP_R350,
132 CHIP_RV350,
133 CHIP_RV380,
134 CHIP_R420,
135 CHIP_RV410,
136 CHIP_RS400,
137 CHIP_LAST,
138 };
139
140 enum radeon_cp_microcode_version {
141 UCODE_R100,
142 UCODE_R200,
143 UCODE_R300,
144 };
145
146 /*
147 * Chip flags
148 */
149 #define RADEON_FAMILY_MASK 0x0000ffffUL
150 #define RADEON_FLAGS_MASK 0xffff0000UL
151 #define RADEON_IS_MOBILITY 0x00010000UL
152 #define RADEON_IS_IGP 0x00020000UL
153 #define RADEON_SINGLE_CRTC 0x00040000UL
154 #define RADEON_IS_AGP 0x00080000UL
155 #define RADEON_HAS_HIERZ 0x00100000UL
156 #define RADEON_IS_PCIE 0x00200000UL
157 #define RADEON_NEW_MEMMAP 0x00400000UL
158 #define RADEON_IS_PCI 0x00800000UL
159
160 #define GET_RING_HEAD(dev_priv) \
161 (dev_priv->writeback_works ? \
162 DRM_READ32((dev_priv)->ring_rptr, 0) : \
163 RADEON_READ(RADEON_CP_RB_RPTR))
164
165 #define SET_RING_HEAD(dev_priv, val) \
166 DRM_WRITE32((dev_priv)->ring_rptr, 0, (val))
167
168 typedef struct drm_radeon_freelist {
169 unsigned int age;
170 drm_buf_t *buf;
171 struct drm_radeon_freelist *next;
172 struct drm_radeon_freelist *prev;
173 } drm_radeon_freelist_t;
174
175 typedef struct drm_radeon_ring_buffer {
176 u32 *start;
177 u32 *end;
178 int size;
179 int size_l2qw;
180
181 u32 tail;
182 u32 tail_mask;
183 int space;
184
185 int high_mark;
186 } drm_radeon_ring_buffer_t;
187
188 typedef struct drm_radeon_depth_clear_t {
189 u32 rb3d_cntl;
190 u32 rb3d_zstencilcntl;
191 u32 se_cntl;
192 } drm_radeon_depth_clear_t;
193
194 struct drm_radeon_driver_file_fields {
195 int64_t radeon_fb_delta;
196 };
197
198 struct mem_block {
199 struct mem_block *next;
200 struct mem_block *prev;
201 int start;
202 int size;
203 drm_file_t *filp; /* 0: free, -1: heap, other: real files */
204 };
205
206 struct radeon_surface {
207 int refcount;
208 u32 lower;
209 u32 upper;
210 u32 flags;
211 };
212
213 struct radeon_virt_surface {
214 int surface_index;
215 u32 lower;
216 u32 upper;
217 u32 flags;
218 drm_file_t *filp;
219 };
220
221 typedef struct drm_radeon_private {
222
223 drm_radeon_ring_buffer_t ring;
224 drm_radeon_sarea_t *sarea_priv;
225
226 u32 fb_location;
227 u32 fb_size;
228 int new_memmap;
229
230 int gart_size;
231 u32 gart_vm_start;
232 unsigned long gart_buffers_offset;
233
234 int cp_mode;
235 int cp_running;
236
237 drm_radeon_freelist_t *head;
238 drm_radeon_freelist_t *tail;
239 int last_buf;
240 volatile u32 *scratch;
241 int writeback_works;
242
243 int usec_timeout;
244
245 int microcode_version;
246
247 struct {
248 u32 boxes;
249 int freelist_timeouts;
250 int freelist_loops;
251 int requested_bufs;
252 int last_frame_reads;
253 int last_clear_reads;
254 int clears;
255 int texture_uploads;
256 } stats;
257
258 int do_boxes;
259 int page_flipping;
260 int current_page;
261
262 u32 color_fmt;
263 unsigned int front_offset;
264 unsigned int front_pitch;
265 unsigned int back_offset;
266 unsigned int back_pitch;
267
268 u32 depth_fmt;
269 unsigned int depth_offset;
270 unsigned int depth_pitch;
271
272 u32 front_pitch_offset;
273 u32 back_pitch_offset;
274 u32 depth_pitch_offset;
275
276 drm_radeon_depth_clear_t depth_clear;
277
278 unsigned long ring_offset;
279 unsigned long ring_rptr_offset;
280 unsigned long buffers_offset;
281 unsigned long gart_textures_offset;
282
283 drm_local_map_t *sarea;
284 drm_local_map_t *mmio;
285 drm_local_map_t *cp_ring;
286 drm_local_map_t *ring_rptr;
287 drm_local_map_t *gart_textures;
288
289 struct mem_block *gart_heap;
290 struct mem_block *fb_heap;
291
292 /* SW interrupt */
293 wait_queue_head_t swi_queue;
294 atomic_t swi_emitted;
295 int vblank_crtc;
296 uint32_t irq_enable_reg;
297 int irq_enabled;
298
299
300 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
301 struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES];
302
303 unsigned long pcigart_offset;
304 drm_ati_pcigart_info gart_info;
305
306 u32 scratch_ages[5];
307
308 /* starting from here on, data is preserved accross an open */
309 uint32_t flags; /* see radeon_chip_flags */
310
311 } drm_radeon_private_t;
312
313 typedef struct drm_radeon_buf_priv {
314 u32 age;
315 } drm_radeon_buf_priv_t;
316
317 typedef struct drm_radeon_kcmd_buffer {
318 int bufsz;
319 char *buf;
320 int nbox;
321 drm_clip_rect_t __user *boxes;
322 } drm_radeon_kcmd_buffer_t;
323
324 extern int radeon_no_wb;
325 extern drm_ioctl_desc_t radeon_ioctls[];
326 extern int radeon_max_ioctl;
327
328
329 /*
330 * Check whether the given hardware address is inside the framebuffer or the
331 * GART area.
332 */
333 #define RADEON_CHECK_OFFSET(dev_priv, off) \
334 (((off >= dev_priv->fb_location) && \
335 (off <= (dev_priv->fb_location + dev_priv->fb_size - 1))) || \
336 ((off >= dev_priv->gart_vm_start) && \
337 (off <= (dev_priv->gart_vm_start + dev_priv->gart_size - 1))))
338
339 /* radeon_cp.c */
340 extern int radeon_cp_init(DRM_IOCTL_ARGS);
341 extern int radeon_cp_start(DRM_IOCTL_ARGS);
342 extern int radeon_cp_stop(DRM_IOCTL_ARGS);
343 extern int radeon_cp_reset(DRM_IOCTL_ARGS);
344 extern int radeon_cp_idle(DRM_IOCTL_ARGS);
345 extern int radeon_cp_resume(DRM_IOCTL_ARGS);
346 extern int radeon_engine_reset(DRM_IOCTL_ARGS);
347 extern int radeon_fullscreen(DRM_IOCTL_ARGS);
348 extern int radeon_cp_buffers(DRM_IOCTL_ARGS);
349
350 extern void radeon_freelist_reset(drm_device_t *dev);
351 extern drm_buf_t *radeon_freelist_get(drm_device_t *dev);
352
353 extern int radeon_wait_ring(drm_radeon_private_t *dev_priv, int n);
354
355 extern int radeon_do_cp_idle(drm_radeon_private_t *dev_priv);
356
357 extern int radeon_mem_alloc(DRM_IOCTL_ARGS);
358 extern int radeon_mem_free(DRM_IOCTL_ARGS);
359 extern int radeon_mem_init_heap(DRM_IOCTL_ARGS);
360 extern void radeon_mem_takedown(struct mem_block **heap);
361 extern void radeon_mem_release(drm_file_t *filp, struct mem_block *heap);
362
363 /* radeon_irq.c */
364 extern int radeon_irq_emit(DRM_IOCTL_ARGS);
365 extern int radeon_irq_wait(DRM_IOCTL_ARGS);
366
367 extern void radeon_do_release(drm_device_t *dev);
368 extern int radeon_driver_vblank_wait(drm_device_t *dev,
369 unsigned int *sequence);
370 extern int radeon_driver_vblank_wait2(drm_device_t *dev,
371 unsigned int *sequence);
372 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
373 extern int radeon_driver_irq_preinstall(drm_device_t *dev);
374 extern void radeon_driver_irq_postinstall(drm_device_t *dev);
375 extern void radeon_driver_irq_uninstall(drm_device_t *dev);
376 extern int radeon_vblank_crtc_get(struct drm_device *dev);
377 extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
378
379 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
380 extern int radeon_driver_unload(struct drm_device *dev);
381 extern int radeon_driver_firstopen(struct drm_device *dev);
382 extern void radeon_driver_preclose(drm_device_t *dev, drm_file_t *filp);
383 extern void radeon_driver_postclose(drm_device_t *dev, drm_file_t *filp);
384 extern void radeon_driver_lastclose(drm_device_t *dev);
385 extern int radeon_driver_open(drm_device_t *dev, drm_file_t *filp_priv);
386 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
387 unsigned long arg);
388
389 /* r300_cmdbuf.c */
390 extern void r300_init_reg_flags(void);
391
392 extern int r300_do_cp_cmdbuf(drm_device_t *dev,
393 drm_file_t *fpriv, drm_radeon_kcmd_buffer_t *cmdbuf);
394
395 /* Flags for stats.boxes */
396 #define RADEON_BOX_DMA_IDLE 0x1
397 #define RADEON_BOX_RING_FULL 0x2
398 #define RADEON_BOX_FLIP 0x4
399 #define RADEON_BOX_WAIT_IDLE 0x8
400 #define RADEON_BOX_TEXTURE_LOAD 0x10
401
402 /*
403 * Register definitions, register access macros and drmAddMap constants
404 * for Radeon kernel driver.
405 */
406 #define RADEON_AGP_COMMAND 0x0f60
407 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
408 #define RADEON_AGP_ENABLE (1<<8)
409 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
410 #define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
411 #define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
412 #define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
413 #define RADEON_SCISSOR_0_ENABLE (1 << 28)
414 #define RADEON_SCISSOR_1_ENABLE (1 << 29)
415 #define RADEON_SCISSOR_2_ENABLE (1 << 30)
416
417 #define RADEON_BUS_CNTL 0x0030
418 #define RADEON_BUS_MASTER_DIS (1 << 6)
419
420 #define RADEON_CLOCK_CNTL_DATA 0x000c
421 #define RADEON_PLL_WR_EN (1 << 7)
422 #define RADEON_CLOCK_CNTL_INDEX 0x0008
423 #define RADEON_CONFIG_APER_SIZE 0x0108
424 #define RADEON_CONFIG_MEMSIZE 0x00f8
425 #define RADEON_CRTC_OFFSET 0x0224
426 #define RADEON_CRTC_OFFSET_CNTL 0x0228
427 #define RADEON_CRTC_TILE_EN (1 << 15)
428 #define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
429 #define RADEON_CRTC2_OFFSET 0x0324
430 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
431
432 #define RADEON_PCIE_INDEX 0x0030
433 #define RADEON_PCIE_DATA 0x0034
434 #define RADEON_PCIE_TX_GART_CNTL 0x10
435 #define RADEON_PCIE_TX_GART_EN (1 << 0)
436 #define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
437 #define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
438 #define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
439 #define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3)
440 #define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3)
441 #define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5)
442 #define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8)
443 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
444 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
445 #define RADEON_PCIE_TX_GART_BASE 0x13
446 #define RADEON_PCIE_TX_GART_START_LO 0x14
447 #define RADEON_PCIE_TX_GART_START_HI 0x15
448 #define RADEON_PCIE_TX_GART_END_LO 0x16
449 #define RADEON_PCIE_TX_GART_END_HI 0x17
450
451 #define RADEON_MPP_TB_CONFIG 0x01c0
452 #define RADEON_MEM_CNTL 0x0140
453 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
454 #define RADEON_AGP_BASE 0x0170
455
456 #define RADEON_RB3D_COLOROFFSET 0x1c40
457 #define RADEON_RB3D_COLORPITCH 0x1c48
458
459 #define RADEON_SRC_X_Y 0x1590
460
461 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
462 #define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
463 #define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
464 #define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
465 #define RADEON_GMC_BRUSH_NONE (15 << 4)
466 #define RADEON_GMC_DST_16BPP (4 << 8)
467 #define RADEON_GMC_DST_24BPP (5 << 8)
468 #define RADEON_GMC_DST_32BPP (6 << 8)
469 #define RADEON_GMC_DST_DATATYPE_SHIFT 8
470 #define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
471 #define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
472 #define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
473 #define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
474 #define RADEON_GMC_WR_MSK_DIS (1 << 30)
475 #define RADEON_ROP3_S 0x00cc0000
476 #define RADEON_ROP3_P 0x00f00000
477 #define RADEON_DP_WRITE_MASK 0x16cc
478 #define RADEON_SRC_PITCH_OFFSET 0x1428
479 #define RADEON_DST_PITCH_OFFSET 0x142c
480 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
481 #define RADEON_DST_TILE_LINEAR (0 << 30)
482 #define RADEON_DST_TILE_MACRO (1 << 30)
483 #define RADEON_DST_TILE_MICRO ((uint_t)2 << 30)
484 #define RADEON_DST_TILE_BOTH ((uint_t)3 << 30)
485
486 #define RADEON_SCRATCH_REG0 0x15e0
487 #define RADEON_SCRATCH_REG1 0x15e4
488 #define RADEON_SCRATCH_REG2 0x15e8
489 #define RADEON_SCRATCH_REG3 0x15ec
490 #define RADEON_SCRATCH_REG4 0x15f0
491 #define RADEON_SCRATCH_REG5 0x15f4
492 #define RADEON_SCRATCH_UMSK 0x0770
493 #define RADEON_SCRATCH_ADDR 0x0774
494
495 #define RADEON_SCRATCHOFF(x) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
496
497 #define GET_SCRATCH(x) (dev_priv->writeback_works ? \
498 DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(x)) : \
499 RADEON_READ(RADEON_SCRATCH_REG0 + 4*(x)))
500
501 #define RADEON_GEN_INT_CNTL 0x0040
502 #define RADEON_CRTC_VBLANK_MASK (1 << 0)
503 #define RADEON_CRTC2_VBLANK_MASK (1 << 9)
504 #define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
505 #define RADEON_SW_INT_ENABLE (1 << 25)
506
507 #define RADEON_GEN_INT_STATUS 0x0044
508 #define RADEON_CRTC_VBLANK_STAT (1 << 0)
509 #define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
510 #define RADEON_CRTC2_VBLANK_STAT (1 << 9)
511 #define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
512 #define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
513 #define RADEON_SW_INT_TEST (1 << 25)
514 #define RADEON_SW_INT_TEST_ACK (1 << 25)
515 #define RADEON_SW_INT_FIRE (1 << 26)
516
517 #define RADEON_HOST_PATH_CNTL 0x0130
518 #define RADEON_HDP_SOFT_RESET (1 << 26)
519 #define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
520 #define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
521
522 #define RADEON_ISYNC_CNTL 0x1724
523 #define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
524 #define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
525 #define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
526 #define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
527 #define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
528 #define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
529
530 #define RADEON_RBBM_GUICNTL 0x172c
531 #define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
532 #define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
533 #define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
534 #define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
535
536 #define RADEON_MC_AGP_LOCATION 0x014c
537 #define RADEON_MC_FB_LOCATION 0x0148
538 #define RADEON_MCLK_CNTL 0x0012
539 #define RADEON_FORCEON_MCLKA (1 << 16)
540 #define RADEON_FORCEON_MCLKB (1 << 17)
541 #define RADEON_FORCEON_YCLKA (1 << 18)
542 #define RADEON_FORCEON_YCLKB (1 << 19)
543 #define RADEON_FORCEON_MC (1 << 20)
544 #define RADEON_FORCEON_AIC (1 << 21)
545
546 #define RADEON_PP_BORDER_COLOR_0 0x1d40
547 #define RADEON_PP_BORDER_COLOR_1 0x1d44
548 #define RADEON_PP_BORDER_COLOR_2 0x1d48
549 #define RADEON_PP_CNTL 0x1c38
550 #define RADEON_SCISSOR_ENABLE (1 << 1)
551 #define RADEON_PP_LUM_MATRIX 0x1d00
552 #define RADEON_PP_MISC 0x1c14
553 #define RADEON_PP_ROT_MATRIX_0 0x1d58
554 #define RADEON_PP_TXFILTER_0 0x1c54
555 #define RADEON_PP_TXOFFSET_0 0x1c5c
556 #define RADEON_PP_TXFILTER_1 0x1c6c
557 #define RADEON_PP_TXFILTER_2 0x1c84
558
559 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
560 #define RADEON_RB2D_DC_FLUSH (3 << 0)
561 #define RADEON_RB2D_DC_FREE (3 << 2)
562 #define RADEON_RB2D_DC_FLUSH_ALL 0xf
563 #define RADEON_RB2D_DC_BUSY 0x80000000
564 #define RADEON_RB3D_CNTL 0x1c3c
565 #define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
566 #define RADEON_PLANE_MASK_ENABLE (1 << 1)
567 #define RADEON_DITHER_ENABLE (1 << 2)
568 #define RADEON_ROUND_ENABLE (1 << 3)
569 #define RADEON_SCALE_DITHER_ENABLE (1 << 4)
570 #define RADEON_DITHER_INIT (1 << 5)
571 #define RADEON_ROP_ENABLE (1 << 6)
572 #define RADEON_STENCIL_ENABLE (1 << 7)
573 #define RADEON_Z_ENABLE (1 << 8)
574 #define RADEON_ZBLOCK16 (1 << 15)
575 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
576 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
577 #define RADEON_RB3D_DEPTHPITCH 0x1c28
578 #define RADEON_RB3D_PLANEMASK 0x1d84
579 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
580 #define RADEON_RB3D_ZCACHE_MODE 0x3250
581 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
582 #define RADEON_RB3D_ZC_FLUSH (1 << 0)
583 #define RADEON_RB3D_ZC_FREE (1 << 2)
584 #define RADEON_RB3D_ZC_FLUSH_ALL 0x5
585 #define RADEON_RB3D_ZC_BUSY 0x80000000UL
586 #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
587 #define RADEON_RB3D_DC_FLUSH (3 << 0)
588 #define RADEON_RB3D_DC_FREE (3 << 2)
589 #define RADEON_RB3D_DC_FLUSH_ALL 0xf
590 #define RADEON_RB3D_DC_BUSY 0x80000000UL
591 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
592 #define RADEON_Z_TEST_MASK (7 << 4)
593 #define RADEON_Z_TEST_ALWAYS (7 << 4)
594 #define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
595 #define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
596 #define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
597 #define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
598 #define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
599 #define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
600 #define RADEON_FORCE_Z_DIRTY (1 << 29)
601 #define RADEON_Z_WRITE_ENABLE (1 << 30)
602 #define RADEON_Z_DECOMPRESSION_ENABLE 0x80000000UL
603 #define RADEON_RBBM_SOFT_RESET 0x00f0
604 #define RADEON_SOFT_RESET_CP (1 << 0)
605 #define RADEON_SOFT_RESET_HI (1 << 1)
606 #define RADEON_SOFT_RESET_SE (1 << 2)
607 #define RADEON_SOFT_RESET_RE (1 << 3)
608 #define RADEON_SOFT_RESET_PP (1 << 4)
609 #define RADEON_SOFT_RESET_E2 (1 << 5)
610 #define RADEON_SOFT_RESET_RB (1 << 6)
611 #define RADEON_SOFT_RESET_HDP (1 << 7)
612 #define RADEON_RBBM_STATUS 0x0e40
613 #define RADEON_RBBM_FIFOCNT_MASK 0x007f
614 #define RADEON_RBBM_ACTIVE 0X80000000UL
615 #define RADEON_RE_LINE_PATTERN 0x1cd0
616 #define RADEON_RE_MISC 0x26c4
617 #define RADEON_RE_TOP_LEFT 0x26c0
618 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
619 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
620 #define RADEON_RE_STIPPLE_DATA 0x1ccc
621
622 #define RADEON_SCISSOR_TL_0 0x1cd8
623 #define RADEON_SCISSOR_BR_0 0x1cdc
624 #define RADEON_SCISSOR_TL_1 0x1ce0
625 #define RADEON_SCISSOR_BR_1 0x1ce4
626 #define RADEON_SCISSOR_TL_2 0x1ce8
627 #define RADEON_SCISSOR_BR_2 0x1cec
628 #define RADEON_SE_COORD_FMT 0x1c50
629 #define RADEON_SE_CNTL 0x1c4c
630 #define RADEON_FFACE_CULL_CW (0 << 0)
631 #define RADEON_BFACE_SOLID (3 << 1)
632 #define RADEON_FFACE_SOLID (3 << 3)
633 #define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
634 #define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
635 #define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
636 #define RADEON_ALPHA_SHADE_FLAT (1 << 10)
637 #define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
638 #define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
639 #define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
640 #define RADEON_FOG_SHADE_FLAT (1 << 14)
641 #define RADEON_FOG_SHADE_GOURAUD (2 << 14)
642 #define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
643 #define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
644 #define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
645 #define RADEON_ROUND_MODE_TRUNC (0 << 28)
646 #define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
647 #define RADEON_SE_CNTL_STATUS 0x2140
648 #define RADEON_SE_LINE_WIDTH 0x1db8
649 #define RADEON_SE_VPORT_XSCALE 0x1d98
650 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
651 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
652 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
653 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
654 #define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
655 #define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
656 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
657 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
658 #define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
659 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
660 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
661 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
662 #define RADEON_SURFACE_CNTL 0x0b00
663 #define RADEON_SURF_TRANSLATION_DIS (1 << 8)
664 #define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
665 #define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
666 #define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
667 #define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
668 #define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
669 #define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
670 #define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
671 #define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
672 #define RADEON_SURFACE0_INFO 0x0b0c
673 #define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
674 #define RADEON_SURF_TILE_MODE_MASK (3 << 16)
675 #define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
676 #define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
677 #define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
678 #define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
679 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
680 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
681 #define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
682 #define RADEON_SURFACE1_INFO 0x0b1c
683 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
684 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
685 #define RADEON_SURFACE2_INFO 0x0b2c
686 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
687 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
688 #define RADEON_SURFACE3_INFO 0x0b3c
689 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
690 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
691 #define RADEON_SURFACE4_INFO 0x0b4c
692 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
693 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
694 #define RADEON_SURFACE5_INFO 0x0b5c
695 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
696 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
697 #define RADEON_SURFACE6_INFO 0x0b6c
698 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
699 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
700 #define RADEON_SURFACE7_INFO 0x0b7c
701 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
702 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
703 #define RADEON_SW_SEMAPHORE 0x013c
704
705 #define RADEON_WAIT_UNTIL 0x1720
706 #define RADEON_WAIT_CRTC_PFLIP (1 << 0)
707 #define RADEON_WAIT_2D_IDLE (1 << 14)
708 #define RADEON_WAIT_3D_IDLE (1 << 15)
709 #define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
710 #define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
711 #define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
712
713 #define RADEON_RB3D_ZMASKOFFSET 0x3234
714 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
715 #define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
716 #define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
717
718 /* CP registers */
719 #define RADEON_CP_ME_RAM_ADDR 0x07d4
720 #define RADEON_CP_ME_RAM_RADDR 0x07d8
721 #define RADEON_CP_ME_RAM_DATAH 0x07dc
722 #define RADEON_CP_ME_RAM_DATAL 0x07e0
723
724 #define RADEON_CP_RB_BASE 0x0700
725 #define RADEON_CP_RB_CNTL 0x0704
726 #define RADEON_BUF_SWAP_32BIT (2 << 16)
727 #define RADEON_RB_NO_UPDATE (1 << 27)
728
729 #define RADEON_CP_RB_RPTR_ADDR 0x070c
730 #define RADEON_CP_RB_RPTR 0x0710
731 #define RADEON_CP_RB_WPTR 0x0714
732
733 #define RADEON_CP_RB_WPTR_DELAY 0x0718
734 #define RADEON_PRE_WRITE_TIMER_SHIFT 0
735 #define RADEON_PRE_WRITE_LIMIT_SHIFT 23
736
737 #define RADEON_CP_IB_BASE 0x0738
738
739 #define RADEON_CP_CSQ_CNTL 0x0740
740 #define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
741 #define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
742 #define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
743 #define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
744 #define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
745 #define RADEON_CSQ_PRIBM_INDBM (4 << 28)
746 #define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
747
748 #define RADEON_AIC_CNTL 0x01d0
749 #define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
750 #define RADEON_AIC_STAT 0x01d4
751 #define RADEON_AIC_PT_BASE 0x01d8
752 #define RADEON_AIC_LO_ADDR 0x01dc
753 #define RADEON_AIC_HI_ADDR 0x01e0
754 #define RADEON_AIC_TLB_ADDR 0x01e4
755 #define RADEON_AIC_TLB_DATA 0x01e8
756
757 /* CP command packets */
758 #define RADEON_CP_PACKET0 0x00000000
759 #define RADEON_ONE_REG_WR (1 << 15)
760 #define RADEON_CP_PACKET1 0x40000000
761 #define RADEON_CP_PACKET2 0x80000000
762 #define RADEON_CP_PACKET3 0xC0000000
763 #define RADEON_CP_NOP 0x00001000
764 #define RADEON_CP_NEXT_CHAR 0x00001900
765 #define RADEON_CP_PLY_NEXTSCAN 0x00001D00
766 #define RADEON_CP_SET_SCISSORS 0x00001E00
767
768 /* GEN_INDX_PRIM is unsupported starting with R300 */
769 #define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
770 #define RADEON_WAIT_FOR_IDLE 0x00002600
771 #define RADEON_3D_DRAW_VBUF 0x00002800
772 #define RADEON_3D_DRAW_IMMD 0x00002900
773 #define RADEON_3D_DRAW_INDX 0x00002A00
774 #define RADEON_CP_LOAD_PALETTE 0x00002C00
775 #define RADEON_3D_LOAD_VBPNTR 0x00002F00
776 #define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
777 #define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
778 #define RADEON_3D_CLEAR_ZMASK 0x00003200
779 #define RADEON_CP_INDX_BUFFER 0x00003300
780 #define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
781 #define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
782 #define RADEON_CP_3D_DRAW_INDX_2 0x00003600
783 #define RADEON_3D_CLEAR_HIZ 0x00003700
784 #define RADEON_CP_3D_CLEAR_CMASK 0x00003802
785 #define RADEON_CNTL_HOSTDATA_BLT 0x00009400
786 #define RADEON_CNTL_PAINT_MULTI 0x00009A00
787 #define RADEON_CNTL_BITBLT_MULTI 0x00009B00
788 #define RADEON_CNTL_SET_SCISSORS 0xC0001E00
789
790 #define RADEON_CP_PACKET_MASK 0xC0000000
791 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
792 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
793 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
794 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
795
796 #define RADEON_VTX_Z_PRESENT 0x80000000
797 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
798
799 #define RADEON_PRIM_TYPE_NONE (0 << 0)
800 #define RADEON_PRIM_TYPE_POINT (1 << 0)
801 #define RADEON_PRIM_TYPE_LINE (2 << 0)
802 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
803 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
804 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
805 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
806 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
807 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
808 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
809 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
810 #define RADEON_PRIM_TYPE_MASK 0xf
811 #define RADEON_PRIM_WALK_IND (1 << 4)
812 #define RADEON_PRIM_WALK_LIST (2 << 4)
813 #define RADEON_PRIM_WALK_RING (3 << 4)
814 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
815 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
816 #define RADEON_MAOS_ENABLE (1 << 7)
817 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
818 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
819 #define RADEON_NUM_VERTICES_SHIFT 16
820
821 #define RADEON_COLOR_FORMAT_CI8 2
822 #define RADEON_COLOR_FORMAT_ARGB1555 3
823 #define RADEON_COLOR_FORMAT_RGB565 4
824 #define RADEON_COLOR_FORMAT_ARGB8888 6
825 #define RADEON_COLOR_FORMAT_RGB332 7
826 #define RADEON_COLOR_FORMAT_RGB8 9
827 #define RADEON_COLOR_FORMAT_ARGB4444 15
828
829 #define RADEON_TXFORMAT_I8 0
830 #define RADEON_TXFORMAT_AI88 1
831 #define RADEON_TXFORMAT_RGB332 2
832 #define RADEON_TXFORMAT_ARGB1555 3
833 #define RADEON_TXFORMAT_RGB565 4
834 #define RADEON_TXFORMAT_ARGB4444 5
835 #define RADEON_TXFORMAT_ARGB8888 6
836 #define RADEON_TXFORMAT_RGBA8888 7
837 #define RADEON_TXFORMAT_Y8 8
838 #define RADEON_TXFORMAT_VYUY422 10
839 #define RADEON_TXFORMAT_YVYU422 11
840 #define RADEON_TXFORMAT_DXT1 12
841 #define RADEON_TXFORMAT_DXT23 14
842 #define RADEON_TXFORMAT_DXT45 15
843
844 #define R200_PP_TXCBLEND_0 0x2f00
845 #define R200_PP_TXCBLEND_1 0x2f10
846 #define R200_PP_TXCBLEND_2 0x2f20
847 #define R200_PP_TXCBLEND_3 0x2f30
848 #define R200_PP_TXCBLEND_4 0x2f40
849 #define R200_PP_TXCBLEND_5 0x2f50
850 #define R200_PP_TXCBLEND_6 0x2f60
851 #define R200_PP_TXCBLEND_7 0x2f70
852 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
853 #define R200_PP_TFACTOR_0 0x2ee0
854 #define R200_SE_VTX_FMT_0 0x2088
855 #define R200_SE_VAP_CNTL 0x2080
856 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
857 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
858 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
859 #define R200_PP_TXFILTER_5 0x2ca0
860 #define R200_PP_TXFILTER_4 0x2c80
861 #define R200_PP_TXFILTER_3 0x2c60
862 #define R200_PP_TXFILTER_2 0x2c40
863 #define R200_PP_TXFILTER_1 0x2c20
864 #define R200_PP_TXFILTER_0 0x2c00
865 #define R200_PP_TXOFFSET_5 0x2d78
866 #define R200_PP_TXOFFSET_4 0x2d60
867 #define R200_PP_TXOFFSET_3 0x2d48
868 #define R200_PP_TXOFFSET_2 0x2d30
869 #define R200_PP_TXOFFSET_1 0x2d18
870 #define R200_PP_TXOFFSET_0 0x2d00
871
872 #define R200_PP_CUBIC_FACES_0 0x2c18
873 #define R200_PP_CUBIC_FACES_1 0x2c38
874 #define R200_PP_CUBIC_FACES_2 0x2c58
875 #define R200_PP_CUBIC_FACES_3 0x2c78
876 #define R200_PP_CUBIC_FACES_4 0x2c98
877 #define R200_PP_CUBIC_FACES_5 0x2cb8
878 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
879 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
880 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
881 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
882 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
883 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
884 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
885 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
886 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
887 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
888 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
889 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
890 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
891 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
892 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
893 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
894 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
895 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
896 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
897 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
898 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
899 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
900 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
901 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
902 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
903 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
904 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
905 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
906 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
907 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
908
909 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
910 #define R200_SE_VTE_CNTL 0x20b0
911 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
912 #define R200_PP_TAM_DEBUG3 0x2d9c
913 #define R200_PP_CNTL_X 0x2cc4
914 #define R200_SE_VAP_CNTL_STATUS 0x2140
915 #define R200_RE_SCISSOR_TL_0 0x1cd8
916 #define R200_RE_SCISSOR_TL_1 0x1ce0
917 #define R200_RE_SCISSOR_TL_2 0x1ce8
918 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
919 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
920 #define R200_SE_VTX_STATE_CNTL 0x2180
921 #define R200_RE_POINTSIZE 0x2648
922 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
923
924 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
925 #define RADEON_PP_TEX_SIZE_1 0x1d0c
926 #define RADEON_PP_TEX_SIZE_2 0x1d14
927
928 #define RADEON_PP_CUBIC_FACES_0 0x1d24
929 #define RADEON_PP_CUBIC_FACES_1 0x1d28
930 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
931 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
932 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
933 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
934
935 #define RADEON_SE_TCL_STATE_FLUSH 0x2284
936
937 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
938 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
939 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
940 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
941 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
942 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
943 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
944 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
945 #define R200_3D_DRAW_IMMD_2 0xC0003500
946 #define R200_SE_VTX_FMT_1 0x208c
947 #define R200_RE_CNTL 0x1c50
948
949 #define R200_RB3D_BLENDCOLOR 0x3218
950
951 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
952
953 #define R200_PP_TRI_PERF 0x2cf8
954
955 #define R200_PP_AFS_0 0x2f80
956 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
957
958 #define R200_VAP_PVS_CNTL_1 0x22D0
959
960 /* MPEG settings from VHA code */
961 #define RADEON_VHA_SETTO16_1 0x2694
962 #define RADEON_VHA_SETTO16_2 0x2680
963 #define RADEON_VHA_SETTO0_1 0x1840
964 #define RADEON_VHA_FB_OFFSET 0x19e4
965 #define RADEON_VHA_SETTO1AND70S 0x19d8
966 #define RADEON_VHA_DST_PITCH 0x1408
967
968 // set as reference header
969 #define RADEON_VHA_BACKFRAME0_OFF_Y 0x1840
970 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y 0x1844
971 #define RADEON_VHA_BACKFRAME0_OFF_U 0x1848
972 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_U 0x184c
973 #define RADOEN_VHA_BACKFRAME0_OFF_V 0x1850
974 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_V 0x1854
975 #define RADEON_VHA_FORWFRAME0_OFF_Y 0x1858
976 #define RADEON_VHA_FORWFRAME1_OFF_PITCH_Y 0x185c
977 #define RADEON_VHA_FORWFRAME0_OFF_U 0x1860
978 #define RADEON_VHA_FORWFRAME1_OFF_PITCH_U 0x1864
979 #define RADEON_VHA_FORWFRAME0_OFF_V 0x1868
980 #define RADEON_VHA_FORWFRAME0_OFF_PITCH_V 0x1880
981 #define RADEON_VHA_BACKFRAME0_OFF_Y_2 0x1884
982 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y_2 0x1888
983 #define RADEON_VHA_BACKFRAME0_OFF_U_2 0x188c
984 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_U_2 0x1890
985 #define RADEON_VHA_BACKFRAME0_OFF_V_2 0x1894
986 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_V_2 0x1898
987
988
989
990 /* Constants */
991 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
992
993 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
994 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
995 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
996 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
997 #define RADEON_LAST_DISPATCH 1
998
999 #define RADEON_MAX_VB_AGE 0x7fffffff
1000 #define RADEON_MAX_VB_VERTS (0xffff)
1001
1002 #define RADEON_RING_HIGH_MARK 128
1003
1004 #define RADEON_PCIGART_TABLE_SIZE (32*1024)
1005
1006 #define RADEON_READ(reg) \
1007 DRM_READ32(dev_priv->mmio, (reg))
1008 #define RADEON_WRITE(reg, val) \
1009 DRM_WRITE32(dev_priv->mmio, (reg), (val))
1010 #define RADEON_READ8(reg) \
1011 DRM_READ8(dev_priv->mmio, (reg))
1012 #define RADEON_WRITE8(reg, val) \
1013 DRM_WRITE8(dev_priv->mmio, (reg), (val))
1014
1015 #define RADEON_WRITE_PLL(addr, val) \
1016 do { \
1017 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
1018 ((addr) & 0x1f) | RADEON_PLL_WR_EN); \
1019 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
1020 } while (*"\0")
1021
1022 #define RADEON_WRITE_PCIE(addr, val) \
1023 do { \
1024 RADEON_WRITE8(RADEON_PCIE_INDEX, \
1025 ((addr) & 0xff)); \
1026 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
1027 } while (*"\0")
1028
1029 #define CP_PACKET0(reg, n) \
1030 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1031 #define CP_PACKET0_TABLE(reg, n) \
1032 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
1033 #define CP_PACKET1(reg0, reg1) \
1034 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1035 #define CP_PACKET2() \
1036 (RADEON_CP_PACKET2)
1037 #define CP_PACKET3(pkt, n) \
1038 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1039
1040 /*
1041 * Engine control helper macros
1042 */
1043
1044 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1045 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \
1046 OUT_RING((RADEON_WAIT_2D_IDLECLEAN | \
1047 RADEON_WAIT_HOST_IDLECLEAN)); \
1048 } while (*"\0")
1049
1050 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1051 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \
1052 OUT_RING((RADEON_WAIT_3D_IDLECLEAN | \
1053 RADEON_WAIT_HOST_IDLECLEAN)); \
1054 } while (*"\0")
1055
1056 #define RADEON_WAIT_UNTIL_IDLE() do { \
1057 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \
1058 OUT_RING((RADEON_WAIT_2D_IDLECLEAN | \
1059 RADEON_WAIT_3D_IDLECLEAN | \
1060 RADEON_WAIT_HOST_IDLECLEAN)); \
1061 } while (*"\0")
1062
1063 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1064 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \
1065 OUT_RING(RADEON_WAIT_CRTC_PFLIP); \
1066 } while (*"\0")
1067
1068 #define RADEON_FLUSH_CACHE() do { \
1069 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1070 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1071 } while (*"\0")
1072
1073 #define RADEON_PURGE_CACHE() do { \
1074 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1075 OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
1076 } while (*"\0")
1077
1078 #define RADEON_FLUSH_ZCACHE() do { \
1079 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1080 OUT_RING(RADEON_RB3D_ZC_FLUSH); \
1081 } while (*"\0")
1082
1083 #define RADEON_PURGE_ZCACHE() do { \
1084 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1085 OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \
1086 } while (*"\0")
1087
1088 /*
1089 * Misc helper macros
1090 */
1091
1092 /* Perfbox functionality only. */
1093 #define RING_SPACE_TEST_WITH_RETURN(dev_priv) \
1094 do { \
1095 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1096 u32 head = GET_RING_HEAD(dev_priv); \
1097 if (head == dev_priv->ring.tail) \
1098 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1099 } \
1100 } while (*"\0")
1101
1102 #define VB_AGE_TEST_WITH_RETURN(dev_priv) \
1103 do { \
1104 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
1105 if (sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE) { \
1106 int __ret = radeon_do_cp_idle(dev_priv); \
1107 if (__ret) \
1108 return (__ret); \
1109 sarea_priv->last_dispatch = 0; \
1110 radeon_freelist_reset(dev); \
1111 } \
1112 } while (*"\0")
1113
1114 #define RADEON_DISPATCH_AGE(age) do { \
1115 OUT_RING(CP_PACKET0(RADEON_LAST_DISPATCH_REG, 0)); \
1116 OUT_RING(age); \
1117 } while (*"\0")
1118
1119 #define RADEON_FRAME_AGE(age) do { \
1120 OUT_RING(CP_PACKET0(RADEON_LAST_FRAME_REG, 0)); \
1121 OUT_RING(age); \
1122 } while (*"\0")
1123
1124 #define RADEON_CLEAR_AGE(age) do { \
1125 OUT_RING(CP_PACKET0(RADEON_LAST_CLEAR_REG, 0)); \
1126 OUT_RING(age); \
1127 } while (*"\0")
1128
1129 /*
1130 * Ring control
1131 */
1132 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1133
1134 #define BEGIN_RING(n) do { \
1135 if (dev_priv->ring.space <= (n) * sizeof (u32)) { \
1136 COMMIT_RING(); \
1137 (void) radeon_wait_ring(dev_priv, (n) * sizeof (u32)); \
1138 } \
1139 _nr = n; dev_priv->ring.space -= (n) * sizeof (u32); \
1140 ring = dev_priv->ring.start; \
1141 write = dev_priv->ring.tail; \
1142 mask = dev_priv->ring.tail_mask; \
1143 } while (*"\0")
1144
1145 #define ADVANCE_RING() do { \
1146 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1147 DRM_ERROR( \
1148 "ADVANCE_RING(): mismatch: nr: " \
1149 "%x write: %x line: %d\n", \
1150 ((dev_priv->ring.tail + _nr) & mask), \
1151 write, __LINE__); \
1152 } else \
1153 dev_priv->ring.tail = write; \
1154 } while (*"\0")
1155
1156
1157 #if defined(lint) || defined(__lint)
1158 #define COMMIT_RING() /* For lint clean */
1159 #else
1160 #define COMMIT_RING() do { \
1161 /* Flush writes to ring */ \
1162 DRM_MEMORYBARRIER(); \
1163 GET_RING_HEAD(dev_priv); \
1164 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail); \
1165 /* read from PCI bus to ensure correct posting */ \
1166 RADEON_READ(RADEON_CP_RB_RPTR); \
1167 } while (*"\0")
1168 #endif
1169
1170 #define OUT_RING(x) do { \
1171 ring[write++] = (x); \
1172 write &= mask; \
1173 } while (*"\0")
1174
1175 #define OUT_RING_REG(reg, val) do { \
1176 OUT_RING(CP_PACKET0(reg, 0)); \
1177 OUT_RING(val); \
1178 } while (*"\0")
1179
1180 #define OUT_RING_TABLE(tab, sz) do { \
1181 int _size = (sz); \
1182 int *_tab = (int *)(uintptr_t)(tab); \
1183 \
1184 if (write + _size > mask) { \
1185 int _i = (mask+1) - write; \
1186 _size -= _i; \
1187 while (_i > 0) { \
1188 *(int *)(ring + write) = *_tab++; \
1189 write++; \
1190 _i--; \
1191 } \
1192 write = 0; \
1193 _tab += _i; \
1194 } \
1195 while (_size > 0) { \
1196 *(ring + write) = *_tab++; \
1197 write++; \
1198 _size--; \
1199 } \
1200 write &= mask; \
1201 } while (*"\0")
1202
1203 #endif /* __RADEON_DRV_H__ */