1 /* BEGIN CSTYLED */
2
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * Copyright (c) 2009, Intel Corporation.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 /*
31 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
32 * Use is subject to license terms.
33 */
34
35 #ifndef _I915_DRM_H
36 #define _I915_DRM_H
37
38 /* Please note that modifications to all structs defined here are
39 * subject to backwards-compatibility constraints.
40 */
41
42 #include "drm.h"
43
44 /* Each region is a minimum of 16k, and there are at most 255 of them.
45 */
46 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
47 * of chars for next/prev indices */
48 #define I915_LOG_MIN_TEX_REGION_SIZE 14
49
50 typedef struct _drm_i915_init {
51 enum {
52 I915_INIT_DMA = 0x01,
53 I915_CLEANUP_DMA = 0x02,
54 I915_RESUME_DMA = 0x03
55 } func;
56 unsigned int mmio_offset;
57 int sarea_priv_offset;
58 unsigned int ring_start;
59 unsigned int ring_end;
60 unsigned int ring_size;
61 unsigned int front_offset;
62 unsigned int back_offset;
63 unsigned int depth_offset;
64 unsigned int w;
65 unsigned int h;
66 unsigned int pitch;
67 unsigned int pitch_bits;
68 unsigned int back_pitch;
69 unsigned int depth_pitch;
70 unsigned int cpp;
71 unsigned int chipset;
72 } drm_i915_init_t;
73
74 typedef struct _drm_i915_sarea {
75 drm_tex_region_t texList[I915_NR_TEX_REGIONS + 1];
76 int last_upload; /* last time texture was uploaded */
77 int last_enqueue; /* last time a buffer was enqueued */
78 int last_dispatch; /* age of the most recently dispatched buffer */
79 int ctxOwner; /* last context to upload state */
80 int texAge;
81 int pf_enabled; /* is pageflipping allowed? */
82 int pf_active;
83 int pf_current_page; /* which buffer is being displayed? */
84 int perf_boxes; /* performance boxes to be displayed */
85 int width, height; /* screen size in pixels */
86 int pad0;
87
88 drm_handle_t front_handle;
89 int front_offset;
90 int front_size;
91
92 drm_handle_t back_handle;
93 int back_offset;
94 int back_size;
95
96 drm_handle_t depth_handle;
97 int depth_offset;
98 int depth_size;
99
100 drm_handle_t tex_handle;
101 int tex_offset;
102 int tex_size;
103 int log_tex_granularity;
104 int pitch;
105 int rotation; /* 0, 90, 180 or 270 */
106 int rotated_offset;
107 int rotated_size;
108 int rotated_pitch;
109 int virtualX, virtualY;
110
111 unsigned int front_tiled;
112 unsigned int back_tiled;
113 unsigned int depth_tiled;
114 unsigned int rotated_tiled;
115 unsigned int rotated2_tiled;
116
117 int pipeA_x;
118 int pipeA_y;
119 int pipeA_w;
120 int pipeA_h;
121 int pipeB_x;
122 int pipeB_y;
123 int pipeB_w;
124 int pipeB_h;
125
126 int pad1;
127 /* Triple buffering */
128 drm_handle_t third_handle;
129 int third_offset;
130 int third_size;
131 unsigned int third_tiled;
132
133 unsigned int front_bo_handle;
134 unsigned int back_bo_handle;
135 unsigned int third_bo_handle;
136 unsigned int depth_bo_handle;
137 } drm_i915_sarea_t;
138
139 /* Driver specific fence types and classes.
140 */
141
142 /* The only fence class we support */
143 #define DRM_I915_FENCE_CLASS_ACCEL 0
144 /* Fence type that guarantees read-write flush */
145 #define DRM_I915_FENCE_TYPE_RW 2
146 /* MI_FLUSH programmed just before the fence */
147 #define DRM_I915_FENCE_FLAG_FLUSHED 0x01000000
148
149 /* Flags for perf_boxes
150 */
151 #define I915_BOX_RING_EMPTY 0x1
152 #define I915_BOX_FLIP 0x2
153 #define I915_BOX_WAIT 0x4
154 #define I915_BOX_TEXTURE_LOAD 0x8
155 #define I915_BOX_LOST_CONTEXT 0x10
156
157 /* I915 specific ioctls
158 * The device specific ioctl range is 0x40 to 0x79.
159 */
160 #define DRM_I915_INIT 0x00
161 #define DRM_I915_FLUSH 0x01
162 #define DRM_I915_FLIP 0x02
163 #define DRM_I915_BATCHBUFFER 0x03
164 #define DRM_I915_IRQ_EMIT 0x04
165 #define DRM_I915_IRQ_WAIT 0x05
166 #define DRM_I915_GETPARAM 0x06
167 #define DRM_I915_SETPARAM 0x07
168 #define DRM_I915_ALLOC 0x08
169 #define DRM_I915_FREE 0x09
170 #define DRM_I915_INIT_HEAP 0x0a
171 #define DRM_I915_CMDBUFFER 0x0b
172 #define DRM_I915_DESTROY_HEAP 0x0c
173 #define DRM_I915_SET_VBLANK_PIPE 0x0d
174 #define DRM_I915_GET_VBLANK_PIPE 0x0e
175 #define DRM_I915_VBLANK_SWAP 0x0f
176 #define DRM_I915_HWS_ADDR 0x11
177 #define DRM_I915_GEM_INIT 0x13
178 #define DRM_I915_GEM_EXECBUFFER 0x14
179 #define DRM_I915_GEM_PIN 0x15
180 #define DRM_I915_GEM_UNPIN 0x16
181 #define DRM_I915_GEM_BUSY 0x17
182 #define DRM_I915_GEM_THROTTLE 0x18
183 #define DRM_I915_GEM_ENTERVT 0x19
184 #define DRM_I915_GEM_LEAVEVT 0x1a
185 #define DRM_I915_GEM_CREATE 0x1b
186 #define DRM_I915_GEM_PREAD 0x1c
187 #define DRM_I915_GEM_PWRITE 0x1d
188 #define DRM_I915_GEM_MMAP 0x1e
189 #define DRM_I915_GEM_SET_DOMAIN 0x1f
190 #define DRM_I915_GEM_SW_FINISH 0x20
191 #define DRM_I915_GEM_SET_TILING 0x21
192 #define DRM_I915_GEM_GET_TILING 0x22
193 #define DRM_I915_GEM_GET_APERTURE 0x23
194 #define DRM_I915_GEM_MMAP_GTT 0x24
195
196 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
197 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
198 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
199 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
200 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
201 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
202 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
203 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
204 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
205 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
206 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
207 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
208 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
209 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
210 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
211 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
212 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
213 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
214 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
215 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
216 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
217 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
218 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
219 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
220 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
221 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
222 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
223 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
224 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
225 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
226 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
227 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
228 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
229 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
230
231 /* Asynchronous page flipping:
232 */
233 typedef struct drm_i915_flip {
234 /*
235 * This is really talking about planes, and we could rename it
236 * except for the fact that some of the duplicated i915_drm.h files
237 * out there check for HAVE_I915_FLIP and so might pick up this
238 * version.
239 */
240 int pipes;
241 } drm_i915_flip_t;
242
243 /* Allow drivers to submit batchbuffers directly to hardware, relying
244 * on the security mechanisms provided by hardware.
245 */
246 typedef struct _drm_i915_batchbuffer {
247 int start; /* agp offset */
248 int used; /* nr bytes in use */
249 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
250 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
251 int num_cliprects; /* mulitpass with multiple cliprects? */
252 drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */
253 } drm_i915_batchbuffer_t;
254
255 typedef struct _drm_i915_batchbuffer32 {
256 int start; /* agp offset */
257 int used; /* nr bytes in use */
258 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
259 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
260 int num_cliprects; /* mulitpass with multiple cliprects? */
261 caddr32_t cliprects; /* pointer to userspace cliprects */
262 } drm_i915_batchbuffer32_t;
263
264 /* As above, but pass a pointer to userspace buffer which can be
265 * validated by the kernel prior to sending to hardware.
266 */
267 typedef struct _drm_i915_cmdbuffer {
268 char __user *buf; /* pointer to userspace command buffer */
269 int sz; /* nr bytes in buf */
270 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
271 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
272 int num_cliprects; /* mulitpass with multiple cliprects? */
273 drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */
274 } drm_i915_cmdbuffer_t;
275
276 typedef struct _drm_i915_cmdbuffer32 {
277 caddr32_t buf; /* pointer to userspace command buffer */
278 int sz; /* nr bytes in buf */
279 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
280 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
281 int num_cliprects; /* mulitpass with multiple cliprects? */
282 caddr32_t cliprects; /* pointer to userspace cliprects */
283 } drm_i915_cmdbuffer32_t;
284
285 /* Userspace can request & wait on irq's:
286 */
287 typedef struct drm_i915_irq_emit {
288 int __user *irq_seq;
289 } drm_i915_irq_emit_t;
290
291 typedef struct drm_i915_irq_emit32 {
292 caddr32_t irq_seq;
293 } drm_i915_irq_emit32_t;
294
295 typedef struct drm_i915_irq_wait {
296 int irq_seq;
297 } drm_i915_irq_wait_t;
298
299 /* Ioctl to query kernel params:
300 */
301 #define I915_PARAM_IRQ_ACTIVE 1
302 #define I915_PARAM_ALLOW_BATCHBUFFER 2
303 #define I915_PARAM_LAST_DISPATCH 3
304 #define I915_PARAM_CHIPSET_ID 4
305 #define I915_PARAM_HAS_GEM 5
306
307 typedef struct drm_i915_getparam {
308 int param;
309 int __user *value;
310 } drm_i915_getparam_t;
311
312 typedef struct drm_i915_getparam32 {
313 int param;
314 caddr32_t value;
315 } drm_i915_getparam32_t;
316
317 /* Ioctl to set kernel params:
318 */
319 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
320 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
321 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
322
323 typedef struct drm_i915_setparam {
324 int param;
325 int value;
326 } drm_i915_setparam_t;
327
328 /* A memory manager for regions of shared memory:
329 */
330 #define I915_MEM_REGION_AGP 1
331
332 typedef struct drm_i915_mem_alloc {
333 int region;
334 int alignment;
335 int size;
336 int __user *region_offset; /* offset from start of fb or agp */
337 } drm_i915_mem_alloc_t;
338
339 typedef struct drm_i915_mem_alloc32 {
340 int region;
341 int alignment;
342 int size;
343 caddr32_t region_offset; /* offset from start of fb or agp */
344 } drm_i915_mem_alloc32_t;
345
346 typedef struct drm_i915_mem_free {
347 int region;
348 int region_offset;
349 } drm_i915_mem_free_t;
350
351 typedef struct drm_i915_mem_init_heap {
352 int region;
353 int size;
354 int start;
355 } drm_i915_mem_init_heap_t;
356
357 /* Allow memory manager to be torn down and re-initialized (eg on
358 * rotate):
359 */
360 typedef struct drm_i915_mem_destroy_heap {
361 int region;
362 } drm_i915_mem_destroy_heap_t;
363
364 /* Allow X server to configure which pipes to monitor for vblank signals
365 */
366 #define DRM_I915_VBLANK_PIPE_A 1
367 #define DRM_I915_VBLANK_PIPE_B 2
368
369 typedef struct drm_i915_vblank_pipe {
370 int pipe;
371 } drm_i915_vblank_pipe_t;
372
373 /* Schedule buffer swap at given vertical blank:
374 */
375 typedef struct drm_i915_vblank_swap {
376 drm_drawable_t drawable;
377 drm_vblank_seq_type_t seqtype;
378 unsigned int sequence;
379 } drm_i915_vblank_swap_t;
380
381 #define I915_MMIO_READ 0
382 #define I915_MMIO_WRITE 1
383
384 #define I915_MMIO_MAY_READ 0x1
385 #define I915_MMIO_MAY_WRITE 0x2
386
387 #define MMIO_REGS_IA_PRIMATIVES_COUNT 0
388 #define MMIO_REGS_IA_VERTICES_COUNT 1
389 #define MMIO_REGS_VS_INVOCATION_COUNT 2
390 #define MMIO_REGS_GS_PRIMITIVES_COUNT 3
391 #define MMIO_REGS_GS_INVOCATION_COUNT 4
392 #define MMIO_REGS_CL_PRIMITIVES_COUNT 5
393 #define MMIO_REGS_CL_INVOCATION_COUNT 6
394 #define MMIO_REGS_PS_INVOCATION_COUNT 7
395 #define MMIO_REGS_PS_DEPTH_COUNT 8
396
397 typedef struct drm_i915_mmio_entry {
398 unsigned int flag;
399 unsigned int offset;
400 unsigned int size;
401 } drm_i915_mmio_entry_t;
402
403 typedef struct drm_i915_mmio {
404 unsigned int read_write:1;
405 unsigned int reg:31;
406 void __user *data;
407 } drm_i915_mmio_t;
408
409 typedef struct drm_i915_hws_addr {
410 uint64_t addr;
411 } drm_i915_hws_addr_t;
412
413
414 struct drm_i915_gem_init {
415 /**
416 * Beginning offset in the GTT to be managed by the DRM memory
417 * manager.
418 */
419 uint64_t gtt_start;
420 /**
421 * Ending offset in the GTT to be managed by the DRM memory
422 * manager.
423 */
424 uint64_t gtt_end;
425
426 };
427
428 struct drm_i915_gem_create {
429 /**
430 * Requested size for the object.
431 *
432 * The (page-aligned) allocated size for the object will be returned.
433 */
434 uint64_t size;
435 /**
436 * Returned handle for the object.
437 *
438 * Object handles are nonzero.
439 */
440 uint32_t handle;
441 uint32_t pad;
442 };
443
444 struct drm_i915_gem_pread {
445 /** Handle for the object being read. */
446 uint32_t handle;
447 uint32_t pad;
448 /** Offset into the object to read from */
449 uint64_t offset;
450 /** Length of data to read */
451 uint64_t size;
452 /**
453 * Pointer to write the data into.
454 *
455 * This is a fixed-size type for 32/64 compatibility.
456 */
457 uint64_t data_ptr;
458 };
459
460 struct drm_i915_gem_pwrite {
461 /** Handle for the object being written to. */
462 uint32_t handle;
463 uint32_t pad;
464 /** Offset into the object to write to */
465 uint64_t offset;
466 /** Length of data to write */
467 uint64_t size;
468 /**
469 * Pointer to read the data from.
470 *
471 * This is a fixed-size type for 32/64 compatibility.
472 */
473 uint64_t data_ptr;
474 };
475
476 struct drm_i915_gem_mmap {
477 /** Handle for the object being mapped. */
478 uint32_t handle;
479 uint32_t pad;
480 /** Offset in the object to map. */
481 uint64_t offset;
482 /**
483 * Length of data to map.
484 *
485 * The value will be page-aligned.
486 */
487 uint64_t size;
488 /**
489 * Returned pointer the data was mapped at.
490 *
491 * This is a fixed-size type for 32/64 compatibility.
492 */
493 uint64_t addr_ptr;
494 };
495
496 struct drm_i915_gem_mmap_gtt {
497 /** Handle for the object being mapped. */
498 uint32_t handle;
499 uint32_t pad;
500 /**
501 * Fake offset to use for subsequent mmap call
502 *
503 * This is a fixed-size type for 32/64 compatibility.
504 */
505 uint64_t offset;
506 };
507
508 struct drm_i915_gem_set_domain {
509 /** Handle for the object */
510 uint32_t handle;
511
512 /** New read domains */
513 uint32_t read_domains;
514
515 /** New write domain */
516 uint32_t write_domain;
517 };
518
519 struct drm_i915_gem_sw_finish {
520 /** Handle for the object */
521 uint32_t handle;
522 };
523
524 struct drm_i915_gem_relocation_entry {
525 /**
526 * Handle of the buffer being pointed to by this relocation entry.
527 *
528 * It's appealing to make this be an index into the mm_validate_entry
529 * list to refer to the buffer, but this allows the driver to create
530 * a relocation list for state buffers and not re-write it per
531 * exec using the buffer.
532 */
533 uint32_t target_handle;
534
535 /**
536 * Value to be added to the offset of the target buffer to make up
537 * the relocation entry.
538 */
539 uint32_t delta;
540
541 /** Offset in the buffer the relocation entry will be written into */
542 uint64_t offset;
543
544 /**
545 * Offset value of the target buffer that the relocation entry was last
546 * written as.
547 *
548 * If the buffer has the same offset as last time, we can skip syncing
549 * and writing the relocation. This value is written back out by
550 * the execbuffer ioctl when the relocation is written.
551 */
552 uint64_t presumed_offset;
553
554 /**
555 * Target memory domains read by this operation.
556 */
557 uint32_t read_domains;
558
559 /**
560 * Target memory domains written by this operation.
561 *
562 * Note that only one domain may be written by the whole
563 * execbuffer operation, so that where there are conflicts,
564 * the application will get -EINVAL back.
565 */
566 uint32_t write_domain;
567 };
568
569 /** @{
570 * Intel memory domains
571 *
572 * Most of these just align with the various caches in
573 * the system and are used to flush and invalidate as
574 * objects end up cached in different domains.
575 */
576 /** CPU cache */
577 #define I915_GEM_DOMAIN_CPU 0x00000001
578 /** Render cache, used by 2D and 3D drawing */
579 #define I915_GEM_DOMAIN_RENDER 0x00000002
580 /** Sampler cache, used by texture engine */
581 #define I915_GEM_DOMAIN_SAMPLER 0x00000004
582 /** Command queue, used to load batch buffers */
583 #define I915_GEM_DOMAIN_COMMAND 0x00000008
584 /** Instruction cache, used by shader programs */
585 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
586 /** Vertex address cache */
587 #define I915_GEM_DOMAIN_VERTEX 0x00000020
588 /** GTT domain - aperture and scanout */
589 #define I915_GEM_DOMAIN_GTT 0x00000040
590 /** @} */
591
592 struct drm_i915_gem_exec_object {
593 /**
594 * User's handle for a buffer to be bound into the GTT for this
595 * operation.
596 */
597 uint32_t handle;
598
599 /** Number of relocations to be performed on this buffer */
600 uint32_t relocation_count;
601
602 /**
603 * Pointer to array of struct drm_i915_gem_relocation_entry containing
604 * the relocations to be performed in this buffer.
605 */
606 uint64_t relocs_ptr;
607
608 /** Required alignment in graphics aperture */
609 uint64_t alignment;
610
611 /**
612 * Returned value of the updated offset of the object, for future
613 * presumed_offset writes.
614 */
615 uint64_t offset;
616
617 };
618
619 struct drm_i915_gem_execbuffer {
620 /**
621 * List of buffers to be validated with their relocations to be
622 * performend on them.
623 *
624 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
625 *
626 * These buffers must be listed in an order such that all relocations
627 * a buffer is performing refer to buffers that have already appeared
628 * in the validate list.
629 */
630 uint64_t buffers_ptr;
631 uint32_t buffer_count;
632
633 /** Offset in the batchbuffer to start execution from. */
634 uint32_t batch_start_offset;
635 /** Bytes used in batchbuffer from batch_start_offset */
636 uint32_t batch_len;
637 uint32_t DR1;
638 uint32_t DR4;
639 uint32_t num_cliprects;
640 /** This is a struct drm_clip_rect *cliprects */
641 uint64_t cliprects_ptr;
642 };
643
644 struct drm_i915_gem_pin {
645 /** Handle of the buffer to be pinned. */
646 uint32_t handle;
647 uint32_t pad;
648
649 /** alignment required within the aperture */
650 uint64_t alignment;
651
652 /** Returned GTT offset of the buffer. */
653 uint64_t offset;
654 };
655
656
657 struct drm_i915_gem_unpin {
658 /** Handle of the buffer to be unpinned. */
659 uint32_t handle;
660 uint32_t pad;
661 };
662
663 struct drm_i915_gem_busy {
664 /** Handle of the buffer to check for busy */
665 uint32_t handle;
666
667 /** Return busy status (1 if busy, 0 if idle) */
668 uint32_t busy;
669 };
670
671 #define I915_TILING_NONE 0
672 #define I915_TILING_X 1
673 #define I915_TILING_Y 2
674
675 #define I915_BIT_6_SWIZZLE_NONE 0
676 #define I915_BIT_6_SWIZZLE_9 1
677 #define I915_BIT_6_SWIZZLE_9_10 2
678 #define I915_BIT_6_SWIZZLE_9_11 3
679 #define I915_BIT_6_SWIZZLE_9_10_11 4
680 /* Not seen by userland */
681 #define I915_BIT_6_SWIZZLE_UNKNOWN 5
682
683 struct drm_i915_gem_set_tiling {
684 /** Handle of the buffer to have its tiling state updated */
685 uint32_t handle;
686
687 /**
688 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
689 * I915_TILING_Y).
690 *
691 * This value is to be set on request, and will be updated by the
692 * kernel on successful return with the actual chosen tiling layout.
693 *
694 * The tiling mode may be demoted to I915_TILING_NONE when the system
695 * has bit 6 swizzling that can't be managed correctly by GEM.
696 *
697 * Buffer contents become undefined when changing tiling_mode.
698 */
699 uint32_t tiling_mode;
700
701 /**
702 * Stride in bytes for the object when in I915_TILING_X or
703 * I915_TILING_Y.
704 */
705 uint32_t stride;
706
707 /**
708 * Returned address bit 6 swizzling required for CPU access through
709 * mmap mapping.
710 */
711 uint32_t swizzle_mode;
712 };
713
714 struct drm_i915_gem_get_tiling {
715 /** Handle of the buffer to get tiling state for. */
716 uint32_t handle;
717
718 /**
719 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
720 * I915_TILING_Y).
721 */
722 uint32_t tiling_mode;
723
724 /**
725 * Returned address bit 6 swizzling required for CPU access through
726 * mmap mapping.
727 */
728 uint32_t swizzle_mode;
729 };
730
731 struct drm_i915_gem_get_aperture {
732 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
733 uint64_t aper_size;
734
735 /**
736 * Available space in the aperture used by i915_gem_execbuffer, in
737 * bytes
738 */
739 uint64_t aper_available_size;
740 };
741
742 #endif /* _I915_DRM_H */