1 /* 2 * Copyright (c) 2012-2015 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 */ 30 31 #include "efx.h" 32 #include "efx_impl.h" 33 #if EFSYS_OPT_MON_MCDI 34 #include "mcdi_mon.h" 35 #endif 36 37 #if EFSYS_OPT_HUNTINGTON 38 39 40 __checkReturn efx_rc_t 41 hunt_board_cfg( 42 __in efx_nic_t *enp) 43 { 44 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); 45 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 46 uint8_t mac_addr[6] = { 0 }; 47 uint32_t board_type = 0; 48 ef10_link_state_t els; 49 efx_port_t *epp = &(enp->en_port); 50 uint32_t port; 51 uint32_t pf; 52 uint32_t vf; 53 uint32_t mask; 54 uint32_t flags; 55 uint32_t sysclk; 56 uint32_t base, nvec; 57 efx_rc_t rc; 58 59 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0) 60 goto fail1; 61 62 /* 63 * NOTE: The MCDI protocol numbers ports from zero. 64 * The common code MCDI interface numbers ports from one. 65 */ 66 emip->emi_port = port + 1; 67 68 if ((rc = ef10_external_port_mapping(enp, port, 69 &encp->enc_external_port)) != 0) 70 goto fail2; 71 72 /* 73 * Get PCIe function number from firmware (used for 74 * per-function privilege and dynamic config info). 75 * - PCIe PF: pf = PF number, vf = 0xffff. 76 * - PCIe VF: pf = parent PF, vf = VF number. 77 */ 78 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0) 79 goto fail3; 80 81 encp->enc_pf = pf; 82 encp->enc_vf = vf; 83 84 /* MAC address for this function */ 85 if (EFX_PCI_FUNCTION_IS_PF(encp)) { 86 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr); 87 if ((rc == 0) && (mac_addr[0] & 0x02)) { 88 /* 89 * If the static config does not include a global MAC 90 * address pool then the board may return a locally 91 * administered MAC address (this should only happen on 92 * incorrectly programmed boards). 93 */ 94 rc = EINVAL; 95 } 96 } else { 97 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr); 98 } 99 if (rc != 0) 100 goto fail4; 101 102 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr); 103 104 /* Board configuration */ 105 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL); 106 if (rc != 0) { 107 /* Unprivileged functions may not be able to read board cfg */ 108 if (rc == EACCES) 109 board_type = 0; 110 else 111 goto fail5; 112 } 113 114 encp->enc_board_type = board_type; 115 encp->enc_clk_mult = 1; /* not used for Huntington */ 116 117 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ 118 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) 119 goto fail6; 120 121 /* Obtain the default PHY advertised capabilities */ 122 if ((rc = ef10_phy_get_link(enp, &els)) != 0) 123 goto fail7; 124 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask; 125 epp->ep_adv_cap_mask = els.els_adv_cap_mask; 126 127 /* 128 * Enable firmware workarounds for hardware errata. 129 * Expected responses are: 130 * - 0 (zero): 131 * Success: workaround enabled or disabled as requested. 132 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP): 133 * Firmware does not support the MC_CMD_WORKAROUND request. 134 * (assume that the workaround is not supported). 135 * - MC_CMD_ERR_ENOENT (reported as ENOENT): 136 * Firmware does not support the requested workaround. 137 * - MC_CMD_ERR_EPERM (reported as EACCES): 138 * Unprivileged function cannot enable/disable workarounds. 139 * 140 * See efx_mcdi_request_errcode() for MCDI error translations. 141 */ 142 143 /* 144 * If the bug35388 workaround is enabled, then use an indirect access 145 * method to avoid unsafe EVQ writes. 146 */ 147 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE, 148 NULL); 149 if ((rc == 0) || (rc == EACCES)) 150 encp->enc_bug35388_workaround = B_TRUE; 151 else if ((rc == ENOTSUP) || (rc == ENOENT)) 152 encp->enc_bug35388_workaround = B_FALSE; 153 else 154 goto fail8; 155 156 /* 157 * If the bug41750 workaround is enabled, then do not test interrupts, 158 * as the test will fail (seen with Greenport controllers). 159 */ 160 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE, 161 NULL); 162 if (rc == 0) { 163 encp->enc_bug41750_workaround = B_TRUE; 164 } else if (rc == EACCES) { 165 /* Assume a controller with 40G ports needs the workaround. */ 166 if (epp->ep_default_adv_cap_mask & EFX_PHY_CAP_40000FDX) 167 encp->enc_bug41750_workaround = B_TRUE; 168 else 169 encp->enc_bug41750_workaround = B_FALSE; 170 } else if ((rc == ENOTSUP) || (rc == ENOENT)) { 171 encp->enc_bug41750_workaround = B_FALSE; 172 } else { 173 goto fail9; 174 } 175 if (EFX_PCI_FUNCTION_IS_VF(encp)) { 176 /* Interrupt testing does not work for VFs. See bug50084. */ 177 encp->enc_bug41750_workaround = B_TRUE; 178 } 179 180 /* 181 * If the bug26807 workaround is enabled, then firmware has enabled 182 * support for chained multicast filters. Firmware will reset (FLR) 183 * functions which have filters in the hardware filter table when the 184 * workaround is enabled/disabled. 185 * 186 * We must recheck if the workaround is enabled after inserting the 187 * first hardware filter, in case it has been changed since this check. 188 */ 189 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807, 190 B_TRUE, &flags); 191 if (rc == 0) { 192 encp->enc_bug26807_workaround = B_TRUE; 193 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) { 194 /* 195 * Other functions had installed filters before the 196 * workaround was enabled, and they have been reset 197 * by firmware. 198 */ 199 EFSYS_PROBE(bug26807_workaround_flr_done); 200 /* FIXME: bump MC warm boot count ? */ 201 } 202 } else if (rc == EACCES) { 203 /* 204 * Unprivileged functions cannot enable the workaround in older 205 * firmware. 206 */ 207 encp->enc_bug26807_workaround = B_FALSE; 208 } else if ((rc == ENOTSUP) || (rc == ENOENT)) { 209 encp->enc_bug26807_workaround = B_FALSE; 210 } else { 211 goto fail10; 212 } 213 214 /* Get sysclk frequency (in MHz). */ 215 if ((rc = efx_mcdi_get_clock(enp, &sysclk)) != 0) 216 goto fail11; 217 218 /* 219 * The timer quantum is 1536 sysclk cycles, documented for the 220 * EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units. 221 */ 222 encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */ 223 if (encp->enc_bug35388_workaround) { 224 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << 225 ERF_DD_EVQ_IND_TIMER_VAL_WIDTH) / 1000; 226 } else { 227 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << 228 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000; 229 } 230 231 /* Check capabilities of running datapath firmware */ 232 if ((rc = ef10_get_datapath_caps(enp)) != 0) 233 goto fail12; 234 235 /* Alignment for receive packet DMA buffers */ 236 encp->enc_rx_buf_align_start = 1; 237 encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */ 238 239 /* Alignment for WPTR updates */ 240 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN; 241 242 /* 243 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use 244 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available 245 * resources (allocated to this PCIe function), which is zero until 246 * after we have allocated VIs. 247 */ 248 encp->enc_evq_limit = 1024; 249 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET; 250 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET; 251 252 encp->enc_buftbl_limit = 0xFFFFFFFF; 253 254 encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS; 255 encp->enc_piobuf_size = HUNT_PIOBUF_SIZE; 256 encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE; 257 258 /* 259 * Get the current privilege mask. Note that this may be modified 260 * dynamically, so this value is informational only. DO NOT use 261 * the privilege mask to check for sufficient privileges, as that 262 * can result in time-of-check/time-of-use bugs. 263 */ 264 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0) 265 goto fail13; 266 encp->enc_privilege_mask = mask; 267 268 /* Get interrupt vector limits */ 269 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) { 270 if (EFX_PCI_FUNCTION_IS_PF(encp)) 271 goto fail14; 272 273 /* Ignore error (cannot query vector limits from a VF). */ 274 base = 0; 275 nvec = 1024; 276 } 277 encp->enc_intr_vec_base = base; 278 encp->enc_intr_limit = nvec; 279 280 /* 281 * Maximum number of bytes into the frame the TCP header can start for 282 * firmware assisted TSO to work. 283 */ 284 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT; 285 286 return (0); 287 288 fail14: 289 EFSYS_PROBE(fail14); 290 fail13: 291 EFSYS_PROBE(fail13); 292 fail12: 293 EFSYS_PROBE(fail12); 294 fail11: 295 EFSYS_PROBE(fail11); 296 fail10: 297 EFSYS_PROBE(fail10); 298 fail9: 299 EFSYS_PROBE(fail9); 300 fail8: 301 EFSYS_PROBE(fail8); 302 fail7: 303 EFSYS_PROBE(fail7); 304 fail6: 305 EFSYS_PROBE(fail6); 306 fail5: 307 EFSYS_PROBE(fail5); 308 fail4: 309 EFSYS_PROBE(fail4); 310 fail3: 311 EFSYS_PROBE(fail3); 312 fail2: 313 EFSYS_PROBE(fail2); 314 fail1: 315 EFSYS_PROBE1(fail1, efx_rc_t, rc); 316 317 return (rc); 318 } 319 320 321 #endif /* EFSYS_OPT_HUNTINGTON */