1 /*
   2  * Copyright (c) 2007-2015 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  */
  30 
  31 #ifndef _SYS_EFX_EF10_REGS_H
  32 #define _SYS_EFX_EF10_REGS_H
  33 
  34 #ifdef  __cplusplus
  35 extern "C" {
  36 #endif
  37 
  38 /**************************************************************************
  39  * NOTE: the line below marks the start of the autogenerated section
  40  * EF10 registers and descriptors
  41  *
  42  **************************************************************************
  43  */
  44 
  45 /*
  46  * BIU_HW_REV_ID_REG(32bit):
  47  *
  48  */
  49 
  50 #define ER_DZ_BIU_HW_REV_ID_REG_OFST 0x00000000
  51 /* hunta0,medforda0=pcie_pf_bar2 */
  52 #define ER_DZ_BIU_HW_REV_ID_REG_RESET 0xeb14face
  53 
  54 
  55 #define ERF_DZ_HW_REV_ID_LBN 0
  56 #define ERF_DZ_HW_REV_ID_WIDTH 32
  57 
  58 
  59 /*
  60  * BIU_MC_SFT_STATUS_REG(32bit):
  61  *
  62  */
  63 
  64 #define ER_DZ_BIU_MC_SFT_STATUS_REG_OFST 0x00000010
  65 /* hunta0,medforda0=pcie_pf_bar2 */
  66 #define ER_DZ_BIU_MC_SFT_STATUS_REG_STEP 4
  67 #define ER_DZ_BIU_MC_SFT_STATUS_REG_ROWS 8
  68 #define ER_DZ_BIU_MC_SFT_STATUS_REG_RESET 0x1111face
  69 
  70 
  71 #define ERF_DZ_MC_SFT_STATUS_LBN 0
  72 #define ERF_DZ_MC_SFT_STATUS_WIDTH 32
  73 
  74 
  75 /*
  76  * BIU_INT_ISR_REG(32bit):
  77  *
  78  */
  79 
  80 #define ER_DZ_BIU_INT_ISR_REG_OFST 0x00000090
  81 /* hunta0,medforda0=pcie_pf_bar2 */
  82 #define ER_DZ_BIU_INT_ISR_REG_RESET 0x0
  83 
  84 
  85 #define ERF_DZ_ISR_REG_LBN 0
  86 #define ERF_DZ_ISR_REG_WIDTH 32
  87 
  88 
  89 /*
  90  * MC_DB_LWRD_REG(32bit):
  91  *
  92  */
  93 
  94 #define ER_DZ_MC_DB_LWRD_REG_OFST 0x00000200
  95 /* hunta0,medforda0=pcie_pf_bar2 */
  96 #define ER_DZ_MC_DB_LWRD_REG_RESET 0x0
  97 
  98 
  99 #define ERF_DZ_MC_DOORBELL_L_LBN 0
 100 #define ERF_DZ_MC_DOORBELL_L_WIDTH 32
 101 
 102 
 103 /*
 104  * MC_DB_HWRD_REG(32bit):
 105  *
 106  */
 107 
 108 #define ER_DZ_MC_DB_HWRD_REG_OFST 0x00000204
 109 /* hunta0,medforda0=pcie_pf_bar2 */
 110 #define ER_DZ_MC_DB_HWRD_REG_RESET 0x0
 111 
 112 
 113 #define ERF_DZ_MC_DOORBELL_H_LBN 0
 114 #define ERF_DZ_MC_DOORBELL_H_WIDTH 32
 115 
 116 
 117 /*
 118  * EVQ_RPTR_REG(32bit):
 119  *
 120  */
 121 
 122 #define ER_DZ_EVQ_RPTR_REG_OFST 0x00000400
 123 /* hunta0,medforda0=pcie_pf_bar2 */
 124 #define ER_DZ_EVQ_RPTR_REG_STEP 8192
 125 #define ER_DZ_EVQ_RPTR_REG_ROWS 2048
 126 #define ER_DZ_EVQ_RPTR_REG_RESET 0x0
 127 
 128 
 129 #define ERF_DZ_EVQ_RPTR_VLD_LBN 15
 130 #define ERF_DZ_EVQ_RPTR_VLD_WIDTH 1
 131 #define ERF_DZ_EVQ_RPTR_LBN 0
 132 #define ERF_DZ_EVQ_RPTR_WIDTH 15
 133 
 134 
 135 /*
 136  * EVQ_TMR_REG(32bit):
 137  *
 138  */
 139 
 140 #define ER_DZ_EVQ_TMR_REG_OFST 0x00000420
 141 /* hunta0,medforda0=pcie_pf_bar2 */
 142 #define ER_DZ_EVQ_TMR_REG_STEP 8192
 143 #define ER_DZ_EVQ_TMR_REG_ROWS 2048
 144 #define ER_DZ_EVQ_TMR_REG_RESET 0x0
 145 
 146 
 147 #define ERF_DZ_TC_TIMER_MODE_LBN 14
 148 #define ERF_DZ_TC_TIMER_MODE_WIDTH 2
 149 #define ERF_DZ_TC_TIMER_VAL_LBN 0
 150 #define ERF_DZ_TC_TIMER_VAL_WIDTH 14
 151 
 152 
 153 /*
 154  * RX_DESC_UPD_REG(32bit):
 155  *
 156  */
 157 
 158 #define ER_DZ_RX_DESC_UPD_REG_OFST 0x00000830
 159 /* hunta0,medforda0=pcie_pf_bar2 */
 160 #define ER_DZ_RX_DESC_UPD_REG_STEP 8192
 161 #define ER_DZ_RX_DESC_UPD_REG_ROWS 2048
 162 #define ER_DZ_RX_DESC_UPD_REG_RESET 0x0
 163 
 164 
 165 #define ERF_DZ_RX_DESC_WPTR_LBN 0
 166 #define ERF_DZ_RX_DESC_WPTR_WIDTH 12
 167 
 168 
 169 /*
 170  * TX_DESC_UPD_REG(96bit):
 171  *
 172  */
 173 
 174 #define ER_DZ_TX_DESC_UPD_REG_OFST 0x00000a10
 175 /* hunta0,medforda0=pcie_pf_bar2 */
 176 #define ER_DZ_TX_DESC_UPD_REG_STEP 8192
 177 #define ER_DZ_TX_DESC_UPD_REG_ROWS 2048
 178 #define ER_DZ_TX_DESC_UPD_REG_RESET 0x0
 179 
 180 
 181 #define ERF_DZ_RSVD_LBN 76
 182 #define ERF_DZ_RSVD_WIDTH 20
 183 #define ERF_DZ_TX_DESC_WPTR_LBN 64
 184 #define ERF_DZ_TX_DESC_WPTR_WIDTH 12
 185 #define ERF_DZ_TX_DESC_HWORD_LBN 32
 186 #define ERF_DZ_TX_DESC_HWORD_WIDTH 32
 187 #define ERF_DZ_TX_DESC_LWORD_LBN 0
 188 #define ERF_DZ_TX_DESC_LWORD_WIDTH 32
 189 
 190 
 191 /* ES_DRIVER_EV */
 192 #define ESF_DZ_DRV_CODE_LBN 60
 193 #define ESF_DZ_DRV_CODE_WIDTH 4
 194 #define ESF_DZ_DRV_SUB_CODE_LBN 56
 195 #define ESF_DZ_DRV_SUB_CODE_WIDTH 4
 196 #define ESE_DZ_DRV_TIMER_EV 3
 197 #define ESE_DZ_DRV_START_UP_EV 2
 198 #define ESE_DZ_DRV_WAKE_UP_EV 1
 199 #define ESF_DZ_DRV_SUB_DATA_DW0_LBN 0
 200 #define ESF_DZ_DRV_SUB_DATA_DW0_WIDTH 32
 201 #define ESF_DZ_DRV_SUB_DATA_DW1_LBN 32
 202 #define ESF_DZ_DRV_SUB_DATA_DW1_WIDTH 24
 203 #define ESF_DZ_DRV_SUB_DATA_LBN 0
 204 #define ESF_DZ_DRV_SUB_DATA_WIDTH 56
 205 #define ESF_DZ_DRV_EVQ_ID_LBN 0
 206 #define ESF_DZ_DRV_EVQ_ID_WIDTH 14
 207 #define ESF_DZ_DRV_TMR_ID_LBN 0
 208 #define ESF_DZ_DRV_TMR_ID_WIDTH 14
 209 
 210 
 211 /* ES_EVENT_ENTRY */
 212 #define ESF_DZ_EV_CODE_LBN 60
 213 #define ESF_DZ_EV_CODE_WIDTH 4
 214 #define ESE_DZ_EV_CODE_MCDI_EV 12
 215 #define ESE_DZ_EV_CODE_DRIVER_EV 5
 216 #define ESE_DZ_EV_CODE_TX_EV 2
 217 #define ESE_DZ_EV_CODE_RX_EV 0
 218 #define ESE_DZ_OTHER other
 219 #define ESF_DZ_EV_DATA_DW0_LBN 0
 220 #define ESF_DZ_EV_DATA_DW0_WIDTH 32
 221 #define ESF_DZ_EV_DATA_DW1_LBN 32
 222 #define ESF_DZ_EV_DATA_DW1_WIDTH 28
 223 #define ESF_DZ_EV_DATA_LBN 0
 224 #define ESF_DZ_EV_DATA_WIDTH 60
 225 
 226 
 227 /* ES_MC_EVENT */
 228 #define ESF_DZ_MC_CODE_LBN 60
 229 #define ESF_DZ_MC_CODE_WIDTH 4
 230 #define ESF_DZ_MC_OVERRIDE_HOLDOFF_LBN 59
 231 #define ESF_DZ_MC_OVERRIDE_HOLDOFF_WIDTH 1
 232 #define ESF_DZ_MC_DROP_EVENT_LBN 58
 233 #define ESF_DZ_MC_DROP_EVENT_WIDTH 1
 234 #define ESF_DZ_MC_SOFT_DW0_LBN 0
 235 #define ESF_DZ_MC_SOFT_DW0_WIDTH 32
 236 #define ESF_DZ_MC_SOFT_DW1_LBN 32
 237 #define ESF_DZ_MC_SOFT_DW1_WIDTH 26
 238 #define ESF_DZ_MC_SOFT_LBN 0
 239 #define ESF_DZ_MC_SOFT_WIDTH 58
 240 
 241 
 242 /* ES_RX_EVENT */
 243 #define ESF_DZ_RX_CODE_LBN 60
 244 #define ESF_DZ_RX_CODE_WIDTH 4
 245 #define ESF_DZ_RX_OVERRIDE_HOLDOFF_LBN 59
 246 #define ESF_DZ_RX_OVERRIDE_HOLDOFF_WIDTH 1
 247 #define ESF_DZ_RX_DROP_EVENT_LBN 58
 248 #define ESF_DZ_RX_DROP_EVENT_WIDTH 1
 249 #define ESF_DD_RX_EV_RSVD2_LBN 54
 250 #define ESF_DD_RX_EV_RSVD2_WIDTH 4
 251 #define ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_LBN 57
 252 #define ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_WIDTH 1
 253 #define ESF_EZ_RX_IP_INNER_CHKSUM_ERR_LBN 56
 254 #define ESF_EZ_RX_IP_INNER_CHKSUM_ERR_WIDTH 1
 255 #define ESF_EZ_RX_EV_RSVD2_LBN 54
 256 #define ESF_EZ_RX_EV_RSVD2_WIDTH 2
 257 #define ESF_DZ_RX_EV_SOFT2_LBN 52
 258 #define ESF_DZ_RX_EV_SOFT2_WIDTH 2
 259 #define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48
 260 #define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4
 261 #define ESF_DZ_RX_L4_CLASS_LBN 45
 262 #define ESF_DZ_RX_L4_CLASS_WIDTH 3
 263 #define ESE_DZ_L4_CLASS_RSVD7 7
 264 #define ESE_DZ_L4_CLASS_RSVD6 6
 265 #define ESE_DZ_L4_CLASS_RSVD5 5
 266 #define ESE_DZ_L4_CLASS_RSVD4 4
 267 #define ESE_DZ_L4_CLASS_RSVD3 3
 268 #define ESE_DZ_L4_CLASS_UDP 2
 269 #define ESE_DZ_L4_CLASS_TCP 1
 270 #define ESE_DZ_L4_CLASS_UNKNOWN 0
 271 #define ESF_DZ_RX_L3_CLASS_LBN 42
 272 #define ESF_DZ_RX_L3_CLASS_WIDTH 3
 273 #define ESE_DZ_L3_CLASS_RSVD7 7
 274 #define ESE_DZ_L3_CLASS_IP6_FRAG 6
 275 #define ESE_DZ_L3_CLASS_ARP 5
 276 #define ESE_DZ_L3_CLASS_IP4_FRAG 4
 277 #define ESE_DZ_L3_CLASS_FCOE 3
 278 #define ESE_DZ_L3_CLASS_IP6 2
 279 #define ESE_DZ_L3_CLASS_IP4 1
 280 #define ESE_DZ_L3_CLASS_UNKNOWN 0
 281 #define ESF_DZ_RX_ETH_TAG_CLASS_LBN 39
 282 #define ESF_DZ_RX_ETH_TAG_CLASS_WIDTH 3
 283 #define ESE_DZ_ETH_TAG_CLASS_RSVD7 7
 284 #define ESE_DZ_ETH_TAG_CLASS_RSVD6 6
 285 #define ESE_DZ_ETH_TAG_CLASS_RSVD5 5
 286 #define ESE_DZ_ETH_TAG_CLASS_RSVD4 4
 287 #define ESE_DZ_ETH_TAG_CLASS_RSVD3 3
 288 #define ESE_DZ_ETH_TAG_CLASS_VLAN2 2
 289 #define ESE_DZ_ETH_TAG_CLASS_VLAN1 1
 290 #define ESE_DZ_ETH_TAG_CLASS_NONE 0
 291 #define ESF_DZ_RX_ETH_BASE_CLASS_LBN 36
 292 #define ESF_DZ_RX_ETH_BASE_CLASS_WIDTH 3
 293 #define ESE_DZ_ETH_BASE_CLASS_LLC_SNAP 2
 294 #define ESE_DZ_ETH_BASE_CLASS_LLC 1
 295 #define ESE_DZ_ETH_BASE_CLASS_ETH2 0
 296 #define ESF_DZ_RX_MAC_CLASS_LBN 35
 297 #define ESF_DZ_RX_MAC_CLASS_WIDTH 1
 298 #define ESE_DZ_MAC_CLASS_MCAST 1
 299 #define ESE_DZ_MAC_CLASS_UCAST 0
 300 #define ESF_DD_RX_EV_SOFT1_LBN 32
 301 #define ESF_DD_RX_EV_SOFT1_WIDTH 3
 302 #define ESF_EZ_RX_EV_SOFT1_LBN 34
 303 #define ESF_EZ_RX_EV_SOFT1_WIDTH 1
 304 #define ESF_EZ_RX_ENCAP_HDR_LBN 32
 305 #define ESF_EZ_RX_ENCAP_HDR_WIDTH 2
 306 #define ESE_EZ_ENCAP_HDR_GRE 2
 307 #define ESE_EZ_ENCAP_HDR_VXLAN 1
 308 #define ESE_EZ_ENCAP_HDR_NONE 0
 309 #define ESF_DD_RX_EV_RSVD1_LBN 30
 310 #define ESF_DD_RX_EV_RSVD1_WIDTH 2
 311 #define ESF_EZ_RX_EV_RSVD1_LBN 31
 312 #define ESF_EZ_RX_EV_RSVD1_WIDTH 1
 313 #define ESF_EZ_RX_ABORT_LBN 30
 314 #define ESF_EZ_RX_ABORT_WIDTH 1
 315 #define ESF_DZ_RX_ECC_ERR_LBN 29
 316 #define ESF_DZ_RX_ECC_ERR_WIDTH 1
 317 #define ESF_DZ_RX_CRC1_ERR_LBN 28
 318 #define ESF_DZ_RX_CRC1_ERR_WIDTH 1
 319 #define ESF_DZ_RX_CRC0_ERR_LBN 27
 320 #define ESF_DZ_RX_CRC0_ERR_WIDTH 1
 321 #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN 26
 322 #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_WIDTH 1
 323 #define ESF_DZ_RX_IPCKSUM_ERR_LBN 25
 324 #define ESF_DZ_RX_IPCKSUM_ERR_WIDTH 1
 325 #define ESF_DZ_RX_ECRC_ERR_LBN 24
 326 #define ESF_DZ_RX_ECRC_ERR_WIDTH 1
 327 #define ESF_DZ_RX_QLABEL_LBN 16
 328 #define ESF_DZ_RX_QLABEL_WIDTH 5
 329 #define ESF_DZ_RX_PARSE_INCOMPLETE_LBN 15
 330 #define ESF_DZ_RX_PARSE_INCOMPLETE_WIDTH 1
 331 #define ESF_DZ_RX_CONT_LBN 14
 332 #define ESF_DZ_RX_CONT_WIDTH 1
 333 #define ESF_DZ_RX_BYTES_LBN 0
 334 #define ESF_DZ_RX_BYTES_WIDTH 14
 335 
 336 
 337 /* ES_RX_KER_DESC */
 338 #define ESF_DZ_RX_KER_RESERVED_LBN 62
 339 #define ESF_DZ_RX_KER_RESERVED_WIDTH 2
 340 #define ESF_DZ_RX_KER_BYTE_CNT_LBN 48
 341 #define ESF_DZ_RX_KER_BYTE_CNT_WIDTH 14
 342 #define ESF_DZ_RX_KER_BUF_ADDR_DW0_LBN 0
 343 #define ESF_DZ_RX_KER_BUF_ADDR_DW0_WIDTH 32
 344 #define ESF_DZ_RX_KER_BUF_ADDR_DW1_LBN 32
 345 #define ESF_DZ_RX_KER_BUF_ADDR_DW1_WIDTH 16
 346 #define ESF_DZ_RX_KER_BUF_ADDR_LBN 0
 347 #define ESF_DZ_RX_KER_BUF_ADDR_WIDTH 48
 348 
 349 
 350 /* ES_TX_CSUM_TSTAMP_DESC */
 351 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63
 352 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
 353 #define ESF_DZ_TX_OPTION_TYPE_LBN 60
 354 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3
 355 #define ESE_DZ_TX_OPTION_DESC_TSO 7
 356 #define ESE_DZ_TX_OPTION_DESC_VLAN 6
 357 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
 358 #define ESF_DZ_TX_OPTION_TS_AT_TXDP_LBN 8
 359 #define ESF_DZ_TX_OPTION_TS_AT_TXDP_WIDTH 1
 360 #define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_LBN 7
 361 #define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_WIDTH 1
 362 #define ESF_DZ_TX_OPTION_INNER_IP_CSUM_LBN 6
 363 #define ESF_DZ_TX_OPTION_INNER_IP_CSUM_WIDTH 1
 364 #define ESF_DZ_TX_TIMESTAMP_LBN 5
 365 #define ESF_DZ_TX_TIMESTAMP_WIDTH 1
 366 #define ESF_DZ_TX_OPTION_CRC_MODE_LBN 2
 367 #define ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3
 368 #define ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5
 369 #define ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4
 370 #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3
 371 #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2
 372 #define ESE_DZ_TX_OPTION_CRC_FCOE 1
 373 #define ESE_DZ_TX_OPTION_CRC_OFF 0
 374 #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1
 375 #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1
 376 #define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0
 377 #define ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1
 378 
 379 
 380 /* ES_TX_EVENT */
 381 #define ESF_DZ_TX_CODE_LBN 60
 382 #define ESF_DZ_TX_CODE_WIDTH 4
 383 #define ESF_DZ_TX_OVERRIDE_HOLDOFF_LBN 59
 384 #define ESF_DZ_TX_OVERRIDE_HOLDOFF_WIDTH 1
 385 #define ESF_DZ_TX_DROP_EVENT_LBN 58
 386 #define ESF_DZ_TX_DROP_EVENT_WIDTH 1
 387 #define ESF_DD_TX_EV_RSVD_LBN 48
 388 #define ESF_DD_TX_EV_RSVD_WIDTH 10
 389 #define ESF_EZ_TCP_UDP_INNER_CHKSUM_ERR_LBN 57
 390 #define ESF_EZ_TCP_UDP_INNER_CHKSUM_ERR_WIDTH 1
 391 #define ESF_EZ_IP_INNER_CHKSUM_ERR_LBN 56
 392 #define ESF_EZ_IP_INNER_CHKSUM_ERR_WIDTH 1
 393 #define ESF_EZ_TX_EV_RSVD_LBN 48
 394 #define ESF_EZ_TX_EV_RSVD_WIDTH 8
 395 #define ESF_DZ_TX_SOFT2_LBN 32
 396 #define ESF_DZ_TX_SOFT2_WIDTH 16
 397 #define ESF_DD_TX_SOFT1_LBN 24
 398 #define ESF_DD_TX_SOFT1_WIDTH 8
 399 #define ESF_EZ_TX_CAN_MERGE_LBN 31
 400 #define ESF_EZ_TX_CAN_MERGE_WIDTH 1
 401 #define ESF_EZ_TX_SOFT1_LBN 24
 402 #define ESF_EZ_TX_SOFT1_WIDTH 7
 403 #define ESF_DZ_TX_QLABEL_LBN 16
 404 #define ESF_DZ_TX_QLABEL_WIDTH 5
 405 #define ESF_DZ_TX_DESCR_INDX_LBN 0
 406 #define ESF_DZ_TX_DESCR_INDX_WIDTH 16
 407 
 408 
 409 /* ES_TX_KER_DESC */
 410 #define ESF_DZ_TX_KER_TYPE_LBN 63
 411 #define ESF_DZ_TX_KER_TYPE_WIDTH 1
 412 #define ESF_DZ_TX_KER_CONT_LBN 62
 413 #define ESF_DZ_TX_KER_CONT_WIDTH 1
 414 #define ESF_DZ_TX_KER_BYTE_CNT_LBN 48
 415 #define ESF_DZ_TX_KER_BYTE_CNT_WIDTH 14
 416 #define ESF_DZ_TX_KER_BUF_ADDR_DW0_LBN 0
 417 #define ESF_DZ_TX_KER_BUF_ADDR_DW0_WIDTH 32
 418 #define ESF_DZ_TX_KER_BUF_ADDR_DW1_LBN 32
 419 #define ESF_DZ_TX_KER_BUF_ADDR_DW1_WIDTH 16
 420 #define ESF_DZ_TX_KER_BUF_ADDR_LBN 0
 421 #define ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48
 422 
 423 
 424 /* ES_TX_PIO_DESC */
 425 #define ESF_DZ_TX_PIO_TYPE_LBN 63
 426 #define ESF_DZ_TX_PIO_TYPE_WIDTH 1
 427 #define ESF_DZ_TX_PIO_OPT_LBN 60
 428 #define ESF_DZ_TX_PIO_OPT_WIDTH 3
 429 #define ESF_DZ_TX_PIO_CONT_LBN 59
 430 #define ESF_DZ_TX_PIO_CONT_WIDTH 1
 431 #define ESF_DZ_TX_PIO_BYTE_CNT_LBN 32
 432 #define ESF_DZ_TX_PIO_BYTE_CNT_WIDTH 12
 433 #define ESF_DZ_TX_PIO_BUF_ADDR_LBN 0
 434 #define ESF_DZ_TX_PIO_BUF_ADDR_WIDTH 12
 435 
 436 
 437 /* ES_TX_TSO_DESC */
 438 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63
 439 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
 440 #define ESF_DZ_TX_OPTION_TYPE_LBN 60
 441 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3
 442 #define ESE_DZ_TX_OPTION_DESC_TSO 7
 443 #define ESE_DZ_TX_OPTION_DESC_VLAN 6
 444 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
 445 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56
 446 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4
 447 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1
 448 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0
 449 #define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48
 450 #define ESF_DZ_TX_TSO_TCP_FLAGS_WIDTH 8
 451 #define ESF_DZ_TX_TSO_IP_ID_LBN 32
 452 #define ESF_DZ_TX_TSO_IP_ID_WIDTH 16
 453 #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0
 454 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32
 455 
 456 
 457 /* TX_TSO_FATSO2A_DESC */
 458 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63
 459 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
 460 #define ESF_DZ_TX_OPTION_TYPE_LBN 60
 461 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3
 462 #define ESE_DZ_TX_OPTION_DESC_TSO 7
 463 #define ESE_DZ_TX_OPTION_DESC_VLAN 6
 464 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
 465 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56
 466 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4
 467 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3
 468 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2
 469 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1
 470 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0
 471 #define ESF_DZ_TX_TSO_IP_ID_LBN 32
 472 #define ESF_DZ_TX_TSO_IP_ID_WIDTH 16
 473 #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0
 474 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32
 475 
 476 
 477 /* TX_TSO_FATSO2B_DESC */
 478 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63
 479 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
 480 #define ESF_DZ_TX_OPTION_TYPE_LBN 60
 481 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3
 482 #define ESE_DZ_TX_OPTION_DESC_TSO 7
 483 #define ESE_DZ_TX_OPTION_DESC_VLAN 6
 484 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
 485 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56
 486 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4
 487 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3
 488 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2
 489 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1
 490 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0
 491 #define ESF_DZ_TX_TSO_OUTER_IP_ID_LBN 16
 492 #define ESF_DZ_TX_TSO_OUTER_IP_ID_WIDTH 16
 493 #define ESF_DZ_TX_TSO_TCP_MSS_LBN 32
 494 #define ESF_DZ_TX_TSO_TCP_MSS_WIDTH 16
 495 #define ESF_DZ_TX_TSO_INNER_PE_CSUM_LBN 0
 496 #define ESF_DZ_TX_TSO_INNER_PE_CSUM_WIDTH 16
 497 
 498 
 499 /* ES_TX_VLAN_DESC */
 500 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63
 501 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
 502 #define ESF_DZ_TX_OPTION_TYPE_LBN 60
 503 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3
 504 #define ESE_DZ_TX_OPTION_DESC_TSO 7
 505 #define ESE_DZ_TX_OPTION_DESC_VLAN 6
 506 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
 507 #define ESF_DZ_TX_VLAN_OP_LBN 32
 508 #define ESF_DZ_TX_VLAN_OP_WIDTH 2
 509 #define ESF_DZ_TX_VLAN_TAG2_LBN 16
 510 #define ESF_DZ_TX_VLAN_TAG2_WIDTH 16
 511 #define ESF_DZ_TX_VLAN_TAG1_LBN 0
 512 #define ESF_DZ_TX_VLAN_TAG1_WIDTH 16
 513 
 514 
 515 /*************************************************************************
 516  * NOTE: the comment line above marks the end of the autogenerated section
 517  */
 518 
 519 /*
 520  * The workaround for bug 35388 requires multiplexing writes through
 521  * the ERF_DZ_TX_DESC_WPTR address.
 522  * TX_DESC_UPD: 0ppppppppppp               (bit 11 lost)
 523  * EVQ_RPTR:    1000hhhhhhhh, 1001llllllll (split into high and low bits)
 524  * EVQ_TMR:     11mmvvvvvvvv               (bits 8:13 of value lost)
 525  */
 526 #define ER_DD_EVQ_INDIRECT_OFST (ER_DZ_TX_DESC_UPD_REG_OFST + 2 * 4)
 527 #define ER_DD_EVQ_INDIRECT_STEP ER_DZ_TX_DESC_UPD_REG_STEP
 528 #define ERF_DD_EVQ_IND_RPTR_FLAGS_LBN 8
 529 #define ERF_DD_EVQ_IND_RPTR_FLAGS_WIDTH 4
 530 #define EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH 8
 531 #define EFE_DD_EVQ_IND_RPTR_FLAGS_LOW 9
 532 #define ERF_DD_EVQ_IND_RPTR_LBN 0
 533 #define ERF_DD_EVQ_IND_RPTR_WIDTH 8
 534 #define ERF_DD_EVQ_IND_TIMER_FLAGS_LBN 10
 535 #define ERF_DD_EVQ_IND_TIMER_FLAGS_WIDTH 2
 536 #define EFE_DD_EVQ_IND_TIMER_FLAGS 3
 537 #define ERF_DD_EVQ_IND_TIMER_MODE_LBN 8
 538 #define ERF_DD_EVQ_IND_TIMER_MODE_WIDTH 2
 539 #define ERF_DD_EVQ_IND_TIMER_VAL_LBN 0
 540 #define ERF_DD_EVQ_IND_TIMER_VAL_WIDTH 8
 541 
 542 
 543 #ifdef  __cplusplus
 544 }
 545 #endif
 546 
 547 #endif /* _SYS_EFX_EF10_REGS_H */